Prepare 2009.08-rc2

Update CHANGELOG

Signed-off-by: Wolfgang Denk <wd@denx.de>

MAINTAINERS

@@ -32,6 +32,8 @@ Reinhard Arlt <reinhard.arlt@esd-electronics.com>
 	mecp5200	MPC5200
 	pf5200		MPC5200
 
+	vme8349		MPC8349
+
 	CPCI750		PPC750FX/GX
 
 Yuli Barcohen <yuli@arabellasw.com>
@@ -135,6 +137,8 @@ Jon Diekema <jon.diekema@smiths-aerospace.com>
 
 Dirk Eibach <eibach@gdsys.de>
 
+	compactcenter	PPC460EX
+	devconcenter	PPC460EX
 	dlvision        PPC405EP
 	gdppc440etx	PPC440EP/GR
 	neo		PPC405EP

MAKEALL

@@ -184,6 +184,7 @@ LIST_4xx="		\
 	canyonlands	\
 	canyonlands_nand \
 	CMS700		\
+	compactcenter	\
 	CPCI2DP		\
 	CPCI405		\
 	CPCI4052	\
@@ -194,6 +195,7 @@ LIST_4xx="		\
 	csb272		\
 	csb472		\
 	DASA_SIM	\
+	devconcenter	\
 	dlvision	\
 	DP405		\
 	DU405		\
@@ -364,6 +366,7 @@ LIST_83xx="		\
 	sbc8349		\
 	SIMPC8313_LP	\
 	TQM834x		\
+	vme8349		\
 "
 
 
@@ -774,6 +777,7 @@ LIST_coldfire="			\
 	EB+MCF-EV123		\
 	EB+MCF-EV123_internal	\
 	idmr			\
+	M5208EVBE		\
 	M52277EVB		\
 	M5235EVB		\
 	M5249EVB		\

Makefile

@@ -24,7 +24,7 @@
 VERSION = 2009
 PATCHLEVEL = 08
 SUBLEVEL =
-EXTRAVERSION = -rc1
+EXTRAVERSION = -rc2
 ifneq "$(SUBLEVEL)" ""
 U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
 else
@@ -221,6 +221,7 @@ LIBS += drivers/net/phy/libphy.a
 LIBS += drivers/net/sk98lin/libsk98lin.a
 LIBS += drivers/pci/libpci.a
 LIBS += drivers/pcmcia/libpcmcia.a
+LIBS += drivers/power/libpower.a
 LIBS += drivers/spi/libspi.a
 ifeq ($(CPU),mpc83xx)
 LIBS += drivers/qe/qe.a
@@ -1282,6 +1283,14 @@ CATcenter_33_config:	unconfig
 CMS700_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx cms700 esd
 
+# Compact-Center & DevCon-Center use different U-Boot images
+compactcenter_config \
+devconcenter_config:	unconfig
+	@mkdir -p $(obj)include
+	@echo "#define CONFIG_$$(echo $(subst ,,$(@:_config=)) | \
+		tr '[:lower:]' '[:upper:]')" >$(obj)include/config.h
+	@$(MKCONFIG) -n $@ -a compactcenter ppc ppc4xx compactcenter gdsys
+
 CPCI2DP_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci2dp esd
 
@@ -1984,6 +1993,9 @@ ZPC1900_config: unconfig
 ## Coldfire
 #########################################################################
 
+M5208EVBE_config :		unconfig
+	@$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5208evbe freescale
+
 M52277EVB_config \
 M52277EVB_spansion_config \
 M52277EVB_stmicro_config :	unconfig
@@ -2088,18 +2100,15 @@ M5373EVB_config :	unconfig
 	@$(MKCONFIG) -a M5373EVB m68k mcf532x m5373evb freescale
 
 M54451EVB_config \
-M54451EVB_spansion_config \
 M54451EVB_stmicro_config :	unconfig
 	@case "$@" in \
-	M54451EVB_config)		FLASH=SPANSION;; \
-	M54451EVB_spansion_config)	FLASH=SPANSION;; \
+	M54451EVB_config)		FLASH=NOR;; \
 	M54451EVB_stmicro_config)	FLASH=STMICRO;; \
 	esac; \
-	if [ "$${FLASH}" = "SPANSION" ] ; then \
-		echo "#define CONFIG_SYS_SPANSION_BOOT"	>> $(obj)include/config.h ; \
+	if [ "$${FLASH}" = "NOR" ] ; then \
 		echo "TEXT_BASE = 0x00000000" > $(obj)board/freescale/m54451evb/config.tmp ; \
 		cp $(obj)board/freescale/m54451evb/u-boot.spa $(obj)board/freescale/m54451evb/u-boot.lds ; \
-		$(XECHO) "... with SPANSION boot..." ; \
+		$(XECHO) "... with NOR boot..." ; \
 	fi; \
 	if [ "$${FLASH}" = "STMICRO" ] ; then \
 		echo "#define CONFIG_CF_SBF"	>> $(obj)include/config.h ; \
@@ -2387,6 +2396,8 @@ SIMPC8313_SP_config: unconfig
 TQM834x_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc83xx tqm834x tqc
 
+vme8349_config:		unconfig
+	@$(MKCONFIG) $(@:_config=) ppc mpc83xx vme8349 esd
 
 #########################################################################
 ## MPC85xx Systems

board/amcc/canyonlands/canyonlands.c

@@ -40,6 +40,24 @@ DECLARE_GLOBAL_DATA_PTR;
 #define BOARD_GLACIER		3
 #define BOARD_ARCHES		4
 
+/*
+ * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
+ * board specific values.
+ */
+#if defined(CONFIG_ARCHES)
+u32 ddr_wrdtr(u32 default_val) {
+	return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_0_DEG | 0x823);
+}
+#else
+u32 ddr_wrdtr(u32 default_val) {
+	return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823);
+}
+
+u32 ddr_clktr(u32 default_val) {
+	return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
+}
+#endif
+
 #if defined(CONFIG_ARCHES)
 /*
  * FPGA read/write helper macros
@@ -76,13 +94,23 @@ static inline void board_cpld_write(int offset, int data)
 	out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset);
 	out_8((void *)(CONFIG_SYS_CPLD_DATA), data);
 }
+#else
+static int pvr_460ex(void)
+{
+	u32 pvr = get_pvr();
+
+	if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA) ||
+	    (pvr == PVR_460EX_RB))
+		return 1;
+
+	return 0;
+}
 #endif	/* defined(CONFIG_ARCHES) */
 
 int board_early_init_f(void)
 {
 #if !defined(CONFIG_ARCHES)
 	u32 sdr0_cust0;
-	u32 pvr = get_pvr();
 #endif
 
 	/*
@@ -157,7 +185,7 @@ int board_early_init_f(void)
 	mtdcr(AHB_TOP, 0x8000004B);
 	mtdcr(AHB_BOT, 0x8000004B);
 
-	if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA)) {
+	if (pvr_460ex()) {
 		/*
 		 * Configure USB-STP pins as alternate and not GPIO
 		 * It seems to be neccessary to configure the STP pins as GPIO
@@ -216,17 +244,16 @@ int get_cpu_num(void)
 int checkboard(void)
 {
 	char *s = getenv("serial#");
-	u32 pvr = get_pvr();
 
-	if ((pvr == PVR_460GT_RA) || (pvr == PVR_460GT_SE_RA)) {
-		printf("Board: Glacier - AMCC PPC460GT Evaluation Board");
-		gd->board_type = BOARD_GLACIER;
-	} else {
+	if (pvr_460ex()) {
 		printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board");
 		if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 3)) & CONFIG_SYS_BCSR3_PCIE)
 			gd->board_type = BOARD_CANYONLANDS_PCIE;
 		else
 			gd->board_type = BOARD_CANYONLANDS_SATA;
+	} else {
+		printf("Board: Glacier - AMCC PPC460GT Evaluation Board");
+		gd->board_type = BOARD_GLACIER;
 	}
 
 	switch (gd->board_type) {
@@ -286,18 +313,6 @@ int checkboard(void)
 }
 #endif	/* !defined(CONFIG_ARCHES) */
 
-/*
- * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
- * board specific values.
- */
-u32 ddr_wrdtr(u32 default_val) {
-	return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823);
-}
-
-u32 ddr_clktr(u32 default_val) {
-	return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
-}
-
 #if defined(CONFIG_NAND_U_BOOT)
 /*
  * NAND booting U-Boot version uses a fixed initialization, since the whole
@@ -492,7 +507,6 @@ int misc_init_r(void)
 {
 	u32 sdr0_srst1 = 0;
 	u32 eth_cfg;
-	u32 pvr = get_pvr();
 	u8 val;
 
 	/*
@@ -507,7 +521,7 @@ int misc_init_r(void)
 	/* Set the for 2 RGMII mode */
 	/* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
 	eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
-	if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA))
+	if (pvr_460ex())
 		eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
 	else
 		eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
@@ -579,23 +593,8 @@ extern void __ft_board_setup(void *blob, bd_t *bd);
 
 void ft_board_setup(void *blob, bd_t *bd)
 {
-	u32 val[4];
-	int rc;
-
 	__ft_board_setup(blob, bd);
 
-	/* Fixup NOR mapping */
-	val[0] = CONFIG_SYS_NOR_CS;		/* chip select number */
-	val[1] = 0;				/* always 0 */
-	val[2] = CONFIG_SYS_FLASH_BASE_PHYS_L;		/* we fixed up this address */
-	val[3] = gd->bd->bi_flashsize;
-	rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
-				  val, sizeof(val), 1);
-	if (rc) {
-		printf("Unable to update property NOR mapping, err=%s\n",
-		       fdt_strerror(rc));
-	}
-
 	if (gd->board_type == BOARD_CANYONLANDS_SATA) {
 		/*
 		 * When SATA is selected we need to disable the first PCIe

board/amcc/kilauea/chip_config.c

@@ -25,6 +25,8 @@
 #include <common.h>
 #include <asm/ppc4xx_config.h>
 
+/* NAND booting versions differ in bytes: 6, 8, 9, 11, 12 */
+
 struct ppc4xx_config ppc4xx_config_val[] = {
 	{
 		"333-nor","NOR  CPU: 333 PLB: 166 OPB:  83 EBC:  83",
@@ -49,10 +51,17 @@ struct ppc4xx_config ppc4xx_config_val[] = {
 	},
 	{
 		"533-nor", "NOR  CPU: 533 PLB: 177 OPB:  88 EBC:  88",
-	  {
-		  0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0a, 0x00,
-		  0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
-	  }
+		{
+			0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0a, 0x00,
+			0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"533-nand", "NOR  CPU: 533 PLB: 177 OPB:  88 EBC:  88",
+		{
+			0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0f, 0x00,
+			0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+		}
 	},
 	{
 		"600-nor", "NOR  CPU: 600 PLB: 200 OPB: 100 EBC: 100",
@@ -61,6 +70,13 @@ struct ppc4xx_config ppc4xx_config_val[] = {
 			0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
 		}
 	},
+	{
+		"600-nand", "NOR  CPU: 600 PLB: 200 OPB: 100 EBC: 100",
+		{
+			0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0f, 0x00,
+			0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
 	{
 		"666-nor", "NOR  CPU: 666 PLB: 222 OPB: 111 EBC: 111",
 		{

board/cray/L1/init.S

@@ -1,5 +1,9 @@
 /*------------------------------------------------------------------------------+ */
 /* */
+/*       This source code is dual-licensed.  You may use it under the terms */
+/*       of the GNU General Public License version 2, or under the license  */
+/*       below.                                                             */
+/*                                                                          */
 /*       This source code has been made available to you by IBM on an AS-IS */
 /*       basis.  Anyone receiving this source is licensed under IBM */
 /*       copyrights to use it in any way he or she deems fit, including */

board/csb272/init.S

@@ -1,4 +1,6 @@
 /******************************************************************************
+ *   This source code is dual-licensed.  You may use it under the terms of the
+ *   GNU General Public License version 2, or under the license below.
  *
  *	 This source code has been made available to you by IBM on an AS-IS
  *	 basis.	 Anyone receiving this source is licensed under IBM

board/csb472/init.S

@@ -1,4 +1,6 @@
 /******************************************************************************
+ *   This source code is dual-licensed.  You may use it under the terms of the
+ *   GNU General Public License version 2, or under the license below.
  *
  *	 This source code has been made available to you by IBM on an AS-IS
  *	 basis.	 Anyone receiving this source is licensed under IBM

board/digsy_mtc/cmd_mtc.c

@@ -44,6 +44,19 @@ static const char *led_names[] = {
 	""
 };
 
+static int msp430_xfer(const void *dout, void *din)
+{
+	int err;
+
+	err = spi_xfer(NULL, MTC_TRANSFER_SIZE, dout, din,
+		       SPI_XFER_BEGIN | SPI_XFER_END);
+
+	/* The MSP chip needs time to ready itself for the next command */
+	udelay(1000);
+
+	return err;
+}
+
 static void mtc_calculate_checksum(tx_msp_cmd *packet)
 {
 	int i;
@@ -59,7 +72,7 @@ static int do_mtc_led(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	tx_msp_cmd pcmd;
 	rx_msp_cmd prx;
-	int err = 0;
+	int err;
 	int i;
 
 	if (argc < 2) {
@@ -102,8 +115,7 @@ static int do_mtc_led(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		pcmd.cmd_val2 = 0;
 
 	mtc_calculate_checksum(&pcmd);
-	err = spi_xfer(NULL, MTC_TRANSFER_SIZE, &pcmd, &prx,
-		       SPI_XFER_BEGIN | SPI_XFER_END);
+	err = msp430_xfer(&pcmd, &prx);
 
 	return err;
 }
@@ -112,7 +124,7 @@ static int do_mtc_key(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	tx_msp_cmd pcmd;
 	rx_msp_cmd prx;
-	int err = 0;
+	int err;
 
 	memset(&pcmd, 0, sizeof(pcmd));
 	memset(&prx, 0, sizeof(prx));
@@ -120,8 +132,7 @@ static int do_mtc_key(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	pcmd.cmd = CMD_GET_VIM;
 
 	mtc_calculate_checksum(&pcmd);
-	err = spi_xfer(NULL, MTC_TRANSFER_SIZE, &pcmd, &prx,
-		       SPI_XFER_BEGIN | SPI_XFER_END);
+	err = msp430_xfer(&pcmd, &prx);
 
 	if (!err) {
 		/* function returns '0' if key is pressed */
@@ -135,7 +146,7 @@ static int do_mtc_digout(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	tx_msp_cmd pcmd;
 	rx_msp_cmd prx;
-	int err = 0;
+	int err;
 	uchar channel_mask = 0;
 
 	if (argc < 3) {
@@ -155,8 +166,7 @@ static int do_mtc_digout(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	pcmd.user_out = channel_mask;
 
 	mtc_calculate_checksum(&pcmd);
-	err = spi_xfer(NULL, MTC_TRANSFER_SIZE, &pcmd, &prx,
-		       SPI_XFER_BEGIN | SPI_XFER_END);
+	err = msp430_xfer(&pcmd, &prx);
 
 	return err;
 }
@@ -165,7 +175,7 @@ static int do_mtc_digin(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	tx_msp_cmd pcmd;
 	rx_msp_cmd prx;
-	int err = 0;
+	int err;
 	uchar channel_num = 0;
 
 	if (argc < 2) {
@@ -185,8 +195,7 @@ static int do_mtc_digin(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	pcmd.cmd = CMD_GET_VIM;
 
 	mtc_calculate_checksum(&pcmd);
-	err = spi_xfer(NULL, MTC_TRANSFER_SIZE, &pcmd, &prx,
-		       SPI_XFER_BEGIN | SPI_XFER_END);
+	err = msp430_xfer(&pcmd, &prx);
 
 	if (!err) {
 		/* function returns '0' when digin is on */
@@ -213,8 +222,8 @@ static int do_mtc_appreg(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	pcmd.cmd_val2 = 0;	/* =0 means read appreg */
 
 	mtc_calculate_checksum(&pcmd);
-	err = spi_xfer(NULL, MTC_TRANSFER_SIZE, &pcmd, &prx,
-		       SPI_XFER_BEGIN | SPI_XFER_END);
+	err = msp430_xfer(&pcmd, &prx);
+
 	if (!err) {
 		sprintf(buf, "%d", prx.ack2);
 		setenv("appreg", buf);
@@ -227,7 +236,7 @@ static int do_mtc_version(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	tx_msp_cmd pcmd;
 	rx_msp_cmd prx;
-	int err = 0;
+	int err;
 
 	memset(&pcmd, 0, sizeof(pcmd));
 	memset(&prx, 0, sizeof(prx));
@@ -235,8 +244,7 @@ static int do_mtc_version(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	pcmd.cmd = CMD_FW_VERSION;
 
 	mtc_calculate_checksum(&pcmd);
-	err = spi_xfer(NULL, MTC_TRANSFER_SIZE, &pcmd, &prx,
-		       SPI_XFER_BEGIN | SPI_XFER_END);
+	err = msp430_xfer(&pcmd, &prx);
 
 	if (!err) {
 		printf("FW V%d.%d.%d / HW %d\n",
@@ -246,6 +254,33 @@ static int do_mtc_version(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return err;
 }
 
+static int do_mtc_state(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	tx_msp_cmd pcmd;
+	rx_msp_cmd prx;
+	int err;
+
+	memset(&pcmd, 0, sizeof(pcmd));
+	memset(&prx, 0, sizeof(prx));
+
+	pcmd.cmd = CMD_WD_WDSTATE;
+	pcmd.cmd_val2 = 1;
+
+	mtc_calculate_checksum(&pcmd);
+	err = msp430_xfer(&pcmd, &prx);
+
+	if (!err) {
+		printf("State     %02Xh\n", prx.state);
+		printf("Input     %02Xh\n", prx.input);
+		printf("UserWD    %02Xh\n", prx.ack2);
+		printf("Sys WD    %02Xh\n", prx.ack3);
+		printf("WD Timout %02Xh\n", prx.ack0);
+		printf("eSysState %02Xh\n", prx.ack1);
+	}
+
+	return err;
+}
+
 static int do_mtc_help(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
 
 cmd_tbl_t cmd_mtc_sub[] = {
@@ -256,17 +291,19 @@ cmd_tbl_t cmd_mtc_sub[] = {
 	" - state: off red green orange\n"
 	" - blink: blink interval in 100ms steps (1 - 10; 0 = static)\n"),
 	U_BOOT_CMD_MKENT(key, 0, 1, do_mtc_key,
-	"returns state of user key\n", ""),
+	"returns state of user key", ""),
 	U_BOOT_CMD_MKENT(version, 0, 1, do_mtc_version,
-	"returns firmware version of supervisor uC\n", ""),
+	"returns firmware version of supervisor uC", ""),
 	U_BOOT_CMD_MKENT(appreg, 0, 1, do_mtc_appreg,
-	"reads appreg value and stores in environment variable 'appreg'\n", ""),
+	"reads appreg value and stores in environment variable 'appreg'", ""),
 	U_BOOT_CMD_MKENT(digin, 1, 1, do_mtc_digin,
 	"returns state of digital input",
 	"<channel_num> - get state of digital input (1 or 2)\n"),
 	U_BOOT_CMD_MKENT(digout, 2, 1, do_mtc_digout,
 	"sets digital outputs",
 	"<on|off> <on|off>- set state of digital output 1 and 2\n"),
+	U_BOOT_CMD_MKENT(state, 0, 1, do_mtc_state,
+	"displays state", ""),
 	U_BOOT_CMD_MKENT(help, 4, 1, do_mtc_help, "get help",
 	"[command] - get help for command\n"),
 };
@@ -333,7 +370,7 @@ int cmd_mtc(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 }
 
 U_BOOT_CMD(mtc, 5, 1, cmd_mtc,
-	"mtc     - special commands for digsyMTC\n",
+	"special commands for digsyMTC",
 	"[subcommand] [args...]\n"
 	"Subcommands list:\n"
 	"led [ledname] [state] [blink] - set state of leds\n"
@@ -346,5 +383,6 @@ U_BOOT_CMD(mtc, 5, 1, cmd_mtc,
 	" 'appreg'\n"
 	"digin [channel] - returns state of digital input (1 or 2)\n"
 	"digout <on|off> <on|off> - sets state of two digital outputs\n"
+	"state - displays state\n"
 	"help [subcommand] - get help for subcommand\n"
 );

board/digsy_mtc/cmd_mtc.h

@@ -27,6 +27,7 @@
 #define CMD_MTC_H
 
 #define	CMD_WD_PARA		0x02
+#define	CMD_WD_WDSTATE		0x04
 #define	CMD_FW_VERSION		0x10
 #define	CMD_GET_VIM		0x30
 #define	CMD_SET_LED		0x40

board/eric/init.S

@@ -1,5 +1,9 @@
 /*------------------------------------------------------------------------------+ */
 /* */
+/*       This source code is dual-licensed.  You may use it under the terms */
+/*       of the GNU General Public License version 2, or under the license  */
+/*       below.                                                             */
+/*                                                                          */
 /*       This source code has been made available to you by IBM on an AS-IS */
 /*       basis.  Anyone receiving this source is licensed under IBM */
 /*       copyrights to use it in any way he or she deems fit, including */

board/esd/pci405/writeibm.S

@@ -1,5 +1,9 @@
 /*------------------------------------------------------------------------------+ */
 /* */
+/*       This source code is dual-licensed.  You may use it under the terms */
+/*       of the GNU General Public License version 2, or under the license  */
+/*       below.                                                             */
+/*                                                                          */
 /*       This source code has been made available to you by IBM on an AS-IS */
 /*       basis.  Anyone receiving this source is licensed under IBM */
 /*       copyrights to use it in any way he or she deems fit, including */

board/esd/vme8349/Makefile

@@ -2,6 +2,8 @@
 # (C) Copyright 2006
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
+# Copyright (c) 2009 esd gmbh hannover germany.
+#
 # See file CREDITS for list of people who contributed to this
 # project.
 #
@@ -12,7 +14,7 @@
 #
 # This program is distributed in the hope that it will be useful,
 # but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 # GNU General Public License for more details.
 #
 # You should have received a copy of the GNU General Public License
@@ -23,27 +25,25 @@
 
 include $(TOPDIR)/config.mk
 
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)board/$(VENDOR)/common)
-endif
+LIB	= $(obj)lib$(BOARD).a
 
-LIB	= $(obj)lib$(VENDOR).a
-
-COBJS-$(CONFIG_OMAP3_BEAGLE) += power.o
-COBJS-$(CONFIG_OMAP3_OVERO) += power.o
-COBJS-$(CONFIG_OMAP3_PANDORA) += power.o
-COBJS-$(CONFIG_OMAP3_ZOOM1) += power.o
-COBJS-$(CONFIG_OMAP3_ZOOM2) += power.o
+COBJS-y += $(BOARD).o caddy.o
+COBJS-$(CONFIG_PCI) += pci.o
 
 COBJS	:= $(COBJS-y)
-SRCS	:= $(COBJS:.o=.c)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(LIB)
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
 $(LIB):	$(obj).depend $(OBJS)
 	$(AR) $(ARFLAGS) $@ $(OBJS)
 
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
 #########################################################################
 
 # defines $(obj).depend target

board/esd/vme8349/caddy.c

@@ -0,0 +1,194 @@
+/*
+ * caddy.c -- esd VME8349 support for "missing" access modes in TSI148.
+ * Copyright (c) 2009 esd gmbh.
+ *
+ * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <asm/mpc8349_pci.h>
+#include <pci.h>
+#include <asm/mmu.h>
+#include <asm/io.h>
+
+#include "caddy.h"
+
+static struct caddy_interface *caddy_interface;
+
+void generate_answer(struct caddy_cmd *cmd, uint32_t status, uint32_t *result)
+{
+	struct caddy_answer *answer;
+	uint32_t ptr;
+
+	answer = &caddy_interface->answer[caddy_interface->answer_in];
+	memset((void *)answer, 0, sizeof(struct caddy_answer));
+	answer->answer = cmd->cmd;
+	answer->issue = cmd->issue;
+	answer->status = status;
+	memcpy(answer->par, result, 5 * sizeof(result[0]));
+	ptr = caddy_interface->answer_in + 1;
+	ptr = ptr & (ANSWER_SIZE - 1);
+	if (ptr != caddy_interface->answer_out)
+		caddy_interface->answer_in = ptr;
+}
+
+int do_caddy(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	unsigned long base_addr;
+	uint32_t ptr;
+	struct caddy_cmd *caddy_cmd;
+	uint32_t result[5];
+	uint16_t data16;
+	uint8_t data8;
+	uint32_t status;
+	pci_dev_t dev;
+	void *pci_ptr;
+
+	if (argc < 2) {
+		puts("Missing parameter\n");
+		return 1;
+	}
+
+	base_addr = simple_strtoul(argv[1], NULL, 16);
+	caddy_interface = (struct caddy_interface *) base_addr;
+
+	memset((void *)caddy_interface, 0, sizeof(struct caddy_interface));
+	memcpy((void *)&caddy_interface->magic[0], &CADDY_MAGIC, 16);
+
+	while (ctrlc() == 0) {
+		if (caddy_interface->cmd_in != caddy_interface->cmd_out) {
+			memset(result, 0, 5 * sizeof(result[0]));
+			status = 0;
+			caddy_cmd = &caddy_interface->cmd[caddy_interface->cmd_out];
+			pci_ptr = (void *)CONFIG_SYS_PCI1_IO_PHYS +
+				(caddy_cmd->addr & 0x001fffff);
+
+			switch (caddy_cmd->cmd) {
+			case CADDY_CMD_IO_READ_8:
+				result[0] = in_8(pci_ptr);
+				break;
+
+			case CADDY_CMD_IO_READ_16:
+				result[0] = in_be16(pci_ptr);
+				break;
+
+			case CADDY_CMD_IO_READ_32:
+				result[0] = in_be32(pci_ptr);
+				break;
+
+			case CADDY_CMD_IO_WRITE_8:
+				data8 = caddy_cmd->par[0] & 0x000000ff;
+				out_8(pci_ptr, data8);
+				break;
+
+			case CADDY_CMD_IO_WRITE_16:
+				data16 = caddy_cmd->par[0] & 0x0000ffff;
+				out_be16(pci_ptr, data16);
+				break;
+
+			case CADDY_CMD_IO_WRITE_32:
+				out_be32(pci_ptr, caddy_cmd->par[0]);
+				break;
+
+			case CADDY_CMD_CONFIG_READ_8:
+				dev = PCI_BDF(caddy_cmd->par[0],
+					      caddy_cmd->par[1],
+					      caddy_cmd->par[2]);
+				status = pci_read_config_byte(dev,
+							      caddy_cmd->addr,
+							      &data8);
+				result[0] = data8;
+				break;
+
+			case CADDY_CMD_CONFIG_READ_16:
+				dev = PCI_BDF(caddy_cmd->par[0],
+					      caddy_cmd->par[1],
+					      caddy_cmd->par[2]);
+				status = pci_read_config_word(dev,
+							      caddy_cmd->addr,
+							      &data16);
+				result[0] = data16;
+				break;
+
+			case CADDY_CMD_CONFIG_READ_32:
+				dev = PCI_BDF(caddy_cmd->par[0],
+					      caddy_cmd->par[1],
+					      caddy_cmd->par[2]);
+				status = pci_read_config_dword(dev,
+							       caddy_cmd->addr,
+							       &result[0]);
+				break;
+
+			case CADDY_CMD_CONFIG_WRITE_8:
+				dev = PCI_BDF(caddy_cmd->par[0],
+					      caddy_cmd->par[1],
+					      caddy_cmd->par[2]);
+				data8 = caddy_cmd->par[3] & 0x000000ff;
+				status = pci_write_config_byte(dev,
+							       caddy_cmd->addr,
+							       data8);
+				break;
+
+			case CADDY_CMD_CONFIG_WRITE_16:
+				dev = PCI_BDF(caddy_cmd->par[0],
+					      caddy_cmd->par[1],
+					      caddy_cmd->par[2]);
+				data16 = caddy_cmd->par[3] & 0x0000ffff;
+				status = pci_write_config_word(dev,
+							       caddy_cmd->addr,
+							       data16);
+				break;
+
+			case CADDY_CMD_CONFIG_WRITE_32:
+				dev = PCI_BDF(caddy_cmd->par[0],
+					      caddy_cmd->par[1],
+					      caddy_cmd->par[2]);
+				status = pci_write_config_dword(dev,
+								caddy_cmd->addr,
+								caddy_cmd->par[3]);
+				break;
+
+			default:
+				status = 0xffffffff;
+				break;
+			}
+
+			generate_answer(caddy_cmd, status, &result[0]);
+
+			ptr = caddy_interface->cmd_out + 1;
+			ptr = ptr & (CMD_SIZE - 1);
+			caddy_interface->cmd_out = ptr;
+		}
+
+		caddy_interface->heartbeat++;
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	caddy,	2,	0,	do_caddy,
+	"Start Caddy server.",
+	"Start Caddy server with Data structure a given addr\n"
+	);

board/esd/vme8349/caddy.h

@@ -0,0 +1,77 @@
+/*
+ * caddy.c -- esd VME8349 support for "missing" access modes in TSI148.
+ * Copyright (c) 2009 esd gmbh.
+ *
+ * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __CADDY_H__
+#define __CADDY_H__
+
+#define CMD_SIZE	1024
+#define ANSWER_SIZE	1024
+#define CADDY_MAGIC	"esd vme8349 V1.0"
+
+enum caddy_cmds {
+	CADDY_CMD_IO_READ_8,
+	CADDY_CMD_IO_READ_16,
+	CADDY_CMD_IO_READ_32,
+	CADDY_CMD_IO_WRITE_8,
+	CADDY_CMD_IO_WRITE_16,
+	CADDY_CMD_IO_WRITE_32,
+	CADDY_CMD_CONFIG_READ_8,
+	CADDY_CMD_CONFIG_READ_16,
+	CADDY_CMD_CONFIG_READ_32,
+	CADDY_CMD_CONFIG_WRITE_8,
+	CADDY_CMD_CONFIG_WRITE_16,
+	CADDY_CMD_CONFIG_WRITE_32,
+};
+
+struct caddy_cmd {
+	uint32_t cmd;
+	uint32_t issue;
+	uint32_t addr;
+	uint32_t par[5];
+};
+
+struct caddy_answer {
+	uint32_t answer;
+	uint32_t issue;
+	uint32_t status;
+	uint32_t par[5];
+};
+
+struct caddy_interface {
+	uint8_t  magic[16];
+	uint32_t cmd_in;
+	uint32_t cmd_out;
+	uint32_t heartbeat;
+	uint32_t reserved1;
+	struct caddy_cmd cmd[CMD_SIZE];
+	uint32_t answer_in;
+	uint32_t answer_out;
+	uint32_t reserved2;
+	uint32_t reserved3;
+	struct caddy_answer answer[CMD_SIZE];
+};
+
+#endif /* of __CADDY_H__ */

board/esd/vme8349/config.mk

@@ -1,6 +1,6 @@
 #
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
 # project.
@@ -20,17 +20,9 @@
 # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 # MA 02111-1307 USA
 #
-PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
-		     -msoft-float
 
-# Make ARMv5 to allow more compilers to work, even though its v7a.
-PLATFORM_CPPFLAGS += -march=armv5
-# =========================================================================
 #
-# Supply options according to compiler version
+# VME8349E
 #
-# =========================================================================
-PLATFORM_CPPFLAGS +=$(call cc-option)
-PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,)
-PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,\
-		    $(call cc-option,-malignment-traps,))
+
+TEXT_BASE  =   0xFFF00000

board/esd/vme8349/pci.c

@@ -0,0 +1,119 @@
+/*
+ * pci.c -- esd VME8349 PCI board support.
+ * Copyright (c) 2006 Wind River Systems, Inc.
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
+ *
+ * Based on MPC8349 PCI support but w/o PIB related code.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <asm/mmu.h>
+#include <asm/io.h>
+#include <common.h>
+#include <mpc83xx.h>
+#include <pci.h>
+#include <i2c.h>
+#include <asm/fsl_i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct pci_region pci1_regions[] = {
+	{
+		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
+		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
+		size: CONFIG_SYS_PCI1_MEM_SIZE,
+		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+	},
+	{
+		bus_start: CONFIG_SYS_PCI1_IO_BASE,
+		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
+		size: CONFIG_SYS_PCI1_IO_SIZE,
+		flags: PCI_REGION_IO
+	},
+	{
+		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
+		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
+		size: CONFIG_SYS_PCI1_MMIO_SIZE,
+		flags: PCI_REGION_MEM
+	},
+};
+
+/*
+ * pci_init_board()
+ *
+ * NOTICE: PCI2 is not supported. There is only one
+ * physical PCI slot on the board.
+ *
+ */
+void
+pci_init_board(void)
+{
+	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+	struct pci_region *reg[] = { pci1_regions };
+	u8 reg8;
+	int monarch = 0;
+
+	i2c_set_bus_num(1);
+	/* Read the PCI_M66EN jumper setting */
+	if ((i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, &reg8, 1) == 0) ||
+	    (i2c_read(0x38                     , 0, 0, &reg8, 1) == 0)) {
+		if (reg8 & 0x40) {
+			clk->occr = 0xff000000;	/* 66 MHz PCI */
+			printf("PCI:   66MHz\n");
+		} else {
+			clk->occr = 0xffff0003;	/* 33 MHz PCI */
+			printf("PCI:   33MHz\n");
+		}
+		if (((reg8 & 0x01) == 0) || ((reg8 & 0x02) == 0))
+			monarch = 1;
+	} else {
+		clk->occr = 0xffff0003;	/* 33 MHz PCI */
+		printf("PCI:   33MHz (I2C read failed)\n");
+	}
+	udelay(2000);
+
+	/*
+	 * Assert/deassert PCI reset
+	 */
+	setbits_be32(&immr->gpio[0].dat, 0x00800000);
+	setbits_be32(&immr->gpio[0].dir, 0x00800000);
+	setbits_be32(&immr->gpio[1].dir, 0x08800000);
+	udelay(200);
+	setbits_be32(&immr->gpio[1].dat, 0x08000000);
+	udelay(200);
+	setbits_be32(&immr->gpio[1].dat, 0x08800000);
+	udelay(600000);
+	clrbits_be32(&immr->gpio[1].dat, 0x00100000);
+
+	/* Configure PCI Local Access Windows */
+	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
+
+	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
+
+	udelay(2000);
+
+	if (monarch == 0)
+		mpc83xx_pci_init(1, reg, 0);
+}

board/esd/vme8349/vme8349.c

@@ -0,0 +1,140 @@
+/*
+ * vme8349.c -- esd VME8349 board support
+ *
+ * Copyright (c) 2008-2009 esd gmbh.
+ *
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+ * Based on board/mpc8349emds/mpc8349emds.c (and previous 834x releases.)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <asm/mpc8349_pci.h>
+#if defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#endif
+#include <asm/io.h>
+#include <asm/mmu.h>
+
+void ddr_enable_ecc(unsigned int dram_size);
+
+int fixed_sdram(void)
+{
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 msize = 0;
+	u32 ddr_size;
+	u32 ddr_size_log2;
+
+	msize = CONFIG_SYS_DDR_SIZE;
+	for (ddr_size = msize << 20, ddr_size_log2 = 0;
+	     (ddr_size > 1);
+	     ddr_size = ddr_size>>1, ddr_size_log2++) {
+		if (ddr_size & 1)
+			return -1;
+	}
+
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+	im->sysconf.ddrlaw[0].ar  = LAWAR_EN | ((ddr_size_log2 - 1) &
+						LAWAR_SIZE);
+
+#if (CONFIG_SYS_DDR_SIZE == 512)
+	im->ddr.csbnds[0].csbnds = 0x0000001f;
+#else
+#warning Currently any DDR size other than 512MiB is not supported
+#endif
+	im->ddr.cs_config[0]     = CONFIG_SYS_DDR_CONFIG | 0x00330000;
+
+	/* currently we use only one CS, so disable the other banks */
+	im->ddr.csbnds[1].csbnds = 0x00000000;
+	im->ddr.csbnds[2].csbnds = 0x00000000;
+	im->ddr.csbnds[3].csbnds = 0x00000000;
+	im->ddr.cs_config[1] = 0;
+	im->ddr.cs_config[2] = 0;
+	im->ddr.cs_config[3] = 0;
+
+	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+
+	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
+	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
+	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
+
+	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+	sync();
+	udelay(200);
+
+	/* enable DDR controller */
+	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+
+	return msize;
+}
+
+phys_size_t initdram(int board_type)
+{
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 msize = 0;
+
+	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
+		return -1;
+
+	/* DDR SDRAM - Main SODIMM */
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
+
+	msize = fixed_sdram();
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+	/*
+	 * Initialize and enable DDR ECC.
+	 */
+	ddr_enable_ecc(msize * 1024 * 1024);
+#endif
+
+	/* Now check memory size (after ECC is initialized) */
+	msize = get_ram_size(0, msize);
+
+	/* return total bus SDRAM size(bytes)  -- DDR */
+	return msize * 1024 * 1024;
+}
+
+int checkboard(void)
+{
+	puts("Board: esd VME8349\n");
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+#endif
+}
+#endif

board/exbitgen/init.S

@@ -1,4 +1,6 @@
 /*----------------------------------------------------------------------+
+ *       This source code is dual-licensed.  You may use it under the terms of
+ *       the GNU General Public License version 2, or under the license below.
  *
  *       This source code has been made available to you by IBM on an AS-IS
  *       basis.  Anyone receiving this source is licensed under IBM

board/freescale/m5208evbe/Makefile

@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/freescale/m5208evbe/config.mk

@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0

board/freescale/m5208evbe/m5208evbe.c

@@ -0,0 +1,94 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/immap.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	puts("Board: ");
+	puts("Freescale M5208EVBe\n");
+	return 0;
+};
+
+phys_size_t initdram(int board_type)
+{
+	volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
+	u32 dramsize, i;
+
+	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+
+	for (i = 0x13; i < 0x20; i++) {
+		if (dramsize == (1 << i))
+			break;
+	}
+	i--;
+
+	sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i);
+#ifdef CONFIG_SYS_SDRAM_BASE1
+	sdram->cs1 = (CONFIG_SYS_SDRAM_BASE | i);
+#endif
+	sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
+	sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
+
+	udelay(500);
+
+	/* Issue PALL */
+	sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+	asm("nop");
+
+	/* Perform two refresh cycles */
+	sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+	sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+	asm("nop");
+
+	/* Issue LEMR */
+	sdram->mode = CONFIG_SYS_SDRAM_MODE;
+	asm("nop");
+	sdram->mode = CONFIG_SYS_SDRAM_EMOD;
+	asm("nop");
+
+	sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+	asm("nop");
+
+	sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00;
+	asm("nop");
+
+	udelay(100);
+
+	return dramsize;
+};
+
+int testdram(void)
+{
+	/* TODO: XXX XXX XXX */
+	printf("DRAM test not implemented!\n");
+
+	return (0);
+}

board/freescale/m5208evbe/u-boot.lds

@@ -0,0 +1,142 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp        : { *(.interp)		}
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt           : { *(.plt)		}
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mcf52x2/start.o		(.text)
+    cpu/mcf52x2/libmcf52x2.a	(.text)
+    lib_m68k/libm68k.a		(.text)
+    common/dlmalloc.o		(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/env_embedded.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+
+  .reloc   :
+  {
+    __got_start = .;
+    *(.got)
+    __got_end = .;
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   _sbss = .;
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+   _ebss = .;
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}

board/freescale/m54451evb/u-boot.spa

@@ -56,10 +56,13 @@ SECTIONS
     /* the sector layout of our flash chips!	XXX FIXME XXX	*/
 
     cpu/mcf5445x/start.o		(.text)
-    lib_m68k/traps.o		(.text)
-    lib_m68k/interrupts.o	(.text)
+    cpu/mcf5445x/libmcf5445x.a	(.text)
+    lib_m68k/libm68k.a		(.text)
+    common/cmd_flash.o		(.text)
     common/dlmalloc.o		(.text)
-    lib_generic/zlib.o		(.text)
+    common/main.o		(.text)
+    common/image.o		(.text)
+    lib_generic/libgeneric.a	(.text)
 
     . = DEFINED(env_offset) ? env_offset : .;
     common/env_embedded.o	(.text)

board/freescale/mpc8349itx/Makefile

@@ -1,5 +1,5 @@
 #
-# Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
+# Copyright (C) Freescale Semiconductor, Inc. 2006.
 #
 # See file CREDITS for list of people who contributed to this
 # project.

board/freescale/mpc8349itx/config.mk

@@ -1,5 +1,5 @@
 #
-# Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
+# Copyright (C) Freescale Semiconductor, Inc. 2006.
 #
 # See file CREDITS for list of people who contributed to this
 # project.

board/freescale/mpc8349itx/mpc8349itx.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
+ * Copyright (C) Freescale Semiconductor, Inc. 2006.
  *
  * See file CREDITS for list of people who contributed to this
  * project.

board/freescale/mpc8569mds/bcsr.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
+ * Copyright (C) 2009 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.

board/freescale/mpc8569mds/bcsr.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
+ * Copyright (C) 2009 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.

board/freescale/mpc8569mds/config.mk

@@ -1,5 +1,5 @@
 #
-# Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
+# Copyright (C) 2009 Freescale Semiconductor, Inc.
 #
 # See file CREDITS for list of people who contributed to this
 # project.

board/gdsys/compactcenter/Makefile

@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2008
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS-y	:= $(BOARD).o
+COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
+SOBJS	:= init.o
+
+COBJS   := $(COBJS-y)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/gdsys/compactcenter/chip_config.c

@@ -0,0 +1,87 @@
+/*
+ * (C) Copyright 2008-2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/ppc4xx_config.h>
+
+struct ppc4xx_config ppc4xx_config_val[] = {
+	{
+		"600-nor", "NOR  CPU: 600 PLB: 200 OPB: 100 EBC: 100",
+		{
+			0x86, 0x80, 0xce, 0x1f, 0x79, 0x80, 0x00, 0xa0,
+			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"600-nand", "NAND CPU: 600 PLB: 200 OPB: 100 EBC: 100",
+		{
+			0x86, 0x80, 0xce, 0x1f, 0x79, 0x90, 0x01, 0xa0,
+			0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"800-nor", "NOR  CPU: 800 PLB: 200 OPB: 100 EBC: 100",
+		{
+			0x86, 0x80, 0xba, 0x14, 0x99, 0x80, 0x00, 0xa0,
+			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"800-nand", "NAND CPU: 800 PLB: 200 OPB: 100 EBC: 100",
+		{
+			0x86, 0x80, 0xba, 0x14, 0x99, 0x90, 0x01, 0xa0,
+			0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"1000-nor", "NOR  CPU:1000 PLB: 200 OPB: 100 EBC: 100",
+		{
+			0x86, 0x82, 0x96, 0x19, 0xb9, 0x80, 0x00, 0xa0,
+			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"1000-nand", "NAND CPU:1000 PLB: 200 OPB: 100 EBC: 100",
+		{
+			0x86, 0x82, 0x96, 0x19, 0xb9, 0x90, 0x01, 0xa0,
+			0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"1066-nor", "NOR  CPU:1066 PLB: 266 OPB:  88 EBC:  88",
+		{
+			0x86, 0x80, 0xb3, 0x01, 0x9d, 0x80, 0x00, 0xa0,
+			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"1066-nand", "NAND CPU:1066 PLB: 266 OPB:  88 EBC:  88",
+		{
+			0x86, 0x80, 0xb3, 0x01, 0x9d, 0x90, 0x01, 0xa0,
+			0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+};
+
+int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);

board/gdsys/compactcenter/compactcenter.c

@@ -0,0 +1,289 @@
+/*
+ * (C) Copyright 2009
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * Based on board/amcc/canyonlands/canyonlands.c
+ * (C) Copyright 2008
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc440.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <i2c.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/mmu.h>
+#include <asm/4xx_pcie.h>
+#include <asm/gpio.h>
+
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CONFIG_SYS_BCSR3_PCIE		0x10
+
+int board_early_init_f(void)
+{
+	/*
+	 * Setup the interrupt controller polarities, triggers, etc.
+	 */
+	mtdcr(uic0sr, 0xffffffff);	/* clear all */
+	mtdcr(uic0er, 0x00000000);	/* disable all */
+	mtdcr(uic0cr, 0x00000005);	/* ATI & UIC1 crit are critical */
+	mtdcr(uic0pr, 0xffffffff);	/* per ref-board manual */
+	mtdcr(uic0tr, 0x00000000);	/* per ref-board manual */
+	mtdcr(uic0vr, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(uic0sr, 0xffffffff);	/* clear all */
+
+	mtdcr(uic1sr, 0xffffffff);	/* clear all */
+	mtdcr(uic1er, 0x00000000);	/* disable all */
+	mtdcr(uic1cr, 0x00000000);	/* all non-critical */
+	mtdcr(uic1pr, 0xffffffff);	/* per ref-board manual */
+	mtdcr(uic1tr, 0x00000000);	/* per ref-board manual */
+	mtdcr(uic1vr, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(uic1sr, 0xffffffff);	/* clear all */
+
+	mtdcr(uic2sr, 0xffffffff);	/* clear all */
+	mtdcr(uic2er, 0x00000000);	/* disable all */
+	mtdcr(uic2cr, 0x00000000);	/* all non-critical */
+	mtdcr(uic2pr, 0xffffffff);	/* per ref-board manual */
+	mtdcr(uic2tr, 0x00000000);	/* per ref-board manual */
+	mtdcr(uic2vr, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(uic2sr, 0xffffffff);	/* clear all */
+
+	mtdcr(uic3sr, 0xffffffff);	/* clear all */
+	mtdcr(uic3er, 0x00000000);	/* disable all */
+	mtdcr(uic3cr, 0x00000000);	/* all non-critical */
+	mtdcr(uic3pr, 0xffffffff);	/* per ref-board manual */
+	mtdcr(uic3tr, 0x00000000);	/* per ref-board manual */
+	mtdcr(uic3vr, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(uic3sr, 0xffffffff);	/* clear all */
+
+	/*
+	 * Configure PFC (Pin Function Control) registers
+	 * enable GPIO 49-63
+	 * UART0: 4 pins
+	 */
+	mtsdr(SDR0_PFC0, 0x00007fff);
+	mtsdr(SDR0_PFC1, 0x00040000);
+
+	/* Enable PCI host functionality in SDR0_PCI0 */
+	mtsdr(SDR0_PCI0, 0xe0000000);
+
+	mtsdr(SDR0_SRST1, 0);	/* Pull AHB out of reset default=1 */
+
+	/* Setup PLB4-AHB bridge based on the system address map */
+	mtdcr(AHB_TOP, 0x8000004B);
+	mtdcr(AHB_BOT, 0x8000004B);
+
+	/*
+	* Configure USB-STP pins as alternate and not GPIO
+	* It seems to be neccessary to configure the STP pins as GPIO
+	* input at powerup (perhaps while USB reset is asserted). So
+	* we configure those pins to their "real" function now.
+	*/
+	gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
+	gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
+
+	/* Trigger board component reset */
+	out_le16((void *)CONFIG_SYS_IO_BASE, 0xffff);
+	out_le16((void *)CONFIG_SYS_IO_BASE + 0x100, 0xffff);
+	udelay(50);
+	out_le16((void *)CONFIG_SYS_IO_BASE, 0xffbf);
+	out_le16((void *)CONFIG_SYS_IO_BASE + 0x100, 0xffbf);
+	udelay(50);
+	out_le16((void *)CONFIG_SYS_IO_BASE, 0xffff);
+	out_le16((void *)CONFIG_SYS_IO_BASE + 0x100, 0xffff);
+
+	return 0;
+}
+
+int get_cpu_num(void)
+{
+	int cpu = NA_OR_UNKNOWN_CPU;
+
+	return cpu;
+}
+
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+
+#ifdef CONFIG_DEVCONCENTER
+	printf("Board: DevCon-Center");
+#else
+	printf("Board: CompactCenter");
+#endif
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	return 0;
+}
+
+/*
+ *  pci_target_init
+ *
+ *	The bootstrap configuration provides default settings for the pci
+ *	inbound map (PIM). But the bootstrap config choices are limited and
+ *	may not be sufficient for a given board.
+ */
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
+void pci_target_init(struct pci_controller *hose)
+{
+	/*
+	 * Disable everything
+	 */
+	out_le32((void *)PCIX0_PIM0SA, 0); /* disable */
+	out_le32((void *)PCIX0_PIM1SA, 0); /* disable */
+	out_le32((void *)PCIX0_PIM2SA, 0); /* disable */
+	out_le32((void *)PCIX0_EROMBA, 0); /* disable expansion rom */
+
+	/*
+	 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
+	 * strapping options to not support sizes such as 128/256 MB.
+	 */
+	out_le32((void *)PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
+	out_le32((void *)PCIX0_PIM0LAH, 0);
+	out_le32((void *)PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
+	out_le32((void *)PCIX0_BAR0, 0);
+
+	/*
+	 * Program the board's subsystem id/vendor id
+	 */
+	out_le16((void *)PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
+	out_le16((void *)PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
+
+	out_le16((void *)PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
+}
+#endif	/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
+
+#if defined(CONFIG_PCI)
+/*
+ * is_pci_host
+ *
+ * This routine is called to determine if a pci scan should be
+ * performed. With various hardware environments (especially cPCI and
+ * PPMC) it's insufficient to depend on the state of the arbiter enable
+ * bit in the strap register, or generic host/adapter assumptions.
+ *
+ * Rather than hard-code a bad assumption in the general 440 code, the
+ * 440 pci code requires the board to decide at runtime.
+ *
+ * Return 0 for adapter mode, non-zero for host (monarch) mode.
+ */
+int is_pci_host(struct pci_controller *hose)
+{
+	/* Board is always configured as host. */
+	return 1;
+}
+#endif /* CONFIG_PCI */
+
+int board_early_init_r(void)
+{
+	/*
+	 * CompactCenter has 64MBytes, DevCon-Center 128MBytes of NOR FLASH
+	 * (Spansion 29GL512), but the boot EBC mapping only supports a maximum
+	 * of 16MBytes (4.ff00.0000 - 4.ffff.ffff).
+	 * To solve this problem, the FLASH has to get remapped to another
+	 * EBC address which accepts bigger regions:
+	 *
+	 * 0xfn00.0000 -> 4.cn00.0000
+	 */
+
+	u32 bxcr_bw = (CONFIG_SYS_FLASH_SIZE == 128 << 20) ?
+		EBC_BXCR_BS_128MB : EBC_BXCR_BS_64MB;
+
+	/* Remap the NOR FLASH to 0xcn00.0000 ... 0xcfff.ffff */
+	mtebc(pb0cr, CONFIG_SYS_FLASH_BASE_PHYS_L
+		| bxcr_bw
+		| EBC_BXCR_BU_RW
+		| EBC_BXCR_BW_16BIT);
+
+	/* Remove TLB entry of boot EBC mapping */
+	remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
+
+	/* Add TLB entry for 0xfn00.0000 -> 0x4.cn00.0000 */
+	program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE,
+			CONFIG_SYS_FLASH_SIZE, TLB_WORD2_I_ENABLE);
+
+	/*
+	 * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
+	 * 0xfc00.0000 is possible
+	 */
+
+	/*
+	 * Clear potential errors resulting from auto-calibration.
+	 * If not done, then we could get an interrupt later on when
+	 * exceptions are enabled.
+	 */
+	set_mcsr(get_mcsr());
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	u32 sdr0_srst1 = 0;
+	u32 eth_cfg;
+
+	/*
+	 * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
+	 * This is board specific, so let's do it here.
+	 */
+	mfsdr(SDR0_ETH_CFG, eth_cfg);
+	/* disable SGMII mode */
+	eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE |
+		     SDR0_ETH_CFG_SGMII1_ENABLE |
+		     SDR0_ETH_CFG_SGMII0_ENABLE);
+	/* Set the for 2 RGMII mode */
+	/* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
+	eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
+	eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
+	mtsdr(SDR0_ETH_CFG, eth_cfg);
+
+	/*
+	 * The AHB Bridge core is held in reset after power-on or reset
+	 * so enable it now
+	 */
+	mfsdr(SDR0_SRST1, sdr0_srst1);
+	sdr0_srst1 &= ~SDR0_SRST1_AHB;
+	mtsdr(SDR0_SRST1, sdr0_srst1);
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+extern void __ft_board_setup(void *blob, bd_t *bd);
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	__ft_board_setup(blob, bd);
+
+	fdt_find_and_setprop(blob, "/plb/pciex@d00000000", "status",
+			     "disabled", sizeof("disabled"), 1);
+
+	fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status",
+			     "disabled", sizeof("disabled"), 1);
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */

board/gdsys/compactcenter/config.mk

@@ -0,0 +1,41 @@
+#
+# (C) Copyright 2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+#
+# G&D CompactCenter
+#
+
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+
+ifndef TEXT_BASE
+TEXT_BASE = 0xFFFA0000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif

board/gdsys/compactcenter/init.S

@@ -0,0 +1,97 @@
+/*
+ * (C) Copyright 2009
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * Based on board/amcc/canyonlands/init.S
+ * (C) Copyright 2008
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+#include <asm-ppc/mmu.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+	.section .bootpg,"ax"
+	.globl tlbtab
+
+tlbtab:
+	tlbtab_start
+
+	/*
+	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to
+	 * use the speed up boot process. It is patched after relocation to
+	 * enable SA_I
+	 */
+	tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR,
+		4, AC_R|AC_W|AC_X|SA_G) /* TLB 0 */
+
+	/*
+	 * TLB entries for SDRAM are not needed on this platform.
+	 * They are dynamically generated in the SPD DDR(2) detection
+	 * routine.
+	 */
+
+#ifdef CONFIG_SYS_INIT_RAM_DCACHE
+	/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+	tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR,
+		0, AC_R|AC_W|AC_X|SA_G)
+#endif
+
+	tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC,
+		AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x20000000, 0xC,
+		AC_R|AC_W|SA_G|SA_I)
+
+	/* TLB-entry for NVRAM */
+	tlbentry(CONFIG_SYS_NVRAM_BASE, SZ_1M, CONFIG_SYS_NVRAM_BASE, 4,
+		AC_R|AC_W|SA_G|SA_I)
+
+	/* TLB-entry for UART */
+	tlbentry(CONFIG_SYS_UART_BASE, SZ_16K, CONFIG_SYS_UART_BASE, 4,
+		AC_R|AC_W|SA_G|SA_I)
+
+	/* TLB-entry for IO */
+	tlbentry(CONFIG_SYS_IO_BASE, SZ_16K, CONFIG_SYS_IO_BASE, 4,
+		AC_R|AC_W|SA_G|SA_I)
+
+	/* TLB-entry for OCM */
+	tlbentry(CONFIG_SYS_OCM_BASE, SZ_1M, 0x00000000, 4,
+		AC_R|AC_W|AC_X|SA_I)
+
+	/* TLB-entry for Local Configuration registers => peripherals */
+	tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M, CONFIG_SYS_LOCAL_CONF_REGS,
+		4, AC_R|AC_W|AC_X|SA_G|SA_I)
+
+	/* AHB: Internal USB Peripherals (USB, SATA) */
+	tlbentry(CONFIG_SYS_AHB_BASE, SZ_1M, 0xbff00000, 4,
+		AC_R|AC_W|AC_X|SA_G|SA_I)
+
+	tlbtab_end

board/gdsys/compactcenter/u-boot.lds

@@ -0,0 +1,144 @@
+/*
+ * (C) Copyright 2008
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .bootpg 0xFFFFF000 :
+  {
+    cpu/ppc4xx/start.o	(.bootpg)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    board/gdsys/compactcenter/init.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD) :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+
+  _end = . ;
+  PROVIDE (end = .);
+}

board/jse/init.S

@@ -1,5 +1,9 @@
 /*------------------------------------------------------------------------+ */
 /* */
+/*       This source code is dual-licensed.  You may use it under the terms */
+/*       of the GNU General Public License version 2, or under the license  */
+/*       below.                                                             */
+/*                                                                          */
 /*       This source code has been made available to you by IBM on an AS-IS */
 /*       basis.  Anyone receiving this source is licensed under IBM */
 /*       copyrights to use it in any way he or she deems fit, including */

board/matrix_vision/mvblm7/Makefile

@@ -1,5 +1,5 @@
 #
-# Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
+# Copyright (C) Freescale Semiconductor, Inc. 2006.
 #
 # See file CREDITS for list of people who contributed to this
 # project.

board/matrix_vision/mvblm7/config.mk

@@ -1,5 +1,5 @@
 #
-# Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
+# Copyright (C) Freescale Semiconductor, Inc. 2006.
 #
 # See file CREDITS for list of people who contributed to this
 # project.

board/matrix_vision/mvblm7/mvblm7.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
+ * Copyright (C) Freescale Semiconductor, Inc. 2006.
  *
  * (C) Copyright 2008
  * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de

board/matrix_vision/mvblm7/pci.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
+ * Copyright (C) Freescale Semiconductor, Inc. 2006.
  *
  * (C) Copyright 2008
  * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de

board/mpl/common/pci.c

@@ -1,4 +1,6 @@
 /*-----------------------------------------------------------------------------+
+|       This source code is dual-licensed.  You may use it under the terms of
+|       the GNU General Public License version 2, or under the license below.
 |
 |       This source code has been made available to you by IBM on an AS-IS
 |       basis.  Anyone receiving this source is licensed under IBM

board/mpl/mip405/init.S

@@ -1,4 +1,6 @@
 /*------------------------------------------------------------------------------+
+ *      This source code is dual-licensed.  You may use it under the terms of
+ *      the GNU General Public License version 2, or under the license below.
  *
  *      This source code has been made available to you by IBM on an AS-IS
  *      basis.  Anyone receiving this source is licensed under IBM

board/mpl/pip405/init.S

@@ -1,4 +1,6 @@
 /*------------------------------------------------------------------------------+
+ *      This source code is dual-licensed.  You may use it under the terms of
+ *      the GNU General Public License version 2, or under the license below.
  *
  *      This source code has been made available to you by IBM on an AS-IS
  *      basis.  Anyone receiving this source is licensed under IBM

board/omap3/beagle/beagle.c

@@ -30,6 +30,7 @@
  * MA 02111-1307 USA
  */
 #include <common.h>
+#include <twl4030.h>
 #include <asm/io.h>
 #include <asm/arch/mux.h>
 #include <asm/arch/sys_proto.h>
@@ -102,10 +103,11 @@ void beagle_identify(void)
  */
 int misc_init_r(void)
 {
-	gpio_t *gpio5_base = (gpio_t *)OMAP34XX_GPIO5_BASE;
-	gpio_t *gpio6_base = (gpio_t *)OMAP34XX_GPIO6_BASE;
+	struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
+	struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
 
-	power_init_r();
+	twl4030_power_init();
+	twl4030_led_init();
 
 	/* Configure GPIOs to output */
 	writel(~(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1), &gpio6_base->oe);

board/omap3/common/power.c

@@ -1,74 +0,0 @@
-/*
- * (C) Copyright 2004-2008
- * Texas Instruments, <www.ti.com>
- *
- * Author :
- *	Sunil Kumar <sunilsaini05@gmail.com>
- *	Shashi Ranjan <shashiranjanmca05@gmail.com>
- *
- * Derived from Beagle Board and 3430 SDP code by
- *	Richard Woodruff <r-woodruff2@ti.com>
- *	Syed Mohammed Khasim <khasim@ti.com>
- *
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <common.h>
-#include <asm/arch/sys_proto.h>
-#include <i2c.h>
-
-/******************************************************************************
- * Routine: power_init_r
- * Description: Configure power supply
- *****************************************************************************/
-void power_init_r(void)
-{
-	unsigned char byte;
-
-#ifdef CONFIG_DRIVER_OMAP34XX_I2C
-	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-#endif
-
-	/*
-	 * Configure OMAP3 supply voltages in power management
-	 * companion chip.
-	 */
-
-	/* set VAUX3 to 2.8V */
-	byte = DEV_GRP_P1;
-	i2c_write(PWRMGT_ADDR_ID4, VAUX3_DEV_GRP, 1, &byte, 1);
-	byte = VAUX3_VSEL_28;
-	i2c_write(PWRMGT_ADDR_ID4, VAUX3_DEDICATED, 1, &byte, 1);
-
-	/* set VPLL2 to 1.8V */
-	byte = DEV_GRP_ALL;
-	i2c_write(PWRMGT_ADDR_ID4, VPLL2_DEV_GRP, 1, &byte, 1);
-	byte = VPLL2_VSEL_18;
-	i2c_write(PWRMGT_ADDR_ID4, VPLL2_DEDICATED, 1, &byte, 1);
-
-	/* set VDAC to 1.8V */
-	byte = DEV_GRP_P1;
-	i2c_write(PWRMGT_ADDR_ID4, VDAC_DEV_GRP, 1, &byte, 1);
-	byte = VDAC_VSEL_18;
-	i2c_write(PWRMGT_ADDR_ID4, VDAC_DEDICATED, 1, &byte, 1);
-
-	/* enable LED */
-	byte = LEDBPWM | LEDAPWM | LEDBON | LEDAON;
-	i2c_write(PWRMGT_ADDR_ID3, LEDEN, 1, &byte, 1);
-}

board/omap3/evm/evm.c

@@ -92,18 +92,17 @@ void set_muxconf_regs(void)
  */
 static void setup_net_chip(void)
 {
-	gpio_t *gpio3_base = (gpio_t *)OMAP34XX_GPIO3_BASE;
-	gpmc_csx_t *gpmc_cs5_base = (gpmc_csx_t *)GPMC_CONFIG_CS5_BASE;
-	ctrl_t *ctrl_base = (ctrl_t *)OMAP34XX_CTRL_BASE;
+	struct gpio *gpio3_base = (struct gpio *)OMAP34XX_GPIO3_BASE;
+	struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
 
 	/* Configure GPMC registers */
-	writel(NET_GPMC_CONFIG1, &gpmc_cs5_base->config1);
-	writel(NET_GPMC_CONFIG2, &gpmc_cs5_base->config2);
-	writel(NET_GPMC_CONFIG3, &gpmc_cs5_base->config3);
-	writel(NET_GPMC_CONFIG4, &gpmc_cs5_base->config4);
-	writel(NET_GPMC_CONFIG5, &gpmc_cs5_base->config5);
-	writel(NET_GPMC_CONFIG6, &gpmc_cs5_base->config6);
-	writel(NET_GPMC_CONFIG7, &gpmc_cs5_base->config7);
+	writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[5].config1);
+	writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[5].config2);
+	writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[5].config3);
+	writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[5].config4);
+	writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[5].config5);
+	writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[5].config6);
+	writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[5].config7);
 
 	/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
 	writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);

board/omap3/overo/overo.c

@@ -29,6 +29,7 @@
  * MA 02111-1307 USA
  */
 #include <common.h>
+#include <twl4030.h>
 #include <asm/io.h>
 #include <asm/arch/mux.h>
 #include <asm/arch/sys_proto.h>
@@ -58,7 +59,8 @@ int board_init(void)
  */
 int misc_init_r(void)
 {
-	power_init_r();
+	twl4030_power_init();
+	twl4030_led_init();
 
 	dieid_num_r();
 

board/omap3/pandora/pandora.c

@@ -30,6 +30,7 @@
  * MA 02111-1307 USA
  */
 #include <common.h>
+#include <twl4030.h>
 #include <asm/io.h>
 #include <asm/arch/mux.h>
 #include <asm/arch/sys_proto.h>
@@ -59,12 +60,13 @@ int board_init(void)
  */
 int misc_init_r(void)
 {
-	gpio_t *gpio1_base = (gpio_t *)OMAP34XX_GPIO1_BASE;
-	gpio_t *gpio4_base = (gpio_t *)OMAP34XX_GPIO4_BASE;
-	gpio_t *gpio5_base = (gpio_t *)OMAP34XX_GPIO5_BASE;
-	gpio_t *gpio6_base = (gpio_t *)OMAP34XX_GPIO6_BASE;
+	struct gpio *gpio1_base = (struct gpio *)OMAP34XX_GPIO1_BASE;
+	struct gpio *gpio4_base = (struct gpio *)OMAP34XX_GPIO4_BASE;
+	struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
+	struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
 
-	power_init_r();
+	twl4030_power_init();
+	twl4030_led_init();
 
 	/* Configure GPIOs to output */
 	writel(~(GPIO14 | GPIO15 | GPIO16 | GPIO23), &gpio1_base->oe);

board/omap3/zoom1/zoom1.c

@@ -31,6 +31,7 @@
  * MA 02111-1307 USA
  */
 #include <common.h>
+#include <twl4030.h>
 #include <asm/io.h>
 #include <asm/arch/mux.h>
 #include <asm/arch/sys_proto.h>
@@ -60,8 +61,17 @@ int board_init(void)
  */
 int misc_init_r(void)
 {
-	power_init_r();
+	twl4030_power_init();
+	twl4030_led_init();
 	dieid_num_r();
+
+	/*
+	 * Board Reset
+	 * The board is reset by holding the red button on the
+	 * top right front face for eight seconds.
+	 */
+	twl4030_power_reset_init();
+
 	return 0;
 }
 

board/omap3/zoom2/zoom2.c

@@ -32,6 +32,7 @@
 #ifdef CONFIG_STATUS_LED
 #include <status_led.h>
 #endif
+#include <twl4030.h>
 #include <asm/io.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/mem.h>
@@ -49,8 +50,8 @@
  * The details of the setting of the serial gpmc setup are not available.
  * The values were provided by another party.
  */
-extern void enable_gpmc_config(u32 *gpmc_config, gpmc_csx_t *gpmc_cs_base,
-			       u32 base, u32 size);
+void enable_gpmc_cs_config(u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
+			u32 size);
 
 static u32 gpmc_serial_TL16CP754C[GPMC_MAX_REG] = {
 	0x00011000,
@@ -122,19 +123,14 @@ void zoom2_identify(void)
 int board_init (void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
-	gpmc_csx_t *serial_cs_base;
 	u32 *gpmc_config;
 
 	gpmc_init ();		/* in SRAM or SDRAM, finish GPMC */
 
 	/* Configure console support on zoom2 */
 	gpmc_config = gpmc_serial_TL16CP754C;
-	serial_cs_base = (gpmc_csx_t *) (GPMC_CONFIG_CS0_BASE +
-					 (3 * GPMC_CONFIG_WIDTH));
-	enable_gpmc_config(gpmc_config,
-			   serial_cs_base,
-			   SERIAL_TL16CP754C_BASE,
-			   GPMC_SIZE_16M);
+	enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[4],
+			SERIAL_TL16CP754C_BASE, GPMC_SIZE_16M);
 
 	/* board id for Linux */
 	gd->bd->bi_arch_number = MACH_TYPE_OMAP_ZOOM2;
@@ -154,8 +150,22 @@ int board_init (void)
 int misc_init_r(void)
 {
 	zoom2_identify();
-	power_init_r();
+	twl4030_power_init();
+	twl4030_led_init();
 	dieid_num_r();
+
+	/*
+	 * Board Reset
+	 * The board is reset by holding the the large button
+	 * on the top right side of the main board for
+	 * eight seconds.
+	 *
+	 * There are reported problems of some beta boards
+	 * continously resetting.  For those boards, disable resetting.
+	 */
+	if (ZOOM2_REVISION_PRODUCTION <= zoom2_get_revision())
+		twl4030_power_reset_init();
+
 	return 0;
 }
 

board/sbc8349/config.mk

@@ -24,4 +24,4 @@
 # SBC8349E
 #
 
-TEXT_BASE  =   0xFFF00000
+TEXT_BASE  =   0xFF800000

board/sc3/init.S

@@ -4,6 +4,9 @@
  *	 (www.eurodsn.de). It's based on the original IBM source code, so
  *	 this follows:
  *
+ *   This source code is dual-licensed.  You may use it under the terms of the
+ *   GNU General Public License version 2, or under the license below.
+ *
  *	 This source code has been made available to you by IBM on an AS-IS
  *	 basis.  Anyone receiving this source is licensed under IBM
  *	 copyrights to use it in any way he or she deems fit, including

board/st/nhk8815/nhk8815.c

@@ -27,6 +27,7 @@
 
 #include <common.h>
 #include <asm/io.h>
+#include <asm/arch/gpio.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -61,9 +62,20 @@ int board_init(void)
 	return 0;
 }
 
-int misc_init_r(void)
+int board_late_init(void)
 {
-	setenv("verify", "n");
+	/* Set the two I2C gpio lines to be gpio high */
+	nmk_gpio_set(__SCL, 1);	nmk_gpio_set(__SDA, 1);
+	nmk_gpio_dir(__SCL, 1);	nmk_gpio_dir(__SDA, 1);
+	nmk_gpio_af(__SCL, GPIO_GPIO); nmk_gpio_af(__SDA, GPIO_GPIO);
+
+	/* Reset the I2C port expander, on GPIO77 */
+	nmk_gpio_af(77, GPIO_GPIO);
+	nmk_gpio_dir(77, 1);
+	nmk_gpio_set(77, 0);
+	udelay(10);
+	nmk_gpio_set(77, 1);
+
 	return 0;
 }
 

board/w7o/init.S

@@ -1,4 +1,6 @@
 /******************************************************************************
+ *   This source code is dual-licensed.  You may use it under the terms of the
+ *   GNU General Public License version 2, or under the license below.
  *
  *	 This source code has been made available to you by IBM on an AS-IS
  *	 basis.	 Anyone receiving this source is licensed under IBM

common/cmd_ext2.c

@@ -67,51 +67,50 @@ int do_ext2ls (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 	if (argc < 3) {
 		cmd_usage(cmdtp);
-		return(1);
+		return 1;
 	}
 	dev = (int)simple_strtoul (argv[2], &ep, 16);
 	dev_desc = get_dev(argv[1],dev);
 
 	if (dev_desc == NULL) {
 		printf ("\n** Block device %s %d not supported\n", argv[1], dev);
-		return(1);
+		return 1;
 	}
 
 	if (*ep) {
 		if (*ep != ':') {
 			puts ("\n** Invalid boot device, use `dev[:part]' **\n");
-			return(1);
+			return 1;
 		}
 		part = (int)simple_strtoul(++ep, NULL, 16);
 	}
 
-	if (argc == 4) {
-	    filename = argv[3];
-	}
+	if (argc == 4)
+		filename = argv[3];
 
 	PRINTF("Using device %s %d:%d, directory: %s\n", argv[1], dev, part, filename);
 
 	if ((part_length = ext2fs_set_blk_dev(dev_desc, part)) == 0) {
 		printf ("** Bad partition - %s %d:%d **\n",  argv[1], dev, part);
 		ext2fs_close();
-		return(1);
+		return 1;
 	}
 
 	if (!ext2fs_mount(part_length)) {
 		printf ("** Bad ext2 partition or disk - %s %d:%d **\n",  argv[1], dev, part);
 		ext2fs_close();
-		return(1);
+		return 1;
 	}
 
 	if (ext2fs_ls (filename)) {
 		printf ("** Error ext2fs_ls() **\n");
 		ext2fs_close();
-		return(1);
+		return 1;
 	};
 
 	ext2fs_close();
 
-	return(0);
+	return 0;
 }
 
 U_BOOT_CMD(
@@ -140,11 +139,11 @@ int do_ext2load (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	switch (argc) {
 	case 3:
 		addr_str = getenv("loadaddr");
-		if (addr_str != NULL) {
+		if (addr_str != NULL)
 			addr = simple_strtoul (addr_str, NULL, 16);
-		} else {
+		else
 			addr = CONFIG_SYS_LOAD_ADDR;
-		}
+
 		filename = getenv ("bootfile");
 		count = 0;
 		break;
@@ -166,24 +165,24 @@ int do_ext2load (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 	default:
 		cmd_usage(cmdtp);
-		return(1);
+		return 1;
 	}
 
 	if (!filename) {
-		puts ("\n** No boot file defined **\n");
-		return(1);
+		puts ("** No boot file defined **\n");
+		return 1;
 	}
 
 	dev = (int)simple_strtoul (argv[2], &ep, 16);
 	dev_desc = get_dev(argv[1],dev);
 	if (dev_desc==NULL) {
-		printf ("\n** Block device %s %d not supported\n", argv[1], dev);
-		return(1);
+		printf ("** Block device %s %d not supported\n", argv[1], dev);
+		return 1;
 	}
 	if (*ep) {
 		if (*ep != ':') {
-			puts ("\n** Invalid boot device, use `dev[:part]' **\n");
-			return(1);
+			puts ("** Invalid boot device, use `dev[:part]' **\n");
+			return 1;
 		}
 		part = (int)simple_strtoul(++ep, NULL, 16);
 	}
@@ -193,50 +192,53 @@ int do_ext2load (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	if (part != 0) {
 		if (get_partition_info (dev_desc, part, &info)) {
 			printf ("** Bad partition %d **\n", part);
-			return(1);
+			return 1;
 		}
 
 		if (strncmp((char *)info.type, BOOT_PART_TYPE, sizeof(info.type)) != 0) {
-			printf ("\n** Invalid partition type \"%.32s\""
+			printf ("** Invalid partition type \"%.32s\""
 				" (expect \"" BOOT_PART_TYPE "\")\n",
 				info.type);
-			return(1);
+			return 1;
 		}
-		PRINTF ("\nLoading from block device %s device %d, partition %d: "
-			"Name: %.32s  Type: %.32s  File:%s\n",
-			argv[1], dev, part, info.name, info.type, filename);
+		printf ("Loading file \"%s\" "
+			"from %s device %d:%d (%.32s)\n",
+			filename,
+			argv[1], dev, part, info.name);
 	} else {
-		PRINTF ("\nLoading from block device %s device %d, File:%s\n",
-			argv[1], dev, filename);
+		printf ("Loading file \"%s\" from %s device %d\n",
+			filename, argv[1], dev);
 	}
 
 
 	if ((part_length = ext2fs_set_blk_dev(dev_desc, part)) == 0) {
 		printf ("** Bad partition - %s %d:%d **\n",  argv[1], dev, part);
 		ext2fs_close();
-		return(1);
+		return 1;
 	}
 
 	if (!ext2fs_mount(part_length)) {
-		printf ("** Bad ext2 partition or disk - %s %d:%d **\n",  argv[1], dev, part);
+		printf ("** Bad ext2 partition or disk - %s %d:%d **\n",
+			argv[1], dev, part);
 		ext2fs_close();
-		return(1);
+		return 1;
 	}
 
 	filelen = ext2fs_open(filename);
 	if (filelen < 0) {
 		printf("** File not found %s\n", filename);
 		ext2fs_close();
-		return(1);
+		return 1;
 	}
 	if ((count < filelen) && (count != 0)) {
 	    filelen = count;
 	}
 
 	if (ext2fs_read((char *)addr, filelen) != filelen) {
-		printf("\n** Unable to read \"%s\" from %s %d:%d **\n", filename, argv[1], dev, part);
+		printf("** Unable to read \"%s\" from %s %d:%d **\n",
+			filename, argv[1], dev, part);
 		ext2fs_close();
-		return(1);
+		return 1;
 	}
 
 	ext2fs_close();
@@ -244,11 +246,11 @@ int do_ext2load (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	/* Loading ok, update default load address */
 	load_addr = addr;
 
-	printf ("\n%d bytes read\n", filelen);
+	printf ("%d bytes read\n", filelen);
 	sprintf(buf, "%X", filelen);
 	setenv("filesize", buf);
 
-	return(filelen);
+	return 0;
 }
 
 U_BOOT_CMD(

common/cmd_sf.c

@@ -48,7 +48,7 @@ static int do_spi_flash_probe(int argc, char *argv[])
 			goto usage;
 	}
 	if (argc >= 4) {
-		mode = simple_strtoul(argv[3], &endp, 0);
+		mode = simple_strtoul(argv[3], &endp, 16);
 		if (*argv[3] == 0 || *endp != 0)
 			goto usage;
 	}

common/env_common.c

@@ -139,11 +139,6 @@ uchar default_environment[] = {
 	"\0"
 };
 
-#if defined(CONFIG_ENV_IS_IN_NAND)		/* Environment is in Nand Flash */ \
-	|| defined(CONFIG_ENV_IS_IN_SPI_FLASH)
-int default_environment_size = sizeof(default_environment);
-#endif
-
 void env_crc_update (void)
 {
 	env_ptr->crc = crc32(0, env_ptr->data, ENV_SIZE);

common/env_dataflash.c

@@ -35,7 +35,6 @@ extern int write_dataflash (unsigned long addr_dest, unsigned long addr_src,
 		     unsigned long size);
 extern int AT91F_DataflashInit (void);
 extern uchar default_environment[];
-/* extern int default_environment_size; */
 
 
 uchar env_get_char_spec (int index)

common/env_flash.c

@@ -83,7 +83,6 @@ static ulong end_addr_new = CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1;
 #endif /* CONFIG_ENV_ADDR_REDUND */
 
 extern uchar default_environment[];
-extern int default_environment_size;
 
 
 uchar env_get_char_spec (int index)

common/env_mgdisk.c

@@ -29,7 +29,6 @@
 
 /* references to names in env_common.c */
 extern uchar default_environment[];
-extern int default_environment_size;
 
 char * env_name_spec = "MG_DISK";
 

common/env_nand.c

@@ -59,7 +59,6 @@
 
 /* references to names in env_common.c */
 extern uchar default_environment[];
-extern int default_environment_size;
 
 char * env_name_spec = "NAND";
 

common/env_nowhere.c

@@ -34,7 +34,6 @@ DECLARE_GLOBAL_DATA_PTR;
 env_t *env_ptr = NULL;
 
 extern uchar default_environment[];
-extern int default_environment_size;
 
 
 void env_relocate_spec (void)

common/env_nvram.c

@@ -58,7 +58,6 @@ env_t *env_ptr = (env_t *)CONFIG_ENV_ADDR;
 char * env_name_spec = "NVRAM";
 
 extern uchar default_environment[];
-extern int default_environment_size;
 
 #ifdef CONFIG_AMIGAONEG3SE
 uchar env_get_char_spec (int index)

common/env_sf.c

@@ -47,7 +47,6 @@ DECLARE_GLOBAL_DATA_PTR;
 
 /* references to names in env_common.c */
 extern uchar default_environment[];
-extern int default_environment_size;
 
 char * env_name_spec = "SPI Flash";
 env_t *env_ptr;
@@ -143,16 +142,7 @@ err_probe:
 err_crc:
 	puts("*** Warning - bad CRC, using default environment\n\n");
 
-	if (default_environment_size > CONFIG_ENV_SIZE) {
-		gd->env_valid = 0;
-		puts("*** Error - default environment is too large\n\n");
-		return;
-	}
-
-	memset(env_ptr, 0, sizeof(env_t));
-	memcpy(env_ptr->data, default_environment, default_environment_size);
-	env_ptr->crc = crc32(0, env_ptr->data, ENV_SIZE);
-	gd->env_valid = 1;
+	set_default_env();
 }
 
 int env_init(void)

common/exports.c

@@ -38,4 +38,12 @@ void jumptable_init (void)
 	gd->jt[XF_i2c_write] = (void *) i2c_write;
 	gd->jt[XF_i2c_read] = (void *) i2c_read;
 #endif
+#ifdef CONFIG_CMD_SPI
+	gd->jt[XF_spi_init] = (void *) spi_init;
+	gd->jt[XF_spi_setup_slave] = (void *) spi_setup_slave;
+	gd->jt[XF_spi_free_slave] = (void *) spi_free_slave;
+	gd->jt[XF_spi_claim_bus] = (void *) spi_claim_bus;
+	gd->jt[XF_spi_release_bus] = (void *) spi_release_bus;
+	gd->jt[XF_spi_xfer] = (void *) spi_xfer;
+#endif
 }

common/fdt_support.c

@@ -625,7 +625,7 @@ int fdt_resize(void *blob)
 }
 
 #ifdef CONFIG_PCI
-#define CONFIG_SYS_PCI_NR_INBOUND_WIN 3
+#define CONFIG_SYS_PCI_NR_INBOUND_WIN 4
 
 #define FDT_PCI_PREFETCH	(0x40000000)
 #define FDT_PCI_MEM32		(0x02000000)
@@ -655,7 +655,7 @@ int fdt_pci_dma_ranges(void *blob, int phb_off, struct pci_controller *hose) {
 		size = (u64)hose->regions[r].size;
 
 		dma_range[0] = 0;
-		if (size > 0x100000000ull)
+		if (size >= 0x100000000ull)
 			dma_range[0] |= FDT_PCI_MEM64;
 		else
 			dma_range[0] |= FDT_PCI_MEM32;

common/hush.c

@@ -2002,7 +2002,7 @@ static int free_pipe(struct pipe *pi, int indent)
 #ifndef __U_BOOT__
 			globfree(&child->glob_result);
 #else
-			for (a = child->argc;a >= 0;a--) {
+			for (a = 0; a < child->argc; a++) {
 				free(child->argv[a]);
 			}
 					free(child->argv);

cpu/arm920t/at91rm9200/lowlevel_init.S

@@ -81,6 +81,7 @@ LoopOsc:
 	bne	0b
 	/* delay - this is all done by guess */
 	ldr	r0, =0x00010000
+	/* (vs reading PMC_SR for LOCKA, LOCKB ... or MOSCS earlier) */
 1:
 	subs	r0, r0, #1
 	bhi	1b
@@ -108,16 +109,6 @@ LoopOsc:
 	.ltorg
 
 SMRDATA:
-	.word AT91C_MC_PUIA
-	.word CONFIG_SYS_MC_PUIA_VAL
-	.word AT91C_MC_PUP
-	.word CONFIG_SYS_MC_PUP_VAL
-	.word AT91C_MC_PUER
-	.word CONFIG_SYS_MC_PUER_VAL
-	.word AT91C_MC_ASR
-	.word CONFIG_SYS_MC_ASR_VAL
-	.word AT91C_MC_AASR
-	.word CONFIG_SYS_MC_AASR_VAL
 	.word AT91C_EBI_CFGR
 	.word CONFIG_SYS_EBI_CFGR_VAL
 	.word AT91C_SMC_CSR0
@@ -128,8 +119,7 @@ SMRDATA:
 	.word CONFIG_SYS_PLLBR_VAL
 	.word AT91C_MCKR
 	.word CONFIG_SYS_MCKR_VAL
-	/* SMRDATA is 80 bytes long */
-	/* here there's a delay of 100 */
+	/* here there's a delay */
 SMRDATA1:
 	.word AT91C_PIOC_ASR
 	.word CONFIG_SYS_PIOC_ASR_VAL

cpu/arm926ejs/at91/lowlevel_init.S

@@ -194,7 +194,7 @@ SMRDATA:
 	.word CONFIG_SYS_PIOD_PPUDR_VAL
 	.word (AT91_BASE_SYS + AT91_PIOD + PIO_ASR)
 	.word CONFIG_SYS_PIOD_PPUDR_VAL
-#elif defined(CONFIG_AT91SAM9261)
+#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261)
 	.word (AT91_BASE_SYS + AT91_PIOC + PIO_PDR)
 	.word CONFIG_SYS_PIOC_PDR_VAL1
 	.word (AT91_BASE_SYS + AT91_PIOC + PIO_PUDR)

cpu/arm926ejs/mx27/generic.c

@@ -23,6 +23,9 @@
 #include <netdev.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
+#ifdef CONFIG_MXC_MMC
+#include <asm/arch/mxcmmc.h>
+#endif
 
 /*
  *  get the system pll clock in Hz
@@ -169,6 +172,19 @@ int cpu_eth_init(bd_t *bis)
 #endif
 }
 
+/*
+ * Initializes on-chip MMC controllers.
+ * to override, implement board_mmc_init()
+ */
+int cpu_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_MXC_MMC
+	return mxc_mmc_init(bis);
+#else
+	return 0;
+#endif
+}
+
 void imx_gpio_mode(int gpio_mode)
 {
 	struct gpio_regs *regs = (struct gpio_regs *)IMX_GPIO_BASE;

cpu/arm926ejs/nomadik/Makefile

@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(SOC).a
 
-COBJS	= timer.o
+COBJS	= timer.o gpio.o
 SOBJS	= reset.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)

cpu/arm926ejs/nomadik/gpio.c

@@ -0,0 +1,99 @@
+/*
+ * (C) Copyright 2009 Alessandro Rubini
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/gpio.h>
+
+static unsigned long gpio_base[4] = {
+	NOMADIK_GPIO0_BASE,
+	NOMADIK_GPIO1_BASE,
+	NOMADIK_GPIO2_BASE,
+	NOMADIK_GPIO3_BASE
+};
+
+enum gpio_registers {
+	GPIO_DAT =	0x00,		/* data register */
+	GPIO_DATS =	0x04,		/* data set */
+	GPIO_DATC =	0x08,		/* data clear */
+	GPIO_PDIS =	0x0c,		/* pull disable */
+	GPIO_DIR =	0x10,		/* direction */
+	GPIO_DIRS =	0x14,		/* direction set */
+	GPIO_DIRC =	0x18,		/* direction clear */
+	GPIO_AFSLA =	0x20,		/* alternate function select A */
+	GPIO_AFSLB =	0x24,		/* alternate function select B */
+};
+
+static inline unsigned long gpio_to_base(int gpio)
+{
+	return gpio_base[gpio / 32];
+}
+
+static inline u32 gpio_to_bit(int gpio)
+{
+	return 1 << (gpio & 0x1f);
+}
+
+void nmk_gpio_af(int gpio, int alternate_function)
+{
+	unsigned long base = gpio_to_base(gpio);
+	u32 bit = gpio_to_bit(gpio);
+	u32 afunc, bfunc;
+
+	/* alternate function is 0..3, with one bit per register */
+	afunc = readl(base + GPIO_AFSLA) & ~bit;
+	bfunc = readl(base + GPIO_AFSLB) & ~bit;
+	if (alternate_function & 1) afunc |= bit;
+	if (alternate_function & 2) bfunc |= bit;
+	writel(afunc, base + GPIO_AFSLA);
+	writel(bfunc, base + GPIO_AFSLB);
+}
+
+void nmk_gpio_dir(int gpio, int dir)
+{
+	unsigned long base = gpio_to_base(gpio);
+	u32 bit = gpio_to_bit(gpio);
+
+	if (dir)
+		writel(bit, base + GPIO_DIRS);
+	else
+		writel(bit, base + GPIO_DIRC);
+}
+
+void nmk_gpio_set(int gpio, int val)
+{
+	unsigned long base = gpio_to_base(gpio);
+	u32 bit = gpio_to_bit(gpio);
+
+	if (val)
+		writel(bit, base + GPIO_DATS);
+	else
+		writel(bit, base + GPIO_DATC);
+}
+
+int nmk_gpio_get(int gpio)
+{
+	unsigned long base = gpio_to_base(gpio);
+	u32 bit = gpio_to_bit(gpio);
+
+	return readl(base + GPIO_DAT) & bit;
+}

cpu/arm_cortexa8/config.mk

@@ -30,7 +30,6 @@ PLATFORM_CPPFLAGS += -march=armv5
 # Supply options according to compiler version
 #
 # =========================================================================
-PLATFORM_CPPFLAGS +=$(call cc-option)
 PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,)
 PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,\
-		    $(call cc-option,-malignment-traps,))
+		    $(call cc-option,-malignment-traps,))

cpu/arm_cortexa8/omap3/board.c

@@ -59,11 +59,11 @@ static inline void delay(unsigned long loops)
  *****************************************************************************/
 void secure_unlock_mem(void)
 {
-	pm_t *pm_rt_ape_base = (pm_t *)PM_RT_APE_BASE_ADDR_ARM;
-	pm_t *pm_gpmc_base = (pm_t *)PM_GPMC_BASE_ADDR_ARM;
-	pm_t *pm_ocm_ram_base = (pm_t *)PM_OCM_RAM_BASE_ADDR_ARM;
-	pm_t *pm_iva2_base = (pm_t *)PM_IVA2_BASE_ADDR_ARM;
-	sms_t *sms_base = (sms_t *)OMAP34XX_SMS_BASE;
+	struct pm *pm_rt_ape_base = (struct pm *)PM_RT_APE_BASE_ADDR_ARM;
+	struct pm *pm_gpmc_base = (struct pm *)PM_GPMC_BASE_ADDR_ARM;
+	struct pm *pm_ocm_ram_base = (struct pm *)PM_OCM_RAM_BASE_ADDR_ARM;
+	struct pm *pm_iva2_base = (struct pm *)PM_IVA2_BASE_ADDR_ARM;
+	struct sms *sms_base = (struct sms *)OMAP34XX_SMS_BASE;
 
 	/* Protection Module Register Target APE (PM_RT) */
 	writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
@@ -234,7 +234,7 @@ void s_init(void)
  * Routine: wait_for_command_complete
  * Description: Wait for posting to finish on watchdog
  *****************************************************************************/
-void wait_for_command_complete(watchdog_t *wd_base)
+void wait_for_command_complete(struct watchdog *wd_base)
 {
 	int pending = 1;
 	do {
@@ -248,8 +248,8 @@ void wait_for_command_complete(watchdog_t *wd_base)
  *****************************************************************************/
 void watchdog_init(void)
 {
-	watchdog_t *wd2_base = (watchdog_t *)WD2_BASE;
-	prcm_t *prcm_base = (prcm_t *)PRCM_BASE;
+	struct watchdog *wd2_base = (struct watchdog *)WD2_BASE;
+	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 
 	/*
 	 * There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is

cpu/arm_cortexa8/omap3/clock.c

@@ -41,10 +41,10 @@
 u32 get_osc_clk_speed(void)
 {
 	u32 start, cstart, cend, cdiff, val;
-	prcm_t *prcm_base = (prcm_t *)PRCM_BASE;
-	prm_t *prm_base = (prm_t *)PRM_BASE;
-	gptimer_t *gpt1_base = (gptimer_t *)OMAP34XX_GPT1;
-	s32ktimer_t *s32k_base = (s32ktimer_t *)SYNC_32KTIMER_BASE;
+	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+	struct prm *prm_base = (struct prm *)PRM_BASE;
+	struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1;
+	struct s32ktimer *s32k_base = (struct s32ktimer *)SYNC_32KTIMER_BASE;
 
 	val = readl(&prm_base->clksrc_ctrl);
 
@@ -133,8 +133,8 @@ void prcm_init(void)
 	int xip_safe, p0, p1, p2, p3;
 	u32 osc_clk = 0, sys_clkin_sel;
 	u32 clk_index, sil_index = 0;
-	prm_t *prm_base = (prm_t *)PRM_BASE;
-	prcm_t *prcm_base = (prcm_t *)PRCM_BASE;
+	struct prm *prm_base = (struct prm *)PRM_BASE;
+	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 	dpll_param *dpll_param_p;
 
 	f_lock_pll = (void *) ((u32) &_end_vect - (u32) &_start +
@@ -341,7 +341,7 @@ void prcm_init(void)
  *****************************************************************************/
 void per_clocks_enable(void)
 {
-	prcm_t *prcm_base = (prcm_t *)PRCM_BASE;
+	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 
 	/* Enable GP2 timer. */
 	sr32(&prcm_base->clksel_per, 0, 1, 0x1);	/* GPT2 = sys clk */

cpu/arm_cortexa8/omap3/lowlevel_init.S

@@ -135,19 +135,19 @@ _go_to_speed: .word go_to_speed
 /* these constants need to be close for PIC code */
 /* The Nor has to be in the Flash Base CS0 for this condition to happen */
 flash_cfg1_addr:
-	.word (GPMC_CONFIG_CS0 + GPMC_CONFIG1)
+	.word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG1)
 flash_cfg3_addr:
-	.word (GPMC_CONFIG_CS0 + GPMC_CONFIG3)
+	.word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG3)
 flash_cfg3_val:
 	.word STNOR_GPMC_CONFIG3
 flash_cfg4_addr:
-	.word (GPMC_CONFIG_CS0 + GPMC_CONFIG4)
+	.word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG4)
 flash_cfg4_val:
 	.word STNOR_GPMC_CONFIG4
 flash_cfg5_val:
 	.word STNOR_GPMC_CONFIG5
 flash_cfg5_addr:
-	.word (GPMC_CONFIG_CS0 + GPMC_CONFIG5)
+	.word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG5)
 pll_ctl_add:
 	.word CM_CLKEN_PLL
 pll_div_add1:

cpu/arm_cortexa8/omap3/mem.c

@@ -41,6 +41,8 @@ unsigned int boot_flash_sec;
 unsigned int boot_flash_type;
 volatile unsigned int boot_flash_env_addr;
 
+struct gpmc *gpmc_cfg;
+
 #if defined(CONFIG_CMD_NAND)
 static u32 gpmc_m_nand[GPMC_MAX_REG] = {
 	M_NAND_GPMC_CONFIG1,
@@ -51,9 +53,6 @@ static u32 gpmc_m_nand[GPMC_MAX_REG] = {
 	M_NAND_GPMC_CONFIG6, 0
 };
 
-gpmc_csx_t *nand_cs_base;
-gpmc_t *gpmc_cfg_base;
-
 #if defined(CONFIG_ENV_IS_IN_NAND)
 #define GPMC_CS 0
 #else
@@ -72,8 +71,6 @@ static u32 gpmc_onenand[GPMC_MAX_REG] = {
 	ONENAND_GPMC_CONFIG6, 0
 };
 
-gpmc_csx_t *onenand_cs_base;
-
 #if defined(CONFIG_ENV_IS_IN_ONENAND)
 #define GPMC_CS 0
 #else
@@ -82,7 +79,7 @@ gpmc_csx_t *onenand_cs_base;
 
 #endif
 
-static sdrc_t *sdrc_base = (sdrc_t *)OMAP34XX_SDRC_BASE;
+static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
 
 /**************************************************************************
  * make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow
@@ -149,12 +146,12 @@ void sdrc_init(void)
 
 void do_sdrc_init(u32 cs, u32 early)
 {
-	sdrc_actim_t *sdrc_actim_base;
+	struct sdrc_actim *sdrc_actim_base;
 
 	if(cs)
-		sdrc_actim_base = (sdrc_actim_t *)SDRC_ACTIM_CTRL1_BASE;
+		sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
 	else
-		sdrc_actim_base = (sdrc_actim_t *)SDRC_ACTIM_CTRL0_BASE;
+		sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
 
 	if (early) {
 		/* reset sdrc controller */
@@ -195,21 +192,21 @@ void do_sdrc_init(u32 cs, u32 early)
 		writel(0, &sdrc_base->cs[cs].mcfg);
 }
 
-void enable_gpmc_config(u32 *gpmc_config, gpmc_csx_t *gpmc_cs_base, u32 base,
+void enable_gpmc_cs_config(u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
 			u32 size)
 {
-	writel(0, &gpmc_cs_base->config7);
+	writel(0, &cs->config7);
 	sdelay(1000);
 	/* Delay for settling */
-	writel(gpmc_config[0], &gpmc_cs_base->config1);
-	writel(gpmc_config[1], &gpmc_cs_base->config2);
-	writel(gpmc_config[2], &gpmc_cs_base->config3);
-	writel(gpmc_config[3], &gpmc_cs_base->config4);
-	writel(gpmc_config[4], &gpmc_cs_base->config5);
-	writel(gpmc_config[5], &gpmc_cs_base->config6);
+	writel(gpmc_config[0], &cs->config1);
+	writel(gpmc_config[1], &cs->config2);
+	writel(gpmc_config[2], &cs->config3);
+	writel(gpmc_config[3], &cs->config4);
+	writel(gpmc_config[4], &cs->config5);
+	writel(gpmc_config[5], &cs->config6);
 	/* Enable the config */
 	writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) |
-		(1 << 6)), &gpmc_cs_base->config7);
+		(1 << 6)), &cs->config7);
 	sdelay(2000);
 }
 
@@ -222,8 +219,7 @@ void gpmc_init(void)
 {
 	/* putting a blanket check on GPMC based on ZeBu for now */
 	u32 *gpmc_config = NULL;
-	gpmc_t *gpmc_base = (gpmc_t *)GPMC_BASE;
-	gpmc_csx_t *gpmc_cs_base = (gpmc_csx_t *)GPMC_CONFIG_CS0_BASE;
+	gpmc_cfg = (struct gpmc *)GPMC_BASE;
 	u32 base = 0;
 	u32 size = 0;
 	u32 f_off = CONFIG_SYS_MONITOR_LEN;
@@ -231,28 +227,26 @@ void gpmc_init(void)
 	u32 config = 0;
 
 	/* global settings */
-	writel(0, &gpmc_base->irqenable); /* isr's sources masked */
-	writel(0, &gpmc_base->timeout_control);/* timeout disable */
+	writel(0, &gpmc_cfg->irqenable); /* isr's sources masked */
+	writel(0, &gpmc_cfg->timeout_control);/* timeout disable */
 
-	config = readl(&gpmc_base->config);
+	config = readl(&gpmc_cfg->config);
 	config &= (~0xf00);
-	writel(config, &gpmc_base->config);
+	writel(config, &gpmc_cfg->config);
 
 	/*
 	 * Disable the GPMC0 config set by ROM code
 	 * It conflicts with our MPDB (both at 0x08000000)
 	 */
-	writel(0, &gpmc_cs_base->config7);
+	writel(0, &gpmc_cfg->cs[0].config7);
 	sdelay(1000);
 
 #if defined(CONFIG_CMD_NAND)	/* CS 0 */
 	gpmc_config = gpmc_m_nand;
-	gpmc_cfg_base = gpmc_base;
-	nand_cs_base = (gpmc_csx_t *)(GPMC_CONFIG_CS0_BASE +
-					(GPMC_CS * GPMC_CONFIG_WIDTH));
+
 	base = PISMO1_NAND_BASE;
 	size = PISMO1_NAND_SIZE;
-	enable_gpmc_config(gpmc_config, nand_cs_base, base, size);
+	enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
 #if defined(CONFIG_ENV_IS_IN_NAND)
 	f_off = SMNAND_ENV_OFFSET;
 	f_sec = SZ_128K;
@@ -266,11 +260,9 @@ void gpmc_init(void)
 
 #if defined(CONFIG_CMD_ONENAND)
 	gpmc_config = gpmc_onenand;
-	onenand_cs_base = (gpmc_csx_t *)(GPMC_CONFIG_CS0_BASE +
-					(GPMC_CS * GPMC_CONFIG_WIDTH));
 	base = PISMO1_ONEN_BASE;
 	size = PISMO1_ONEN_SIZE;
-	enable_gpmc_config(gpmc_config, onenand_cs_base, base, size);
+	enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
 #if defined(CONFIG_ENV_IS_IN_ONENAND)
 	f_off = ONENAND_ENV_OFFSET;
 	f_sec = SZ_128K;

cpu/arm_cortexa8/omap3/sys_info.c

@@ -32,9 +32,8 @@
 #include <i2c.h>
 
 extern omap3_sysinfo sysinfo;
-static gpmc_csx_t *gpmc_cs_base = (gpmc_csx_t *)GPMC_CONFIG_CS0_BASE;
-static sdrc_t *sdrc_base = (sdrc_t *)OMAP34XX_SDRC_BASE;
-static ctrl_t *ctrl_base = (ctrl_t *)OMAP34XX_CTRL_BASE;
+static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
+static struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
 static char *rev_s[CPU_3XX_MAX_REV] = {
 				"1.0",
 				"2.0",
@@ -47,7 +46,7 @@ static char *rev_s[CPU_3XX_MAX_REV] = {
  *****************************************************************/
 void dieid_num_r(void)
 {
-	ctrl_id_t *id_base = (ctrl_id_t *)OMAP34XX_ID_L4_IO_BASE;
+	struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
 	char *uid_s, die_id[34];
 	u32 id[4];
 
@@ -82,7 +81,7 @@ u32 get_cpu_type(void)
 u32 get_cpu_rev(void)
 {
 	u32 cpuid = 0;
-	ctrl_id_t *id_base;
+	struct ctrl_id *id_base;
 
 	/*
 	 * On ES1.0 the IDCODE register is not exposed on L4
@@ -93,7 +92,7 @@ u32 get_cpu_rev(void)
 		return CPU_3XX_ES10;
 	else {
 		/* Decode the IDs on > ES1.0 */
-		id_base = (ctrl_id_t *) OMAP34XX_ID_L4_IO_BASE;
+		id_base = (struct ctrl_id *) OMAP34XX_ID_L4_IO_BASE;
 
 		cpuid = (readl(&id_base->idcode) >> CPU_3XX_ID_SHIFT) & 0xf;
 
@@ -160,7 +159,7 @@ u32 get_gpmc0_base(void)
 {
 	u32 b;
 
-	b = readl(&gpmc_cs_base->config7);
+	b = readl(&gpmc_cfg->cs[0].config7);
 	b &= 0x1F;		/* keep base [5:0] */
 	b = b << 24;		/* ret 0x0b000000 */
 	return b;

cpu/arm_cortexa8/omap3/timer.c

@@ -37,7 +37,7 @@
 
 static ulong timestamp;
 static ulong lastinc;
-static gptimer_t *timer_base = (gptimer_t *)CONFIG_SYS_TIMERBASE;
+static struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE;
 
 /*
  * Nothing really to do with interrupts, just starts up a counter.

cpu/i386/serial.c

@@ -26,6 +26,9 @@
 /*------------------------------------------------------------------------------+ */
 
 /*
+ * This source code is dual-licensed.  You may use it under the terms of the
+ * GNU General Public License version 2, or under the license below.
+ *
  * This source code has been made available to you by IBM on an AS-IS
  * basis.  Anyone receiving this source is licensed under IBM
  * copyrights to use it in any way he or she deems fit, including

cpu/ixp/npe/miiphy.c

@@ -1,4 +1,6 @@
 /*-----------------------------------------------------------------------------+
+  |   This source code is dual-licensed.  You may use it under the terms of the
+  |   GNU General Public License version 2, or under the license below.
   |
   |	  This source code has been made available to you by IBM on an AS-IS
   |	  basis.  Anyone receiving this source is licensed under IBM

cpu/mcf5227x/Makefile

@@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk
 LIB	= lib$(CPU).a
 
 START	= start.o
-COBJS	= cpu.o speed.o cpu_init.o interrupts.o dspi.o
+COBJS	= cpu.o speed.o cpu_init.o interrupts.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))

cpu/mcf5227x/cpu_init.c

@@ -152,3 +152,56 @@ void uart_port_conf(void)
 		break;
 	}
 }
+
+#ifdef CONFIG_CF_DSPI
+void cfspi_port_conf(void)
+{
+	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+	gpio->par_dspi =
+	    GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
+	    GPIO_PAR_DSPI_SCK_SCK;
+}
+
+int cfspi_claim_bus(uint bus, uint cs)
+{
+	volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+	if ((dspi->sr & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
+		return -1;
+
+	/* Clear FIFO and resume transfer */
+	dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF);
+
+	switch (cs) {
+	case 0:
+		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_MASK;
+		gpio->par_dspi |= GPIO_PAR_DSPI_PCS0_PCS0;
+		break;
+	case 2:
+		gpio->par_timer &= GPIO_PAR_TIMER_T2IN_MASK;
+		gpio->par_timer |= GPIO_PAR_TIMER_T2IN_DSPIPCS2;
+		break;
+	}
+
+	return 0;
+}
+
+void cfspi_release_bus(uint bus, uint cs)
+{
+	volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+	dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF);	/* Clear FIFO */
+
+	switch (cs) {
+	case 0:
+		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
+		break;
+	case 2:
+		gpio->par_timer &= GPIO_PAR_TIMER_T2IN_MASK;
+		break;
+	}
+}
+#endif

cpu/mcf5227x/dspi.c

@@ -1,261 +0,0 @@
-/*
- *
- * (C) Copyright 2000-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <spi.h>
-#include <malloc.h>
-
-#if defined(CONFIG_CF_DSPI)
-#include <asm/immap.h>
-
-void dspi_init(void)
-{
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-	volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
-
-	gpio->par_dspi =
-	    GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
-	    GPIO_PAR_DSPI_SCK_SCK;
-
-	dspi->dmcr = DSPI_DMCR_MSTR | DSPI_DMCR_CSIS7 | DSPI_DMCR_CSIS6 |
-	    DSPI_DMCR_CSIS5 | DSPI_DMCR_CSIS4 | DSPI_DMCR_CSIS3 |
-	    DSPI_DMCR_CSIS2 | DSPI_DMCR_CSIS1 | DSPI_DMCR_CSIS0 |
-	    DSPI_DMCR_CRXF | DSPI_DMCR_CTXF;
-
-#ifdef CONFIG_SYS_DSPI_DCTAR0
-	dspi->dctar0 = CONFIG_SYS_DSPI_DCTAR0;
-#endif
-#ifdef CONFIG_SYS_DSPI_DCTAR1
-	dspi->dctar1 = CONFIG_SYS_DSPI_DCTAR1;
-#endif
-#ifdef CONFIG_SYS_DSPI_DCTAR2
-	dspi->dctar2 = CONFIG_SYS_DSPI_DCTAR2;
-#endif
-#ifdef CONFIG_SYS_DSPI_DCTAR3
-	dspi->dctar3 = CONFIG_SYS_DSPI_DCTAR3;
-#endif
-#ifdef CONFIG_SYS_DSPI_DCTAR4
-	dspi->dctar4 = CONFIG_SYS_DSPI_DCTAR4;
-#endif
-#ifdef CONFIG_SYS_DSPI_DCTAR5
-	dspi->dctar5 = CONFIG_SYS_DSPI_DCTAR5;
-#endif
-#ifdef CONFIG_SYS_DSPI_DCTAR6
-	dspi->dctar6 = CONFIG_SYS_DSPI_DCTAR6;
-#endif
-#ifdef CONFIG_SYS_DSPI_DCTAR7
-	dspi->dctar7 = CONFIG_SYS_DSPI_DCTAR7;
-#endif
-}
-
-void dspi_tx(int chipsel, u8 attrib, u16 data)
-{
-	volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
-
-	while ((dspi->dsr & 0x0000F000) >= 4) ;
-
-	dspi->dtfr = (attrib << 24) | ((1 << chipsel) << 16) | data;
-}
-
-u16 dspi_rx(void)
-{
-	volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
-
-	while ((dspi->dsr & 0x000000F0) == 0) ;
-
-	return (dspi->drfr & 0xFFFF);
-}
-
-#if defined(CONFIG_CMD_SPI)
-void spi_init_f(void)
-{
-}
-
-void spi_init_r(void)
-{
-}
-
-void spi_init(void)
-{
-	dspi_init();
-}
-
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
-				  unsigned int max_hz, unsigned int mode)
-{
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-	struct spi_slave *slave;
-
-	slave = malloc(sizeof(struct spi_slave));
-	if (!slave)
-		return NULL;
-
-	switch (cs) {
-	case 0:
-		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
-		gpio->par_dspi |= GPIO_PAR_DSPI_PCS0_PCS0;
-		break;
-	case 2:
-		gpio->par_timer &= GPIO_PAR_TIMER_T2IN_MASK;
-		gpio->par_timer |= GPIO_PAR_TIMER_T2IN_DSPIPCS2;
-		break;
-	}
-
-	slave->bus = bus;
-	slave->cs = cs;
-
-	return slave;
-}
-
-void spi_free_slave(struct spi_slave *slave)
-{
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
-	switch (slave->cs) {
-	case 0:
-		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
-		break;
-	case 2:
-		gpio->par_timer &= GPIO_PAR_TIMER_T2IN_MASK;
-		break;
-	}
-
-	free(slave);
-}
-
-int spi_claim_bus(struct spi_slave *slave)
-{
-	return 0;
-}
-
-void spi_release_bus(struct spi_slave *slave)
-{
-}
-
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
-	     void *din, unsigned long flags)
-{
-	static int bWrite = 0;
-	u8 *spi_rd, *spi_wr;
-	int len = bitlen >> 3;
-
-	spi_rd = (u8 *) din;
-	spi_wr = (u8 *) dout;
-
-	/* command handling */
-	if (((len == 4) || (len == 1) || (len == 5)) && (dout != NULL)) {
-		switch (*spi_wr) {
-		case 0x02:	/* Page Prog */
-			bWrite = 1;
-			dspi_tx(slave->cs, 0x80, spi_wr[0]);
-			dspi_rx();
-			dspi_tx(slave->cs, 0x80, spi_wr[1]);
-			dspi_rx();
-			dspi_tx(slave->cs, 0x80, spi_wr[2]);
-			dspi_rx();
-			dspi_tx(slave->cs, 0x80, spi_wr[3]);
-			dspi_rx();
-			return 0;
-		case 0x05:	/* Read Status */
-			if (len == 4)
-				if ((spi_wr[1] == 0xFF) && (spi_wr[2] == 0xFF)
-				    && (spi_wr[3] == 0xFF)) {
-					dspi_tx(slave->cs, 0x80, *spi_wr);
-					dspi_rx();
-				}
-			return 0;
-		case 0x06:	/* WREN */
-			dspi_tx(slave->cs, 0x00, *spi_wr);
-			dspi_rx();
-			return 0;
-		case 0x0B:	/* Fast read */
-			if ((len == 5) && (spi_wr[4] == 0)) {
-				dspi_tx(slave->cs, 0x80, spi_wr[0]);
-				dspi_rx();
-				dspi_tx(slave->cs, 0x80, spi_wr[1]);
-				dspi_rx();
-				dspi_tx(slave->cs, 0x80, spi_wr[2]);
-				dspi_rx();
-				dspi_tx(slave->cs, 0x80, spi_wr[3]);
-				dspi_rx();
-				dspi_tx(slave->cs, 0x80, spi_wr[4]);
-				dspi_rx();
-			}
-			return 0;
-		case 0x9F:	/* RDID */
-			dspi_tx(slave->cs, 0x80, *spi_wr);
-			dspi_rx();
-			return 0;
-		case 0xD8:	/* Sector erase */
-			if (len == 4)
-				if ((spi_wr[2] == 0) && (spi_wr[3] == 0)) {
-					dspi_tx(slave->cs, 0x80, spi_wr[0]);
-					dspi_rx();
-					dspi_tx(slave->cs, 0x80, spi_wr[1]);
-					dspi_rx();
-					dspi_tx(slave->cs, 0x80, spi_wr[2]);
-					dspi_rx();
-					dspi_tx(slave->cs, 0x00, spi_wr[3]);
-					dspi_rx();
-				}
-			return 0;
-		}
-	}
-
-	if (bWrite)
-		len--;
-
-	while (len--) {
-		if (dout != NULL) {
-			dspi_tx(slave->cs, 0x80, *spi_wr);
-			dspi_rx();
-			spi_wr++;
-		}
-
-		if (din != NULL) {
-			dspi_tx(slave->cs, 0x80, 0);
-			*spi_rd = dspi_rx();
-			spi_rd++;
-		}
-	}
-
-	if (flags == SPI_XFER_END) {
-		if (bWrite) {
-			dspi_tx(slave->cs, 0x00, *spi_wr);
-			dspi_rx();
-			bWrite = 0;
-		} else {
-			dspi_tx(slave->cs, 0x00, 0);
-			dspi_rx();
-		}
-	}
-
-	return 0;
-}
-#endif				/* CONFIG_CMD_SPI */
-
-#endif				/* CONFIG_CF_DSPI */

cpu/mcf52x2/config.mk

@@ -26,6 +26,7 @@
 PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
 
 cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/')
+is5208:=$(shell grep CONFIG_M5208 $(TOPDIR)/include/$(cfg))
 is5249:=$(shell grep CONFIG_M5249 $(TOPDIR)/include/$(cfg))
 is5253:=$(shell grep CONFIG_M5253 $(TOPDIR)/include/$(cfg))
 is5271:=$(shell grep CONFIG_M5271 $(TOPDIR)/include/$(cfg))
@@ -36,6 +37,9 @@ is5282:=$(shell grep CONFIG_M5282 $(TOPDIR)/include/$(cfg))
 
 ifneq ($(findstring 4.1,$(shell $(CC) --version)),4.1)
 
+ifneq (,$(findstring CONFIG_M5208,$(is5208)))
+PLATFORM_CPPFLAGS += -mcpu=5208
+endif
 ifneq (,$(findstring CONFIG_M5249,$(is5249)))
 PLATFORM_CPPFLAGS += -mcpu=5249
 endif

cpu/mcf52x2/cpu.c

@@ -34,6 +34,72 @@
 #include <asm/immap.h>
 #include <netdev.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef	CONFIG_M5208
+int do_reset(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+{
+	volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM);
+
+	udelay(1000);
+
+	rcm->rcr = RCM_RCR_SOFTRST;
+
+	/* we don't return! */
+	return 0;
+};
+
+int checkcpu(void)
+{
+	char buf1[32], buf2[32];
+
+	printf("CPU:   Freescale Coldfire MCF5208\n"
+	       "       CPU CLK %s MHz BUS CLK %s MHz\n",
+	       strmhz(buf1, gd->cpu_clk),
+	       strmhz(buf2, gd->bus_clk));
+	return 0;
+};
+
+#if defined(CONFIG_WATCHDOG)
+/* Called by macro WATCHDOG_RESET */
+void watchdog_reset(void)
+{
+	volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
+	wdt->sr = 0x5555;
+	wdt->sr = 0xAAAA;
+}
+
+int watchdog_disable(void)
+{
+	volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
+
+	wdt->sr = 0x5555; /* reset watchdog counteDECLARE_GLOBAL_DATA_PTR;
+r */
+	wdt->sr = 0xAAAA;
+	wdt->cr = 0;	/* disable watchdog timer */
+
+	puts("WATCHDOG:disabled\n");
+	return (0);
+}
+
+int watchdog_init(void)
+{
+	volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
+
+	wdt->cr = 0;	/* disable watchdog */
+
+	/* set timeout and enable watchdog */
+	wdt->mr =
+		((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1;
+	wdt->sr = 0x5555; /* reset watchdog counter */
+	wdt->sr = 0xAAAA;
+
+	puts("WATCHDOG:enabled\n");
+	return (0);
+}
+#endif				/* #ifdef CONFIG_WATCHDOG */
+#endif				/* #ifdef CONFIG_M5208 */
+
 #ifdef  CONFIG_M5271
 /*
  * Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to

cpu/mcf52x2/cpu_init.c

@@ -101,6 +101,95 @@ void init_fbcs(void)
 }
 #endif
 
+#if defined(CONFIG_M5208)
+void cpu_init_f(void)
+{
+	volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
+
+#ifndef CONFIG_WATCHDOG
+	volatile wdog_t *wdg = (wdog_t *) MMAP_WDOG;
+
+	/* Disable the watchdog if we aren't using it */
+	wdg->cr = 0;
+#endif
+
+	scm1->mpr = 0x77777777;
+	scm1->pacra = 0;
+	scm1->pacrb = 0;
+	scm1->pacrc = 0;
+	scm1->pacrd = 0;
+	scm1->pacre = 0;
+	scm1->pacrf = 0;
+
+	/* FlexBus Chipselect */
+	init_fbcs();
+
+	icache_enable();
+}
+
+/* initialize higher level parts of CPU like timers */
+int cpu_init_r(void)
+{
+	return (0);
+}
+
+void uart_port_conf(void)
+{
+	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+	/* Setup Ports: */
+	switch (CONFIG_SYS_UART_PORT) {
+	case 0:
+		gpio->par_uart &= GPIO_PAR_UART0_MASK;
+		gpio->par_uart |= (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
+		break;
+	case 1:
+		gpio->par_uart &= GPIO_PAR_UART0_MASK;
+		gpio->par_uart |= (GPIO_PAR_UART_U1TXD | GPIO_PAR_UART_U1RXD);
+		break;
+	case 2:
+#ifdef CONFIG_SYS_UART2_PRI_GPIO
+		gpio->par_timer &=
+		    (GPIO_PAR_TMR_TIN0_MASK | GPIO_PAR_TMR_TIN1_MASK);
+		gpio->par_timer |=
+		    (GPIO_PAR_TMR_TIN0_U2TXD | GPIO_PAR_TMR_TIN1_U2RXD);
+#endif
+#ifdef CONFIG_SYS_UART2_ALT1_GPIO
+		gpio->par_feci2c &=
+		    (GPIO_PAR_FECI2C_MDC_MASK | GPIO_PAR_FECI2C_MDIO_MASK);
+		gpio->par_feci2c |=
+		    (GPIO_PAR_FECI2C_MDC_U2TXD | GPIO_PAR_FECI2C_MDIO_U2RXD);
+#endif
+#ifdef CONFIG_SYS_UART2_ALT1_GPIO
+		gpio->par_feci2c &=
+		    (GPIO_PAR_FECI2C_SDA_MASK | GPIO_PAR_FECI2C_SCL_MASK);
+		gpio->par_feci2c |=
+		    (GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD);
+#endif
+		break;
+	}
+}
+
+#if defined(CONFIG_CMD_NET)
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+	if (setclear) {
+		gpio->par_fec |=
+		    GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC;
+		gpio->par_feci2c |=
+		    GPIO_PAR_FECI2C_MDC_MDC | GPIO_PAR_FECI2C_MDIO_MDIO;
+	} else {
+		gpio->par_fec &=
+		    (GPIO_PAR_FEC_7W_MASK & GPIO_PAR_FEC_MII_MASK);
+		gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII_MASK;
+	}
+	return 0;
+}
+#endif				/* CONFIG_CMD_NET */
+#endif				/* CONFIG_M5208 */
+
 #if defined(CONFIG_M5253)
 /*
  * Breath some life into the CPU...

cpu/mcf52x2/interrupts.c

@@ -59,13 +59,19 @@ void dtimer_intr_setup(void)
 #endif				/* CONFIG_MCFTMR */
 #endif				/* CONFIG_M5272 */
 
-#if defined(CONFIG_M5282) || defined(CONFIG_M5271) || defined(CONFIG_M5275)
+#if defined(CONFIG_M5208) || defined(CONFIG_M5282) || \
+    defined(CONFIG_M5271) || defined(CONFIG_M5275)
 int interrupt_init(void)
 {
 	volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
 
 	/* Make sure all interrupts are disabled */
+#if defined(CONFIG_M5208)
+	intp->imrl0 = 0xFFFFFFFF;
+	intp->imrh0 = 0xFFFFFFFF;
+#else
 	intp->imrl0 |= 0x1;
+#endif
 
 	enable_interrupts();
 	return 0;

cpu/mcf52x2/speed.c

@@ -30,11 +30,16 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-/*
- * get_clocks() fills in gd->cpu_clock and gd->bus_clk
- */
+/* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
 int get_clocks (void)
 {
+#if defined(CONFIG_M5208)
+	volatile pll_t *pll = (pll_t *) MMAP_PLL;
+
+	pll->odr = CONFIG_SYS_PLL_ODR;
+	pll->fdr = CONFIG_SYS_PLL_FDR;
+#endif
+
 #if defined(CONFIG_M5249) || defined(CONFIG_M5253)
 	volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR);
 	unsigned long pllcr;
@@ -77,7 +82,7 @@ int get_clocks (void)
 #endif
 
 	gd->cpu_clk = CONFIG_SYS_CLK;
-#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || \
+#if defined(CONFIG_M5208) || defined(CONFIG_M5249) || defined(CONFIG_M5253) || \
     defined(CONFIG_M5271) || defined(CONFIG_M5275)
 	gd->bus_clk = gd->cpu_clk / 2;
 #else

cpu/mcf52x2/start.S

@@ -120,6 +120,12 @@ _start:
 	nop
 	move.w #0x2700,%sr
 
+#if defined(CONFIG_M5208)
+	/* Initialize RAMBAR: locate SRAM and validate it */
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+	movec	%d0, %RAMBAR1
+#endif
+
 #if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5253)
 	move.l	#(CONFIG_SYS_MBAR + 1), %d0		/* set MBAR address + valid flag */
 	move.c	%d0, %MBAR
@@ -195,15 +201,6 @@ _after_flashbar_copy:
 	movec	%d0, %RAMBAR1
 #endif
 
-#if 0
-	/* invalidate and disable cache */
-	move.l	#0x01000000, %d0		/* Invalidate cache cmd */
-	movec	%d0, %CACR			/* Invalidate cache */
-	move.l	#0, %d0
-	movec	%d0, %ACR0
-	movec	%d0, %ACR1
-#endif
-
 	/* set stackpointer to end of internal ram to get some stackspace for the first c-code */
 	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
 	clr.l %sp@-
@@ -340,6 +337,24 @@ _int_handler:
 
 /*------------------------------------------------------------------------------*/
 /* cache functions */
+#ifdef	CONFIG_M5208
+	.globl	icache_enable
+icache_enable:
+	move.l	#0x01000000, %d0		/* Invalidate cache cmd */
+	movec	%d0, %CACR			/* Invalidate cache */
+	move.l	#(CONFIG_SYS_SDRAM_BASE + 0xC000), %d0	/* Setup cache mask */
+	movec	%d0, %ACR0			/* Enable cache */
+
+	move.l	#0x80000200, %d0		/* Setup cache mask */
+	movec	%d0, %CACR			/* Enable cache */
+	nop
+
+	move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
+	moveq	#1, %d0
+	move.l	%d0, (%a1)
+	rts
+#endif
+
 #ifdef	CONFIG_M5271
 	.globl	icache_enable
 icache_enable:

cpu/mcf5445x/Makefile

@@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk
 LIB	= lib$(CPU).a
 
 START	= start.o
-COBJS	= cpu.o speed.o cpu_init.o interrupts.o pci.o dspi.o
+COBJS	= cpu.o speed.o cpu_init.o interrupts.o pci.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))

cpu/mcf5445x/cpu_init.c

@@ -171,3 +171,69 @@ int fecpin_setclear(struct eth_device *dev, int setclear)
 	return 0;
 }
 #endif
+
+#ifdef CONFIG_CF_DSPI
+void cfspi_port_conf(void)
+{
+	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+	gpio->par_dspi = GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
+	    GPIO_PAR_DSPI_SCK_SCK;
+}
+
+int cfspi_claim_bus(uint bus, uint cs)
+{
+	volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+	if ((dspi->sr & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
+		return -1;
+
+	/* Clear FIFO and resume transfer */
+	dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF);
+
+	switch (cs) {
+	case 0:
+		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
+		gpio->par_dspi |= GPIO_PAR_DSPI_PCS0_PCS0;
+		break;
+	case 1:
+		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS1_PCS1;
+		gpio->par_dspi |= GPIO_PAR_DSPI_PCS1_PCS1;
+		break;
+	case 2:
+		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS2_PCS2;
+		gpio->par_dspi |= GPIO_PAR_DSPI_PCS2_PCS2;
+		break;
+	case 5:
+		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS5_PCS5;
+		gpio->par_dspi |= GPIO_PAR_DSPI_PCS5_PCS5;
+		break;
+	}
+
+	return 0;
+}
+
+void cfspi_release_bus(uint bus, uint cs)
+{
+	volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+	dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF);	/* Clear FIFO */
+
+	switch (cs) {
+	case 0:
+		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
+		break;
+	case 1:
+		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS1_PCS1;
+		break;
+	case 2:
+		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS2_PCS2;
+		break;
+	case 5:
+		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS5_PCS5;
+		break;
+	}
+}
+#endif

cpu/mcf5445x/dspi.c

@@ -1,239 +0,0 @@
-/*
- *
- * (C) Copyright 2000-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <spi.h>
-#include <malloc.h>
-
-#if defined(CONFIG_CF_DSPI)
-#include <asm/immap.h>
-
-void dspi_init(void)
-{
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-	volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
-
-	gpio->par_dspi = GPIO_PAR_DSPI_PCS5_PCS5 | GPIO_PAR_DSPI_PCS2_PCS2 |
-	    GPIO_PAR_DSPI_PCS1_PCS1 | GPIO_PAR_DSPI_PCS0_PCS0 |
-	    GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
-	    GPIO_PAR_DSPI_SCK_SCK;
-
-	dspi->dmcr = DSPI_DMCR_MSTR | DSPI_DMCR_CSIS7 | DSPI_DMCR_CSIS6 |
-	    DSPI_DMCR_CSIS5 | DSPI_DMCR_CSIS4 | DSPI_DMCR_CSIS3 |
-	    DSPI_DMCR_CSIS2 | DSPI_DMCR_CSIS1 | DSPI_DMCR_CSIS0 |
-	    DSPI_DMCR_CRXF | DSPI_DMCR_CTXF;
-
-#ifdef CONFIG_SYS_DSPI_DCTAR0
-	dspi->dctar0 = CONFIG_SYS_DSPI_DCTAR0;
-#endif
-#ifdef CONFIG_SYS_DSPI_DCTAR1
-	dspi->dctar1 = CONFIG_SYS_DSPI_DCTAR1;
-#endif
-#ifdef CONFIG_SYS_DSPI_DCTAR2
-	dspi->dctar2 = CONFIG_SYS_DSPI_DCTAR2;
-#endif
-#ifdef CONFIG_SYS_DSPI_DCTAR3
-	dspi->dctar3 = CONFIG_SYS_DSPI_DCTAR3;
-#endif
-#ifdef CONFIG_SYS_DSPI_DCTAR4
-	dspi->dctar4 = CONFIG_SYS_DSPI_DCTAR4;
-#endif
-#ifdef CONFIG_SYS_DSPI_DCTAR5
-	dspi->dctar5 = CONFIG_SYS_DSPI_DCTAR5;
-#endif
-#ifdef CONFIG_SYS_DSPI_DCTAR6
-	dspi->dctar6 = CONFIG_SYS_DSPI_DCTAR6;
-#endif
-#ifdef CONFIG_SYS_DSPI_DCTAR7
-	dspi->dctar7 = CONFIG_SYS_DSPI_DCTAR7;
-#endif
-}
-
-void dspi_tx(int chipsel, u8 attrib, u16 data)
-{
-	volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
-
-	while ((dspi->dsr & 0x0000F000) >= 4) ;
-
-	dspi->dtfr = (attrib << 24) | ((1 << chipsel) << 16) | data;
-}
-
-u16 dspi_rx(void)
-{
-	volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
-
-	while ((dspi->dsr & 0x000000F0) == 0) ;
-
-	return (dspi->drfr & 0xFFFF);
-}
-
-#if defined(CONFIG_CMD_SPI)
-void spi_init_f(void)
-{
-}
-
-void spi_init_r(void)
-{
-}
-
-void spi_init(void)
-{
-	dspi_init();
-}
-
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
-				  unsigned int max_hz, unsigned int mode)
-{
-	struct spi_slave *slave;
-
-	slave = malloc(sizeof(struct spi_slave));
-	if (!slave)
-		return NULL;
-
-	slave->bus = bus;
-	slave->cs = cs;
-
-	return slave;
-}
-
-void spi_free_slave(struct spi_slave *slave)
-{
-	free(slave);
-}
-
-int spi_claim_bus(struct spi_slave *slave)
-{
-	return 0;
-}
-
-void spi_release_bus(struct spi_slave *slave)
-{
-}
-
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
-	     void *din, unsigned long flags)
-{
-	static int bWrite = 0;
-	u8 *spi_rd, *spi_wr;
-	int len = bitlen >> 3;
-
-	spi_rd = (u8 *) din;
-	spi_wr = (u8 *) dout;
-
-	/* command handling */
-	if (((len == 4) || (len == 1) || (len == 5)) && (dout != NULL)) {
-		switch (*spi_wr) {
-		case 0x02:	/* Page Prog */
-			bWrite = 1;
-			dspi_tx(slave->cs, 0x80, spi_wr[0]);
-			dspi_rx();
-			dspi_tx(slave->cs, 0x80, spi_wr[1]);
-			dspi_rx();
-			dspi_tx(slave->cs, 0x80, spi_wr[2]);
-			dspi_rx();
-			dspi_tx(slave->cs, 0x80, spi_wr[3]);
-			dspi_rx();
-			return 0;
-		case 0x05:	/* Read Status */
-			if (len == 4)
-				if ((spi_wr[1] == 0xFF) && (spi_wr[2] == 0xFF)
-				    && (spi_wr[3] == 0xFF)) {
-					dspi_tx(slave->cs, 0x80, *spi_wr);
-					dspi_rx();
-				}
-			return 0;
-		case 0x06:	/* WREN */
-			dspi_tx(slave->cs, 0x00, *spi_wr);
-			dspi_rx();
-			return 0;
-		case 0x0B:	/* Fast read */
-			if ((len == 5) && (spi_wr[4] == 0)) {
-				dspi_tx(slave->cs, 0x80, spi_wr[0]);
-				dspi_rx();
-				dspi_tx(slave->cs, 0x80, spi_wr[1]);
-				dspi_rx();
-				dspi_tx(slave->cs, 0x80, spi_wr[2]);
-				dspi_rx();
-				dspi_tx(slave->cs, 0x80, spi_wr[3]);
-				dspi_rx();
-				dspi_tx(slave->cs, 0x80, spi_wr[4]);
-				dspi_rx();
-			}
-			return 0;
-		case 0x9F:	/* RDID */
-			dspi_tx(slave->cs, 0x80, *spi_wr);
-			dspi_rx();
-			return 0;
-		case 0xD8:	/* Sector erase */
-			if (len == 4)
-				if ((spi_wr[2] == 0) && (spi_wr[3] == 0)) {
-					dspi_tx(slave->cs, 0x80, spi_wr[0]);
-					dspi_rx();
-					dspi_tx(slave->cs, 0x80, spi_wr[1]);
-					dspi_rx();
-					dspi_tx(slave->cs, 0x80, spi_wr[2]);
-					dspi_rx();
-					dspi_tx(slave->cs, 0x00, spi_wr[3]);
-					dspi_rx();
-				}
-			return 0;
-		}
-	}
-
-	if (bWrite)
-		len--;
-
-	while (len--) {
-		if (dout != NULL) {
-			dspi_tx(slave->cs, 0x80, *spi_wr);
-			dspi_rx();
-			spi_wr++;
-		}
-
-		if (din != NULL) {
-			dspi_tx(slave->cs, 0x80, 0);
-			*spi_rd = dspi_rx();
-			spi_rd++;
-		}
-	}
-
-	if (flags == SPI_XFER_END) {
-		if (bWrite) {
-			dspi_tx(slave->cs, 0x00, *spi_wr);
-			dspi_rx();
-			bWrite = 0;
-		} else {
-			dspi_tx(slave->cs, 0x00, 0);
-			dspi_rx();
-		}
-	}
-
-	return 0;
-}
-#endif				/* CONFIG_CMD_SPI */
-
-#endif				/* CONFIG_CF_DSPI */

cpu/mcf5445x/start.S

@@ -150,8 +150,32 @@ asm_sbf_img_hdr:
 	.long	TEXT_BASE	/* image to be relocated at */
 
 asm_dram_init:
+	move.w #0x2700,%sr		/* Mask off Interrupt */
+
+	move.l	#CONFIG_SYS_INIT_RAM_ADDR, %d0
+	movec	%d0, %VBR
+
 	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
-	movec	%d0, %RAMBAR1	/* init Rambar */
+	movec	%d0, %RAMBAR1
+
+	/* initialize general use internal ram */
+	move.l #0, %d0
+	move.l #(CACR_STATUS), %a1	/* CACR */
+	move.l #(ICACHE_STATUS), %a2	/* icache */
+	move.l #(DCACHE_STATUS), %a3	/* dcache */
+	move.l %d0, (%a1)
+	move.l %d0, (%a2)
+	move.l %d0, (%a3)
+
+	/* invalidate and disable cache */
+	move.l	#0x01004100, %d0	/* Invalidate cache cmd */
+	movec	%d0, %CACR		/* Invalidate cache */
+	move.l	#0, %d0
+	movec	%d0, %ACR0
+	movec	%d0, %ACR1
+	movec	%d0, %ACR2
+	movec	%d0, %ACR3
+
 	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
 	clr.l %sp@-
 
@@ -163,10 +187,7 @@ asm_dram_init:
 	move.l	#0xFC008004, %a1
 	move.l	#(CONFIG_SYS_CS0_MASK), (%a1)
 
-	/*
-	 * Dram Initialization
-	 * a1, a2, and d0
-	 */
+	/* Dram Initialization a1, a2, and d0 */
 	/* mscr sdram */
 	move.l	#0xFC0A4074, %a1
 	move.b	#(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
@@ -209,24 +230,21 @@ dramsz_loop:
 	move.l	#0xFC0B8000, %a1	/* Mode */
 	move.l	#0xFC0B8004, %a2	/* Ctrl */
 
-#ifdef CONFIG_M54455EVB
 	/* Issue PALL */
 	move.l	#(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
 	nop
 
+#ifdef CONFIG_M54455EVB
 	/* Issue LEMR */
 	move.l	#(CONFIG_SYS_SDRAM_EMOD + 0x408), (%a1)
 	nop
 	move.l	#(CONFIG_SYS_SDRAM_MODE + 0x300), (%a1)
 	nop
-
-	move.l	#1000, %d0
-wait1000:
-	nop
-	subq.l	#1, %d0
-	bne	wait1000
 #endif
 
+	move.l	#1000, %d1
+	jsr	asm_delay
+
 	/* Issue PALL */
 	move.l	#(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
 	nop
@@ -246,25 +264,24 @@ wait1000:
 	move.l	#(CONFIG_SYS_SDRAM_MODE), (%a1)
 	nop
 	move.l	#(CONFIG_SYS_SDRAM_EMOD), (%a1)
-	nop
 #endif
 
-	move.l	#500, %d0
-wait500:
-	nop
-	subq.l	#1, %d0
-	bne	wait500
+	move.l	#500, %d1
+	jsr	asm_delay
 
-	move.l	#(CONFIG_SYS_SDRAM_CTRL), %d0
-	and.l	#0x7FFFFFFF, %d0
+	move.l	#(CONFIG_SYS_SDRAM_CTRL), %d1
+	and.l	#0x7FFFFFFF, %d1
 #ifdef CONFIG_M54455EVB
-	or.l	#0x10000c00, %d0
+	or.l	#0x10000C00, %d1
 #elif defined(CONFIG_M54451EVB)
-	or.l	#0x10000000, %d0
+	or.l	#0x10000C00, %d1
 #endif
-	move.l	%d0, (%a2)
+	move.l	%d1, (%a2)
 	nop
 
+	move.l	#2000, %d1
+	jsr	asm_delay
+
 	/*
 	 * DSPI Initialization
 	 * a0 - general, sram - 0x80008000 - 32, see M54455EVB.h
@@ -274,6 +291,7 @@ wait500:
 	 * a4 - Dst addr
 	 */
 	/* Enable pins for DSPI mode - chip-selects are enabled later */
+asm_dspi_init:
 	move.l	#0xFC0A4063, %a0
 	move.b	#0x7F, (%a0)
 
@@ -367,27 +385,29 @@ asm_dspi_rd_status:
 
 	move.b	(%a3), %d1
 	rts
+
+asm_delay:
+	nop
+	subq.l	#1, %d1
+	bne	asm_delay
+	rts
 #endif			/* CONFIG_CF_SBF */
 
 	.text
 	. = 0x400
 	.globl	_start
 _start:
+#if !defined(CONFIG_CF_SBF)
 	nop
 	nop
 	move.w #0x2700,%sr		/* Mask off Interrupt */
 
 	/* Set vector base register at the beginning of the Flash */
-#if defined(CONFIG_CF_SBF)
-	move.l	#TEXT_BASE, %d0
-	movec	%d0, %VBR
-#else
 	move.l	#CONFIG_SYS_FLASH_BASE, %d0
 	movec	%d0, %VBR
 
 	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
 	movec	%d0, %RAMBAR1
-#endif
 
 	/* initialize general use internal ram */
 	move.l #0, %d0
@@ -411,6 +431,7 @@ _start:
 	   the first c-code */
 	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
 	clr.l %sp@-
+#endif
 
 	move.l #__got_start, %a5	/* put relocation table address to a5 */
 
@@ -532,7 +553,7 @@ icache_enable:
 	move.l	#0x00040100, %d0	/* Invalidate icache */
 	movec	%d0, %CACR
 
-	move.l	#(CONFIG_SYS_SDRAM_BASE + 0x1c000), %d0	/* Setup icache */
+	move.l	#(CONFIG_SYS_SDRAM_BASE + 0xC000), %d0	/* Setup icache */
 	movec	%d0, %ACR2
 
 	move.l	#0x04088020, %d0	/* Enable bcache and icache */

cpu/mpc512x/pci.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (C) Freescale Semiconductor, Inc. 2006, 2007. All rights reserved.
+ * Copyright (C) Freescale Semiconductor, Inc. 2006, 2007.
  * Copyright (C) 2009 DENX Software Engineering <wd@denx.de>
  *
  * See file CREDITS for list of people who contributed to this

cpu/mpc512x/start.S

@@ -2,7 +2,7 @@
  * Copyright (C) 1998  Dan Malek <dmalek@jlc.net>
  * Copyright (C) 1999  Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
  * Copyright (C) 2000-2009 Wolfgang Denk <wd@denx.de>
- * Copyright Freescale Semiconductor, Inc. 2004, 2006. All rights reserved.
+ * Copyright Freescale Semiconductor, Inc. 2004, 2006.
  *
  * See file CREDITS for list of people who contributed to this
  * project.

cpu/mpc83xx/Makefile

@@ -38,8 +38,8 @@ COBJS-y += spd_sdram.o
 COBJS-y += ecc.o
 COBJS-$(CONFIG_QE) += qe_io.o
 COBJS-$(CONFIG_FSL_SERDES) += serdes.o
-COBJS-$(CONFIG_83XX_GENERIC_PCI) += pci.o
-COBJS-$(CONFIG_83XX_GENERIC_PCIE) += pcie.o
+COBJS-$(CONFIG_PCI) += pci.o
+COBJS-$(CONFIG_PCIE) += pcie.o
 COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
 
 COBJS	:= $(COBJS-y)

cpu/mpc83xx/serdes.c

@@ -1,7 +1,7 @@
 /*
  * Freescale SerDes initialization routine
  *
- * Copyright (C) 2007 Freescale Semicondutor, Inc. All rights reserved.
+ * Copyright (C) 2007 Freescale Semicondutor, Inc.
  * Copyright (C) 2008 MontaVista Software, Inc. All rights reserved.
  *
  * Author: Li Yang <leoli@freescale.com>