Prepare 2009.08

Update CHANGELOG

Signed-off-by: Wolfgang Denk <wd@denx.de>

.gitignore

@@ -27,6 +27,7 @@
 /u-boot.ldr
 /u-boot.ldr.hex
 /u-boot.ldr.srec
+/u-boot.lds
 /u-boot-onenand.bin
 /u-boot-flexonenand.bin
 

CHANGELOG

@@ -1,3 +1,820 @@
+commit 632a6dd0b612eb7b143f789f2a0273917468c041
+Author: Andre Schwarz <andre.schwarz@matrix-vision.de>
+Date:	Mon Aug 31 16:18:24 2009 +0200
+
+    Add common code dir for Matrix Vision boards.
+
+    This fixes current build failure.
+
+    Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
+
+    mvblm7.c: fix warning: implicit declaration of function
+    'mv_reset_environment'
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 52f6c34c85d6c16f2a41433b5000490ecf374992
+Author: David Brownell <dbrownell@users.sourceforge.net>
+Date:	Sun Aug 30 11:05:29 2009 -0700
+
+    bugfix CONFIG_SYS_CONSOLE_INFO_QUIET
+
+    The "console: unify printing current devices" patch goofed:
+    CONFIG_SYS_CONSOLE_INFO_QUIET is supposed to *REMOVE* boot
+    time noise, not add it.  Said patch changed the #ifndefs
+    to #ifdef; this one restores them to the proper sense.
+
+    Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
+
+commit 28887d831b02c66ccc10d7f1379204b5a62f4543
+Author: André Schwarz <andre.schwarz@matrix-vision.de>
+Date:	Thu Aug 27 14:48:35 2009 +0200
+
+    Use common code for Matrix Vision boards
+
+    Clean up existing boards (mvBC-P/MPC5200 and mvBL-M7/MPC8343) by
+    using common code.
+
+    Signed-off-by: André Schwarz <andre.schwarz@matrix-vision.de>
+
+commit 05f91a65abc3180e2896cd8ddee7a34b1d1ce6e0
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date:	Wed Aug 26 21:27:37 2009 -0500
+
+    mpc83xx: mpc8349itx - accommodate larger kernel sizes & unzero the bootdelay
+
+    apparently the ITX was missed last round.
+
+    Also make bootdelay consistent with other boards, so as to give on the
+    opportunity to fix mistakenly set bootcmd without having checked for an
+    bootdelay zero setting first.
+
+    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit cc861f7127f200e704baaf061a7f508e3c93f2a3
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date:	Wed Aug 26 21:25:46 2009 -0500
+
+    mpc83xx: match dtb filename references to their dts equivalents in the linux kernel
+
+    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 68e74567cf317318df52dbcb2ac170ffc5e7758a
+Author: Feng Kan <fkan@amcc.com>
+Date:	Fri Aug 21 10:59:42 2009 -0700
+
+    ppc4xx: Fix ECC Correction bug with SMC ordering for NDFC driver
+
+    Fix ECC Correction bug where the byte offset location were double
+    flipped causing correction routine to toggle the wrong byte location
+    in the ECC segment. The ndfc_calculate_ecc routine change the order
+    of getting the ECC code.
+	    /* The NDFC uses Smart Media (SMC) bytes order */
+	    ecc_code[0] = p[2];
+	    ecc_code[1] = p[1];
+	    ecc_code[2] = p[3];
+    But in the Correction algorithm when calculating the byte offset
+    location, the s1 is used as the upper part of the address. Which
+    again reverse the order making the final byte offset address
+    location incorrect.
+	byteoffs = (s1 << 0) & 0x80;
+	.
+	.
+	byteoffs |= (s0 >> 4) & 0x08;
+    The order is change to read it in straight and let the correction
+    function to revert it to SMC order.
+
+    Signed-off-by: Feng Kan <fkan@amcc.com>
+    Acked-by: Victor Gallardo <vgallardo@amcc.com>
+    Acked-by: Prodyut Hazarika <phazarika@amcc.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 30fc5cd3116cb112d0aab7e6d7c8eef1b67ed075
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Tue Aug 25 12:22:38 2009 +0200
+
+    include/s3c24x0.h: fix S3C24X0_SPI_CHANNEL declaration
+
+    The SPI controller on the S3C24X0 has 8 bit registers, not 32 bit.
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit e637385e69f63bc73b9dfd2ddd8d0f383790ca28
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Thu Aug 20 19:17:59 2009 -0400
+
+    Blackfin: fix typos in gpio comments
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit c2fbcb6ae86c10621a386c13be57eaa766221ed5
+Author: Harald Krapfenbauer <Harald.Krapfenbauer@bluetechnix.at>
+Date:	Tue Aug 18 04:49:57 2009 -0400
+
+    Blackfin: cm-bf527/cm-bf537: increase flash sectors
+
+    Newer revisions of these boards have slightly larger flashes, so increase
+    the configured number of sectors so that U-Boot works on all revisions.
+
+    Signed-off-by: Harald Krapfenbauer <Harald.Krapfenbauer@bluetechnix.at>
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit a794f59a75bf9fd4a44f1ad2349cae903c42b89c
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Sun Aug 23 14:14:52 2009 +0200
+
+    sh/rsk7203: add missing include net.h
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 6ac9f47977a9fc1876979871eeb14f26ba1bdbe6
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Sun Aug 23 02:47:59 2009 -0400
+
+    start a linker script helper file
+
+    Start a common header file for common linker script code (such as
+    workarounds for older linkers) rather than doing this in the build system.
+
+    As fallout, we no longer execute the linker every time config.mk is
+    included by a build file (which can easily be 70+ times), but rather only
+    execute it once.
+
+    This also fixes a bug in the major version checking by creating a macro to
+    easily compare versions and keep people from making the same common
+    mistake (forgetting to check major and minor together).
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 2ed0869d30602eb660569eababb8fedff36bd23a
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Sat Aug 22 19:50:22 2009 -0400
+
+    Blackfin: use common code to preprocess linker script
+
+    Now that the common code preprocesses the linker script, the Blackfin code
+    no longer needs to do it.
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 4d3758c835c7e96da2a291e7fb5acfc19bc06e8e
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Sat Aug 22 19:48:56 2009 -0400
+
+    .gitignore: ignore generated u-boot.lds
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 79b91de958511840d2a7491be92d435b7ef43f17
+Author: Albin Tonnerre <albin.tonnerre@free-electrons.com>
+Date:	Sat Aug 22 14:21:53 2009 +0200
+
+    include/mmc.h: Fix typo in IS_SD() macro
+
+    Signed-off-by: Albin Tonnerre <albin.tonnerre@free-electrons.com>
+
+commit 963f2f611741f8d9c38bd7caf20ae8c95cab7b3f
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Sat Aug 22 23:27:26 2009 +0200
+
+    Prepare 2009.08-rc3
+
+    Update CHANGELOG, minor Coding Style cleanup.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 5b2da6a309266f21cbb68f06fcfdf9ba141022e7
+Author: Michal Simek <monstr@monstr.eu>
+Date:	Fri Aug 21 06:52:25 2009 +1000
+
+    qemu-mips: Fix Qemu website
+
+    Signed-off-by: Michal Simek <monstr@monstr.eu>
+    Signed-off-by: Michal Simek <michal.simek@petalogix.com>
+    Acked-by: Shinya Kuribayashi <skuribay@pobox.com>
+
+commit 79f516bccc3cff5a5cd4b3dffb7d254e746fdbde
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date:	Fri Aug 21 16:34:38 2009 -0500
+
+    mpc83xx: accommodate larger kernel sizes by default
+
+    linux mpc83xx_defconfig kernels are getting bigger, accommodate for
+    their growth by adjusting default load and fdt addresses.
+
+    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 8eceeb7fd656d6d071c0a8b615e178aca5775fff
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date:	Fri Aug 21 16:33:15 2009 -0500
+
+    mpc83xx: mpc8377erdb - change DDR settings to those from latest bsp
+
+    when using Linus' 83xx_defconfig, the mpc8377rdb would hang at boot
+    at either:
+
+    NET: Registered protocol family 16
+
+    or the
+
+    io scheduler cfq registered
+
+    message.  Fixing up these DDR settings appears to fix the problem.
+
+    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 27c5248dd4c9ba4a36899689595956c5e59e349a
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date:	Fri Aug 21 16:31:20 2009 -0500
+
+    mpc83xx: tqm8349 - remove pci & flash window conflict
+
+    commit 9993e196da707a0a1cd4584f1fcef12382c1c144 "mpc83xx: convert all
+    remaining boards over to 83XX_GENERIC_PCI" remapped pci windows on
+    tqm834x to make it more consistent with the other 83xx boards.  During
+    that time however, the author failed to realize that FLASH_BASE was
+    occupying the same range as what PCI1_MEM_BASE was being assigned.
+
+    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+    Tested-by: Wolfgang Denk <wd@denx.de>
+
+commit 6d2c26ac831f033b0025cfb256365a047f8dd115
+Author: Heiko Schocher <hs@denx.de>
+Date:	Fri Aug 21 16:30:30 2009 -0500
+
+    mpc83xx: add missing CSCONFIG_ODT_WR_CFG for 832x CPUs
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 193b4cb3f641ed0fd9bb79b8fa4671882c50ffdb
+Author: Paul Gortmaker <paul.gortmaker@windriver.com>
+Date:	Fri Aug 21 16:27:05 2009 -0500
+
+    mpc83xx: mpc8349 - delete unused SYS_MID_FLASH_JUMP
+
+    This was introduced with the MPC8349EMDS board, and then copied to
+    a couple other boards by nature of being the reference implementation.
+
+      u-boot$git grep CONFIG_SYS_MID_FLASH_JUMP
+      include/configs/MPC8349EMDS.h:#define CONFIG_SYS_MID_FLASH_JUMP 0x7F000000
+      include/configs/sbc8349.h:#define CONFIG_SYS_MID_FLASH_JUMP     0x7F000000
+      include/configs/vme8349.h:#define CONFIG_SYS_MID_FLASH_JUMP     0x7F000000
+      u-boot$
+
+    It currently isn't used, so delete it before it spreads further.
+
+    Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
+    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit c0d660fbbede322648ec79d3e39389e48f5fab24
+Author: Paul Gortmaker <paul.gortmaker@windriver.com>
+Date:	Fri Aug 21 16:21:58 2009 -0500
+
+    mpc83xx: sbc8349 - make enabling PCI more user friendly
+
+    Prior to this commit, to enable PCI, you had to go manually
+    edit the board config header, which isn't really user friendly.
+    This adds the typical PCI make targets to the toplevel Makefile
+    in accordance with what is being done with other boards.
+
+    Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
+    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit a3c5057a6c05b4c7235a270486220e4511366133
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Fri Aug 7 23:37:54 2009 +0200
+
+    eeprom_m95xxx: remove unused variable i
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 8cf19b9fec92d8aa22b2fe4b4e6976743b1daa51
+Author: Ilya Yanok <yanok@emcraft.com>
+Date:	Fri Jul 17 15:02:42 2009 +0400
+
+    jffs2: some fixes to summary support
+
+    This patch fixes some issues with JFFS2 summary support in U-Boot.
+    1/ Summary support made compilation configurable (as summary support
+    considered expiremental even in Linux).
+    2/ Summary code can do unaligned 16-bit and 32-bit memory accesses.
+    We need to get data byte by byte to exclude data aborts.
+    3/ Make summary scan in two passes so we can safely fall back to full
+    scan if we found unsupported entry in the summary.
+
+    Signed-off-by: Ilya Yanok <yanok@emcraft.com>
+
+commit 11906936e168d12d684bb3d2930a62693ba3d84e
+Author: Prafulla Wadaskar <prafulla@marvell.com>
+Date:	Mon Aug 10 18:55:54 2009 +0530
+
+    arm: rd6281a: Fixed NAND specific warning
+
+    It is recommended to define the macro CONFIG_SYS_64BIT_VSPRINTF
+    for NAND specific warning removal, same is done in this patch
+
+    Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
+
+commit b5ffb193330113d2e00489d96bf8ec1f541ed4e1
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Thu Aug 13 00:37:16 2009 +0200
+
+    TRAB: make independent of specific libgcc helper routines
+
+    The TRAB board references local libgcc helper routines
+    (lib_arm/div0.o and lib_arm/_umodsi3.o) which cause build problems
+    when we try to use the normal, compiler provided libgcc instead.
+    Removing these references allows to build both with and without the
+    local libgcc helper routines.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 1aada9cd643567d351667138851e9231ccfa245a
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Mon Aug 17 14:00:53 2009 +0200
+
+    Fix all linker scripts for older binutils versions (pre-2.16)
+
+    Commit f62fb99941c6 fixed handling of all rodata sections by using a
+    wildcard combined with calls to ld's builtin functions SORT_BY_ALIGNMENT()
+    and SORT_BY_NAME().  Unfortunately these functions were only
+    introduced with biunutils version 2.16, so the modification broke
+    building with all tool chains using older binutils.
+
+    This patch makes it work again.  This is done by omitting the use of
+    these functions for such old tool chains.  This will result in
+    slightly larger target binaries, as the rodata sections are no longer
+    in optimal order alignment-wise which reauls in unused gaps, but the
+    effect was found to be insignificant - especially compared to the fact
+    that you cannot build U-Boot at all in the current state.
+
+    As ld seems to have no support for conditionals we run the linker
+    script through the C preprocessor which can be easily used to remove
+    the unwanted function calls.
+
+    Note that the C preprocessor must be run with the "-ansi" (or a
+    "-std=") option to make sure all the system-specific predefined
+    macros outside the reserved namespace are suppressed. Otherise, cpp
+    might for example substitute "powerpc" to "1", thus corrupting for
+    example "OUTPUT_ARCH(powerpc)" etc.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+    Cc: Mike Frysinger <vapier@gentoo.org>
+
+commit f772acf8a584067033eff1e231fcd1fb3a00d3d9
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Mon Aug 17 13:17:29 2009 +0200
+
+    ARM: compiler options cleanup - improve tool chain support
+
+    For some time there have been repeated reports about build problems
+    with some ARM (cross) tool chains.	Especially issues about
+    (in)compatibility with the tool chain provided runtime support
+    library libgcc.a caused to add and support a private implementation
+    of such runtime support code in U-Boot.  A closer look at the code
+    indicated that some of these issues are actually home-made.  This
+    patch attempts to clean up some of the most obvious problems and make
+    building of U-Boot with different tool chains easier:
+
+    - Even though all ARM systems basicy used the same compiler options
+      to select a specific ABI from the tool chain, the code for this was
+      distributed over all cpu/*/config.mk files.  We move this one level
+      up into lib_arm/config.mk instead.
+
+    - So far, we only checked if "-mapcs-32" was supported by the tool
+      chain; if yes, this was used, if not, "-mabi=apcs-gnu" was
+      selected, no matter if the tool chain actually understood this
+      option.  There was no support for EABI conformant tool chains.
+      This patch implements the following logic:
+
+      1) If the tool chain supports
+	"-mabi=aapcs-linux -mno-thumb-interwork"
+	 we use these options (EABI conformant tool chain).
+      2) Otherwise, we check first if
+	"-mapcs-32"
+	 is supported, and then check for
+	"-mabi=apcs-gnu"
+	 If one test succeeds, we use the first found option.
+      3) In case 2), we also test if "-mno-thumb-interwork", and use
+	 this if the test succeeds. [For "-mabi=aapcs-linux" we set
+	 "-mno-thumb-interwork" mandatorily.]
+
+      This way we use a similar logic for the compile options as the
+      Linux kernel does.
+
+    - Some EABI conformant tool chains cause external references to
+      utility functions like raise(); such functions are provided in the
+      new file lib_arm/eabi_compat.c
+
+      Note that lib_arm/config.mk gets parsed several times, so we must
+      make sure to add eabi_compat.o only once to the linker list.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+    Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+    Cc: Dirk Behme <dirk.behme@googlemail.com>
+    Cc: Magnus Lilja <lilja.magnus@gmail.com>
+    Cc: Tom Rix <Tom.Rix@windriver.com>
+    Cc: Prafulla Wadaskar <prafulla@marvell.com>
+    Acked-by: Sergey Kubushyn <ksi@koi8.net>
+    Tested-by: Magnus Lilja <lilja.magnus@gmail.com>
+    Tested-by: Andrzej Wolski <awolski@poczta.fm>
+    Tested-by: Gaye Abdoulaye Walsimou <walsimou@walsimou.com>
+    Tested-by: Tom Rix <Tom.Rix@windriver.com>
+    Tested-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 269610f6ba2e4a7bc27d2e53d43160614016964f
+Author: Mingkai Hu <Mingkai.hu@freescale.com>
+Date:	Thu Jul 30 17:56:51 2009 +0800
+
+    NAND boot: fix nand_load overlap issue
+
+    The code copy data from NAND flash block by block, so when
+    the data length isn't a whole-number multiple of the block
+    size, it will overlap the rest space.
+
+    Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
+    Signed-off-by: Scott Wood <scottwood@freescale.com>
+
+commit 1fc1d9aed08f2b3366d634fda6712a710b2cff9a
+Author: Giulio Benetti <giulio.benetti@micronovasrl.com>
+Date:	Fri Jul 31 17:30:34 2009 -0500
+
+    add WATCHDOG_RESET() on nand write and read
+
+    Signed-off-by: giulio.benetti@micronovasrl.com
+    Acked-by: Wolfgang Denk <wd@denx.de>
+    Signed-off-by: Scott Wood <scottwood@freescale.com>
+
+commit b1e849f2201bbbf3ca81fde164f154f9caf7f0e9
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date:	Wed Feb 4 15:14:05 2009 -0600
+
+    tsec: Wait for auto-negotiation to complete without link
+
+    Previously, waiting for auto-negotiation would only occur if a valid
+    link had been detected.  Problems arose when attempting to use a
+    tsec immediately after bootup but before link was achieved, eg:
+    => dhcp
+    Auto-neg error, defaulting to 10BT/HD
+    eTSEC1: No link.
+    Auto-neg error, defaulting to 10BT/HD
+    eTSEC2: No link.
+    =>
+
+    With this patch applied the same operation as above resulted in:
+    => dhcp
+    Waiting for PHY auto negotiation to complete. done
+    Enet starting in 1000BT/FD
+    Speed: 1000, full duplex
+
+    Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 477fa6378fbd3e47a5e2e83d0dd3970d5b1c8371
+Author: Simon Kagstrom <simon.kagstrom@netinsight.net>
+Date:	Thu Aug 20 10:14:11 2009 +0200
+
+    arm: kirkwood: See to it that sent data is 8-byte aligned
+
+    U-boot might use non-8-byte-aligned addresses for sending data, which
+    the kwgbe_send doesn't accept (bootp does this for me). This patch
+    copies the data to be sent to a malloced temporary buffer if it is
+    non-aligned.
+
+    Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit cad713bf7548b9e90433dac8270165402a6c9cc3
+Author: Simon Kagstrom <simon.kagstrom@netinsight.net>
+Date:	Thu Aug 20 10:13:06 2009 +0200
+
+    Wait for the link to come up on kirkwood network init
+
+    This patch makes the device wait for up to 5 seconds for the link to
+    come up, similar to what many of the other network drivers do. This
+    avoids confusing situations where, e.g., a tftp fails when initiated
+    early after U-boot has started (before the link has come up).
+
+    Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit bb1ca3b27f7fba8c73cb10279a6a8b8b69a308ff
+Author: Simon Kagstrom <simon.kagstrom@netinsight.net>
+Date:	Thu Aug 20 10:12:28 2009 +0200
+
+    arm:kirkwood Define kirkwood phy address magic number
+
+    Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit f81ecb5d3300bf92d17302d3712f30585c182da9
+Author: Timur Tabi <timur@freescale.com>
+Date:	Mon Aug 17 15:55:38 2009 -0500
+
+    e1000: fix PCI memory addressing
+
+    The Intel E1000 driver was making assumptions about the relationship between
+    some virtual, physical, and PCI addresses.
+
+    Also fix some bad usage of the DEBUGOUT macro
+
+    Signed-off-by: Timur Tabi <timur@freescale.com>
+    Acked-by: Kumar Gala <galak@kernel.crashing.org>
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit b644006e1a7baa227aedc606ecdf0bb5eeb24cab
+Author: Ilya Yanok <yanok@emcraft.com>
+Date:	Wed Aug 12 16:42:48 2009 +0400
+
+    jffs2: clean the cache in case of malloc fails in build_lists
+
+    We should call jffs2_clean_cache() if we return from jffs2_build_lists()
+    with an error to prevent usage of incomplete lists. Also we should
+    free() a local buffer to prevent memory leaks.
+
+    Signed-off-by: Ilya Yanok <yanok@emcraft.com>
+
+commit 7ff66bb0be80cadd681be22a72e5eb02ee14c878
+Author: Heiko Schocher <hs@denx.de>
+Date:	Wed Aug 12 10:17:03 2009 +0200
+
+    ppc: trigger WDT before starting Linux
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit 918319c705d8a3d6251919a660baef32ff3a829a
+Author: Albin Tonnerre <albin.tonnerre@free-electrons.com>
+Date:	Wed Jul 22 18:30:03 2009 +0200
+
+    Update the mtd driver name in bootargs for at91-based boards
+
+    The name of the atmel nand driver in the kernel changed from at91_nand
+    to atmel_nand back in June 2008, but the at91-based boards config files
+    still refer to at91_nand. This patch updates them with the new name
+
+    Signed-off-by: Albin Tonnerre <albin.tonnerre@free-electrons.com>
+
+commit 8fa656aa5289815d942ebdc26182ccb9f2b9c86f
+Author: Ben Goska <goskab@onid.oregonstate.edu>
+Date:	Fri Aug 14 10:03:36 2009 -0700
+
+    omap3: Fixed a problem with hwecc
+
+    In commit 187af954cf7958c24efcf0fd62289bbdb4f1f24e there
+    was a typo that offset all the ecc registers by 4 bytes, fixed that.
+
+    Signed-off-by: Ben Goska <goskab@onid.oregonstate.edu>
+    Acked-by: Dirk Behme <dirk.behme@googlemail.com>
+
+commit 514bab6609acd1a2a19fdd75c2f6255178db7c96
+Author: Stefan Roese <sr@denx.de>
+Date:	Mon Aug 17 16:57:53 2009 +0200
+
+    ppc4xx: Fix "chip_config" command for AMCC Arches
+
+    This patch fixes the "chip_config" command for I2C bootstrap EEPROM
+    configuration. First it changes the I2C bootstrap EEPROM address to
+    0x54 as this is used on Arches (instead of 0x52 on Canyonlands/
+    Glacier). Additionally, the NAND bootstrap settings are removed
+    for Arches since Arches doesn't support NAND-booting.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 4af34177b657e91263919a307fd0b0865a299e52
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Sun Aug 16 23:40:13 2009 +0200
+
+    Monahans: avoid floating point calculations
+
+    Current code for the Monahans CPU defined OSCR_CLK_FREQ as 3.250 (MHz)
+    which caused floating point operations to be used. This resulted in
+    unresolved references to some FP related libgcc functions when using
+    U-Boot's private libgcc functions.
+
+    Change the code to use fixed point math only.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit e393e2e9bc5cd3d5484e193d1380e7cd7587ab5c
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Fri Aug 14 16:43:22 2009 -0500
+
+    85xx: Fix addrmap to include memory
+
+    When we init the addrmap based on the TLB we will not end up getting
+    the TLB that covers memory if we are using SPD.  The reason is we
+    haven't relocated at the point that we setup the memory TLB and thus it
+    will not get setup in the addrmap.
+
+    Instead we can just walk over the TLB array after we've relocated and
+    see all the TLBs that have been set and use that information to populate
+    the initial addrmap.  By doing this we insure that we get the TLB
+    entries that cover memory.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 7dedefdf749ff02c1086f7ddb8cb83a77b00d030
+Author: John Schmoller <jschmoller@xes-inc.com>
+Date:	Wed Aug 12 10:55:47 2009 -0500
+
+    flash: Fix CFI buffer size bug
+
+    Fix bug introduced by 9c048b523413ae5f3ff34e00cf57569c3368ab51.
+
+    The cfi_flash.c driver cast the flash buffer size to a uchar in
+    flash_write_cfibuffer(). On some flash parts, (tested on Numonyx
+    part PC32F512M29EWH), the buffer size is 1KB. Remove the cast to
+    uchar to enable buffer sizes to be larger.
+
+    Signed-off-by: John Schmoller <jschmoller@xes-inc.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit f6e3a1fa92f61083885178101e973c86b419a6f7
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Thu Aug 13 00:32:14 2009 -0400
+
+    trab: rename spi_init()
+
+    The local board-specific spi_init() function conflicts with the common SPI
+    layer, so rename it to something board-specific.
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 253cb831f5861358a7fa673305cdf7ded1096f44
+Author: Giuseppe CONDORELLI <giuseppe.condorelli@st.com>
+Date:	Wed Jul 29 06:05:20 2009 -0400
+
+    zlib: add watchdog reset call
+
+    This patch adds watchdog reset call to allow its invokation during decompression
+    phase. This control was present on old zlib version and here it is
+    backported for those relevant routines. This patch is sent as a zlib separate
+    one beacuse it was not tested due to specific board lack.
+    zlib patches will be unified just in one when this will be validated through
+    tests.
+
+    Signed-off-by: Giuseppe Condorelli <giuseppe.condorelli@st.com>
+
+commit dce3d797102b6618e8bdd4a09cfd35969f165d86
+Author: Giuseppe CONDORELLI <giuseppe.condorelli@st.com>
+Date:	Wed Jul 29 08:05:08 2009 -0400
+
+    zlib: updated to v.1.2.3
+
+    This patch updates zlib to the latest stable version.
+    Only relevant zlib parts were ported to u-boot tree, as already did for the
+    current zlib (0.95). New zlib guarantees a faster inflate performances
+    other then others improvements as explained at www.zlib.net.
+    It also includes Alessandro Rubini's patches to allow 0 as destination pointer
+    and to call watchdog reset if required by architecture.
+
+    Signed-off-by: Giuseppe Condorelli <giuseppe.condorelli@st.com>
+    Reviewed-by: Angelo Castello <angelo.castello@st.com>
+    Reviewed-by: Alessandro Rubini <rubini-list@gnudd.com>
+
+commit 3426d65daab6af483b177ed502038f52ed2e5aef
+Author: Heiko Schocher <hs@denx.de>
+Date:	Tue Aug 11 10:37:58 2009 +0200
+
+    dtt, lm81: move unneccessary printf into a debug printf
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit 54e399f110bbaa24e662e6dd9e88ddb86989d668
+Author: Mark Jackson <mpfj-list@mimc.co.uk>
+Date:	Tue Aug 11 11:33:47 2009 +0100
+
+    MIMC200: reduce LCD pixclock
+
+    The initial pixclock for the MIMC200 board is wrong (and causes
+    screen corruption due to DMA underruns).
+
+    This patch simply reduces the pixel clock to fix the problem.
+
+    Signed-off-by: Mark Jackson <mpfj@mimc.co.uk>
+
+commit 1443cd7e54d6893ab7cc51d93fe7759cdaa8b31f
+Author: Richard Retanubun <RichardRetanubun@RuggedCom.com>
+Date:	Wed Jul 1 14:04:05 2009 -0400
+
+    UEC FIXED PHY: Determine fixed-phy port using UEC interface name.
+
+    Fixed a misunderstanding in the original implementation, 'devnum' that
+    was used in the cpu/ppc4xx/4xx_enet.c implementation was NOT the
+    PHY's SMI address, rather it was the number of the MAC interface on
+    the CPU. The equivalent of this for uec_phy will be the UEC number
+    stored in mii_info->dev->name. Usage example is updated for uec.
+
+    Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 1a9519373b977ef3f7c9563ad3acb6c6f2424657
+Author: Richard Retanubun <RichardRetanubun@RuggedCom.com>
+Date:	Wed Jul 1 14:03:15 2009 -0400
+
+    Assigned a static SMI address to all UECs TBIPA address.
+
+    It is set to 0x1F by default and can be overwritten on the board
+    header file by defining CONFIG_UTBIPAR_INIT_TBIPA. This allows
+    the CPU to simply "reserve" one SMI address instead of using
+    a different one for each UEC.
+
+    Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 9fd38a01cbc0ce4a8db41f72677103ed04b23db5
+Author: Prafulla Wadaskar <prafulla@marvell.com>
+Date:	Mon Aug 10 19:43:06 2009 +0530
+
+    net: kirkwood: updates: used eth_setenv_enetaddr api
+
+    eth_setenv_enetaddr is avaible by upper layer
+    using this saves 204 bytes on total image size
+
+    used Local OUI instead of Marvell OUI for
+    random MAC address generation logic
+
+    Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit ecbd2078a1f56c85b6c56afaaed862bf92ccd3f3
+Author: Roy Zang <tie-fei.zang@freescale.com>
+Date:	Tue Aug 11 03:48:05 2009 +0800
+
+    Fix E1000 build warning on AP1000 board
+
+     Fix E1000 build warning on AP1000 board
+     Fix the build warning on AP1000 board:
+     e1000.c:131: warning: 'e1000_read_eeprom' used but never defined
+     e1000.c:2012: warning: 'e1000_set_phy_mode' defined but not used
+
+    Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit b3af1d698b031e721bacaee8715d79daaf823de6
+Author: Sandeep Paulraj <s-paulraj@ti.com>
+Date:	Mon Aug 10 12:24:40 2009 -0400
+
+    ARM: Davinci DM355: Enabling DM9000 on DM355 EVM
+
+    Due to recent changes to the NET support on U-boot, DM9000
+    is no longer detected on the DM355 EVM.
+    This minor update enables DM9000 on the DM355 EVM.
+    Tested on the DM355 EVM
+
+    Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 08c2df33f1cd5935938486e968696f94ad406313
+Author: Prafulla Wadaskar <prafulla@marvell.com>
+Date:	Mon Aug 10 19:23:19 2009 +0530
+
+    net: phy: bugfixes: mv88E61xx compiler warnings fixed
+
+    1. mv88E61xx driver compiler warnings fixed
+    2. idstr if-else statements changed to switch() construct
+       and added default case too.
+       This fixed idstr may be uninitialized warning
+
+    Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 750326e5d540885e3ec36bda9464b8269249f6ce
+Author: Po-Yu Chuang <ratbert@faraday-tech.com>
+Date:	Mon Aug 10 11:00:00 2009 +0800
+
+    arm: A320: driver for FTMAC100 ethernet controller
+
+    This patch adds an FTMAC100 ethernet driver for Faraday A320 evaluation board.
+
+    Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com>
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit f90dc43fd67eea71124b999a7d5e617d0d86795b
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Mon Aug 10 16:40:55 2009 -0500
+
+    85xx: Removed BEDBUG support from FSL 85xx boards
+
+    For some reason the MPC8544 enabled BEDBUG if PCI was enabled and that
+    got copied int the MPC8536, MPC8572 and P2020 DS boards.  The BEDBUG
+    support has never been made to work completely on e500/85xx so we
+    just disable it to save space and match the other FSL 85xx boards.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit eb1a4d0a471505c169bef19a73a60f8641f0b875
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Mon Aug 10 10:39:12 2009 +0200
+
+    Prepare 2009.08-rc2
+
+    Update CHANGELOG
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
 commit 53cc18c71b2b920cca171874c6663e274fa80556
 Author: Wolfgang Denk <wd@denx.de>
 Date:	Mon Aug 10 10:38:34 2009 +0200
@@ -527,6 +1344,19 @@ Date:	Tue Jul 28 10:50:32 2009 +0200
 
     Signed-off-by: Stefan Roese <sr@denx.de>
 
+commit 901be89a27e11b2627c132ee87c7761bd6886091
+Author: Heiko Schocher <hs@denx.de>
+Date:	Tue Jul 28 14:53:44 2009 +0200
+
+    83xx, kmeter1, fix: update in the DTS the correct size for the first flash
+
+    When updating the "reg" in the "/localbus/flash@f0000000,0" node
+    size was wrong updated for the first flash, because the total
+    size was filled in, instead of the right size for it.
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
 commit 4c2e3da82dc2b7f8b39b7f1d57f570e4bc5caa6d
 Author: Kumar Gala <kumar.gala@freescale.com>
 Date:	Tue Jul 28 21:49:52 2009 -0500

Makefile

@@ -24,7 +24,7 @@
 VERSION = 2009
 PATCHLEVEL = 08
 SUBLEVEL =
-EXTRAVERSION = -rc2
+EXTRAVERSION =
 ifneq "$(SUBLEVEL)" ""
 U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
 else
@@ -267,6 +267,14 @@ endif
 PLATFORM_LIBS += $(PLATFORM_LIBGCC)
 export PLATFORM_LIBS
 
+# Special flags for CPP when processing the linker script.
+# Pass the version down so we can handle backwards compatibility
+# on the fly.
+LDPPFLAGS += \
+	-include $(TOPDIR)/include/u-boot/u-boot.lds.h \
+	$(shell $(LD) --version | \
+	  sed -ne 's/GNU ld version \([0-9][0-9]*\)\.\([0-9][0-9]*\).*/-DLD_MAJOR=\1 -DLD_MINOR=\2/p')
+
 ifeq ($(CONFIG_NAND_U_BOOT),y)
 NAND_SPL = nand_spl
 U_BOOT_NAND = $(obj)u-boot-nand.bin
@@ -326,11 +334,13 @@ GEN_UBOOT = \
 		cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
 			--start-group $(__LIBS) --end-group $(PLATFORM_LIBS) \
 			-Map u-boot.map -o u-boot
-$(obj)u-boot:		depend $(SUBDIRS) $(OBJS) $(LIBBOARD) $(LIBS) $(LDSCRIPT)
+$(obj)u-boot:	depend $(SUBDIRS) $(OBJS) $(LIBBOARD) $(LIBS) $(LDSCRIPT) $(obj)u-boot.lds
 		$(GEN_UBOOT)
 ifeq ($(CONFIG_KALLSYMS),y)
-		smap=`$(call SYSTEM_MAP,u-boot) | awk '$$2 ~ /[tTwW]/ {printf $$1 $$3 "\\\\000"}'` ; \
-		$(CC) $(CFLAGS) -DSYSTEM_MAP="\"$${smap}\"" -c common/system_map.c -o $(obj)common/system_map.o
+		smap=`$(call SYSTEM_MAP,u-boot) | \
+			awk '$$2 ~ /[tTwW]/ {printf $$1 $$3 "\\\\000"}'` ; \
+		$(CC) $(CFLAGS) -DSYSTEM_MAP="\"$${smap}\"" \
+			-c common/system_map.c -o $(obj)common/system_map.o
 		$(GEN_UBOOT) $(obj)common/system_map.o
 endif
 
@@ -349,6 +359,9 @@ $(SUBDIRS):	depend
 $(LDSCRIPT):	depend
 		$(MAKE) -C $(dir $@) $(notdir $@)
 
+$(obj)u-boot.lds: $(LDSCRIPT)
+		$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
+
 $(NAND_SPL):	$(TIMESTAMP_FILE) $(VERSION_FILE) $(obj)include/autoconf.mk
 		$(MAKE) -C nand_spl/board/$(BOARDDIR) all
 
@@ -2375,8 +2388,23 @@ MPC837XERDB_config:	unconfig
 MVBLM7_config: unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc83xx mvblm7 matrix_vision
 
-sbc8349_config:		unconfig
-	@$(MKCONFIG) $(@:_config=) ppc mpc83xx sbc8349
+sbc8349_config \
+sbc8349_PCI_33_config \
+sbc8349_PCI_66_config: unconfig
+	@mkdir -p $(obj)include
+	@if [ "$(findstring _PCI_,$@)" ] ; then \
+		$(XECHO) -n "... PCI HOST at " ; \
+		echo "#define CONFIG_PCI" >>$(obj)include/config.h ; \
+	fi ; \
+	if [ "$(findstring _33_,$@)" ] ; then \
+		$(XECHO) -n "33MHz... " ; \
+		echo "#define PCI_33M" >>$(obj)include/config.h ; \
+	fi ; \
+	if [ "$(findstring _66_,$@)" ] ; then \
+		$(XECHO) -n "66MHz... " ; \
+		echo "#define PCI_66M" >>$(obj)include/config.h ; \
+	fi ;
+	@$(MKCONFIG) -a sbc8349 ppc mpc83xx sbc8349
 
 SIMPC8313_LP_config \
 SIMPC8313_SP_config: unconfig
@@ -3653,10 +3681,12 @@ clean:
 	       $(obj)board/trab/trab_fkt   $(obj)board/voiceblue/eeprom   \
 	       $(obj)board/armltd/{integratorap,integratorcp}/u-boot.lds  \
 	       $(obj)lib_blackfin/u-boot.lds				  \
+	       $(obj)u-boot.lds						  \
 	       $(obj)cpu/blackfin/bootrom-asm-offsets.[chs]
 	@rm -f $(obj)include/bmp_logo.h
-	@rm -f $(obj)nand_spl/{u-boot-spl,u-boot-spl.map,System.map}
+	@rm -f $(obj)nand_spl/{u-boot.lds,u-boot-spl,u-boot-spl.map,System.map}
 	@rm -f $(obj)onenand_ipl/onenand-{ipl,ipl.bin,ipl-2k.bin,ipl-4k.bin,ipl.map}
+	@rm -f $(obj)onenand_ipl/u-boot.lds
 	@rm -f $(TIMESTAMP_FILE) $(VERSION_FILE)
 	@find $(OBJTREE) -type f \
 		\( -name 'core' -o -name '*.bak' -o -name '*~' \

board/amcc/canyonlands/chip_config.c

@@ -33,13 +33,6 @@ struct ppc4xx_config ppc4xx_config_val[] = {
 			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
 		}
 	},
-	{
-		"600-nand", "NAND CPU: 600 PLB: 200 OPB: 100 EBC: 100",
-		{
-			0x86, 0x80, 0xce, 0x1f, 0x79, 0x90, 0x01, 0xa0,
-			0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
-		}
-	},
 	{
 		"800-nor", "NOR  CPU: 800 PLB: 200 OPB: 100 EBC: 100",
 		{
@@ -47,13 +40,6 @@ struct ppc4xx_config ppc4xx_config_val[] = {
 			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
 		}
 	},
-	{
-		"800-nand", "NAND CPU: 800 PLB: 200 OPB: 100 EBC: 100",
-		{
-			0x86, 0x80, 0xba, 0x14, 0x99, 0x90, 0x01, 0xa0,
-			0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
-		}
-	},
 	{
 		"1000-nor", "NOR  CPU:1000 PLB: 200 OPB: 100 EBC: 100",
 		{
@@ -61,13 +47,6 @@ struct ppc4xx_config ppc4xx_config_val[] = {
 			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
 		}
 	},
-	{
-		"1000-nand", "NAND CPU:1000 PLB: 200 OPB: 100 EBC: 100",
-		{
-			0x86, 0x82, 0x96, 0x19, 0xb9, 0x90, 0x01, 0xa0,
-			0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
-		}
-	},
 	{
 		"1066-nor", "NOR  CPU:1066 PLB: 266 OPB:  88 EBC:  88",
 		{
@@ -75,6 +54,28 @@ struct ppc4xx_config ppc4xx_config_val[] = {
 			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
 		}
 	},
+#if !defined(CONFIG_ARCHES)
+	{
+		"600-nand", "NAND CPU: 600 PLB: 200 OPB: 100 EBC: 100",
+		{
+			0x86, 0x80, 0xce, 0x1f, 0x79, 0x90, 0x01, 0xa0,
+			0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"800-nand", "NAND CPU: 800 PLB: 200 OPB: 100 EBC: 100",
+		{
+			0x86, 0x80, 0xba, 0x14, 0x99, 0x90, 0x01, 0xa0,
+			0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"1000-nand", "NAND CPU:1000 PLB: 200 OPB: 100 EBC: 100",
+		{
+			0x86, 0x82, 0x96, 0x19, 0xb9, 0x90, 0x01, 0xa0,
+			0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
 	{
 		"1066-nand", "NAND CPU:1066 PLB: 266 OPB:  88 EBC:  88",
 		{
@@ -82,6 +83,7 @@ struct ppc4xx_config ppc4xx_config_val[] = {
 			0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
 		}
 	},
+#endif
 };
 
 int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);

board/cm-bf527/gpio_cfi_flash.c

@@ -51,9 +51,9 @@ u##size flash_read##size(void *addr) \
 	return __raw_read##sfx(gpio_cfi_flash_swizzle(addr)); \
 }
 MAKE_FLASH(8, b)  /* flash_write8()  flash_read8() */
-MAKE_FLASH(16, w) /* flash_write16() flash_write16() */
-MAKE_FLASH(32, l) /* flash_write32() flash_write32() */
-MAKE_FLASH(64, q) /* flash_write64() flash_write64() */
+MAKE_FLASH(16, w) /* flash_write16() flash_read16() */
+MAKE_FLASH(32, l) /* flash_write32() flash_read32() */
+MAKE_FLASH(64, q) /* flash_write64() flash_read64() */
 
 void gpio_cfi_flash_init(void)
 {

board/cm-bf537e/gpio_cfi_flash.c

@@ -49,9 +49,9 @@ u##size flash_read##size(void *addr) \
 	return __raw_read##sfx(gpio_cfi_flash_swizzle(addr)); \
 }
 MAKE_FLASH(8, b)  /* flash_write8()  flash_read8() */
-MAKE_FLASH(16, w) /* flash_write16() flash_write16() */
-MAKE_FLASH(32, l) /* flash_write32() flash_write32() */
-MAKE_FLASH(64, q) /* flash_write64() flash_write64() */
+MAKE_FLASH(16, w) /* flash_write16() flash_read16() */
+MAKE_FLASH(32, l) /* flash_write32() flash_read32() */
+MAKE_FLASH(64, q) /* flash_write64() flash_read64() */
 
 void gpio_cfi_flash_init(void)
 {

board/davinci/dm355evm/dm355evm.c

@@ -23,7 +23,8 @@
 #include <asm/arch/emif_defs.h>
 #include <asm/arch/nand_defs.h>
 #include "../common/misc.h"
-
+#include <net.h>
+#include <netdev.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -79,6 +80,13 @@ int board_init(void)
 	return 0;
 }
 
+#ifdef CONFIG_DRIVER_DM9000
+int board_eth_init(bd_t *bis)
+{
+	return dm9000_initialize(bis);
+}
+#endif
+
 #ifdef CONFIG_NAND_DAVINCI
 
 static void nand_dm355evm_select_chip(struct mtd_info *mtd, int chip)

board/delta/nand.c

@@ -193,7 +193,7 @@ static unsigned long get_delta(unsigned long start)
 static void wait_us(unsigned long us)
 {
 	unsigned long start = OSCR;
-	us *= OSCR_CLK_FREQ;
+	us = DIV_ROUND_UP(us * OSCR_CLK_FREQ, 1000);
 
 	while (get_delta(start) < us) {
 		/* do nothing */
@@ -214,9 +214,11 @@ static unsigned long dfc_wait_event(unsigned long event)
 	if(!event)
 		return 0xff000000;
 	else if(event & (NDSR_CS0_CMDD | NDSR_CS0_BBD))
-		timeout = CONFIG_SYS_NAND_PROG_ERASE_TO * OSCR_CLK_FREQ;
+		timeout = DIV_ROUND_UP(CONFIG_SYS_NAND_PROG_ERASE_TO
+					* OSCR_CLK_FREQ, 1000);
 	else
-		timeout = CONFIG_SYS_NAND_OTHER_TO * OSCR_CLK_FREQ;
+		timeout = DIV_ROUND_UP(CONFIG_SYS_NAND_OTHER_TO
+					* OSCR_CLK_FREQ, 1000);
 
 	while(1) {
 		ndsr = NDSR;

board/keymile/kmeter1/kmeter1.c

@@ -228,6 +228,7 @@ void ft_blob_update (void *blob, bd_t *bd)
 				len);
 
 	info = flash_get_info(CONFIG_SYS_FLASH_BASE);
+	size = info->size;
 	flash_reg[2] = cpu_to_be32 (size);
 	flash_reg[4] = flash_reg[2];
 	info = flash_get_info(CONFIG_SYS_FLASH_BASE_1);

board/matrix_vision/common/Makefile

@@ -0,0 +1,54 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)board/$(VENDOR)/common)
+endif
+
+LIB	= $(obj)lib$(VENDOR).a
+
+COBJS-y	= mv_common.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/matrix_vision/common/mv_common.c

@@ -0,0 +1,126 @@
+/*
+ * (C) Copyright 2008
+ * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <environment.h>
+#include <fpga.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static char* entries_to_keep[] = {
+	"serial#", "ethaddr", "eth1addr", "model_info", "sensor_cnt",
+	"fpgadatasize", "ddr_size", "use_dhcp", "use_static_ipaddr",
+	"static_ipaddr", "static_netmask", "static_gateway",
+	"syslog", "watchdog", "netboot", "evo8serialnumber" };
+
+#define MV_MAX_ENV_ENTRY_LENGTH	64
+#define MV_KEEP_ENTRIES		ARRAY_SIZE(entries_to_keep)
+
+void mv_reset_environment(void)
+{
+	int i;
+	char *s[MV_KEEP_ENTRIES];
+	char entries[MV_KEEP_ENTRIES][MV_MAX_ENV_ENTRY_LENGTH];
+
+	printf("\n*** RESET ENVIRONMENT ***\n");
+
+	memset(entries, 0, MV_KEEP_ENTRIES * MV_MAX_ENV_ENTRY_LENGTH);
+	for (i = 0; i < MV_KEEP_ENTRIES; i++) {
+		s[i] = getenv(entries_to_keep[i]);
+		if (s[i]) {
+			printf("save '%s' : %s\n", entries_to_keep[i], s[i]);
+			strncpy(entries[i], s[i], MV_MAX_ENV_ENTRY_LENGTH);
+		}
+	}
+
+	gd->env_valid = 0;
+	env_relocate();
+
+	for (i = 0; i < MV_KEEP_ENTRIES; i++) {
+		if (s[i]) {
+			printf("restore '%s' : %s\n", entries_to_keep[i], s[i]);
+			setenv(entries_to_keep[i], s[i]);
+		}
+	}
+
+	saveenv();
+}
+
+int mv_load_fpga(void)
+{
+	int result;
+	size_t data_size = 0;
+	void *fpga_data = NULL;
+	char *datastr = getenv("fpgadata");
+	char *sizestr = getenv("fpgadatasize");
+
+	if (getenv("skip_fpga")) {
+		printf("found 'skip_fpga' -> FPGA _not_ loaded !\n");
+		return -1;
+	}
+	printf("loading FPGA\n");
+
+	if (datastr)
+		fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
+	if (sizestr)
+		data_size = (size_t)simple_strtoul(sizestr, NULL, 16);
+	if (!data_size) {
+		printf("fpgadatasize invalid -> FPGA _not_ loaded !\n");
+		return -1;
+	}
+
+	result = fpga_load(0, fpga_data, data_size);
+	if (!result)
+		show_boot_progress(0);
+
+	return result;
+}
+
+u8 *dhcp_vendorex_prep(u8 *e)
+{
+	char *ptr;
+
+	/* DHCP vendor-class-identifier = 60 */
+	if ((ptr = getenv("dhcp_vendor-class-identifier"))) {
+		*e++ = 60;
+		*e++ = strlen(ptr);
+		while (*ptr)
+			*e++ = *ptr++;
+	}
+	/* DHCP_CLIENT_IDENTIFIER = 61 */
+	if ((ptr = getenv("dhcp_client_id"))) {
+		*e++ = 61;
+		*e++ = strlen(ptr);
+		while (*ptr)
+			*e++ = *ptr++;
+	}
+
+	return e;
+}
+
+u8 *dhcp_vendorex_proc(u8 *popt)
+{
+	return NULL;
+}

board/matrix_vision/common/mv_common.h

@@ -0,0 +1,25 @@
+/*
+ * Copyright 2008 Matrix Vision GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+extern int mv_load_fpga(void);
+extern void mv_reset_environment(void);

board/matrix_vision/mvbc_p/mvbc_p.c

@@ -39,6 +39,7 @@
 #include <asm/io.h>
 #include "fpga.h"
 #include "mvbc_p.h"
+#include "../common/mv_common.h"
 
 #define SDRAM_MODE	0x00CD0000
 #define SDRAM_CONTROL	0x504F0000
@@ -134,23 +135,6 @@ void mvbc_init_gpio(void)
 	printf("sint_gpioe  : 0x%08x\n", gpio->sint_gpioe);
 }
 
-void reset_environment(void)
-{
-	char *s, sernr[64];
-
-	printf("\n*** RESET ENVIRONMENT ***\n");
-	memset(sernr, 0, sizeof(sernr));
-	s = getenv("serial#");
-	if (s) {
-		printf("found serial# : %s\n", s);
-		strncpy(sernr, s, 64);
-	}
-	gd->env_valid = 0;
-	env_relocate();
-	if (s)
-		setenv("serial#", sernr);
-}
-
 int misc_init_r(void)
 {
 	char *s = getenv("reset_env");
@@ -166,7 +150,7 @@ int misc_init_r(void)
 			return 0;
 	}
 	printf(" === FACTORY RESET ===\n");
-	reset_environment();
+	mv_reset_environment();
 	saveenv();
 
 	return -1;
@@ -206,19 +190,28 @@ void flash_afterinit(ulong size)
 void pci_mvbc_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
 {
 	unsigned char line = 0xff;
+	char *s = getenv("pci_latency");
 	u32 base;
+	u8 val = 0;
+
+	if (s)
+		val = simple_strtoul(s, NULL, 16);
 
 	if (PCI_BUS(dev) == 0) {
 		switch (PCI_DEV (dev)) {
 		case 0xa: /* FPGA */
 			line = 3;
 			pci_hose_read_config_dword(hose, dev, PCI_BASE_ADDRESS_0, &base);
-			printf("found FPA - enable arbitration\n");
+			printf("found FPGA - enable arbitration\n");
 			writel(0x03, (u32*)(base + 0x80c0));
 			writel(0xf0, (u32*)(base + 0x8080));
+			if (val)
+				pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, val);
 			break;
 		case 0xb: /* LAN */
 			line = 2;
+			if (val)
+				pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, val);
 			break;
 		case 0x1a:
 			break;
@@ -234,85 +227,31 @@ struct pci_controller hose = {
 	fixup_irq:pci_mvbc_fixup_irq
 };
 
-int mvbc_p_load_fpga(void)
-{
-	size_t data_size = 0;
-	void *fpga_data = NULL;
-	char *datastr = getenv("fpgadata");
-	char *sizestr = getenv("fpgadatasize");
-
-	if (datastr)
-		fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
-	if (sizestr)
-		data_size = (size_t)simple_strtoul(sizestr, NULL, 16);
-
-	return fpga_load(0, fpga_data, data_size);
-}
-
 extern void pci_mpc5xxx_init(struct pci_controller *);
 
 void pci_init_board(void)
 {
-	char *s;
-	int load_fpga = 1;
-
 	mvbc_p_init_fpga();
-	s = getenv("skip_fpga");
-	if (s) {
-		printf("found 'skip_fpga' -> FPGA _not_ loaded !\n");
-		load_fpga = 0;
-	}
-	if (load_fpga) {
-		printf("loading FPGA ... ");
-		mvbc_p_load_fpga();
-		printf("done\n");
-	}
+	mv_load_fpga();
 	pci_mpc5xxx_init(&hose);
 }
 
-u8 *dhcp_vendorex_prep(u8 *e)
-{
-	char *ptr;
-
-	/* DHCP vendor-class-identifier = 60 */
-	if ((ptr = getenv("dhcp_vendor-class-identifier"))) {
-		*e++ = 60;
-		*e++ = strlen(ptr);
-		while (*ptr)
-			*e++ = *ptr++;
-	}
-	/* DHCP_CLIENT_IDENTIFIER = 61 */
-	if ((ptr = getenv("dhcp_client_id"))) {
-		*e++ = 61;
-		*e++ = strlen(ptr);
-		while (*ptr)
-			*e++ = *ptr++;
-	}
-
-	return e;
-}
-
-u8 *dhcp_vendorex_proc (u8 *popt)
-{
-	return NULL;
-}
-
 void show_boot_progress(int val)
 {
 	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
 
 	switch(val) {
 	case 0: /* FPGA ok */
-		setbits_be32(&gpio->simple_dvo, 0x80);
+		setbits_be32(&gpio->simple_dvo, LED_G0);
 		break;
-	case 1:
-		setbits_be32(&gpio->simple_dvo, 0x40);
+	case 65:
+		setbits_be32(&gpio->simple_dvo, LED_G1);
 		break;
 	case 12:
-		setbits_be32(&gpio->simple_dvo, 0x20);
+		setbits_be32(&gpio->simple_dvo, LED_Y);
 		break;
 	case 15:
-		setbits_be32(&gpio->simple_dvo, 0x10);
+		setbits_be32(&gpio->simple_dvo, LED_R);
 		break;
 	default:
 		break;

board/matrix_vision/mvbc_p/mvbc_p.h

@@ -23,7 +23,7 @@
 #define SIMPLE_DDR      (LED_G0 | LED_G1 | LED_Y | LED_R | \
 			 FPGA_DIN | FPGA_CCLK | FPGA_CONFIG | WD_WDI)
 #define SIMPLE_DVO      (FPGA_CONFIG)
-#define SIMPLE_ODE      (FPGA_CONFIG)
+#define SIMPLE_ODE      (FPGA_CONFIG | LED_G0 | LED_G1 | LED_Y | LED_R)
 #define SIMPLE_GPIOEN   (LED_G0 | LED_G1 | LED_Y | LED_R | \
 			 FPGA_DIN | FPGA_CCLK | FPGA_CONF_DONE | FPGA_CONFIG |\
 			 WD_WDI | COP_PRESENT)

board/matrix_vision/mvbc_p/mvbc_p_autoscript

@@ -5,7 +5,7 @@ setenv bootdtb bootm \${kernel_boot} \${mv_initrd_addr_ram} \${mv_dtb_addr_ram}
 setenv ramkernel setenv kernel_boot \${loadaddr}
 setenv flashkernel setenv kernel_boot \${mv_kernel_addr}
 setenv cpird cp \${mv_initrd_addr} \${mv_initrd_addr_ram} \${mv_initrd_length}
-setenv bootfromflash run flashkernel cpird ramparam addcons e1000para bootdtb
+setenv bootfromflash run flashkernel cpird ramparam addcons e1000para addprofile bootdtb
 setenv getdtb tftp \${mv_dtb_addr_ram} \${dtb_name}
 setenv cpdtb cp \${mv_dtb_addr} \${mv_dtb_addr_ram} 0x2000
 setenv rundtb fdt addr \${mv_dtb_addr_ram}\;fdt boardsetup
@@ -16,12 +16,16 @@ setenv addcons setenv bootargs \${bootargs} console=ttyPSC\${console_nr},\${baud
 else
 setenv addcons setenv bootargs \${bootargs} console=tty0
 fi
-setenv e1000para setenv bootargs \${bootargs} e1000.TxDescriptors=1500 e1000.SmartPowerDownEnable=1
+setenv e1000para setenv bootargs \${bootargs} e1000.TxDescriptors=256 e1000.SmartPowerDownEnable=1
 setenv set_static_ip setenv ipaddr \${static_ipaddr}
 setenv set_static_nm setenv netmask \${static_netmask}
 setenv set_static_gw setenv gatewayip \${static_gateway}
 setenv set_ip setenv ip \${ipaddr}::\${gatewayip}:\${netmask}
 setenv ramparam setenv bootargs root=/dev/ram0 ro rootfstype=squashfs
+if test ${oprofile} = yes;
+then
+setenv addprofile setenv bootargs \${bootargs} profile=\${profile}
+fi
 if test ${autoscr_boot} != no;
 then
   if test ${netboot} = yes;
@@ -31,7 +35,7 @@ then
     then
       echo "=== bootp succeeded -> netboot ==="
       run set_ip
-      run getdtb rundtb bootfromnet ramparam addcons e1000para bootdtb
+      run getdtb rundtb bootfromnet ramparam addcons e1000para addprofile bootdtb
     else
       echo "=== netboot failed ==="
     fi

board/matrix_vision/mvblm7/mvblm7.c

@@ -34,6 +34,7 @@
 #include <libfdt.h>
 #endif
 
+#include "../common/mv_common.h"
 #include "mvblm7.h"
 
 int fixed_sdram(void)
@@ -42,8 +43,15 @@ int fixed_sdram(void)
 	u32 msize = 0;
 	u32 ddr_size;
 	u32 ddr_size_log2;
+	char *s = getenv("ddr_size");
 
 	msize = CONFIG_SYS_DDR_SIZE;
+	if (s) {
+		u32 env_ddr_size = simple_strtoul(s, NULL, 10);
+		if (env_ddr_size == 512)
+			msize = 512;
+	}
+
 	for (ddr_size = msize << 20, ddr_size_log2 = 0;
 	     (ddr_size > 1);
 	     ddr_size = ddr_size >> 1, ddr_size_log2++) {
@@ -63,14 +71,19 @@ int fixed_sdram(void)
 	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
 	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
 	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
 	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
-	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
+	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
 
-	udelay(300);
+	asm("sync;isync");
+	udelay(600);
 
 	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
 
-	return CONFIG_SYS_DDR_SIZE;
+	asm("sync;isync");
+	udelay(500);
+
+	return msize;
 }
 
 phys_size_t initdram(int board_type)
@@ -88,6 +101,17 @@ phys_size_t initdram(int board_type)
 	return msize * 1024 * 1024;
 }
 
+int misc_init_r(void)
+{
+	char *s = getenv("reset_env");
+
+	if (s) {
+		mv_reset_environment();
+	}
+
+	return 0;
+}
+
 int checkboard(void)
 {
 	puts("Board: Matrix Vision mvBlueLYNX-M7\n");
@@ -95,35 +119,6 @@ int checkboard(void)
 	return 0;
 }
 
-u8 *dhcp_vendorex_prep(u8 *e)
-{
-	char *ptr;
-
-	/* DHCP vendor-class-identifier = 60 */
-	ptr = getenv("dhcp_vendor-class-identifier");
-	if (ptr) {
-		*e++ = 60;
-		*e++ = strlen(ptr);
-		while (*ptr)
-			*e++ = *ptr++;
-	}
-	/* DHCP_CLIENT_IDENTIFIER = 61 */
-	ptr = getenv("dhcp_client_id");
-	if (ptr) {
-		*e++ = 61;
-		*e++ = strlen(ptr);
-		while (*ptr)
-			*e++ = *ptr++;
-	}
-
-	return e;
-}
-
-u8 *dhcp_vendorex_proc(u8 *popt)
-{
-	return NULL;
-}
-
 #ifdef CONFIG_HARD_SPI
 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
 {

board/matrix_vision/mvblm7/mvblm7.h

@@ -8,14 +8,13 @@
 #define FPGA_DIN        0x20000000
 #define FPGA_STATUS     0x10000000
 #define FPGA_CONF_DONE  0x08000000
-#define MMC_CS		0x04000000
 
 #define WD_WDI          0x00400000
 #define WD_TS           0x00200000
 #define MAN_RST         0x00100000
 
 #define MV_GPIO_DAT	(WD_TS)
-#define MV_GPIO_OUT	(FPGA_CONFIG|FPGA_DIN|FPGA_CCLK|WD_TS|WD_WDI|MMC_CS)
+#define MV_GPIO_OUT	(FPGA_CONFIG|FPGA_DIN|FPGA_CCLK|MVBLM7_MMC_CS)
 #define MV_GPIO_ODE	(FPGA_CONFIG|MAN_RST)
 
 #endif

board/matrix_vision/mvblm7/pci.c

@@ -32,24 +32,10 @@
 #include <fpga.h>
 #include "mvblm7.h"
 #include "fpga.h"
+#include "../common/mv_common.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int mvblm7_load_fpga(void)
-{
-	size_t data_size = 0;
-	void *fpga_data = NULL;
-	char *datastr = getenv("fpgadata");
-	char *sizestr = getenv("fpgadatasize");
-
-	if (datastr)
-		fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
-	if (sizestr)
-		data_size = (size_t)simple_strtoul(sizestr, NULL, 16);
-
-	return fpga_load(0, fpga_data, data_size);
-}
-
 static struct pci_region pci_regions[] = {
 	{
 		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
@@ -73,10 +59,8 @@ static struct pci_region pci_regions[] = {
 
 void pci_init_board(void)
 {
-	char *s;
 	int i;
 	int warmboot;
-	int load_fpga;
 	volatile immap_t *immr;
 	volatile pcictrl83xx_t *pci_ctrl;
 	volatile gpio83xx_t *gpio;
@@ -84,32 +68,23 @@ void pci_init_board(void)
 	volatile law83xx_t *pci_law;
 	struct pci_region *reg[] = { pci_regions };
 
-	load_fpga = 1;
 	immr = (immap_t *) CONFIG_SYS_IMMR;
 	clk = (clk83xx_t *) &immr->clk;
 	pci_ctrl = immr->pci_ctrl;
 	pci_law = immr->sysconf.pcilaw;
 	gpio  = (volatile gpio83xx_t *)&immr->gpio[0];
 
-	s = getenv("skip_fpga");
-	if (s) {
-		printf("found 'skip_fpga' -> FPGA _not_ loaded !\n");
-		load_fpga = 0;
-	}
-
 	gpio->dat = MV_GPIO_DAT;
 	gpio->odr = MV_GPIO_ODE;
-	if (load_fpga)
-		gpio->dir = MV_GPIO_OUT;
-	else
-		gpio->dir = MV_GPIO_OUT & ~(FPGA_DIN|FPGA_CCLK);
+	gpio->dir = MV_GPIO_OUT;
 
 	printf("SICRH / SICRL : 0x%08x / 0x%08x\n", immr->sysconf.sicrh,
 		immr->sysconf.sicrl);
 
 	mvblm7_init_fpga();
-	if (load_fpga)
-		mvblm7_load_fpga();
+	mv_load_fpga();
+
+	gpio->dir = MV_GPIO_OUT & ~(FPGA_DIN|FPGA_CCLK);
 
 	/* Enable PCI_CLK_OUTPUTs 0 and 1 with 1:1 clocking */
 	clk->occr = 0xc0000000;

board/mimc/mimc200/mimc200.c

@@ -38,7 +38,7 @@
 vidinfo_t panel_info = {
 	.vl_col			= 480,		/* Number of columns */
 	.vl_row			= 272,		/* Number of rows */
-	.vl_clk			= 10000000,	/* pixel clock in ps */
+	.vl_clk			= 5000000,	/* pixel clock in ps */
 	.vl_sync		= ATMEL_LCDC_INVCLK_INVERTED |
 				  ATMEL_LCDC_INVLINE_INVERTED |
 				  ATMEL_LCDC_INVFRAME_INVERTED,

board/netstar/Makefile

@@ -50,8 +50,8 @@ all:	$(obj).depend $(LIB) $(obj)eeprom.srec $(obj)eeprom.bin \
 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) $(ARFLAGS) $@ $^
 
-$(obj)eeprom.srec:	$(obj)eeprom.o $(obj)eeprom_start.o
-	cd $(lnk) && $(LD) -T $(LDSCRIPT) -g -Ttext $(LOAD_ADDR) \
+$(obj)eeprom.srec:	$(obj)eeprom.o $(obj)eeprom_start.o $(obj)u-boot.lds
+	cd $(lnk) && $(LD) -T $(obj)u-boot.lds -g -Ttext $(LOAD_ADDR) \
 		-o $(<:.o=) -e eeprom eeprom.o eeprom_start.o \
 		-L$(obj)../../examples/standalone -lstubs \
 		-L$(obj)../../lib_generic -lgeneric \
@@ -78,10 +78,13 @@ $(obj)crcit.o:	crcit.c
 $(obj)crc32.o:	$(SRCTREE)/lib_generic/crc32.c
 	$(HOSTCC) $(HOSTCFLAGS) -DUSE_HOSTCC -o $@ -c $<
 
+$(obj)u-boot.lds: $(LDSCRIPT)
+	$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
+
 clean:
 	rm -f $(SOBJS) $(OBJS) $(obj)eeprom $(obj)eeprom.srec \
 		$(obj)eeprom.bin $(obj)crcek $(obj)crcek.srec \
-		$(obj)crcek.bin
+		$(obj)crcek.bin $(obj)u-boot.lds
 
 distclean:	clean
 	rm -f $(LIB) core *.bak $(obj).depend

board/qemu-mips/README

@@ -2,7 +2,7 @@ By Vlad Lungu vlad.lungu@windriver.com 2007-Oct-01
 ----------------------------------------
 Qemu is a full system emulator. See
 
-http://fabrice.bellard.free.fr/qemu
+http://www.nongnu.org/qemu/
 
 Limitations & comments
 ----------------------

board/renesas/rsk7203/rsk7203.c

@@ -21,6 +21,7 @@
  */
 
 #include <common.h>
+#include <net.h>
 #include <netdev.h>
 #include <asm/io.h>
 #include <asm/processor.h>

board/tcm-bf537/gpio_cfi_flash.c

@@ -51,9 +51,9 @@ u##size flash_read##size(void *addr) \
 	return __raw_read##sfx(gpio_cfi_flash_swizzle(addr)); \
 }
 MAKE_FLASH(8, b)  /* flash_write8()  flash_read8() */
-MAKE_FLASH(16, w) /* flash_write16() flash_write16() */
-MAKE_FLASH(32, l) /* flash_write32() flash_write32() */
-MAKE_FLASH(64, q) /* flash_write64() flash_write64() */
+MAKE_FLASH(16, w) /* flash_write16() flash_read16() */
+MAKE_FLASH(32, l) /* flash_write32() flash_read32() */
+MAKE_FLASH(64, q) /* flash_write64() flash_read64() */
 
 void gpio_cfi_flash_init(void)
 {

board/trab/Makefile

@@ -49,7 +49,6 @@ $(obj)trab_fkt.srec:	$(OBJS_FKT) $(LIB)
 	$(LD) -g -Ttext $(LOAD_ADDR) -o $(<:.o=) -e trab_fkt $^ $(LIB) \
 		-L$(obj)../../examples/standalone -lstubs \
 		-L$(obj)../../lib_generic -lgeneric \
-		$(obj)../../lib_arm/div0.o \
 		$(PLATFORM_LIBS)
 	$(OBJCOPY) -O srec $(<:.o=) $@
 

board/trab/cmd_trab.c

@@ -106,7 +106,7 @@ extern int i2c_write (uchar, uint, int , uchar* , int);
 extern int i2c_read (uchar, uint, int , uchar* , int);
 extern void tsc2000_reg_init (void);
 extern s32 tsc2000_contact_temp (void);
-extern void spi_init(void);
+extern void tsc2000_spi_init(void);
 
 /* function declarations */
 int do_dip (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
@@ -175,7 +175,7 @@ int do_burn_in (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	led_init ();
 	global_vars_init ();
 	test_function_table_init ();
-	spi_init ();
+	tsc2000_spi_init ();
 
 	if (global_vars_write_to_eeprom () != 0) {
 		printf ("%s: error writing global_vars to eeprom\n",
@@ -336,7 +336,7 @@ int do_contact_temp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		return 1;
 	}
 
-	spi_init ();
+	tsc2000_spi_init ();
 
 	contact_temp = tsc2000_contact_temp();
 	printf ("%d degree C * 100\n", contact_temp) ;
@@ -859,7 +859,7 @@ int do_temp_log (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		delay = simple_strtoul(argv[1], NULL, 10);
 	}
 
-	spi_init ();
+	tsc2000_spi_init ();
 	while (1) {
 
 #if defined(CONFIG_CMD_DATE)

board/trab/trab_fkt.c

@@ -729,7 +729,7 @@ int do_dac (char **argv)
 	int brightness;
 
 	/* initialize SPI */
-	spi_init ();
+	tsc2000_spi_init ();
 
 	if  (((brightness = simple_strtoul (argv[2], NULL, 10)) < 0) ||
 	     (brightness > 255)) {

board/trab/tsc2000.c

@@ -42,7 +42,7 @@
  */
 #define MAX_DEVIATION	18	/* unit: DIGITs of adc; 18 DIGIT = 0.5 °C */
 
-void spi_init(void)
+void tsc2000_spi_init(void)
 {
 	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
 	S3C24X0_SPI * const spi = S3C24X0_GetBase_SPI();

board/trab/tsc2000.h

@@ -121,7 +121,7 @@ void tsc2000_set_range (unsigned int);
 void tsc2000_reg_init (void);
 s32 tsc2000_contact_temp (void);
 void spi_wait_transmit_done (void);
-void spi_init(void);
+void tsc2000_spi_init(void);
 int tsc2000_interpolate(long value, long data[][2], long *result);
 void adc_wait_conversion_done(void);
 

board/trab/u-boot.lds

@@ -33,7 +33,6 @@ SECTIONS
 	.text      :
 	{
 	  cpu/arm920t/start.o	(.text)
-	  lib_arm/_umodsi3.o	(.text)
 	  lib_generic/zlib.o	(.text)
 	  lib_generic/crc32.o	(.text)
 	  lib_generic/string.o	(.text)

board/voiceblue/Makefile

@@ -44,8 +44,8 @@ all:	$(obj).depend $(LIB) $(obj)eeprom.srec $(obj)eeprom.bin
 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
 
-$(obj)eeprom.srec:	$(obj)eeprom.o $(obj)eeprom_start.o
-	cd $(lnk) && $(LD) -T $(LDSCRIPT) -g -Ttext $(LOAD_ADDR) \
+$(obj)eeprom.srec:	$(obj)eeprom.o $(obj)eeprom_start.o $(obj)u-boot.lds
+	cd $(lnk) && $(LD) -T $(obj)u-boot.lds -g -Ttext $(LOAD_ADDR) \
 		-o $(<:.o=) -e eeprom eeprom.o eeprom_start.o \
 		-L$(obj)../../examples/standalone -lstubs \
 		-L$(obj)../../lib_generic -lgeneric \
@@ -55,11 +55,14 @@ $(obj)eeprom.srec:	$(obj)eeprom.o $(obj)eeprom_start.o
 $(obj)eeprom.bin:	$(obj)eeprom.srec
 	$(OBJCOPY) -I srec -O binary $< $@ 2>/dev/null
 
+$(obj)u-boot.lds: $(LDSCRIPT)
+	$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
+
 clean:
 	rm -f $(SOBJS) $(OBJS) $(obj)eeprom \
 		$(obj)eeprom.srec $(obj)eeprom.bin \
-		$(obj)eeprom.o $(obj)eeprom_start.o
-
+		$(obj)eeprom.o $(obj)eeprom_start.o \
+		 $(obj)u-boot.lds
 
 distclean:	clean
 	rm -f $(LIB) core *.bak $(obj).depend

board/zylonite/nand.c

@@ -198,7 +198,7 @@ static unsigned long get_delta(unsigned long start)
 static void wait_us(unsigned long us)
 {
 	unsigned long start = OSCR;
-	us *= OSCR_CLK_FREQ;
+	us = DIV_ROUND_UP(us * OSCR_CLK_FREQ, 1000);
 
 	while (get_delta(start) < us) {
 		/* do nothing */
@@ -219,9 +219,11 @@ static unsigned long dfc_wait_event(unsigned long event)
 	if(!event)
 		return 0xff000000;
 	else if(event & (NDSR_CS0_CMDD | NDSR_CS0_BBD))
-		timeout = CONFIG_SYS_NAND_PROG_ERASE_TO * OSCR_CLK_FREQ;
+		timeout = DIV_ROUND_UP(CONFIG_SYS_NAND_PROG_ERASE_TO
+					* OSCR_CLK_FREQ, 1000);
 	else
-		timeout = CONFIG_SYS_NAND_OTHER_TO * OSCR_CLK_FREQ;
+		timeout = DIV_ROUND_UP(CONFIG_SYS_NAND_OTHER_TO
+					* OSCR_CLK_FREQ, 1000);
 
 	while(1) {
 		ndsr = NDSR;

common/console.c

@@ -534,7 +534,7 @@ int console_init_f(void)
 
 void stdio_print_current_devices(void)
 {
-#ifdef CONFIG_SYS_CONSOLE_INFO_QUIET
+#ifndef CONFIG_SYS_CONSOLE_INFO_QUIET
 	/* Print information */
 	puts("In:    ");
 	if (stdio_devices[stdin] == NULL) {

config.mk

@@ -86,7 +86,7 @@ ifdef	ARCH
 sinclude $(TOPDIR)/lib_$(ARCH)/config.mk	# include architecture dependend rules
 endif
 ifdef	CPU
-sinclude $(TOPDIR)/cpu/$(CPU)/config.mk	# include  CPU	specific rules
+sinclude $(TOPDIR)/cpu/$(CPU)/config.mk		# include  CPU	specific rules
 endif
 ifdef	SOC
 sinclude $(TOPDIR)/cpu/$(CPU)/$(SOC)/config.mk	# include  SoC	specific rules
@@ -166,7 +166,7 @@ endif
 
 AFLAGS := $(AFLAGS_DEBUG) -D__ASSEMBLY__ $(CPPFLAGS)
 
-LDFLAGS += -Bstatic -T $(LDSCRIPT) $(PLATFORM_LDFLAGS)
+LDFLAGS += -Bstatic -T $(obj)u-boot.lds $(PLATFORM_LDFLAGS)
 ifneq ($(TEXT_BASE),)
 LDFLAGS += -Ttext $(TEXT_BASE)
 endif

cpu/arm1136/config.mk

@@ -30,6 +30,4 @@ PLATFORM_CPPFLAGS += -march=armv5
 # Supply options according to compiler version
 #
 # =========================================================================
-PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
-PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,)
 PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))

cpu/arm1176/config.mk

@@ -30,6 +30,4 @@ PLATFORM_CPPFLAGS += -march=armv5t
 # Supply options according to compiler version
 #
 # =========================================================================
-PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
-PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,)
 PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))

cpu/arm1176/s3c64xx/config.mk

@@ -30,5 +30,4 @@ PLATFORM_CPPFLAGS += -march=armv5t
 # Supply options according to compiler version
 #
 # =========================================================================
-#PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
 PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))

cpu/arm720t/config.mk

@@ -31,6 +31,4 @@ PLATFORM_CPPFLAGS += -march=armv4 -mtune=arm7tdmi
 # Supply options according to compiler version
 #
 # =========================================================================
-PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
-PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,)
 PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))

cpu/arm920t/config.mk

@@ -30,6 +30,4 @@ PLATFORM_CPPFLAGS += -march=armv4
 # Supply options according to compiler version
 #
 # =========================================================================
-PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
-PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,)
 PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))

cpu/arm925t/config.mk

@@ -30,6 +30,4 @@ PLATFORM_CPPFLAGS += -march=armv4
 # Supply options according to compiler version
 #
 # =========================================================================
-PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
-PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,)
 PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))

cpu/arm926ejs/config.mk

@@ -30,6 +30,4 @@ PLATFORM_CPPFLAGS += -march=armv5te
 # Supply options according to compiler version
 #
 # =========================================================================
-PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
-PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,)
 PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))

cpu/arm926ejs/davinci/config.mk

@@ -30,6 +30,4 @@ PLATFORM_CPPFLAGS += -march=armv5te
 # Supply options according to compiler version
 #
 # =========================================================================
-PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
-PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,)
 PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))

cpu/arm946es/config.mk

@@ -30,6 +30,4 @@ PLATFORM_CPPFLAGS +=  -march=armv4
 # Supply options according to compiler version
 #
 # =========================================================================
-PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
-PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,)
 PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))

cpu/arm_cortexa8/config.mk

@@ -30,6 +30,5 @@ PLATFORM_CPPFLAGS += -march=armv5
 # Supply options according to compiler version
 #
 # =========================================================================
-PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,)
 PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,\
 		    $(call cc-option,-malignment-traps,))

cpu/arm_cortexa8/omap3/board.c

@@ -297,13 +297,6 @@ int dram_init(void)
 	return 0;
 }
 
-/******************************************************************************
- * Dummy function to handle errors for EABI incompatibility
- *****************************************************************************/
-void raise(void)
-{
-}
-
 /******************************************************************************
  * Dummy function to handle errors for EABI incompatibility
  *****************************************************************************/

cpu/arm_intcm/config.mk

@@ -30,6 +30,4 @@ PLATFORM_CPPFLAGS +=  -march=armv4
 # Supply options according to compiler version
 #
 # =========================================================================
-PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
-PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,)
 PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))

cpu/ixp/config.mk

@@ -33,5 +33,4 @@ PLATFORM_CPPFLAGS += -mbig-endian -march=armv5te -mtune=strongarm1100
 # Supply options according to compiler version
 #
 # =========================================================================
-PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
 PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))

cpu/lh7a40x/config.mk

@@ -30,6 +30,4 @@ PLATFORM_CPPFLAGS += -march=armv4
 # Supply options according to compiler version
 #
 # ========================================================================
-PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
-PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,)
 PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))

cpu/mpc85xx/tlb.c

@@ -110,15 +110,31 @@ void init_tlbs(void)
 void init_addr_map(void)
 {
 	int i;
+	unsigned int max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xff;
 
-	for (i = 0; i < num_tlb_entries; i++) {
-		if (tlb_table[i].tlb == 0)
+	/* walk all the entries */
+	for (i = 0; i < max_cam; i++) {
+		unsigned long epn;
+		u32 tsize, _mas1;
+		phys_addr_t rpn;
+
+		mtspr(MAS0, FSL_BOOKE_MAS0(1, i, 0));
+
+		asm volatile("tlbre;isync");
+		_mas1 = mfspr(MAS1);
+
+		/* if the entry isn't valid skip it */
+		if (!(_mas1 & MAS1_VALID))
 			continue;
 
-		addrmap_set_entry(tlb_table[i].epn,
-			tlb_table[i].rpn,
-			(1UL << ((tlb_table[i].tsize * 2) + 10)),
-			tlb_table[i].esel);
+		tsize = (_mas1 >> 8) & 0xf;
+		epn = mfspr(MAS2) & MAS2_EPN;
+		rpn = mfspr(MAS3) & MAS3_RPN;
+#ifdef CONFIG_ENABLE_36BIT_PHYS
+		rpn |= ((phys_addr_t)mfspr(MAS7)) << 32;
+#endif
+
+		addrmap_set_entry(epn, rpn, (1UL << ((tsize * 2) + 10)), i);
 	}
 
 	return ;

cpu/pxa/config.mk

@@ -31,6 +31,4 @@ PLATFORM_CPPFLAGS += -march=armv5te -mtune=xscale
 # Supply options according to compiler version
 #
 # ========================================================================
-PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
-PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,)
 PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))

cpu/s3c44b0/config.mk

@@ -31,6 +31,4 @@ PLATFORM_CPPFLAGS += -march=armv4 -mtune=arm7tdmi -msoft-float
 # Supply options according to compiler version
 #
 # ========================================================================
-PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
-PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,)
 PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))

cpu/sa1100/config.mk

@@ -31,6 +31,4 @@ PLATFORM_CPPFLAGS += -march=armv4 -mtune=strongarm1100
 # Supply options according to compiler version
 #
 # ========================================================================
-PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
-PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,)
 PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))

doc/README.sbc8349

@@ -91,19 +91,37 @@ safety check before resetting the board upon completion of the reflash.
 PCI:
 ====
 
-This board and U-Boot have been tested with PCI built in, on a SBC8349
-and confirmed that the "pci" command showed the intel e1000 that was
-present in the PCI slot.  Note that if a 33MHz 32bit card is inserted
-in the slot, then the whole board will clock down to a 33MHz base
-clock instead of the default 66MHz.  This will change the baud clocks
-and mess up your serial console output.  If you want to use a 33MHz PCI
-card, then you should build a U-Boot with #undef PCI_66M in the
-include/configs/sbc8349.h and store this to flash prior to powering down
-the board and inserting the 33MHz PCI card.
+There are three configuration choices:
+	sbc8349_config
+	sbc8349_PCI_33_config
+	sbc8349_PCI_66_config
 
-By default PCI support is disabled to better support very early
-revision MPC834x chips with possible PCI issues.  Also PCI support is
-untested on the sbc8347 variants at this point in time.
+The 1st does not enable CONFIG_PCI, and assumes that the PCI slot
+will be left empty (M66EN high), and so the board will operate with
+a base clock of 66MHz.  Note that you need both PCI enabled in u-boot
+and linux in order to have functional PCI under linux.  The only
+reason for choosing to not enable PCI would be if you had a very
+early (rev 1.0) CPU with possible PCI issues.
 
+The second enables PCI support and builds for a 33MHz clock rate.  Note
+that if a 33MHz 32bit card is inserted in the slot, then the whole board
+will clock down to a 33MHz base clock instead of the default 66MHz.  This
+will change the baud clocks and mess up your serial console output if you
+were previously running at 66MHz.  If you want to use a 33MHz PCI card,
+then you should build a U-Boot with sbc8349_PCI_33_config and store this
+to flash prior to powering down the board and inserting the 33MHz PCI
+card.
 
-						Paul Gortmaker, 01/2007
+The third option builds PCI support in, and leaves the clocking at the
+default 66MHz.  This has been tested with an intel PCI-X e1000 card.
+This is also the appropriate choice for people with a recent (non 1.0)
+CPU who currently have the PCI slot physically empty, but intend to
+possibly add a PCI-X card at a later date.
+
+   => pci
+   Scanning PCI devices on bus 0
+   BusDevFun  VendorId   DeviceId   Device Class       Sub-Class
+   _____________________________________________________________
+   00.00.00   0x1957     0x0080     Processor               0x20
+   00.11.00   0x8086     0x1026     Network controller      0x00
+   =>

drivers/hwmon/lm81.c

@@ -109,7 +109,7 @@ static int _dtt_init(int sensor)
 	if (adr < 0)
 		return 1;
 
-	printf ("DTT:   Found LM81@%x Rev: %d\n", adr, rev);
+	debug ("DTT:   Found LM81@%x Rev: %d\n", adr, rev);
 	return 0;
 } /* _dtt_init() */
 

drivers/mtd/cfi_flash.c

@@ -1001,7 +1001,7 @@ static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp,
 #endif
 		flash_write_cmd(info, sector, offset, AMD_CMD_WRITE_TO_BUFFER);
 		cnt = len >> shift;
-		flash_write_cmd(info, sector, offset, (uchar)cnt - 1);
+		flash_write_cmd(info, sector, offset, cnt - 1);
 
 		switch (info->portwidth) {
 		case FLASH_CFI_8BIT:

drivers/mtd/nand/nand_util.c

@@ -508,6 +508,8 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
 		size_t block_offset = offset & (nand->erasesize - 1);
 		size_t write_size;
 
+		WATCHDOG_RESET ();
+
 		if (nand_block_isbad (nand, offset & ~(nand->erasesize - 1))) {
 			printf ("Skip bad block 0x%08llx\n",
 				offset & ~(nand->erasesize - 1));
@@ -578,6 +580,8 @@ int nand_read_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
 		size_t block_offset = offset & (nand->erasesize - 1);
 		size_t read_length;
 
+		WATCHDOG_RESET ();
+
 		if (nand_block_isbad (nand, offset & ~(nand->erasesize - 1))) {
 			printf ("Skipping bad block 0x%08llx\n",
 				offset & ~(nand->erasesize - 1));

drivers/mtd/nand/ndfc.c

@@ -89,8 +89,8 @@ static int ndfc_calculate_ecc(struct mtd_info *mtdinfo,
 
 	/* The NDFC uses Smart Media (SMC) bytes order
 	 */
-	ecc_code[0] = p[2];
-	ecc_code[1] = p[1];
+	ecc_code[0] = p[1];
+	ecc_code[1] = p[2];
 	ecc_code[2] = p[3];
 
 	return 0;

drivers/mtd/spi/eeprom_m95xxx.c

@@ -71,7 +71,6 @@ ssize_t spi_read (uchar *addr, int alen, uchar *buffer, int len)
 ssize_t spi_write (uchar *addr, int alen, uchar *buffer, int len)
 {
 	struct spi_slave *slave;
-	int i;
 	char buf[3];
 
 	slave = spi_setup_slave(CONFIG_DEFAULT_SPI_BUS, 1, 1000000,

drivers/net/Makefile

@@ -39,6 +39,7 @@ COBJS-$(CONFIG_EEPRO100) += eepro100.o
 COBJS-$(CONFIG_ENC28J60) += enc28j60.o
 COBJS-$(CONFIG_FEC_MXC) += fec_mxc.o
 COBJS-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o
+COBJS-$(CONFIG_FTMAC100) += ftmac100.o
 COBJS-$(CONFIG_GRETH) += greth.o
 COBJS-$(CONFIG_INCA_IP_SWITCH) += inca-ip_sw.o
 COBJS-$(CONFIG_KIRKWOOD_EGIGA) += kirkwood_egiga.o

drivers/net/e1000.c

@@ -46,8 +46,7 @@ tested on both gig copper and gig fiber boards
 
 #define TOUT_LOOP   100000
 
-#undef	virt_to_bus
-#define	virt_to_bus(x)	((unsigned long)x)
+#define virt_to_bus(devno, v)	pci_virt_to_mem(devno, (void *) (v))
 #define bus_to_phys(devno, a)	pci_mem_to_phys(devno, a)
 #define mdelay(n)	udelay((n)*1000)
 
@@ -126,9 +125,6 @@ static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
 static int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
 static int e1000_phy_reset(struct e1000_hw *hw);
 static int e1000_detect_gig_phy(struct e1000_hw *hw);
-static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
-		uint16_t words,
-		uint16_t *data);
 static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
 static void e1000_set_media_type(struct e1000_hw *hw);
 
@@ -143,6 +139,9 @@ static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
 #define E1000_WRITE_FLUSH(a) {uint32_t x; x = E1000_READ_REG(a, STATUS);}
 
 #ifndef CONFIG_AP1000 /* remove for warnings */
+static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
+		uint16_t words,
+		uint16_t *data);
 /******************************************************************************
  * Raises the EEPROM's clock input.
  *
@@ -357,7 +356,7 @@ e1000_acquire_eeprom(struct e1000_hw *hw)
 	struct e1000_eeprom_info *eeprom = &hw->eeprom;
 	uint32_t eecd, i = 0;
 
-	DEBUGOUT();
+	DEBUGFUNC();
 
 	if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
 		return -E1000_ERR_SWFW_SYNC;
@@ -418,7 +417,7 @@ static int32_t e1000_init_eeprom_params(struct e1000_hw *hw)
 	int32_t ret_val = E1000_SUCCESS;
 	uint16_t eeprom_size;
 
-	DEBUGOUT();
+	DEBUGFUNC();
 
 	switch (hw->mac_type) {
 	case e1000_82542_rev2_0:
@@ -896,6 +895,47 @@ e1000_validate_eeprom_checksum(struct eth_device *nic)
 		return -E1000_ERR_EEPROM;
 	}
 }
+
+/*****************************************************************************
+ * Set PHY to class A mode
+ * Assumes the following operations will follow to enable the new class mode.
+ *  1. Do a PHY soft reset
+ *  2. Restart auto-negotiation or force link.
+ *
+ * hw - Struct containing variables accessed by shared code
+ ****************************************************************************/
+static int32_t
+e1000_set_phy_mode(struct e1000_hw *hw)
+{
+	int32_t ret_val;
+	uint16_t eeprom_data;
+
+	DEBUGFUNC();
+
+	if ((hw->mac_type == e1000_82545_rev_3) &&
+		(hw->media_type == e1000_media_type_copper)) {
+		ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD,
+				1, &eeprom_data);
+		if (ret_val)
+			return ret_val;
+
+		if ((eeprom_data != EEPROM_RESERVED_WORD) &&
+			(eeprom_data & EEPROM_PHY_CLASS_A)) {
+			ret_val = e1000_write_phy_reg(hw,
+					M88E1000_PHY_PAGE_SELECT, 0x000B);
+			if (ret_val)
+				return ret_val;
+			ret_val = e1000_write_phy_reg(hw,
+					M88E1000_PHY_GEN_CONTROL, 0x8104);
+			if (ret_val)
+				return ret_val;
+
+			hw->phy_reset_disable = FALSE;
+		}
+	}
+
+	return E1000_SUCCESS;
+}
 #endif /* #ifndef CONFIG_AP1000 */
 
 /***************************************************************************
@@ -1999,47 +2039,6 @@ e1000_setup_fiber_link(struct eth_device *nic)
 	return 0;
 }
 
-/*****************************************************************************
- * Set PHY to class A mode
- * Assumes the following operations will follow to enable the new class mode.
- *  1. Do a PHY soft reset
- *  2. Restart auto-negotiation or force link.
- *
- * hw - Struct containing variables accessed by shared code
- ****************************************************************************/
-static int32_t
-e1000_set_phy_mode(struct e1000_hw *hw)
-{
-	int32_t ret_val;
-	uint16_t eeprom_data;
-
-	DEBUGFUNC();
-
-	if ((hw->mac_type == e1000_82545_rev_3) &&
-		(hw->media_type == e1000_media_type_copper)) {
-		ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD,
-				1, &eeprom_data);
-		if (ret_val)
-			return ret_val;
-
-		if ((eeprom_data != EEPROM_RESERVED_WORD) &&
-			(eeprom_data & EEPROM_PHY_CLASS_A)) {
-			ret_val = e1000_write_phy_reg(hw,
-					M88E1000_PHY_PAGE_SELECT, 0x000B);
-			if (ret_val)
-				return ret_val;
-			ret_val = e1000_write_phy_reg(hw,
-					M88E1000_PHY_GEN_CONTROL, 0x8104);
-			if (ret_val)
-				return ret_val;
-
-			hw->phy_reset_disable = FALSE;
-		}
-	}
-
-	return E1000_SUCCESS;
-}
-
 /******************************************************************************
 * Make sure we have a valid PHY and change PHY mode before link setup.
 *
@@ -2355,7 +2354,7 @@ e1000_copper_link_igp_setup(struct e1000_hw *hw)
 	int32_t ret_val;
 	uint16_t phy_data;
 
-	DEBUGOUT();
+	DEBUGFUNC();
 
 	if (hw->phy_reset_disable)
 		return E1000_SUCCESS;
@@ -5017,7 +5016,7 @@ e1000_transmit(struct eth_device *nic, volatile void *packet, int length)
 	txp = tx_base + tx_tail;
 	tx_tail = (tx_tail + 1) % 8;
 
-	txp->buffer_addr = cpu_to_le64(virt_to_bus(packet));
+	txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev, packet));
 	txp->lower.data = cpu_to_le32(hw->txd_cmd | length);
 	txp->upper.data = 0;
 	E1000_WRITE_REG(hw, TDT, tx_tail);
@@ -5145,6 +5144,8 @@ e1000_initialize(bd_t * bis)
 	int idx = 0;
 	u32 PciCommandWord;
 
+	DEBUGFUNC();
+
 	while (1) {		/* Find PCI device(s) */
 		if ((devno = pci_find_devices(supported, idx++)) < 0) {
 			break;
@@ -5170,7 +5171,6 @@ e1000_initialize(bd_t * bis)
 		hw = (struct e1000_hw *) malloc(sizeof (*hw));
 		hw->pdev = devno;
 		nic->priv = hw;
-		nic->iobase = bus_to_phys(devno, iobase);
 
 		sprintf(nic->name, "e1000#%d", card_number);
 
@@ -5180,7 +5180,8 @@ e1000_initialize(bd_t * bis)
 		hw->autoneg_failed = 0;
 		hw->autoneg = 1;
 		hw->get_link_status = TRUE;
-		hw->hw_addr = (typeof(hw->hw_addr)) iobase;
+		hw->hw_addr =
+			pci_map_bar(devno, PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
 		hw->mac_type = e1000_undefined;
 
 		/* MAC and Phy settings */

drivers/net/ftmac100.c

@@ -0,0 +1,278 @@
+/*
+ * Faraday FTMAC100 Ethernet
+ *
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <malloc.h>
+#include <net.h>
+#include <asm/io.h>
+
+#include "ftmac100.h"
+
+#define ETH_ZLEN	60
+
+struct ftmac100_data {
+	volatile struct ftmac100_txdes txdes[1];
+	volatile struct ftmac100_rxdes rxdes[PKTBUFSRX];
+	int rx_index;
+};
+
+/*
+ * Reset MAC
+ */
+static void ftmac100_reset (struct eth_device *dev)
+{
+	struct ftmac100 *ftmac100 = (struct ftmac100 *)dev->iobase;
+
+	debug ("%s()\n", __func__);
+
+	writel (FTMAC100_MACCR_SW_RST, &ftmac100->maccr);
+
+	while (readl (&ftmac100->maccr) & FTMAC100_MACCR_SW_RST)
+		;
+}
+
+/*
+ * Set MAC address
+ */
+static void ftmac100_set_mac (struct eth_device *dev, const unsigned char *mac)
+{
+	struct ftmac100 *ftmac100 = (struct ftmac100 *)dev->iobase;
+	unsigned int maddr = mac[0] << 8 | mac[1];
+	unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
+
+	debug ("%s(%x %x)\n", __func__, maddr, laddr);
+
+	writel (maddr, &ftmac100->mac_madr);
+	writel (laddr, &ftmac100->mac_ladr);
+}
+
+static void ftmac100_set_mac_from_env (struct eth_device *dev)
+{
+	eth_getenv_enetaddr ("ethaddr", dev->enetaddr);
+
+	ftmac100_set_mac (dev, dev->enetaddr);
+}
+
+/*
+ * disable transmitter, receiver
+ */
+static void ftmac100_halt (struct eth_device *dev)
+{
+	struct ftmac100 *ftmac100 = (struct ftmac100 *)dev->iobase;
+
+	debug ("%s()\n", __func__);
+
+	writel (0, &ftmac100->maccr);
+}
+
+static int ftmac100_init (struct eth_device *dev, bd_t *bd)
+{
+	struct ftmac100 *ftmac100 = (struct ftmac100 *)dev->iobase;
+	struct ftmac100_data *priv = dev->priv;
+	volatile struct ftmac100_txdes *txdes = priv->txdes;
+	volatile struct ftmac100_rxdes *rxdes = priv->rxdes;
+	unsigned int maccr;
+	int i;
+
+	debug ("%s()\n", __func__);
+
+	ftmac100_reset (dev);
+
+	/* set the ethernet address */
+
+	ftmac100_set_mac_from_env (dev);
+
+	/* disable all interrupts */
+
+	writel (0, &ftmac100->imr);
+
+	/* initialize descriptors */
+
+	priv->rx_index = 0;
+
+	txdes[0].txdes1			= FTMAC100_TXDES1_EDOTR;
+	rxdes[PKTBUFSRX - 1].rxdes1	= FTMAC100_RXDES1_EDORR;
+
+	for (i = 0; i < PKTBUFSRX; i++) {
+		/* RXBUF_BADR */
+		rxdes[i].rxdes2 = (unsigned int)NetRxPackets[i];
+		rxdes[i].rxdes1 |= FTMAC100_RXDES1_RXBUF_SIZE (PKTSIZE_ALIGN);
+		rxdes[i].rxdes0 = FTMAC100_RXDES0_RXDMA_OWN;
+	}
+
+	/* transmit ring */
+
+	writel ((unsigned int)txdes, &ftmac100->txr_badr);
+
+	/* receive ring */
+
+	writel ((unsigned int)rxdes, &ftmac100->rxr_badr);
+
+	/* poll receive descriptor automatically */
+
+	writel (FTMAC100_APTC_RXPOLL_CNT (1), &ftmac100->aptc);
+
+	/* enable transmitter, receiver */
+
+	maccr = FTMAC100_MACCR_XMT_EN |
+		FTMAC100_MACCR_RCV_EN |
+		FTMAC100_MACCR_XDMA_EN |
+		FTMAC100_MACCR_RDMA_EN |
+		FTMAC100_MACCR_CRC_APD |
+		FTMAC100_MACCR_ENRX_IN_HALFTX |
+		FTMAC100_MACCR_RX_RUNT |
+		FTMAC100_MACCR_RX_BROADPKT;
+
+	writel (maccr, &ftmac100->maccr);
+
+	return 0;
+}
+
+/*
+ * Get a data block via Ethernet
+ */
+static int ftmac100_recv (struct eth_device *dev)
+{
+	struct ftmac100_data *priv = dev->priv;
+	volatile struct ftmac100_rxdes *curr_des;
+	unsigned short rxlen;
+
+	curr_des = &priv->rxdes[priv->rx_index];
+
+	if (curr_des->rxdes0 & FTMAC100_RXDES0_RXDMA_OWN)
+		return -1;
+
+	if (curr_des->rxdes0 & (FTMAC100_RXDES0_RX_ERR |
+				FTMAC100_RXDES0_CRC_ERR |
+				FTMAC100_RXDES0_FTL |
+				FTMAC100_RXDES0_RUNT |
+				FTMAC100_RXDES0_RX_ODD_NB)) {
+		return -1;
+	}
+
+	rxlen = FTMAC100_RXDES0_RFL (curr_des->rxdes0);
+
+	debug ("%s(): RX buffer %d, %x received\n",
+	       __func__, priv->rx_index, rxlen);
+
+	/* pass the packet up to the protocol layers. */
+
+	NetReceive ((void *)curr_des->rxdes2, rxlen);
+
+	/* release buffer to DMA */
+
+	curr_des->rxdes0 |= FTMAC100_RXDES0_RXDMA_OWN;
+
+	priv->rx_index = (priv->rx_index + 1) % PKTBUFSRX;
+
+	return 0;
+}
+
+/*
+ * Send a data block via Ethernet
+ */
+static int
+ftmac100_send (struct eth_device *dev, volatile void *packet, int length)
+{
+	struct ftmac100 *ftmac100 = (struct ftmac100 *)dev->iobase;
+	struct ftmac100_data *priv = dev->priv;
+	volatile struct ftmac100_txdes *curr_des = priv->txdes;
+	int tmo;
+
+	if (curr_des->txdes0 & FTMAC100_TXDES0_TXDMA_OWN) {
+		debug ("%s(): no TX descriptor available\n", __func__);
+		return -1;
+	}
+
+	debug ("%s(%x, %x)\n", __func__, (int)packet, length);
+
+	length = (length < ETH_ZLEN) ? ETH_ZLEN : length;
+
+	/* initiate a transmit sequence */
+
+	curr_des->txdes2 = (unsigned int)packet;	/* TXBUF_BADR */
+
+	curr_des->txdes1 &= FTMAC100_TXDES1_EDOTR;
+	curr_des->txdes1 |= FTMAC100_TXDES1_FTS |
+			    FTMAC100_TXDES1_LTS |
+			    FTMAC100_TXDES1_TXBUF_SIZE (length);
+
+	curr_des->txdes0 = FTMAC100_TXDES0_TXDMA_OWN;
+
+	/* start transmit */
+
+	writel (1, &ftmac100->txpd);
+
+	/* wait for transfer to succeed */
+
+	tmo = get_timer (0) + 5 * CONFIG_SYS_HZ;
+	while (curr_des->txdes0 & FTMAC100_TXDES0_TXDMA_OWN) {
+		if (get_timer (0) >= tmo) {
+			debug ("%s(): timed out\n", __func__);
+			return -1;
+		}
+	}
+
+	debug ("%s(): packet sent\n", __func__);
+
+	return 0;
+}
+
+int ftmac100_initialize (bd_t *bd)
+{
+	struct eth_device *dev;
+	struct ftmac100_data *priv;
+
+	dev = malloc (sizeof *dev);
+	if (!dev) {
+		printf ("%s(): failed to allocate dev\n", __func__);
+		goto out;
+	}
+
+	/* Transmit and receive descriptors should align to 16 bytes */
+
+	priv = memalign (16, sizeof (struct ftmac100_data));
+	if (!priv) {
+		printf ("%s(): failed to allocate priv\n", __func__);
+		goto free_dev;
+	}
+
+	memset (dev, 0, sizeof (*dev));
+	memset (priv, 0, sizeof (*priv));
+
+	sprintf (dev->name, "FTMAC100");
+	dev->iobase	= CONFIG_FTMAC100_BASE;
+	dev->init	= ftmac100_init;
+	dev->halt	= ftmac100_halt;
+	dev->send	= ftmac100_send;
+	dev->recv	= ftmac100_recv;
+	dev->priv	= priv;
+
+	eth_register (dev);
+
+	return 1;
+
+free_dev:
+	free (dev);
+out:
+	return 0;
+}

drivers/net/ftmac100.h

@@ -0,0 +1,154 @@
+/*
+ * Faraday FTMAC100 Ethernet
+ *
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __FTMAC100_H
+#define __FTMAC100_H
+
+struct ftmac100 {
+	unsigned int	isr;		/* 0x00 */
+	unsigned int	imr;		/* 0x04 */
+	unsigned int	mac_madr;	/* 0x08 */
+	unsigned int	mac_ladr;	/* 0x0c */
+	unsigned int	maht0;		/* 0x10 */
+	unsigned int	maht1;		/* 0x14 */
+	unsigned int	txpd;		/* 0x18 */
+	unsigned int	rxpd;		/* 0x1c */
+	unsigned int	txr_badr;	/* 0x20 */
+	unsigned int	rxr_badr;	/* 0x24 */
+	unsigned int	itc;		/* 0x28 */
+	unsigned int	aptc;		/* 0x2c */
+	unsigned int	dblac;		/* 0x30 */
+	unsigned int	pad1[3];	/* 0x34 - 0x3c */
+	unsigned int	pad2[16];	/* 0x40 - 0x7c */
+	unsigned int	pad3[2];	/* 0x80 - 0x84 */
+	unsigned int	maccr;		/* 0x88 */
+	unsigned int	macsr;		/* 0x8c */
+	unsigned int	phycr;		/* 0x90 */
+	unsigned int	phywdata;	/* 0x94 */
+	unsigned int	fcr;		/* 0x98 */
+	unsigned int	bpr;		/* 0x9c */
+	unsigned int	pad4[8];	/* 0xa0 - 0xbc */
+	unsigned int	pad5;		/* 0xc0 */
+	unsigned int	ts;		/* 0xc4 */
+	unsigned int	dmafifos;	/* 0xc8 */
+	unsigned int	tm;		/* 0xcc */
+	unsigned int	pad6;		/* 0xd0 */
+	unsigned int	tx_mcol_scol;	/* 0xd4 */
+	unsigned int	rpf_aep;	/* 0xd8 */
+	unsigned int	xm_pg;		/* 0xdc */
+	unsigned int	runt_tlcc;	/* 0xe0 */
+	unsigned int	crcer_ftl;	/* 0xe4 */
+	unsigned int	rlc_rcc;	/* 0xe8 */
+	unsigned int	broc;		/* 0xec */
+	unsigned int	mulca;		/* 0xf0 */
+	unsigned int	rp;		/* 0xf4 */
+	unsigned int	xp;		/* 0xf8 */
+};
+
+/*
+ * Interrupt status register & interrupt mask register
+ */
+#define FTMAC100_INT_RPKT_FINISH	(1 << 0)
+#define FTMAC100_INT_NORXBUF		(1 << 1)
+#define FTMAC100_INT_XPKT_FINISH	(1 << 2)
+#define FTMAC100_INT_NOTXBUF		(1 << 3)
+#define FTMAC100_INT_XPKT_OK		(1 << 4)
+#define FTMAC100_INT_XPKT_LOST		(1 << 5)
+#define FTMAC100_INT_RPKT_SAV		(1 << 6)
+#define FTMAC100_INT_RPKT_LOST		(1 << 7)
+#define FTMAC100_INT_AHB_ERR		(1 << 8)
+#define FTMAC100_INT_PHYSTS_CHG		(1 << 9)
+
+/*
+ * Automatic polling timer control register
+ */
+#define FTMAC100_APTC_RXPOLL_CNT(x)	(((x) & 0xf) << 0)
+#define FTMAC100_APTC_RXPOLL_TIME_SEL	(1 << 4)
+#define FTMAC100_APTC_TXPOLL_CNT(x)	(((x) & 0xf) << 8)
+#define FTMAC100_APTC_TXPOLL_TIME_SEL	(1 << 12)
+
+/*
+ * MAC control register
+ */
+#define FTMAC100_MACCR_XDMA_EN		(1 << 0)
+#define FTMAC100_MACCR_RDMA_EN		(1 << 1)
+#define FTMAC100_MACCR_SW_RST		(1 << 2)
+#define FTMAC100_MACCR_LOOP_EN		(1 << 3)
+#define FTMAC100_MACCR_CRC_DIS		(1 << 4)
+#define FTMAC100_MACCR_XMT_EN		(1 << 5)
+#define FTMAC100_MACCR_ENRX_IN_HALFTX	(1 << 6)
+#define FTMAC100_MACCR_RCV_EN		(1 << 8)
+#define FTMAC100_MACCR_HT_MULTI_EN	(1 << 9)
+#define FTMAC100_MACCR_RX_RUNT		(1 << 10)
+#define FTMAC100_MACCR_RX_FTL		(1 << 11)
+#define FTMAC100_MACCR_RCV_ALL		(1 << 12)
+#define FTMAC100_MACCR_CRC_APD		(1 << 14)
+#define FTMAC100_MACCR_FULLDUP		(1 << 15)
+#define FTMAC100_MACCR_RX_MULTIPKT	(1 << 16)
+#define FTMAC100_MACCR_RX_BROADPKT	(1 << 17)
+
+/*
+ * Transmit descriptor, aligned to 16 bytes
+ */
+struct ftmac100_txdes {
+	unsigned int	txdes0;
+	unsigned int	txdes1;
+	unsigned int	txdes2;	/* TXBUF_BADR */
+	unsigned int	txdes3;	/* not used by HW */
+} __attribute__ ((aligned(16)));
+
+#define FTMAC100_TXDES0_TXPKT_LATECOL	(1 << 0)
+#define FTMAC100_TXDES0_TXPKT_EXSCOL	(1 << 1)
+#define FTMAC100_TXDES0_TXDMA_OWN	(1 << 31)
+
+#define FTMAC100_TXDES1_TXBUF_SIZE(x)	((x) & 0x7ff)
+#define FTMAC100_TXDES1_LTS		(1 << 27)
+#define FTMAC100_TXDES1_FTS		(1 << 28)
+#define FTMAC100_TXDES1_TX2FIC		(1 << 29)
+#define FTMAC100_TXDES1_TXIC		(1 << 30)
+#define FTMAC100_TXDES1_EDOTR		(1 << 31)
+
+/*
+ * Receive descriptor, aligned to 16 bytes
+ */
+struct ftmac100_rxdes {
+	unsigned int	rxdes0;
+	unsigned int	rxdes1;
+	unsigned int	rxdes2;	/* RXBUF_BADR */
+	unsigned int	rxdes3;	/* not used by HW */
+} __attribute__ ((aligned(16)));
+
+#define FTMAC100_RXDES0_RFL(des)	((des) & 0x7ff)
+#define FTMAC100_RXDES0_MULTICAST	(1 << 16)
+#define FTMAC100_RXDES0_BROADCAST	(1 << 17)
+#define FTMAC100_RXDES0_RX_ERR		(1 << 18)
+#define FTMAC100_RXDES0_CRC_ERR		(1 << 19)
+#define FTMAC100_RXDES0_FTL		(1 << 20)
+#define FTMAC100_RXDES0_RUNT		(1 << 21)
+#define FTMAC100_RXDES0_RX_ODD_NB	(1 << 22)
+#define FTMAC100_RXDES0_LRS		(1 << 28)
+#define FTMAC100_RXDES0_FRS		(1 << 29)
+#define FTMAC100_RXDES0_RXDMA_OWN	(1 << 31)
+
+#define FTMAC100_RXDES1_RXBUF_SIZE(x)	((x) & 0x7ff)
+#define FTMAC100_RXDES1_EDORR		(1 << 31)
+
+#endif	/* __FTMAC100_H */

drivers/net/kirkwood_egiga.c

@@ -38,6 +38,8 @@
 #include <asm/arch/kirkwood.h>
 #include "kirkwood_egiga.h"
 
+#define KIRKWOOD_PHY_ADR_REQUEST 0xee
+
 /*
  * smi_reg_read - miiphy_read callback function.
  *
@@ -52,7 +54,8 @@ static int smi_reg_read(char *devname, u8 phy_adr, u8 reg_ofs, u16 * data)
 	u32 timeout;
 
 	/* Phyadr read request */
-	if (phy_adr == 0xEE && reg_ofs == 0xEE) {
+	if (phy_adr == KIRKWOOD_PHY_ADR_REQUEST &&
+			reg_ofs == KIRKWOOD_PHY_ADR_REQUEST) {
 		/* */
 		*data = (u16) (KWGBEREG_RD(regs->phyadr) & PHYADR_MASK);
 		return 0;
@@ -127,7 +130,8 @@ static int smi_reg_write(char *devname, u8 phy_adr, u8 reg_ofs, u16 data)
 	u32 timeout;
 
 	/* Phyadr write request*/
-	if (phy_adr == 0xEE && reg_ofs == 0xEE) {
+	if (phy_adr == KIRKWOOD_PHY_ADR_REQUEST &&
+			reg_ofs == KIRKWOOD_PHY_ADR_REQUEST) {
 		KWGBEREG_WR(regs->phyadr, data);
 		return 0;
 	}
@@ -396,6 +400,7 @@ static int kwgbe_init(struct eth_device *dev)
 {
 	struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
 	struct kwgbe_registers *regs = dkwgbe->regs;
+	int i;
 
 	/* setup RX rings */
 	kwgbe_init_rx_desc_ring(dkwgbe);
@@ -443,12 +448,20 @@ static int kwgbe_init(struct eth_device *dev)
 
 #if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
 	 && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
-	u16 phyadr;
-	miiphy_read(dev->name, 0xEE, 0xEE, &phyadr);
-	if (!miiphy_link(dev->name, phyadr)) {
-		printf("%s: No link on %s\n", __FUNCTION__, dev->name);
-		return -1;
+	/* Wait up to 5s for the link status */
+	for (i = 0; i < 5; i++) {
+		u16 phyadr;
+
+		miiphy_read(dev->name, KIRKWOOD_PHY_ADR_REQUEST,
+				KIRKWOOD_PHY_ADR_REQUEST, &phyadr);
+		/* Return if we get link up */
+		if (miiphy_link(dev->name, phyadr))
+			return 0;
+		udelay(1000000);
 	}
+
+	printf("No link on %s\n", dev->name);
+	return -1;
 #endif
 	return 0;
 }
@@ -487,18 +500,26 @@ static int kwgbe_send(struct eth_device *dev, volatile void *dataptr,
 	struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
 	struct kwgbe_registers *regs = dkwgbe->regs;
 	struct kwgbe_txdesc *p_txdesc = dkwgbe->p_txdesc;
+	void *p = (void *)dataptr;
 	u32 cmd_sts;
 
+	/* Copy buffer if it's misaligned */
 	if ((u32) dataptr & 0x07) {
-		printf("Err..(%s) xmit dataptr not 64bit aligned\n",
-			__FUNCTION__);
-		return -1;
+		if (datasize > PKTSIZE_ALIGN) {
+			printf("Non-aligned data too large (%d)\n",
+					datasize);
+			return -1;
+		}
+
+		memcpy(dkwgbe->p_aligned_txbuf, p, datasize);
+		p = dkwgbe->p_aligned_txbuf;
 	}
+
 	p_txdesc->cmd_sts = KWGBE_ZERO_PADDING | KWGBE_GEN_CRC;
 	p_txdesc->cmd_sts |= KWGBE_TX_FIRST_DESC | KWGBE_TX_LAST_DESC;
 	p_txdesc->cmd_sts |= KWGBE_BUFFER_OWNED_BY_DMA;
 	p_txdesc->cmd_sts |= KWGBE_TX_EN_INTERRUPT;
-	p_txdesc->buf_ptr = (u8 *) dataptr;
+	p_txdesc->buf_ptr = (u8 *) p;
 	p_txdesc->byte_cnt = datasize;
 
 	/* Apply send command using zeroth RXUQ */
@@ -592,7 +613,7 @@ int kirkwood_egiga_initialize(bd_t * bis)
 	struct kwgbe_device *dkwgbe;
 	struct eth_device *dev;
 	int devnum;
-	char *s, buf[NAMESIZE * 2];
+	char *s;
 	u8 used_ports[MAX_KWGBE_DEVS] = CONFIG_KIRKWOOD_EGIGA_PORTS;
 
 	for (devnum = 0; devnum < MAX_KWGBE_DEVS; devnum++) {
@@ -615,8 +636,13 @@ int kirkwood_egiga_initialize(bd_t * bis)
 							* PKTSIZE_ALIGN + 1)))
 			goto error3;
 
+		if (!(dkwgbe->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN)))
+			goto error4;
+
 		if (!(dkwgbe->p_txdesc = (struct kwgbe_txdesc *)
 		      memalign(PKTALIGN, sizeof(struct kwgbe_txdesc) + 1))) {
+			free(dkwgbe->p_aligned_txbuf);
+		      error4:
 			free(dkwgbe->p_rxbuf);
 		      error3:
 			free(dkwgbe->p_rxdesc);
@@ -650,11 +676,14 @@ int kirkwood_egiga_initialize(bd_t * bis)
 		}
 
 		while (!eth_getenv_enetaddr(s, dev->enetaddr)) {
-			/* Generate Ramdom MAC addresses if not set */
-			sprintf(buf, "00:50:43:%02x:%02x:%02x",
-				get_random_hex(), get_random_hex(),
-				get_random_hex());
-			setenv(s, buf);
+			/* Generate Random Private MAC addr if not set */
+			dev->enetaddr[0] = 0x02;
+			dev->enetaddr[1] = 0x50;
+			dev->enetaddr[2] = 0x43;
+			dev->enetaddr[3] = get_random_hex();
+			dev->enetaddr[4] = get_random_hex();
+			dev->enetaddr[5] = get_random_hex();
+			eth_setenv_enetaddr(s, dev->enetaddr);
 		}
 
 		dev->init = (void *)kwgbe_init;
@@ -667,7 +696,8 @@ int kirkwood_egiga_initialize(bd_t * bis)
 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
 		miiphy_register(dev->name, smi_reg_read, smi_reg_write);
 		/* Set phy address of the port */
-		miiphy_write(dev->name, 0xEE, 0xEE, PHY_BASE_ADR + devnum);
+		miiphy_write(dev->name, KIRKWOOD_PHY_ADR_REQUEST,
+				KIRKWOOD_PHY_ADR_REQUEST, PHY_BASE_ADR + devnum);
 #endif
 	}
 	return 0;

drivers/net/kirkwood_egiga.h

@@ -499,6 +499,7 @@ struct kwgbe_device {
 	struct kwgbe_rxdesc *p_rxdesc;
 	struct kwgbe_rxdesc *p_rxdesc_curr;
 	u8 *p_rxbuf;
+	u8 *p_aligned_txbuf;
 };
 
 #endif /* __EGIGA_H__ */

drivers/net/phy/mv88e61xx.c

@@ -38,7 +38,7 @@
  */
 static int mv88e61xx_busychk_multic(char *name, u32 devaddr)
 {
-	u32 reg = 0;
+	u16 reg = 0;
 	u32 timeout = MV88E61XX_PHY_TIMEOUT;
 
 	/* Poll till SMIBusy bit is clear */
@@ -54,8 +54,7 @@ static int mv88e61xx_busychk_multic(char *name, u32 devaddr)
 
 static void mv88e61xx_wr_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 data)
 {
-	u16 reg;
-	u32 mii_dev_addr;
+	u16 mii_dev_addr;
 
 	/* command to read PHY dev address */
 	if (miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr)) {
@@ -73,8 +72,7 @@ static void mv88e61xx_wr_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 data)
 
 static void mv88e61xx_rd_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 * data)
 {
-	u16 reg;
-	u32 mii_dev_addr;
+	u16 mii_dev_addr;
 
 	/* command to read PHY dev address */
 	if (miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr)) {
@@ -357,15 +355,22 @@ int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig)
 	}
 
 	RD_PHY(name, MV88E61XX_PRT_OFST, PHY_PHYIDR2, &reg);
-	reg &= 0xfff0;
-	if (reg == 0x1610)
+	switch (reg &= 0xfff0) {
+	case 0x1610:
 		idstr = "88E6161";
-	if (reg == 0x1650)
+		break;
+	case 0x1650:
 		idstr = "88E6165";
-	if (reg == 0x1210) {
+		break;
+	case 0x1210:
 		idstr = "88E6123";
 		/* ports 2,3,4 not available */
 		swconfig->ports_enabled &= 0x023;
+		break;
+	default:
+		/* Could not detect switch id */
+		idstr = "88E61??";
+		break;
 	}
 
 	/* Port based VLANs configuration */

drivers/net/tsec.c

@@ -356,8 +356,8 @@ uint mii_cr_init(uint mii_reg, struct tsec_private * priv)
 		return MIIM_CR_INIT;
 }
 
-/* Parse the status register for link, and then do
- * auto-negotiation
+/*
+ * Wait for auto-negotiation to complete, then determine link
  */
 uint mii_parse_sr(uint mii_reg, struct tsec_private * priv)
 {
@@ -366,8 +366,7 @@ uint mii_parse_sr(uint mii_reg, struct tsec_private * priv)
 	 * (ie - we're capable and it's not done)
 	 */
 	mii_reg = read_phy_reg(priv, MIIM_STATUS);
-	if ((mii_reg & MIIM_STATUS_LINK) && (mii_reg & PHY_BMSR_AUTN_ABLE)
-	    && !(mii_reg & PHY_BMSR_AUTN_COMP)) {
+	if ((mii_reg & PHY_BMSR_AUTN_ABLE) && !(mii_reg & PHY_BMSR_AUTN_COMP)) {
 		int i = 0;
 
 		puts("Waiting for PHY auto negotiation to complete");
@@ -388,15 +387,15 @@ uint mii_parse_sr(uint mii_reg, struct tsec_private * priv)
 			mii_reg = read_phy_reg(priv, MIIM_STATUS);
 		}
 		puts(" done\n");
-		priv->link = 1;
+
+		/* Link status bit is latched low, read it again */
+		mii_reg = read_phy_reg(priv, MIIM_STATUS);
+
 		udelay(500000);	/* another 500 ms (results in faster booting) */
-	} else {
-		if (mii_reg & MIIM_STATUS_LINK)
-			priv->link = 1;
-		else
-			priv->link = 0;
 	}
 
+	priv->link = mii_reg & MIIM_STATUS_LINK ? 1 : 0;
+
 	return 0;
 }
 

drivers/qe/uec.c

@@ -31,6 +31,11 @@
 #include "uec_phy.h"
 #include "miiphy.h"
 
+/* Default UTBIPAR SMI address */
+#ifndef CONFIG_UTBIPAR_INIT_TBIPA
+#define CONFIG_UTBIPAR_INIT_TBIPA 0x1F
+#endif
+
 static uec_info_t uec_info[] = {
 #ifdef CONFIG_UEC_ETH1
 	STD_UEC_INFO(1),	/* UEC1 */
@@ -1071,15 +1076,11 @@ static int uec_startup(uec_private_t *uec)
 	utbipar = in_be32(&uec_regs->utbipar);
 	utbipar &= ~UTBIPAR_PHY_ADDRESS_MASK;
 	enet_interface = uec->uec_info->enet_interface;
-	if (enet_interface == ENET_1000_TBI ||
-		 enet_interface == ENET_1000_RTBI) {
-		utbipar |=  (uec_info->phy_address + uec_info->uf_info.ucc_num)
-						 << UTBIPAR_PHY_ADDRESS_SHIFT;
-	} else {
-		utbipar |=  (0x10 + uec_info->uf_info.ucc_num)
-						 << UTBIPAR_PHY_ADDRESS_SHIFT;
-	}
 
+	/* Initialize UTBIPAR address to CONFIG_UTBIPAR_INIT_TBIPA for ALL UEC.
+	 * This frees up the remaining SMI addresses for use.
+	 */
+	utbipar |= CONFIG_UTBIPAR_INIT_TBIPA << UTBIPAR_PHY_ADDRESS_SHIFT;
 	out_be32(&uec_regs->utbipar, utbipar);
 
 	/* Configure the TBI for SGMII operation */

drivers/qe/uec_phy.c

@@ -51,27 +51,28 @@
  *--------------------------------------------------------------------*/
 
 /*
- * Some boards do not have a PHY for each ethernet port. These ports
- * are known as Fixed PHY (or PHY-less) ports. For such ports, set
- * the appropriate CONFIG_PHY_ADDR equal to CONFIG_FIXED_PHY and
- * then define CONFIG_SYS_FIXED_PHY_PORTS to define what the speed and
- * duplex should be for these ports in the board configuration
- * file.
+ * Some boards do not have a PHY for each ethernet port. These ports are known
+ * as Fixed PHY (or PHY-less) ports. For such ports, set the appropriate
+ * CONFIG_SYS_UECx_PHY_ADDR equal to CONFIG_FIXED_PHY_ADDR (an unused address)
+ * When the drver tries to identify the PHYs, CONFIG_FIXED_PHY will be returned
+ * and the driver will search CONFIG_SYS_FIXED_PHY_PORTS to find what network
+ * speed and duplex should be for the port.
  *
- * For Example:
+ * Example board header configuration file:
  *     #define CONFIG_FIXED_PHY   0xFFFFFFFF
+ *     #define CONFIG_SYS_FIXED_PHY_ADDR 0x1E (pick an unused phy address)
  *
- *     #define CONFIG_PHY_ADDR    CONFIG_FIXED_PHY
- *     #define CONFIG_PHY1_ADDR   1
- *     #define CONFIG_PHY2_ADDR   CONFIG_FIXED_PHY
- *     #define CONFIG_PHY3_ADDR   3
+ *     #define CONFIG_SYS_UEC1_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR
+ *     #define CONFIG_SYS_UEC2_PHY_ADDR 0x02
+ *     #define CONFIG_SYS_UEC3_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR
+ *     #define CONFIG_SYS_UEC4_PHY_ADDR 0x04
  *
- *     #define CONFIG_SYS_FIXED_PHY_PORT(devnum,speed,duplex) \
- *                     {devnum, speed, duplex},
+ *     #define CONFIG_SYS_FIXED_PHY_PORT(name,speed,duplex) \
+ *                 {name, speed, duplex},
  *
  *     #define CONFIG_SYS_FIXED_PHY_PORTS \
- *                     CONFIG_SYS_FIXED_PHY_PORT(0,SPEED_100,DUPLEX_FULL) \
- *                     CONFIG_SYS_FIXED_PHY_PORT(2,SPEED_100,DUPLEX_HALF)
+ *                 CONFIG_SYS_FIXED_PHY_PORT("FSL UEC0",SPEED_100,DUPLEX_FULL) \
+ *                 CONFIG_SYS_FIXED_PHY_PORT("FSL UEC2",SPEED_100,DUPLEX_HALF)
  */
 
 #ifndef CONFIG_FIXED_PHY
@@ -83,7 +84,7 @@
 #endif
 
 struct fixed_phy_port {
-	unsigned int devnum;	/* ethernet port */
+	char name[NAMESIZE];	/* ethernet port name */
 	unsigned int speed;	/* specified speed 10,100 or 1000 */
 	unsigned int duplex;	/* specified duplex FULL or HALF */
 };
@@ -592,7 +593,8 @@ static int fixed_phy_read_status (struct uec_mii_info *mii_info)
 	int i = 0;
 
 	for (i = 0; i < ARRAY_SIZE(fixed_phy_port); i++) {
-		if (mii_info->mii_id == fixed_phy_port[i].devnum) {
+		if (strncmp(mii_info->dev->name, fixed_phy_port[i].name,
+				strlen(mii_info->dev->name)) == 0) {
 			mii_info->speed = fixed_phy_port[i].speed;
 			mii_info->duplex = fixed_phy_port[i].duplex;
 			mii_info->link = 1; /* Link is always UP */

fs/jffs2/jffs2_1pass.c

@@ -120,6 +120,7 @@
 #include <jffs2/jffs2.h>
 #include <jffs2/jffs2_1pass.h>
 #include <linux/mtd/compat.h>
+#include <asm/errno.h>
 
 #include "jffs2_private.h"
 
@@ -1200,8 +1201,30 @@ jffs2_1pass_rescan_needed(struct part_info *part)
 	return 0;
 }
 
+#ifdef CONFIG_JFFS2_SUMMARY
+static u32 sum_get_unaligned32(u32 *ptr)
+{
+	u32 val;
+	u8 *p = (u8 *)ptr;
+
+	val = *p | (*(p + 1) << 8) | (*(p + 2) << 16) | (*(p + 3) << 24);
+
+	return __le32_to_cpu(val);
+}
+
+static u16 sum_get_unaligned16(u16 *ptr)
+{
+	u16 val;
+	u8 *p = (u8 *)ptr;
+
+	val = *p | (*(p + 1) << 8);
+
+	return __le16_to_cpu(val);
+}
+
 #define dbg_summary(...) do {} while (0);
-/* Process the stored summary information - helper function for
+/*
+ * Process the stored summary information - helper function for
  * jffs2_sum_scan_sumnode()
  */
 
@@ -1210,54 +1233,64 @@ static int jffs2_sum_process_sum_data(struct part_info *part, uint32_t offset,
 				struct b_lists *pL)
 {
 	void *sp;
-	int i;
+	int i, pass;
+	void *ret;
 
-	sp = summary->sum;
+	for (pass = 0; pass < 2; pass++) {
+		sp = summary->sum;
 
-	for (i = 0; i < summary->sum_num; i++) {
-		dbg_summary("processing summary index %d\n", i);
+		for (i = 0; i < summary->sum_num; i++) {
+			struct jffs2_sum_unknown_flash *spu = sp;
+			dbg_summary("processing summary index %d\n", i);
 
-		switch (((struct jffs2_sum_unknown_flash *)sp)->nodetype) {
-			case JFFS2_NODETYPE_INODE: {
+			switch (sum_get_unaligned16(&spu->nodetype)) {
+				case JFFS2_NODETYPE_INODE: {
 				struct jffs2_sum_inode_flash *spi;
-				spi = sp;
+					if (pass) {
+						spi = sp;
 
-				dbg_summary("Inode at 0x%08x-0x%08x\n",
-					    offset + spi->offset,
-					    offset + spi->offset + spi->totlen);
+						ret = insert_node(&pL->frag,
+							(u32)part->offset +
+							offset +
+							sum_get_unaligned32(
+								&spi->offset));
+						if (ret == NULL)
+							return -1;
+					}
 
-				if (insert_node(&pL->frag, (u32) part->offset +
-						offset + spi->offset) == NULL)
-					return -1;
+					sp += JFFS2_SUMMARY_INODE_SIZE;
 
-				sp += JFFS2_SUMMARY_INODE_SIZE;
+					break;
+				}
+				case JFFS2_NODETYPE_DIRENT: {
+					struct jffs2_sum_dirent_flash *spd;
+					spd = sp;
+					if (pass) {
+						ret = insert_node(&pL->dir,
+							(u32) part->offset +
+							offset +
+							sum_get_unaligned32(
+								&spd->offset));
+						if (ret == NULL)
+							return -1;
+					}
 
-				break;
-			}
+					sp += JFFS2_SUMMARY_DIRENT_SIZE(
+							spd->nsize);
 
-			case JFFS2_NODETYPE_DIRENT: {
-				struct jffs2_sum_dirent_flash *spd;
-				spd = sp;
-
-				dbg_summary("Dirent at 0x%08x-0x%08x\n",
-					    offset + spd->offset,
-					    offset + spd->offset + spd->totlen);
-
-				if (insert_node(&pL->dir, (u32) part->offset +
-						offset + spd->offset) == NULL)
-					return -1;
-
-				sp += JFFS2_SUMMARY_DIRENT_SIZE(spd->nsize);
-
-				break;
-			}
-			default : {
-				uint16_t nodetype =
-					((struct jffs2_sum_unknown_flash *)
-					 sp)->nodetype;
-				printf("Unsupported node type %x found in "
-						"summary!\n", nodetype);
-				break;
+					break;
+				}
+				default : {
+					uint16_t nodetype = sum_get_unaligned16(
+								&spu->nodetype);
+					printf("Unsupported node type %x found"
+							" in summary!\n",
+							nodetype);
+					if ((nodetype & JFFS2_COMPAT_MASK) ==
+							JFFS2_FEATURE_INCOMPAT)
+						return -EIO;
+					return -EBADMSG;
+				}
 			}
 		}
 	}
@@ -1315,6 +1348,8 @@ int jffs2_sum_scan_sumnode(struct part_info *part, uint32_t offset,
 		dbg_summary("Summary : CLEANMARKER node \n");
 
 	ret = jffs2_sum_process_sum_data(part, offset, summary, pL);
+	if (ret == -EBADMSG)
+		return 0;
 	if (ret)
 		return ret;		/* real error */
 
@@ -1325,6 +1360,7 @@ crc_err:
 
 	return 0;
 }
+#endif /* CONFIG_JFFS2_SUMMARY */
 
 #ifdef DEBUG_FRAGMENTS
 static void
@@ -1430,13 +1466,16 @@ jffs2_1pass_build_lists(struct part_info * part)
 		uint32_t buf_ofs = sector_ofs;
 		uint32_t buf_len;
 		uint32_t ofs, prevofs;
+#ifdef CONFIG_JFFS2_SUMMARY
 		struct jffs2_sum_marker *sm;
 		void *sumptr = NULL;
 		uint32_t sumlen;
 		int ret;
+#endif
 
 		WATCHDOG_RESET();
 
+#ifdef CONFIG_JFFS2_SUMMARY
 		buf_len = sizeof(*sm);
 
 		/* Read as much as we want into the _end_ of the preallocated
@@ -1457,6 +1496,8 @@ jffs2_1pass_build_lists(struct part_info * part)
 				if (!sumptr) {
 					putstr("Can't get memory for summary "
 							"node!\n");
+					free(buf);
+					jffs2_free_cache(part);
 					return 0;
 				}
 				memcpy(sumptr + sumlen - buf_len, buf +
@@ -1478,12 +1519,16 @@ jffs2_1pass_build_lists(struct part_info * part)
 
 			if (buf_size && sumlen > buf_size)
 				free(sumptr);
-			if (ret < 0)
+			if (ret < 0) {
+				free(buf);
+				jffs2_free_cache(part);
 				return 0;
+			}
 			if (ret)
 				continue;
 
 		}
+#endif /* CONFIG_JFFS2_SUMMARY */
 
 		buf_len = EMPTY_SCAN_SIZE(part->sector_size);
 
@@ -1592,8 +1637,11 @@ jffs2_1pass_build_lists(struct part_info * part)
 				       break;
 
 				if (insert_node(&pL->frag, (u32) part->offset +
-						ofs) == NULL)
+						ofs) == NULL) {
+					free(buf);
+					jffs2_free_cache(part);
 					return 0;
+				}
 				if (max_totlen < node->totlen)
 					max_totlen = node->totlen;
 				break;
@@ -1619,8 +1667,11 @@ jffs2_1pass_build_lists(struct part_info * part)
 				if (! (counterN%100))
 					puts ("\b\b.  ");
 				if (insert_node(&pL->dir, (u32) part->offset +
-						ofs) == NULL)
+						ofs) == NULL) {
+					free(buf);
+					jffs2_free_cache(part);
 					return 0;
+				}
 				if (max_totlen < node->totlen)
 					max_totlen = node->totlen;
 				counterN++;

include/asm-arm/arch-omap3/cpu.h

@@ -120,9 +120,9 @@ struct gpmc {
 	u8 res4[0xC];
 	u32 config;		/* 0x50 */
 	u32 status;		/* 0x54 */
-	u8 res5[0x8];
+	u8 res5[0x8];	/* 0x58 */
 	struct gpmc_cs cs[8];	/* 0x60, 0x90, .. */
-	u8 res6[0x18];
+	u8 res6[0x14];		/* 0x1E0 */
 	u32 ecc_config;		/* 0x1F4 */
 	u32 ecc_control;	/* 0x1F8 */
 	u32 ecc_size_config;	/* 0x1FC */

include/asm-arm/arch-pxa/pxa-regs.h

@@ -1094,7 +1094,7 @@ typedef void		(*ExcpHndlr) (void) ;
 #define OMCR10		__REG(0x40A000D8)  /* OS Match Control Register 10 */
 #define OMCR11		__REG(0x40A000DC)  /* OS Match Control Register 11 */
 
-#define OSCR_CLK_FREQ	 3.250		   /* MHz */
+#define OSCR_CLK_FREQ	 3250		   /* kHz = 3.25 MHz */
 #endif /* CONFIG_CPU_MONAHANS */
 
 #define OSSR_M4		(1 << 4)	/* Match status channel 4 */

include/configs/MPC8313ERDB.h

@@ -594,7 +594,7 @@
 #define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP server */
 #define CONFIG_FDTFILE		mpc8313erdb.dtb
 
-#define CONFIG_LOADADDR		500000	/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		800000	/* default location for tftp and bootm */
 #define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
 #define CONFIG_BAUDRATE		115200
 
@@ -611,7 +611,7 @@
 		"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "	\
 		"protect on " MK_STR(TEXT_BASE) " +$filesize; "		\
 		"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"	\
-	"fdtaddr=400000\0"						\
+	"fdtaddr=780000\0"						\
 	"fdtfile=" MK_STR(CONFIG_FDTFILE) "\0"				\
 	"console=ttyS0\0"						\
 	"setbootargs=setenv bootargs "					\

include/configs/MPC8315ERDB.h

@@ -566,7 +566,7 @@
 
 #define CONFIG_BAUDRATE 115200
 
-#define CONFIG_LOADADDR 500000	/* default location for tftp and bootm */
+#define CONFIG_LOADADDR 800000	/* default location for tftp and bootm */
 
 #define CONFIG_BOOTDELAY 6	/* -1 disables auto-boot */
 #undef CONFIG_BOOTARGS		/* the boot command will set bootargs */
@@ -576,7 +576,7 @@
    "consoledev=ttyS0\0"							\
    "ramdiskaddr=1000000\0"						\
    "ramdiskfile=ramfs.83xx\0"						\
-   "fdtaddr=400000\0"							\
+   "fdtaddr=780000\0"							\
    "fdtfile=mpc8315erdb.dtb\0"						\
    "usb_phy_type=utmi\0"						\
    ""

include/configs/MPC8323ERDB.h

@@ -542,7 +542,7 @@
 #define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP server */
 #define CONFIG_FDTFILE		mpc832x_rdb.dtb
 
-#define CONFIG_LOADADDR		500000	/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		800000	/* default location for tftp and bootm */
 #define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
 #define CONFIG_BAUDRATE		115200
 
@@ -558,7 +558,7 @@
 		"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "	\
 		"protect on " MK_STR(TEXT_BASE) " +$filesize; "		\
 		"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"	\
-	"fdtaddr=400000\0"						\
+	"fdtaddr=780000\0"						\
 	"fdtfile=" MK_STR(CONFIG_FDTFILE) "\0"				\
 	"ramdiskaddr=1000000\0"						\
 	"ramdiskfile=" MK_STR(CONFIG_RAMDISKFILE) "\0"			\

include/configs/MPC832XEMDS.h

@@ -548,7 +548,7 @@
 
 #define CONFIG_BAUDRATE	115200
 
-#define CONFIG_LOADADDR	500000	/* default location for tftp and bootm */
+#define CONFIG_LOADADDR	800000	/* default location for tftp and bootm */
 
 #define CONFIG_BOOTDELAY 6	/* -1 disables auto-boot */
 #undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
@@ -558,7 +558,7 @@
    "consoledev=ttyS0\0"							\
    "ramdiskaddr=1000000\0"						\
    "ramdiskfile=ramfs.83xx\0"						\
-   "fdtaddr=400000\0"							\
+   "fdtaddr=780000\0"							\
    "fdtfile=mpc832x_mds.dtb\0"						\
    ""
 

include/configs/MPC8349EMDS.h

@@ -172,7 +172,6 @@
 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
 
-#define CONFIG_SYS_MID_FLASH_JUMP	0x7F000000
 #define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 
 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
@@ -701,7 +700,7 @@
 #define CONFIG_GATEWAYIP	192.168.1.1
 #define CONFIG_NETMASK		255.255.255.0
 
-#define CONFIG_LOADADDR		500000	/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		800000	/* default location for tftp and bootm */
 
 #define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
 #undef  CONFIG_BOOTARGS			/* the boot command will set bootargs */
@@ -732,8 +731,8 @@
 	"update=protect off fe000000 fe03ffff; "			\
 		"era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"	\
 	"upd=run load update\0"						\
-	"fdtaddr=400000\0"						\
-	"fdtfile=mpc8349emds.dtb\0"					\
+	"fdtaddr=780000\0"						\
+	"fdtfile=mpc834x_mds.dtb\0"					\
 	""
 
 #define CONFIG_NFSBOOTCOMMAND	                                        \

include/configs/MPC8349ITX.h

@@ -515,7 +515,7 @@ boards, we say we have two, but don't display a message if we find only one. */
 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-#define CONFIG_LOADADDR	500000	/* default location for tftp and bootm */
+#define CONFIG_LOADADDR	800000	/* default location for tftp and bootm */
 
 #ifdef CONFIG_MPC8349ITX
 #define CONFIG_SYS_PROMPT	"MPC8349E-mITX> "	/* Monitor Command Prompt */
@@ -708,7 +708,7 @@ boards, we say we have two, but don't display a message if we find only one. */
 #define CONFIG_FDTFILE		mpc8349emitxgp.dtb
 #endif
 
-#define CONFIG_BOOTDELAY	0
+#define CONFIG_BOOTDELAY	6
 
 #define XMK_STR(x)	#x
 #define MK_STR(x)	XMK_STR(x)
@@ -731,7 +731,7 @@ boards, we say we have two, but don't display a message if we find only one. */
 		"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "	\
 		"protect on " MK_STR(TEXT_BASE) " +$filesize; "		\
 		"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"	\
-	"fdtaddr=400000\0"						\
+	"fdtaddr=780000\0"						\
 	"fdtfile=" MK_STR(CONFIG_FDTFILE) "\0"
 
 #define CONFIG_NFSBOOTCOMMAND						\

include/configs/MPC8360EMDS.h

@@ -589,7 +589,7 @@
 
 #define CONFIG_BAUDRATE 115200
 
-#define CONFIG_LOADADDR 500000	/* default location for tftp and bootm */
+#define CONFIG_LOADADDR 800000	/* default location for tftp and bootm */
 
 #define CONFIG_BOOTDELAY 6	/* -1 disables auto-boot */
 #undef	CONFIG_BOOTARGS		/* the boot command will set bootargs */
@@ -599,7 +599,7 @@
    "consoledev=ttyS0\0"							\
    "ramdiskaddr=1000000\0"						\
    "ramdiskfile=ramfs.83xx\0"						\
-   "fdtaddr=400000\0"							\
+   "fdtaddr=780000\0"							\
    "fdtfile=mpc836x_mds.dtb\0"						\
    ""
 

include/configs/MPC8360ERDK.h

@@ -530,7 +530,7 @@
    "consoledev=ttyS0\0"\
    "loadaddr=a00000\0"\
    "fdtaddr=900000\0"\
-   "fdtfile=dtb\0"\
+   "fdtfile=mpc836x_rdk.dtb\0"\
    "fsfile=fs\0"\
    "ubootfile=u-boot.bin\0"\
    "mtdparts=mtdparts=60000000.nand-flash:4096k(kernel),128k(dtb),-(rootfs)\0"\

include/configs/MPC837XEMDS.h

@@ -646,7 +646,7 @@ extern int board_pci_host_broken(void);
 
 #define CONFIG_BAUDRATE 115200
 
-#define CONFIG_LOADADDR 500000	/* default location for tftp and bootm */
+#define CONFIG_LOADADDR 800000	/* default location for tftp and bootm */
 
 #define CONFIG_BOOTDELAY 6	/* -1 disables auto-boot */
 #undef CONFIG_BOOTARGS		/* the boot command will set bootargs */
@@ -656,7 +656,7 @@ extern int board_pci_host_broken(void);
    "consoledev=ttyS0\0"							\
    "ramdiskaddr=1000000\0"						\
    "ramdiskfile=ramfs.83xx\0"						\
-   "fdtaddr=400000\0"							\
+   "fdtaddr=780000\0"							\
    "fdtfile=mpc8379_mds.dtb\0"						\
    ""
 

include/configs/MPC837XERDB.h

@@ -190,8 +190,8 @@
 				/* 0x3937d322 */
 #define CONFIG_SYS_DDR_TIMING_2	0x02984cc8
 
-#define CONFIG_SYS_DDR_INTERVAL	((1545 << SDRAM_INTERVAL_REFINT_SHIFT) \
-				| (256 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
+#define CONFIG_SYS_DDR_INTERVAL	((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
+				| (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 				/* 0x06090100 */
 
 #if defined(CONFIG_DDR_2T_TIMING)
@@ -205,7 +205,7 @@
 				/* 0x43000000 */
 #endif
 #define CONFIG_SYS_DDR_SDRAM_CFG2	0x00001000 /* 1 posted refresh */
-#define CONFIG_SYS_DDR_MODE		((0x0440 << SDRAM_MODE_ESD_SHIFT) \
+#define CONFIG_SYS_DDR_MODE		((0x0406 << SDRAM_MODE_ESD_SHIFT) \
 				| (0x0442 << SDRAM_MODE_SD_SHIFT))
 				/* 0x04400442 */ /* DDR400 */
 #define CONFIG_SYS_DDR_MODE2		0x00000000
@@ -668,7 +668,7 @@
 #define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP server */
 #define CONFIG_FDTFILE		mpc8379_rdb.dtb
 
-#define CONFIG_LOADADDR		500000	/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		800000	/* default location for tftp and bootm */
 #define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
 #define CONFIG_BAUDRATE		115200
 
@@ -684,7 +684,7 @@
 		"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "	\
 		"protect on " MK_STR(TEXT_BASE) " +$filesize; "		\
 		"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"	\
-	"fdtaddr=400000\0"						\
+	"fdtaddr=780000\0"						\
 	"fdtfile=" MK_STR(CONFIG_FDTFILE) "\0"				\
 	"ramdiskaddr=1000000\0"						\
 	"ramdiskfile=" MK_STR(CONFIG_RAMDISKFILE) "\0"			\

include/configs/MPC8536DS.h

@@ -534,7 +534,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 
 #if defined(CONFIG_PCI)
 #define CONFIG_CMD_PCI
-#define CONFIG_CMD_BEDBUG
 #define CONFIG_CMD_NET
 #endif
 

include/configs/MPC8544DS.h

@@ -433,7 +433,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI
-    #define CONFIG_CMD_BEDBUG
     #define CONFIG_CMD_NET
     #define CONFIG_CMD_SCSI
     #define CONFIG_CMD_EXT2

include/configs/MPC8572DS.h

@@ -585,7 +585,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 
 #if defined(CONFIG_PCI)
 #define CONFIG_CMD_PCI
-#define CONFIG_CMD_BEDBUG
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_SCSI
 #define CONFIG_CMD_EXT2

include/configs/MVBC_P.h

@@ -67,7 +67,7 @@
 #define MV_CI			mvBlueCOUGAR-P
 #define MV_VCI			mvBlueCOUGAR-P
 #define MV_FPGA_DATA		0xff860000
-#define MV_FPGA_SIZE		0x0003c886
+#define MV_FPGA_SIZE		0
 #define MV_KERNEL_ADDR		0xffd00000
 #define MV_INITRD_ADDR		0xff900000
 #define MV_INITRD_LENGTH	0x00400000

include/configs/MVBLM7.h

@@ -46,10 +46,9 @@
 #define CONFIG_MPC8XXX_SPI
 #define CONFIG_HARD_SPI
 #define MVBLM7_MMC_CS   0x04000000
+#define CONFIG_MISC_INIT_R
 
 /* I2C */
-#undef CONFIG_SOFT_I2C
-
 #define CONFIG_FSL_I2C
 #define CONFIG_I2C_MULTI_BUS
 #define CONFIG_SYS_I2C_OFFSET		0x3000
@@ -61,44 +60,36 @@
 /*
  * DDR Setup
  */
+#undef	CONFIG_SPD_EEPROM
+
 #define CONFIG_SYS_DDR_BASE		0x00000000
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
 #define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
 #define CONFIG_SYS_83XX_DDR_USES_CS0	1
 #define CONFIG_SYS_MEMTEST_START	(60<<20)
 #define CONFIG_SYS_MEMTEST_END		(70<<20)
+#define CONFIG_VERY_BIG_RAM
 
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
-				DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
+#define CONFIG_SYS_DDRCDR		0x22000001
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 
-#define CONFIG_SYS_DDR_SIZE		256
+#define CONFIG_SYS_DDR_SIZE		512
 
-/* HC, 75Ohm, DDR-II, DRQ */
-#define CONFIG_SYS_DDRCDR		0x80000001
-/* EN, ODT_WR, 3BA, 14row, 10col */
-#define CONFIG_SYS_DDR_CS0_CONFIG	0x80014102
-#define CONFIG_SYS_DDR_CS1_CONFIG	0x0
-#define CONFIG_SYS_DDR_CS2_CONFIG	0x0
-#define CONFIG_SYS_DDR_CS3_CONFIG	0x0
+#define CONFIG_SYS_DDR_CS0_CONFIG	0x80014202
 
-#define CONFIG_SYS_DDR_CS0_BNDS	0x0000000f
-#define CONFIG_SYS_DDR_CS1_BNDS	0x0
-#define CONFIG_SYS_DDR_CS2_BNDS	0x0
-#define CONFIG_SYS_DDR_CS3_BNDS	0x0
+#define CONFIG_SYS_DDR_CS0_BNDS		0x0000003f
 
-#define CONFIG_SYS_DDR_CLK_CNTL	0x02000000
+#define CONFIG_SYS_DDR_TIMING_0		0x00260802
+#define CONFIG_SYS_DDR_TIMING_1		0x3837c322
+#define CONFIG_SYS_DDR_TIMING_2		0x0f9848c6
+#define CONFIG_SYS_DDR_TIMING_3		0x00000000
 
-#define CONFIG_SYS_DDR_TIMING_0	0x00260802
-#define CONFIG_SYS_DDR_TIMING_1	0x2625b221
-#define CONFIG_SYS_DDR_TIMING_2	0x1f9820c7
-#define CONFIG_SYS_DDR_TIMING_3	0x00000000
-
-/* ~MEM_EN, SREN, DDR-II, 32_BE */
-#define CONFIG_SYS_DDR_SDRAM_CFG	0x43080000
+#define CONFIG_SYS_DDR_SDRAM_CFG	0x43080008
 #define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
-#define CONFIG_SYS_DDR_INTERVAL	0x04060100
+#define CONFIG_SYS_DDR_INTERVAL		0x02000100
 
-#define CONFIG_SYS_DDR_MODE		0x078e0232
+#define CONFIG_SYS_DDR_MODE		0x04040242
+#define CONFIG_SYS_DDR_MODE2		0x00800000
 
 /* Flash */
 #define CONFIG_SYS_FLASH_CFI
@@ -404,8 +395,8 @@
 
 #define MV_CI			mvBL-M7
 #define MV_VCI			mvBL-M7
-#define MV_FPGA_DATA		0xfff80000
-#define MV_FPGA_SIZE		0x00076ca2
+#define MV_FPGA_DATA		0xfff40000
+#define MV_FPGA_SIZE		0
 #define MV_KERNEL_ADDR		0xff810000
 #define MV_INITRD_ADDR		0xffb00000
 #define MV_SOURCE_ADDR		0xff804000
@@ -452,7 +443,7 @@
 	"static_ipaddr=192.168.90.10\0"				\
 	"static_netmask=255.255.255.0\0"			\
 	"static_gateway=0.0.0.0\0"				\
-	"initrd_name=uInitrd.mvblm7-xenorfs\0"			\
+	"initrd_name=uInitrd.mvBL-M7-rfs\0"			\
 	"zcip=no\0"						\
 	"netboot=yes\0"						\
 	"mvtest=Ff\0"						\

include/configs/P2020DS.h

@@ -614,7 +614,6 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy);
 
 #if defined(CONFIG_PCI)
 #define CONFIG_CMD_PCI
-#define CONFIG_CMD_BEDBUG
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_SCSI
 #define CONFIG_CMD_EXT2

include/configs/TQM834x.h

@@ -250,7 +250,7 @@ extern int tqm834x_num_flash_banks;
 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 
 /* PCI1 host bridge */
-#define CONFIG_SYS_PCI1_MEM_BASE       0x80000000
+#define CONFIG_SYS_PCI1_MEM_BASE       0x90000000
 #define CONFIG_SYS_PCI1_MEM_PHYS       CONFIG_SYS_PCI1_MEM_BASE
 #define CONFIG_SYS_PCI1_MEM_SIZE       0x10000000      /* 256M */
 #define CONFIG_SYS_PCI1_MMIO_BASE      (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)

include/configs/at91cap9adk.h

@@ -172,7 +172,7 @@
 #define CONFIG_BOOTARGS		"console=ttyS0,115200 "			\
 				"root=/dev/mtdblock1 "			\
 				"mtdparts=physmap-flash.0:-(nor);"	\
-				"at91_nand:-(root) "			\
+				"atmel_nand:-(root) "			\
 				"rw rootfstype=jffs2"
 
 #else
@@ -188,7 +188,7 @@
 				"root=/dev/mtdblock4 "			\
 				"mtdparts=physmap-flash.0:16k(bootstrap)ro,"\
 				"16k(env),224k(uboot)ro,-(linux);"	\
-				"at91_nand:-(root) "			\
+				"atmel_nand:-(root) "			\
 				"rw rootfstype=jffs2"
 
 #endif

include/configs/at91sam9260ek.h

@@ -163,7 +163,7 @@
 #define CONFIG_BOOTCOMMAND	"cp.b 0xC0042000 0x22000000 0x210000; bootm"
 #define CONFIG_BOOTARGS		"console=ttyS0,115200 "			\
 				"root=/dev/mtdblock0 "			\
-				"mtdparts=at91_nand:-(root) "		\
+				"mtdparts=atmel_nand:-(root) "		\
 				"rw rootfstype=jffs2"
 
 #elif CONFIG_SYS_USE_DATAFLASH_CS1
@@ -177,7 +177,7 @@
 #define CONFIG_BOOTCOMMAND	"cp.b 0xD0042000 0x22000000 0x210000; bootm"
 #define CONFIG_BOOTARGS		"console=ttyS0,115200 "			\
 				"root=/dev/mtdblock0 "			\
-				"mtdparts=at91_nand:-(root) "		\
+				"mtdparts=atmel_nand:-(root) "		\
 				"rw rootfstype=jffs2"
 
 #else /* CONFIG_SYS_USE_NANDFLASH */
@@ -190,7 +190,7 @@
 #define CONFIG_BOOTCOMMAND	"nand read 0x22000000 0xA0000 0x200000; bootm"
 #define CONFIG_BOOTARGS		"console=ttyS0,115200 "			\
 				"root=/dev/mtdblock5 "			\
-				"mtdparts=at91_nand:128k(bootstrap)ro,"	\
+				"mtdparts=atmel_nand:128k(bootstrap)ro,"	\
 				"256k(uboot)ro,128k(env1)ro,"		\
 				"128k(env2)ro,2M(linux),-(root) "	\
 				"rw rootfstype=jffs2"

include/configs/at91sam9261ek.h

@@ -181,7 +181,7 @@
 #define CONFIG_BOOTCOMMAND	"cp.b 0xC0042000 0x22000000 0x210000; bootm"
 #define CONFIG_BOOTARGS		"console=ttyS0,115200 "			\
 				"root=/dev/mtdblock0 "			\
-				"mtdparts=at91_nand:-(root) "		\
+				"mtdparts=atmel_nand:-(root) "		\
 				"rw rootfstype=jffs2"
 
 #elif CONFIG_SYS_USE_DATAFLASH_CS3
@@ -195,7 +195,7 @@
 #define CONFIG_BOOTCOMMAND	"cp.b 0xD0042000 0x22000000 0x210000; bootm"
 #define CONFIG_BOOTARGS		"console=ttyS0,115200 "			\
 				"root=/dev/mtdblock0 "			\
-				"mtdparts=at91_nand:-(root) "		\
+				"mtdparts=atmel_nand:-(root) "		\
 				"rw rootfstype=jffs2"
 
 #else /* CONFIG_SYS_USE_NANDFLASH */
@@ -208,7 +208,7 @@
 #define CONFIG_BOOTCOMMAND	"nand read 0x22000000 0xA0000 0x200000; bootm"
 #define CONFIG_BOOTARGS		"console=ttyS0,115200 "			\
 				"root=/dev/mtdblock5 "			\
-				"mtdparts=at91_nand:128k(bootstrap)ro,"	\
+				"mtdparts=atmel_nand:128k(bootstrap)ro,"	\
 				"256k(uboot)ro,128k(env1)ro,"		\
 				"128k(env2)ro,2M(linux),-(root) "	\
 				"rw rootfstype=jffs2"

include/configs/at91sam9263ek.h

@@ -304,7 +304,7 @@
 #define CONFIG_BOOTCOMMAND	"cp.b 0xC0042000 0x22000000 0x210000; bootm"
 #define CONFIG_BOOTARGS		"console=ttyS0,115200 " \
 				"root=/dev/mtdblock0 " \
-				"mtdparts=at91_nand:-(root) "\
+				"mtdparts=atmel_nand:-(root) "\
 				"rw rootfstype=jffs2"
 
 #elif CONFIG_SYS_USE_NANDFLASH
@@ -317,7 +317,7 @@
 #define CONFIG_BOOTCOMMAND	"nand read 0x22000000 0xA0000 0x200000; bootm"
 #define CONFIG_BOOTARGS		"console=ttyS0,115200 " \
 				"root=/dev/mtdblock5 " \
-				"mtdparts=at91_nand:128k(bootstrap)ro,256k(uboot)ro,128k(env1)ro,128k(env2)ro,2M(linux),-(root) " \
+				"mtdparts=atmel_nand:128k(bootstrap)ro,256k(uboot)ro,128k(env1)ro,128k(env2)ro,2M(linux),-(root) " \
 				"rw rootfstype=jffs2"
 
 #endif

include/configs/at91sam9m10g45ek.h

@@ -179,7 +179,7 @@
 #define CONFIG_BOOTCOMMAND	"cp.b 0xC0042000 0x22000000 0x210000; bootm"
 #define CONFIG_BOOTARGS		"console=ttyS0,115200 " \
 				"root=/dev/mtdblock0 " \
-				"mtdparts=at91_nand:-(root) "\
+				"mtdparts=atmel_nand:-(root) "\
 				"rw rootfstype=jffs2"
 
 #else /* CONFIG_SYS_USE_NANDFLASH */
@@ -192,7 +192,7 @@
 #define CONFIG_BOOTCOMMAND	"nand read 0x72000000 0x200000 0x200000; bootm"
 #define CONFIG_BOOTARGS		"console=ttyS0,115200 " \
 				"root=/dev/mtdblock5 " \
-				"mtdparts=at91_nand:128k(bootstrap)ro, \
+				"mtdparts=atmel_nand:128k(bootstrap)ro, \
 				256k(uboot)ro,128k(env1)ro,128k(env2)ro, \
 				2M(linux),-(root) " \
 				"rw rootfstype=jffs2"

include/configs/at91sam9rlek.h

@@ -142,7 +142,7 @@
 #define CONFIG_BOOTCOMMAND	"cp.b 0xC0042000 0x22000000 0x210000; bootm"
 #define CONFIG_BOOTARGS		"console=ttyS0,115200 " \
 				"root=/dev/mtdblock0 " \
-				"mtdparts=at91_nand:-(root) "\
+				"mtdparts=atmel_nand:-(root) "\
 				"rw rootfstype=jffs2"
 
 #else /* CONFIG_SYS_USE_NANDFLASH */
@@ -155,7 +155,7 @@
 #define CONFIG_BOOTCOMMAND	"nand read 0x22000000 0xA0000 0x200000; bootm"
 #define CONFIG_BOOTARGS		"console=ttyS0,115200 " \
 				"root=/dev/mtdblock5 " \
-				"mtdparts=at91_nand:128k(bootstrap)ro,256k(uboot)ro,128k(env1)ro,128k(env2)ro,2M(linux),-(root) " \
+				"mtdparts=atmel_nand:128k(bootstrap)ro,256k(uboot)ro,128k(env1)ro,128k(env2)ro,2M(linux),-(root) " \
 				"rw rootfstype=jffs2"
 
 #endif

include/configs/canyonlands.h

@@ -331,7 +331,11 @@
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
 
 /* I2C bootstrap EEPROM */
+#if defined(CONFIG_ARCHES)
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR	0x54
+#else
 #define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR	0x52
+#endif
 #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET	0
 #define CONFIG_4xx_CONFIG_BLOCKSIZE		16
 

include/configs/cm-bf527.h

@@ -95,7 +95,7 @@
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_SYS_FLASH_PROTECTION
 #define CONFIG_SYS_MAX_FLASH_BANKS	1
-#define CONFIG_SYS_MAX_FLASH_SECT 	64
+#define CONFIG_SYS_MAX_FLASH_SECT 	67
 
 
 /*

include/configs/cm-bf537e.h

@@ -79,7 +79,7 @@
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_SYS_FLASH_PROTECTION
 #define CONFIG_SYS_MAX_FLASH_BANKS	1
-#define CONFIG_SYS_MAX_FLASH_SECT	32
+#define CONFIG_SYS_MAX_FLASH_SECT	35
 
 
 /*

include/configs/pm9261.h

@@ -289,7 +289,7 @@
 #define CONFIG_BOOTCOMMAND	"cp.b 0xC0042000 0x22000000 0x210000; bootm"
 #define CONFIG_BOOTARGS		"console=ttyS0,115200 "			\
 				"root=/dev/mtdblock0 "			\
-				"mtdparts=at91_nand:-(root) "		\
+				"mtdparts=atmel_nand:-(root) "		\
 				"rw rootfstype=jffs2"
 
 #elif defined(CONFIG_SYS_USE_NANDFLASH) /* CONFIG_SYS_USE_NANDFLASH */
@@ -302,7 +302,7 @@
 #define CONFIG_BOOTCOMMAND	"nand read 0x22000000 0xA0000 0x200000; bootm"
 #define CONFIG_BOOTARGS		"console=ttyS0,115200 "			\
 				"root=/dev/mtdblock5 "			\
-				"mtdparts=at91_nand:128k(bootstrap)ro,"	\
+				"mtdparts=atmel_nand:128k(bootstrap)ro,"	\
 				"256k(uboot)ro,128k(env1)ro,"		\
 				"128k(env2)ro,2M(linux),-(root) "	\
 				"rw rootfstype=jffs2"

include/configs/pm9263.h

@@ -310,7 +310,7 @@
 #define CONFIG_BOOTCOMMAND	"cp.b 0xC0042000 0x22000000 0x210000; bootm"
 #define CONFIG_BOOTARGS		"console=ttyS0,115200 " \
 				"root=/dev/mtdblock0 " \
-				"mtdparts=at91_nand:-(root) "\
+				"mtdparts=atmel_nand:-(root) "\
 				"rw rootfstype=jffs2"
 
 #elif defined(CONFIG_SYS_USE_NANDFLASH) /* CFG_USE_NANDFLASH */
@@ -323,7 +323,7 @@
 #define CONFIG_BOOTCOMMAND	"nand read 0x22000000 0xA0000 0x200000; bootm"
 #define CONFIG_BOOTARGS		"console=ttyS0,115200 "		\
 				"root=/dev/mtdblock5 "		\
-				"mtdparts=at91_nand:"		\
+				"mtdparts=atmel_nand:"		\
 					"128k(bootstrap)ro,"	\
 					"256k(uboot)ro,"	\
 					"128k(env1)ro,"		\

include/configs/rd6281a.h

@@ -107,6 +107,7 @@
 #define NAND_MAX_CHIPS			1
 #define CONFIG_SYS_NAND_BASE		0xD8000000	/* KW_DEFADR_NANDF */
 #define NAND_ALLOW_ERASE_ALL		1
+#define CONFIG_SYS_64BIT_VSPRINTF	/* needed for nand_util.c */
 #endif
 
 /*

include/configs/sbc8349.h

@@ -40,24 +40,28 @@
 #define CONFIG_MPC8349		1	/* MPC8349 specific */
 #define CONFIG_SBC8349		1	/* WRS SBC8349 board specific */
 
-#undef CONFIG_PCI
 /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */
 #undef CONFIG_MPC83XX_PCI2		/* support for 2nd PCI controller */
 
-#define PCI_66M
-#ifdef PCI_66M
-#define CONFIG_83XX_CLKIN	66000000	/* in Hz */
-#else
+/*
+ * The default if PCI isn't enabled, or if no PCI clk setting is given
+ * is 66MHz; this is what the board defaults to when the PCI slot is
+ * physically empty.  The board will automatically (i.e w/o jumpers)
+ * clock down to 33MHz if you insert a 33MHz PCI card.
+ */
+#ifdef PCI_33M
 #define CONFIG_83XX_CLKIN	33000000	/* in Hz */
+#else	/* 66M */
+#define CONFIG_83XX_CLKIN	66000000	/* in Hz */
 #endif
 
 #ifndef CONFIG_SYS_CLK_FREQ
-#ifdef PCI_66M
-#define CONFIG_SYS_CLK_FREQ	66000000
-#define HRCWL_CSB_TO_CLKIN	HRCWL_CSB_TO_CLKIN_4X1
-#else
+#ifdef PCI_33M
 #define CONFIG_SYS_CLK_FREQ	33000000
 #define HRCWL_CSB_TO_CLKIN	HRCWL_CSB_TO_CLKIN_8X1
+#else	/* 66M */
+#define CONFIG_SYS_CLK_FREQ	66000000
+#define HRCWL_CSB_TO_CLKIN	HRCWL_CSB_TO_CLKIN_4X1
 #endif
 #endif
 
@@ -153,7 +157,6 @@
 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
 
-#define CONFIG_SYS_MID_FLASH_JUMP	0x7F000000
 #define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 
 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
@@ -627,7 +630,7 @@
 #define CONFIG_GATEWAYIP	192.168.1.1
 #define CONFIG_NETMASK		255.255.255.0
 
-#define CONFIG_LOADADDR		500000	/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		800000	/* default location for tftp and bootm */
 
 #define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
 #undef  CONFIG_BOOTARGS			/* the boot command will set bootargs */
@@ -654,7 +657,7 @@
 	"update=protect off ff800000 ff83ffff; "			\
 		"era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0"	\
 	"upd=run load update\0"						\
-	"fdtaddr=400000\0"						\
+	"fdtaddr=780000\0"						\
 	"fdtfile=sbc8349.dtb\0"						\
 	""