Update CHANGELOG; prepare Prepare v2009.11

Signed-off-by: Wolfgang Denk <wd@denx.de>

MAINTAINERS

@@ -277,7 +277,7 @@ Nye Liu <nyet@zumanetworks.com>
 
 	ZUMA		MPC7xx_74xx
 
-Jon Loeliger <jdl@freescale.com>
+Kumar Gala <kumar.gala@freescale.com>
 
 	MPC8540ADS	MPC8540
 	MPC8560ADS	MPC8560

MAKEALL

@@ -1,4 +1,4 @@
-#!/bin/sh
+#!/bin/bash
 
 # Print statistics when we exit
 trap exit 1 2 3 15
@@ -39,6 +39,7 @@ LIST=""
 ERR_CNT=0
 ERR_LIST=""
 TOTAL_CNT=0
+RC=0
 
 #########################################################################
 ## MPC5xx Systems
@@ -936,6 +937,12 @@ build_target() {
 
 	${MAKE} ${JOBS} all 2>&1 >${LOG_DIR}/$target.MAKELOG \
 				| tee ${LOG_DIR}/$target.ERR
+
+	# Check for 'make' errors
+	if [ ${PIPESTATUS[0]} -ne 0 ] ; then
+		RC=1
+	fi
+
 	if [ -s ${LOG_DIR}/$target.ERR ] ; then
 		ERR_CNT=$((ERR_CNT + 1))
 		ERR_LIST="${ERR_LIST} $target"
@@ -959,6 +966,8 @@ print_stats() {
 		echo "Boards with warnings or errors: ${ERR_CNT} (${ERR_LIST} )"
 	fi
 	echo "----------------------------------------------------------"
+
+	exit $RC
 }
 
 #-----------------------------------------------------------------------

Makefile

@@ -24,7 +24,7 @@
 VERSION = 2009
 PATCHLEVEL = 11
 SUBLEVEL =
-EXTRAVERSION = -rc1
+EXTRAVERSION =
 ifneq "$(SUBLEVEL)" ""
 U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
 else
@@ -3257,6 +3257,7 @@ zylonite_config :
 #########################################################################
 
 apollon_config		: unconfig
+	@mkdir -p $(obj)include
 	@echo "#define CONFIG_ONENAND_U_BOOT" > $(obj)include/config.h
 	@$(MKCONFIG) $(@:_config=) arm arm1136 apollon NULL omap24xx
 	@echo "CONFIG_ONENAND_U_BOOT = y" >> $(obj)include/config.mk

README

@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2000 - 2008
+# (C) Copyright 2000 - 2009
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
@@ -138,6 +138,7 @@ U-Boot will always have a patchlevel of "0".
 Directory Hierarchy:
 ====================
 
+- api		Machine/arch independent API for external apps
 - board		Board dependent files
 - common	Misc architecture independent functions
 - cpu		CPU specific files
@@ -178,8 +179,8 @@ Directory Hierarchy:
 - disk		Code for disk drive partition handling
 - doc		Documentation (don't expect too much)
 - drivers	Commonly used device drivers
-- dtt		Digital Thermometer and Thermostat drivers
 - examples	Example code for standalone applications, etc.
+- fs		Filesystem code (cramfs, ext2, jffs2, etc.)
 - include	Header Files
 - lib_arm	Files generic to ARM	 architecture
 - lib_avr32	Files generic to AVR32	 architecture
@@ -187,9 +188,12 @@ Directory Hierarchy:
 - lib_generic	Files generic to all	 architectures
 - lib_i386	Files generic to i386	 architecture
 - lib_m68k	Files generic to m68k	 architecture
+- lib_microblaze Files generic to microblaze architecture
 - lib_mips	Files generic to MIPS	 architecture
 - lib_nios	Files generic to NIOS	 architecture
+- lib_nios2	Files generic to NIOS2	 architecture
 - lib_ppc	Files generic to PowerPC architecture
+- lib_sh	Files generic to SH	 architecture
 - lib_sparc	Files generic to SPARC	 architecture
 - libfdt	Library files to support flattened device trees
 - net		Networking code
@@ -842,20 +846,20 @@ The following options need to be configured:
 			Define this to use i/o functions instead of macros
 			(some hardware wont work with macros)
 
-		CONFIG_DRIVER_SMC911X
+		CONFIG_SMC911X
 		Support for SMSC's LAN911x and LAN921x chips
 
-			CONFIG_DRIVER_SMC911X_BASE
+			CONFIG_SMC911X_BASE
 			Define this to hold the physical address
 			of the device (I/O space)
 
-			CONFIG_DRIVER_SMC911X_32_BIT
+			CONFIG_SMC911X_32_BIT
 			Define this if data bus is 32 bits
 
-			CONFIG_DRIVER_SMC911X_16_BIT
+			CONFIG_SMC911X_16_BIT
 			Define this if data bus is 16 bits. If your processor
 			automatically converts one 32 bit word to two 16 bit
-			words you may also try CONFIG_DRIVER_SMC911X_32_BIT.
+			words you may also try CONFIG_SMC911X_32_BIT.
 
 - USB Support:
 		At the moment only the UHCI host controller is
@@ -1889,25 +1893,6 @@ The following options need to be configured:
 		example, some LED's) on your board. At the moment,
 		the following checkpoints are implemented:
 
-- Automatic software updates via TFTP server
-		CONFIG_UPDATE_TFTP
-		CONFIG_UPDATE_TFTP_CNT_MAX
-		CONFIG_UPDATE_TFTP_MSEC_MAX
-
-		These options enable and control the auto-update feature;
-		for a more detailed description refer to doc/README.update.
-
-- MTD Support (mtdparts command, UBI support)
-		CONFIG_MTD_DEVICE
-
-		Adds the MTD device infrastructure from the Linux kernel.
-		Needed for mtdparts command support.
-
-		CONFIG_MTD_PARTITIONS
-
-		Adds the MTD partitioning infrastructure from the Linux
-		kernel. Needed for UBI support.
-
 Legacy uImage format:
 
   Arg	Where			When
@@ -2061,6 +2046,25 @@ FIT uImage format:
  -150	common/cmd_nand.c	Incorrect FIT image format
   151	common/cmd_nand.c	FIT image format OK
 
+- Automatic software updates via TFTP server
+		CONFIG_UPDATE_TFTP
+		CONFIG_UPDATE_TFTP_CNT_MAX
+		CONFIG_UPDATE_TFTP_MSEC_MAX
+
+		These options enable and control the auto-update feature;
+		for a more detailed description refer to doc/README.update.
+
+- MTD Support (mtdparts command, UBI support)
+		CONFIG_MTD_DEVICE
+
+		Adds the MTD device infrastructure from the Linux kernel.
+		Needed for mtdparts command support.
+
+		CONFIG_MTD_PARTITIONS
+
+		Adds the MTD partitioning infrastructure from the Linux
+		kernel. Needed for UBI support.
+
 
 Modem Support:
 --------------

board/atmel/at91sam9261ek/at91sam9261ek.c

@@ -265,11 +265,12 @@ int board_init(void)
 }
 
 #ifdef CONFIG_DRIVER_DM9000
- int board_eth_init(bd_t *bis)
- {
+int board_eth_init(bd_t *bis)
+{
 	return dm9000_initialize(bis);
- }
- #endif
+}
+#endif
+
 int dram_init(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM;

board/esd/plu405/plu405.c

@@ -26,6 +26,7 @@
 #include <asm/io.h>
 #include <command.h>
 #include <malloc.h>
+#include <sja1000.h>
 
 #undef FPGA_DEBUG
 
@@ -61,6 +62,34 @@ au_image_t au_image[] = {
 
 int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
 
+/*
+ * generate a short spike on the CAN tx line
+ * to bring the couplers in sync
+ */
+void init_coupler(u32 addr)
+{
+	struct sja1000_basic_s *ctrl = (struct sja1000_basic_s *)addr;
+
+	/* reset */
+	out_8(&ctrl->cr, CR_RR);
+
+	/* dominant */
+	out_8(&ctrl->btr0, 0x00); /* btr setup is required */
+	out_8(&ctrl->btr1, 0x14); /* we use 1Mbit/s */
+	out_8(&ctrl->oc, OC_TP1 | OC_TN1 | OC_POL1 |
+	      OC_TP0 | OC_TN0 | OC_POL0 | OC_MODE1);
+	out_8(&ctrl->cr, 0x00);
+
+	/* delay */
+	in_8(&ctrl->cr);
+	in_8(&ctrl->cr);
+	in_8(&ctrl->cr);
+	in_8(&ctrl->cr);
+
+	/* reset */
+	out_8(&ctrl->cr, CR_RR);
+}
+
 /* Prototypes */
 int gunzip(void *, int, unsigned char *, unsigned long *);
 
@@ -214,6 +243,13 @@ int misc_init_r(void)
 	out_8((void *)DUART1_BA + 1, fctr); /* write FCTR */
 	out_8((void *)DUART1_BA + 3, 0);    /* write LCR */
 
+	/*
+	 * Init magnetic couplers
+	 */
+	if (!getenv("noinitcoupler")) {
+		init_coupler(CAN0_BA);
+		init_coupler(CAN1_BA);
+	}
 	return 0;
 }
 

board/esd/vom405/vom405.c

@@ -26,11 +26,40 @@
 #include <asm/io.h>
 #include <command.h>
 #include <malloc.h>
+#include <sja1000.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 extern void lxt971_no_sleep(void);
 
+/*
+ * generate a short spike on the CAN tx line
+ * to bring the couplers in sync
+ */
+void init_coupler(u32 addr)
+{
+	struct sja1000_basic_s *ctrl = (struct sja1000_basic_s *)addr;
+
+	/* reset */
+	out_8(&ctrl->cr, CR_RR);
+
+	/* dominant */
+	out_8(&ctrl->btr0, 0x00); /* btr setup is required */
+	out_8(&ctrl->btr1, 0x14); /* we use 1Mbit/s */
+	out_8(&ctrl->oc, OC_TP1 | OC_TN1 | OC_POL1 |
+	      OC_TP0 | OC_TN0 | OC_POL0 | OC_MODE1);
+	out_8(&ctrl->cr, 0x00);
+
+	/* delay */
+	in_8(&ctrl->cr);
+	in_8(&ctrl->cr);
+	in_8(&ctrl->cr);
+	in_8(&ctrl->cr);
+
+	/* reset */
+	out_8(&ctrl->cr, CR_RR);
+}
+
 int board_early_init_f (void)
 {
 	/*
@@ -77,6 +106,12 @@ int misc_init_r (void)
 	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
 	gd->bd->bi_flashoffset = 0;
 
+	/*
+	 * Init magnetic coupler
+	 */
+	if (!getenv("noinitcoupler"))
+		init_coupler(CAN_BA);
+
 	return (0);
 }
 

board/espt/lowlevel_init.S

@@ -72,15 +72,7 @@ lowlevel_init:
 	/* set DDR-SDRAM dummy read */
 	write32 MMSEL_A, MMSEL_D
 
-	mov.l	MMSEL_A, r0
-	synco
-	mov.l	@r0, r1
-	synco
-
-	mov.l	CS0_A, r0
-	synco
-	mov.l	@r0, r1
-	synco
+	write32 MMSEL_A, CS0_A
 
 	/* set DDR-SDRAM bus/endian etc */
 	write32 MIM_U_A, MIM_U_D

board/freescale/mpc8260ads/mpc8260ads.c

@@ -550,24 +550,11 @@ void pci_init_board(void)
 #endif
 
 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_blob_update(void *blob, bd_t *bd)
-{
-	int ret;
-
-	ret = fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
-
-	if (ret < 0) {
-		printf("ft_blob_update(): cannot set /memory/reg "
-			"property err:%s\n", fdt_strerror(ret));
-	}
-}
-
 void ft_board_setup(void *blob, bd_t *bd)
 {
 	ft_cpu_setup(blob, bd);
 #ifdef CONFIG_PCI
 	ft_pci_setup(blob, bd);
 #endif
-	ft_blob_update(blob, bd);
 }
 #endif

board/freescale/mpc8572ds/mpc8572ds.c

@@ -199,7 +199,7 @@ void pci_init_board(void)
 				pcie_ep ? "End Point" : "Root Complex",
 				pci_info[num].regs);
 		first_free_busno = fsl_pci_init_port(&pci_info[num++],
-				&pcie3_hose, first_free_busno, pcie_ep);
+					&pcie3_hose, first_free_busno);
 		/*
 		 * Activate ULI1575 legacy chip by performing a fake
 		 * memory access.  Needed to make ULI RTC work.
@@ -231,7 +231,7 @@ void pci_init_board(void)
 				pcie_ep ? "End Point" : "Root Complex",
 				pci_info[num].regs);
 		first_free_busno = fsl_pci_init_port(&pci_info[num++],
-				&pcie2_hose, first_free_busno, pcie_ep);
+					&pcie2_hose, first_free_busno);
 	} else {
 		printf ("    PCIE2: disabled\n");
 	}
@@ -251,7 +251,7 @@ void pci_init_board(void)
 				pcie_ep ? "End Point" : "Root Complex",
 				pci_info[num].regs);
 		first_free_busno = fsl_pci_init_port(&pci_info[num++],
-				&pcie1_hose, first_free_busno, pcie_ep);
+					&pcie1_hose, first_free_busno);
 	} else {
 		printf ("    PCIE1: disabled\n");
 	}

board/freescale/mpc8610hpcd/mpc8610hpcd.c

@@ -127,11 +127,6 @@ initdram(int board_type)
 	dram_size = fixed_sdram();
 #endif
 
-#if defined(CONFIG_SYS_RAMBOOT)
-	puts(" DDR: ");
-	return dram_size;
-#endif
-
 	puts(" DDR: ");
 	return dram_size;
 }

board/freescale/mpc8641hpcn/mpc8641hpcn.c

@@ -74,11 +74,6 @@ initdram(int board_type)
 	dram_size = fixed_sdram();
 #endif
 
-#if defined(CONFIG_SYS_RAMBOOT)
-	puts("    DDR: ");
-	return dram_size;
-#endif
-
 	puts("    DDR: ");
 	return dram_size;
 }

board/freescale/p1_p2_rdb/pci.c

@@ -71,7 +71,7 @@ void pci_init_board(void)
 				pcie_ep ? "End Point" : "Root Complex",
 				pci_info[num].regs);
 		first_free_busno = fsl_pci_init_port(&pci_info[num++],
-					&pcie2_hose, first_free_busno, pcie_ep);
+					&pcie2_hose, first_free_busno);
 	} else {
 		printf ("    PCIE2: disabled\n");
 	}
@@ -90,7 +90,7 @@ void pci_init_board(void)
 				pcie_ep ? "End Point" : "Root Complex",
 				pci_info[num].regs);
 		first_free_busno = fsl_pci_init_port(&pci_info[num++],
-					&pcie1_hose, first_free_busno, pcie_ep);
+					&pcie1_hose, first_free_busno);
 	} else {
 		printf ("    PCIE1: disabled\n");
 	}

board/freescale/p2020ds/p2020ds.c

@@ -227,7 +227,7 @@ void pci_init_board(void)
 				pcie_ep ? "End Point" : "Root Complex",
 				pci_info[num].regs);
 		first_free_busno = fsl_pci_init_port(&pci_info[num++],
-				&pcie2_hose, first_free_busno, pcie_ep);
+					&pcie2_hose, first_free_busno);
 
 		/*
 		 * The workaround doesn't work on p2020 because the location
@@ -267,7 +267,7 @@ void pci_init_board(void)
 				pcie_ep ? "End Point" : "Root Complex",
 				pci_info[num].regs);
 		first_free_busno = fsl_pci_init_port(&pci_info[num++],
-				&pcie3_hose, first_free_busno, pcie_ep);
+					&pcie3_hose, first_free_busno);
 	} else {
 		printf("    PCIE3: disabled\n");
 	}
@@ -286,7 +286,7 @@ void pci_init_board(void)
 				pcie_ep ? "End Point" : "Root Complex",
 				pci_info[num].regs);
 		first_free_busno = fsl_pci_init_port(&pci_info[num++],
-				&pcie1_hose, first_free_busno, pcie_ep);
+					&pcie1_hose, first_free_busno);
 	} else {
 		printf("    PCIE1: disabled\n");
 	}

board/ids8247/ids8247.c

@@ -400,24 +400,8 @@ int board_nand_init(struct nand_chip *nand)
 #endif	/* CONFIG_CMD_NAND */
 
 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
-/*
- * update "memory" property in the blob
- */
-void ft_blob_update(void *blob, bd_t *bd)
-{
-	int ret;
-
-	ret = fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
-
-	if (ret < 0) {
-		printf("ft_blob_update(): cannot set /memory/reg "
-			"property err:%s\n", fdt_strerror(ret));
-	}
-}
-
 void ft_board_setup(void *blob, bd_t *bd)
 {
 	ft_cpu_setup( blob, bd);
-	ft_blob_update(blob, bd);
 }
 #endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */

board/keymile/mgcoge/mgcoge.c

@@ -312,11 +312,10 @@ int hush_init_var (void)
 
 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
 /*
- * update "memory" property in the blob
+ * update "flash" property in the blob
  */
 void ft_blob_update (void *blob, bd_t *bd)
 {
-	ulong memory_data[2] = {0};
 	ulong *flash_data = NULL;
 	ulong	flash_reg[6] = {0};
 	flash_info_t	*info;
@@ -324,11 +323,6 @@ void ft_blob_update (void *blob, bd_t *bd)
 	int	size;
 	int	i = 0;
 
-	memory_data[0] = cpu_to_be32 (bd->bi_memstart);
-	memory_data[1] = cpu_to_be32 (bd->bi_memsize);
-	fdt_set_node_and_value (blob, "/memory", "reg", memory_data,
-				sizeof (memory_data));
-
 	len = fdt_get_node_and_value (blob, "/localbus", "ranges",
 					(void *)&flash_data);
 

board/muas3001/muas3001.c

@@ -308,25 +308,9 @@ int board_early_init_r (void)
 void ft_blob_update (void *blob, bd_t *bd)
 {
 	int ret, nodeoffset = 0;
-	ulong memory_data[2] = {0};
 	ulong flash_data[4] = {0};
 	ulong	speed = 0;
 
-	memory_data[0] = cpu_to_be32 (bd->bi_memstart);
-	memory_data[1] = cpu_to_be32 (bd->bi_memsize);
-
-	nodeoffset = fdt_path_offset (blob, "/memory");
-	if (nodeoffset >= 0) {
-		ret = fdt_setprop (blob, nodeoffset, "reg", memory_data,
-					sizeof(memory_data));
-	if (ret < 0)
-		printf ("ft_blob_update): cannot set /memory/reg "
-			"property err:%s\n", fdt_strerror (ret));
-	} else {
-		/* memory node is required in dts */
-		printf ("ft_blob_update(): cannot find /memory node "
-			"err:%s\n", fdt_strerror(nodeoffset));
-	}
 	/* update Flash addr, size */
 	flash_data[2] = cpu_to_be32 (CONFIG_SYS_FLASH_BASE);
 	flash_data[3] = cpu_to_be32 (CONFIG_SYS_FLASH_SIZE);

board/mucmc52/mucmc52.c

@@ -31,6 +31,7 @@
  */
 
 #include <common.h>
+#include <fdt_support.h>
 #include <mpc5xxx.h>
 #include <pci.h>
 #include <malloc.h>
@@ -403,5 +404,6 @@ void pci_init_board (void)
 void ft_board_setup(void *blob, bd_t *bd)
 {
 	ft_cpu_setup(blob, bd);
+	fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
 }
 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */

board/pandora/pandora.h

@@ -219,7 +219,8 @@ const omap3_sysinfo sysinfo = {
 	MUX_VAL(CP(UART2_RX),		(IEN  | PTD | EN  | M4)) /*GPIO_147,*/\
 								 /*UART2_RX*/\
  /*Serial Interface (Peripheral boot, Linux console, on AV connector)*/\
-	MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTD | DIS | M0)) /*UART3_RX*/\
+ /*RX pulled up to avoid noise when nothing is connected to serial port*/\
+	MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTU | EN  | M0)) /*UART3_RX*/\
 	MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M0)) /*UART3_TX*/\
  /*LEDs (Controlled by OMAP)*/\
 	MUX_VAL(CP(MMC1_DAT6),		(IDIS | PTD | DIS | M4)) /*GPIO_128*/\

board/renesas/sh7785lcr/lowlevel_init.S

@@ -178,60 +178,6 @@ lbsc_end:
 
 	.align 4
 
-/*------- LBSC -------*/
-MMSELR_A:	.long	0xfc400020
-#if defined(CONFIG_SH_32BIT)
-MMSELR_D:	.long	0xa5a50005
-#else
-MMSELR_D:	.long	0xa5a50002
-#endif
-
-/*------- DBSC2 -------*/
-#define DBSC2_BASE	0xfe800000
-DBSC2_DBSTATE_A:	.long	DBSC2_BASE + 0x0c
-DBSC2_DBEN_A:		.long	DBSC2_BASE + 0x10
-DBSC2_DBCMDCNT_A:	.long	DBSC2_BASE + 0x14
-DBSC2_DBCONF_A:		.long	DBSC2_BASE + 0x20
-DBSC2_DBTR0_A:		.long	DBSC2_BASE + 0x30
-DBSC2_DBTR1_A:		.long	DBSC2_BASE + 0x34
-DBSC2_DBTR2_A:		.long	DBSC2_BASE + 0x38
-DBSC2_DBRFCNT0_A:	.long	DBSC2_BASE + 0x40
-DBSC2_DBRFCNT1_A:	.long	DBSC2_BASE + 0x44
-DBSC2_DBRFCNT2_A:	.long	DBSC2_BASE + 0x48
-DBSC2_DBRFSTS_A:	.long	DBSC2_BASE + 0x4c
-DBSC2_DBFREQ_A:		.long	DBSC2_BASE + 0x50
-DBSC2_DBDICODTOCD_A:	.long	DBSC2_BASE + 0x54
-DBSC2_DBMRCNT_A:	.long	DBSC2_BASE + 0x60
-DDR_DUMMY_ACCESS_A:	.long	0x40000000
-
-DBSC2_DBCONF_D:		.long	0x00630002
-DBSC2_DBTR0_D:		.long	0x050b1f04
-DBSC2_DBTR1_D:		.long	0x00040204
-DBSC2_DBTR2_D:		.long	0x02100308
-DBSC2_DBFREQ_D1:	.long	0x00000000
-DBSC2_DBFREQ_D2:	.long	0x00000100
-DBSC2_DBDICODTOCD_D:	.long	0x000f0907
-
-DBSC2_DBCMDCNT_D_CKE_H:	.long	0x00000003
-DBSC2_DBCMDCNT_D_PALL:	.long	0x00000002
-DBSC2_DBCMDCNT_D_REF:	.long	0x00000004
-
-DBSC2_DBMRCNT_D_EMRS2:	.long	0x00020000
-DBSC2_DBMRCNT_D_EMRS3:	.long	0x00030000
-DBSC2_DBMRCNT_D_EMRS1_1:	.long	0x00010006
-DBSC2_DBMRCNT_D_EMRS1_2:	.long	0x00010386
-DBSC2_DBMRCNT_D_MRS_1:	.long	0x00000952
-DBSC2_DBMRCNT_D_MRS_2:	.long	0x00000852
-
-DBSC2_DBEN_D:		.long	0x00000001
-
-DBSC2_DBPDCNT0_D3:	.long	0x00000080
-DBSC2_DBRFCNT1_D:	.long	0x00000926
-DBSC2_DBRFCNT2_D:	.long	0x00fe00fe
-DBSC2_DBRFCNT0_D:	.long	0x00010000
-
-WAIT_200US:	.long	33333
-
 /*------- GPIO -------*/
 PACR_D:		.long	0x0000
 PBCR_D:		.long	0x0000
@@ -291,6 +237,59 @@ PPUPR2_A:	.long	GPIO_BASE + 0x62
 P1MSELR_A:	.long	GPIO_BASE + 0x80
 P2MSELR_A:	.long	GPIO_BASE + 0x82
 
+MMSELR_A:      .long   0xfc400020
+#if defined(CONFIG_SH_32BIT)
+MMSELR_D:      .long   0xa5a50005
+#else
+MMSELR_D:      .long   0xa5a50002
+#endif
+
+/*------- DBSC2 -------*/
+#define DBSC2_BASE	0xfe800000
+DBSC2_DBSTATE_A:	.long	DBSC2_BASE + 0x0c
+DBSC2_DBEN_A:		.long	DBSC2_BASE + 0x10
+DBSC2_DBCMDCNT_A:	.long	DBSC2_BASE + 0x14
+DBSC2_DBCONF_A:		.long	DBSC2_BASE + 0x20
+DBSC2_DBTR0_A:		.long	DBSC2_BASE + 0x30
+DBSC2_DBTR1_A:		.long	DBSC2_BASE + 0x34
+DBSC2_DBTR2_A:		.long	DBSC2_BASE + 0x38
+DBSC2_DBRFCNT0_A:	.long	DBSC2_BASE + 0x40
+DBSC2_DBRFCNT1_A:	.long	DBSC2_BASE + 0x44
+DBSC2_DBRFCNT2_A:	.long	DBSC2_BASE + 0x48
+DBSC2_DBRFSTS_A:	.long	DBSC2_BASE + 0x4c
+DBSC2_DBFREQ_A:		.long	DBSC2_BASE + 0x50
+DBSC2_DBDICODTOCD_A:.long	DBSC2_BASE + 0x54
+DBSC2_DBMRCNT_A:	.long	DBSC2_BASE + 0x60
+DDR_DUMMY_ACCESS_A:	.long	0x40000000
+
+DBSC2_DBCONF_D:		.long	0x00630002
+DBSC2_DBTR0_D:		.long	0x050b1f04
+DBSC2_DBTR1_D:		.long	0x00040204
+DBSC2_DBTR2_D:		.long	0x02100308
+DBSC2_DBFREQ_D1:	.long	0x00000000
+DBSC2_DBFREQ_D2:	.long	0x00000100
+DBSC2_DBDICODTOCD_D:.long	0x000f0907
+
+DBSC2_DBCMDCNT_D_CKE_H:	.long	0x00000003
+DBSC2_DBCMDCNT_D_PALL:	.long	0x00000002
+DBSC2_DBCMDCNT_D_REF:	.long	0x00000004
+
+DBSC2_DBMRCNT_D_EMRS2:	.long	0x00020000
+DBSC2_DBMRCNT_D_EMRS3:	.long	0x00030000
+DBSC2_DBMRCNT_D_EMRS1_1:	.long	0x00010006
+DBSC2_DBMRCNT_D_EMRS1_2:	.long	0x00010386
+DBSC2_DBMRCNT_D_MRS_1:	.long	0x00000952
+DBSC2_DBMRCNT_D_MRS_2:	.long	0x00000852
+
+DBSC2_DBEN_D:		.long	0x00000001
+
+DBSC2_DBPDCNT0_D3:	.long	0x00000080
+DBSC2_DBRFCNT1_D:	.long	0x00000926
+DBSC2_DBRFCNT2_D:	.long	0x00fe00fe
+DBSC2_DBRFCNT0_D:	.long	0x00010000
+
+WAIT_200US:    .long   33333
+
 /*------- LBSC -------*/
 PASCR_A:		.long	0xff000070
 PASCR_32BIT_MODE:	.long	0x80000000	/* check booting mode */

board/sbc8548/sbc8548.c

@@ -359,7 +359,7 @@ pci_init_board(void)
 
 		SET_STD_PCI_INFO(pci_info[num], 1);
 		first_free_busno = fsl_pci_init_port(&pci_info[num++],
-					&pci1_hose, first_free_busno, 0);
+					&pci1_hose, first_free_busno);
 	} else {
 		printf ("    PCI: disabled\n");
 	}
@@ -378,7 +378,7 @@ pci_init_board(void)
 		SET_STD_PCIE_INFO(pci_info[num], 1);
 		printf ("    PCIE at base address %lx\n", pci_info[num].regs);
 		first_free_busno = fsl_pci_init_port(&pci_info[num++],
-					&pcie1_hose, first_free_busno, 0);
+					&pcie1_hose, first_free_busno);
 	} else {
 		printf ("    PCIE: disabled\n");
 	}

board/sbc8641d/sbc8641d.c

@@ -62,11 +62,6 @@ phys_size_t initdram (int board_type)
 	dram_size = fixed_sdram ();
 #endif
 
-#if defined(CONFIG_SYS_RAMBOOT)
-	puts ("    DDR: ");
-	return dram_size;
-#endif
-
 	puts ("    DDR: ");
 	return dram_size;
 }

board/uc101/uc101.c

@@ -31,6 +31,7 @@
  */
 
 #include <common.h>
+#include <fdt_support.h>
 #include <mpc5xxx.h>
 #include <pci.h>
 #include <malloc.h>
@@ -376,5 +377,6 @@ void hw_watchdog_reset(void)
 void ft_board_setup(void *blob, bd_t *bd)
 {
 	ft_cpu_setup(blob, bd);
+	fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
 }
 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */

common/Makefile

@@ -29,7 +29,6 @@ AOBJS	=
 
 # core
 COBJS-y += main.o
-COBJS-y += circbuf.o
 COBJS-y += console.o
 COBJS-y += command.o
 COBJS-y += dlmalloc.o

common/cmd_bootm.c

@@ -129,7 +129,7 @@ int do_bootelf (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
 static boot_os_fn do_bootm_integrity;
 #endif
 
-boot_os_fn * boot_os[] = {
+static boot_os_fn *boot_os[] = {
 #ifdef CONFIG_BOOTM_LINUX
 	[IH_OS_LINUX] = do_bootm_linux,
 #endif
@@ -453,8 +453,8 @@ cmd_tbl_t cmd_bootm_sub[] = {
 #ifdef CONFIG_OF_LIBFDT
 	U_BOOT_CMD_MKENT(fdt, 0, 1, (void *)BOOTM_STATE_FDT, "", ""),
 #endif
-	U_BOOT_CMD_MKENT(bdt, 0, 1, (void *)BOOTM_STATE_OS_BD_T, "", ""),
 	U_BOOT_CMD_MKENT(cmdline, 0, 1, (void *)BOOTM_STATE_OS_CMDLINE, "", ""),
+	U_BOOT_CMD_MKENT(bdt, 0, 1, (void *)BOOTM_STATE_OS_BD_T, "", ""),
 	U_BOOT_CMD_MKENT(prep, 0, 1, (void *)BOOTM_STATE_OS_PREP, "", ""),
 	U_BOOT_CMD_MKENT(go, 0, 1, (void *)BOOTM_STATE_OS_GO, "", ""),
 };
@@ -524,7 +524,7 @@ int do_bootm_subcommand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		}
 			break;
 #endif
-#ifdef CONFIG_OF_LIBFDT
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_SYS_BOOTMAPSZ)
 		case BOOTM_STATE_FDT:
 		{
 			ulong bootmap_base = getenv_bootm_low();
@@ -1000,8 +1000,8 @@ U_BOOT_CMD(
 #if defined(CONFIG_OF_LIBFDT)
 	"\tfdt     - relocate flat device tree\n"
 #endif
-	"\tbdt     - OS specific bd_t processing\n"
 	"\tcmdline - OS specific command line processing/setup\n"
+	"\tbdt     - OS specific bd_t processing\n"
 	"\tprep    - OS specific prep before relocation or go\n"
 	"\tgo      - start OS"
 );

common/cmd_cache.c

@@ -27,8 +27,6 @@
 #include <common.h>
 #include <command.h>
 
-#if defined(CONFIG_CMD_CACHE)
-
 static int on_off (const char *);
 
 int do_icache ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
@@ -108,5 +106,3 @@ U_BOOT_CMD(
 	"[on, off]\n"
 	"    - enable or disable data (writethrough) cache"
 );
-
-#endif

common/cmd_date.c

@@ -71,9 +71,9 @@ int do_date (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 				/* and write to RTC */
 				rcode = rtc_set (&tm);
 				if(rcode)
-					puts("## Set date failled\n");
+					puts("## Set date failed\n");
 			} else {
-				puts("## Get date failled\n");
+				puts("## Get date failed\n");
 			}
 		}
 		/* FALL TROUGH */
@@ -81,7 +81,7 @@ int do_date (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		rcode = rtc_get (&tm);
 
 		if (rcode) {
-			puts("## Get date failled\n");
+			puts("## Get date failed\n");
 			break;
 		}
 

common/cmd_i2c.c

@@ -315,10 +315,6 @@ int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		/*
 		 * Wait for the write to complete.  The write can take
 		 * up to 10mSec (we allow a little more time).
-		 *
-		 * On some chips, while the write is in progress, the
-		 * chip doesn't respond.  This apparently isn't a
-		 * universal feature so we don't take advantage of it.
 		 */
 /*
  * No write delay with FRAM devices.
@@ -326,14 +322,6 @@ int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 #if !defined(CONFIG_SYS_I2C_FRAM)
 		udelay(11000);
 #endif
-
-#if 0
-		for (timeout = 0; timeout < 10; timeout++) {
-			udelay(2000);
-			if (i2c_probe(chip) == 0)
-				break;
-		}
-#endif
 	}
 
 	return (0);

common/cmd_irq.c

@@ -47,3 +47,12 @@ U_BOOT_CMD(
 	"enable or disable interrupts",
 	"[on, off]"
 );
+
+/* Implemented in $(CPU)/interrupts.c */
+int do_irqinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+
+U_BOOT_CMD(
+	irqinfo,    1,    1,     do_irqinfo,
+	"print information about IRQs",
+	""
+);

common/cmd_license.c

@@ -23,8 +23,6 @@
 
 #include <common.h>
 
-#if defined(CONFIG_CMD_LICENSE)
-
 /* COPYING is currently 15951 bytes in size */
 #define LICENSE_MAX	20480
 
@@ -56,5 +54,3 @@ U_BOOT_CMD(license, 1, 1, do_license,
 	"print GPL license text",
 	""
 );
-
-#endif /* CONFIG_CMD_LICENSE */

common/cmd_mgdisk.c

@@ -24,8 +24,6 @@
 #include <common.h>
 #include <command.h>
 
-#if defined (CONFIG_CMD_MG_DISK)
-
 #include <mg_disk.h>
 
 int do_mg_disk_cmd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
@@ -72,5 +70,3 @@ U_BOOT_CMD(
 	"    - sector read : mgd readsec [sector] [to] [counts]\n"
 	"    - sector write : mgd writesec [from] [sector] [counts]"
 );
-
-#endif

common/cmd_misc.c

@@ -49,17 +49,6 @@ int do_sleep (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return 0;
 }
 
-/* Implemented in $(CPU)/interrupts.c */
-#if defined(CONFIG_CMD_IRQ)
-int do_irqinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
-
-U_BOOT_CMD(
-	irqinfo,    1,    1,     do_irqinfo,
-	"print information about IRQs",
-	""
-);
-#endif
-
 U_BOOT_CMD(
 	sleep ,    2,    1,     do_sleep,
 	"delay execution for some time",

cpu/arm920t/s3c24x0/timer.c

@@ -205,6 +205,8 @@ void reset_cpu(ulong ignored)
 	struct s3c24x0_watchdog *watchdog;
 
 #ifdef CONFIG_TRAB
+	extern void disable_vfd(void);
+
 	disable_vfd();
 #endif
 

cpu/arm_cortexa8/omap3/board.c

@@ -328,7 +328,7 @@ usage:
 
 U_BOOT_CMD(
 	nandecc, 2, 1,	do_switch_ecc,
-	"nandecc - switch OMAP3 NAND ECC calculation algorithm\n",
+	"switch OMAP3 NAND ECC calculation algorithm",
 	"[hw/sw] - Switch between NAND hardware (hw) or software (sw) ecc algorithm"
 );
 

cpu/mpc8260/cpu.c

@@ -318,6 +318,7 @@ void ft_cpu_setup (void *blob, bd_t *bd)
 		"timebase-frequency", OF_TBCLK, 1);
 	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
 		"clock-frequency", bd->bi_intfreq, 1);
+	fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
 }
 #endif /* CONFIG_OF_LIBFDT */
 

cpu/mpc83xx/cpu_init.c

@@ -169,6 +169,28 @@ void cpu_init_f (volatile immap_t * im)
 #endif
 #ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
 		(CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) |
+#endif
+		0;
+	__be32 lcrr_mask =
+#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
+		LCRR_DBYP |
+#endif
+#ifdef CONFIG_SYS_LCRR_EADC /* external address delay */
+		LCRR_EADC |
+#endif
+#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
+		LCRR_CLKDIV |
+#endif
+		0;
+	__be32 lcrr_val =
+#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
+		CONFIG_SYS_LCRR_DBYP |
+#endif
+#ifdef CONFIG_SYS_LCRR_EADC
+		CONFIG_SYS_LCRR_EADC |
+#endif
+#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
+		CONFIG_SYS_LCRR_CLKDIV |
 #endif
 		0;
 
@@ -199,6 +221,13 @@ void cpu_init_f (volatile immap_t * im)
 	 */
 	__raw_writel(RMR_CSRE & (1<<RMR_CSRE_SHIFT), &im->reset.rmr);
 
+	/* LCRR - Clock Ratio Register (10.3.1.16)
+	 * write, read, and isync per MPC8379ERM rev.1 CLKDEV field description
+	 */
+	clrsetbits_be32(&im->lbus.lcrr, lcrr_mask, lcrr_val);
+	__raw_readl(&im->lbus.lcrr);
+	isync();
+
 	/* Enable Time Base & Decrementer ( so we will have udelay() )*/
 	setbits_be32(&im->sysconf.spcr, SPCR_TBEN);
 
@@ -331,41 +360,9 @@ void cpu_init_f (volatile immap_t * im)
 
 int cpu_init_r (void)
 {
-	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
 #ifdef CONFIG_QE
 	uint qe_base = CONFIG_SYS_IMMR + 0x00100000; /* QE immr base */
-#endif
-	__be32 lcrr_mask =
-#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
-		LCRR_DBYP |
-#endif
-#ifdef CONFIG_SYS_LCRR_EADC /* external address delay */
-		LCRR_EADC |
-#endif
-#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
-		LCRR_CLKDIV |
-#endif
-		0;
-	__be32 lcrr_val =
-#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
-		CONFIG_SYS_LCRR_DBYP |
-#endif
-#ifdef CONFIG_SYS_LCRR_EADC
-		CONFIG_SYS_LCRR_EADC |
-#endif
-#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
-		CONFIG_SYS_LCRR_CLKDIV |
-#endif
-		0;
 
-	/* LCRR - Clock Ratio Register (10.3.1.16)
-	 * write, read, and isync per MPC8379ERM rev.1 CLKDEV field description
-	 */
-	clrsetbits_be32(&im->lbus.lcrr, lcrr_mask, lcrr_val);
-	__raw_readl(&im->lbus.lcrr);
-	isync();
-
-#ifdef CONFIG_QE
 	qe_init(qe_base);
 	qe_reset();
 #endif

cpu/mpc85xx/release.S

@@ -102,18 +102,22 @@ __secondary_start_page:
 #ifdef CONFIG_BACKSIDE_L2_CACHE
 	/* Enable/invalidate the L2 cache */
 	msync
-	lis	r3,(L2CSR0_L2FI|L2CSR0_L2LFC)@h
-	ori	r3,r3,(L2CSR0_L2FI|L2CSR0_L2LFC)@l
-	mtspr	SPRN_L2CSR0,r3
+	lis	r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@h
+	ori	r2,r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@l
+	mtspr	SPRN_L2CSR0,r2
 1:
 	mfspr	r3,SPRN_L2CSR0
-	andis.	r1,r3,L2CSR0_L2FI@h
+	and.	r1,r3,r2
 	bne	1b
 
 	lis	r3,CONFIG_SYS_INIT_L2CSR0@h
 	ori	r3,r3,CONFIG_SYS_INIT_L2CSR0@l
 	mtspr	SPRN_L2CSR0,r3
 	isync
+2:
+	mfspr	r3,SPRN_L2CSR0
+	andis.	r1,r3,L2CSR0_L2E@h
+	beq	2b
 #endif
 
 #define EPAPR_MAGIC		(0x45504150)

cpu/mpc85xx/tlb.c

@@ -132,10 +132,10 @@ int find_tlb_idx(void *addr, u8 tlbsel)
 void init_addr_map(void)
 {
 	int i;
-	unsigned int max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xff;
+	unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff;
 
 	/* walk all the entries */
-	for (i = 0; i < max_cam; i++) {
+	for (i = 0; i < num_cam; i++) {
 		unsigned long epn;
 		u32 tsize, _mas1;
 		phys_addr_t rpn;

cpu/mpc8xxx/ddr/options.c

@@ -22,9 +22,7 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
 			unsigned int ctrl_num)
 {
 	unsigned int i;
-#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
 	const char *p;
-#endif
 
 	/* Chip select options. */
 
@@ -242,8 +240,10 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
 						simple_strtoul(p, NULL, 0);
 		}
 	}
+#endif
 
-	if( (p = getenv("ba_intlv_ctl")) != NULL) {
+	if( ((p = getenv("ba_intlv_ctl")) != NULL) &&
+		(CONFIG_CHIP_SELECTS_PER_CTRL > 1)) {
 		if (strcmp(p, "cs0_cs1") == 0)
 			popts->ba_intlv_ctl = FSL_DDR_CS0_CS1;
 		else if (strcmp(p, "cs2_cs3") == 0)
@@ -283,7 +283,6 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
 			break;
 		}
 	}
-#endif
 
 	fsl_ddr_board_options(popts, pdimm, ctrl_num);
 

cpu/ppc4xx/44x_spd_ddr2.c

@@ -3160,7 +3160,7 @@ inline void ppc4xx_ibm_ddr2_register_dump(void)
 	PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR3);
 	PPC4xx_IBM_DDR2_DUMP_REGISTER(MMODE);
 	PPC4xx_IBM_DDR2_DUMP_REGISTER(MEMODE);
-	PPC4xx_IBM_DDR2_DUMP_REGISTER(ECCCR);
+	PPC4xx_IBM_DDR2_DUMP_REGISTER(ECCES);
 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
      defined(CONFIG_460EX) || defined(CONFIG_460GT))
 	PPC4xx_IBM_DDR2_DUMP_REGISTER(CID);

doc/README.drivers.eth

@@ -122,10 +122,12 @@ function can be called multiple times in a row.
 
 The recv function should process packets as long as the hardware has them
 readily available before returning.  i.e. you should drain the hardware fifo.
-The common code sets up packet buffers for you already (NetRxPackets), so there
-is no need to allocate your own.  For each packet you receive, you should call
-the NetReceive() function on it with the packet length.  So the pseudo code
-here would look something like:
+For each packet you receive, you should call the NetReceive() function on it
+along with the packet length.  The common code sets up packet buffers for you
+already in the .bss (NetRxPackets), so there should be no need to allocate your
+own.  This doesn't mean you must use the NetRxPackets array however; you're
+free to call the NetReceive() function with any buffer you wish.  So the pseudo
+code here would look something like:
 int ape_recv(struct eth_device *dev)
 {
 	int length, i = 0;
@@ -145,7 +147,8 @@ int ape_recv(struct eth_device *dev)
 }
 
 The halt function should turn off / disable the hardware and place it back in
-its reset state.
+its reset state.  It can be called at any time (before any call to the related
+init function), so make sure it can handle this sort of thing.
 
 So the call graph at this stage would look something like:
 some net operation (ping / tftp / whatever...)

doc/uImage.FIT/kernel.its

@@ -1,6 +1,9 @@
 /*
  * Simple U-boot uImage source file containing a single kernel
  */
+
+/dts-v1/;
+
 / {
 	description = "Simple image with single Linux kernel";
 	#address-cells = <1>;

doc/uImage.FIT/kernel_fdt.its

@@ -1,6 +1,9 @@
 /*
  * Simple U-boot uImage source file containing a single kernel and FDT blob
  */
+
+/dts-v1/;
+
 / {
 	description = "Simple image with single Linux kernel and FDT blob";
 	#address-cells = <1>;

doc/uImage.FIT/multi.its

@@ -1,6 +1,9 @@
 /*
  * U-boot uImage source file with multiple kernels, ramdisks and FDT blobs
  */
+
+/dts-v1/;
+
 / {
 	description = "Various kernels, ramdisks and FDT blobs";
 	#address-cells = <1>;

doc/uImage.FIT/update3.its

@@ -1,6 +1,9 @@
 /*
  * Example Automatic software update file.
  */
+
+/dts-v1/;
+
 / {
 	description = "Automatic software updates: kernel, ramdisk, FDT";
 	#address-cells = <1>;

doc/uImage.FIT/update_uboot.its

@@ -2,6 +2,9 @@
  * Automatic software update for U-Boot
  * Make sure the flashing addresses ('load' prop) is correct for your board!
  */
+
+/dts-v1/;
+
 / {
 	description = "Automatic U-Boot update";
 	#address-cells = <1>;

drivers/mtd/cfi_flash.c

@@ -39,6 +39,7 @@
 #include <asm/io.h>
 #include <asm/byteorder.h>
 #include <environment.h>
+#include <mtd/cfi_flash.h>
 
 /*
  * This file implements a Common Flash Interface (CFI) driver for
@@ -65,100 +66,6 @@
 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
 #endif
 
-#define FLASH_CMD_CFI			0x98
-#define FLASH_CMD_READ_ID		0x90
-#define FLASH_CMD_RESET			0xff
-#define FLASH_CMD_BLOCK_ERASE		0x20
-#define FLASH_CMD_ERASE_CONFIRM		0xD0
-#define FLASH_CMD_WRITE			0x40
-#define FLASH_CMD_PROTECT		0x60
-#define FLASH_CMD_PROTECT_SET		0x01
-#define FLASH_CMD_PROTECT_CLEAR		0xD0
-#define FLASH_CMD_CLEAR_STATUS		0x50
-#define FLASH_CMD_READ_STATUS		0x70
-#define FLASH_CMD_WRITE_TO_BUFFER	0xE8
-#define FLASH_CMD_WRITE_BUFFER_PROG	0xE9
-#define FLASH_CMD_WRITE_BUFFER_CONFIRM	0xD0
-
-#define FLASH_STATUS_DONE		0x80
-#define FLASH_STATUS_ESS		0x40
-#define FLASH_STATUS_ECLBS		0x20
-#define FLASH_STATUS_PSLBS		0x10
-#define FLASH_STATUS_VPENS		0x08
-#define FLASH_STATUS_PSS		0x04
-#define FLASH_STATUS_DPS		0x02
-#define FLASH_STATUS_R			0x01
-#define FLASH_STATUS_PROTECT		0x01
-
-#define AMD_CMD_RESET			0xF0
-#define AMD_CMD_WRITE			0xA0
-#define AMD_CMD_ERASE_START		0x80
-#define AMD_CMD_ERASE_SECTOR		0x30
-#define AMD_CMD_UNLOCK_START		0xAA
-#define AMD_CMD_UNLOCK_ACK		0x55
-#define AMD_CMD_WRITE_TO_BUFFER		0x25
-#define AMD_CMD_WRITE_BUFFER_CONFIRM	0x29
-
-#define AMD_STATUS_TOGGLE		0x40
-#define AMD_STATUS_ERROR		0x20
-
-#define ATM_CMD_UNLOCK_SECT		0x70
-#define ATM_CMD_SOFTLOCK_START		0x80
-#define ATM_CMD_LOCK_SECT		0x40
-
-#define FLASH_CONTINUATION_CODE		0x7F
-
-#define FLASH_OFFSET_MANUFACTURER_ID	0x00
-#define FLASH_OFFSET_DEVICE_ID		0x01
-#define FLASH_OFFSET_DEVICE_ID2		0x0E
-#define FLASH_OFFSET_DEVICE_ID3		0x0F
-#define FLASH_OFFSET_CFI		0x55
-#define FLASH_OFFSET_CFI_ALT		0x555
-#define FLASH_OFFSET_CFI_RESP		0x10
-#define FLASH_OFFSET_PRIMARY_VENDOR	0x13
-/* extended query table primary address */
-#define FLASH_OFFSET_EXT_QUERY_T_P_ADDR	0x15
-#define FLASH_OFFSET_WTOUT		0x1F
-#define FLASH_OFFSET_WBTOUT		0x20
-#define FLASH_OFFSET_ETOUT		0x21
-#define FLASH_OFFSET_CETOUT		0x22
-#define FLASH_OFFSET_WMAX_TOUT		0x23
-#define FLASH_OFFSET_WBMAX_TOUT		0x24
-#define FLASH_OFFSET_EMAX_TOUT		0x25
-#define FLASH_OFFSET_CEMAX_TOUT		0x26
-#define FLASH_OFFSET_SIZE		0x27
-#define FLASH_OFFSET_INTERFACE		0x28
-#define FLASH_OFFSET_BUFFER_SIZE	0x2A
-#define FLASH_OFFSET_NUM_ERASE_REGIONS	0x2C
-#define FLASH_OFFSET_ERASE_REGIONS	0x2D
-#define FLASH_OFFSET_PROTECT		0x02
-#define FLASH_OFFSET_USER_PROTECTION	0x85
-#define FLASH_OFFSET_INTEL_PROTECTION	0x81
-
-#define CFI_CMDSET_NONE			0
-#define CFI_CMDSET_INTEL_EXTENDED	1
-#define CFI_CMDSET_AMD_STANDARD		2
-#define CFI_CMDSET_INTEL_STANDARD	3
-#define CFI_CMDSET_AMD_EXTENDED		4
-#define CFI_CMDSET_MITSU_STANDARD	256
-#define CFI_CMDSET_MITSU_EXTENDED	257
-#define CFI_CMDSET_SST			258
-#define CFI_CMDSET_INTEL_PROG_REGIONS	512
-
-#ifdef CONFIG_SYS_FLASH_CFI_AMD_RESET /* needed for STM_ID_29W320DB on UC100 */
-# undef  FLASH_CMD_RESET
-# define FLASH_CMD_RESET	AMD_CMD_RESET /* use AMD-Reset instead */
-#endif
-
-typedef union {
-	unsigned char c;
-	unsigned short w;
-	unsigned long l;
-	unsigned long long ll;
-} cfiword_t;
-
-#define NUM_ERASE_REGIONS	4 /* max. number of erase regions */
-
 static uint flash_offset_cfi[2] = { FLASH_OFFSET_CFI, FLASH_OFFSET_CFI_ALT };
 static uint flash_verbose = 1;
 
@@ -178,38 +85,6 @@ flash_info_t flash_info[CFI_MAX_FLASH_BANKS];	/* FLASH chips info */
 #define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
 #endif
 
-/* CFI standard query structure */
-struct cfi_qry {
-	u8	qry[3];
-	u16	p_id;
-	u16	p_adr;
-	u16	a_id;
-	u16	a_adr;
-	u8	vcc_min;
-	u8	vcc_max;
-	u8	vpp_min;
-	u8	vpp_max;
-	u8	word_write_timeout_typ;
-	u8	buf_write_timeout_typ;
-	u8	block_erase_timeout_typ;
-	u8	chip_erase_timeout_typ;
-	u8	word_write_timeout_max;
-	u8	buf_write_timeout_max;
-	u8	block_erase_timeout_max;
-	u8	chip_erase_timeout_max;
-	u8	dev_size;
-	u16	interface_desc;
-	u16	max_buf_write_size;
-	u8	num_erase_regions;
-	u32	erase_region_info[NUM_ERASE_REGIONS];
-} __attribute__((packed));
-
-struct cfi_pri_hdr {
-	u8	pri[3];
-	u8	major_version;
-	u8	minor_version;
-} __attribute__((packed));
-
 static void __flash_write8(u8 value, void *addr)
 {
 	__raw_writeb(value, addr);
@@ -452,8 +327,8 @@ static ulong flash_read_long (flash_info_t * info, flash_sect_t sect,
 /*
  * Write a proper sized command to the correct address
  */
-static void flash_write_cmd (flash_info_t * info, flash_sect_t sect,
-			     uint offset, u32 cmd)
+void flash_write_cmd (flash_info_t * info, flash_sect_t sect,
+		      uint offset, u32 cmd)
 {
 
 	void *addr;
@@ -1699,15 +1574,25 @@ static void flash_read_cfi (flash_info_t *info, void *buf,
 		p[i] = flash_read_uchar(info, start + i);
 }
 
+void __flash_cmd_reset(flash_info_t *info)
+{
+	/*
+	 * We do not yet know what kind of commandset to use, so we issue
+	 * the reset command in both Intel and AMD variants, in the hope
+	 * that AMD flash roms ignore the Intel command.
+	 */
+	flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
+	flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+}
+void flash_cmd_reset(flash_info_t *info)
+	__attribute__((weak,alias("__flash_cmd_reset")));
+
 static int __flash_detect_cfi (flash_info_t * info, struct cfi_qry *qry)
 {
 	int cfi_offset;
 
-	/* We do not yet know what kind of commandset to use, so we issue
-	   the reset command in both Intel and AMD variants, in the hope
-	   that AMD flash roms ignore the Intel command. */
-	flash_write_cmd (info, 0, 0, AMD_CMD_RESET);
-	flash_write_cmd (info, 0, 0, FLASH_CMD_RESET);
+	/* Issue FLASH reset command */
+	flash_cmd_reset(info);
 
 	for (cfi_offset=0;
 	     cfi_offset < sizeof(flash_offset_cfi) / sizeof(uint);

drivers/mtd/nand/nand_util.c

@@ -452,7 +452,7 @@ static size_t get_len_incl_bad (nand_info_t *nand, loff_t offset,
 		len_incl_bad += block_len;
 		offset       += block_len;
 
-		if ((offset + len_incl_bad) >= nand->size)
+		if (offset >= nand->size)
 			break;
 	}
 
@@ -490,7 +490,7 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
 
 	len_incl_bad = get_len_incl_bad (nand, offset, *length);
 
-	if ((offset + len_incl_bad) >= nand->size) {
+	if ((offset + len_incl_bad) > nand->size) {
 		printf ("Attempt to write outside the flash area\n");
 		return -EINVAL;
 	}
@@ -562,7 +562,7 @@ int nand_read_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
 
 	len_incl_bad = get_len_incl_bad (nand, offset, *length);
 
-	if ((offset + len_incl_bad) >= nand->size) {
+	if ((offset + len_incl_bad) > nand->size) {
 		printf ("Attempt to read outside the flash area\n");
 		return -EINVAL;
 	}

drivers/mtd/spi/Makefile

@@ -31,6 +31,7 @@ COBJS-$(CONFIG_SPI_FLASH_MACRONIX)	+= macronix.o
 COBJS-$(CONFIG_SPI_FLASH_SPANSION)	+= spansion.o
 COBJS-$(CONFIG_SPI_FLASH_SST)	+= sst.o
 COBJS-$(CONFIG_SPI_FLASH_STMICRO)	+= stmicro.o
+COBJS-$(CONFIG_SPI_FLASH_WINBOND)	+= winbond.o
 COBJS-$(CONFIG_SPI_M95XXX) += eeprom_m95xxx.o
 
 COBJS	:= $(COBJS-y)

drivers/mtd/spi/spi_flash.c

@@ -140,6 +140,11 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
 		flash = spi_flash_probe_macronix(spi, idcode);
 		break;
 #endif
+#ifdef CONFIG_SPI_FLASH_WINBOND
+	case 0xef:
+		flash = spi_flash_probe_winbond(spi, idcode);
+		break;
+#endif
 #ifdef CONFIG_SPI_FLASH_STMICRO
 	case 0x20:
 		flash = spi_flash_probe_stmicro(spi, idcode);

drivers/mtd/spi/spi_flash_internal.h

@@ -49,3 +49,4 @@ struct spi_flash *spi_flash_probe_atmel(struct spi_slave *spi, u8 *idcode);
 struct spi_flash *spi_flash_probe_macronix(struct spi_slave *spi, u8 *idcode);
 struct spi_flash *spi_flash_probe_sst(struct spi_slave *spi, u8 *idcode);
 struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 *idcode);
+struct spi_flash *spi_flash_probe_winbond(struct spi_slave *spi, u8 *idcode);

drivers/mtd/spi/stmicro.c

@@ -281,7 +281,8 @@ int stmicro_erase(struct spi_flash *flash, u32 offset, size_t len)
 
 	ret = 0;
 	for (actual = 0; actual < len; actual++) {
-		cmd[1] = (offset / sector_size) + actual;
+		cmd[1] = offset >> 16;
+		offset += sector_size;
 
 		ret = spi_flash_cmd(flash->spi, CMD_M25PXX_WREN, NULL, 0);
 		if (ret < 0) {

drivers/mtd/spi/winbond.c

@@ -0,0 +1,332 @@
+/*
+ * Copyright 2008, Network Appliance Inc.
+ * Author: Jason McMullan <mcmullan <at> netapp.com>
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <spi_flash.h>
+
+#include "spi_flash_internal.h"
+
+/* M25Pxx-specific commands */
+#define CMD_W25_WREN		0x06	/* Write Enable */
+#define CMD_W25_WRDI		0x04	/* Write Disable */
+#define CMD_W25_RDSR		0x05	/* Read Status Register */
+#define CMD_W25_WRSR		0x01	/* Write Status Register */
+#define CMD_W25_READ		0x03	/* Read Data Bytes */
+#define CMD_W25_FAST_READ	0x0b	/* Read Data Bytes at Higher Speed */
+#define CMD_W25_PP		0x02	/* Page Program */
+#define CMD_W25_SE		0x20	/* Sector (4K) Erase */
+#define CMD_W25_BE		0xd8	/* Block (64K) Erase */
+#define CMD_W25_CE		0xc7	/* Chip Erase */
+#define CMD_W25_DP		0xb9	/* Deep Power-down */
+#define CMD_W25_RES		0xab	/* Release from DP, and Read Signature */
+
+#define WINBOND_ID_W25X16		0x3015
+#define WINBOND_ID_W25X32		0x3016
+#define WINBOND_ID_W25X64		0x3017
+
+#define WINBOND_SR_WIP		(1 << 0)	/* Write-in-Progress */
+
+struct winbond_spi_flash_params {
+	uint16_t	id;
+	/* Log2 of page size in power-of-two mode */
+	uint8_t		l2_page_size;
+	uint16_t	pages_per_sector;
+	uint16_t	sectors_per_block;
+	uint8_t		nr_blocks;
+	const char	*name;
+};
+
+/* spi_flash needs to be first so upper layers can free() it */
+struct winbond_spi_flash {
+	struct spi_flash flash;
+	const struct winbond_spi_flash_params *params;
+};
+
+static inline struct winbond_spi_flash *
+to_winbond_spi_flash(struct spi_flash *flash)
+{
+	return container_of(flash, struct winbond_spi_flash, flash);
+}
+
+static const struct winbond_spi_flash_params winbond_spi_flash_table[] = {
+	{
+		.id			= WINBOND_ID_W25X16,
+		.l2_page_size		= 8,
+		.pages_per_sector	= 16,
+		.sectors_per_block	= 16,
+		.nr_blocks		= 32,
+		.name			= "W25X16",
+	},
+	{
+		.id			= WINBOND_ID_W25X32,
+		.l2_page_size		= 8,
+		.pages_per_sector	= 16,
+		.sectors_per_block	= 16,
+		.nr_blocks		= 64,
+		.name			= "W25X32",
+	},
+	{
+		.id			= WINBOND_ID_W25X64,
+		.l2_page_size		= 8,
+		.pages_per_sector	= 16,
+		.sectors_per_block	= 16,
+		.nr_blocks		= 128,
+		.name			= "W25X64",
+	},
+};
+
+static int winbond_wait_ready(struct spi_flash *flash, unsigned long timeout)
+{
+	struct spi_slave *spi = flash->spi;
+	unsigned long timebase;
+	int ret;
+	u8 status;
+	u8 cmd[4] = { CMD_W25_RDSR, 0xff, 0xff, 0xff };
+
+	ret = spi_xfer(spi, 32, &cmd[0], NULL, SPI_XFER_BEGIN);
+	if (ret) {
+		debug("SF: Failed to send command %02x: %d\n", cmd, ret);
+		return ret;
+	}
+
+	timebase = get_timer(0);
+	do {
+		ret = spi_xfer(spi, 8, NULL, &status, 0);
+		if (ret) {
+			debug("SF: Failed to get status for cmd %02x: %d\n", cmd, ret);
+			return -1;
+		}
+
+		if ((status & WINBOND_SR_WIP) == 0)
+			break;
+
+	} while (get_timer(timebase) < timeout);
+
+	spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END);
+
+	if ((status & WINBOND_SR_WIP) == 0)
+		return 0;
+
+	debug("SF: Timed out on command %02x: %d\n", cmd, ret);
+	/* Timed out */
+	return -1;
+}
+
+/*
+ * Assemble the address part of a command for Winbond devices in
+ * non-power-of-two page size mode.
+ */
+static void winbond_build_address(struct winbond_spi_flash *stm, u8 *cmd, u32 offset)
+{
+	unsigned long page_addr;
+	unsigned long byte_addr;
+	unsigned long page_size;
+	unsigned int page_shift;
+
+	/*
+	 * The "extra" space per page is the power-of-two page size
+	 * divided by 32.
+	 */
+	page_shift = stm->params->l2_page_size;
+	page_size = (1 << page_shift);
+	page_addr = offset / page_size;
+	byte_addr = offset % page_size;
+
+	cmd[0] = page_addr >> (16 - page_shift);
+	cmd[1] = page_addr << (page_shift - 8) | (byte_addr >> 8);
+	cmd[2] = byte_addr;
+}
+
+static int winbond_read_fast(struct spi_flash *flash,
+		u32 offset, size_t len, void *buf)
+{
+	struct winbond_spi_flash *stm = to_winbond_spi_flash(flash);
+	u8 cmd[5];
+
+	cmd[0] = CMD_READ_ARRAY_FAST;
+	winbond_build_address(stm, cmd + 1, offset);
+	cmd[4] = 0x00;
+
+	return spi_flash_read_common(flash, cmd, sizeof(cmd), buf, len);
+}
+
+static int winbond_write(struct spi_flash *flash,
+		u32 offset, size_t len, const void *buf)
+{
+	struct winbond_spi_flash *stm = to_winbond_spi_flash(flash);
+	unsigned long page_addr;
+	unsigned long byte_addr;
+	unsigned long page_size;
+	unsigned int page_shift;
+	size_t chunk_len;
+	size_t actual;
+	int ret;
+	u8 cmd[4];
+
+	page_shift = stm->params->l2_page_size;
+	page_size = (1 << page_shift);
+	page_addr = offset / page_size;
+	byte_addr = offset % page_size;
+
+	ret = spi_claim_bus(flash->spi);
+	if (ret) {
+		debug("SF: Unable to claim SPI bus\n");
+		return ret;
+	}
+
+	for (actual = 0; actual < len; actual += chunk_len) {
+		chunk_len = min(len - actual, page_size - byte_addr);
+
+		cmd[0] = CMD_W25_PP;
+		cmd[1] = page_addr >> (16 - page_shift);
+		cmd[2] = page_addr << (page_shift - 8) | (byte_addr >> 8);
+		cmd[3] = byte_addr;
+		debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %d\n",
+			buf + actual,
+			cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
+
+		ret = spi_flash_cmd(flash->spi, CMD_W25_WREN, NULL, 0);
+		if (ret < 0) {
+			debug("SF: Enabling Write failed\n");
+			goto out;
+		}
+
+		ret = spi_flash_cmd_write(flash->spi, cmd, 4,
+				buf + actual, chunk_len);
+		if (ret < 0) {
+			debug("SF: Winbond Page Program failed\n");
+			goto out;
+		}
+
+		ret = winbond_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
+		if (ret < 0) {
+			debug("SF: Winbond page programming timed out\n");
+			goto out;
+		}
+
+		page_addr++;
+		byte_addr = 0;
+	}
+
+	debug("SF: Winbond: Successfully programmed %u bytes @ 0x%x\n",
+			len, offset);
+	ret = 0;
+
+out:
+	spi_release_bus(flash->spi);
+	return ret;
+}
+
+int winbond_erase(struct spi_flash *flash, u32 offset, size_t len)
+{
+	struct winbond_spi_flash *stm = to_winbond_spi_flash(flash);
+	unsigned long sector_size;
+	unsigned int page_shift;
+	size_t actual;
+	int ret;
+	u8 cmd[4];
+
+	/*
+	 * This function currently uses sector erase only.
+	 * probably speed things up by using bulk erase
+	 * when possible.
+	 */
+
+	page_shift = stm->params->l2_page_size;
+	sector_size = (1 << page_shift) * stm->params->pages_per_sector;
+
+	if (offset % sector_size || len % sector_size) {
+		debug("SF: Erase offset/length not multiple of sector size\n");
+		return -1;
+	}
+
+	len /= sector_size;
+	cmd[0] = CMD_W25_SE;
+
+	ret = spi_claim_bus(flash->spi);
+	if (ret) {
+		debug("SF: Unable to claim SPI bus\n");
+		return ret;
+	}
+
+	for (actual = 0; actual < len; actual++) {
+		winbond_build_address(stm, &cmd[1], offset + actual * sector_size);
+		printf("Erase: %02x %02x %02x %02x\n",
+				cmd[0], cmd[1], cmd[2], cmd[3]);
+
+		ret = spi_flash_cmd(flash->spi, CMD_W25_WREN, NULL, 0);
+		if (ret < 0) {
+			debug("SF: Enabling Write failed\n");
+			goto out;
+		}
+
+		ret = spi_flash_cmd_write(flash->spi, cmd, 4, NULL, 0);
+		if (ret < 0) {
+			debug("SF: Winbond sector erase failed\n");
+			goto out;
+		}
+
+		ret = winbond_wait_ready(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT);
+		if (ret < 0) {
+			debug("SF: Winbond sector erase timed out\n");
+			goto out;
+		}
+	}
+
+	debug("SF: Winbond: Successfully erased %u bytes @ 0x%x\n",
+			len * sector_size, offset);
+	ret = 0;
+
+out:
+	spi_release_bus(flash->spi);
+	return ret;
+}
+
+struct spi_flash *spi_flash_probe_winbond(struct spi_slave *spi, u8 *idcode)
+{
+	const struct winbond_spi_flash_params *params;
+	unsigned long page_size;
+	struct winbond_spi_flash *stm;
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(winbond_spi_flash_table); i++) {
+		params = &winbond_spi_flash_table[i];
+		if (params->id == ((idcode[1] << 8) | idcode[2]))
+			break;
+	}
+
+	if (i == ARRAY_SIZE(winbond_spi_flash_table)) {
+		debug("SF: Unsupported Winbond ID %02x%02x\n",
+				idcode[1], idcode[2]);
+		return NULL;
+	}
+
+	stm = malloc(sizeof(struct winbond_spi_flash));
+	if (!stm) {
+		debug("SF: Failed to allocate memory\n");
+		return NULL;
+	}
+
+	stm->params = params;
+	stm->flash.spi = spi;
+	stm->flash.name = params->name;
+
+	/* Assuming power-of-two page size initially. */
+	page_size = 1 << params->l2_page_size;
+
+	stm->flash.write = winbond_write;
+	stm->flash.erase = winbond_erase;
+	stm->flash.read = winbond_read_fast;
+	stm->flash.size = page_size * params->pages_per_sector
+				* params->sectors_per_block
+				* params->nr_blocks;
+
+	debug("SF: Detected %s with page size %u, total %u bytes\n",
+			params->name, page_size, stm->flash.size);
+
+	return &stm->flash;
+}

drivers/net/cs8900.c

@@ -56,7 +56,7 @@
 #define REG_READ(a) readl((a))
 
 /* we don't need 16 bit initialisation on 32 bit bus */
-#define get_reg_init_bus(x) get_reg((x))
+#define get_reg_init_bus(r,d) get_reg((r),(d))
 
 #else
 
@@ -321,15 +321,16 @@ int cs8900_initialize(u8 dev_num, int base_addr)
 	memset(priv, 0, sizeof(*priv));
 	priv->regs = (struct cs8900_regs *)base_addr;
 
-	/* Load MAC address from EEPROM */
-	cs8900_get_enetaddr(dev);
-
 	dev->iobase = base_addr;
 	dev->priv = priv;
 	dev->init = cs8900_init;
 	dev->halt = cs8900_halt;
 	dev->send = cs8900_send;
 	dev->recv = cs8900_recv;
+
+	/* Load MAC address from EEPROM */
+	cs8900_get_enetaddr(dev);
+
 	sprintf(dev->name, "%s-%hu", CS8900_DRIVERNAME, dev_num);
 
 	eth_register(dev);

drivers/net/dm9000x.c

@@ -284,7 +284,6 @@ static int dm9000_init(struct eth_device *dev, bd_t *bd)
 	int i, oft, lnk;
 	u8 io_mode;
 	struct board_info *db = &dm9000_info;
-	uchar enetaddr[6];
 
 	DM9000_DBG("%s\n", __func__);
 
@@ -342,20 +341,11 @@ static int dm9000_init(struct eth_device *dev, bd_t *bd)
 	/* Clear interrupt status */
 	DM9000_iow(DM9000_ISR, ISR_ROOS | ISR_ROS | ISR_PTS | ISR_PRS);
 
-	/* Set Node address */
-	if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
-#if !defined(CONFIG_DM9000_NO_SROM)
-		for (i = 0; i < 3; i++)
-			dm9000_read_srom_word(i, enetaddr + 2 * i);
-		eth_setenv_enetaddr("ethaddr", enetaddr);
-#endif
-	}
-
-	printf("MAC: %pM\n", enetaddr);
+	printf("MAC: %pM\n", dev->enetaddr);
 
 	/* fill device MAC address registers */
 	for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++)
-		DM9000_iow(oft, enetaddr[i]);
+		DM9000_iow(oft, dev->enetaddr[i]);
 	for (i = 0, oft = 0x16; i < 8; i++, oft++)
 		DM9000_iow(oft, 0xff);
 
@@ -558,6 +548,15 @@ void dm9000_write_srom_word(int offset, u16 val)
 }
 #endif
 
+static void dm9000_get_enetaddr(struct eth_device *dev)
+{
+#if !defined(CONFIG_DM9000_NO_SROM)
+	int i;
+	for (i = 0; i < 3; i++)
+		dm9000_read_srom_word(i, dev->enetaddr + (2 * i));
+#endif
+}
+
 /*
    Read a byte from I/O port
 */
@@ -621,6 +620,9 @@ int dm9000_initialize(bd_t *bis)
 {
 	struct eth_device *dev = &(dm9000_info.netdev);
 
+	/* Load MAC address from EEPROM */
+	dm9000_get_enetaddr(dev);
+
 	dev->init = dm9000_init;
 	dev->halt = dm9000_halt;
 	dev->send = dm9000_send;

drivers/net/fec_mxc.c

@@ -55,6 +55,8 @@ struct fec_priv gfec = {
 	.tbd_base  = NULL,
 	.tbd_index = 0,
 	.bd        = NULL,
+	.rdb_ptr   = NULL,
+	.base_ptr  = NULL,
 };
 
 /*
@@ -157,7 +159,9 @@ static int miiphy_restart_aneg(struct eth_device *dev)
 	/*
 	 * Set the auto-negotiation advertisement register bits
 	 */
-	miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_ANAR, 0x1e0);
+	miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_ANAR,
+			PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | PHY_ANLPAR_10FD |
+			PHY_ANLPAR_10 | PHY_ANLPAR_PSB_802_3);
 	miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_BMCR,
 			PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
 
@@ -228,7 +232,8 @@ static int fec_rbd_init(struct fec_priv *fec, int count, int size)
 	uint32_t p = 0;
 
 	/* reserve data memory and consider alignment */
-	fec->rdb_ptr = malloc(size * count + DB_DATA_ALIGNMENT);
+	if (fec->rdb_ptr == NULL)
+		fec->rdb_ptr = malloc(size * count + DB_DATA_ALIGNMENT);
 	p = (uint32_t)fec->rdb_ptr;
 	if (!p) {
 		puts("fec_imx27: not enough malloc memory!\n");
@@ -341,8 +346,8 @@ static int fec_open(struct eth_device *edev)
 	writel(FEC_ECNTRL_ETHER_EN, &fec->eth->ecntrl);
 
 	miiphy_wait_aneg(edev);
-	miiphy_speed(edev->name, 0);
-	miiphy_duplex(edev->name, 0);
+	miiphy_speed(edev->name, CONFIG_FEC_MXC_PHYADDR);
+	miiphy_duplex(edev->name, CONFIG_FEC_MXC_PHYADDR);
 
 	/*
 	 * Enable SmartDMA receive task
@@ -363,8 +368,9 @@ static int fec_init(struct eth_device *dev, bd_t* bd)
 	 * Datasheet forces the startaddress of each chain is 16 byte
 	 * aligned
 	 */
-	fec->base_ptr = malloc((2 + FEC_RBD_NUM) *
-			sizeof(struct fec_bd) + DB_ALIGNMENT);
+	if (fec->base_ptr == NULL)
+		fec->base_ptr = malloc((2 + FEC_RBD_NUM) *
+				sizeof(struct fec_bd) + DB_ALIGNMENT);
 	base = (uint32_t)fec->base_ptr;
 	if (!base) {
 		puts("fec_imx27: not enough malloc memory!\n");
@@ -491,8 +497,6 @@ static void fec_halt(struct eth_device *dev)
 	writel(0, &fec->eth->ecntrl);
 	fec->rbd_index = 0;
 	fec->tbd_index = 0;
-	free(fec->rdb_ptr);
-	free(fec->base_ptr);
 	debug("eth_halt: done\n");
 }
 

drivers/net/smc91111.h

@@ -81,10 +81,10 @@ struct smc91111_priv{
 #ifdef CONFIG_PXA250
 
 #ifdef CONFIG_XSENGINE
-#define	SMC_inl(a,r)	(*((volatile dword *)((a)->iobase+(r<<1))))
-#define	SMC_inw(a,r)	(*((volatile word *)((a)->iobase+(r<<1))))
+#define	SMC_inl(a,r)	(*((volatile dword *)((a)->iobase+((r)<<1))))
+#define	SMC_inw(a,r)	(*((volatile word *)((a)->iobase+((r)<<1))))
 #define SMC_inb(a,p)  ({ \
-	unsigned int __p = (unsigned int)((a)->iobase + (p<<1)); \
+	unsigned int __p = (unsigned int)((a)->iobase + ((p)<<1)); \
 	unsigned int __v = *(volatile unsigned short *)((__p) & ~2); \
 	if (__p & 2) __v >>= 8; \
 	else __v &= 0xff; \
@@ -99,7 +99,7 @@ struct smc91111_priv{
 	__v; })
 #define SMC_inb(a,p)	({ \
 	unsigned int ___v = SMC_inw((a),(p) & ~1); \
-	if (p & 1) ___v >>= 8; \
+	if ((p) & 1) ___v >>= 8; \
 	else ___v &= 0xff; \
 	___v; })
 #else

drivers/net/smc911x.c

@@ -37,7 +37,7 @@ void pkt_data_push(struct eth_device *dev, u32 addr, u32 val) \
 
 #define mdelay(n)       udelay((n)*1000)
 
-static void smx911x_handle_mac_address(struct eth_device *dev)
+static void smc911x_handle_mac_address(struct eth_device *dev)
 {
 	unsigned long addrh, addrl;
 	uchar *m = dev->enetaddr;
@@ -155,7 +155,7 @@ static int smc911x_init(struct eth_device *dev, bd_t * bd)
 	/* Configure the PHY, initialize the link state */
 	smc911x_phy_configure(dev);
 
-	smx911x_handle_mac_address(dev);
+	smc911x_handle_mac_address(dev);
 
 	/* Turn on Tx + Rx */
 	smc911x_enable(dev);
@@ -243,7 +243,7 @@ int smc911x_initialize(u8 dev_num, int base_addr)
 	dev = malloc(sizeof(*dev));
 	if (!dev) {
 		free(dev);
-		return 0;
+		return -1;
 	}
 	memset(dev, 0, sizeof(*dev));
 
@@ -271,5 +271,5 @@ int smc911x_initialize(u8 dev_num, int base_addr)
 	sprintf(dev->name, "%s-%hu", DRIVERNAME, dev_num);
 
 	eth_register(dev);
-	return 0;
+	return 1;
 }

drivers/pci/fsl_pci_init.c

@@ -42,6 +42,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define FSL_PCI_PBFR		0x44
 #define FSL_PCIE_CAP_ID		0x4c
 #define FSL_PCIE_CFG_RDY	0x4b0
+#define FSL_PROG_IF_AGENT	0x1
 
 void pciauto_prescan_setup_bridge(struct pci_controller *hose,
 				pci_dev_t dev, int sub_bus);
@@ -412,28 +413,24 @@ void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data)
 	}
 }
 
+int fsl_is_pci_agent(struct pci_controller *hose)
+{
+	u8 prog_if;
+	pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
+
+	pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prog_if);
+
+	return (prog_if == FSL_PROG_IF_AGENT);
+}
+
 int fsl_pci_init_port(struct fsl_pci_info *pci_info,
-			struct pci_controller *hose, int busno, int pcie_ep)
+			struct pci_controller *hose, int busno)
 {
 	volatile ccsr_fsl_pci_t *pci;
 	struct pci_region *r;
 
 	pci = (ccsr_fsl_pci_t *) pci_info->regs;
 
-	if (pcie_ep) {
-		volatile pit_t *pi = &pci->pit[2];
-
-		pci_setup_indirect(hose, (u32)&pci->cfg_addr,
-					 (u32)&pci->cfg_data);
-		out_be32(&pi->pitar, 0);
-		out_be32(&pi->piwbar, 0);
-		out_be32(&pi->piwar, PIWAR_EN | PIWAR_LOCAL |
-			PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_IWS_4K);
-
-		fsl_pci_config_unlock(hose);
-		return 0;
-	}
-
 	/* on non-PCIe controllers we don't have pme_msg_det so this code
 	 * should do nothing since the read will return 0
 	 */
@@ -464,6 +461,11 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info,
 
 	fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
 
+	if (fsl_is_pci_agent(hose)) {
+		fsl_pci_config_unlock(hose);
+		hose->last_busno = hose->first_busno;
+	}
+
 	printf("    PCIE%x on bus %02x - %02x\n", pci_info->pci_num,
 			hose->first_busno, hose->last_busno);
 

drivers/rtc/Makefile

@@ -40,6 +40,7 @@ COBJS-$(CONFIG_RTC_DS1556) += ds1556.o
 COBJS-$(CONFIG_RTC_DS164x) += ds164x.o
 COBJS-$(CONFIG_RTC_DS174x) += ds174x.o
 COBJS-$(CONFIG_RTC_DS3231) += ds3231.o
+COBJS-$(CONFIG_RTC_FTRTC010) += ftrtc010.o
 COBJS-$(CONFIG_RTC_ISL1208) += isl1208.o
 COBJS-$(CONFIG_RTC_M41T11) += m41t11.o
 COBJS-$(CONFIG_RTC_M41T60) += m41t60.o

drivers/rtc/ftrtc010.c

@@ -0,0 +1,124 @@
+/*
+ * Faraday FTRTC010 Real Time Clock
+ *
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <rtc.h>
+#include <asm/io.h>
+
+struct ftrtc010 {
+	unsigned int sec;		/* 0x00 */
+	unsigned int min;		/* 0x04 */
+	unsigned int hour;		/* 0x08 */
+	unsigned int day;		/* 0x0c */
+	unsigned int alarm_sec;		/* 0x10 */
+	unsigned int alarm_min;		/* 0x14 */
+	unsigned int alarm_hour;	/* 0x18 */
+	unsigned int record;		/* 0x1c */
+	unsigned int cr;		/* 0x20 */
+};
+
+/*
+ * RTC Control Register
+ */
+#define FTRTC010_CR_ENABLE		(1 << 0)
+#define FTRTC010_CR_INTERRUPT_SEC	(1 << 1)	/* per second irq */
+#define FTRTC010_CR_INTERRUPT_MIN	(1 << 2)	/* per minute irq */
+#define FTRTC010_CR_INTERRUPT_HR	(1 << 3)	/* per hour   irq */
+#define FTRTC010_CR_INTERRUPT_DAY	(1 << 4)	/* per day    irq */
+
+static struct ftrtc010 *rtc = (struct ftrtc010 *)CONFIG_FTRTC010_BASE;
+
+static void ftrtc010_enable (void)
+{
+	writel (FTRTC010_CR_ENABLE, &rtc->cr);
+}
+
+/*
+ * return current time in seconds
+ */
+static unsigned long ftrtc010_time (void)
+{
+	unsigned long day;
+	unsigned long hour;
+	unsigned long minute;
+	unsigned long second;
+	unsigned long second2;
+
+	do {
+		second	= readl (&rtc->sec);
+		day	= readl (&rtc->day);
+		hour	= readl (&rtc->hour);
+		minute	= readl (&rtc->min);
+		second2	= readl (&rtc->sec);
+	} while (second != second2);
+
+	return day * 24 * 60 * 60 + hour * 60 * 60 + minute * 60 + second;
+}
+
+/*
+ * Get the current time from the RTC
+ */
+
+int rtc_get (struct rtc_time *tmp)
+{
+	unsigned long now;
+
+	debug ("%s(): record register: %x\n",
+	       __func__, readl (&rtc->record));
+
+	now = ftrtc010_time () + readl (&rtc->record);
+
+	to_tm (now, tmp);
+
+	return 0;
+}
+
+/*
+ * Set the RTC
+ */
+int rtc_set (struct rtc_time *tmp)
+{
+	unsigned long new;
+	unsigned long now;
+
+	debug ("%s(): DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
+	       __func__,
+	       tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
+	       tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+
+	new = mktime (tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_hour,
+		      tmp->tm_min, tmp->tm_sec);
+
+	now = ftrtc010_time ();
+
+	debug ("%s(): write %lx to record register\n", __func__, new - now);
+
+	writel (new - now, &rtc->record);
+
+	return 0;
+}
+
+void rtc_reset (void)
+{
+	debug ("%s()\n", __func__);
+	ftrtc010_enable ();
+}

drivers/rtc/m41t11.c

@@ -181,18 +181,4 @@ void rtc_reset (void)
 	val = val & 0x3F;/*turn off freq test keep calibration*/
 	i2c_write(CONFIG_SYS_I2C_RTC_ADDR, RTC_CONTROL_ADDR, 1, &val, 1);
 }
-
-int rtc_store(int addr, unsigned char* data, int size)
-{
-	/*don't let things wrap onto the time on a write*/
-	if( (addr+size) >= M41T11_STORAGE_SZ )
-		return 1;
-	return i2c_write( CONFIG_SYS_I2C_RTC_ADDR, REG_CNT+addr, 1, data, size );
-}
-
-int rtc_recall(int addr, unsigned char* data, int size)
-{
-	return i2c_read( CONFIG_SYS_I2C_RTC_ADDR, REG_CNT+addr, 1, data, size );
-}
-
 #endif

drivers/rtc/mc13783-rtc.c

@@ -109,7 +109,7 @@ int rtc_set(struct rtc_time *rtc)
 
 	spi_release_bus(slave);
 
-	return -1;
+	return 0;
 }
 
 void rtc_reset(void)

drivers/spi/atmel_dataflash_spi.c

@@ -30,7 +30,8 @@
 #include <dataflash.h>
 
 #define AT91_SPI_PCS0_DATAFLASH_CARD	0xE	/* Chip Select 0: NPCS0%1110 */
-#define AT91_SPI_PCS1_DATAFLASH_CARD	0xD	/* Chip Select 0: NPCS0%1101 */
+#define AT91_SPI_PCS1_DATAFLASH_CARD	0xD	/* Chip Select 1: NPCS1%1101 */
+#define AT91_SPI_PCS2_DATAFLASH_CARD	0xB	/* Chip Select 2: NPCS2%1011 */
 #define AT91_SPI_PCS3_DATAFLASH_CARD	0x7	/* Chip Select 3: NPCS3%0111 */
 
 void AT91F_SpiInit(void)
@@ -57,7 +58,14 @@ void AT91F_SpiInit(void)
 	       ((get_mck_clk_rate() / AT91_SPI_CLK) << 8),
 	       AT91_BASE_SPI + AT91_SPI_CSR(1));
 #endif
-
+#ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS2
+	/* Configure CS2 */
+	writel(AT91_SPI_NCPHA |
+	       (AT91_SPI_DLYBS & DATAFLASH_TCSS) |
+	       (AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
+	       ((get_mck_clk_rate() / AT91_SPI_CLK) << 8),
+	       AT91_BASE_SPI + AT91_SPI_CSR(2));
+#endif
 #ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3
 	/* Configure CS3 */
 	writel(AT91_SPI_NCPHA |
@@ -99,6 +107,12 @@ void AT91F_SpiEnable(int cs)
 		writel(mode | ((AT91_SPI_PCS1_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
 		       AT91_BASE_SPI + AT91_SPI_MR);
 		break;
+	case 2:	/* Configure SPI CS2 for Serial DataFlash AT45DBxx */
+		mode = readl(AT91_BASE_SPI + AT91_SPI_MR);
+		mode &= 0xFFF0FFFF;
+		writel(mode | ((AT91_SPI_PCS2_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
+		       AT91_BASE_SPI + AT91_SPI_MR);
+		break;
 	case 3:
 		mode = readl(AT91_BASE_SPI + AT91_SPI_MR);
 		mode &= 0xFFF0FFFF;

examples/standalone/Makefile

@@ -38,7 +38,13 @@ ELF-mpc8260                      += mem_to_mem_idma2intr
 ELF-ppc                          += sched
 ELF-oxc                          += eepro100_eeprom
 
-ELF := $(ELF-y) $(ELF-$(ARCH)) $(ELF-$(BOARD)) $(ELF-$(CPU))
+#
+# Some versions of make do not handle trailing white spaces properly;
+# leading to build failures. The problem was found with GNU Make 3.80.
+# Using 'strip' as a workaround for the problem.
+#
+ELF := $(strip $(ELF-y) $(ELF-$(ARCH)) $(ELF-$(BOARD)) $(ELF-$(CPU)))
+
 SREC = $(addsuffix .srec,$(ELF))
 BIN  = $(addsuffix .bin,$(ELF))
 

examples/standalone/nios2.lds

@@ -1,133 +0,0 @@
-/*
- * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
- * Scott McNutt <smcnutt@psyent.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-OUTPUT_FORMAT("elf32-littlenios2")
-OUTPUT_ARCH(nios2)
-ENTRY(_start)
-
-SECTIONS
-{
-	.text :
-	{
-	  *(.text)
-	  *(.text.*)
-	  *(.gnu.linkonce.t*)
-	  *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-	  *(.gnu.linkonce.r*)
-	}
-	. = ALIGN (4);
-	_etext = .;
-	PROVIDE (etext = .);
-
-	/* INIT DATA sections - "Small" data (see the gcc -G option)
-	 * is always gp-relative. Here we make all init data sections
-	 * adjacent to simplify the startup code -- and provide
-	 * the global pointer for gp-relative access.
-	 */
-	_data = .;
-	.data :
-	{
-	  *(.data)
-	  *(.data.*)
-	  *(.gnu.linkonce.d*)
-	}
-
-	. = ALIGN(16);
-	_gp = .;			/* Global pointer addr */
-	PROVIDE (gp = .);
-
-	.sdata :
-	{
-	  *(.sdata)
-	  *(.sdata.*)
-	  *(.gnu.linkonce.s.*)
-	}
-	. = ALIGN(4);
-
-	_edata = .;
-	PROVIDE (edata = .);
-
-	/* UNINIT DATA - Small uninitialized data is first so it's
-	 * adjacent to sdata and can be referenced via gp. The normal
-	 * bss follows. We keep it adjacent to simplify init code.
-	 */
-	__bss_start = .;
-	.sbss (NOLOAD) :
-	{
-	  *(.sbss)
-	  *(.sbss.*)
-	  *(.gnu.linkonce.sb.*)
-	  *(.scommon)
-	}
-	. = ALIGN(4);
-	.bss (NOLOAD) :
-	{
-	  *(.bss)
-	  *(.bss.*)
-	  *(.dynbss)
-	  *(COMMON)
-	  *(.scommon)
-	}
-	. = ALIGN(4);
-	_end = .;
-	PROVIDE (end = .);
-
-	/* CMD TABLE - uboot command sections
-	 */
-	. = .;
-	__uboot_cmd_start = .;
-	.u_boot_cmd :
-	{
-	  *(.u_boot_cmd)
-	}
-	. = ALIGN(4);
-	__u_boot_cmd_end = .;
-
-	/* DEBUG -- symbol table, string table, etc. etc.
-	 */
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug          0 : { *(.debug) }
-	.line           0 : { *(.line) }
-	.debug_srcinfo  0 : { *(.debug_srcinfo) }
-	.debug_sfnames  0 : { *(.debug_sfnames) }
-	.debug_aranges  0 : { *(.debug_aranges) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_info     0 : { *(.debug_info) }
-	.debug_abbrev   0 : { *(.debug_abbrev) }
-	.debug_line     0 : { *(.debug_line) }
-	.debug_frame    0 : { *(.debug_frame) }
-	.debug_str      0 : { *(.debug_str) }
-	.debug_loc      0 : { *(.debug_loc) }
-	.debug_macinfo  0 : { *(.debug_macinfo) }
-	.debug_weaknames 0 : { *(.debug_weaknames) }
-	.debug_funcnames 0 : { *(.debug_funcnames) }
-	.debug_typenames 0 : { *(.debug_typenames) }
-	.debug_varnames  0 : { *(.debug_varnames) }
-}

examples/standalone/smc91111_eeprom.c

@@ -33,8 +33,6 @@
 struct eth_device { unsigned long iobase; };
 #include "../drivers/net/smc91111.h"
 
-#ifdef CONFIG_SMC91111
-
 #ifndef SMC91111_EEPROM_INIT
 # define SMC91111_EEPROM_INIT()
 #endif
@@ -391,13 +389,3 @@ void dump_reg (struct eth_device *dev)
 		printf ("\n");
 	}
 }
-
-#else
-
-int smc91111_eeprom (int argc, char *argv[])
-{
-	printf("Not supported for this board\n");
-	return 1;
-}
-
-#endif

examples/standalone/smc911x_eeprom.c

@@ -2,7 +2,7 @@
  * smc911x_eeprom.c - EEPROM interface to SMC911x parts.
  * Only tested on SMSC9118 though ...
  *
- * Copyright 2004-2008 Analog Devices Inc.
+ * Copyright 2004-2009 Analog Devices Inc.
  *
  * Licensed under the GPL-2 or later.
  *
@@ -17,8 +17,12 @@
 #include <common.h>
 #include <exports.h>
 
-#ifdef CONFIG_DRIVER_SMC911X
-
+/* the smc911x.h gets base addr through eth_device' iobase */
+struct eth_device {
+	const char *name;
+	unsigned long iobase;
+	void *priv;
+};
 #include "../drivers/net/smc911x.h"
 
 /**
@@ -55,32 +59,32 @@ static void usage(void)
  * Registers 0x00 - 0x50 are FIFOs.  The 0x50+ are the control registers
  * and they're all 32bits long.  0xB8+ are reserved, so don't bother.
  */
-static void dump_regs(void)
+static void dump_regs(struct eth_device *dev)
 {
 	u8 i, j = 0;
 	for (i = 0x50; i < 0xB8; i += sizeof(u32))
 		printf("%02x: 0x%08x %c", i,
-			smc911x_reg_read(CONFIG_DRIVER_SMC911X_BASE + i),
+			smc911x_reg_read(dev, i),
 			(j++ % 2 ? '\n' : ' '));
 }
 
 /**
  *	do_eeprom_cmd - handle eeprom communication
  */
-static int do_eeprom_cmd(int cmd, u8 reg)
+static int do_eeprom_cmd(struct eth_device *dev, int cmd, u8 reg)
 {
-	if (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY) {
+	if (smc911x_reg_read(dev, E2P_CMD) & E2P_CMD_EPC_BUSY) {
 		printf("eeprom_cmd: busy at start (E2P_CMD = 0x%08x)\n",
-			smc911x_reg_read(E2P_CMD));
+			smc911x_reg_read(dev, E2P_CMD));
 		return -1;
 	}
 
-	smc911x_reg_write(E2P_CMD, E2P_CMD_EPC_BUSY | cmd | reg);
+	smc911x_reg_write(dev, E2P_CMD, E2P_CMD_EPC_BUSY | cmd | reg);
 
-	while (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY)
+	while (smc911x_reg_read(dev, E2P_CMD) & E2P_CMD_EPC_BUSY)
 		if (smsc_ctrlc()) {
 			printf("eeprom_cmd: timeout (E2P_CMD = 0x%08x)\n",
-				smc911x_reg_read(E2P_CMD));
+				smc911x_reg_read(dev, E2P_CMD));
 			return -1;
 		}
 
@@ -90,37 +94,37 @@ static int do_eeprom_cmd(int cmd, u8 reg)
 /**
  *	read_eeprom_reg - read specified register in EEPROM
  */
-static u8 read_eeprom_reg(u8 reg)
+static u8 read_eeprom_reg(struct eth_device *dev, u8 reg)
 {
-	int ret = do_eeprom_cmd(E2P_CMD_EPC_CMD_READ, reg);
-	return (ret ? : smc911x_reg_read(E2P_DATA));
+	int ret = do_eeprom_cmd(dev, E2P_CMD_EPC_CMD_READ, reg);
+	return (ret ? : smc911x_reg_read(dev, E2P_DATA));
 }
 
 /**
  *	write_eeprom_reg - write specified value into specified register in EEPROM
  */
-static int write_eeprom_reg(u8 value, u8 reg)
+static int write_eeprom_reg(struct eth_device *dev, u8 value, u8 reg)
 {
 	int ret;
 
 	/* enable erasing/writing */
-	ret = do_eeprom_cmd(E2P_CMD_EPC_CMD_EWEN, reg);
+	ret = do_eeprom_cmd(dev, E2P_CMD_EPC_CMD_EWEN, reg);
 	if (ret)
 		goto done;
 
 	/* erase the eeprom reg */
-	ret = do_eeprom_cmd(E2P_CMD_EPC_CMD_ERASE, reg);
+	ret = do_eeprom_cmd(dev, E2P_CMD_EPC_CMD_ERASE, reg);
 	if (ret)
 		goto done;
 
 	/* write the eeprom reg */
-	smc911x_reg_write(E2P_DATA, value);
-	ret = do_eeprom_cmd(E2P_CMD_EPC_CMD_WRITE, reg);
+	smc911x_reg_write(dev, E2P_DATA, value);
+	ret = do_eeprom_cmd(dev, E2P_CMD_EPC_CMD_WRITE, reg);
 	if (ret)
 		goto done;
 
 	/* disable erasing/writing */
-	ret = do_eeprom_cmd(E2P_CMD_EPC_CMD_EWDS, reg);
+	ret = do_eeprom_cmd(dev, E2P_CMD_EPC_CMD_EWDS, reg);
 
  done:
 	return ret;
@@ -139,7 +143,7 @@ static char *skip_space(char *buf)
 /**
  *	write_stuff - handle writing of MAC registers / eeprom
  */
-static void write_stuff(char *line)
+static void write_stuff(struct eth_device *dev, char *line)
 {
 	char dest;
 	char *endp;
@@ -182,39 +186,39 @@ static void write_stuff(char *line)
 	/* Finally, execute the command */
 	if (dest == 'E') {
 		printf("Writing EEPROM register %02x with %02x\n", reg, value);
-		write_eeprom_reg(value, reg);
+		write_eeprom_reg(dev, value, reg);
 	} else {
 		printf("Writing MAC register %02x with %08x\n", reg, value);
-		smc911x_reg_write(CONFIG_DRIVER_SMC911X_BASE + reg, value);
+		smc911x_reg_write(dev, reg, value);
 	}
 }
 
 /**
  *	copy_from_eeprom - copy MAC address in eeprom to address registers
  */
-static void copy_from_eeprom(void)
+static void copy_from_eeprom(struct eth_device *dev)
 {
 	ulong addrl =
-		read_eeprom_reg(0x01) |
-		read_eeprom_reg(0x02) << 8 |
-		read_eeprom_reg(0x03) << 16 |
-		read_eeprom_reg(0x04) << 24;
+		read_eeprom_reg(dev, 0x01) |
+		read_eeprom_reg(dev, 0x02) << 8 |
+		read_eeprom_reg(dev, 0x03) << 16 |
+		read_eeprom_reg(dev, 0x04) << 24;
 	ulong addrh =
-		read_eeprom_reg(0x05) |
-		read_eeprom_reg(0x06) << 8;
-	smc911x_set_mac_csr(ADDRL, addrl);
-	smc911x_set_mac_csr(ADDRH, addrh);
+		read_eeprom_reg(dev, 0x05) |
+		read_eeprom_reg(dev, 0x06) << 8;
+	smc911x_set_mac_csr(dev, ADDRL, addrl);
+	smc911x_set_mac_csr(dev, ADDRH, addrh);
 	puts("EEPROM contents copied to MAC\n");
 }
 
 /**
  *	print_macaddr - print MAC address registers and MAC address in eeprom
  */
-static void print_macaddr(void)
+static void print_macaddr(struct eth_device *dev)
 {
 	puts("Current MAC Address in MAC:     ");
-	ulong addrl = smc911x_get_mac_csr(ADDRL);
-	ulong addrh = smc911x_get_mac_csr(ADDRH);
+	ulong addrl = smc911x_get_mac_csr(dev, ADDRL);
+	ulong addrh = smc911x_get_mac_csr(dev, ADDRH);
 	printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
 		(u8)(addrl), (u8)(addrl >> 8), (u8)(addrl >> 16),
 		(u8)(addrl >> 24), (u8)(addrh), (u8)(addrh >> 8));
@@ -222,41 +226,42 @@ static void print_macaddr(void)
 	puts("Current MAC Address in EEPROM:  ");
 	int i;
 	for (i = 1; i < 6; ++i)
-		printf("%02x:", read_eeprom_reg(i));
-	printf("%02x\n", read_eeprom_reg(i));
+		printf("%02x:", read_eeprom_reg(dev, i));
+	printf("%02x\n", read_eeprom_reg(dev, i));
 }
 
 /**
  *	dump_eeprom - dump the whole content of the EEPROM
  */
-static void dump_eeprom(void)
+static void dump_eeprom(struct eth_device *dev)
 {
 	int i;
 	puts("EEPROM:\n");
 	for (i = 0; i < 7; ++i)
-		printf("%02x: 0x%02x\n", i, read_eeprom_reg(i));
+		printf("%02x: 0x%02x\n", i, read_eeprom_reg(dev, i));
 }
 
 /**
  *	smc911x_init - get the MAC/EEPROM up and ready for use
  */
-static int smc911x_init(void)
+static int smc911x_init(struct eth_device *dev)
 {
 	/* See if there is anything there */
-	if (!smc911x_detect_chip())
+	if (!smc911x_detect_chip(dev))
 		return 1;
 
-	smc911x_reset();
+	smc911x_reset(dev);
 
 	/* Make sure we set EEDIO/EECLK to the EEPROM */
-	if (smc911x_reg_read(GPIO_CFG) & GPIO_CFG_EEPR_EN) {
-		while (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY)
+	if (smc911x_reg_read(dev, GPIO_CFG) & GPIO_CFG_EEPR_EN) {
+		while (smc911x_reg_read(dev, E2P_CMD) & E2P_CMD_EPC_BUSY)
 			if (smsc_ctrlc()) {
 				printf("init: timeout (E2P_CMD = 0x%08x)\n",
-					smc911x_reg_read(E2P_CMD));
+					smc911x_reg_read(dev, E2P_CMD));
 				return 1;
 			}
-		smc911x_reg_write(GPIO_CFG, smc911x_reg_read(GPIO_CFG) & ~GPIO_CFG_EEPR_EN);
+		smc911x_reg_write(dev, GPIO_CFG,
+			smc911x_reg_read(dev, GPIO_CFG) & ~GPIO_CFG_EEPR_EN);
 	}
 
 	return 0;
@@ -317,6 +322,11 @@ static char *getline(void)
  */
 int smc911x_eeprom(int argc, char *argv[])
 {
+	/* Avoid initializing on stack as gcc likes to call memset() */
+	struct eth_device dev;
+	dev.name = __func__;
+	dev.iobase = CONFIG_SMC911X_BASE;
+
 	/* Print the ABI version */
 	app_startup(argv);
 	if (XF_VERSION != get_version()) {
@@ -328,7 +338,7 @@ int smc911x_eeprom(int argc, char *argv[])
 
 	/* Initialize the MAC/EEPROM somewhat */
 	puts("\n");
-	if (smc911x_init())
+	if (smc911x_init(&dev))
 		return 1;
 
 	/* Dump helpful usage information */
@@ -360,11 +370,11 @@ int smc911x_eeprom(int argc, char *argv[])
 
 		/* Now parse the command */
 		switch (line[0]) {
-		case 'W': write_stuff(line);  break;
-		case 'D': dump_eeprom();      break;
-		case 'M': dump_regs();        break;
-		case 'C': copy_from_eeprom(); break;
-		case 'P': print_macaddr();    break;
+		case 'W': write_stuff(&dev, line); break;
+		case 'D': dump_eeprom(&dev);       break;
+		case 'M': dump_regs(&dev);         break;
+		case 'C': copy_from_eeprom(&dev);  break;
+		case 'P': print_macaddr(&dev);     break;
 		unknown_cmd:
 		default:  puts("ERROR: Unknown command!\n\n");
 		case '?':
@@ -373,11 +383,3 @@ int smc911x_eeprom(int argc, char *argv[])
 		}
 	}
 }
-
-#else
-int smc911x_eeprom(int argc, char *argv[])
-{
-	puts("Not supported for this board\n");
-	return 1;
-}
-#endif

examples/standalone/stubs.c

@@ -181,9 +181,9 @@ gd_t *global_data;
 "	or %%g1, %%g7, %%g1\n"				\
 "	ld [%%g1], %%g1\n"				\
 "	ld [%%g1 + %1], %%g1\n"				\
-"	call %%g1\n"					\
+"	jmp %%g1\n"					\
 "	nop\n"						\
-	: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x) : "g1" );
+	: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "g1" );
 
 #else
 #error stubs definition missing for this architecture

fs/ext2/ext2fs.c

@@ -178,6 +178,7 @@ int indir1_blkno = -1;
 uint32_t *indir2_block = NULL;
 int indir2_size = 0;
 int indir2_blkno = -1;
+static unsigned int inode_size;
 
 
 static int ext2fs_blockgroup
@@ -212,7 +213,7 @@ static int ext2fs_read_inode
 	unsigned int blkoff;
 
 #ifdef DEBUG
-	printf ("ext2fs read inode %d\n", ino);
+	printf ("ext2fs read inode %d, inode_size %d\n", ino, inode_size);
 #endif
 	/* It is easier to calculate if the first inode is 0.  */
 	ino--;
@@ -222,16 +223,12 @@ static int ext2fs_read_inode
 		return (0);
 	}
 
-	inodes_per_block = EXT2_BLOCK_SIZE(data) / __le16_to_cpu(sblock->inode_size);
-
-#ifdef DEBUG
-	printf ("ext2fs read inode blkno %d blkoff %d\n", blkno, blkoff);
-#endif
+	inodes_per_block = EXT2_BLOCK_SIZE(data) / inode_size;
 
 	blkno = __le32_to_cpu (blkgrp.inode_table_id) +
 		(ino % __le32_to_cpu (sblock->inodes_per_group))
 		/ inodes_per_block;
-	blkoff = (ino % inodes_per_block) * __le16_to_cpu (sblock->inode_size);
+	blkoff = (ino % inodes_per_block) * inode_size;
 #ifdef DEBUG
 	printf ("ext2fs read inode blkno %d blkoff %d\n", blkno, blkoff);
 #endif
@@ -863,6 +860,15 @@ int ext2fs_mount (unsigned part_length) {
 	if (__le16_to_cpu (data->sblock.magic) != EXT2_MAGIC) {
 		goto fail;
 	}
+	if (__le32_to_cpu(data->sblock.revision_level == 0)) {
+		inode_size = 128;
+	} else {
+		inode_size = __le16_to_cpu(data->sblock.inode_size);
+	}
+#ifdef DEBUG
+	printf("EXT2 rev %d, inode_size %d\n",
+			__le32_to_cpu(data->sblock.revision_level), inode_size);
+#endif
 	data->diropen.data = data;
 	data->diropen.ino = 2;
 	data->diropen.inode_read = 1;

include/asm-arm/unaligned.h

@@ -1,7 +1,8 @@
 #ifndef _ASM_ARM_UNALIGNED_H
 #define _ASM_ARM_UNALIGNED_H
 
-#include <linux/unaligned/access_ok.h>
+#include <linux/unaligned/le_byteshift.h>
+#include <linux/unaligned/be_byteshift.h>
 #include <linux/unaligned/generic.h>
 
 /*

include/asm-microblaze/bitops.h

@@ -266,8 +266,6 @@ found_middle:
 	return result + ffz(tmp);
 }
 
-#define ffs(x) generic_ffs(x)
-
 /*
  * hweightN: returns the hamming weight (i.e. the number
  * of bits set) of a N-bit word

include/asm-ppc/fsl_pci.h

@@ -25,6 +25,7 @@
 int is_fsl_pci_agent(enum law_trgt_if trgt, u32 host_agent);
 int is_fsl_pci_cfg(enum law_trgt_if trgt, u32 io_sel);
 
+int fsl_is_pci_agent(struct pci_controller *hose);
 void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data);
 void fsl_pci_config_unlock(struct pci_controller *hose);
 void ft_fsl_pci_setup(void *blob, const char *pci_alias,
@@ -62,7 +63,6 @@ typedef struct pci_inbound_window {
 #define PIWAR_LOCAL		0x00f00000
 #define PIWAR_READ_SNOOP	0x00050000
 #define PIWAR_WRITE_SNOOP	0x00005000
-#define PIWAR_IWS_4K		0x0000000b
 	u32	res2[3];
 } pit_t;
 
@@ -172,7 +172,7 @@ struct fsl_pci_info {
 };
 
 int fsl_pci_init_port(struct fsl_pci_info *pci_info,
-			struct pci_controller *hose, int busno, int pcie_ep);
+				struct pci_controller *hose, int busno);
 
 #define SET_STD_PCI_INFO(x, num) \
 {			\

include/configs/MPC8536DS.h

@@ -70,13 +70,6 @@
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
 
-/*
- * When initializing flash, if we cannot find the manufacturer ID,
- * assume this is the AMD flash associated with the CDS board.
- * This allows booting from a promjet.
- */
-#define CONFIG_ASSUME_AMD_FLASH
-
 #ifndef __ASSEMBLY__
 extern unsigned long get_board_sys_clk(unsigned long dummy);
 extern unsigned long get_board_ddr_clk(unsigned long dummy);

include/configs/MPC8541CDS.h

@@ -46,13 +46,6 @@
 
 #define CONFIG_FSL_VIA
 
-/*
- * When initializing flash, if we cannot find the manufacturer ID,
- * assume this is the AMD flash associated with the CDS board.
- * This allows booting from a promjet.
- */
-#define CONFIG_ASSUME_AMD_FLASH
-
 #ifndef __ASSEMBLY__
 extern unsigned long get_clock_freq(void);
 #endif

include/configs/MPC8544DS.h

@@ -50,13 +50,6 @@
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */
 
-/*
- * When initializing flash, if we cannot find the manufacturer ID,
- * assume this is the AMD flash associated with the CDS board.
- * This allows booting from a promjet.
- */
-#define CONFIG_ASSUME_AMD_FLASH
-
 #ifndef __ASSEMBLY__
 extern unsigned long get_board_sys_clk(unsigned long dummy);
 #endif

include/configs/MPC8548CDS.h

@@ -52,13 +52,6 @@
 
 #define CONFIG_FSL_VIA
 
-/*
- * When initializing flash, if we cannot find the manufacturer ID,
- * assume this is the AMD flash associated with the CDS board.
- * This allows booting from a promjet.
- */
-#define CONFIG_ASSUME_AMD_FLASH
-
 #ifndef __ASSEMBLY__
 extern unsigned long get_clock_freq(void);
 #endif

include/configs/MPC8555CDS.h

@@ -46,13 +46,6 @@
 #define CONFIG_FSL_VIA
 
 
-/*
- * When initializing flash, if we cannot find the manufacturer ID,
- * assume this is the AMD flash associated with the CDS board.
- * This allows booting from a promjet.
- */
-#define CONFIG_ASSUME_AMD_FLASH
-
 #ifndef __ASSEMBLY__
 extern unsigned long get_clock_freq(void);
 #endif

include/configs/MPC8568MDS.h

@@ -44,13 +44,6 @@
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 
-/*
- * When initializing flash, if we cannot find the manufacturer ID,
- * assume this is the AMD flash associated with the MDS board.
- * This allows booting from a promjet.
- */
-#define CONFIG_ASSUME_AMD_FLASH
-
 #ifndef __ASSEMBLY__
 extern unsigned long get_clock_freq(void);
 #endif						  /*Replace a call to get_clock_freq (after it is implemented)*/

include/configs/MPC8569MDS.h

@@ -44,13 +44,6 @@
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 
-/*
- * When initializing flash, if we cannot find the manufacturer ID,
- * assume this is the AMD flash associated with the MDS board.
- * This allows booting from a promjet.
- */
-#define CONFIG_ASSUME_AMD_FLASH
-
 #ifndef __ASSEMBLY__
 extern unsigned long get_clock_freq(void);
 #endif

include/configs/MPC8572DS.h

@@ -53,13 +53,6 @@
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
 
-/*
- * When initializing flash, if we cannot find the manufacturer ID,
- * assume this is the AMD flash associated with the CDS board.
- * This allows booting from a promjet.
- */
-#define CONFIG_ASSUME_AMD_FLASH
-
 #ifndef __ASSEMBLY__
 extern unsigned long get_board_sys_clk(unsigned long dummy);
 extern unsigned long get_board_ddr_clk(unsigned long dummy);

include/configs/MVBLUE.h

@@ -88,7 +88,6 @@
 #define CONFIG_CMD_SAVEENV
 #define CONFIG_CMD_FLASH
 #define CONFIG_CMD_IMI
-#define CONFIG_CMD_IRQ
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_RUN

include/configs/P2020DS.h

@@ -54,13 +54,6 @@
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
 
-/*
- * When initializing flash, if we cannot find the manufacturer ID,
- * assume this is the AMD flash associated with the CDS board.
- * This allows booting from a promjet.
- */
-#define CONFIG_ASSUME_AMD_FLASH
-
 #ifndef __ASSEMBLY__
 extern unsigned long calculate_board_sys_clk(unsigned long dummy);
 extern unsigned long calculate_board_ddr_clk(unsigned long dummy);

include/configs/PLU405.h

@@ -300,7 +300,8 @@
 /*
  * External Bus Controller (EBC) Setup
  */
-#define CAN_BA		0xF0000000	    /* CAN Base Address	        */
+#define CAN0_BA		0xF0000000	    /* CAN0 Base Address	*/
+#define CAN1_BA		0xF0000100	    /* CAN1 Base Address	*/
 #define DUART0_BA	0xF0000400	    /* DUART Base Address       */
 #define DUART1_BA	0xF0000408	    /* DUART Base Address       */
 #define RTC_BA		0xF0000500	    /* RTC Base Address         */

include/configs/canyonlands.h

@@ -593,7 +593,7 @@
 #define CONFIG_SYS_EBC_PB1CR		(CONFIG_SYS_FPGA_BASE | 0x3a000) /* BAS=FPGA,BS=2MB,BU=R/W,BW=16bit*/
 #endif	/* !defined(CONFIG_ARCHES) */
 
-#define CONFIG_SYS_EBC_CFG		0xB8400000		/*  EBC0_CFG */
+#define CONFIG_SYS_EBC_CFG		0xbfc00000
 
 /*
  * Arches doesn't use PerCS3 but GPIO43, so let's configure the GPIO

include/configs/galaxy5200.h

@@ -88,15 +88,21 @@
 /*
  * Autobooting
  */
-#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds */
+#define CONFIG_BOOTDELAY	10	/* autoboot after 10 seconds */
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* allow stopping of boot process */
 					/* even with bootdelay=0 */
-#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOT_RETRY_TIME 120	/* Reset if no command is entered  */
+#define CONFIG_RESET_TO_RETRY
 
 #define CONFIG_PREBOOT	"echo;"	\
 	"echo Welcome to U-Boot;"\
 	"echo"
 
+#define CONFIG_BOOTCOMMAND     "go ff300004 0; go ff300004 2 2;" \
+	"bootm ff040000 ff900000 fffc0000"
+#define CONFIG_BOOTARGS        "console=ttyPSC0,115200"
+#define CONFIG_EXTRA_ENV_SETTINGS "epson=yes\0"
+
 /*
  * IPB Bus clocking configuration.
  */

include/configs/imx27lite.h

@@ -145,6 +145,7 @@
 /*
  * MTD
  */
+#define CONFIG_FLASH_CFI_MTD
 #define CONFIG_MTD_DEVICE
 
 /*

include/configs/lpd7a400-10.h

@@ -76,6 +76,5 @@
 #define CONFIG_SMC91111
 #define CONFIG_SMC91111_BASE	(0x70000000)
 #undef CONFIG_SMC_USE_32_BIT
-#define CONFIG_SMC_USE_IOFUNCS
 
 #endif  /* __LPD7A400_10_H */

include/configs/lpd7a404-10.h

@@ -76,6 +76,5 @@
 #define CONFIG_SMC91111
 #define CONFIG_SMC91111_BASE	(0x70000000)
 #undef CONFIG_SMC_USE_32_BIT
-#define CONFIG_SMC_USE_IOFUNCS
 
 #endif  /* __LPD7A404_10_H */

include/configs/lpd7a404.h

@@ -72,7 +72,7 @@
 #include <config_cmd_default.h>
 
 #ifndef USE_920T_MMU
-    #define CONFIG_CMD_PING)
+    #define CONFIG_CMD_PING
     #undef CONFIG_CMD_CACHE
 #else
     #define CONFIG_CMD_DATE

include/configs/microblaze-generic.h

@@ -146,7 +146,7 @@
 #define	CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
 
 /* stack */
-#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_MONITOR_BASE
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_MALLOC_BASE
 
 /*#define	RAMENV */
 #define	FLASH

include/configs/mimc200.h

@@ -74,7 +74,7 @@
 
 #define CONFIG_BAUDRATE			115200
 #define CONFIG_BOOTARGS							\
-	"root=/dev/mtdblock1 rootfstype=jffs2 console=ttyS1"
+	"root=/dev/mtdblock1 rootfstype=jffs2 fbmem=512k console=ttyS1"
 #define CONFIG_BOOTCOMMAND						\
 	"fsload boot/uImage; bootm"
 

include/configs/sbc35_a9g20.h

@@ -161,6 +161,7 @@
 #define CONFIG_ENV_OFFSET		0x60000
 #define CONFIG_ENV_OFFSET_REDUND	0x80000
 #define CONFIG_ENV_SIZE			0x20000
+#define CONFIG_SYS_64BIT_VSPRINTF	/* needed for nand_util.c */
 #endif
 
 #define CONFIG_BOOTCOMMAND	"nboot 0x21000000 0 400000"

include/configs/sbc8349.h

@@ -158,7 +158,7 @@
 /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
 
 #define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE |	/* flash Base address */ \
-				(2 << BR_PS_SHIFT) |	/* 32 bit port size */	 \
+				(2 << BR_PS_SHIFT) |	/* 16 bit port size */	 \
 				BR_V)			/* valid */
 
 #define CONFIG_SYS_OR0_PRELIM		0xFF806FF7	/* 8 MB flash size */

include/configs/tny_a9260.h

@@ -138,6 +138,7 @@
 #define CONFIG_ENV_OFFSET 0x60000
 #define CONFIG_ENV_OFFSET_REDUND 0x80000
 #define CONFIG_ENV_SIZE 0x20000
+#define CONFIG_SYS_64BIT_VSPRINTF	/* needed for nand_util.c */
 #endif
 
 #define CONFIG_BOOTCOMMAND	"nboot 0x21000000 0 400000"

include/image.h

@@ -219,12 +219,10 @@ typedef struct bootm_headers {
 	const char	*fit_uname_rd;	/* init ramdisk subimage node unit name */
 	int		fit_noffset_rd;	/* init ramdisk subimage node offset */
 
-#if defined(CONFIG_PPC)
 	void		*fit_hdr_fdt;	/* FDT blob FIT image header */
 	const char	*fit_uname_fdt;	/* FDT blob subimage node unit name */
 	int		fit_noffset_fdt;/* FDT blob subimage node offset */
 #endif
-#endif
 
 #ifndef USE_HOSTCC
 	image_info_t	os;		/* os image info */

include/linux/unaligned/be_byteshift.h

@@ -0,0 +1,70 @@
+#ifndef _LINUX_UNALIGNED_BE_BYTESHIFT_H
+#define _LINUX_UNALIGNED_BE_BYTESHIFT_H
+
+#include <linux/types.h>
+
+static inline u16 __get_unaligned_be16(const u8 *p)
+{
+	return p[0] << 8 | p[1];
+}
+
+static inline u32 __get_unaligned_be32(const u8 *p)
+{
+	return p[0] << 24 | p[1] << 16 | p[2] << 8 | p[3];
+}
+
+static inline u64 __get_unaligned_be64(const u8 *p)
+{
+	return (u64)__get_unaligned_be32(p) << 32 |
+	       __get_unaligned_be32(p + 4);
+}
+
+static inline void __put_unaligned_be16(u16 val, u8 *p)
+{
+	*p++ = val >> 8;
+	*p++ = val;
+}
+
+static inline void __put_unaligned_be32(u32 val, u8 *p)
+{
+	__put_unaligned_be16(val >> 16, p);
+	__put_unaligned_be16(val, p + 2);
+}
+
+static inline void __put_unaligned_be64(u64 val, u8 *p)
+{
+	__put_unaligned_be32(val >> 32, p);
+	__put_unaligned_be32(val, p + 4);
+}
+
+static inline u16 get_unaligned_be16(const void *p)
+{
+	return __get_unaligned_be16((const u8 *)p);
+}
+
+static inline u32 get_unaligned_be32(const void *p)
+{
+	return __get_unaligned_be32((const u8 *)p);
+}
+
+static inline u64 get_unaligned_be64(const void *p)
+{
+	return __get_unaligned_be64((const u8 *)p);
+}
+
+static inline void put_unaligned_be16(u16 val, void *p)
+{
+	__put_unaligned_be16(val, p);
+}
+
+static inline void put_unaligned_be32(u32 val, void *p)
+{
+	__put_unaligned_be32(val, p);
+}
+
+static inline void put_unaligned_be64(u64 val, void *p)
+{
+	__put_unaligned_be64(val, p);
+}
+
+#endif /* _LINUX_UNALIGNED_BE_BYTESHIFT_H */

include/linux/unaligned/le_byteshift.h

@@ -0,0 +1,70 @@
+#ifndef _LINUX_UNALIGNED_LE_BYTESHIFT_H
+#define _LINUX_UNALIGNED_LE_BYTESHIFT_H
+
+#include <linux/types.h>
+
+static inline u16 __get_unaligned_le16(const u8 *p)
+{
+	return p[0] | p[1] << 8;
+}
+
+static inline u32 __get_unaligned_le32(const u8 *p)
+{
+	return p[0] | p[1] << 8 | p[2] << 16 | p[3] << 24;
+}
+
+static inline u64 __get_unaligned_le64(const u8 *p)
+{
+	return (u64)__get_unaligned_le32(p + 4) << 32 |
+	       __get_unaligned_le32(p);
+}
+
+static inline void __put_unaligned_le16(u16 val, u8 *p)
+{
+	*p++ = val;
+	*p++ = val >> 8;
+}
+
+static inline void __put_unaligned_le32(u32 val, u8 *p)
+{
+	__put_unaligned_le16(val >> 16, p + 2);
+	__put_unaligned_le16(val, p);
+}
+
+static inline void __put_unaligned_le64(u64 val, u8 *p)
+{
+	__put_unaligned_le32(val >> 32, p + 4);
+	__put_unaligned_le32(val, p);
+}
+
+static inline u16 get_unaligned_le16(const void *p)
+{
+	return __get_unaligned_le16((const u8 *)p);
+}
+
+static inline u32 get_unaligned_le32(const void *p)
+{
+	return __get_unaligned_le32((const u8 *)p);
+}
+
+static inline u64 get_unaligned_le64(const void *p)
+{
+	return __get_unaligned_le64((const u8 *)p);
+}
+
+static inline void put_unaligned_le16(u16 val, void *p)
+{
+	__put_unaligned_le16(val, p);
+}
+
+static inline void put_unaligned_le32(u32 val, void *p)
+{
+	__put_unaligned_le32(val, p);
+}
+
+static inline void put_unaligned_le64(u64 val, void *p)
+{
+	__put_unaligned_le64(val, p);
+}
+
+#endif /* _LINUX_UNALIGNED_LE_BYTESHIFT_H */

include/mtd/cfi_flash.h

@@ -0,0 +1,157 @@
+/*
+ * (C) Copyright 2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __CFI_FLASH_H__
+#define __CFI_FLASH_H__
+
+#define FLASH_CMD_CFI			0x98
+#define FLASH_CMD_READ_ID		0x90
+#define FLASH_CMD_RESET			0xff
+#define FLASH_CMD_BLOCK_ERASE		0x20
+#define FLASH_CMD_ERASE_CONFIRM		0xD0
+#define FLASH_CMD_WRITE			0x40
+#define FLASH_CMD_PROTECT		0x60
+#define FLASH_CMD_PROTECT_SET		0x01
+#define FLASH_CMD_PROTECT_CLEAR		0xD0
+#define FLASH_CMD_CLEAR_STATUS		0x50
+#define FLASH_CMD_READ_STATUS		0x70
+#define FLASH_CMD_WRITE_TO_BUFFER	0xE8
+#define FLASH_CMD_WRITE_BUFFER_PROG	0xE9
+#define FLASH_CMD_WRITE_BUFFER_CONFIRM	0xD0
+
+#define FLASH_STATUS_DONE		0x80
+#define FLASH_STATUS_ESS		0x40
+#define FLASH_STATUS_ECLBS		0x20
+#define FLASH_STATUS_PSLBS		0x10
+#define FLASH_STATUS_VPENS		0x08
+#define FLASH_STATUS_PSS		0x04
+#define FLASH_STATUS_DPS		0x02
+#define FLASH_STATUS_R			0x01
+#define FLASH_STATUS_PROTECT		0x01
+
+#define AMD_CMD_RESET			0xF0
+#define AMD_CMD_WRITE			0xA0
+#define AMD_CMD_ERASE_START		0x80
+#define AMD_CMD_ERASE_SECTOR		0x30
+#define AMD_CMD_UNLOCK_START		0xAA
+#define AMD_CMD_UNLOCK_ACK		0x55
+#define AMD_CMD_WRITE_TO_BUFFER		0x25
+#define AMD_CMD_WRITE_BUFFER_CONFIRM	0x29
+
+#define AMD_STATUS_TOGGLE		0x40
+#define AMD_STATUS_ERROR		0x20
+
+#define ATM_CMD_UNLOCK_SECT		0x70
+#define ATM_CMD_SOFTLOCK_START		0x80
+#define ATM_CMD_LOCK_SECT		0x40
+
+#define FLASH_CONTINUATION_CODE		0x7F
+
+#define FLASH_OFFSET_MANUFACTURER_ID	0x00
+#define FLASH_OFFSET_DEVICE_ID		0x01
+#define FLASH_OFFSET_DEVICE_ID2		0x0E
+#define FLASH_OFFSET_DEVICE_ID3		0x0F
+#define FLASH_OFFSET_CFI		0x55
+#define FLASH_OFFSET_CFI_ALT		0x555
+#define FLASH_OFFSET_CFI_RESP		0x10
+#define FLASH_OFFSET_PRIMARY_VENDOR	0x13
+/* extended query table primary address */
+#define FLASH_OFFSET_EXT_QUERY_T_P_ADDR	0x15
+#define FLASH_OFFSET_WTOUT		0x1F
+#define FLASH_OFFSET_WBTOUT		0x20
+#define FLASH_OFFSET_ETOUT		0x21
+#define FLASH_OFFSET_CETOUT		0x22
+#define FLASH_OFFSET_WMAX_TOUT		0x23
+#define FLASH_OFFSET_WBMAX_TOUT		0x24
+#define FLASH_OFFSET_EMAX_TOUT		0x25
+#define FLASH_OFFSET_CEMAX_TOUT		0x26
+#define FLASH_OFFSET_SIZE		0x27
+#define FLASH_OFFSET_INTERFACE		0x28
+#define FLASH_OFFSET_BUFFER_SIZE	0x2A
+#define FLASH_OFFSET_NUM_ERASE_REGIONS	0x2C
+#define FLASH_OFFSET_ERASE_REGIONS	0x2D
+#define FLASH_OFFSET_PROTECT		0x02
+#define FLASH_OFFSET_USER_PROTECTION	0x85
+#define FLASH_OFFSET_INTEL_PROTECTION	0x81
+
+#define CFI_CMDSET_NONE			0
+#define CFI_CMDSET_INTEL_EXTENDED	1
+#define CFI_CMDSET_AMD_STANDARD		2
+#define CFI_CMDSET_INTEL_STANDARD	3
+#define CFI_CMDSET_AMD_EXTENDED		4
+#define CFI_CMDSET_MITSU_STANDARD	256
+#define CFI_CMDSET_MITSU_EXTENDED	257
+#define CFI_CMDSET_SST			258
+#define CFI_CMDSET_INTEL_PROG_REGIONS	512
+
+#ifdef CONFIG_SYS_FLASH_CFI_AMD_RESET /* needed for STM_ID_29W320DB on UC100 */
+# undef  FLASH_CMD_RESET
+# define FLASH_CMD_RESET	AMD_CMD_RESET /* use AMD-Reset instead */
+#endif
+
+#define NUM_ERASE_REGIONS	4 /* max. number of erase regions */
+
+typedef union {
+	unsigned char c;
+	unsigned short w;
+	unsigned long l;
+	unsigned long long ll;
+} cfiword_t;
+
+/* CFI standard query structure */
+struct cfi_qry {
+	u8	qry[3];
+	u16	p_id;
+	u16	p_adr;
+	u16	a_id;
+	u16	a_adr;
+	u8	vcc_min;
+	u8	vcc_max;
+	u8	vpp_min;
+	u8	vpp_max;
+	u8	word_write_timeout_typ;
+	u8	buf_write_timeout_typ;
+	u8	block_erase_timeout_typ;
+	u8	chip_erase_timeout_typ;
+	u8	word_write_timeout_max;
+	u8	buf_write_timeout_max;
+	u8	block_erase_timeout_max;
+	u8	chip_erase_timeout_max;
+	u8	dev_size;
+	u16	interface_desc;
+	u16	max_buf_write_size;
+	u8	num_erase_regions;
+	u32	erase_region_info[NUM_ERASE_REGIONS];
+} __attribute__((packed));
+
+struct cfi_pri_hdr {
+	u8	pri[3];
+	u8	major_version;
+	u8	minor_version;
+} __attribute__((packed));
+
+void flash_write_cmd(flash_info_t * info, flash_sect_t sect,
+		     uint offset, u32 cmd);
+
+#endif /* __CFI_FLASH_H__ */