Prepare v2009.11.1

Update CHANGELOG

Signed-off-by: Wolfgang Denk <wd@denx.de>

CHANGELOG

@@ -1,3 +1,227 @@
+commit 580ca3c2b1d032534195cd0bfd89aa11e8c03bb3
+Author: Stefan Roese <sr@denx.de>
+Date:	Thu Jan 21 11:37:31 2010 +0100
+
+    ppc4xx: Kilauea: Add CPLD version detection and EBC reconfiguration
+
+    A newer CPLD version on the 405EX evaluation board requires a different
+    EBC controller setup for the CPLD register access. This patch adds a CPLD
+    version detection for Kilauea and code to reconfigure the EBC controller
+    (chip select 2) for the old CPLD if no new version is found.
+
+    Additionally the CPLD version is printed upon bootup:
+
+    Board: Kilauea - AMCC PPC405EX Evaluation Board (CPLD rev. 0)
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+    Acked-by: Wolfgang Denk <wd@denx.de>
+    Cc: Zhang Bao Quan <bqzhang@udtech.com.cn>
+
+commit eb20392ca986074c78ee4f241a8f2369777a8df3
+Author: Felix Radensky <felix@embedded-sol.com>
+Date:	Sat Jan 23 01:35:24 2010 +0200
+
+    ppc4xx: Fix sending type 1 PCI transactions
+
+    The list of 4xx SoCs that should send type 1 PCI transactions
+    is not defined correctly. As a result PCI-PCI bridges and devices
+    behind them are not identified. The following 4xx variants should
+    send type 1 transactions: 440GX, 440GP, 440SP, 440SPE, 460EX and 460GT.
+
+    Signed-off-by: Felix Radensky <felix@embedded-sol.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 57ab8a129dd4121711540e2b976aff882998de51
+Author: Felix Radensky <felix@embedded-sol.com>
+Date:	Tue Jan 19 21:19:06 2010 +0200
+
+    ppc4xx: Allow setting a single SPD EEPROM address for DDR2 DIMMs
+
+    On platforms where SPD EEPROM and another EEPROM have adjacent
+    I2C addresses SPD_EEPROM_ADDRESS should be defined as a single
+    element array, otherwise DDR2 setup code would fail with the
+    following error:
+
+    ERROR: Unknown DIMM detected in slot 1
+
+    However, fixing SPD_EEPROM_ADDRESS would result in another
+    error:
+
+    ERROR: DIMM's DDR1 and DDR2 type can not be mixed.
+
+    This happens because initdram() routine does not explicitly
+    initialize dimm_populated array. This patch fixes the problem.
+
+    Signed-off-by: Felix Radensky <felix@embedded-sol.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 17ab3057bde25208af71326c0ff213d05eadb318
+Author: Felix Radensky <felix@embedded-sol.com>
+Date:	Tue Jan 19 17:37:13 2010 +0200
+
+    ppc4xx: Fix reporting of bootstrap options G and F on 460EX/GT
+
+    Bootstrap options G and F are reported incorrectly (G instead
+    of F and vice versa). This patch fixes this.
+
+    Signed-off-by: Felix Radensky <felix@embedded-sol.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit a200a7c04d89853d2a1395b96d8ca5e3dd754551
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Tue Dec 15 23:20:54 2009 +0100
+
+    Update CHANGELOG; prepare Prepare v2009.11
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit f9476902b789b0481b9df49af88d6ca94fb16fa0
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date:	Tue Dec 15 12:10:47 2009 -0600
+
+    mpc85xx, mpc86xx: Fix gd->cpu pointer after relocation
+
+    The gd->cpu pointer is set to an address located in flash when the
+    probecpu() function is called while U-Boot is executing from flash.
+    This pointer needs to be updated to point to an address in RAM after
+    relocation has occurred otherwise Linux may not be able to boot due to
+    "fdt board" crashing if flash has been erased or changed.
+
+    This bug was introduced in commit
+    a0e2066f392782730f0398095e583c87812d97f2.
+
+    Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+    Reported-by: Ed Swarthout <Ed.Swarthout@freescale.com>
+    Tested-by: Kumar Gala <galak@kernel.crashing.org>
+    Tested on MPC8527DS.
+    Tested by: Ed Swarthout <Ed.Swarthout@freescale.com>
+
+commit 3363a34b9eeda9783afcbbed5cdd738926d1f4bf
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date:	Sun Dec 13 17:58:34 2009 -0600
+
+    MVBLUE: Remove CONFIG_CMD_IRQ
+
+    Neither the MVBLUE nor its underlying architecture implement the
+    do_irqinfo() function which is required when CONFIG_CMD_IRQ is defined.
+    This change fixes the following MVBLUE compiler error:
+
+    -> ./MAKEALL MVBLUE
+    Configuring for MVBLUE board...
+    common/libcommon.a(cmd_irq.o):(.u_boot_cmd+0x24): undefined reference to `do_irqinfo'
+    make: *** [u-boot] Error 1
+
+    Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+    Acked-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
+
+commit 18e8ad60ee87431c01cc2686985b60cc54f5dd3b
+Author: Detlev Zundel <dzu@denx.de>
+Date:	Mon Dec 14 17:54:40 2009 +0100
+
+    imx27lite: Reenable MTD support on NOR flash.
+
+    The support for this was silently dropped by a configuration
+    split during the merge of the imx27lite board support in commit
+    864aa034f3a0e10ce710e8bbda171df3cab59414 (cmd_mtdparts: Move to common
+    handling of FLASH devices via MTD layer).
+
+    Signed-off-by: Detlev Zundel <dzu@denx.de>
+
+commit f4cfe42758192d09f8375e384cc000aa70d97029
+Author: Stefan Roese <sr@denx.de>
+Date:	Wed Dec 9 09:01:43 2009 +0100
+
+    nand: Fix access to last block in NAND devices
+
+    Currently, the last block of NAND devices can't be accessed. This patch
+    fixes this issue by correcting the boundary checking (off-by-one error).
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+    Cc: Scott Wood <scottwood@freescale.com>
+    Cc: Wolfgang Denk <wd@denx.de>
+
+commit 3b887ca8ce72cc12129183538f6e828db13f4867
+Author: Peter Korsgaard <jacmet@sunsite.dk>
+Date:	Tue Dec 8 22:20:34 2009 +0100
+
+    mpc83xx: boot time regression, move LCRR setup back to cpu_init_f
+
+    Commit c7190f02 (retain POR values of non-configured ACR, SPCR, SCCR,
+    and LCRR bitfields) moved the LCRR assignment to after relocation
+    to RAM because of the potential problem with changing the local bus
+    clock while executing from flash.
+
+    This change unfortunately adversely affects the boot time, as running
+    all code up to cpu_init_r can cause significant slowdown.
+
+    E.G. on a 8347 board a bootup time increase of ~600ms has been observed:
+
+       0.020 CPU:   e300c1, MPC8347_PBGA_EA, Rev: 3.0 at 400 MHz, CSB: 266.667 MHz
+       0.168 RS:    232
+       0.172 I2C:   ready
+       0.176 DRAM:  64 MB
+       1.236 FLASH: 32 MB
+
+    Versus:
+
+       0.016 CPU:   e300c1, MPC8347_PBGA_EA, Rev: 3.0 at 400 MHz, CSB: 266.667 MHz
+       0.092 RS:    232
+       0.092 I2C:   ready
+       0.096 DRAM:  64 MB
+       0.644 FLASH: 32 MB
+
+    So far no boards have needed the late LCRR setup, so simply revert it
+    for now - If it is needed at a later time, those boards can either do
+    their own final LCRR setup in board code (E.G. in board_early_init_r),
+    or we can introduce a CONFIG_SYS_LCRR_LATE config option to only do
+    the setup in cpu_init_r.
+
+    Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
+    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 386118a896554b13f14ad0f82356276988f7de82
+Author: Michal Simek <monstr@monstr.eu>
+Date:	Tue Dec 8 09:12:49 2009 +0100
+
+    microblaze: Correct ffs regression for Microblaze
+
+    We are using generic implementation of ffs. This should
+    be part of Simon's commit 0413cfecea350000eab5e591a0965c3e3ee0ff00
+
+    Here is warning message which this patch removes.
+
+    In file included from /tmp/u-boot-microblaze/include/common.h:38,
+		     from cmd_mtdparts.c:87:
+    /tmp/u-boot-microblaze/include/linux/bitops.h:123:1: warning: "ffs" redefined
+    In file included from /tmp/u-boot-microblaze/include/linux/bitops.h:110,
+		     from /tmp/u-boot-microblaze/include/common.h:38,
+		     from cmd_mtdparts.c:87:
+    /tmp/u-boot-microblaze/include/asm/bitops.h:269:1:
+    warning: this is the location of the previous definition
+
+    Signed-off-by: Michal Simek <monstr@monstr.eu>
+
+commit 8fe7b29f9811322931f0192a56431edcf819d6b9
+Author: Graeme Smecher <graeme.smecher@mail.mcgill.ca>
+Date:	Mon Dec 7 08:09:57 2009 -0800
+
+    microblaze: Stop stack clobbering in microblaze-generic.
+
+    A typo caused the stack and malloc regions to overlap, which prevented
+    mem_malloc_init() from returning. This commit makes the memory layout match
+    the example described in include/configs/microblaze-generic.h
+
+    Signed-off-by: Graeme Smecher <graeme.smecher@mail.mcgill.ca>
+    Signed-off-by: Michal Simek <monstr@monstr.eu>
+
+commit 0fc52948bda0734431cb528ee4fd82f1dec8c7b5
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Mon Dec 7 23:14:13 2009 +0100
+
+    Update CHANGELOG, prepare -rc2
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
 commit f2352877cb2daac88115192fb09991a2397d0b27
 Author: Peter Tyser <ptyser@xes-inc.com>
 Date:	Sun Dec 6 23:58:28 2009 -0600

Makefile

@@ -23,8 +23,8 @@
 
 VERSION = 2009
 PATCHLEVEL = 11
-SUBLEVEL =
-EXTRAVERSION = -rc2
+SUBLEVEL = 1
+EXTRAVERSION =
 ifneq "$(SUBLEVEL)" ""
 U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
 else

board/amcc/kilauea/kilauea.c

@@ -39,6 +39,37 @@ DECLARE_GLOBAL_DATA_PTR;
 
 extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
+static int board_cpld_version(void)
+{
+	u32 cpld;
+
+	cpld = in_be32((void *)CONFIG_SYS_FPGA_FIFO_BASE);
+	if ((cpld & CONFIG_SYS_FPGA_MAGIC_MASK) != CONFIG_SYS_FPGA_MAGIC) {
+		/*
+		 * Magic not found -> "old" CPLD revision which needs
+		 * the "old" EBC configuration
+		 */
+		mtebc(PB2AP, EBC_BXAP_BME_ENABLED | EBC_BXAP_FWT_ENCODE(5) |
+		      EBC_BXAP_BWT_ENCODE(0) | EBC_BXAP_BCE_DISABLE |
+		      EBC_BXAP_BCT_2TRANS | EBC_BXAP_CSN_ENCODE(0) |
+		      EBC_BXAP_OEN_ENCODE(0) | EBC_BXAP_WBN_ENCODE(3) |
+		      EBC_BXAP_WBF_ENCODE(0) | EBC_BXAP_TH_ENCODE(4) |
+		      EBC_BXAP_RE_DISABLED | EBC_BXAP_SOR_DELAYED |
+		      EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED);
+
+		/*
+		 * Return 0 for "old" CPLD version
+		 */
+		return 0;
+	}
+
+	/*
+	 * Magic found -> "new" CPLD revision which needs no new
+	 * EBC configuration
+	 */
+	return (cpld & CONFIG_SYS_FPGA_VER_MASK) >> 8;
+}
+
 /*
  * Board early initialization function
  */
@@ -208,6 +239,13 @@ int board_early_init_f (void)
 	val = SDR0_PFC1_USBEN | SDR0_PFC1_USBBIGEN | SDR0_PFC1_GPT_FREQ;
 	mtsdr(SDR0_PFC1, val);
 
+	/*
+	 * The CPLD version detection has to be the first access to
+	 * the CPLD, so we need to make this access this early and
+	 * save the CPLD version for later.
+	 */
+	gd->board_type = board_cpld_version();
+
 	/*
 	 * Configure FPGA register with PCIe reset
 	 */
@@ -276,7 +314,7 @@ int checkboard (void)
 		puts(", serial# ");
 		puts(s);
 	}
-	putc('\n');
+	printf(" (CPLD rev. %ld)\n", gd->board_type);
 
 	return (0);
 }

cpu/mpc83xx/cpu_init.c

@@ -169,6 +169,28 @@ void cpu_init_f (volatile immap_t * im)
 #endif
 #ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
 		(CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) |
+#endif
+		0;
+	__be32 lcrr_mask =
+#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
+		LCRR_DBYP |
+#endif
+#ifdef CONFIG_SYS_LCRR_EADC /* external address delay */
+		LCRR_EADC |
+#endif
+#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
+		LCRR_CLKDIV |
+#endif
+		0;
+	__be32 lcrr_val =
+#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
+		CONFIG_SYS_LCRR_DBYP |
+#endif
+#ifdef CONFIG_SYS_LCRR_EADC
+		CONFIG_SYS_LCRR_EADC |
+#endif
+#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
+		CONFIG_SYS_LCRR_CLKDIV |
 #endif
 		0;
 
@@ -199,6 +221,13 @@ void cpu_init_f (volatile immap_t * im)
 	 */
 	__raw_writel(RMR_CSRE & (1<<RMR_CSRE_SHIFT), &im->reset.rmr);
 
+	/* LCRR - Clock Ratio Register (10.3.1.16)
+	 * write, read, and isync per MPC8379ERM rev.1 CLKDEV field description
+	 */
+	clrsetbits_be32(&im->lbus.lcrr, lcrr_mask, lcrr_val);
+	__raw_readl(&im->lbus.lcrr);
+	isync();
+
 	/* Enable Time Base & Decrementer ( so we will have udelay() )*/
 	setbits_be32(&im->sysconf.spcr, SPCR_TBEN);
 
@@ -331,41 +360,9 @@ void cpu_init_f (volatile immap_t * im)
 
 int cpu_init_r (void)
 {
-	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
 #ifdef CONFIG_QE
 	uint qe_base = CONFIG_SYS_IMMR + 0x00100000; /* QE immr base */
-#endif
-	__be32 lcrr_mask =
-#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
-		LCRR_DBYP |
-#endif
-#ifdef CONFIG_SYS_LCRR_EADC /* external address delay */
-		LCRR_EADC |
-#endif
-#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
-		LCRR_CLKDIV |
-#endif
-		0;
-	__be32 lcrr_val =
-#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
-		CONFIG_SYS_LCRR_DBYP |
-#endif
-#ifdef CONFIG_SYS_LCRR_EADC
-		CONFIG_SYS_LCRR_EADC |
-#endif
-#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
-		CONFIG_SYS_LCRR_CLKDIV |
-#endif
-		0;
 
-	/* LCRR - Clock Ratio Register (10.3.1.16)
-	 * write, read, and isync per MPC8379ERM rev.1 CLKDEV field description
-	 */
-	clrsetbits_be32(&im->lbus.lcrr, lcrr_mask, lcrr_val);
-	__raw_readl(&im->lbus.lcrr);
-	isync();
-
-#ifdef CONFIG_QE
 	qe_init(qe_base);
 	qe_reset();
 #endif

cpu/ppc4xx/44x_spd_ddr2.c

@@ -426,7 +426,7 @@ phys_size_t initdram(int board_type)
 	unsigned char spd0[MAX_SPD_BYTES];
 	unsigned char spd1[MAX_SPD_BYTES];
 	unsigned char *dimm_spd[MAXDIMMS];
-	unsigned long dimm_populated[MAXDIMMS];
+	unsigned long dimm_populated[MAXDIMMS] = {SDRAM_NONE, SDRAM_NONE};
 	unsigned long num_dimm_banks;		/* on board dimm banks */
 	unsigned long val;
 	ddr_cas_id_t selected_cas = DDR_CAS_5;	/* preset to silence compiler */

cpu/ppc4xx/cpu.c

@@ -196,7 +196,7 @@ static char *bootstrap_str[] = {
 	"I2C (Addr 0x54)",	/* A8 */
 	"I2C (Addr 0x52)",	/* A4 */
 };
-static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
+static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' };
 #endif
 
 #if defined(CONFIG_460SX)

drivers/mtd/nand/nand_util.c

@@ -490,7 +490,7 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
 
 	len_incl_bad = get_len_incl_bad (nand, offset, *length);
 
-	if ((offset + len_incl_bad) >= nand->size) {
+	if ((offset + len_incl_bad) > nand->size) {
 		printf ("Attempt to write outside the flash area\n");
 		return -EINVAL;
 	}
@@ -562,7 +562,7 @@ int nand_read_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
 
 	len_incl_bad = get_len_incl_bad (nand, offset, *length);
 
-	if ((offset + len_incl_bad) >= nand->size) {
+	if ((offset + len_incl_bad) > nand->size) {
 		printf ("Attempt to read outside the flash area\n");
 		return -EINVAL;
 	}

drivers/pci/pci_indirect.c

@@ -59,7 +59,8 @@ indirect_##rw##_config_##size(struct pci_controller *hose,               \
 	cfg_##rw(val, hose->cfg_data + (offset & mask), type, op);       \
 	return 0;                                                        \
 }
-#elif defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SPE)
+#elif defined(CONFIG_440GX)  || defined(CONFIG_440GP) || defined(CONFIG_440SP) || \
+      defined(CONFIG_440SPE) || defined(CONFIG_460EX) || defined(CONFIG_460GT)
 #define INDIRECT_PCI_OP(rw, size, type, op, mask)			 \
 static int								 \
 indirect_##rw##_config_##size(struct pci_controller *hose,		 \

include/asm-microblaze/bitops.h

@@ -266,8 +266,6 @@ found_middle:
 	return result + ffz(tmp);
 }
 
-#define ffs(x) generic_ffs(x)
-
 /*
  * hweightN: returns the hamming weight (i.e. the number
  * of bits set) of a N-bit word

include/configs/MVBLUE.h

@@ -88,7 +88,6 @@
 #define CONFIG_CMD_SAVEENV
 #define CONFIG_CMD_FLASH
 #define CONFIG_CMD_IMI
-#define CONFIG_CMD_IRQ
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_RUN

include/configs/imx27lite.h

@@ -145,6 +145,7 @@
 /*
  * MTD
  */
+#define CONFIG_FLASH_CFI_MTD
 #define CONFIG_MTD_DEVICE
 
 /*

include/configs/kilauea.h

@@ -47,6 +47,7 @@
 
 #define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_early_init_f */
 #define CONFIG_MISC_INIT_R	1		/* Call misc_init_r	*/
+#define CONFIG_BOARD_TYPES
 #define CONFIG_BOARD_EMAC_COUNT
 
 /*-----------------------------------------------------------------------
@@ -522,9 +523,22 @@
 #define CONFIG_SYS_EBC_PB1CR		(CONFIG_SYS_NAND_ADDR | 0x1e000)
 #endif
 
-/* Memory Bank 2 (FPGA) initialization						*/
-#define CONFIG_SYS_EBC_PB2AP           0x9400C800
-#define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_FPGA_BASE | 0x18000)
+/* Memory Bank 2 (FPGA) initialization					*/
+#define CONFIG_SYS_EBC_PB2AP		(EBC_BXAP_BME_ENABLED |		\
+					 EBC_BXAP_FWT_ENCODE(6) |	\
+					 EBC_BXAP_BWT_ENCODE(1) |	\
+					 EBC_BXAP_BCE_DISABLE |		\
+					 EBC_BXAP_BCT_2TRANS |		\
+					 EBC_BXAP_CSN_ENCODE(0) |	\
+					 EBC_BXAP_OEN_ENCODE(0) |	\
+					 EBC_BXAP_WBN_ENCODE(3) |	\
+					 EBC_BXAP_WBF_ENCODE(1) |	\
+					 EBC_BXAP_TH_ENCODE(4) |	\
+					 EBC_BXAP_RE_DISABLED |		\
+					 EBC_BXAP_SOR_DELAYED |		\
+					 EBC_BXAP_BEM_WRITEONLY |	\
+					 EBC_BXAP_PEN_DISABLED)
+#define CONFIG_SYS_EBC_PB2CR	(CONFIG_SYS_FPGA_BASE | 0x18000)
 
 #define CONFIG_SYS_EBC_CFG		0x7FC00000 /*  EBC0_CFG */
 
@@ -573,7 +587,7 @@
  * Some Kilauea stuff..., mainly fpga registers
  */
 #define CONFIG_SYS_FPGA_REG_BASE		CONFIG_SYS_FPGA_BASE
-#define CONFIG_SYS_FPGA_FIFO_BASE		(in32(CONFIG_SYS_FPGA_BASE) | (1 << 10))
+#define CONFIG_SYS_FPGA_FIFO_BASE		(CONFIG_SYS_FPGA_BASE | (1 << 10))
 
 /* interrupt */
 #define CONFIG_SYS_FPGA_SLIC0_R_DPRAM_INT	0x80000000
@@ -604,4 +618,8 @@
 #define CONFIG_SYS_FPGA_USER_LED0		0x00000200
 #define CONFIG_SYS_FPGA_USER_LED1		0x00000100
 
+#define CONFIG_SYS_FPGA_MAGIC_MASK		0xffff0000
+#define CONFIG_SYS_FPGA_MAGIC			0xabcd0000
+#define CONFIG_SYS_FPGA_VER_MASK		0x0000ff00
+
 #endif	/* __CONFIG_H */

include/configs/microblaze-generic.h

@@ -146,7 +146,7 @@
 #define	CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
 
 /* stack */
-#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_MONITOR_BASE
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_MALLOC_BASE
 
 /*#define	RAMENV */
 #define	FLASH

lib_ppc/board.c

@@ -645,6 +645,14 @@ void board_init_r (gd_t *id, ulong dest_addr)
 	/* The Malloc area is immediately below the monitor copy in DRAM */
 	malloc_start = dest_addr - TOTAL_MALLOC_LEN;
 
+#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
+	/*
+	 * The gd->cpu pointer is set to an address in flash before relocation.
+	 * We need to update it to point to the same CPU entry in RAM.
+	 */
+	gd->cpu += dest_addr - CONFIG_SYS_MONITOR_BASE;
+#endif
+
 #ifdef CONFIG_SERIAL_MULTI
 	serial_initialize();
 #endif