Prepare v2010.12-rc2

Signed-off-by: Wolfgang Denk <wd@denx.de>

.gitignore

@@ -40,6 +40,9 @@
 /errlog
 /reloc_off
 
+/include/generated/
+/lib/asm-offsets.s
+
 # stgit generated dirs
 patches-*
 .stgit-edit.txt

CREDITS

@@ -22,10 +22,6 @@ N: Guillaume Alexandre
 E: guillaume.alexandre@gespac.ch
 D: Add PCIPPC6 configuration
 
-N: Swen Anderson
-E: sand@peppercon.de
-D: ERIC Support
-
 N: Pantelis Antoniou
 E: panto@intracom.gr
 D: NETVIA & NETPHONE board support, ARTOS support.
@@ -200,10 +196,6 @@ N: Andreas Heppel
 E: aheppel@sysgo.de
 D: CPU Support for MPC 75x; board support for Eltec BAB750 [obsolete!]
 
-N: August Hoeraendl
-E: august.hoerandl@gmx.at
-D: Support for the logodl board (PXA2xx)
-
 N: Josh Huber
 E: huber@alum.wpi.edu
 D: Port to the Galileo Evaluation Board, and the MPC74xx cpu series.
@@ -286,11 +278,6 @@ N: Thomas Lange
 E: thomas@corelatus.se
 D: Support for GTH, GTH2 and dbau1x00 boards; lots of PCMCIA fixes
 
-N: Marc Leeman
-E: marc.leeman@barco.com
-D: Support for Barco Streaming Video Card (SVC) and Sample Compress Network (SCN)
-W: www.barco.com
-
 N: The LEOX team
 E: team@leox.org
 D: Support for LEOX boards, DS164x RTC
@@ -437,11 +424,11 @@ D: FADS823 configuration, MPC823 video support, I2C, wireless keyboard, lots mor
 
 N: Andre Schwarz
 E: andre.schwarz@matrix-vision.de
-D: Support for Matrix Vision boards (MVBLM7/MVBC_P)
+D: Support for Matrix Vision boards (MVBLM7/MVBC_P/MVSMR)
 
 N: Robert Schwebel
 E: r.schwebel@pengutronix.de
-D: Support for csb226, logodl and innokom boards (PXA2xx)
+D: Support for csb226 and innokom boards (PXA2xx)
 
 N: Aaron Sells
 E: sellsa@embeddedplanet.com
@@ -511,6 +498,11 @@ N: Martin Winistoerfer
 E: martinwinistoerfer@gmx.ch
 D: Port to MPC555/556 microcontrollers and support for cmi board
 
+N: David Wu
+E: support@arcturusnetworks.com
+D: Mercury Security EP2500
+W: http://www.arcturusnetworks.com
+
 N: Ming-Len Wu
 E: minglen_wu@techware.com.tw
 D: Motorola MX1ADS board support

MAINTAINERS

@@ -62,6 +62,10 @@ Oliver Brown <obrown@adventnetworks.com>
 
 	gw8260		MPC8260
 
+Cyril Chemparathy <cyril@ti.com>
+
+	tnetv107x_evm	tnetv107x
+
 Conn Clark <clark@esteem.com>
 
 	ESTEEM192E	MPC8xx
@@ -80,7 +84,6 @@ Torsten Demke <torsten.demke@fci.com>
 
 Wolfgang Denk <wd@denx.de>
 
-	IceCube_5100	MGT5100
 	IceCube_5200	MPC5200
 
 	ARIA		MPC5121e
@@ -99,7 +102,6 @@ Wolfgang Denk <wd@denx.de>
 	IVMS8_256	MPC860
 	LANTEC		MPC850
 	LWMON		MPC823
-	NC650		MPC852
 	R360MPI		MPC823
 	RMU		MPC850
 	RRvision	MPC823
@@ -114,7 +116,6 @@ Wolfgang Denk <wd@denx.de>
 	c2mon		MPC855
 	hermes		MPC860
 	lwmon		MPC823
-	pcu_e		MPC855
 
 	CU824		MPC8240
 	Sandpoint8240	MPC8240
@@ -143,16 +144,14 @@ Dirk Eibach <eibach@gdsys.de>
 	dlvision        PPC405EP
 	gdppc440etx	PPC440EP/GR
 	intip		PPC460EX
+	io		PPC405EP
+	iocon		PPC405EP
 	neo		PPC405EP
 
 Dave Ellis <DGE@sixnetio.com>
 
 	SXNI855T	MPC8xx
 
-Fred Fan <fanyefeng@gmail.com>
-
-	mx51evk		i.MX51
-
 Thomas Frieden <ThomasF@hyperion-entertainment.com>
 
 	AmigaOneG3SE	MPC7xx
@@ -195,6 +194,10 @@ Niklaus Giger <niklaus.giger@netstal.com>
 	MCU25		PPC405GPr
 	HCU5		PPC440EPx
 
+Siddarth Gore <gores@marvell.com>
+
+	guruplug	ARM926EJS (Kirkwood SoC)
+
 Frank Gottschling <fgottschling@eltec.de>
 
 	MHPC		MPC8xx
@@ -205,8 +208,6 @@ Wolfgang Grandegger <wg@denx.de>
 
 	ipek01		MPC5200
 
-	CCM		MPC855
-
 	PN62		MPC8240
 	IPHASE4539	MPC8260
 	SCM		MPC8260
@@ -225,6 +226,7 @@ Ilko Iliev <iliev@ronetix.at>
 
 	PM9261		AT91SAM9261
 	PM9263		AT91SAM9263
+	PM9G45		ARM926EJS (AT91SAM9G45 SoC)
 
 Gary Jennejohn <garyj@denx.de>
 
@@ -254,10 +256,6 @@ Sangmoon Kim <dogoil@etinsys.com>
 	debris		MPC8245
 	KVME080		MPC8245
 
-Thomas Lange <thomas@corelatus.se>
-
-	GTH		MPC860
-
 Robert Lazarski <robertlazarski@gmail.com>
 
 	ATUM8548	MPC8548
@@ -308,6 +306,10 @@ Andrea "llandre" Marson <andrea.marson@dave-tech.it>
 
 	PPChameleonEVB	PPC405EP
 
+Tirumala Marri <tmarri@apm.com>
+
+	bluestone       APM821XX
+
 Reinhard Meyer <r.meyer@emk-elektronik.de>
 
 	TOP860		MPC860T
@@ -346,6 +348,14 @@ Daniel Poirot <dan.poirot@windriver.com>
 	sbc8240		MPC8240
 	sbc405		PPC405GP
 
+Sergei Poselenov <sposelenov@emcraft.com>
+
+	a4m072		MPC5200
+
+Sudhakar Rajashekhara <sudhakar.raj@ti.com>
+
+	da850evm	ARM926EJS (DA850/OMAP-L138)
+
 Ricardo Ribalda <ricardo.ribalda@uam.es>
 
 	ml507 		PPC440x5
@@ -369,6 +379,7 @@ Stefan Roese <sr@denx.de>
 	ebony		PPC440GP
 	glacier		PPC460GT
 	haleakala	PPC405EXr
+	icon		PPC440SPe
 	katmai		PPC440SPe
 	kilauea		PPC405EX
 	lwmon5		PPC440EPx
@@ -379,6 +390,7 @@ Stefan Roese <sr@denx.de>
 	rainier		PPC440GRx
 	sequoia		PPC440EPx
 	sycamore	PPC405GPr
+	t3corp		PPC460GT
 	taishan		PPC440GX
 	walnut		PPC405GP
 	yellowstone	PPC440GR
@@ -414,6 +426,7 @@ Heiko Schocher <hs@denx.de>
 	sc3		PPC405GP
 	suen3		ARM926EJS (Kirkwood SoC)
 	uc101		MPC5200
+	ve8313		MPC8313
 
 Peter De Schrijver <p2@mind.be>
 
@@ -423,6 +436,7 @@ Andre Schwarz <andre.schwarz@matrix-vision.de>
 
 	mvbc_p		MPC5200
 	mvblm7		MPC8343
+	mvsmr		MPC5200
 
 Jon Smirl <jonsmirl@gmail.com>
 
@@ -432,6 +446,7 @@ Timur Tabi <timur@freescale.com>
 
 	MPC8349E-mITX	MPC8349
 	MPC8349E-mITX-GP MPC8349
+	P1022DS		P1022
 
 Erik Theisen <etheisen@mindspring.com>
 
@@ -449,10 +464,11 @@ Rune Torgersen <runet@innovsys.com>
 
 Peter Tyser <ptyser@xes-inc.com>
 
-	XPEDITE1000	PPC440GX
-	XPEDITE5170	MPC8640
-	XPEDITE5200	MPC8548
-	XPEDITE5370	MPC8572
+	xpedite1000	PPC440GX
+	xpedite5170	MPC8640
+	xpedite5200	MPC8548
+	xpedite5370	MPC8572
+	xpedite5500	P2020
 
 David Updegraff <dave@cray.com>
 
@@ -467,10 +483,19 @@ Josef Wagner <Wagner@Microsys.de>
 	CPC45		MPC8245
 	PM520		MPC5200
 
+Michael Weiss <michael.weiss@ifm.com>
+
+	PDM360NG	MPC5121e
+
 Stephen Williams <steve@icarus.com>
 
 	JSE		PPC405GPr
 
+Ilya Yanok <yanok@emcraft.com>
+
+	mpc8308_p1m	MPC8308
+	MPC8308RDB	MPC8308
+
 Roy Zang <tie-fei.zang@freescale.com>
 
 	mpc7448hpc2	MPC7448
@@ -499,8 +524,6 @@ Unknown / orphaned boards:
 	RPXClassic	MPC8xx
 	RPXlite		MPC8xx
 
-	ERIC		PPC4xx
-
 	MOUSSE		MPC824x
 
 	RPXsuper	MPC8260
@@ -516,6 +539,10 @@ Unknown / orphaned boards:
 #	Board		CPU						#
 #########################################################################
 
+Albert ARIBAUD <albert.aribaud@free.fr>
+
+	edminiv2	ARM926EJS (Orion5x SoC)
+
 Rowel Atienza <rowel@diwalabs.com>
 
 	armadillo	ARM720T
@@ -524,10 +551,17 @@ Stefano Babic <sbabic@denx.de>
 
 	polaris		xscale
 	trizepsiv	xscale
+	mx51evk		i.MX51
+ 	vision2		i.MX51
+
+Enric Balletbo i Serra <eballetbo@iseebcn.com>
+
+	igep0020	ARM ARMV7 (OMAP3xx SoC)
+	igep0030	ARM ARMV7 (OMAP3xx SoC)
 
 Dirk Behme <dirk.behme@gmail.com>
 
-	omap3_beagle	ARM CORTEX-A8 (OMAP3530 SoC)
+	omap3_beagle	ARM ARMV7 (OMAP3530 SoC)
 
 Eric Benard <eric@eukrea.com>
 
@@ -539,6 +573,10 @@ Rishi Bhattacharya <rishi@ti.com>
 
 	omap5912osk	ARM926EJS
 
+Andreas Bießmann <andreas.devel@gmail.com>
+
+	at91rm9200ek	at91rm9200
+
 Cliff Brake <cliff.brake@gmail.com>
 
 	pxa255_idp	xscale
@@ -551,6 +589,10 @@ Po-Yu Chuang <ratbert@faraday-tech.com>
 
 	a320evb		FA526 (ARM920T-like) (a320 SoC)
 
+Eric Cooper <ecc@cmu.edu>
+
+	dockstar	ARM926EJS (Kirkwood SoC)
+
 George G. Davis <gdavis@mvista.com>
 
 	assabet		SA1100
@@ -564,6 +606,10 @@ Thomas Elste <info@elste.org>
 
 	modnet50	ARM720T (NET+50)
 
+Kristoffer Ericson <kristoffer.ericson@gmail.com>
+
+	jornada	SA1110
+
 Fabio Estevam <Fabio.Estevam@freescale.com>
 
 	mx31pdk		i.MX31
@@ -591,9 +637,13 @@ Kshitij Gupta <kshitij@ti.com>
 	omap1510inn	ARM925T
 	omap1610inn	ARM926EJS
 
+Vaibhav Hiremath <hvaibhav@ti.com>
+
+	am3517_evm	ARM ARMV7 (AM35x SoC)
+
 Grazvydas Ignotas <notasas@gmail.com>
 
-	omap3_pandora	ARM CORTEX-A8 (OMAP3xx SoC)
+	omap3_pandora	ARM ARMV7 (OMAP3xx SoC)
 
 Gary Jennejohn <garyj@denx.de>
 
@@ -621,9 +671,14 @@ Nishant Kamat <nskamat@ti.com>
 
 	omap1610h2	ARM926EJS
 
+Minkyu Kang <mk7.kang@samsung.com>
+
+	s5p_goni	ARM ARMV7 (S5PC110 SoC)
+	SMDKC100	ARM ARMV7 (S5PC100 SoC)
+
 Frederik Kriewitz <frederik@kriewitz.eu>
 
-	devkit8000	ARM CORTEX-A8 (OMAP3530 SoC)
+	devkit8000	ARM ARMV7 (OMAP3530 SoC)
 
 Sergey Kubushyn <ksi@koi8.net>
 
@@ -631,31 +686,25 @@ Sergey Kubushyn <ksi@koi8.net>
 	SONATA		ARM926EJS
 	SCHMOOGIE	ARM926EJS
 
-Sandeep Paulraj <s-paulraj@ti.com>
-
-	davinci_dm355evm	ARM926EJS
-	davinci_dm355leopard	ARM926EJS
-	davinci_dm365evm	ARM926EJS
-	davinci_dm6467evm	ARM926EJS
-
 Prakash Kumar <prakash@embedx.com>
 
 	cerf250		xscale
 
+Vipin Kumar <vipin.kumar@st.com>
+
+	spear300	ARM926EJS (spear300 Soc)
+	spear310	ARM926EJS (spear310 Soc)
+	spear320	ARM926EJS (spear320 Soc)
+	spear600	ARM926EJS (spear600 Soc)
+
 Sergey Lapin <slapin@ossfans.org>
 
 	afeb9260	ARM926EJS (AT91SAM9260 SoC)
 
-Guennadi Liakhovetski <g.liakhovetski@gmx.de>
-
-	imx31_phycore_eet	i.MX31
-	mx31ads			i.MX31
-	SMDK6400		S3C6400
-
 Nishanth Menon <nm@ti.com>
 
-	omap3_sdp3430	ARM CORTEX-A8 (OMAP3xx SoC)
-	omap3_zoom1	ARM CORTEX-A8 (OMAP3xx SoC)
+	omap3_sdp3430	ARM ARMV7 (OMAP3xx SoC)
+	omap3_zoom1	ARM ARMV7 (OMAP3xx SoC)
 
 David Müller <d.mueller@elsoft.ch>
 
@@ -674,6 +723,13 @@ Kyungmin Park <kyungmin.park@samsung.com>
 
 	apollon		ARM1136EJS
 
+Sandeep Paulraj <s-paulraj@ti.com>
+
+	davinci_dm355evm	ARM926EJS
+	davinci_dm355leopard	ARM926EJS
+	davinci_dm365evm	ARM926EJS
+	davinci_dm6467evm	ARM926EJS
+
 Peter Pearse <peter.pearse@arm.com>
 	integratorcp	All current ARM supplied & supported core modules
 			-see http://www.arm.com/products/DevTools/Hardware_Platforms.html
@@ -686,7 +742,7 @@ Dave Peverley <dpeverley@mpc-data.co.uk>
 
 Manikandan Pillai <mani.pillai@ti.com>
 
-	omap3_evm	ARM CORTEX-A8 (OMAP3xx SoC)
+	omap3_evm	ARM ARMV7 (OMAP3xx SoC)
 
 Stelian Pop <stelian.pop@leadtechdesign.com>
 
@@ -698,7 +754,7 @@ Stelian Pop <stelian.pop@leadtechdesign.com>
 
 Tom Rix <Tom.Rix@windriver.com>
 
-	omap3_zoom2	ARM CORTEX-A8 (OMAP3xx SoC)
+	omap3_zoom2	ARM ARMV7 (OMAP3xx SoC)
 
 John Rigby <jcrigby@gmail.com>
 
@@ -717,12 +773,18 @@ Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com>
 
 Steve Sakoman <sakoman@gmail.com>
 
-	omap3_overo	ARM CORTEX-A8 (OMAP3xx SoC)
+	omap3_overo	ARM ARMV7 (OMAP3xx SoC)
+	omap4_panda	ARM ARMV7 (OMAP4xx SoC)
+	omap4_sdp4430	ARM ARMV7 (OMAP4xx SoC)
 
 Jens Scharsig <esw@bus-elektronik.de>
 
 	eb_cpux9k2	ARM920T (AT91RM9200 SoC)
 
+Heiko Schocher <hs@denx.de>
+
+	magnesium	i.MX27
+
 Robert Schwebel <r.schwebel@pengutronix.de>
 
 	csb226		xscale
@@ -755,16 +817,33 @@ Greg Ungerer <greg.ungerer@opengear.com>
 	cm4116		ks8695p
 	cm4148		ks8695p
 
+Marek Vasut <marek.vasut@gmail.com>
+
+	balloon3	xscale
+	colibri_pxa270	xscale
+	palmld		xscale
+	palmtc		xscale
+	vpac270		xscale
+	zipitz2		xscale
+
 Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
 
 	SFFSDR		ARM926EJS
 
+Matt Waddel <matt.waddel@linaro.org>
+
+	ca9x4_ct_vxp	ARM ARMV7 (Quad Core)
+
 Prafulla Wadaskar <prafulla@marvell.com>
 
 	mv88f6281gtw_ge	ARM926EJS (Kirkwood SoC)
 	rd6281a		ARM926EJS (Kirkwood SoC)
 	sheevaplug	ARM926EJS (Kirkwood SoC)
 
+Matthias Weisser <weisserm@arcor.de>
+
+	jadecpu		ARM926EJS (MB86R01 SoC)
+
 Richard Woodruff <r-woodruff2@ti.com>
 
 	omap2420h4	ARM1136EJS
@@ -774,10 +853,6 @@ Alex Z
 	lart		SA1100
 	dnp1110		SA1110
 
-Minkyu Kang <mk7.kang@samsung.com>
-
-	SMDKC100	ARM CORTEX-A8 (S5PC100 SoC)
-
 -------------------------------------------------------------------------
 
 Unknown / orphaned boards:
@@ -787,6 +862,10 @@ Unknown / orphaned boards:
 	ixdp425		xscale	Kyle Harris <kharris@nexus-tech.net> / dead address
 	lubbock		xscale	Kyle Harris <kharris@nexus-tech.net> / dead address
 
+	imx31_phycore_eet i.MX31  Guennadi Liakhovetski <g.liakhovetski@gmx.de> / resigned
+	mx31ads		  i.MX31  Guennadi Liakhovetski <g.liakhovetski@gmx.de> / resigned
+	SMDK6400	  S3C6400 Guennadi Liakhovetski <g.liakhovetski@gmx.de> / resigned
+
 #########################################################################
 # x86 Systems:								#
 #									#
@@ -821,22 +900,6 @@ Stefan Roese <sr@denx.de>
 
 	vct_xxx		MIPS32 4Kc
 
-#########################################################################
-# Nios-32 Systems:							#
-#									#
-# Maintainer Name, Email Address					#
-#	Board		CPU						#
-#########################################################################
-
-Stephan Linz <linz@li-pro.net>
-
-	DK1S10		Nios-32
-	ADNPESC1	Nios-32
-
-Scott McNutt <smcnutt@psyent.com>
-
-	DK1C20		Nios-32
-
 #########################################################################
 # Nios-II Systems:							#
 #									#
@@ -848,9 +911,7 @@ Scott McNutt <smcnutt@psyent.com>
 
 	PCI5441		Nios-II
 	PK1C20		Nios-II
-	EP1C20		Nios-II
-	EP1S10		Nios-II
-	EP1S40		Nios-II
+	nios2-generic	Nios-II
 
 #########################################################################
 # MicroBlaze Systems:							#
@@ -890,6 +951,10 @@ TsiChung Liew <Tsi-Chung.Liew@freescale.com>
 	M5475EVB	mcf547x_8x
 	M5485EVB	mcf547x_8x
 
+Wolfgang Wegner <w.wegner@astro-kom.de>
+
+	astro_mcf5373l	MCF5373L
+
 #########################################################################
 # AVR32 Systems:							#
 #									#
@@ -964,6 +1029,7 @@ Blackfin Team <u-boot-devel@blackfin.uclinux.org>
 	BF526-EZBRD	BF526
 	BF527-EZKIT	BF527
 	BF527-EZKIT-V2	BF527
+	BF527-SDP	BF527
 	BF533-EZKIT	BF533
 	BF533-STAMP	BF533
 	BF537-PNAV	BF537
@@ -972,6 +1038,8 @@ Blackfin Team <u-boot-devel@blackfin.uclinux.org>
 	BF548-EZKIT	BF548
 	BF561-EZKIT	BF561
 
+	BF527-AD7160-EVAL	BF527
+
 Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
 Blackfin Team <u-boot-devel@blackfin.uclinux.org>
 
@@ -991,9 +1059,12 @@ Blackfin Team <u-boot-devel@blackfin.uclinux.org>
 	BF537-srv1	BF537
 
 Wojtek Skulski <skulski@pas.rochester.edu>
+Wojtek Skulski <info@skutek.com>
+Blackfin Team <u-boot-devel@blackfin.uclinux.org>
 Benjamin Matthews <mben12@gmail.com>
 
-	BLACKSTAMP	BF532
+	BlackStamp	BF533
+	BlackVME	BF561
 
 I-SYST Micromodule <support@i-syst.com>
 Blackfin Team <u-boot-devel@blackfin.uclinux.org>
@@ -1005,6 +1076,14 @@ Anton Shurpin <shurpin.aa@niistt.ru>
 
 	BF561-ACVILON	BF561
 
+Brent Kandetzki <brentk@teleco.com>
+
+	IP04		BF532
+
+Peter Meerwald <devel@bct-electronic.com>
+
+	bct-brettl2	BF536
+
 #########################################################################
 # End of MAINTAINERS list						#
 #########################################################################

MAKEALL

@@ -1,5 +1,140 @@
 #!/bin/bash
 
+# Tool mainly for U-Boot Quality Assurance: build one or more board
+# configurations with minimal verbosity, showing only warnings and
+# errors.
+#
+# There are several ways to select which boards to build.
+#
+# Traditionally, architecture names (like "powerpc"), CPU family names
+# (like "mpc83xx") or board names can be specified on the command
+# line; without any arguments, MAKEALL defaults to building all Power
+# Architecture systems (i. e. same as for "MAKEALL powerpc").
+#
+# With the introduction of the board.cfg file, it has become possible
+# to provide additional selections.  We use standard command line
+# options for this:
+#
+# -a or --arch	:	Select architecture
+# -c or --cpu	:	Select CPU family
+# -s or --soc	:	Select SoC type
+# -v or --vendor:	Select board vendor
+#
+# Selections by these options are logically ANDed; if the same option
+# is used repeatedly, such selections are ORed.  So "-v FOO -v BAR"
+# will select all configurations where the vendor is either FOO or
+# BAR.  Any additional arguments specified on the command line are
+# always build additionally.
+#
+# Examples:
+#
+# - build all Power Architecture boards:
+#
+#	MAKEALL -a powerpc
+#   or
+#	MAKEALL --arch powerpc
+#   or
+#	MAKEALL powerpc
+#
+# - build all PowerPC boards manufactured by vendor "esd":
+#
+#	MAKEALL -a powerpc -v esd
+#
+# - build all PowerPC boards manufactured either by "keymile" or
+#   "siemens":
+#
+#	MAKEALL -a powerpc -v keymile -v siemens
+#
+# - build all Freescale boards with MPC83xx CPUs, plus all 4xx boards:
+#
+#	MAKEALL -c mpc83xx -v freescale 4xx
+#
+#########################################################################
+
+SHORT_OPTS="a:c:v:s:"
+LONG_OPTS="arch:,cpu:,vendor:,soc:"
+
+# Option processing based on util-linux-2.13/getopt-parse.bash
+
+# Note that we use `"$@"' to let each command-line parameter expand to a
+# separate word. The quotes around `$@' are essential!
+# We need TEMP as the `eval set --' would nuke the return value of
+# getopt.
+TEMP=`getopt -o ${SHORT_OPTS} --long ${LONG_OPTS} \
+     -n 'MAKEALL' -- "$@"`
+
+if [ $? != 0 ] ; then echo "Terminating..." >&2 ; exit 1 ; fi
+
+# Note the quotes around `$TEMP': they are essential!
+eval set -- "$TEMP"
+
+SELECTED=''
+
+while true ; do
+	case "$1" in
+	-a|--arch)
+		# echo "Option ARCH: argument \`$2'"
+		if [ "$opt_a" ] ; then
+			opt_a="${opt_a%)} || \$2 == \"$2\")"
+		else
+			opt_a="(\$2 == \"$2\")"
+		fi
+		SELECTED='y'
+		shift 2 ;;
+	-c|--cpu)
+		# echo "Option CPU: argument \`$2'"
+		if [ "$opt_c" ] ; then
+			opt_c="${opt_c%)} || \$3 == \"$2\")"
+		else
+			opt_c="(\$3 == \"$2\")"
+		fi
+		SELECTED='y'
+		shift 2 ;;
+	-s|--soc)
+		# echo "Option SoC: argument \`$2'"
+		if [ "$opt_s" ] ; then
+			opt_s="${opt_s%)} || \$6 == \"$2\")"
+		else
+			opt_s="(\$6 == \"$2\")"
+		fi
+		SELECTED='y'
+		shift 2 ;;
+	-v|--vendor)
+		# echo "Option VENDOR: argument \`$2'"
+		if [ "$opt_v" ] ; then
+			opt_v="${opt_v%)} || \$5 == \"$2\")"
+		else
+			opt_v="(\$5 == \"$2\")"
+		fi
+		SELECTED='y'
+		shift 2 ;;
+	--)
+		shift ; break ;;
+	*)
+		echo "Internal error!" >&2 ; exit 1 ;;
+	esac
+done
+# echo "Remaining arguments:"
+# for arg do echo '--> '"\`$arg'" ; done
+
+FILTER="\$1 !~ /^#/"
+[ "$opt_a" ] && FILTER="${FILTER} && $opt_a"
+[ "$opt_c" ] && FILTER="${FILTER} && $opt_c"
+[ "$opt_s" ] && FILTER="${FILTER} && $opt_s"
+[ "$opt_v" ] && FILTER="${FILTER} && $opt_v"
+
+if [ "$SELECTED" ] ; then
+	SELECTED=$(awk '('"$FILTER"') { print $1 }' boards.cfg)
+
+	# Make sure some boards from boards.cfg are actually found
+	if [ -z "$SELECTED" ] ; then
+		echo "Error: No boards selected, invalid arguments"
+		exit 1
+	fi
+fi
+
+#########################################################################
+
 # Print statistics when we exit
 trap exit 1 2 3 15
 trap print_stats 0
@@ -41,444 +176,89 @@ ERR_LIST=""
 TOTAL_CNT=0
 RC=0
 
+# Helper funcs for parsing boards.cfg
+boards_by_field()
+{
+	awk \
+		-v field="$1" \
+		-v select="$2" \
+		'($1 !~ /^#/ && $field == select) { print $1 }' \
+		boards.cfg
+}
+boards_by_arch() { boards_by_field 2 "$@" ; }
+boards_by_cpu()  { boards_by_field 3 "$@" ; }
+
 #########################################################################
 ## MPC5xx Systems
 #########################################################################
 
-LIST_5xx="		\
-	cmi_mpc5xx	\
-"
+LIST_5xx="$(boards_by_cpu mpc5xx)"
 
 #########################################################################
 ## MPC5xxx Systems
 #########################################################################
 
-LIST_5xxx="		\
-	BC3450		\
-	cm5200		\
-	cpci5200	\
-	digsy_mtc	\
-	EVAL5200	\
-	fo300		\
-	galaxy5200	\
-	icecube_5100	\
-	icecube_5200	\
-	inka4x0		\
-	ipek01		\
-	lite5200b	\
-	mcc200		\
-	mecp5200	\
-	motionpro	\
-	munices		\
-	MVBC_P		\
-	o2dnt		\
-	pcm030		\
-	pf5200		\
-	PM520		\
-	TB5200		\
-	Total5100	\
-	Total5200	\
-	Total5200_Rev2	\
-	TQM5200		\
-	TQM5200_B	\
-	TQM5200S	\
-	v38b		\
-"
+LIST_5xxx="$(boards_by_cpu mpc5xxx)"
 
 #########################################################################
 ## MPC512x Systems
 #########################################################################
 
-LIST_512x="		\
-	aria		\
-	mecp5123	\
-	mpc5121ads	\
-"
+LIST_512x="$(boards_by_cpu mpc512x)"
 
 #########################################################################
 ## MPC8xx Systems
 #########################################################################
-LIST_8xx="		\
-	Adder87x	\
-	AdderII		\
-	ADS860		\
-	AMX860		\
-	c2mon		\
-	CCM		\
-	cogent_mpc8xx	\
-	ELPT860		\
-	EP88x		\
-	ESTEEM192E	\
-	ETX094		\
-	FADS823		\
-	FADS850SAR	\
-	FADS860T	\
-	FLAGADM		\
-	FPS850L		\
-	GEN860T		\
-	GEN860T_SC	\
-	GENIETV		\
-	GTH		\
-	hermes		\
-	IAD210		\
-	ICU862_100MHz	\
-	IP860		\
-	IVML24		\
-	IVML24_128	\
-	IVML24_256	\
-	IVMS8		\
-	IVMS8_128	\
-	IVMS8_256	\
-	KUP4K		\
-	KUP4X		\
-	LANTEC		\
-	lwmon		\
-	kmsupx4		\
-	MBX		\
-	MBX860T		\
-	mgsuvd		\
-	MHPC		\
-	MPC86xADS	\
-	MPC885ADS	\
-	NETPHONE	\
-	NETTA		\
-	NETTA2		\
-	NETTA_ISDN	\
-	NETVIA		\
-	NETVIA_V2	\
-	NX823		\
-	pcu_e		\
-	QS823		\
-	QS850		\
-	QS860T		\
-	quantum		\
-	R360MPI		\
-	RBC823		\
-	rmu		\
-	RPXClassic	\
-	RPXlite		\
-	RPXlite_DW	\
-	RRvision	\
-	SM850		\
-	spc1920		\
-	SPD823TS	\
-	svm_sc8xx	\
-	SXNI855T	\
-	TK885D		\
-	TOP860		\
-	TQM823L		\
-	TQM823L_LCD	\
-	TQM850L		\
-	TQM855L		\
-	TQM860L		\
-	TQM885D		\
-	uc100		\
-	v37		\
-"
+
+LIST_8xx="$(boards_by_cpu mpc8xx)"
 
 #########################################################################
 ## PPC4xx Systems
 #########################################################################
 
-LIST_4xx="		\
-	acadia		\
-	acadia_nand	\
-	ADCIOP		\
-	alpr		\
-	AP1000		\
-	AR405		\
-	arches		\
-	ASH405		\
-	bamboo		\
-	bamboo_nand	\
-	bubinga		\
-	CANBT		\
-	canyonlands	\
-	canyonlands_nand \
-	CMS700		\
-	CPCI2DP		\
-	CPCI405		\
-	CPCI4052	\
-	CPCI405AB	\
-	CPCI405DT	\
-	CPCIISER4	\
-	CRAYL1		\
-	csb272		\
-	csb472		\
-	DASA_SIM	\
-	devconcenter	\
-	dlvision	\
-	DP405		\
-	DU405		\
-	DU440		\
-	ebony		\
-	ERIC		\
-	fx12mm		\
-	G2000		\
-	gdppc440etx	\
-	glacier		\
-	haleakala	\
-	haleakala_nand	\
-	hcu4		\
-	hcu5		\
-	HH405		\
-	HUB405		\
-	intip		\
-	JSE		\
-	KAREF		\
-	katmai		\
-	kilauea		\
-	kilauea_nand	\
-	korat		\
-	luan		\
-	lwmon5		\
-	makalu		\
-	mcu25		\
-	METROBOX	\
-	MIP405		\
-	MIP405T		\
-	ML2		\
-	ml507		\
-	ml507_flash	\
-	neo		\
-	ocotea		\
-	OCRTC		\
-	ORSG		\
-	p3p440		\
-	PCI405		\
-	pcs440ep	\
-	PIP405		\
-	PLU405		\
-	PMC405		\
-	PMC405DE	\
-	PMC440		\
-	PPChameleonEVB	\
-	quad100hd	\
-	rainier		\
-	redwood		\
-	sbc405		\
-	sc3		\
-	sequoia		\
-	sequoia_nand	\
-	taihu		\
-	taishan		\
-	v5fx30teval	\
-	v5fx30teval_flash \
-	VOH405		\
-	VOM405		\
-	W7OLMC		\
-	W7OLMG		\
-	walnut		\
-	WUH405		\
-	xilinx-ppc440-generic \
-	xilinx-ppc440-generic_flash \
-	XPEDITE1000	\
-	yellowstone	\
-	yosemite	\
-	yucca		\
-	zeus		\
-"
+LIST_4xx="$(boards_by_cpu ppc4xx)"
 
 #########################################################################
 ## MPC8220 Systems
 #########################################################################
 
-LIST_8220="		\
-	Alaska8220	\
-	Yukon8220	\
-"
+LIST_8220="$(boards_by_cpu mpc8220)"
 
 #########################################################################
 ## MPC824x Systems
 #########################################################################
 
-LIST_824x="		\
-	A3000		\
-	barco		\
-	BMW		\
-	CPC45		\
-	CU824		\
-	debris		\
-	eXalion		\
-	HIDDEN_DRAGON	\
-	IDS8247		\
-	linkstation_HGLAN	\
-	MOUSSE		\
-	MUSENKI		\
-	MVBLUE		\
-	OXC		\
-	PN62		\
-	Sandpoint8240	\
-	Sandpoint8245	\
-	sbc8240		\
-	utx8245		\
-"
+LIST_824x="$(boards_by_cpu mpc824x)"
 
 #########################################################################
 ## MPC8260 Systems (includes 8250, 8255 etc.)
 #########################################################################
 
-LIST_8260="		\
-	atc		\
-	cogent_mpc8260	\
-	CPU86		\
-	CPU87		\
-	ep8248		\
-	ep8260		\
-	ep82xxm		\
-	gw8260		\
-	hymod		\
-	IPHASE4539	\
-	ISPAN		\
-	mgcoge		\
-	MPC8260ADS	\
-	MPC8266ADS	\
-	MPC8272ADS	\
-	PM826		\
-	PM828		\
-	ppmc8260	\
-	Rattler8248	\
-	RPXsuper	\
-	rsdproto	\
-	sacsng		\
-	sbc8260		\
-	SCM		\
-	TQM8260_AC	\
-	TQM8260_AD	\
-	TQM8260_AE	\
-	TQM8272		\
-	ZPC1900		\
-"
+LIST_8260="$(boards_by_cpu mpc8260)"
 
 #########################################################################
 ## MPC83xx Systems (includes 8349, etc.)
 #########################################################################
 
-LIST_83xx="		\
-	caddy2		\
-	kmeter1		\
-	MPC8313ERDB_33	\
-	MPC8313ERDB_NAND_66	\
-	MPC8315ERDB	\
-	MPC8315ERDB_NAND	\
-	MPC8323ERDB	\
-	MPC832XEMDS	\
-	MPC832XEMDS_ATM	\
-	MPC8349EMDS	\
-	MPC8349ITX	\
-	MPC8349ITXGP	\
-	MPC8360EMDS	\
-	MPC8360EMDS_ATM	\
-	MPC8360ERDK_33	\
-	MPC8360ERDK_66	\
-	MPC837XEMDS	\
-	MPC837XERDB	\
-	MVBLM7		\
-	sbc8349		\
-	SIMPC8313_LP	\
-	TQM834x		\
-	vme8349		\
-"
-
+LIST_83xx="$(boards_by_cpu mpc83xx)"
 
 #########################################################################
 ## MPC85xx Systems (includes 8540, 8560 etc.)
 #########################################################################
 
-LIST_85xx="		\
-	ATUM8548	\
-	MPC8536DS	\
-	MPC8536DS_NAND	\
-	MPC8536DS_SDCARD	\
-	MPC8536DS_SPIFLASH	\
-	MPC8540ADS	\
-	MPC8540EVAL	\
-	MPC8541CDS	\
-	MPC8544DS	\
-	MPC8548CDS	\
-	MPC8555CDS	\
-	MPC8560ADS	\
-	MPC8568MDS	\
-	MPC8569MDS	\
-	MPC8569MDS_ATM	\
-	MPC8569MDS_NAND \
-	MPC8572DS	\
-	MPC8572DS_36BIT	\
-	P2020DS		\
-	P2020DS_36BIT	\
-	P1011RDB	\
-	P1011RDB_NAND	\
-	P1011RDB_SDCARD	\
-	P1011RDB_SPIFLASH	\
-	P1020RDB	\
-	P1020RDB_NAND	\
-	P1020RDB_SDCARD	\
-	P1020RDB_SPIFLASH	\
-	P2010RDB	\
-	P2010RDB_NAND	\
-	P2010RDB_SDCARD	\
-	P2010RDB_SPIFLASH	\
-	P2020RDB	\
-	P2020RDB_NAND	\
-	P2020RDB_SDCARD	\
-	P2020RDB_SPIFLASH	\
-	PM854		\
-	PM856		\
-	sbc8540		\
-	sbc8548		\
-	sbc8548_PCI_33	\
-	sbc8548_PCI_66	\
-	sbc8548_PCI_33_PCIE \
-	sbc8548_PCI_66_PCIE \
-	sbc8560		\
-	socrates	\
-	stxgp3		\
-	stxssa		\
-	TQM8540		\
-	TQM8541		\
-	TQM8548		\
-	TQM8548_AG	\
-	TQM8548_BE	\
-	TQM8555		\
-	TQM8560		\
-	XPEDITE5200	\
-	XPEDITE5370	\
-"
+LIST_85xx="$(boards_by_cpu mpc85xx)"
 
 #########################################################################
 ## MPC86xx Systems
 #########################################################################
 
-LIST_86xx="		\
-	MPC8610HPCD	\
-	MPC8641HPCN	\
-	sbc8641d	\
-	XPEDITE5170	\
-"
+LIST_86xx="$(boards_by_cpu mpc86xx)"
 
 #########################################################################
 ## 74xx/7xx Systems
 #########################################################################
 
-LIST_74xx="		\
-	DB64360		\
-	DB64460		\
-	EVB64260	\
-	mpc7448hpc2	\
-	P3G4		\
-	p3m7448		\
-	PCIPPC2		\
-	PCIPPC6		\
-	ZUMA		\
-"
-
-LIST_7xx="		\
-	BAB7xx		\
-	CPCI750		\
-	ELPPC		\
-	p3m750		\
-	ppmc7xx		\
-"
+LIST_74xx_7xx="$(boards_by_cpu 74xx_7xx)"
 
 #########################################################################
 ## PowerPC groups
@@ -490,7 +270,7 @@ LIST_TSEC="		\
 	${LIST_86xx}	\
 "
 
-LIST_ppc="		\
+LIST_powerpc="		\
 	${LIST_5xx}	\
 	${LIST_512x}	\
 	${LIST_5xxx}	\
@@ -502,21 +282,20 @@ LIST_ppc="		\
 	${LIST_85xx}	\
 	${LIST_86xx}	\
 	${LIST_4xx}	\
-	${LIST_74xx}	\
-	${LIST_7xx}	\
+	${LIST_74xx_7xx}\
+"
+
+# Alias "ppc" -> "powerpc" to not break compatibility with older scripts
+# still using "ppc" instead of "powerpc"
+LIST_ppc="		\
+	${LIST_powerpc}	\
 "
 
 #########################################################################
 ## StrongARM Systems
 #########################################################################
 
-LIST_SA="		\
-	assabet		\
-	dnp1110		\
-	gcplus		\
-	lart		\
-	shannon		\
-"
+LIST_SA="$(boards_by_cpu sa1100)"
 
 #########################################################################
 ## ARM7 Systems
@@ -553,6 +332,7 @@ LIST_ARM9="			\
 	cp946es			\
 	cp966			\
 	da830evm		\
+	da850evm		\
 	edb9301			\
 	edb9302			\
 	edb9302a		\
@@ -561,8 +341,12 @@ LIST_ARM9="			\
 	edb9312			\
 	edb9315			\
 	edb9315a		\
+	edminiv2		\
+	guruplug		\
 	imx27lite		\
+	jadecpu			\
 	lpd7a400		\
+	magnesium		\
 	mv88f6281gtw_ge		\
 	mx1ads			\
 	mx1fs2			\
@@ -625,13 +409,18 @@ LIST_ARM11="			\
 	mx31pdk_nand		\
 	qong			\
 	smdk6400		\
+	tnetv107x_evm		\
 "
 
 #########################################################################
-## ARM Cortex-A8 Systems
+## ARMV7 Systems
 #########################################################################
-LIST_ARM_CORTEX_A8="		\
+LIST_ARMV7="		\
+	am3517_evm		\
+	ca9x4_ct_vxp		\
 	devkit8000		\
+	igep0020		\
+	igep0030		\
 	mx51evk			\
 	omap3_beagle		\
 	omap3_overo		\
@@ -640,6 +429,9 @@ LIST_ARM_CORTEX_A8="		\
 	omap3_sdp3430		\
 	omap3_zoom1		\
 	omap3_zoom2		\
+	omap4_panda		\
+	omap4_sdp4430		\
+	s5p_goni		\
 	smdkc100		\
 "
 
@@ -672,6 +464,7 @@ LIST_at91="			\
 	otc570			\
 	pm9261			\
 	pm9263			\
+	pm9g45			\
 	SBC35_A9G20		\
 	TNY_A9260		\
 	TNY_A9G20		\
@@ -681,31 +474,9 @@ LIST_at91="			\
 ## Xscale Systems
 #########################################################################
 
-LIST_pxa="		\
-	cerf250		\
-	cradle		\
-	csb226		\
-	delta		\
-	innokom		\
-	lubbock		\
-	pleb2		\
-	polaris		\
-	pxa255_idp	\
-	trizepsiv	\
-	wepep250	\
-	xaeniax		\
-	xm250		\
-	xsengine	\
-	zylonite	\
-"
+LIST_pxa="$(boards_by_cpu pxa)"
 
-LIST_ixp="		\
-	actux1		\
-	actux2		\
-	actux3		\
-	actux4		\
-	ixdp425		\
-	ixdpg425	\
+LIST_ixp="$(boards_by_cpu ixp)
 	pdnb3		\
 	scpu		\
 "
@@ -720,7 +491,7 @@ LIST_arm="			\
 	${LIST_ARM9}		\
 	${LIST_ARM10}		\
 	${LIST_ARM11}		\
-	${LIST_ARM_CORTEX_A8}	\
+	${LIST_ARMV7}	\
 	${LIST_at91}		\
 	${LIST_pxa}		\
 	${LIST_ixp}		\
@@ -789,167 +560,68 @@ LIST_mips_el="			\
 ## i386 Systems
 #########################################################################
 
-LIST_I486="		\
-	sc520_cdp	\
-	sc520_eNET	\
-	sc520_spunk	\
-	sc520_spunk_rel	\
-"
-
-LIST_x86="		\
-	${LIST_I486}	\
-"
-
-#########################################################################
-## NIOS Systems
-#########################################################################
-
-LIST_nios="			\
-	ADNPESC1		\
-	ADNPESC1_base_32	\
-	ADNPESC1_DNPEVA2_base_32\
-	DK1C20			\
-	DK1C20_standard_32	\
-	DK1S10			\
-	DK1S10_standard_32	\
-	DK1S10_mtx_ldk_20	\
-"
+LIST_x86="$(boards_by_arch i386)"
 
 #########################################################################
 ## Nios-II Systems
 #########################################################################
 
-LIST_nios2="		\
-	EP1C20		\
-	EP1S10		\
-	EP1S40		\
-	PCI5441		\
-	PK1C20		\
+LIST_nios2="$(boards_by_arch nios2)
+	nios2-generic	\
 "
 
 #########################################################################
 ## MicroBlaze Systems
 #########################################################################
 
-LIST_microblaze="			\
-	microblaze-generic		\
-"
+LIST_microblaze="$(boards_by_arch microblaze)"
 
 #########################################################################
 ## ColdFire Systems
 #########################################################################
 
-LIST_coldfire="			\
+LIST_coldfire="$(boards_by_arch m68k)
+	astro_mcf5373l		\
 	cobra5272		\
 	EB+MCF-EV123		\
 	EB+MCF-EV123_internal	\
-	idmr			\
-	M5208EVBE		\
 	M52277EVB		\
 	M5235EVB		\
-	M5249EVB		\
-	M5253DEMO		\
-	M5253EVBE		\
-	M5271EVB		\
-	M5272C3			\
-	M5275EVB		\
-	M5282EVB		\
-	M53017EVB		\
 	M5329AFEE		\
 	M5373EVB		\
 	M54451EVB		\
 	M54455EVB		\
 	M5475AFE		\
 	M5485AFE		\
-	TASREG			\
 "
 
 #########################################################################
 ## AVR32 Systems
 #########################################################################
 
-LIST_avr32="		\
-	atstk1002	\
-	atstk1003	\
-	atstk1004	\
-	atstk1006	\
-	atngw100	\
-	favr-32-ezkit	\
-	hammerhead	\
-	mimc200		\
-"
+LIST_avr32="$(boards_by_arch avr32)"
 
 #########################################################################
 ## Blackfin Systems
 #########################################################################
 
-LIST_blackfin="		\
-	bf518f-ezbrd	\
-	bf526-ezbrd	\
-	bf527-ezkit	\
-	bf527-ezkit-v2	\
-	bf533-ezkit	\
-	bf533-stamp	\
-	bf537-minotaur	\
-	bf537-pnav	\
-	bf537-srv1	\
-	bf537-stamp	\
-	bf538f-ezkit	\
-	bf548-ezkit	\
-	bf561-acvilon	\
-	bf561-ezkit	\
-	blackstamp	\
-	cm-bf527	\
-	cm-bf533	\
-	cm-bf537e	\
-	cm-bf537u	\
-	cm-bf548	\
-	cm-bf561	\
-	ibf-dsp561	\
-	tcm-bf518	\
-	tcm-bf537	\
-"
+LIST_blackfin="$(boards_by_arch blackfin)"
 
 #########################################################################
 ## SH Systems
 #########################################################################
 
-LIST_sh2="		\
-	rsk7203		\
-"
-LIST_sh3="		\
-	mpr2		\
-	ms7720se	\
-"
+LIST_sh2="$(boards_by_cpu sh2)"
+LIST_sh3="$(boards_by_cpu sh3)"
+LIST_sh4="$(boards_by_cpu sh4)"
 
-LIST_sh4="		\
-	ms7750se	\
-	ms7722se	\
-	MigoR		\
-	r7780mp		\
-	r2dplus		\
-	sh7763rdp	\
-	sh7785lcr	\
-	ap325rxa	\
-	espt		\
-"
-
-LIST_sh="		\
-	${LIST_sh2}	\
-	${LIST_sh3}	\
-	${LIST_sh4}	\
-"
+LIST_sh="$(boards_by_arch sh)"
 
 #########################################################################
 ## SPARC Systems
 #########################################################################
 
-LIST_sparc="gr_xc3s_1500	gr_cpci_ax2000	gr_ep2s60	grsim	grsim_leon2"
-
-#-----------------------------------------------------------------------
-
-#----- for now, just run PPC by default -----
-[ $# = 0 ] && set $LIST_ppc
+LIST_sparc="$(boards_by_arch sparc)"
 
 #-----------------------------------------------------------------------
 
@@ -957,7 +629,7 @@ build_target() {
 	target=$1
 
 	${MAKE} distclean >/dev/null
-	${MAKE} ${target}_config
+	${MAKE} -s ${target}_config
 
 	${MAKE} ${JOBS} all 2>&1 >${LOG_DIR}/$target.MAKELOG \
 				| tee ${LOG_DIR}/$target.ERR
@@ -979,6 +651,22 @@ build_target() {
 	${CROSS_COMPILE}size ${BUILD_DIR}/u-boot \
 				| tee -a ${LOG_DIR}/$target.MAKELOG
 }
+build_targets() {
+	for t in "$@" ; do
+		# If a LIST_xxx var exists, use it.  But avoid variable
+		# expansion in the eval when a board name contains certain
+		# characters that the shell interprets.
+		case ${t} in
+			*[-+=]*) list= ;;
+			*)       list=$(eval echo '${LIST_'$t'}') ;;
+		esac
+		if [ -n "${list}" ] ; then
+			build_targets ${list}
+		else
+			build_target ${t}
+		fi
+	done
+}
 
 #-----------------------------------------------------------------------
 
@@ -995,27 +683,9 @@ print_stats() {
 }
 
 #-----------------------------------------------------------------------
-for arg in $@
-do
-	case "$arg" in
-	arm|SA|ARM7|ARM9|ARM10|ARM11|ARM_CORTEX_A8|at91|ixp|pxa \
-	|avr32 \
-	|blackfin \
-	|coldfire \
-	|microblaze \
-	|mips|mips_el \
-	|nios|nios2 \
-	|ppc|5xx|5xxx|512x|8xx|8220|824x|8260|83xx|85xx|86xx|4xx|7xx|74xx|TSEC \
-	|sh|sh2|sh3|sh4 \
-	|sparc \
-	|x86|I486 \
-	)
-			for target in `eval echo '$LIST_'${arg}`
-			do
-				build_target ${target}
-			done
-			;;
-	*)		build_target ${arg}
-			;;
-	esac
-done
+
+# Build target groups selected by options, plus any command line args
+set -- ${SELECTED} "$@"
+# run PowerPC by default
+[ $# = 0 ] && set -- powerpc
+build_targets "$@"

README

@@ -126,80 +126,104 @@ the string "u_boot" or on "U_BOOT". Example:
 Versioning:
 ===========
 
-U-Boot uses a 3 level version number containing a version, a
-sub-version, and a patchlevel: "U-Boot-2.34.5" means version "2",
-sub-version "34", and patchlevel "4".
+Starting with the release in October 2008, the names of the releases
+were changed from numerical release numbers without deeper meaning
+into a time stamp based numbering. Regular releases are identified by
+names consisting of the calendar year and month of the release date.
+Additional fields (if present) indicate release candidates or bug fix
+releases in "stable" maintenance trees.
 
-The patchlevel is used to indicate certain stages of development
-between released versions, i. e. officially released versions of
-U-Boot will always have a patchlevel of "0".
+Examples:
+	U-Boot v2009.11     - Release November 2009
+	U-Boot v2009.11.1   - Release 1 in version November 2009 stable tree
+	U-Boot v2010.09-rc1 - Release candiate 1 for September 2010 release
 
 
 Directory Hierarchy:
 ====================
 
-- api		Machine/arch independent API for external apps
-- board		Board dependent files
-- common	Misc architecture independent functions
-- cpu		CPU specific files
-  - 74xx_7xx	Files specific to Freescale MPC74xx and 7xx CPUs
-  - arm720t	Files specific to ARM 720 CPUs
-  - arm920t	Files specific to ARM 920 CPUs
-    - at91rm9200 Files specific to Atmel AT91RM9200 CPU
-    - imx	Files specific to Freescale MC9328 i.MX CPUs
-    - s3c24x0	Files specific to Samsung S3C24X0 CPUs
-  - arm925t	Files specific to ARM 925 CPUs
-  - arm926ejs	Files specific to ARM 926 CPUs
-  - arm1136	Files specific to ARM 1136 CPUs
-  - at32ap	Files specific to Atmel AVR32 AP CPUs
-  - blackfin	Files specific to Analog Devices Blackfin CPUs
-  - i386	Files specific to i386 CPUs
-  - ixp		Files specific to Intel XScale IXP CPUs
-  - leon2	Files specific to Gaisler LEON2 SPARC CPU
-  - leon3	Files specific to Gaisler LEON3 SPARC CPU
-  - mcf52x2	Files specific to Freescale ColdFire MCF52x2 CPUs
-  - mcf5227x	Files specific to Freescale ColdFire MCF5227x CPUs
-  - mcf532x	Files specific to Freescale ColdFire MCF5329 CPUs
-  - mcf5445x	Files specific to Freescale ColdFire MCF5445x CPUs
-  - mcf547x_8x	Files specific to Freescale ColdFire MCF547x_8x CPUs
-  - mips	Files specific to MIPS CPUs
-  - mpc5xx	Files specific to Freescale MPC5xx  CPUs
-  - mpc5xxx	Files specific to Freescale MPC5xxx CPUs
-  - mpc8xx	Files specific to Freescale MPC8xx  CPUs
-  - mpc8220	Files specific to Freescale MPC8220 CPUs
-  - mpc824x	Files specific to Freescale MPC824x CPUs
-  - mpc8260	Files specific to Freescale MPC8260 CPUs
-  - mpc85xx	Files specific to Freescale MPC85xx CPUs
-  - nios	Files specific to Altera NIOS CPUs
-  - nios2	Files specific to Altera Nios-II CPUs
-  - ppc4xx	Files specific to AMCC PowerPC 4xx CPUs
-  - pxa		Files specific to Intel XScale PXA CPUs
-  - s3c44b0	Files specific to Samsung S3C44B0 CPUs
-  - sa1100	Files specific to Intel StrongARM SA1100 CPUs
-- disk		Code for disk drive partition handling
-- doc		Documentation (don't expect too much)
-- drivers	Commonly used device drivers
-- examples	Example code for standalone applications, etc.
-- fs		Filesystem code (cramfs, ext2, jffs2, etc.)
-- include	Header Files
-- lib_arm	Files generic to ARM	 architecture
-- lib_avr32	Files generic to AVR32	 architecture
-- lib_blackfin	Files generic to Blackfin architecture
-- lib_generic	Files generic to all	 architectures
-- lib_i386	Files generic to i386	 architecture
-- lib_m68k	Files generic to m68k	 architecture
-- lib_microblaze Files generic to microblaze architecture
-- lib_mips	Files generic to MIPS	 architecture
-- lib_nios	Files generic to NIOS	 architecture
-- lib_nios2	Files generic to NIOS2	 architecture
-- lib_ppc	Files generic to PowerPC architecture
-- lib_sh	Files generic to SH	 architecture
-- lib_sparc	Files generic to SPARC	 architecture
-- libfdt	Library files to support flattened device trees
-- net		Networking code
-- post		Power On Self Test
-- rtc		Real Time Clock drivers
-- tools		Tools to build S-Record or U-Boot images, etc.
+/arch			Architecture specific files
+  /arm			Files generic to ARM architecture
+    /cpu		CPU specific files
+      /arm720t		Files specific to ARM 720 CPUs
+      /arm920t		Files specific to ARM 920 CPUs
+	/at91rm9200	Files specific to Atmel AT91RM9200 CPU
+	/imx		Files specific to Freescale MC9328 i.MX CPUs
+	/s3c24x0	Files specific to Samsung S3C24X0 CPUs
+      /arm925t		Files specific to ARM 925 CPUs
+      /arm926ejs	Files specific to ARM 926 CPUs
+      /arm1136		Files specific to ARM 1136 CPUs
+      /ixp		Files specific to Intel XScale IXP CPUs
+      /pxa		Files specific to Intel XScale PXA CPUs
+      /s3c44b0		Files specific to Samsung S3C44B0 CPUs
+      /sa1100		Files specific to Intel StrongARM SA1100 CPUs
+    /lib		Architecture specific library files
+  /avr32		Files generic to AVR32 architecture
+    /cpu		CPU specific files
+    /lib		Architecture specific library files
+  /blackfin		Files generic to Analog Devices Blackfin architecture
+    /cpu		CPU specific files
+    /lib		Architecture specific library files
+  /i386			Files generic to i386 architecture
+    /cpu		CPU specific files
+    /lib		Architecture specific library files
+  /m68k			Files generic to m68k architecture
+    /cpu		CPU specific files
+      /mcf52x2		Files specific to Freescale ColdFire MCF52x2 CPUs
+      /mcf5227x		Files specific to Freescale ColdFire MCF5227x CPUs
+      /mcf532x		Files specific to Freescale ColdFire MCF5329 CPUs
+      /mcf5445x		Files specific to Freescale ColdFire MCF5445x CPUs
+      /mcf547x_8x	Files specific to Freescale ColdFire MCF547x_8x CPUs
+    /lib		Architecture specific library files
+  /microblaze		Files generic to microblaze architecture
+    /cpu		CPU specific files
+    /lib		Architecture specific library files
+  /mips			Files generic to MIPS architecture
+    /cpu		CPU specific files
+    /lib		Architecture specific library files
+  /nios2		Files generic to Altera NIOS2 architecture
+    /cpu		CPU specific files
+    /lib		Architecture specific library files
+  /powerpc		Files generic to PowerPC architecture
+    /cpu		CPU specific files
+      /74xx_7xx		Files specific to Freescale MPC74xx and 7xx CPUs
+      /mpc5xx		Files specific to Freescale MPC5xx CPUs
+      /mpc5xxx		Files specific to Freescale MPC5xxx CPUs
+      /mpc8xx		Files specific to Freescale MPC8xx CPUs
+      /mpc8220		Files specific to Freescale MPC8220 CPUs
+      /mpc824x		Files specific to Freescale MPC824x CPUs
+      /mpc8260		Files specific to Freescale MPC8260 CPUs
+      /mpc85xx		Files specific to Freescale MPC85xx CPUs
+      /ppc4xx		Files specific to AMCC PowerPC 4xx CPUs
+    /lib		Architecture specific library files
+  /sh			Files generic to SH architecture
+    /cpu		CPU specific files
+      /sh2		Files specific to sh2 CPUs
+      /sh3		Files specific to sh3 CPUs
+      /sh4		Files specific to sh4 CPUs
+    /lib		Architecture specific library files
+  /sparc		Files generic to SPARC architecture
+    /cpu		CPU specific files
+      /leon2		Files specific to Gaisler LEON2 SPARC CPU
+      /leon3		Files specific to Gaisler LEON3 SPARC CPU
+    /lib		Architecture specific library files
+/api			Machine/arch independent API for external apps
+/board			Board dependent files
+/common			Misc architecture independent functions
+/disk			Code for disk drive partition handling
+/doc			Documentation (don't expect too much)
+/drivers		Commonly used device drivers
+/examples		Example code for standalone applications, etc.
+/fs			Filesystem code (cramfs, ext2, jffs2, etc.)
+/include		Header Files
+/lib			Files generic to all architectures
+  /libfdt		Library files to support flattened device trees
+  /lzma			Library files to support LZMA decompression
+  /lzo			Library files to support LZO decompression
+/net			Networking code
+/post			Power On Self Test
+/rtc			Real Time Clock drivers
+/tools			Tools to build S-Record or U-Boot images, etc.
 
 Software Configuration:
 =======================
@@ -512,25 +536,6 @@ The following options need to be configured:
 		must be defined, to setup the maximum idle timeout for
 		the SMC.
 
-- Interrupt driven serial port input:
-		CONFIG_SERIAL_SOFTWARE_FIFO
-
-		PPC405GP only.
-		Use an interrupt handler for receiving data on the
-		serial port. It also enables using hardware handshake
-		(RTS/CTS) and UART's built-in FIFO. Set the number of
-		bytes the interrupt driven input buffer should have.
-
-		Leave undefined to disable this feature, including
-		disable the buffer and hardware handshake.
-
-- Console UART Number:
-		CONFIG_UART1_CONSOLE
-
-		AMCC PPC4xx only.
-		If defined internal UART1 (and not UART0) is used
-		as default U-Boot console.
-
 - Boot Delay:	CONFIG_BOOTDELAY - in seconds
 		Delay before automatically booting the default image;
 		set to -1 to disable autoboot.
@@ -1133,6 +1138,12 @@ The following options need to be configured:
 		images, gzipped BMP images can be displayed via the
 		splashscreen support or the bmp command.
 
+- Run length encoded BMP image (RLE8) support: CONFIG_VIDEO_BMP_RLE8
+
+		If this option is set, 8-bit RLE compressed BMP images
+		can be displayed via the splashscreen support or the
+		bmp command.
+
 - Compression support:
 		CONFIG_BZIP2
 
@@ -1387,10 +1398,11 @@ The following options need to be configured:
 		to run and CONFIG_SYS_I2C_SLAVE to be the address of this node (ie
 		the CPU's i2c node address).
 
-		Now, the u-boot i2c code for the mpc8xx (cpu/mpc8xx/i2c.c)
-		sets the CPU up as a master node and so its address should
-		therefore be cleared to 0 (See, eg, MPC823e User's Manual
-		p.16-473). So, set CONFIG_SYS_I2C_SLAVE to 0.
+		Now, the u-boot i2c code for the mpc8xx
+		(arch/powerpc/cpu/mpc8xx/i2c.c) sets the CPU up as a master node
+		and so its address should therefore be cleared to 0 (See,
+		eg, MPC823e User's Manual p.16-473). So, set
+		CONFIG_SYS_I2C_SLAVE to 0.
 
 		CONFIG_SYS_I2C_INIT_MPC5XXX
 
@@ -1468,6 +1480,16 @@ The following options need to be configured:
 
 		#define I2C_DELAY  udelay(2)
 
+		CONFIG_SOFT_I2C_GPIO_SCL / CONFIG_SOFT_I2C_GPIO_SDA
+
+		If your arch supports the generic GPIO framework (asm/gpio.h),
+		then you may alternatively define the two GPIOs that are to be
+		used as SCL / SDA.  Any of the previous I2C_xxx macros will
+		have GPIO-based defaults assigned to them as appropriate.
+
+		You should define these to the GPIO value as given directly to
+		the generic GPIO functions.
+
 		CONFIG_SYS_I2C_INIT_BOARD
 
 		When a board is reset during an i2c bus transfer
@@ -1479,6 +1501,17 @@ The following options need to be configured:
 		custom i2c_init_board() routine in boards/xxx/board.c
 		is run early in the boot sequence.
 
+		CONFIG_SYS_I2C_BOARD_LATE_INIT
+
+		An alternative to CONFIG_SYS_I2C_INIT_BOARD. If this option is
+		defined a custom i2c_board_late_init() routine in
+		boards/xxx/board.c is run AFTER the operations in i2c_init()
+		is completed. This callpoint can be used to unreset i2c bus
+		using CPU i2c controller register accesses for CPUs whose i2c
+		controller provide such a method. It is called at the end of
+		i2c_init() to allow i2c_init operations to setup the i2c bus
+		controller on the CPU (e.g. setting bus speed & slave address).
+
 		CONFIG_I2CFAST (PPC405GP|PPC405EP only)
 
 		This option enables configuration of bi_iic_fast[] flags
@@ -1748,7 +1781,7 @@ The following options need to be configured:
 
 			ETX094, IVMS8, IVML24, SPD8xx, TQM8xxL,
 			HERMES, IP860, RPXlite, LWMON, LANTEC,
-			PCU_E, FLAGADM, TQM8260
+			FLAGADM, TQM8260
 
 - Error Recovery:
 		CONFIG_PANIC_HANG
@@ -1934,9 +1967,9 @@ Legacy uImage format:
    13	common/image.c		Start multifile image verification
    14	common/image.c		No initial ramdisk, no multifile, continue.
 
-   15	lib_<arch>/bootm.c	All preparation done, transferring control to OS
+   15	arch/<arch>/lib/bootm.c	All preparation done, transferring control to OS
 
-  -30	lib_ppc/board.c		Fatal error, hang the system
+  -30	arch/powerpc/lib/board.c	Fatal error, hang the system
   -31	post/post.c		POST test failed, detected by post_output_backlog()
   -32	post/post.c		POST test failed, detected by post_run_single()
 
@@ -2215,7 +2248,7 @@ Configuration Settings:
 - CONFIG_SYS_MONITOR_BASE:
 		Physical start address of boot monitor code (set by
 		make config files to be same as the text base address
-		(TEXT_BASE) used when linking) - same as
+		(CONFIG_SYS_TEXT_BASE) used when linking) - same as
 		CONFIG_SYS_FLASH_BASE when booting from flash.
 
 - CONFIG_SYS_MONITOR_LEN:
@@ -2242,6 +2275,19 @@ Configuration Settings:
 		all data for the Linux kernel must be between "bootm_low"
 		and "bootm_low" + CONFIG_SYS_BOOTMAPSZ.
 
+- CONFIG_SYS_BOOT_RAMDISK_HIGH:
+		Enable initrd_high functionality.  If defined then the
+		initrd_high feature is enabled and the bootm ramdisk subcommand
+		is enabled.
+
+- CONFIG_SYS_BOOT_GET_CMDLINE:
+		Enables allocating and saving kernel cmdline in space between
+		"bootm_low" and "bootm_low" + BOOTMAPSZ.
+
+- CONFIG_SYS_BOOT_GET_KBD:
+		Enables allocating and saving a kernel copy of the bd_info in
+		space between "bootm_low" and "bootm_low" + BOOTMAPSZ.
+
 - CONFIG_SYS_MAX_FLASH_BANKS:
 		Max number of Flash memory banks
 
@@ -2316,6 +2362,14 @@ Configuration Settings:
 		on high Ethernet traffic.
 		Defaults to 4 if not defined.
 
+- CONFIG_ENV_MAX_ENTRIES
+
+	Maximum number of entries in the hash table that is used
+	internally to store the environment settings. The default
+	setting is supposed to be generous and should work in most
+	cases. This setting can be used to tune behaviour; see
+	lib/hashtable.c for details.
+
 The following definitions that deal with the placement and management
 of environment data (variable area); in general, we support the
 following configurations:
@@ -2466,7 +2520,7 @@ to save the current settings.
 	  I2C muxes, you can define here, how to reach this
 	  EEPROM. For example:
 
-	  #define CONFIG_I2C_ENV_EEPROM_BUS       "pca9547:70:d\0"
+	  #define CONFIG_I2C_ENV_EEPROM_BUS	  "pca9547:70:d\0"
 
 	  EEPROM which holds the environment, is reached over
 	  a pca9547 i2c mux with address 0x70, channel 3.
@@ -2493,18 +2547,32 @@ to save the current settings.
 	- CONFIG_ENV_SIZE:
 
 	  These two #defines specify the offset and size of the environment
-	  area within the first NAND device.
+	  area within the first NAND device.  CONFIG_ENV_OFFSET must be
+	  aligned to an erase block boundary.
 
-	- CONFIG_ENV_OFFSET_REDUND
+	- CONFIG_ENV_OFFSET_REDUND (optional):
 
 	  This setting describes a second storage area of CONFIG_ENV_SIZE
-	  size used to hold a redundant copy of the environment data,
-	  so that there is a valid backup copy in case there is a
-	  power failure during a "saveenv" operation.
+	  size used to hold a redundant copy of the environment data, so
+	  that there is a valid backup copy in case there is a power failure
+	  during a "saveenv" operation.  CONFIG_ENV_OFFSET_RENDUND must be
+	  aligned to an erase block boundary.
 
-	Note: CONFIG_ENV_OFFSET and CONFIG_ENV_OFFSET_REDUND must be aligned
-	to a block boundary, and CONFIG_ENV_SIZE must be a multiple of
-	the NAND devices block size.
+	- CONFIG_ENV_RANGE (optional):
+
+	  Specifies the length of the region in which the environment
+	  can be written.  This should be a multiple of the NAND device's
+	  block size.  Specifying a range with more erase blocks than
+	  are needed to hold CONFIG_ENV_SIZE allows bad blocks within
+	  the range to be avoided.
+
+	- CONFIG_ENV_OFFSET_OOB (optional):
+
+	  Enables support for dynamically retrieving the offset of the
+	  environment from block zero's out-of-band data.  The
+	  "nand env.oob" command can be used to record this offset.
+	  Currently, CONFIG_ENV_OFFSET_REDUND is not supported when
+	  using CONFIG_ENV_OFFSET_OOB.
 
 - CONFIG_NAND_ENV_DST
 
@@ -2524,7 +2592,7 @@ to save the current settings.
 
 Please note that the environment is read-only until the monitor
 has been relocated to RAM and a RAM copy of the environment has been
-created; also, when using EEPROM you will have to use getenv_r()
+created; also, when using EEPROM you will have to use getenv_f()
 until then to read environment variables.
 
 The environment is protected by a CRC32 checksum. Before the monitor
@@ -2618,7 +2686,7 @@ Low Level (hardware related) configuration options:
 		area defined by CONFIG_SYS_INIT_RAM_ADDR. Usually
 		CONFIG_SYS_GBL_DATA_OFFSET is chosen such that the initial
 		data is located at the end of the available space
-		(sometimes written as (CONFIG_SYS_INIT_RAM_END -
+		(sometimes written as (CONFIG_SYS_INIT_RAM_SIZE -
 		CONFIG_SYS_INIT_DATA_SIZE), and the initial stack is just
 		below that area (growing from (CONFIG_SYS_INIT_RAM_ADDR +
 		CONFIG_SYS_GBL_DATA_OFFSET) downward.
@@ -2697,7 +2765,7 @@ Low Level (hardware related) configuration options:
   CONFIG_SYS_PCI_MSTR_MEMIO_SIZE, CONFIG_SYS_POCMR1_MASK_ATTRIB, CONFIG_SYS_PCI_MSTR_IO_LOCAL,
   CONFIG_SYS_PCI_MSTR_IO_BUS, CONFIG_SYS_CPU_PCI_IO_START, CONFIG_SYS_PCI_MSTR_IO_SIZE,
   CONFIG_SYS_POCMR2_MASK_ATTRIB: (MPC826x only)
-		Overrides the default PCI memory map in cpu/mpc8260/pci.c if set.
+		Overrides the default PCI memory map in arch/powerpc/cpu/mpc8260/pci.c if set.
 
 - CONFIG_PCI_DISABLE_PCIE:
 		Disable PCI-Express on systems where it is supported but not
@@ -2768,19 +2836,17 @@ Low Level (hardware related) configuration options:
 		globally (CONFIG_CMD_MEM).
 
 - CONFIG_SKIP_LOWLEVEL_INIT
-- CONFIG_SKIP_RELOCATE_UBOOT
+		[ARM only] If this variable is defined, then certain
+		low level initializations (like setting up the memory
+		controller) are omitted and/or U-Boot does not
+		relocate itself into RAM.
 
-		[ARM only] If these variables are defined, then
-		certain low level initializations (like setting up
-		the memory controller) are omitted and/or U-Boot does
-		not relocate itself into RAM.
-		Normally these variables MUST NOT be defined. The
-		only exception is when U-Boot is loaded (to RAM) by
-		some other boot loader or by a debugger which
-		performs these initializations itself.
+		Normally this variable MUST NOT be defined. The only
+		exception is when U-Boot is loaded (to RAM) by some
+		other boot loader or by a debugger which performs
+		these initializations itself.
 
 - CONFIG_PRELOADER
-
 		Modifies the behaviour of start.S when compiling a loader
 		that is executed before the actual U-Boot. E.g. when
 		compiling a NAND SPL.
@@ -3110,10 +3176,10 @@ List of environment variables (most likely not complete):
 		  interface is currently active. For example you
 		  can do the following
 
-		  => setenv ethact FEC ETHERNET
-		  => ping 192.168.0.1 # traffic sent on FEC ETHERNET
-		  => setenv ethact SCC ETHERNET
-		  => ping 10.0.0.1 # traffic sent on SCC ETHERNET
+		  => setenv ethact FEC
+		  => ping 192.168.0.1 # traffic sent on FEC
+		  => setenv ethact SCC
+		  => ping 10.0.0.1 # traffic sent on SCC
 
   ethrotate	- When set to "no" U-Boot does not go through all
 		  available network interfaces.
@@ -3262,6 +3328,11 @@ o If both the SROM and the environment contain a MAC address, and the
 o If neither SROM nor the environment contain a MAC address, an error
   is raised.
 
+If Ethernet drivers implement the 'write_hwaddr' function, valid MAC addresses
+will be programmed into hardware as part of the initialization process.  This
+may be skipped by setting the appropriate 'ethmacskip' environment variable.
+The naming convention is as follows:
+"ethmacskip" (=>eth0), "eth1macskip" (=>eth1) etc.
 
 Image Formats:
 ==============
@@ -3291,8 +3362,8 @@ details; basically, the header defines the following image properties:
   Currently supported: Linux, NetBSD, VxWorks, QNX, RTEMS, LynxOS,
   INTEGRITY).
 * Target CPU Architecture (Provisions for Alpha, ARM, AVR32, Intel x86,
-  IA64, MIPS, NIOS, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit;
-  Currently supported: ARM, AVR32, Intel x86, MIPS, NIOS, PowerPC).
+  IA64, MIPS, Nios II, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit;
+  Currently supported: ARM, AVR32, Intel x86, MIPS, Nios II, PowerPC).
 * Compression Type (uncompressed, gzip, bzip2)
 * Load Address
 * Entry Point
@@ -3343,7 +3414,7 @@ configure the Linux device drivers for use with your target hardware
 (no, we don't intend to provide a full virtual machine interface to
 Linux :-).
 
-But now you can ignore ALL boot loader code (in arch/ppc/mbxboot).
+But now you can ignore ALL boot loader code (in arch/powerpc/mbxboot).
 
 Just make sure your machine specific header file (for instance
 include/asm-ppc/tqm8xx.h) includes the same definition of the Board
@@ -3441,7 +3512,7 @@ So a typical call to build a U-Boot image would read:
 
 	-> tools/mkimage -n '2.4.4 kernel for TQM850L' \
 	> -A ppc -O linux -T kernel -C gzip -a 0 -e 0 \
-	> -d /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/ppc/coffboot/vmlinux.gz \
+	> -d /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/powerpc/coffboot/vmlinux.gz \
 	> examples/uImage.TQM850L
 	Image Name:   2.4.4 kernel for TQM850L
 	Created:      Wed Jul 19 02:34:59 2000
@@ -3465,10 +3536,10 @@ speed for memory and install an UNCOMPRESSED image instead: this
 needs more space in Flash, but boots much faster since it does not
 need to be uncompressed:
 
-	-> gunzip /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/ppc/coffboot/vmlinux.gz
+	-> gunzip /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/powerpc/coffboot/vmlinux.gz
 	-> tools/mkimage -n '2.4.4 kernel for TQM850L' \
 	> -A ppc -O linux -T kernel -C none -a 0 -e 0 \
-	> -d /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/ppc/coffboot/vmlinux \
+	> -d /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/powerpc/coffboot/vmlinux \
 	> examples/uImage.TQM850L-uncompressed
 	Image Name:   2.4.4 kernel for TQM850L
 	Created:      Wed Jul 19 02:34:59 2000
@@ -3977,6 +4048,14 @@ On ARM, the following registers are used:
 
     ==> U-Boot will use R8 to hold a pointer to the global data
 
+On Nios II, the ABI is documented here:
+	http://www.altera.com/literature/hb/nios2/n2cpu_nii51016.pdf
+
+    ==> U-Boot will use gp to hold a pointer to the global data
+
+    Note: on Nios II, we give "-G0" option to gcc and don't use gp
+    to access small data sections, so gp is free.
+
 NOTE: DECLARE_GLOBAL_DATA_PTR must be used with file-global scope,
 or current versions of GCC may "optimize" the code too much.
 

api/Makefile

@@ -22,7 +22,7 @@
 
 include $(TOPDIR)/config.mk
 
-LIB	= $(obj)libapi.a
+LIB	= $(obj)libapi.o
 
 COBJS-$(CONFIG_API) += api.o api_net.o api_storage.o api_platform-$(ARCH).o
 
@@ -31,7 +31,7 @@ SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
 
 $(LIB):	$(obj).depend $(OBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
 
 # defines $(obj).depend target
 include $(SRCTREE)/rules.mk

api/api.c

@@ -37,7 +37,7 @@
 #undef DEBUG
 
 /* U-Boot routines needed */
-extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
 
 /*****************************************************************************
  *

arch/.gitignore

@@ -0,0 +1,2 @@
+/*/include/asm/arch
+/*/include/asm/proc

arch/arm/config.mk

@@ -0,0 +1,71 @@
+#
+# (C) Copyright 2000-2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+CROSS_COMPILE ?= arm-linux-
+
+ifeq ($(BOARD),omap2420h4)
+STANDALONE_LOAD_ADDR = 0x80300000
+else
+ifeq ($(SOC),omap3)
+STANDALONE_LOAD_ADDR = 0x80300000
+else
+STANDALONE_LOAD_ADDR = 0xc100000
+endif
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_ARM -D__ARM__
+
+# Explicitly specifiy 32-bit ARM ISA since toolchain default can be -mthumb:
+PLATFORM_CPPFLAGS += $(call cc-option,-marm,)
+
+# Try if EABI is supported, else fall back to old API,
+# i. e. for example:
+# - with ELDK 4.2 (EABI supported), use:
+#	-mabi=aapcs-linux -mno-thumb-interwork
+# - with ELDK 4.1 (gcc 4.x, no EABI), use:
+#	-mabi=apcs-gnu -mno-thumb-interwork
+# - with ELDK 3.1 (gcc 3.x), use:
+#	-mapcs-32 -mno-thumb-interwork
+PLATFORM_CPPFLAGS += $(call cc-option,\
+				-mabi=aapcs-linux -mno-thumb-interwork,\
+				$(call cc-option,\
+					-mapcs-32,\
+					$(call cc-option,\
+						-mabi=apcs-gnu,\
+					)\
+				) $(call cc-option,-mno-thumb-interwork,)\
+			)
+
+# For EABI, make sure to provide raise()
+ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS)))
+# This file is parsed several times; make sure to add only once.
+ifeq (,$(findstring arch/arm/lib/eabi_compat.o,$(PLATFORM_LIBS)))
+PLATFORM_LIBS += $(OBJTREE)/arch/arm/lib/eabi_compat.o
+endif
+endif
+LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds
+
+# needed for relocation
+ifndef CONFIG_NAND_SPL
+PLATFORM_LDFLAGS += -pie
+endif

arch/arm/cpu/arm1136/Makefile

@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(CPU).o
+
+START	= start.o
+COBJS	= cpu.o
+
+SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+START	:= $(addprefix $(obj),$(START))
+
+all:	$(obj).depend $(START) $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

arch/arm/cpu/arm1136/cpu.c

@@ -0,0 +1,77 @@
+/*
+ * (C) Copyright 2004 Texas Insturments
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * CPU specific code
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/system.h>
+
+static void cache_flush(void);
+
+int cleanup_before_linux (void)
+{
+	/*
+	 * this function is called just before we call linux
+	 * it prepares the processor for linux
+	 *
+	 * we turn off caches etc ...
+	 */
+
+	disable_interrupts ();
+
+#ifdef CONFIG_LCD
+	{
+		extern void lcd_disable(void);
+		extern void lcd_panel_disable(void);
+
+		lcd_disable(); /* proper disable of lcd & panel */
+		lcd_panel_disable();
+	}
+#endif
+
+	/* turn off I/D-cache */
+	icache_disable();
+	dcache_disable();
+	/* flush I/D-cache */
+	cache_flush();
+
+	return 0;
+}
+
+static void cache_flush(void)
+{
+	unsigned long i = 0;
+
+	asm ("mcr p15, 0, %0, c7, c10, 0": :"r" (i)); /* clean entire data cache */
+	asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));  /* invalidate both caches and flush btb */
+	asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); /* mem barrier to sync things */
+}

arch/arm/cpu/arm1136/mx31/Makefile

@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).o
+
+COBJS	+= generic.o
+COBJS	+= timer.o
+COBJS	+= devices.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

arch/arm/cpu/arm1136/mx31/generic.c

@@ -0,0 +1,116 @@
+/*
+ * (C) Copyright 2007
+ * Sascha Hauer, Pengutronix
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/mx31-regs.h>
+#include <asm/io.h>
+
+static u32 mx31_decode_pll(u32 reg, u32 infreq)
+{
+	u32 mfi = (reg >> 10) & 0xf;
+	u32 mfn = reg & 0x3ff;
+	u32 mfd = (reg >> 16) & 0x3ff;
+	u32 pd =  (reg >> 26) & 0xf;
+
+	mfi = mfi <= 5 ? 5 : mfi;
+	mfd += 1;
+	pd += 1;
+
+	return ((2 * (infreq >> 10) * (mfi * mfd + mfn)) /
+		(mfd * pd)) << 10;
+}
+
+static u32 mx31_get_mpl_dpdgck_clk(void)
+{
+	u32 infreq;
+
+	if ((__REG(CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM)
+		infreq = CONFIG_MX31_CLK32 * 1024;
+	else
+		infreq = CONFIG_MX31_HCLK_FREQ;
+
+	return mx31_decode_pll(__REG(CCM_MPCTL), infreq);
+}
+
+static u32 mx31_get_mcu_main_clk(void)
+{
+	/* For now we assume mpl_dpdgck_clk == mcu_main_clk
+	 * which should be correct for most boards
+	 */
+	return mx31_get_mpl_dpdgck_clk();
+}
+
+u32 mx31_get_ipg_clk(void)
+{
+	u32 freq = mx31_get_mcu_main_clk();
+	u32 pdr0 = __REG(CCM_PDR0);
+
+	freq /= ((pdr0 >> 3) & 0x7) + 1;
+	freq /= ((pdr0 >> 6) & 0x3) + 1;
+
+	return freq;
+}
+
+void mx31_dump_clocks(void)
+{
+	u32 cpufreq = mx31_get_mcu_main_clk();
+	printf("mx31 cpu clock: %dMHz\n",cpufreq / 1000000);
+	printf("ipg clock     : %dHz\n", mx31_get_ipg_clk());
+}
+
+void mx31_gpio_mux(unsigned long mode)
+{
+	unsigned long reg, shift, tmp;
+
+	reg = IOMUXC_BASE + (mode & 0x1fc);
+	shift = (~mode & 0x3) * 8;
+
+	tmp = __REG(reg);
+	tmp &= ~(0xff << shift);
+	tmp |= ((mode >> IOMUX_MODE_POS) & 0xff) << shift;
+	__REG(reg) = tmp;
+}
+
+void mx31_set_pad(enum iomux_pins pin, u32 config)
+{
+	u32 field, l, reg;
+
+	pin &= IOMUX_PADNUM_MASK;
+	reg = (IOMUXC_BASE + 0x154) + (pin + 2) / 3 * 4;
+	field = (pin + 2) % 3;
+
+	l = __REG(reg);
+	l &= ~(0x1ff << (field * 10));
+	l |= config << (field * 10);
+	__REG(reg) = l;
+
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo (void)
+{
+	printf("CPU:   Freescale i.MX31 at %d MHz\n",
+		mx31_get_mcu_main_clk() / 1000000);
+	return 0;
+}
+#endif

arch/arm/cpu/arm1136/mx31/timer.c

@@ -0,0 +1,170 @@
+/*
+ * (C) Copyright 2007
+ * Sascha Hauer, Pengutronix
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/mx31-regs.h>
+#include <div64.h>
+
+#define TIMER_BASE 0x53f90000 /* General purpose timer 1 */
+
+/* General purpose timers registers */
+#define GPTCR	__REG(TIMER_BASE)		/* Control register	*/
+#define GPTPR	__REG(TIMER_BASE + 0x4)		/* Prescaler register	*/
+#define GPTSR	__REG(TIMER_BASE + 0x8)		/* Status register	*/
+#define GPTCNT	__REG(TIMER_BASE + 0x24)	/* Counter register	*/
+
+/* General purpose timers bitfields */
+#define GPTCR_SWR		(1 << 15)	/* Software reset	*/
+#define GPTCR_FRR		(1 << 9)	/* Freerun / restart	*/
+#define GPTCR_CLKSOURCE_32	(4 << 6)	/* Clock source		*/
+#define GPTCR_TEN		1		/* Timer enable		*/
+
+static ulong timestamp;
+static ulong lastinc;
+
+/* "time" is measured in 1 / CONFIG_SYS_HZ seconds, "tick" is internal timer period */
+#ifdef CONFIG_MX31_TIMER_HIGH_PRECISION
+/* ~0.4% error - measured with stop-watch on 100s boot-delay */
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+	tick *= CONFIG_SYS_HZ;
+	do_div(tick, CONFIG_MX31_CLK32);
+	return tick;
+}
+
+static inline unsigned long long time_to_tick(unsigned long long time)
+{
+	time *= CONFIG_MX31_CLK32;
+	do_div(time, CONFIG_SYS_HZ);
+	return time;
+}
+
+static inline unsigned long long us_to_tick(unsigned long long us)
+{
+	us = us * CONFIG_MX31_CLK32 + 999999;
+	do_div(us, 1000000);
+	return us;
+}
+#else
+/* ~2% error */
+#define TICK_PER_TIME	((CONFIG_MX31_CLK32 + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ)
+#define US_PER_TICK	(1000000 / CONFIG_MX31_CLK32)
+
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+	do_div(tick, TICK_PER_TIME);
+	return tick;
+}
+
+static inline unsigned long long time_to_tick(unsigned long long time)
+{
+	return time * TICK_PER_TIME;
+}
+
+static inline unsigned long long us_to_tick(unsigned long long us)
+{
+	us += US_PER_TICK - 1;
+	do_div(us, US_PER_TICK);
+	return us;
+}
+#endif
+
+/* The 32768Hz 32-bit timer overruns in 131072 seconds */
+int timer_init (void)
+{
+	int i;
+
+	/* setup GP Timer 1 */
+	GPTCR = GPTCR_SWR;
+	for (i = 0; i < 100; i++)
+		GPTCR = 0; /* We have no udelay by now */
+	GPTPR = 0; /* 32Khz */
+	/* Freerun Mode, PERCLK1 input */
+	GPTCR |= GPTCR_CLKSOURCE_32 | GPTCR_TEN;
+
+	return 0;
+}
+
+void reset_timer_masked (void)
+{
+	/* reset time */
+	lastinc = GPTCNT; /* capture current incrementer value time */
+	timestamp = 0; /* start "advancing" time stamp from 0 */
+}
+
+void reset_timer(void)
+{
+	reset_timer_masked();
+}
+
+unsigned long long get_ticks (void)
+{
+	ulong now = GPTCNT; /* current tick value */
+
+	if (now >= lastinc)	/* normal mode (non roll) */
+		/* move stamp forward with absolut diff ticks */
+		timestamp += (now - lastinc);
+	else			/* we have rollover of incrementer */
+		timestamp += (0xFFFFFFFF - lastinc) + now;
+	lastinc = now;
+	return timestamp;
+}
+
+ulong get_timer_masked (void)
+{
+	/*
+	 * get_ticks() returns a long long (64 bit), it wraps in
+	 * 2^64 / CONFIG_MX31_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
+	 * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
+	 * 5 * 10^6 days - long enough.
+	 */
+	return tick_to_time(get_ticks());
+}
+
+ulong get_timer (ulong base)
+{
+	return get_timer_masked () - base;
+}
+
+void set_timer (ulong t)
+{
+	timestamp = time_to_tick(t);
+}
+
+/* delay x useconds AND preserve advance timestamp value */
+void __udelay (unsigned long usec)
+{
+	unsigned long long tmp;
+	ulong tmo;
+
+	tmo = us_to_tick(usec);
+	tmp = get_ticks() + tmo;	/* get current timestamp */
+
+	while (get_ticks() < tmp)	/* loop till event */
+		 /*NOP*/;
+}
+
+void reset_cpu (ulong addr)
+{
+	__REG16(WDOG_BASE) = 4;
+}

arch/arm/cpu/arm1136/omap24xx/Makefile

@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).o
+
+SOBJS	= reset.o
+
+COBJS	= timer.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

arch/arm/cpu/arm1136/omap24xx/timer.c

@@ -0,0 +1,158 @@
+/*
+ * (C) Copyright 2004
+ * Texas Instruments
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/bits.h>
+#include <asm/arch/omap2420.h>
+
+#define TIMER_LOAD_VAL 0
+
+/* macro to read the 32 bit timer */
+#define READ_TIMER (*((volatile ulong *)(CONFIG_SYS_TIMERBASE+TCRR)))
+
+static ulong timestamp;
+static ulong lastinc;
+
+int timer_init (void)
+{
+	int32_t val;
+
+	/* Start the counter ticking up */
+	*((int32_t *) (CONFIG_SYS_TIMERBASE + TLDR)) = TIMER_LOAD_VAL;	/* reload value on overflow*/
+	val = (CONFIG_SYS_PTV << 2) | BIT5 | BIT1 | BIT0;		/* mask to enable timer*/
+	*((int32_t *) (CONFIG_SYS_TIMERBASE + TCLR)) = val;	/* start timer */
+
+	reset_timer_masked(); /* init the timestamp and lastinc value */
+
+	return(0);
+}
+/*
+ * timer without interrupts
+ */
+void reset_timer (void)
+{
+	reset_timer_masked ();
+}
+
+ulong get_timer (ulong base)
+{
+	return get_timer_masked () - base;
+}
+
+void set_timer (ulong t)
+{
+	timestamp = t;
+}
+
+/* delay x useconds AND preserve advance timestamp value */
+void __udelay (unsigned long usec)
+{
+	ulong tmo, tmp;
+
+	if (usec >= 1000) {		/* if "big" number, spread normalization to seconds */
+		tmo = usec / 1000;	/* start to normalize for usec to ticks per sec */
+		tmo *= CONFIG_SYS_HZ;	/* find number of "ticks" to wait to achieve target */
+		tmo /= 1000;		/* finish normalize. */
+	} else {			/* else small number, don't kill it prior to HZ multiply */
+		tmo = usec * CONFIG_SYS_HZ;
+		tmo /= (1000*1000);
+	}
+
+	tmp = get_timer (0);		/* get current timestamp */
+	if ( (tmo + tmp + 1) < tmp )	/* if setting this forward will roll time stamp */
+		reset_timer_masked ();	/* reset "advancing" timestamp to 0, set lastinc value */
+	else
+		tmo	+= tmp;		/* else, set advancing stamp wake up time */
+	while (get_timer_masked () < tmo)/* loop till event */
+		/*NOP*/;
+}
+
+void reset_timer_masked (void)
+{
+	/* reset time */
+	lastinc = READ_TIMER;		/* capture current incrementer value time */
+	timestamp = 0;			/* start "advancing" time stamp from 0 */
+}
+
+ulong get_timer_masked (void)
+{
+	ulong now = READ_TIMER;		/* current tick value */
+
+	if (now >= lastinc)		/* normal mode (non roll) */
+		timestamp += (now - lastinc); /* move stamp fordward with absoulte diff ticks */
+	else				/* we have rollover of incrementer */
+		timestamp += (0xFFFFFFFF - lastinc) + now;
+	lastinc = now;
+	return timestamp;
+}
+
+/* waits specified delay value and resets timestamp */
+void udelay_masked (unsigned long usec)
+{
+	ulong tmo;
+	ulong endtime;
+	signed long diff;
+
+	if (usec >= 1000) {			/* if "big" number, spread normalization to seconds */
+		tmo = usec / 1000;		/* start to normalize for usec to ticks per sec */
+		tmo *= CONFIG_SYS_HZ;			/* find number of "ticks" to wait to achieve target */
+		tmo /= 1000;			/* finish normalize. */
+	} else {					/* else small number, don't kill it prior to HZ multiply */
+		tmo = usec * CONFIG_SYS_HZ;
+		tmo /= (1000*1000);
+	}
+	endtime = get_timer_masked () + tmo;
+
+	do {
+		ulong now = get_timer_masked ();
+		diff = endtime - now;
+	} while (diff >= 0);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{
+	ulong tbclk;
+	tbclk = CONFIG_SYS_HZ;
+	return tbclk;
+}

arch/arm/cpu/arm1136/start.S

@@ -0,0 +1,527 @@
+/*
+ *  armboot - Startup Code for OMP2420/ARM1136 CPU-core
+ *
+ *  Copyright (c) 2004	Texas Instruments <r-woodruff2@ti.com>
+ *
+ *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
+ *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
+ *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
+ *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
+ *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <version.h>
+.globl _start
+_start: b	reset
+#ifdef CONFIG_PRELOADER
+	ldr	pc, _hang
+	ldr	pc, _hang
+	ldr	pc, _hang
+	ldr	pc, _hang
+	ldr	pc, _hang
+	ldr	pc, _hang
+	ldr	pc, _hang
+
+_hang:
+	.word	do_hang
+	.word	0x12345678
+	.word	0x12345678
+	.word	0x12345678
+	.word	0x12345678
+	.word	0x12345678
+	.word	0x12345678
+	.word	0x12345678	/* now 16*4=64 */
+#else
+	ldr	pc, _undefined_instruction
+	ldr	pc, _software_interrupt
+	ldr	pc, _prefetch_abort
+	ldr	pc, _data_abort
+	ldr	pc, _not_used
+	ldr	pc, _irq
+	ldr	pc, _fiq
+
+_undefined_instruction: .word undefined_instruction
+_software_interrupt:	.word software_interrupt
+_prefetch_abort:	.word prefetch_abort
+_data_abort:		.word data_abort
+_not_used:		.word not_used
+_irq:			.word irq
+_fiq:			.word fiq
+_pad:			.word 0x12345678 /* now 16*4=64 */
+#endif	/* CONFIG_PRELOADER */
+.global _end_vect
+_end_vect:
+
+	.balignl 16,0xdeadbeef
+/*
+ *************************************************************************
+ *
+ * Startup Code (reset vector)
+ *
+ * do important init only if we don't start from memory!
+ * setup Memory and board specific bits prior to relocation.
+ * relocate armboot to ram
+ * setup stack
+ *
+ *************************************************************************
+ */
+
+.globl _TEXT_BASE
+_TEXT_BASE:
+	.word	CONFIG_SYS_TEXT_BASE
+
+/*
+ * These are defined in the board-specific linker script.
+ * Subtracting _start from them lets the linker put their
+ * relative position in the executable instead of leaving
+ * them null.
+ */
+.globl _bss_start_ofs
+_bss_start_ofs:
+	.word __bss_start - _start
+
+.globl _bss_end_ofs
+_bss_end_ofs:
+	.word _end - _start
+
+#ifdef CONFIG_USE_IRQ
+/* IRQ stack memory (calculated at run-time) */
+.globl IRQ_STACK_START
+IRQ_STACK_START:
+	.word	0x0badc0de
+
+/* IRQ stack memory (calculated at run-time) */
+.globl FIQ_STACK_START
+FIQ_STACK_START:
+	.word 0x0badc0de
+#endif
+
+/* IRQ stack memory (calculated at run-time) + 8 bytes */
+.globl IRQ_STACK_START_IN
+IRQ_STACK_START_IN:
+	.word	0x0badc0de
+
+/*
+ * the actual reset code
+ */
+
+reset:
+	/*
+	 * set the cpu to SVC32 mode
+	 */
+	mrs	r0,cpsr
+	bic	r0,r0,#0x1f
+	orr	r0,r0,#0xd3
+	msr	cpsr,r0
+
+#ifdef CONFIG_OMAP2420H4
+       /* Copy vectors to mask ROM indirect addr */
+	adr	r0, _start		/* r0 <- current position of code   */
+		add     r0, r0, #4				/* skip reset vector			*/
+	mov	r2, #64			/* r2 <- size to copy  */
+	add	r2, r0, r2		/* r2 <- source end address	    */
+	mov	r1, #SRAM_OFFSET0	  /* build vect addr */
+	mov	r3, #SRAM_OFFSET1
+	add	r1, r1, r3
+	mov	r3, #SRAM_OFFSET2
+	add	r1, r1, r3
+next:
+	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
+	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
+	cmp	r0, r2			/* until source end address [r2]    */
+	bne	next			/* loop until equal */
+	bl	cpy_clk_code		/* put dpll adjust code behind vectors */
+#endif
+	/* the mask ROM code should have PLL and others stable */
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+	bl  cpu_init_crit
+#endif
+
+/* Set stackpointer in internal RAM to call board_init_f */
+call_board_init_f:
+	ldr	sp, =(CONFIG_SYS_INIT_SP_ADDR)
+	ldr	r0,=0x00000000
+
+#ifdef CONFIG_NAND_SPL
+	bl	nand_boot
+#else
+#ifdef CONFIG_ONENAND_IPL
+	bl	start_oneboot
+#else
+	bl	board_init_f
+#endif /* CONFIG_ONENAND_IPL */
+#endif /* CONFIG_NAND_SPL */
+
+/*------------------------------------------------------------------------------*/
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ */
+	.globl	relocate_code
+relocate_code:
+	mov	r4, r0	/* save addr_sp */
+	mov	r5, r1	/* save addr of gd */
+	mov	r6, r2	/* save addr of destination */
+	mov	r7, r2	/* save addr of destination */
+
+	/* Set up the stack						    */
+stack_setup:
+	mov	sp, r4
+
+	adr	r0, _start
+	ldr	r2, _TEXT_BASE
+	ldr	r3, _bss_start_ofs
+	add	r2, r0, r3		/* r2 <- source end address	    */
+	cmp	r0, r6
+	beq	clear_bss
+
+copy_loop:
+	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
+	stmia	r6!, {r9-r10}		/* copy to   target address [r1]    */
+	cmp	r0, r2			/* until source end address [r2]    */
+	blo	copy_loop
+
+#ifndef CONFIG_PRELOADER
+	/*
+	 * fix .rel.dyn relocations
+	 */
+	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
+	sub	r9, r7, r0		/* r9 <- relocation offset */
+	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
+	add	r10, r10, r0		/* r10 <- sym table in FLASH */
+	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
+	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
+	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
+	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
+fixloop:
+	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
+	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
+	ldr	r1, [r2, #4]
+	and	r8, r1, #0xff
+	cmp	r8, #23			/* relative fixup? */
+	beq	fixrel
+	cmp	r8, #2			/* absolute fixup? */
+	beq	fixabs
+	/* ignore unknown type of fixup */
+	b	fixnext
+fixabs:
+	/* absolute fix: set location to (offset) symbol value */
+	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
+	add	r1, r10, r1		/* r1 <- address of symbol in table */
+	ldr	r1, [r1, #4]		/* r1 <- symbol value */
+	add	r1, r9			/* r1 <- relocated sym addr */
+	b	fixnext
+fixrel:
+	/* relative fix: increase location by offset */
+	ldr	r1, [r0]
+	add	r1, r1, r9
+fixnext:
+	str	r1, [r0]
+	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
+	cmp	r2, r3
+	blo	fixloop
+#endif
+
+clear_bss:
+#ifndef CONFIG_PRELOADER
+	ldr	r0, _bss_start_ofs
+	ldr	r1, _bss_end_ofs
+	ldr	r3, _TEXT_BASE		/* Text base */
+	mov	r4, r7			/* reloc addr */
+	add	r0, r0, r4
+	add	r1, r1, r4
+	mov	r2, #0x00000000		/* clear			    */
+
+clbss_l:str	r2, [r0]		/* clear loop...		    */
+	add	r0, r0, #4
+	cmp	r0, r1
+	bne	clbss_l
+#endif	/* #ifndef CONFIG_PRELOADER */
+
+/*
+ * We are done. Do not return, instead branch to second part of board
+ * initialization, now running from RAM.
+ */
+#ifdef CONFIG_NAND_SPL
+	ldr     r0, _nand_boot_ofs
+	adr	r1, _start
+	add	pc, r0, r1
+_nand_boot_ofs
+	: .word nand_boot - _start
+#else
+jump_2_ram:
+	ldr	r0, _board_init_r_ofs
+	adr	r1, _start
+	add	lr, r0, r1
+	add	lr, lr, r9
+	/* setup parameters for board_init_r */
+	mov	r0, r5		/* gd_t */
+	mov	r1, r7		/* dest_addr */
+	/* jump to it ... */
+	mov	pc, lr
+
+_board_init_r_ofs:
+	.word board_init_r - _start
+#endif
+
+_rel_dyn_start_ofs:
+	.word __rel_dyn_start - _start
+_rel_dyn_end_ofs:
+	.word __rel_dyn_end - _start
+_dynsym_start_ofs:
+	.word __dynsym_start - _start
+
+/*
+ *************************************************************************
+ *
+ * CPU_init_critical registers
+ *
+ * setup important registers
+ * setup memory timing
+ *
+ *************************************************************************
+ */
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+cpu_init_crit:
+	/*
+	 * flush v4 I/D caches
+	 */
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c7, 0	/* Invalidate I+D+BTB caches */
+	mcr	p15, 0, r0, c8, c7, 0	/* Invalidate Unified TLB */
+
+	/*
+	 * disable MMU stuff and caches
+	 */
+	mrc	p15, 0, r0, c1, c0, 0
+	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
+	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
+	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
+	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
+	mcr	p15, 0, r0, c1, c0, 0
+
+	/*
+	 * Jump to board specific initialization... The Mask ROM will have already initialized
+	 * basic memory.  Go here to bump up clock rate and handle wake up conditions.
+	 */
+	mov	ip, lr		/* persevere link reg across call */
+	bl	lowlevel_init	/* go setup pll,mux,memory */
+	mov	lr, ip		/* restore link */
+	mov	pc, lr		/* back to my caller */
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
+
+#ifndef CONFIG_PRELOADER
+/*
+ *************************************************************************
+ *
+ * Interrupt handling
+ *
+ *************************************************************************
+ */
+@
+@ IRQ stack frame.
+@
+#define S_FRAME_SIZE	72
+
+#define S_OLD_R0	68
+#define S_PSR		64
+#define S_PC		60
+#define S_LR		56
+#define S_SP		52
+
+#define S_IP		48
+#define S_FP		44
+#define S_R10		40
+#define S_R9		36
+#define S_R8		32
+#define S_R7		28
+#define S_R6		24
+#define S_R5		20
+#define S_R4		16
+#define S_R3		12
+#define S_R2		8
+#define S_R1		4
+#define S_R0		0
+
+#define MODE_SVC 0x13
+#define I_BIT	 0x80
+
+/*
+ * use bad_save_user_regs for abort/prefetch/undef/swi ...
+ * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
+ */
+
+	.macro	bad_save_user_regs
+	sub	sp, sp, #S_FRAME_SIZE		@ carve out a frame on current user stack
+	stmia	sp, {r0 - r12}			@ Save user registers (now in svc mode) r0-r12
+
+	ldr	r2, IRQ_STACK_START_IN		@ set base 2 words into abort stack
+	ldmia	r2, {r2 - r3}			@ get values for "aborted" pc and cpsr (into parm regs)
+	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack
+
+	add	r5, sp, #S_SP
+	mov	r1, lr
+	stmia	r5, {r0 - r3}			@ save sp_SVC, lr_SVC, pc, cpsr
+	mov	r0, sp				@ save current stack into r0 (param register)
+	.endm
+
+	.macro	irq_save_user_regs
+	sub	sp, sp, #S_FRAME_SIZE
+	stmia	sp, {r0 - r12}			@ Calling r0-r12
+	add	r8, sp, #S_PC			@ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
+	stmdb	r8, {sp, lr}^			@ Calling SP, LR
+	str	lr, [r8, #0]			@ Save calling PC
+	mrs	r6, spsr
+	str	r6, [r8, #4]			@ Save CPSR
+	str	r0, [r8, #8]			@ Save OLD_R0
+	mov	r0, sp
+	.endm
+
+	.macro	irq_restore_user_regs
+	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
+	mov	r0, r0
+	ldr	lr, [sp, #S_PC]			@ Get PC
+	add	sp, sp, #S_FRAME_SIZE
+	subs	pc, lr, #4			@ return & move spsr_svc into cpsr
+	.endm
+
+	.macro get_bad_stack
+	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack (enter in banked mode)
+
+	str	lr, [r13]			@ save caller lr in position 0 of saved stack
+	mrs	lr, spsr			@ get the spsr
+	str	lr, [r13, #4]			@ save spsr in position 1 of saved stack
+
+	mov	r13, #MODE_SVC			@ prepare SVC-Mode
+	@ msr	spsr_c, r13
+	msr	spsr, r13			@ switch modes, make sure moves will execute
+	mov	lr, pc				@ capture return pc
+	movs	pc, lr				@ jump to next instruction & switch modes.
+	.endm
+
+	.macro get_bad_stack_swi
+	sub	r13, r13, #4			@ space on current stack for scratch reg.
+	str	r0, [r13]			@ save R0's value.
+	ldr	r0, IRQ_STACK_START_IN		@ get data regions start
+	str	lr, [r0]			@ save caller lr in position 0 of saved stack
+	mrs	r0, spsr			@ get the spsr
+	str	lr, [r0, #4]			@ save spsr in position 1 of saved stack
+	ldr	r0, [r13]			@ restore r0
+	add	r13, r13, #4			@ pop stack entry
+	.endm
+
+	.macro get_irq_stack			@ setup IRQ stack
+	ldr	sp, IRQ_STACK_START
+	.endm
+
+	.macro get_fiq_stack			@ setup FIQ stack
+	ldr	sp, FIQ_STACK_START
+	.endm
+#endif	/* CONFIG_PRELOADER */
+
+/*
+ * exception handlers
+ */
+#ifdef CONFIG_PRELOADER
+	.align	5
+do_hang:
+	ldr	sp, _TEXT_BASE			/* use 32 words about stack */
+	bl	hang				/* hang and never return */
+#else	/* !CONFIG_PRELOADER */
+	.align	5
+undefined_instruction:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_undefined_instruction
+
+	.align	5
+software_interrupt:
+	get_bad_stack_swi
+	bad_save_user_regs
+	bl	do_software_interrupt
+
+	.align	5
+prefetch_abort:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_prefetch_abort
+
+	.align	5
+data_abort:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_data_abort
+
+	.align	5
+not_used:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_not_used
+
+#ifdef CONFIG_USE_IRQ
+
+	.align	5
+irq:
+	get_irq_stack
+	irq_save_user_regs
+	bl	do_irq
+	irq_restore_user_regs
+
+	.align	5
+fiq:
+	get_fiq_stack
+	/* someone ought to write a more effiction fiq_save_user_regs */
+	irq_save_user_regs
+	bl	do_fiq
+	irq_restore_user_regs
+
+#else
+
+	.align	5
+irq:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_irq
+
+	.align	5
+fiq:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_fiq
+
+#endif
+	.align 5
+.global arm1136_cache_flush
+arm1136_cache_flush:
+#if !defined(CONFIG_SYS_NO_ICACHE)
+		mcr	p15, 0, r1, c7, c5, 0	@ invalidate I cache
+#endif
+#if !defined(CONFIG_SYS_NO_DCACHE)
+		mcr	p15, 0, r1, c7, c14, 0	@ invalidate D cache
+#endif
+		mov	pc, lr			@ back to caller
+#endif	/* CONFIG_PRELOADER */

arch/arm/cpu/arm1136/u-boot.lds

@@ -0,0 +1,87 @@
+/*
+ * (C) Copyright 2009
+ * Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
+ *
+ * Copyright (C) 2005-2007 Samsung Electronics
+ * Kyungin Park <kyugnmin.park@samsung.com>
+ *
+ * Copyright (c) 2004 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		arch/arm/cpu/arm1136/start.o	(.text)
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : {
+		*(.data)
+	}
+
+	. = ALIGN(4);
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+
+	.rel.dyn : {
+		__rel_dyn_start = .;
+		*(.rel*)
+		__rel_dyn_end = .;
+	}
+
+	.dynsym : {
+		__dynsym_start = .;
+		*(.dynsym)
+	}
+
+	.bss __rel_dyn_start (OVERLAY) : {
+		__bss_start = .;
+		*(.bss)
+		 . = ALIGN(4);
+		_end = .;
+	}
+
+	/DISCARD/ : { *(.dynstr*) }
+	/DISCARD/ : { *(.dynamic*) }
+	/DISCARD/ : { *(.plt*) }
+	/DISCARD/ : { *(.interp*) }
+	/DISCARD/ : { *(.gnu*) }
+}

arch/arm/cpu/arm1176/Makefile

@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(CPU).o
+
+START	= start.o
+COBJS	= cpu.o
+
+SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+START	:= $(addprefix $(obj),$(START))
+
+all:	$(obj).depend $(START) $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

arch/arm/cpu/arm1176/cpu.c

@@ -0,0 +1,67 @@
+/*
+ * (C) Copyright 2004 Texas Insturments
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * CPU specific code
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/system.h>
+
+static void cache_flush (void);
+
+int cleanup_before_linux (void)
+{
+	/*
+	 * this function is called just before we call linux
+	 * it prepares the processor for linux
+	 *
+	 * we turn off caches etc ...
+	 */
+
+	disable_interrupts ();
+
+	/* turn off I/D-cache */
+	icache_disable();
+	dcache_disable();
+	/* flush I/D-cache */
+	cache_flush();
+
+	return 0;
+}
+
+/* flush I/D-cache */
+static void cache_flush (void)
+{
+	/* invalidate both caches and flush btb */
+	asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (0));
+	/* mem barrier to sync things */
+	asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (0));
+}

arch/arm/cpu/arm1176/s3c64xx/Makefile

@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).o
+
+SOBJS	= reset.o
+
+COBJS-$(CONFIG_S3C6400)	+= cpu_init.o speed.o
+COBJS-y	+= timer.o
+
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
+
+all:	$(obj).depend $(START) $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

arch/arm/cpu/arm1176/start.S

@@ -0,0 +1,573 @@
+/*
+ *  armboot - Startup Code for ARM1176 CPU-core
+ *
+ * Copyright (c) 2007	Samsung Electronics
+ *
+ * Copyright (C) 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * 2007-09-21 - Restructured codes by jsgood (jsgood.yang@samsung.com)
+ * 2007-09-21 - Added MoviNAND and OneNAND boot codes by
+ * jsgood (jsgood.yang@samsung.com)
+ * Base codes by scsuh (sc.suh)
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <version.h>
+#ifdef CONFIG_ENABLE_MMU
+#include <asm/proc/domain.h>
+#endif
+
+#if !defined(CONFIG_ENABLE_MMU) && !defined(CONFIG_SYS_PHY_UBOOT_BASE)
+#define CONFIG_SYS_PHY_UBOOT_BASE	CONFIG_SYS_UBOOT_BASE
+#endif
+
+/*
+ *************************************************************************
+ *
+ * Jump vector table as in table 3.1 in [1]
+ *
+ *************************************************************************
+ */
+
+.globl _start
+_start: b	reset
+#ifndef CONFIG_NAND_SPL
+	ldr	pc, _undefined_instruction
+	ldr	pc, _software_interrupt
+	ldr	pc, _prefetch_abort
+	ldr	pc, _data_abort
+	ldr	pc, _not_used
+	ldr	pc, _irq
+	ldr	pc, _fiq
+
+_undefined_instruction:
+	.word undefined_instruction
+_software_interrupt:
+	.word software_interrupt
+_prefetch_abort:
+	.word prefetch_abort
+_data_abort:
+	.word data_abort
+_not_used:
+	.word not_used
+_irq:
+	.word irq
+_fiq:
+	.word fiq
+_pad:
+	.word 0x12345678 /* now 16*4=64 */
+#else
+	. = _start + 64
+#endif
+
+.global _end_vect
+_end_vect:
+	.balignl 16,0xdeadbeef
+/*
+ *************************************************************************
+ *
+ * Startup Code (reset vector)
+ *
+ * do important init only if we don't start from memory!
+ * setup Memory and board specific bits prior to relocation.
+ * relocate armboot to ram
+ * setup stack
+ *
+ *************************************************************************
+ */
+
+.globl _TEXT_BASE
+_TEXT_BASE:
+	.word	CONFIG_SYS_TEXT_BASE
+
+/*
+ * Below variable is very important because we use MMU in U-Boot.
+ * Without it, we cannot run code correctly before MMU is ON.
+ * by scsuh.
+ */
+_TEXT_PHY_BASE:
+	.word	CONFIG_SYS_PHY_UBOOT_BASE
+
+/*
+ * These are defined in the board-specific linker script.
+ * Subtracting _start from them lets the linker put their
+ * relative position in the executable instead of leaving
+ * them null.
+ */
+
+.globl _bss_start_ofs
+_bss_start_ofs:
+	.word __bss_start - _start
+
+.globl _bss_end_ofs
+_bss_end_ofs:
+	.word _end - _start
+
+/* IRQ stack memory (calculated at run-time) + 8 bytes */
+.globl IRQ_STACK_START_IN
+IRQ_STACK_START_IN:
+	.word	0x0badc0de
+
+/*
+ * the actual reset code
+ */
+
+reset:
+	/*
+	 * set the cpu to SVC32 mode
+	 */
+	mrs	r0, cpsr
+	bic	r0, r0, #0x3f
+	orr	r0, r0, #0xd3
+	msr	cpsr, r0
+
+/*
+ *************************************************************************
+ *
+ * CPU_init_critical registers
+ *
+ * setup important registers
+ * setup memory timing
+ *
+ *************************************************************************
+ */
+	/*
+	 * we do sys-critical inits only at reboot,
+	 * not when booting from ram!
+	 */
+cpu_init_crit:
+	/*
+	 * When booting from NAND - it has definitely been a reset, so, no need
+	 * to flush caches and disable the MMU
+	 */
+#ifndef CONFIG_NAND_SPL
+	/*
+	 * flush v4 I/D caches
+	 */
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
+	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
+
+	/*
+	 * disable MMU stuff and caches
+	 */
+	mrc	p15, 0, r0, c1, c0, 0
+	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
+	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
+	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
+	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
+
+	/* Prepare to disable the MMU */
+	adr	r2, mmu_disable_phys
+	sub	r2, r2, #(CONFIG_SYS_PHY_UBOOT_BASE - CONFIG_SYS_TEXT_BASE)
+	b	mmu_disable
+
+	.align 5
+	/* Run in a single cache-line */
+mmu_disable:
+	mcr	p15, 0, r0, c1, c0, 0
+	nop
+	nop
+	mov	pc, r2
+mmu_disable_phys:
+
+#ifdef CONFIG_DISABLE_TCM
+	/*
+	 * Disable the TCMs
+	 */
+	mrc	p15, 0, r0, c0, c0, 2	/* Return TCM details */
+	cmp	r0, #0
+	beq	skip_tcmdisable
+	mov	r1, #0
+	mov	r2, #1
+	tst	r0, r2
+	mcrne	p15, 0, r1, c9, c1, 1	/* Disable Instruction TCM if present*/
+	tst	r0, r2, LSL #16
+	mcrne	p15, 0, r1, c9, c1, 0	/* Disable Data TCM if present*/
+skip_tcmdisable:
+#endif
+#endif
+
+#ifdef CONFIG_PERIPORT_REMAP
+	/* Peri port setup */
+	ldr	r0, =CONFIG_PERIPORT_BASE
+	orr	r0, r0, #CONFIG_PERIPORT_SIZE
+	mcr	p15,0,r0,c15,c2,4
+#endif
+
+	/*
+	 * Go setup Memory and board specific bits prior to relocation.
+	 */
+	bl	lowlevel_init		/* go setup pll,mux,memory */
+
+/* Set stackpointer in internal RAM to call board_init_f */
+call_board_init_f:
+	ldr	sp, =(CONFIG_SYS_INIT_SP_ADDR)
+	ldr	r0,=0x00000000
+	bl	board_init_f
+
+/*------------------------------------------------------------------------------*/
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ */
+	.globl	relocate_code
+relocate_code:
+	mov	r4, r0	/* save addr_sp */
+	mov	r5, r1	/* save addr of gd */
+	mov	r6, r2	/* save addr of destination */
+	mov	r7, r2	/* save addr of destination */
+
+	/* Set up the stack						    */
+stack_setup:
+	mov	sp, r4
+
+	adr	r0, _start
+	ldr	r2, _TEXT_BASE
+	ldr	r3, _bss_start_ofs
+	add	r2, r0, r3		/* r2 <- source end address	    */
+	cmp	r0, r6
+	beq	clear_bss
+
+copy_loop:
+	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
+	stmia	r6!, {r9-r10}		/* copy to   target address [r1]    */
+	cmp	r0, r2			/* until source end address [r2]    */
+	blo	copy_loop
+
+#ifndef CONFIG_PRELOADER
+	/*
+	 * fix .rel.dyn relocations
+	 */
+	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
+	sub	r9, r7, r0		/* r9 <- relocation offset */
+	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
+	add	r10, r10, r0		/* r10 <- sym table in FLASH */
+	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
+	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
+	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
+	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
+fixloop:
+	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
+	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
+	ldr	r1, [r2, #4]
+	and	r8, r1, #0xff
+	cmp	r8, #23			/* relative fixup? */
+	beq	fixrel
+	cmp	r8, #2			/* absolute fixup? */
+	beq	fixabs
+	/* ignore unknown type of fixup */
+	b	fixnext
+fixabs:
+	/* absolute fix: set location to (offset) symbol value */
+	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
+	add	r1, r10, r1		/* r1 <- address of symbol in table */
+	ldr	r1, [r1, #4]		/* r1 <- symbol value */
+	add	r1, r9			/* r1 <- relocated sym addr */
+	b	fixnext
+fixrel:
+	/* relative fix: increase location by offset */
+	ldr	r1, [r0]
+	add	r1, r1, r9
+fixnext:
+	str	r1, [r0]
+	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
+	cmp	r2, r3
+	blo	fixloop
+#endif
+
+#ifdef CONFIG_ENABLE_MMU
+enable_mmu:
+	/* enable domain access */
+	ldr	r5, =0x0000ffff
+	mcr	p15, 0, r5, c3, c0, 0	/* load domain access register */
+
+	/* Set the TTB register */
+	ldr	r0, _mmu_table_base
+	ldr	r1, =CONFIG_SYS_PHY_UBOOT_BASE
+	ldr	r2, =0xfff00000
+	bic	r0, r0, r2
+	orr	r1, r0, r1
+	mcr	p15, 0, r1, c2, c0, 0
+
+	/* Enable the MMU */
+	mrc	p15, 0, r0, c1, c0, 0
+	orr	r0, r0, #1		/* Set CR_M to enable MMU */
+
+	/* Prepare to enable the MMU */
+	adr	r1, skip_hw_init
+	and	r1, r1, #0x3fc
+	ldr	r2, _TEXT_BASE
+	ldr	r3, =0xfff00000
+	and	r2, r2, r3
+	orr	r2, r2, r1
+	b	mmu_enable
+
+	.align 5
+	/* Run in a single cache-line */
+mmu_enable:
+
+	mcr	p15, 0, r0, c1, c0, 0
+	nop
+	nop
+	mov	pc, r2
+skip_hw_init:
+#endif
+
+clear_bss:
+#ifndef CONFIG_PRELOADER
+	ldr	r0, _bss_start_ofs
+	ldr	r1, _bss_end_ofs
+	ldr	r3, _TEXT_BASE		/* Text base */
+	mov	r4, r7			/* reloc addr */
+	add	r0, r0, r4
+	add	r1, r1, r4
+	mov	r2, #0x00000000		/* clear			    */
+
+clbss_l:str	r2, [r0]		/* clear loop...		    */
+	add	r0, r0, #4
+	cmp	r0, r1
+	bne	clbss_l
+
+	bl coloured_LED_init
+	bl red_LED_on
+#endif
+
+/*
+ * We are done. Do not return, instead branch to second part of board
+ * initialization, now running from RAM.
+ */
+#ifdef CONFIG_NAND_SPL
+	ldr     pc, _nand_boot
+
+_nand_boot: .word nand_boot
+#else
+	ldr	r0, _board_init_r_ofs
+	adr	r1, _start
+	add	lr, r0, r1
+	add     lr, lr, r9
+	/* setup parameters for board_init_r */
+	mov	r0, r5		/* gd_t */
+	mov	r1, r7		/* dest_addr */
+	/* jump to it ... */
+	mov	pc, lr
+
+_board_init_r_ofs:
+	.word board_init_r - _start
+#endif
+
+_rel_dyn_start_ofs:
+	.word __rel_dyn_start - _start
+_rel_dyn_end_ofs:
+	.word __rel_dyn_end - _start
+_dynsym_start_ofs:
+	.word __dynsym_start - _start
+
+#ifdef CONFIG_ENABLE_MMU
+_mmu_table_base:
+	.word mmu_table
+#endif
+
+#ifndef CONFIG_NAND_SPL
+/*
+ * we assume that cache operation is done before. (eg. cleanup_before_linux())
+ * actually, we don't need to do anything about cache if not use d-cache in
+ * U-Boot. So, in this function we clean only MMU. by scsuh
+ *
+ * void	theLastJump(void *kernel, int arch_num, uint boot_params);
+ */
+#ifdef CONFIG_ENABLE_MMU
+	.globl theLastJump
+theLastJump:
+	mov	r9, r0
+	ldr	r3, =0xfff00000
+	ldr	r4, _TEXT_PHY_BASE
+	adr	r5, phy_last_jump
+	bic	r5, r5, r3
+	orr	r5, r5, r4
+	mov	pc, r5
+phy_last_jump:
+	/*
+	 * disable MMU stuff
+	 */
+	mrc	p15, 0, r0, c1, c0, 0
+	bic	r0, r0, #0x00002300	/* clear bits 13, 9:8 (--V- --RS) */
+	bic	r0, r0, #0x00000087	/* clear bits 7, 2:0 (B--- -CAM) */
+	orr	r0, r0, #0x00000002	/* set bit 2 (A) Align */
+	orr	r0, r0, #0x00001000	/* set bit 12 (I) I-Cache */
+	mcr	p15, 0, r0, c1, c0, 0
+
+	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
+
+	mov	r0, #0
+	mov	pc, r9
+#endif
+
+
+/*
+ *************************************************************************
+ *
+ * Interrupt handling
+ *
+ *************************************************************************
+ */
+@
+@ IRQ stack frame.
+@
+#define S_FRAME_SIZE	72
+
+#define S_OLD_R0	68
+#define S_PSR		64
+#define S_PC		60
+#define S_LR		56
+#define S_SP		52
+
+#define S_IP		48
+#define S_FP		44
+#define S_R10		40
+#define S_R9		36
+#define S_R8		32
+#define S_R7		28
+#define S_R6		24
+#define S_R5		20
+#define S_R4		16
+#define S_R3		12
+#define S_R2		8
+#define S_R1		4
+#define S_R0		0
+
+#define MODE_SVC 0x13
+#define I_BIT	 0x80
+
+/*
+ * use bad_save_user_regs for abort/prefetch/undef/swi ...
+ */
+
+	.macro	bad_save_user_regs
+	/* carve out a frame on current user stack */
+	sub	sp, sp, #S_FRAME_SIZE
+	/* Save user registers (now in svc mode) r0-r12 */
+	stmia	sp, {r0 - r12}
+
+	ldr	r2, IRQ_STACK_START_IN
+	/* get values for "aborted" pc and cpsr (into parm regs) */
+	ldmia	r2, {r2 - r3}
+	/* grab pointer to old stack */
+	add	r0, sp, #S_FRAME_SIZE
+
+	add	r5, sp, #S_SP
+	mov	r1, lr
+	/* save sp_SVC, lr_SVC, pc, cpsr */
+	stmia	r5, {r0 - r3}
+	/* save current stack into r0 (param register) */
+	mov	r0, sp
+	.endm
+
+	.macro get_bad_stack
+	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
+
+	/* save caller lr in position 0 of saved stack */
+	str	lr, [r13]
+	/* get the spsr */
+	mrs	lr, spsr
+	/* save spsr in position 1 of saved stack */
+	str	lr, [r13, #4]
+
+	/* prepare SVC-Mode */
+	mov	r13, #MODE_SVC
+	@ msr	spsr_c, r13
+	/* switch modes, make sure moves will execute */
+	msr	spsr, r13
+	/* capture return pc */
+	mov	lr, pc
+	/* jump to next instruction & switch modes. */
+	movs	pc, lr
+	.endm
+
+	.macro get_bad_stack_swi
+	/* space on current stack for scratch reg. */
+	sub	r13, r13, #4
+	/* save R0's value. */
+	str	r0, [r13]
+	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
+	/* save caller lr in position 0 of saved stack */
+	str	lr, [r0]
+	/* get the spsr */
+	mrs	r0, spsr
+	/* save spsr in position 1 of saved stack */
+	str	lr, [r0, #4]
+	/* restore r0 */
+	ldr	r0, [r13]
+	/* pop stack entry */
+	add	r13, r13, #4
+	.endm
+
+/*
+ * exception handlers
+ */
+	.align	5
+undefined_instruction:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_undefined_instruction
+
+	.align	5
+software_interrupt:
+	get_bad_stack_swi
+	bad_save_user_regs
+	bl	do_software_interrupt
+
+	.align	5
+prefetch_abort:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_prefetch_abort
+
+	.align	5
+data_abort:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_data_abort
+
+	.align	5
+not_used:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_not_used
+
+	.align	5
+irq:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_irq
+
+	.align	5
+fiq:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_fiq
+#endif /* CONFIG_NAND_SPL */

arch/arm/cpu/arm1176/tnetv107x/Makefile

@@ -0,0 +1,44 @@
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).o
+
+COBJS	+= aemif.o clock.o init.o mux.o timer.o wdt.o
+SOBJS	+= lowlevel_init.o
+
+SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+
+OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+START	:= $(addprefix $(obj),$(START))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

arch/arm/cpu/arm1176/tnetv107x/aemif.c

@@ -0,0 +1,93 @@
+/*
+ * TNETV107X: Asynchronous EMIF Configuration
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/mux.h>
+
+#define ASYNC_EMIF_BASE			TNETV107X_ASYNC_EMIF_CNTRL_BASE
+#define ASYNC_EMIF_CONFIG(cs)		(ASYNC_EMIF_BASE+0x10+(cs)*4)
+#define ASYNC_EMIF_ONENAND_CONTROL	(ASYNC_EMIF_BASE+0x5c)
+#define ASYNC_EMIF_NAND_CONTROL		(ASYNC_EMIF_BASE+0x60)
+#define ASYNC_EMIF_WAITCYCLE_CONFIG	(ASYNC_EMIF_BASE+0x4)
+
+#define CONFIG_SELECT_STROBE(v)		((v) ? 1 << 31 : 0)
+#define CONFIG_EXTEND_WAIT(v)		((v) ? 1 << 30 : 0)
+#define CONFIG_WR_SETUP(v)		(((v) & 0x0f) << 26)
+#define CONFIG_WR_STROBE(v)		(((v) & 0x3f) << 20)
+#define CONFIG_WR_HOLD(v)		(((v) & 0x07) << 17)
+#define CONFIG_RD_SETUP(v)		(((v) & 0x0f) << 13)
+#define CONFIG_RD_STROBE(v)		(((v) & 0x3f) << 7)
+#define CONFIG_RD_HOLD(v)		(((v) & 0x07) << 4)
+#define CONFIG_TURN_AROUND(v)		(((v) & 0x03) << 2)
+#define CONFIG_WIDTH(v)			(((v) & 0x03) << 0)
+
+#define NUM_CS				4
+
+#define set_config_field(reg, field, val)			\
+	do {							\
+		if (val != -1) {				\
+			reg &= ~CONFIG_##field(0xffffffff);	\
+			reg |=	CONFIG_##field(val);		\
+		}						\
+	} while (0)
+
+void configure_async_emif(int cs, struct async_emif_config *cfg)
+{
+	unsigned long tmp;
+
+	if (cfg->mode == ASYNC_EMIF_MODE_NAND) {
+		tmp = __raw_readl(ASYNC_EMIF_NAND_CONTROL);
+		tmp |= (1 << cs);
+		__raw_writel(tmp, ASYNC_EMIF_NAND_CONTROL);
+
+	} else if (cfg->mode == ASYNC_EMIF_MODE_ONENAND) {
+		tmp = __raw_readl(ASYNC_EMIF_ONENAND_CONTROL);
+		tmp |= (1 << cs);
+		__raw_writel(tmp, ASYNC_EMIF_ONENAND_CONTROL);
+	}
+
+	tmp = __raw_readl(ASYNC_EMIF_CONFIG(cs));
+
+	set_config_field(tmp, SELECT_STROBE,	cfg->select_strobe);
+	set_config_field(tmp, EXTEND_WAIT,	cfg->extend_wait);
+	set_config_field(tmp, WR_SETUP,		cfg->wr_setup);
+	set_config_field(tmp, WR_STROBE,	cfg->wr_strobe);
+	set_config_field(tmp, WR_HOLD,		cfg->wr_hold);
+	set_config_field(tmp, RD_SETUP,		cfg->rd_setup);
+	set_config_field(tmp, RD_STROBE,	cfg->rd_strobe);
+	set_config_field(tmp, RD_HOLD,		cfg->rd_hold);
+	set_config_field(tmp, TURN_AROUND,	cfg->turn_around);
+	set_config_field(tmp, WIDTH,		cfg->width);
+
+	__raw_writel(tmp, ASYNC_EMIF_CONFIG(cs));
+}
+
+void init_async_emif(int num_cs, struct async_emif_config *config)
+{
+	int cs;
+
+	clk_enable(TNETV107X_LPSC_AEMIF);
+
+	for (cs = 0; cs < num_cs; cs++)
+		configure_async_emif(cs, config + cs);
+}

arch/arm/cpu/arm1176/tnetv107x/clock.c

@@ -0,0 +1,451 @@
+/*
+ * TNETV107X: Clock management APIs
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm-generic/errno.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/arch/clock.h>
+
+#define CLOCK_BASE		TNETV107X_CLOCK_CONTROL_BASE
+#define PSC_BASE		TNETV107X_PSC_BASE
+
+#define BIT(x)			(1 << (x))
+
+#define MAX_PREDIV		64
+#define MAX_POSTDIV		8
+#define MAX_MULT		512
+#define MAX_DIV			(MAX_PREDIV * MAX_POSTDIV)
+
+/* LPSC registers */
+#define PSC_PTCMD		0x120
+#define PSC_PTSTAT		0x128
+#define PSC_MDSTAT(n)		(0x800 + (n) * 4)
+#define PSC_MDCTL(n)		(0xA00 + (n) * 4)
+
+#define PSC_MDCTL_LRSTZ		BIT(8)
+
+#define psc_reg_read(reg)	__raw_readl((u32 *)(PSC_BASE + (reg)))
+#define psc_reg_write(reg, val)	__raw_writel(val, (u32 *)(PSC_BASE + (reg)))
+
+/* SSPLL registers */
+struct sspll_regs {
+	u32	modes;
+	u32	postdiv;
+	u32	prediv;
+	u32	mult_factor;
+	u32	divider_range;
+	u32	bw_divider;
+	u32	spr_amount;
+	u32	spr_rate_div;
+	u32	diag;
+};
+
+/* SSPLL base addresses */
+static struct sspll_regs *sspll_regs[] = {
+	(struct sspll_regs *)(CLOCK_BASE + 0x040),
+	(struct sspll_regs *)(CLOCK_BASE + 0x080),
+	(struct sspll_regs *)(CLOCK_BASE + 0x0c0),
+};
+
+#define sspll_reg(pll, reg)		(&(sspll_regs[pll]->reg))
+#define sspll_reg_read(pll, reg)	__raw_readl(sspll_reg(pll, reg))
+#define sspll_reg_write(pll, reg, val)	__raw_writel(val, sspll_reg(pll, reg))
+
+
+/* PLL Control Registers */
+struct pllctl_regs {
+	u32	ctl;		/* 00 */
+	u32	ocsel;		/* 04 */
+	u32	secctl;		/* 08 */
+	u32	__pad0;
+	u32	mult;		/* 10 */
+	u32	prediv;		/* 14 */
+	u32	div1;		/* 18 */
+	u32	div2;		/* 1c */
+	u32	div3;		/* 20 */
+	u32	oscdiv1;	/* 24 */
+	u32	postdiv;	/* 28 */
+	u32	bpdiv;		/* 2c */
+	u32	wakeup;		/* 30 */
+	u32	__pad1;
+	u32	cmd;		/* 38 */
+	u32	stat;		/* 3c */
+	u32	alnctl;		/* 40 */
+	u32	dchange;	/* 44 */
+	u32	cken;		/* 48 */
+	u32	ckstat;		/* 4c */
+	u32	systat;		/* 50 */
+	u32	ckctl;		/* 54 */
+	u32	__pad2[2];
+	u32	div4;		/* 60 */
+	u32	div5;		/* 64 */
+	u32	div6;		/* 68 */
+	u32	div7;		/* 6c */
+	u32	div8;		/* 70 */
+};
+
+struct lpsc_map {
+	int	pll, div;
+};
+
+static struct pllctl_regs *pllctl_regs[] = {
+	(struct pllctl_regs *)(CLOCK_BASE + 0x700),
+	(struct pllctl_regs *)(CLOCK_BASE + 0x300),
+	(struct pllctl_regs *)(CLOCK_BASE + 0x500),
+};
+
+#define pllctl_reg(pll, reg)		(&(pllctl_regs[pll]->reg))
+#define pllctl_reg_read(pll, reg)	__raw_readl(pllctl_reg(pll, reg))
+#define pllctl_reg_write(pll, reg, val)	__raw_writel(val, pllctl_reg(pll, reg))
+
+#define pllctl_reg_rmw(pll, reg, mask, val)			\
+	pllctl_reg_write(pll, reg,				\
+		(pllctl_reg_read(pll, reg) & ~(mask)) | val)
+
+#define pllctl_reg_setbits(pll, reg, mask)			\
+	pllctl_reg_rmw(pll, reg, 0, mask)
+
+#define pllctl_reg_clrbits(pll, reg, mask)			\
+	pllctl_reg_rmw(pll, reg, mask, 0)
+
+/* PLLCTL Bits */
+#define PLLCTL_CLKMODE		BIT(8)
+#define PLLCTL_PLLSELB		BIT(7)
+#define PLLCTL_PLLENSRC		BIT(5)
+#define PLLCTL_PLLDIS		BIT(4)
+#define PLLCTL_PLLRST		BIT(3)
+#define PLLCTL_PLLPWRDN		BIT(1)
+#define PLLCTL_PLLEN		BIT(0)
+
+#define PLLDIV_ENABLE		BIT(15)
+
+static int pll_div_offset[] = {
+#define div_offset(reg)	offsetof(struct pllctl_regs, reg)
+	div_offset(div1), div_offset(div2), div_offset(div3),
+	div_offset(div4), div_offset(div5), div_offset(div6),
+	div_offset(div7), div_offset(div8),
+};
+
+static unsigned long pll_bypass_mask[] = { 1, 4, 2 };
+static unsigned long pll_div_mask[] = { 0x01ff, 0x00ff, 0x00ff };
+
+/* Mappings from PLL+DIV to subsystem clocks */
+#define sys_arm1176_clk		{SYS_PLL, 0}
+#define sys_dsp_clk		{SYS_PLL, 1}
+#define sys_ddr_clk		{SYS_PLL, 2}
+#define sys_full_clk		{SYS_PLL, 3}
+#define sys_lcd_clk		{SYS_PLL, 4}
+#define sys_vlynq_ref_clk	{SYS_PLL, 5}
+#define sys_tsc_clk		{SYS_PLL, 6}
+#define sys_half_clk		{SYS_PLL, 7}
+
+#define eth_clk_5		{ETH_PLL, 0}
+#define eth_clk_50		{ETH_PLL, 1}
+#define eth_clk_125		{ETH_PLL, 2}
+#define eth_clk_250		{ETH_PLL, 3}
+#define eth_clk_25		{ETH_PLL, 4}
+
+#define tdm_clk			{TDM_PLL, 0}
+#define tdm_extra_clk		{TDM_PLL, 1}
+#define tdm1_clk		{TDM_PLL, 2}
+
+/* Optimization barrier */
+#define barrier()	\
+	__asm__ __volatile__("mov r0, r0\n" : : : "memory");
+
+static const struct lpsc_map lpsc_clk_map[] = {
+	[TNETV107X_LPSC_ARM]			= sys_arm1176_clk,
+	[TNETV107X_LPSC_GEM]			= sys_dsp_clk,
+	[TNETV107X_LPSC_DDR2_PHY]		= sys_ddr_clk,
+	[TNETV107X_LPSC_TPCC]			= sys_full_clk,
+	[TNETV107X_LPSC_TPTC0]			= sys_full_clk,
+	[TNETV107X_LPSC_TPTC1]			= sys_full_clk,
+	[TNETV107X_LPSC_RAM]			= sys_full_clk,
+	[TNETV107X_LPSC_MBX_LITE]		= sys_arm1176_clk,
+	[TNETV107X_LPSC_LCD]			= sys_lcd_clk,
+	[TNETV107X_LPSC_ETHSS]			= eth_clk_125,
+	[TNETV107X_LPSC_AEMIF]			= sys_full_clk,
+	[TNETV107X_LPSC_CHIP_CFG]		= sys_half_clk,
+	[TNETV107X_LPSC_TSC]			= sys_tsc_clk,
+	[TNETV107X_LPSC_ROM]			= sys_half_clk,
+	[TNETV107X_LPSC_UART2]			= sys_half_clk,
+	[TNETV107X_LPSC_PKTSEC]			= sys_half_clk,
+	[TNETV107X_LPSC_SECCTL]			= sys_half_clk,
+	[TNETV107X_LPSC_KEYMGR]			= sys_half_clk,
+	[TNETV107X_LPSC_KEYPAD]			= sys_half_clk,
+	[TNETV107X_LPSC_GPIO]			= sys_half_clk,
+	[TNETV107X_LPSC_MDIO]			= sys_half_clk,
+	[TNETV107X_LPSC_SDIO0]			= sys_half_clk,
+	[TNETV107X_LPSC_UART0]			= sys_half_clk,
+	[TNETV107X_LPSC_UART1]			= sys_half_clk,
+	[TNETV107X_LPSC_TIMER0]			= sys_half_clk,
+	[TNETV107X_LPSC_TIMER1]			= sys_half_clk,
+	[TNETV107X_LPSC_WDT_ARM]		= sys_half_clk,
+	[TNETV107X_LPSC_WDT_DSP]		= sys_half_clk,
+	[TNETV107X_LPSC_SSP]			= sys_half_clk,
+	[TNETV107X_LPSC_TDM0]			= tdm_clk,
+	[TNETV107X_LPSC_VLYNQ]			= sys_vlynq_ref_clk,
+	[TNETV107X_LPSC_MCDMA]			= sys_half_clk,
+	[TNETV107X_LPSC_USB0]			= sys_half_clk,
+	[TNETV107X_LPSC_TDM1]			= tdm1_clk,
+	[TNETV107X_LPSC_DEBUGSS]		= sys_half_clk,
+	[TNETV107X_LPSC_ETHSS_RGMII]		= eth_clk_250,
+	[TNETV107X_LPSC_SYSTEM]			= sys_half_clk,
+	[TNETV107X_LPSC_IMCOP]			= sys_dsp_clk,
+	[TNETV107X_LPSC_SPARE]			= sys_half_clk,
+	[TNETV107X_LPSC_SDIO1]			= sys_half_clk,
+	[TNETV107X_LPSC_USB1]			= sys_half_clk,
+	[TNETV107X_LPSC_USBSS]			= sys_half_clk,
+	[TNETV107X_LPSC_DDR2_EMIF1_VRST]	= sys_ddr_clk,
+	[TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST]	= sys_ddr_clk,
+};
+
+static const unsigned long pll_ext_freq[] = {
+	[SYS_PLL] = CONFIG_PLL_SYS_EXT_FREQ,
+	[ETH_PLL] = CONFIG_PLL_ETH_EXT_FREQ,
+	[TDM_PLL] = CONFIG_PLL_TDM_EXT_FREQ,
+};
+
+static unsigned long pll_freq_get(int pll)
+{
+	unsigned long mult = 1, prediv = 1, postdiv = 1;
+	unsigned long ref = CONFIG_SYS_INT_OSC_FREQ;
+	unsigned long ret;
+	u32 bypass;
+
+	bypass = __raw_readl((u32 *)(CLOCK_BASE));
+	if (!(bypass & pll_bypass_mask[pll])) {
+		mult	= sspll_reg_read(pll, mult_factor);
+		prediv	= sspll_reg_read(pll, prediv) + 1;
+		postdiv	= sspll_reg_read(pll, postdiv) + 1;
+	}
+
+	if (pllctl_reg_read(pll, ctl) & PLLCTL_CLKMODE)
+		ref = pll_ext_freq[pll];
+
+	if (!(pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN))
+		return ref;
+
+	ret = (unsigned long)(ref + ((unsigned long long)ref * mult) / 256);
+	ret /= (prediv * postdiv);
+
+	return ret;
+}
+
+static unsigned long __pll_div_freq_get(int pll, unsigned int fpll,
+					int div)
+{
+	int divider = 1;
+	unsigned long divreg;
+
+	divreg = __raw_readl((void *)pllctl_regs[pll] + pll_div_offset[div]);
+
+	if (divreg & PLLDIV_ENABLE)
+		divider = (divreg & pll_div_mask[pll]) + 1;
+
+	return fpll / divider;
+}
+
+static unsigned long pll_div_freq_get(int pll, int div)
+{
+	unsigned int fpll = pll_freq_get(pll);
+
+	return __pll_div_freq_get(pll, fpll, div);
+}
+
+static void __pll_div_freq_set(int pll, unsigned int fpll, int div,
+			       unsigned long hz)
+{
+	int divider = (fpll / hz - 1);
+
+	divider &= pll_div_mask[pll];
+	divider |= PLLDIV_ENABLE;
+
+	__raw_writel(divider, (void *)pllctl_regs[pll] + pll_div_offset[div]);
+	pllctl_reg_setbits(pll, alnctl, (1 << div));
+	pllctl_reg_setbits(pll, dchange, (1 << div));
+}
+
+static unsigned long pll_div_freq_set(int pll, int div, unsigned long hz)
+{
+	unsigned int fpll = pll_freq_get(pll);
+
+	__pll_div_freq_set(pll, fpll, div, hz);
+
+	pllctl_reg_write(pll, cmd, 1);
+
+	/* Wait until new divider takes effect */
+	while (pllctl_reg_read(pll, stat) & 0x01);
+
+	return __pll_div_freq_get(pll, fpll, div);
+}
+
+unsigned long clk_get_rate(unsigned int clk)
+{
+	return pll_div_freq_get(lpsc_clk_map[clk].pll, lpsc_clk_map[clk].div);
+}
+
+unsigned long clk_round_rate(unsigned int clk, unsigned long hz)
+{
+	unsigned long fpll, divider, pll;
+
+	pll = lpsc_clk_map[clk].pll;
+	fpll = pll_freq_get(pll);
+	divider = (fpll / hz - 1);
+	divider &= pll_div_mask[pll];
+
+	return fpll / (divider + 1);
+}
+
+int clk_set_rate(unsigned int clk, unsigned long _hz)
+{
+	unsigned long hz;
+
+	hz = clk_round_rate(clk, _hz);
+	if (hz != _hz)
+		return -EINVAL;	/* Cannot set to target freq */
+
+	pll_div_freq_set(lpsc_clk_map[clk].pll, lpsc_clk_map[clk].div, hz);
+	return 0;
+}
+
+void lpsc_control(int mod, unsigned long state, int lrstz)
+{
+	u32 mdctl;
+
+	mdctl = psc_reg_read(PSC_MDCTL(mod));
+	mdctl &= ~0x1f;
+	mdctl |= state;
+
+	if (lrstz == 0)
+		mdctl &= ~PSC_MDCTL_LRSTZ;
+	else if (lrstz == 1)
+		mdctl |= PSC_MDCTL_LRSTZ;
+
+	psc_reg_write(PSC_MDCTL(mod), mdctl);
+
+	psc_reg_write(PSC_PTCMD, 1);
+
+	/* wait for power domain transition to end */
+	while (psc_reg_read(PSC_PTSTAT) & 1);
+
+	/* Wait for module state change */
+	while ((psc_reg_read(PSC_MDSTAT(mod)) & 0x1f) != state);
+}
+
+int lpsc_status(unsigned int id)
+{
+	return psc_reg_read(PSC_MDSTAT(id)) & 0x1f;
+}
+
+static void init_pll(const struct pll_init_data *data)
+{
+	unsigned long fpll;
+	unsigned long best_pre = 0, best_post = 0, best_mult = 0;
+	unsigned long div, prediv, postdiv, mult;
+	unsigned long delta, actual;
+	long best_delta = -1;
+	int i;
+	u32 tmp;
+
+	if (data->pll == SYS_PLL)
+		return; /* cannot reconfigure system pll on the fly */
+
+	tmp = pllctl_reg_read(data->pll, ctl);
+	if (data->internal_osc) {
+		tmp &= ~PLLCTL_CLKMODE;
+		fpll = CONFIG_SYS_INT_OSC_FREQ;
+	} else {
+		tmp |= PLLCTL_CLKMODE;
+		fpll = pll_ext_freq[data->pll];
+	}
+	pllctl_reg_write(data->pll, ctl, tmp);
+
+	mult = data->pll_freq / fpll;
+	for (mult = MAX(mult, 1); mult <= MAX_MULT; mult++) {
+		div = (fpll * mult) / data->pll_freq;
+		if (div < 1 || div > MAX_DIV)
+			continue;
+
+		for (postdiv = 1; postdiv <= min(div, MAX_POSTDIV); postdiv++) {
+			prediv = div / postdiv;
+			if (prediv < 1 || prediv > MAX_PREDIV)
+				continue;
+
+			actual = (fpll / prediv) * (mult / postdiv);
+			delta = (actual - data->pll_freq);
+			if (delta < 0)
+				delta = -delta;
+			if ((delta < best_delta) || (best_delta == -1)) {
+				best_delta = delta;
+				best_mult = mult;
+				best_pre = prediv;
+				best_post = postdiv;
+				if (delta == 0)
+					goto done;
+			}
+		}
+	}
+done:
+
+	if (best_delta == -1) {
+		printf("pll cannot derive %lu from %lu\n",
+				data->pll_freq, fpll);
+		return;
+	}
+
+	fpll = fpll * best_mult;
+	fpll /= best_pre * best_post;
+
+	pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLENSRC);
+	pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN);
+
+	pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST);
+
+	pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN);
+	pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLDIS);
+
+	sspll_reg_write(data->pll, mult_factor,	(best_mult - 1) << 8);
+	sspll_reg_write(data->pll, prediv,	best_pre - 1);
+	sspll_reg_write(data->pll, postdiv,	best_post - 1);
+
+	for (i = 0; i < 10; i++)
+		if (data->div_freq[i])
+			__pll_div_freq_set(data->pll, fpll, i,
+					   data->div_freq[i]);
+
+	pllctl_reg_write(data->pll, cmd, 1);
+
+	/* Wait until pll "go" operation completes */
+	while (pllctl_reg_read(data->pll, stat) & 0x01);
+
+	pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST);
+	pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN);
+}
+
+void init_plls(int num_pll, struct pll_init_data *config)
+{
+	int i;
+
+	for (i = 0; i < num_pll; i++)
+		init_pll(&config[i]);
+}

arch/arm/cpu/arm1176/tnetv107x/init.c

@@ -0,0 +1,37 @@
+/*
+ * TNETV107X: Architecture initialization
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+void chip_configuration_unlock(void)
+{
+       __raw_writel(TNETV107X_KICK0_MAGIC, TNETV107X_KICK0);
+       __raw_writel(TNETV107X_KICK1_MAGIC, TNETV107X_KICK1);
+}
+
+int arch_cpu_init(void)
+{
+       icache_enable();
+       chip_configuration_unlock();
+
+       return 0;
+}

arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S

@@ -0,0 +1,25 @@
+/*
+ * TNETV107X: Low-level pre-relocation initialization
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+.globl lowlevel_init
+lowlevel_init:
+	/* nothing for now, maybe needed for more exotic boot modes */
+	mov	pc, lr

arch/arm/cpu/arm1176/tnetv107x/mux.c

@@ -0,0 +1,334 @@
+/*
+ * TNETV107X: Pinmux configuration
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/mux.h>
+
+#define MUX_MODE_1		0x00
+#define MUX_MODE_2		0x04
+#define MUX_MODE_3		0x0c
+#define MUX_MODE_4		0x1c
+
+#define MUX_DEBUG		0
+
+static const struct pin_config pin_table[] = {
+	/*		  reg	shift	mode	*/
+	TNETV107X_MUX_CFG(0,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(0,	0,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(0,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(0,	5,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(0,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(0,	10,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(0,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(0,	15,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(0,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(0,	20,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(0,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(0,	25,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(1,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(1,	0,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(1,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(1,	5,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(1,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(1,	10,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(1,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(1,	15,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(1,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(1,	20,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(1,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(1,	25,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(2,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(2,	0,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(2,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(2,	5,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(2,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(2,	10,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(2,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(2,	15,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(2,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(2,	20,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(2,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(2,	25,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(3,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(3,	0,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(3,	0,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(3,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(3,	5,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(3,	5,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(3,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(3,	10,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(3,	10,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(3,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(3,	15,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(3,	15,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(3,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(3,	20,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(3,	20,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(3,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(3,	25,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(3,	25,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(4,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(4,	0,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(4,	0,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(4,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(4,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(4,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(4,	15,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(4,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(4,	20,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(4,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(4,	25,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(5,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(5,	0,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(5,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(5,	5,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(5,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(5,	10,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(5,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(5,	15,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(5,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(5,	20,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(5,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(5,	25,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(6,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(6,	0,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(6,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(6,	5,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(6,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(6,	10,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(6,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(6,	15,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(6,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(6,	20,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(6,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(6,	25,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(7,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(7,	0,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(7,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(7,	5,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(7,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(7,	10,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(7,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(7,	15,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(7,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(7,	20,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(7,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(7,	25,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(8,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(8,	0,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(8,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(8,	5,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(8,	5,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(8,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(8,	10,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(9,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(9,	0,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(9,	0,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(9,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(9,	5,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(9,	5,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(9,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(9,	10,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(9,	10,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(9,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(9,	15,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(9,	15,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(9,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(9,	20,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(9,	20,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(10,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(10,	0,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(10,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(10,	5,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(10,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(10,	10,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(10,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(10,	15,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(10,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(10,	20,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(10,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(10,	25,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(11,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(11,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(12,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(12,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(12,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(12,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(12,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(12,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(13,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(13,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(13,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(13,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(14,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(14,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(14,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(14,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(14,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(14,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(15,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(15,	0,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(15,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(15,	5,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(15,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(15,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(15,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(15,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(16,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(16,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(16,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(16,	10,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(16,	10,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(16,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(16,	15,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(17,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(17,	0,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(17,	0,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(17,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(17,	5,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(17,	5,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(17,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(17,	10,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(17,	10,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(17,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(17,	15,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(17,	15,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(18,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(18,	0,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(18,	0,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(18,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(18,	5,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(18,	5,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(18,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(18,	10,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(18,	10,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(18,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(18,	15,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(18,	15,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(19,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(19,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(19,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(19,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(19,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(19,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(20,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(20,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(20,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(20,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(20,	15,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(20,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(20,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(21,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(21,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(21,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(21,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(21,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(21,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(22,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(22,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(22,	5,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(22,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(22,	10,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(22,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(22,	15,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(22,	15,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(22,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(22,	20,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(22,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(22,	25,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(23,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(23,	0,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(23,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(23,	5,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(23,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(23,	10,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(24,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(24,	0,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(24,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(24,	5,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(24,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(24,	10,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(24,	10,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(24,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(24,	15,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(24,	15,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(24,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(24,	20,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(24,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(24,	25,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(25,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(25,	0,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(25,	0,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(25,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(25,	5,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(25,	5,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(25,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(25,	10,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(25,	10,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(25,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(25,	15,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(25,	15,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(25,	15,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(26,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(26,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(26,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(26,	10,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(26,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(26,	15,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(26,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(26,	20,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(26,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(26,	25,	MUX_MODE_2),
+};
+
+const int pin_table_size = sizeof(pin_table) / sizeof(pin_table[0]);
+
+int mux_select_pin(short index)
+{
+	const struct pin_config *cfg;
+	unsigned long mask, mode, reg;
+
+	if (index >= pin_table_size)
+		return 0;
+
+	cfg = &pin_table[index];
+
+	mask = 0x1f << cfg->mask_offset;
+	mode = cfg->mode << cfg->mask_offset;
+
+	reg = __raw_readl(TNETV107X_PINMUX(cfg->reg_index));
+	reg = (reg & ~mask) | mode;
+	__raw_writel(reg, TNETV107X_PINMUX(cfg->reg_index));
+
+	return 1;
+}
+
+int mux_select_pins(const short *pins)
+{
+	int i, ret = 1;
+
+	for (i = 0; pins[i] >= 0; i++)
+		ret &= mux_select_pin(pins[i]);
+
+	return ret;
+}

arch/arm/cpu/arm1176/tnetv107x/timer.c

@@ -0,0 +1,122 @@
+/*
+ * TNETV107X: Timer implementation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+
+struct timer_regs {
+	u_int32_t pid12;
+	u_int32_t pad[3];
+	u_int32_t tim12;
+	u_int32_t tim34;
+	u_int32_t prd12;
+	u_int32_t prd34;
+	u_int32_t tcr;
+	u_int32_t tgcr;
+	u_int32_t wdtcr;
+};
+
+#define regs ((struct timer_regs *)CONFIG_SYS_TIMERBASE)
+
+#define TIMER_LOAD_VAL	(CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
+#define TIM_CLK_DIV	16
+
+static ulong timestamp;
+static ulong lastinc;
+
+int timer_init(void)
+{
+	clk_enable(TNETV107X_LPSC_TIMER0);
+
+	lastinc = timestamp = 0;
+
+	/* We are using timer34 in unchained 32-bit mode, full speed */
+	__raw_writel(0x0, &regs->tcr);
+	__raw_writel(0x0, &regs->tgcr);
+	__raw_writel(0x06 | ((TIM_CLK_DIV - 1) << 8), &regs->tgcr);
+	__raw_writel(0x0, &regs->tim34);
+	__raw_writel(TIMER_LOAD_VAL, &regs->prd34);
+	__raw_writel(2 << 22, &regs->tcr);
+
+	return 0;
+}
+
+void reset_timer(void)
+{
+	lastinc = timestamp = 0;
+
+	__raw_writel(0,		&regs->tcr);
+	__raw_writel(0,		&regs->tim34);
+	__raw_writel(2 << 22,	&regs->tcr);
+}
+
+static ulong get_timer_raw(void)
+{
+	ulong now = __raw_readl(&regs->tim34);
+
+	if (now >= lastinc)
+		timestamp += now - lastinc;
+	else
+		timestamp += now + TIMER_LOAD_VAL - lastinc;
+
+	lastinc = now;
+
+	return timestamp;
+}
+
+ulong get_timer(ulong base)
+{
+	return (get_timer_raw() / (TIMER_LOAD_VAL / TIM_CLK_DIV)) - base;
+}
+
+void set_timer(ulong t)
+{
+	timestamp = t;
+}
+
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+void __udelay(unsigned long usec)
+{
+	ulong tmo;
+	ulong endtime;
+	signed long diff;
+
+	tmo = CONFIG_SYS_HZ_CLOCK / 1000;
+	tmo *= usec;
+	tmo /= (1000 * TIM_CLK_DIV);
+
+	endtime = get_timer_raw() + tmo;
+
+	do {
+		ulong now = get_timer_raw();
+		diff = endtime - now;
+	} while (diff >= 0);
+}
+
+ulong get_tbclk(void)
+{
+	return CONFIG_SYS_HZ;
+}

arch/arm/cpu/arm1176/tnetv107x/wdt.c

@@ -0,0 +1,180 @@
+/*
+ * TNETV107X: Watchdog timer implementation (for reset)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+
+#define MAX_DIV		0xFFFE0001
+
+struct wdt_regs {
+	u32 kick_lock;
+#define KICK_LOCK_1	0x5555
+#define KICK_LOCK_2	0xaaaa
+	u32 kick;
+
+	u32 change_lock;
+#define CHANGE_LOCK_1	0x6666
+#define CHANGE_LOCK_2	0xbbbb
+	u32 change;
+
+	u32 disable_lock;
+#define DISABLE_LOCK_1	0x7777
+#define DISABLE_LOCK_2	0xcccc
+#define DISABLE_LOCK_3	0xdddd
+	u32 disable;
+
+	u32 prescale_lock;
+#define PRESCALE_LOCK_1	0x5a5a
+#define PRESCALE_LOCK_2	0xa5a5
+	u32 prescale;
+};
+
+static struct wdt_regs* regs = (struct wdt_regs *)TNETV107X_WDT0_ARM_BASE;
+
+#define wdt_reg_read(reg)	__raw_readl(&regs->reg)
+#define wdt_reg_write(reg, val)	__raw_writel((val), &regs->reg)
+
+static int write_prescale_reg(unsigned long prescale_value)
+{
+	wdt_reg_write(prescale_lock, PRESCALE_LOCK_1);
+	if ((wdt_reg_read(prescale_lock) & 0x3) != 0x1)
+		return -1;
+
+	wdt_reg_write(prescale_lock, PRESCALE_LOCK_2);
+	if ((wdt_reg_read(prescale_lock) & 0x3) != 0x3)
+		return -1;
+
+	wdt_reg_write(prescale, prescale_value);
+
+	return 0;
+}
+
+static int write_change_reg(unsigned long initial_timer_value)
+{
+	wdt_reg_write(change_lock, CHANGE_LOCK_1);
+	if ((wdt_reg_read(change_lock) & 0x3) != 0x1)
+		return -1;
+
+	wdt_reg_write(change_lock, CHANGE_LOCK_2);
+	if ((wdt_reg_read(change_lock) & 0x3) != 0x3)
+		return -1;
+
+	wdt_reg_write(change, initial_timer_value);
+
+	return 0;
+}
+
+static int wdt_control(unsigned long disable_value)
+{
+	wdt_reg_write(disable_lock, DISABLE_LOCK_1);
+	if ((wdt_reg_read(disable_lock) & 0x3) != 0x1)
+		return -1;
+
+	wdt_reg_write(disable_lock, DISABLE_LOCK_2);
+	if ((wdt_reg_read(disable_lock) & 0x3) != 0x2)
+		return -1;
+
+	wdt_reg_write(disable_lock, DISABLE_LOCK_3);
+	if ((wdt_reg_read(disable_lock) & 0x3) != 0x3)
+		return -1;
+
+	wdt_reg_write(disable, disable_value);
+	return 0;
+}
+
+static int wdt_set_period(unsigned long msec)
+{
+	unsigned long change_value, count_value;
+	unsigned long prescale_value = 1;
+	unsigned long refclk_khz, maxdiv;
+	int ret;
+
+	refclk_khz = clk_get_rate(TNETV107X_LPSC_WDT_ARM);
+	maxdiv = (MAX_DIV / refclk_khz);
+
+	if ((!msec) || (msec > maxdiv))
+		return -1;
+
+	count_value = refclk_khz * msec;
+	if (count_value > 0xffff) {
+		change_value = count_value / 0xffff + 1;
+		prescale_value = count_value / change_value;
+	} else {
+		change_value = count_value;
+	}
+
+	ret = write_prescale_reg(prescale_value - 1);
+	if (ret)
+		return ret;
+
+	ret = write_change_reg(change_value);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+unsigned long last_wdt = -1;
+
+int wdt_start(unsigned long msecs)
+{
+	int ret;
+	ret = wdt_control(0);
+	if (ret)
+		return ret;
+	ret = wdt_set_period(msecs);
+	if (ret)
+		return ret;
+	ret = wdt_control(1);
+	if (ret)
+		return ret;
+	ret = wdt_kick();
+	last_wdt = msecs;
+	return ret;
+}
+
+int wdt_stop(void)
+{
+	last_wdt = -1;
+	return wdt_control(0);
+}
+
+int wdt_kick(void)
+{
+	wdt_reg_write(kick_lock, KICK_LOCK_1);
+	if ((wdt_reg_read(kick_lock) & 0x3) != 0x1)
+		return -1;
+
+	wdt_reg_write(kick_lock, KICK_LOCK_2);
+	if ((wdt_reg_read(kick_lock) & 0x3) != 0x3)
+		return -1;
+
+	wdt_reg_write(kick, 1);
+	return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+	clk_enable(TNETV107X_LPSC_WDT_ARM);
+	wdt_start(1);
+	wdt_kick();
+}

arch/arm/cpu/arm1176/u-boot.lds

@@ -0,0 +1,76 @@
+/*
+ * (C) Copyright 2002-2004
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		arch/arm/cpu/arm1176/start.o	(.text)
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : {
+		*(.data)
+	}
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+
+	.rel.dyn : {
+		__rel_dyn_start = .;
+		*(.rel*)
+		__rel_dyn_end = .;
+	}
+
+	.dynsym : {
+		__dynsym_start = .;
+		*(.dynsym)
+	}
+
+	.bss __rel_dyn_start (OVERLAY) : {
+		__bss_start = .;
+		*(.bss)
+		 . = ALIGN(4);
+		_end = .;
+	}
+
+	/DISCARD/ : { *(.dynstr*) }
+	/DISCARD/ : { *(.dynamic*) }
+	/DISCARD/ : { *(.plt*) }
+	/DISCARD/ : { *(.interp*) }
+	/DISCARD/ : { *(.gnu*) }
+}

arch/arm/cpu/arm720t/Makefile

@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(CPU).o
+
+START	= start.o
+COBJS	= interrupts.o cpu.o
+
+SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+START	:= $(addprefix $(obj),$(START))
+
+all:	$(obj).depend $(START) $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

arch/arm/cpu/arm720t/lpc2292/Makefile

@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2000-2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).o
+
+COBJS	= flash.o mmc.o mmc_hw.o spi.o
+SOBJS	= $(obj)iap_entry.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+# this MUST be compiled as thumb code!
+$(SOBJS):
+	$(CC) $(AFLAGS) -march=armv4t -c -o $(SOBJS) iap_entry.S
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

arch/arm/cpu/arm720t/s3c4510b/Makefile

@@ -0,0 +1,45 @@
+#
+# (C) Copyright 2000-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).o
+
+COBJS-y	+= cache.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

arch/arm/cpu/arm720t/start.S

@@ -0,0 +1,678 @@
+/*
+ *  armboot - Startup Code for ARM720 CPU-core
+ *
+ *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
+ *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <version.h>
+#include <asm/hardware.h>
+
+/*
+ *************************************************************************
+ *
+ * Jump vector table as in table 3.1 in [1]
+ *
+ *************************************************************************
+ */
+
+
+.globl _start
+_start: b	reset
+	ldr	pc, _undefined_instruction
+	ldr	pc, _software_interrupt
+	ldr	pc, _prefetch_abort
+	ldr	pc, _data_abort
+#ifdef CONFIG_LPC2292
+	.word	0xB4405F76 /* 2's complement of the checksum of the vectors */
+#else
+	ldr	pc, _not_used
+#endif
+	ldr	pc, _irq
+	ldr	pc, _fiq
+
+_undefined_instruction: .word undefined_instruction
+_software_interrupt:	.word software_interrupt
+_prefetch_abort:	.word prefetch_abort
+_data_abort:		.word data_abort
+_not_used:		.word not_used
+_irq:			.word irq
+_fiq:			.word fiq
+
+	.balignl 16,0xdeadbeef
+
+
+/*
+ *************************************************************************
+ *
+ * Startup Code (reset vector)
+ *
+ * do important init only if we don't start from RAM!
+ * relocate armboot to ram
+ * setup stack
+ * jump to second stage
+ *
+ *************************************************************************
+ */
+
+.globl _TEXT_BASE
+_TEXT_BASE:
+	.word	CONFIG_SYS_TEXT_BASE
+
+/*
+ * These are defined in the board-specific linker script.
+ * Subtracting _start from them lets the linker put their
+ * relative position in the executable instead of leaving
+ * them null.
+ */
+.globl _bss_start_ofs
+_bss_start_ofs:
+	.word __bss_start - _start
+
+.globl _bss_end_ofs
+_bss_end_ofs:
+	.word _end - _start
+
+#ifdef CONFIG_USE_IRQ
+/* IRQ stack memory (calculated at run-time) */
+.globl IRQ_STACK_START
+IRQ_STACK_START:
+	.word	0x0badc0de
+
+/* IRQ stack memory (calculated at run-time) */
+.globl FIQ_STACK_START
+FIQ_STACK_START:
+	.word 0x0badc0de
+#endif
+
+/* IRQ stack memory (calculated at run-time) + 8 bytes */
+.globl IRQ_STACK_START_IN
+IRQ_STACK_START_IN:
+	.word	0x0badc0de
+
+/*
+ * the actual reset code
+ */
+
+reset:
+	/*
+	 * set the cpu to SVC32 mode
+	 */
+	mrs	r0,cpsr
+	bic	r0,r0,#0x1f
+	orr	r0,r0,#0xd3
+	msr	cpsr,r0
+
+	/*
+	 * we do sys-critical inits only at reboot,
+	 * not when booting from ram!
+	 */
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+	bl	cpu_init_crit
+#endif
+
+#ifdef CONFIG_LPC2292
+	bl	lowlevel_init
+#endif
+
+/* Set stackpointer in internal RAM to call board_init_f */
+call_board_init_f:
+	ldr	sp, =(CONFIG_SYS_INIT_SP_ADDR)
+	ldr	r0,=0x00000000
+	bl	board_init_f
+
+/*------------------------------------------------------------------------------*/
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ */
+	.globl	relocate_code
+relocate_code:
+	mov	r4, r0	/* save addr_sp */
+	mov	r5, r1	/* save addr of gd */
+	mov	r6, r2	/* save addr of destination */
+	mov	r7, r2	/* save addr of destination */
+
+	/* Set up the stack						    */
+stack_setup:
+	mov	sp, r4
+
+	adr	r0, _start
+	ldr	r2, _TEXT_BASE
+	ldr	r3, _bss_start_ofs
+	add	r2, r0, r3		/* r2 <- source end address	    */
+	cmp	r0, r6
+	beq	clear_bss
+
+copy_loop:
+	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
+	stmia	r6!, {r9-r10}		/* copy to   target address [r1]    */
+	cmp	r0, r2			/* until source end address [r2]    */
+	blo	copy_loop
+
+#ifndef CONFIG_PRELOADER
+	/*
+	 * fix .rel.dyn relocations
+	 */
+	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
+	sub	r9, r7, r0		/* r9 <- relocation offset */
+	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
+	add	r10, r10, r0		/* r10 <- sym table in FLASH */
+	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
+	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
+	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
+	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
+fixloop:
+	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
+	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
+	ldr	r1, [r2, #4]
+	and	r8, r1, #0xff
+	cmp	r8, #23			/* relative fixup? */
+	beq	fixrel
+	cmp	r8, #2			/* absolute fixup? */
+	beq	fixabs
+	/* ignore unknown type of fixup */
+	b	fixnext
+fixabs:
+	/* absolute fix: set location to (offset) symbol value */
+	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
+	add	r1, r10, r1		/* r1 <- address of symbol in table */
+	ldr	r1, [r1, #4]		/* r1 <- symbol value */
+	add	r1, r9			/* r1 <- relocated sym addr */
+	b	fixnext
+fixrel:
+	/* relative fix: increase location by offset */
+	ldr	r1, [r0]
+	add	r1, r1, r9
+fixnext:
+	str	r1, [r0]
+	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
+	cmp	r2, r3
+	blo	fixloop
+#endif
+
+clear_bss:
+#ifndef CONFIG_PRELOADER
+	ldr	r0, _bss_start_ofs
+	ldr	r1, _bss_end_ofs
+	ldr	r3, _TEXT_BASE		/* Text base */
+	mov	r4, r7			/* reloc addr */
+	add	r0, r0, r4
+	add	r1, r1, r4
+	mov	r2, #0x00000000		/* clear			    */
+
+clbss_l:str	r2, [r0]		/* clear loop...		    */
+	add	r0, r0, #4
+	cmp	r0, r1
+	bne	clbss_l
+
+	bl coloured_LED_init
+	bl red_LED_on
+#endif
+
+/*
+ * We are done. Do not return, instead branch to second part of board
+ * initialization, now running from RAM.
+ */
+	ldr	r0, _board_init_r_ofs
+	adr	r1, _start
+	add	lr, r0, r1
+	add	lr, lr, r9
+	/* setup parameters for board_init_r */
+	mov	r0, r5		/* gd_t */
+	mov	r1, r7		/* dest_addr */
+	/* jump to it ... */
+	mov	pc, lr
+
+_board_init_r_ofs:
+	.word board_init_r - _start
+
+_rel_dyn_start_ofs:
+	.word __rel_dyn_start - _start
+_rel_dyn_end_ofs:
+	.word __rel_dyn_end - _start
+_dynsym_start_ofs:
+	.word __dynsym_start - _start
+
+/*
+ *************************************************************************
+ *
+ * CPU_init_critical registers
+ *
+ * setup important registers
+ * setup memory timing
+ *
+ *************************************************************************
+ */
+
+#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
+
+/* Interupt-Controller base addresses */
+INTMR1:		.word	0x80000280 @ 32 bit size
+INTMR2:		.word	0x80001280 @ 16 bit size
+INTMR3:		.word	0x80002280 @  8 bit size
+
+/* SYSCONs */
+SYSCON1:	.word	0x80000100
+SYSCON2:	.word	0x80001100
+SYSCON3:	.word	0x80002200
+
+#define CLKCTL	       0x6  /* mask */
+#define CLKCTL_18      0x0  /* 18.432 MHz */
+#define CLKCTL_36      0x2  /* 36.864 MHz */
+#define CLKCTL_49      0x4  /* 49.152 MHz */
+#define CLKCTL_73      0x6  /* 73.728 MHz */
+
+#elif defined(CONFIG_LPC2292)
+PLLCFG_ADR:	.word	PLLCFG
+PLLFEED_ADR:	.word	PLLFEED
+PLLCON_ADR:	.word	PLLCON
+PLLSTAT_ADR:	.word	PLLSTAT
+VPBDIV_ADR:	.word	VPBDIV
+MEMMAP_ADR:	.word	MEMMAP
+
+#endif
+
+cpu_init_crit:
+#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
+
+	/*
+	 * mask all IRQs by clearing all bits in the INTMRs
+	 */
+	mov	r1, #0x00
+	ldr	r0, INTMR1
+	str	r1, [r0]
+	ldr	r0, INTMR2
+	str	r1, [r0]
+	ldr	r0, INTMR3
+	str	r1, [r0]
+
+	/*
+	 * flush v4 I/D caches
+	 */
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
+	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
+
+	/*
+	 * disable MMU stuff and caches
+	 */
+	mrc	p15,0,r0,c1,c0
+	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
+	bic	r0, r0, #0x0000008f	@ clear bits 7, 3:0 (B--- WCAM)
+	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
+	mcr	p15,0,r0,c1,c0
+#elif defined(CONFIG_NETARM)
+	/*
+	 * prior to software reset : need to set pin PORTC4 to be *HRESET
+	 */
+	ldr	r0, =NETARM_GEN_MODULE_BASE
+	ldr	r1, =(NETARM_GEN_PORT_MODE(0x10) | \
+			NETARM_GEN_PORT_DIR(0x10))
+	str	r1, [r0, #+NETARM_GEN_PORTC]
+	/*
+	 * software reset : see HW Ref. Guide 8.2.4 : Software Service register
+	 *		    for an explanation of this process
+	 */
+	ldr	r0, =NETARM_GEN_MODULE_BASE
+	ldr	r1, =NETARM_GEN_SW_SVC_RESETA
+	str	r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
+	ldr	r1, =NETARM_GEN_SW_SVC_RESETB
+	str	r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
+	ldr	r1, =NETARM_GEN_SW_SVC_RESETA
+	str	r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
+	ldr	r1, =NETARM_GEN_SW_SVC_RESETB
+	str	r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
+	/*
+	 * setup PLL and System Config
+	 */
+	ldr	r0, =NETARM_GEN_MODULE_BASE
+
+	ldr	r1, =(	NETARM_GEN_SYS_CFG_LENDIAN | \
+			NETARM_GEN_SYS_CFG_BUSFULL | \
+			NETARM_GEN_SYS_CFG_USER_EN | \
+			NETARM_GEN_SYS_CFG_ALIGN_ABORT | \
+			NETARM_GEN_SYS_CFG_BUSARB_INT | \
+			NETARM_GEN_SYS_CFG_BUSMON_EN )
+
+	str	r1, [r0, #+NETARM_GEN_SYSTEM_CONTROL]
+
+#ifndef CONFIG_NETARM_PLL_BYPASS
+	ldr	r1, =(	NETARM_GEN_PLL_CTL_PLLCNT(NETARM_PLL_COUNT_VAL) | \
+			NETARM_GEN_PLL_CTL_POLTST_DEF | \
+			NETARM_GEN_PLL_CTL_INDIV(1) | \
+			NETARM_GEN_PLL_CTL_ICP_DEF | \
+			NETARM_GEN_PLL_CTL_OUTDIV(2) )
+	str	r1, [r0, #+NETARM_GEN_PLL_CONTROL]
+#endif
+
+	/*
+	 * mask all IRQs by clearing all bits in the INTMRs
+	 */
+	mov	r1, #0
+	ldr	r0, =NETARM_GEN_MODULE_BASE
+	str	r1, [r0, #+NETARM_GEN_INTR_ENABLE]
+
+#elif defined(CONFIG_S3C4510B)
+
+	/*
+	 * Mask off all IRQ sources
+	 */
+	ldr	r1, =REG_INTMASK
+	ldr	r0, =0x3FFFFF
+	str	r0, [r1]
+
+	/*
+	 * Disable Cache
+	 */
+	ldr r0, =REG_SYSCFG
+	ldr r1, =0x83ffffa0	/* cache-disabled  */
+	str r1, [r0]
+
+#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
+	/* No specific initialisation for IntegratorAP/CM720T as yet */
+#elif defined(CONFIG_LPC2292)
+	/* Set-up PLL */
+	mov	r3, #0xAA
+	mov	r4, #0x55
+	/* First disconnect and disable the PLL */
+	ldr	r0, PLLCON_ADR
+	mov	r1, #0x00
+	str	r1, [r0]
+	ldr	r0, PLLFEED_ADR /* start feed sequence */
+	str	r3, [r0]
+	str	r4, [r0]	/* feed sequence done */
+	/* Set new M and P values */
+	ldr	r0, PLLCFG_ADR
+	mov	r1, #0x23	/* M=4 and P=2 */
+	str	r1, [r0]
+	ldr	r0, PLLFEED_ADR /* start feed sequence */
+	str	r3, [r0]
+	str	r4, [r0]	/* feed sequence done */
+	/* Then enable the PLL */
+	ldr	r0, PLLCON_ADR
+	mov	r1, #0x01	/* PLL enable bit */
+	str	r1, [r0]
+	ldr	r0, PLLFEED_ADR /* start feed sequence */
+	str	r3, [r0]
+	str	r4, [r0]	/* feed sequence done */
+	/* Wait for the lock */
+	ldr	r0, PLLSTAT_ADR
+	mov	r1, #0x400	/* lock bit */
+lock_loop:
+	ldr	r2, [r0]
+	and	r2, r1, r2
+	cmp	r2, #0
+	beq	lock_loop
+	/* And finally connect the PLL */
+	ldr	r0, PLLCON_ADR
+	mov	r1, #0x03	/* PLL enable bit and connect bit */
+	str	r1, [r0]
+	ldr	r0, PLLFEED_ADR /* start feed sequence */
+	str	r3, [r0]
+	str	r4, [r0]	/* feed sequence done */
+	/* Set-up VPBDIV register */
+	ldr	r0, VPBDIV_ADR
+	mov	r1, #0x01	/* VPB clock is same as process clock */
+	str	r1, [r0]
+#else
+#error No cpu_init_crit() defined for current CPU type
+#endif
+
+#ifdef CONFIG_ARM7_REVD
+	/* set clock speed */
+	/* !!! we run @ 36 MHz due to a hardware flaw in Rev. D processors */
+	/* !!! not doing DRAM refresh properly! */
+	ldr	r0, SYSCON3
+	ldr	r1, [r0]
+	bic	r1, r1, #CLKCTL
+	orr	r1, r1, #CLKCTL_36
+	str	r1, [r0]
+#endif
+
+#ifndef CONFIG_LPC2292
+	mov	ip, lr
+	/*
+	 * before relocating, we have to setup RAM timing
+	 * because memory timing is board-dependent, you will
+	 * find a lowlevel_init.S in your board directory.
+	 */
+	bl	lowlevel_init
+	mov	lr, ip
+#endif
+
+	mov	pc, lr
+
+
+/*
+ *************************************************************************
+ *
+ * Interrupt handling
+ *
+ *************************************************************************
+ */
+
+@
+@ IRQ stack frame.
+@
+#define S_FRAME_SIZE	72
+
+#define S_OLD_R0	68
+#define S_PSR		64
+#define S_PC		60
+#define S_LR		56
+#define S_SP		52
+
+#define S_IP		48
+#define S_FP		44
+#define S_R10		40
+#define S_R9		36
+#define S_R8		32
+#define S_R7		28
+#define S_R6		24
+#define S_R5		20
+#define S_R4		16
+#define S_R3		12
+#define S_R2		8
+#define S_R1		4
+#define S_R0		0
+
+#define MODE_SVC 0x13
+#define I_BIT	 0x80
+
+/*
+ * use bad_save_user_regs for abort/prefetch/undef/swi ...
+ * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
+ */
+
+	.macro	bad_save_user_regs
+	sub	sp, sp, #S_FRAME_SIZE
+	stmia	sp, {r0 - r12}			@ Calling r0-r12
+	add	r8, sp, #S_PC
+
+	ldr	r2, IRQ_STACK_START_IN
+	ldmia	r2, {r2 - r4}			@ get pc, cpsr, old_r0
+	add	r0, sp, #S_FRAME_SIZE		@ restore sp_SVC
+
+	add	r5, sp, #S_SP
+	mov	r1, lr
+	stmia	r5, {r0 - r4}			@ save sp_SVC, lr_SVC, pc, cpsr, old_r
+	mov	r0, sp
+	.endm
+
+	.macro	irq_save_user_regs
+	sub	sp, sp, #S_FRAME_SIZE
+	stmia	sp, {r0 - r12}			@ Calling r0-r12
+	add	r8, sp, #S_PC
+	stmdb	r8, {sp, lr}^			@ Calling SP, LR
+	str	lr, [r8, #0]			@ Save calling PC
+	mrs	r6, spsr
+	str	r6, [r8, #4]			@ Save CPSR
+	str	r0, [r8, #8]			@ Save OLD_R0
+	mov	r0, sp
+	.endm
+
+	.macro	irq_restore_user_regs
+	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
+	mov	r0, r0
+	ldr	lr, [sp, #S_PC]			@ Get PC
+	add	sp, sp, #S_FRAME_SIZE
+	subs	pc, lr, #4			@ return & move spsr_svc into cpsr
+	.endm
+
+	.macro get_bad_stack
+	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
+
+	str	lr, [r13]			@ save caller lr / spsr
+	mrs	lr, spsr
+	str	lr, [r13, #4]
+
+	mov	r13, #MODE_SVC			@ prepare SVC-Mode
+	msr	spsr_c, r13
+	mov	lr, pc
+	movs	pc, lr
+	.endm
+
+	.macro get_irq_stack			@ setup IRQ stack
+	ldr	sp, IRQ_STACK_START
+	.endm
+
+	.macro get_fiq_stack			@ setup FIQ stack
+	ldr	sp, FIQ_STACK_START
+	.endm
+
+/*
+ * exception handlers
+ */
+	.align	5
+undefined_instruction:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_undefined_instruction
+
+	.align	5
+software_interrupt:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_software_interrupt
+
+	.align	5
+prefetch_abort:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_prefetch_abort
+
+	.align	5
+data_abort:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_data_abort
+
+	.align	5
+not_used:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_not_used
+
+#ifdef CONFIG_USE_IRQ
+
+	.align	5
+irq:
+	get_irq_stack
+	irq_save_user_regs
+	bl	do_irq
+	irq_restore_user_regs
+
+	.align	5
+fiq:
+	get_fiq_stack
+	/* someone ought to write a more effiction fiq_save_user_regs */
+	irq_save_user_regs
+	bl	do_fiq
+	irq_restore_user_regs
+
+#else
+
+	.align	5
+irq:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_irq
+
+	.align	5
+fiq:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_fiq
+
+#endif
+
+#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
+	.align	5
+.globl reset_cpu
+reset_cpu:
+	mov	ip, #0
+	mcr	p15, 0, ip, c7, c7, 0		@ invalidate cache
+	mcr	p15, 0, ip, c8, c7, 0		@ flush TLB (v4)
+	mrc	p15, 0, ip, c1, c0, 0		@ get ctrl register
+	bic	ip, ip, #0x000f			@ ............wcam
+	bic	ip, ip, #0x2100			@ ..v....s........
+	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
+	mov	pc, r0
+#elif defined(CONFIG_NETARM)
+	.align	5
+.globl reset_cpu
+reset_cpu:
+	ldr	r1, =NETARM_MEM_MODULE_BASE
+	ldr	r0, [r1, #+NETARM_MEM_CS0_BASE_ADDR]
+	ldr	r1, =0xFFFFF000
+	and	r0, r1, r0
+	ldr	r1, =(relocate-CONFIG_SYS_TEXT_BASE)
+	add	r0, r1, r0
+	ldr	r4, =NETARM_GEN_MODULE_BASE
+	ldr	r1, =NETARM_GEN_SW_SVC_RESETA
+	str	r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
+	ldr	r1, =NETARM_GEN_SW_SVC_RESETB
+	str	r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
+	ldr	r1, =NETARM_GEN_SW_SVC_RESETA
+	str	r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
+	ldr	r1, =NETARM_GEN_SW_SVC_RESETB
+	str	r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
+	mov	pc, r0
+#elif defined(CONFIG_S3C4510B)
+/* Nothing done here as reseting the CPU is board specific, depending
+ * on external peripherals such as watchdog timers, etc. */
+#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
+	/* No specific reset actions for IntegratorAP/CM720T as yet */
+#elif defined(CONFIG_LPC2292)
+	.align	5
+.globl reset_cpu
+reset_cpu:
+	mov	pc, r0
+#else
+#error No reset_cpu() defined for current CPU type
+#endif

arch/arm/cpu/arm720t/u-boot.lds

@@ -0,0 +1,77 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		arch/arm/cpu/arm720t/start.o	(.text)
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : {
+	}
+
+	. = ALIGN(4);
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+
+	.rel.dyn : {
+		__rel_dyn_start = .;
+		*(.rel*)
+		__rel_dyn_end = .;
+	}
+
+	.dynsym : {
+		__dynsym_start = .;
+		*(.dynsym)
+	}
+
+	.bss __rel_dyn_start (OVERLAY) : {
+		__bss_start = .;
+		*(.bss)
+		 . = ALIGN(4);
+		_end = .;
+	}
+
+	/DISCARD/ : { *(.dynstr*) }
+	/DISCARD/ : { *(.dynamic*) }
+	/DISCARD/ : { *(.plt*) }
+	/DISCARD/ : { *(.interp*) }
+	/DISCARD/ : { *(.gnu*) }
+}

arch/arm/cpu/arm920t/Makefile

@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(CPU).o
+
+START	= start.o
+
+COBJS-y	+= cpu.o
+COBJS-$(CONFIG_USE_IRQ)	+= interrupts.o
+
+SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y) $(SOBJS))
+START	:= $(addprefix $(obj),$(START))
+
+all:	$(obj).depend $(START) $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

arch/arm/cpu/arm920t/a320/Makefile

@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).o
+
+SOBJS	+= reset.o
+COBJS	+= timer.o
+COBJS	+= ftsmc020.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

arch/arm/cpu/arm920t/a320/timer.c

@@ -0,0 +1,193 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/ftpmu010.h>
+#include <asm/arch/fttmr010.h>
+
+static ulong timestamp;
+static ulong lastdec;
+
+static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE;
+
+#define TIMER_CLOCK	32768
+#define TIMER_LOAD_VAL	0xffffffff
+
+int timer_init(void)
+{
+	unsigned int oscc;
+	unsigned int cr;
+
+	debug("%s()\n", __func__);
+
+	/* disable timers */
+	writel(0, &tmr->cr);
+
+	/*
+	 * use 32768Hz oscillator for RTC, WDT, TIMER
+	 */
+
+	/* enable the 32768Hz oscillator */
+	oscc = readl(&pmu->OSCC);
+	oscc &= ~(FTPMU010_OSCC_OSCL_OFF | FTPMU010_OSCC_OSCL_TRI);
+	writel(oscc, &pmu->OSCC);
+
+	/* wait until ready */
+	while (!(readl(&pmu->OSCC) & FTPMU010_OSCC_OSCL_STABLE))
+		;
+
+	/* select 32768Hz oscillator */
+	oscc = readl(&pmu->OSCC);
+	oscc |= FTPMU010_OSCC_OSCL_RTCLSEL;
+	writel(oscc, &pmu->OSCC);
+
+	/* setup timer */
+	writel(TIMER_LOAD_VAL, &tmr->timer3_load);
+	writel(TIMER_LOAD_VAL, &tmr->timer3_counter);
+	writel(0, &tmr->timer3_match1);
+	writel(0, &tmr->timer3_match2);
+
+	/* we don't want timer to issue interrupts */
+	writel(FTTMR010_TM3_MATCH1 |
+	       FTTMR010_TM3_MATCH2 |
+	       FTTMR010_TM3_OVERFLOW,
+	       &tmr->interrupt_mask);
+
+	cr = readl(&tmr->cr);
+	cr |= FTTMR010_TM3_CLOCK;	/* use external clock */
+	cr |= FTTMR010_TM3_ENABLE;
+	writel(cr, &tmr->cr);
+
+	/* init the timestamp and lastdec value */
+	reset_timer_masked();
+
+	return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+
+/*
+ * reset time
+ */
+void reset_timer_masked(void)
+{
+	/* capure current decrementer value time */
+	lastdec = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
+	timestamp = 0;		/* start "advancing" time stamp from 0 */
+
+	debug("%s(): lastdec = %lx\n", __func__, lastdec);
+}
+
+void reset_timer(void)
+{
+	debug("%s()\n", __func__);
+	reset_timer_masked();
+}
+
+/*
+ * return timer ticks
+ */
+ulong get_timer_masked(void)
+{
+	/* current tick value */
+	ulong now = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
+
+	debug("%s(): now = %lx, lastdec = %lx\n", __func__, now, lastdec);
+
+	if (lastdec >= now) {
+		/*
+		 * normal mode (non roll)
+		 * move stamp fordward with absoulte diff ticks
+		 */
+		timestamp += lastdec - now;
+	} else {
+		/*
+		 * we have overflow of the count down timer
+		 *
+		 * nts = ts + ld + (TLV - now)
+		 * ts=old stamp, ld=time that passed before passing through -1
+		 * (TLV-now) amount of time after passing though -1
+		 * nts = new "advancing time stamp"...it could also roll and
+		 * cause problems.
+		 */
+		timestamp += lastdec + TIMER_LOAD_VAL - now;
+	}
+
+	lastdec = now;
+
+	debug("%s() returns %lx\n", __func__, timestamp);
+
+	return timestamp;
+}
+
+/*
+ * return difference between timer ticks and base
+ */
+ulong get_timer(ulong base)
+{
+	debug("%s(%lx)\n", __func__, base);
+	return get_timer_masked() - base;
+}
+
+void set_timer(ulong t)
+{
+	debug("%s(%lx)\n", __func__, t);
+	timestamp = t;
+}
+
+/* delay x useconds AND preserve advance timestamp value */
+void __udelay(unsigned long usec)
+{
+	long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
+	unsigned long now, last = readl(&tmr->timer3_counter);
+
+	debug("%s(%lu)\n", __func__, usec);
+	while (tmo > 0) {
+		now = readl(&tmr->timer3_counter);
+		if (now > last) /* count down timer overflow */
+			tmo -= TIMER_LOAD_VAL + last - now;
+		else
+			tmo -= last - now;
+		last = now;
+	}
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	debug("%s()\n", __func__);
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	debug("%s()\n", __func__);
+	return CONFIG_SYS_HZ;
+}

arch/arm/cpu/arm920t/at91/Makefile

@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).o
+
+SOBJS	+= lowlevel_init.o
+COBJS	+= reset.o
+COBJS	+= timer.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

arch/arm/cpu/arm920t/at91/lowlevel_init.S

@@ -0,0 +1,164 @@
+/*
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ *		       Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ *
+ * Modified for the at91rm9200dk board by
+ * (C) Copyright 2004
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_mc.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_pio.h>
+
+#define ARM920T_CONTROL	0xC0000000	/* @ set bit 31 (iA) and 30 (nF) */
+
+_MTEXT_BASE:
+#undef START_FROM_MEM
+#ifdef START_FROM_MEM
+	.word	CONFIG_SYS_TEXT_BASE-PHYS_FLASH_1
+#else
+	.word	CONFIG_SYS_TEXT_BASE
+#endif
+
+.globl lowlevel_init
+lowlevel_init:
+	ldr     r1, =AT91_ASM_PMC_MOR
+	/* Main oscillator Enable register */
+#ifdef CONFIG_SYS_USE_MAIN_OSCILLATOR
+	ldr     r0, =0x0000FF01		/* Enable main oscillator */
+#else
+	ldr     r0, =0x0000FF00		/* Disable main oscillator */
+#endif
+	str     r0, [r1] /*AT91C_CKGR_MOR] */
+	/* Add loop to compensate Main Oscillator startup time */
+	ldr     r0, =0x00000010
+LoopOsc:
+	subs    r0, r0, #1
+	bhi     LoopOsc
+
+	/* memory control configuration */
+	/* this isn't very elegant, but	 what the heck */
+	ldr	r0, =SMRDATA
+	ldr	r1, _MTEXT_BASE
+	sub	r0, r0, r1
+	add	r2, r0, #80
+pllloop:
+	/* the address */
+	ldr	r1, [r0], #4
+	/* the value */
+	ldr	r3, [r0], #4
+	str	r3, [r1]
+	cmp	r2, r0
+	bne	pllloop
+	/* delay - this is all done by guess */
+	ldr	r0, =0x00010000
+	/* (vs reading PMC_SR for LOCKA, LOCKB ... or MOSCS earlier) */
+lock:
+	subs	r0, r0, #1
+	bhi	lock
+	ldr	r0, =SMRDATA1
+	ldr	r1, _MTEXT_BASE
+	sub	r0, r0, r1
+	add	r2, r0, #176
+sdinit:
+	/* the address */
+	ldr	r1, [r0], #4
+	/* the value */
+	ldr	r3, [r0], #4
+	str	r3, [r1]
+	cmp	r2, r0
+	bne	sdinit
+
+	/* switch from FastBus to Asynchronous clock mode */
+	mrc	p15, 0, r0, c1, c0, 0
+	orr	r0, r0, #ARM920T_CONTROL
+	mcr	p15, 0, r0, c1, c0, 0
+
+	/* everything is fine now */
+	mov	pc, lr
+
+	.ltorg
+
+SMRDATA:
+	.word AT91_ASM_MC_EBI_CFG
+	.word CONFIG_SYS_EBI_CFGR_VAL
+	.word AT91_ASM_MC_SMC_CSR0
+	.word CONFIG_SYS_SMC_CSR0_VAL
+	.word AT91_ASM_PMC_PLLAR
+	.word CONFIG_SYS_PLLAR_VAL
+	.word AT91_ASM_PMC_PLLBR
+	.word CONFIG_SYS_PLLBR_VAL
+	.word AT91_ASM_PMC_MCKR
+	.word CONFIG_SYS_MCKR_VAL
+	/* here there's a delay */
+SMRDATA1:
+	.word AT91_ASM_PIOC_ASR
+	.word CONFIG_SYS_PIOC_ASR_VAL
+	.word AT91_ASM_PIOC_BSR
+	.word CONFIG_SYS_PIOC_BSR_VAL
+	.word AT91_ASM_PIOC_PDR
+	.word CONFIG_SYS_PIOC_PDR_VAL
+	.word AT91_ASM_MC_EBI_CSA
+	.word CONFIG_SYS_EBI_CSA_VAL
+	.word AT91_ASM_MC_SDRAMC_CR
+	.word CONFIG_SYS_SDRC_CR_VAL
+	.word AT91_ASM_MC_SDRAMC_MR
+	.word CONFIG_SYS_SDRC_MR_VAL
+	.word CONFIG_SYS_SDRAM
+	.word CONFIG_SYS_SDRAM_VAL
+	.word AT91_ASM_MC_SDRAMC_MR
+	.word CONFIG_SYS_SDRC_MR_VAL1
+	.word CONFIG_SYS_SDRAM
+	.word CONFIG_SYS_SDRAM_VAL
+	.word CONFIG_SYS_SDRAM
+	.word CONFIG_SYS_SDRAM_VAL
+	.word CONFIG_SYS_SDRAM
+	.word CONFIG_SYS_SDRAM_VAL
+	.word CONFIG_SYS_SDRAM
+	.word CONFIG_SYS_SDRAM_VAL
+	.word CONFIG_SYS_SDRAM
+	.word CONFIG_SYS_SDRAM_VAL
+	.word CONFIG_SYS_SDRAM
+	.word CONFIG_SYS_SDRAM_VAL
+	.word CONFIG_SYS_SDRAM
+	.word CONFIG_SYS_SDRAM_VAL
+	.word CONFIG_SYS_SDRAM
+	.word CONFIG_SYS_SDRAM_VAL
+	.word AT91_ASM_MC_SDRAMC_MR
+	.word CONFIG_SYS_SDRC_MR_VAL2
+	.word CONFIG_SYS_SDRAM1
+	.word CONFIG_SYS_SDRAM_VAL
+	.word AT91_ASM_MC_SDRAMC_TR
+	.word CONFIG_SYS_SDRC_TR_VAL
+	.word CONFIG_SYS_SDRAM
+	.word CONFIG_SYS_SDRAM_VAL
+	.word AT91_ASM_MC_SDRAMC_MR
+	.word CONFIG_SYS_SDRC_MR_VAL3
+	.word CONFIG_SYS_SDRAM
+	.word CONFIG_SYS_SDRAM_VAL
+	/* SMRDATA1 is 176 bytes long */
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */

arch/arm/cpu/arm920t/at91rm9200/Makefile

@@ -0,0 +1,56 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).o
+
+SOBJS	+= lowlevel_init.o
+
+COBJS	+= bcm5221.o
+COBJS	+= dm9161.o
+COBJS	+= ether.o
+COBJS	+= i2c.o
+COBJS-$(CONFIG_KS8721_PHY)	+= ks8721.o
+COBJS	+= lxt972.o
+COBJS	+= reset.o
+COBJS	+= spi.o
+COBJS	+= timer.o
+COBJS	+= usb.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS) $(COBJS-y))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

arch/arm/cpu/arm920t/at91rm9200/ether.c

@@ -0,0 +1,316 @@
+/*
+ * (C) Copyright 2003
+ * Author : Hamid Ikdoumi (Atmel)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <at91rm9200_net.h>
+#include <net.h>
+#include <miiphy.h>
+#include <asm/mach-types.h>
+
+/* ----- Ethernet Buffer definitions ----- */
+
+typedef struct {
+	unsigned long addr, size;
+} rbf_t;
+
+#define RBF_ADDR      0xfffffffc
+#define RBF_OWNER     (1<<0)
+#define RBF_WRAP      (1<<1)
+#define RBF_BROADCAST (1<<31)
+#define RBF_MULTICAST (1<<30)
+#define RBF_UNICAST   (1<<29)
+#define RBF_EXTERNAL  (1<<28)
+#define RBF_UNKOWN    (1<<27)
+#define RBF_SIZE      0x07ff
+#define RBF_LOCAL4    (1<<26)
+#define RBF_LOCAL3    (1<<25)
+#define RBF_LOCAL2    (1<<24)
+#define RBF_LOCAL1    (1<<23)
+
+#define RBF_FRAMEMAX 64
+#define RBF_FRAMELEN 0x600
+
+#ifdef CONFIG_DRIVER_ETHER
+
+#if defined(CONFIG_CMD_NET)
+
+/* alignment as per Errata #11 (64 bytes) is insufficient! */
+rbf_t rbfdt[RBF_FRAMEMAX] __attribute__((aligned(512)));
+rbf_t *rbfp;
+
+unsigned char rbf_framebuf[RBF_FRAMEMAX][RBF_FRAMELEN]
+	__attribute__((aligned(4)));
+
+/* structure to interface the PHY */
+AT91S_PhyOps PhyOps;
+
+AT91PS_EMAC p_mac;
+
+/*********** EMAC Phy layer Management functions *************************/
+/*
+ * Name:
+ *	at91rm9200_EmacEnableMDIO
+ * Description:
+ *	Enables the MDIO bit in MAC control register
+ * Arguments:
+ *	p_mac - pointer to struct AT91S_EMAC
+ * Return value:
+ *	none
+ */
+void at91rm9200_EmacEnableMDIO (AT91PS_EMAC p_mac)
+{
+	/* Mac CTRL reg set for MDIO enable */
+	p_mac->EMAC_CTL |= AT91C_EMAC_MPE;	/* Management port enable */
+}
+
+/*
+ * Name:
+ *	at91rm9200_EmacDisableMDIO
+ * Description:
+ *	Disables the MDIO bit in MAC control register
+ * Arguments:
+ *	p_mac - pointer to struct AT91S_EMAC
+ * Return value:
+ *	none
+ */
+void at91rm9200_EmacDisableMDIO (AT91PS_EMAC p_mac)
+{
+	/* Mac CTRL reg set for MDIO disable */
+	p_mac->EMAC_CTL &= ~AT91C_EMAC_MPE;	/* Management port disable */
+}
+
+
+/*
+ * Name:
+ *	at91rm9200_EmacReadPhy
+ * Description:
+ *	Reads data from the PHY register
+ * Arguments:
+ *	dev - pointer to struct net_device
+ *	RegisterAddress - unsigned char
+ *	pInput - pointer to value read from register
+ * Return value:
+ *	TRUE - if data read successfully
+ */
+UCHAR at91rm9200_EmacReadPhy (AT91PS_EMAC p_mac,
+				     unsigned char RegisterAddress,
+				     unsigned short *pInput)
+{
+	p_mac->EMAC_MAN = (AT91C_EMAC_HIGH & ~AT91C_EMAC_LOW) |
+			  (AT91C_EMAC_RW_R) |
+			  (RegisterAddress << 18) |
+			  (AT91C_EMAC_CODE_802_3);
+
+	udelay (10000);
+
+	*pInput = (unsigned short) p_mac->EMAC_MAN;
+
+	return TRUE;
+}
+
+
+/*
+ * Name:
+ *	at91rm9200_EmacWritePhy
+ * Description:
+ *	Writes data to the PHY register
+ * Arguments:
+ *	dev - pointer to struct net_device
+ *	RegisterAddress - unsigned char
+ *	pOutput - pointer to value to be written in the register
+ * Return value:
+ *	TRUE - if data read successfully
+ */
+UCHAR at91rm9200_EmacWritePhy (AT91PS_EMAC p_mac,
+				      unsigned char RegisterAddress,
+				      unsigned short *pOutput)
+{
+	p_mac->EMAC_MAN = (AT91C_EMAC_HIGH & ~AT91C_EMAC_LOW) |
+			AT91C_EMAC_CODE_802_3 | AT91C_EMAC_RW_W |
+			(RegisterAddress << 18) | *pOutput;
+
+	udelay (10000);
+
+	return TRUE;
+}
+
+int eth_init (bd_t * bd)
+{
+	int ret;
+	int i;
+	uchar enetaddr[6];
+
+	p_mac = AT91C_BASE_EMAC;
+
+	/* PIO Disable Register */
+	*AT91C_PIOA_PDR = AT91C_PA16_EMDIO | AT91C_PA15_EMDC | AT91C_PA14_ERXER |
+			  AT91C_PA13_ERX1 | AT91C_PA12_ERX0 | AT91C_PA11_ECRS_ECRSDV |
+			  AT91C_PA10_ETX1 | AT91C_PA9_ETX0 | AT91C_PA8_ETXEN |
+			  AT91C_PA7_ETXCK_EREFCK;
+
+#ifdef CONFIG_AT91C_USE_RMII
+	*AT91C_PIOB_PDR = AT91C_PB19_ERXCK;
+	*AT91C_PIOB_BSR = AT91C_PB19_ERXCK;
+#else
+	*AT91C_PIOB_PDR = AT91C_PB19_ERXCK | AT91C_PB18_ECOL | AT91C_PB17_ERXDV |
+			  AT91C_PB16_ERX3 | AT91C_PB15_ERX2 | AT91C_PB14_ETXER |
+			  AT91C_PB13_ETX3 | AT91C_PB12_ETX2;
+
+	/* Select B Register */
+	*AT91C_PIOB_BSR = AT91C_PB19_ERXCK | AT91C_PB18_ECOL |
+			  AT91C_PB17_ERXDV | AT91C_PB16_ERX3 | AT91C_PB15_ERX2 |
+			  AT91C_PB14_ETXER | AT91C_PB13_ETX3 | AT91C_PB12_ETX2;
+#endif
+
+	*AT91C_PMC_PCER = 1 << AT91C_ID_EMAC;	/* Peripheral Clock Enable Register */
+
+	p_mac->EMAC_CFG |= AT91C_EMAC_CSR;	/* Clear statistics */
+
+	/* Init Ethernet buffers */
+	for (i = 0; i < RBF_FRAMEMAX; i++) {
+		rbfdt[i].addr = (unsigned long)rbf_framebuf[i];
+		rbfdt[i].size = 0;
+	}
+	rbfdt[RBF_FRAMEMAX - 1].addr |= RBF_WRAP;
+	rbfp = &rbfdt[0];
+
+	eth_getenv_enetaddr("ethaddr", enetaddr);
+
+	/* The CSB337 originally used a version of the MicroMonitor bootloader
+	 * which saved Ethernet addresses in the "wrong" order.  Operating
+	 * systems (like Linux) know this, and apply a workaround.  Replicate
+	 * that MicroMonitor behavior so we avoid needing to make such OS code
+	 * care about which bootloader was used.
+	 */
+	if (machine_is_csb337()) {
+		p_mac->EMAC_SA2H = (enetaddr[0] <<  8) | (enetaddr[1]);
+		p_mac->EMAC_SA2L = (enetaddr[2] << 24) | (enetaddr[3] << 16)
+				 | (enetaddr[4] <<  8) | (enetaddr[5]);
+	} else {
+		p_mac->EMAC_SA2L = (enetaddr[3] << 24) | (enetaddr[2] << 16)
+				 | (enetaddr[1] <<  8) | (enetaddr[0]);
+		p_mac->EMAC_SA2H = (enetaddr[5] <<  8) | (enetaddr[4]);
+	}
+
+	p_mac->EMAC_RBQP = (long) (&rbfdt[0]);
+	p_mac->EMAC_RSR &= ~(AT91C_EMAC_RSR_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA);
+
+	p_mac->EMAC_CFG = (p_mac->EMAC_CFG | AT91C_EMAC_CAF | AT91C_EMAC_NBC)
+			& ~AT91C_EMAC_CLK;
+
+#ifdef CONFIG_AT91C_USE_RMII
+	p_mac->EMAC_CFG |= AT91C_EMAC_RMII;
+#endif
+
+#if (AT91C_MASTER_CLOCK > 40000000)
+	/* MDIO clock must not exceed 2.5 MHz, so enable MCK divider */
+	p_mac->EMAC_CFG |= AT91C_EMAC_CLK_HCLK_64;
+#endif
+
+	p_mac->EMAC_CTL |= AT91C_EMAC_TE | AT91C_EMAC_RE;
+
+	at91rm9200_GetPhyInterface (& PhyOps);
+
+	if (!PhyOps.IsPhyConnected (p_mac))
+		printf ("PHY not connected!!\n\r");
+
+	/* MII management start from here */
+	if (!(p_mac->EMAC_SR & AT91C_EMAC_LINK)) {
+		if (!(ret = PhyOps.Init (p_mac))) {
+			printf ("MAC: error during MII initialization\n");
+			return 0;
+		}
+	} else {
+		printf ("No link\n\r");
+		return 0;
+	}
+
+	return 0;
+}
+
+int eth_send (volatile void *packet, int length)
+{
+	while (!(p_mac->EMAC_TSR & AT91C_EMAC_BNQ));
+	p_mac->EMAC_TAR = (long) packet;
+	p_mac->EMAC_TCR = length;
+	while (p_mac->EMAC_TCR & 0x7ff);
+	p_mac->EMAC_TSR |= AT91C_EMAC_COMP;
+	return 0;
+}
+
+int eth_rx (void)
+{
+	int size;
+
+	if (!(rbfp->addr & RBF_OWNER))
+		return 0;
+
+	size = rbfp->size & RBF_SIZE;
+	NetReceive ((volatile uchar *) (rbfp->addr & RBF_ADDR), size);
+
+	rbfp->addr &= ~RBF_OWNER;
+	if (rbfp->addr & RBF_WRAP)
+		rbfp = &rbfdt[0];
+	else
+		rbfp++;
+
+	p_mac->EMAC_RSR |= AT91C_EMAC_REC;
+
+	return size;
+}
+
+void eth_halt (void)
+{
+};
+
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
+int  at91rm9200_miiphy_read(const char *devname, unsigned char addr,
+		unsigned char reg, unsigned short * value)
+{
+	at91rm9200_EmacEnableMDIO (p_mac);
+	at91rm9200_EmacReadPhy (p_mac, reg, value);
+	at91rm9200_EmacDisableMDIO (p_mac);
+	return 0;
+}
+
+int  at91rm9200_miiphy_write(const char *devname, unsigned char addr,
+		unsigned char reg, unsigned short value)
+{
+	at91rm9200_EmacEnableMDIO (p_mac);
+	at91rm9200_EmacWritePhy (p_mac, reg, &value);
+	at91rm9200_EmacDisableMDIO (p_mac);
+	return 0;
+}
+
+#endif
+
+int at91rm9200_miiphy_initialize(bd_t *bis)
+{
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
+	miiphy_register("at91rm9200phy", at91rm9200_miiphy_read, at91rm9200_miiphy_write);
+#endif
+	return 0;
+}
+
+#endif
+
+#endif	/* CONFIG_DRIVER_ETHER */

arch/arm/cpu/arm920t/at91rm9200/lowlevel_init.S

@@ -0,0 +1,169 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ *		       Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ *
+ * Modified for the at91rm9200dk board by
+ * (C) Copyright 2004
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+/*
+ * some parameters for the board
+ *
+ * This is based on rm9200dk.cfg for the BDI2000 from ABATRON which in
+ * turn is based on the boot.bin code from ATMEL
+ *
+ */
+#include <asm/arch/AT91RM9200.h>
+
+_MTEXT_BASE:
+#undef START_FROM_MEM
+#ifdef START_FROM_MEM
+	.word	CONFIG_SYS_TEXT_BASE-PHYS_FLASH_1
+#else
+	.word	CONFIG_SYS_TEXT_BASE
+#endif
+
+.globl lowlevel_init
+lowlevel_init:
+	/* Get the CKGR Base Address */
+	ldr     r1, =AT91C_BASE_CKGR
+	/* Main oscillator Enable register */
+#ifdef CONFIG_SYS_USE_MAIN_OSCILLATOR
+	ldr     r0, =0x0000FF01		/* Enable main oscillator,  OSCOUNT = 0xFF */
+#else
+	ldr     r0, =0x0000FF00		/* Disable main oscillator, OSCOUNT = 0xFF */
+#endif
+	str     r0, [r1, #AT91C_CKGR_MOR]
+	/* Add loop to compensate Main Oscillator startup time */
+	ldr     r0, =0x00000010
+LoopOsc:
+	subs    r0, r0, #1
+	bhi     LoopOsc
+
+	/* memory control configuration */
+	/* this isn't very elegant, but	 what the heck */
+	ldr	r0, =SMRDATA
+	ldr	r1, _MTEXT_BASE
+	sub	r0, r0, r1
+	add	r2, r0, #80
+0:
+	/* the address */
+	ldr	r1, [r0], #4
+	/* the value */
+	ldr	r3, [r0], #4
+	str	r3, [r1]
+	cmp	r2, r0
+	bne	0b
+	/* delay - this is all done by guess */
+	ldr	r0, =0x00010000
+	/* (vs reading PMC_SR for LOCKA, LOCKB ... or MOSCS earlier) */
+1:
+	subs	r0, r0, #1
+	bhi	1b
+	ldr	r0, =SMRDATA1
+	ldr	r1, _MTEXT_BASE
+	sub	r0, r0, r1
+	add	r2, r0, #176
+2:
+	/* the address */
+	ldr	r1, [r0], #4
+	/* the value */
+	ldr	r3, [r0], #4
+	str	r3, [r1]
+	cmp	r2, r0
+	bne	2b
+
+	/* switch from FastBus to Asynchronous clock mode */
+	mrc	p15, 0, r0, c1, c0, 0
+	orr	r0, r0, #0xC0000000	@ set bit 31 (iA) and 30 (nF)
+	mcr	p15, 0, r0, c1, c0, 0
+
+	/* everything is fine now */
+	mov	pc, lr
+
+	.ltorg
+
+SMRDATA:
+	.word AT91C_EBI_CFGR
+	.word CONFIG_SYS_EBI_CFGR_VAL
+	.word AT91C_SMC_CSR0
+	.word CONFIG_SYS_SMC_CSR0_VAL
+	.word AT91C_PLLAR
+	.word CONFIG_SYS_PLLAR_VAL
+	.word AT91C_PLLBR
+	.word CONFIG_SYS_PLLBR_VAL
+	.word AT91C_MCKR
+	.word CONFIG_SYS_MCKR_VAL
+	/* here there's a delay */
+SMRDATA1:
+	.word AT91C_PIOC_ASR
+	.word CONFIG_SYS_PIOC_ASR_VAL
+	.word AT91C_PIOC_BSR
+	.word CONFIG_SYS_PIOC_BSR_VAL
+	.word AT91C_PIOC_PDR
+	.word CONFIG_SYS_PIOC_PDR_VAL
+	.word AT91C_EBI_CSA
+	.word CONFIG_SYS_EBI_CSA_VAL
+	.word AT91C_SDRC_CR
+	.word CONFIG_SYS_SDRC_CR_VAL
+	.word AT91C_SDRC_MR
+	.word CONFIG_SYS_SDRC_MR_VAL
+	.word CONFIG_SYS_SDRAM
+	.word CONFIG_SYS_SDRAM_VAL
+	.word AT91C_SDRC_MR
+	.word CONFIG_SYS_SDRC_MR_VAL1
+	.word CONFIG_SYS_SDRAM
+	.word CONFIG_SYS_SDRAM_VAL
+	.word CONFIG_SYS_SDRAM
+	.word CONFIG_SYS_SDRAM_VAL
+	.word CONFIG_SYS_SDRAM
+	.word CONFIG_SYS_SDRAM_VAL
+	.word CONFIG_SYS_SDRAM
+	.word CONFIG_SYS_SDRAM_VAL
+	.word CONFIG_SYS_SDRAM
+	.word CONFIG_SYS_SDRAM_VAL
+	.word CONFIG_SYS_SDRAM
+	.word CONFIG_SYS_SDRAM_VAL
+	.word CONFIG_SYS_SDRAM
+	.word CONFIG_SYS_SDRAM_VAL
+	.word CONFIG_SYS_SDRAM
+	.word CONFIG_SYS_SDRAM_VAL
+	.word AT91C_SDRC_MR
+	.word CONFIG_SYS_SDRC_MR_VAL2
+	.word CONFIG_SYS_SDRAM1
+	.word CONFIG_SYS_SDRAM_VAL
+	.word AT91C_SDRC_TR
+	.word CONFIG_SYS_SDRC_TR_VAL
+	.word CONFIG_SYS_SDRAM
+	.word CONFIG_SYS_SDRAM_VAL
+	.word AT91C_SDRC_MR
+	.word CONFIG_SYS_SDRC_MR_VAL3
+	.word CONFIG_SYS_SDRAM
+	.word CONFIG_SYS_SDRAM_VAL
+	/* SMRDATA1 is 176 bytes long */
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */

arch/arm/cpu/arm920t/ep93xx/Makefile

@@ -0,0 +1,55 @@
+#
+# Cirrus Logic EP93xx CPU-specific Makefile
+#
+# Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+#
+# Copyright (C) 2004, 2005
+# Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
+#
+# Copyright (C) 2006
+# Dominic Rath <Dominic.Rath@gmx.de>
+#
+# Based on an original Makefile, which is
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this project.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+# or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+# for more details.
+#
+# You should have received a copy of the GNU General Public License along
+# with this program; if not, write to the Free Software Foundation, Inc.,
+# 675 Mass Ave, Cambridge, MA 02139, USA.
+#
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).o
+
+COBJS   = cpu.o led.o speed.o timer.o
+SOBJS   = lowlevel_init.o
+
+SRCS    := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS    := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+all:    $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

arch/arm/cpu/arm920t/ep93xx/timer.c

@@ -0,0 +1,143 @@
+/*
+ * Cirrus Logic EP93xx timer support.
+ *
+ * Copyright (C) 2009, 2010 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * Copyright (C) 2004, 2005
+ * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
+ *
+ * Based on the original intr.c Cirrus Logic EP93xx Rev D. interrupt support,
+ * author unknown.
+ *
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <linux/types.h>
+#include <asm/arch/ep93xx.h>
+#include <asm/io.h>
+#include <div64.h>
+
+#define TIMER_CLKSEL	(1 << 3)
+#define TIMER_ENABLE	(1 << 7)
+
+#define TIMER_FREQ			508469		/* ticks / second */
+#define TIMER_MAX_VAL			0xFFFFFFFF
+
+static struct ep93xx_timer
+{
+	unsigned long long ticks;
+	unsigned long last_read;
+} timer;
+
+static inline unsigned long long usecs_to_ticks(unsigned long usecs)
+{
+	unsigned long long ticks = (unsigned long long)usecs * TIMER_FREQ;
+	do_div(ticks, 1000 * 1000);
+
+	return ticks;
+}
+
+static inline void read_timer(void)
+{
+	struct timer_regs *timer_regs = (struct timer_regs *)TIMER_BASE;
+	const unsigned long now = TIMER_MAX_VAL - readl(&timer_regs->timer3.value);
+
+	if (now >= timer.last_read)
+		timer.ticks += now - timer.last_read;
+	else
+		/* an overflow occurred */
+		timer.ticks += TIMER_MAX_VAL - timer.last_read + now;
+
+	timer.last_read = now;
+}
+
+/*
+ * Get the number of ticks (in CONFIG_SYS_HZ resolution)
+ */
+unsigned long long get_ticks(void)
+{
+	unsigned long long sys_ticks;
+
+	read_timer();
+
+	sys_ticks = timer.ticks * CONFIG_SYS_HZ;
+	do_div(sys_ticks, TIMER_FREQ);
+
+	return sys_ticks;
+}
+
+unsigned long get_timer_masked(void)
+{
+	return get_ticks();
+}
+
+unsigned long get_timer(unsigned long base)
+{
+	return get_timer_masked() - base;
+}
+
+void reset_timer_masked(void)
+{
+	read_timer();
+	timer.ticks = 0;
+}
+
+void reset_timer(void)
+{
+	reset_timer_masked();
+}
+
+void __udelay(unsigned long usec)
+{
+	unsigned long long target;
+
+	read_timer();
+
+	target = timer.ticks + usecs_to_ticks(usec);
+
+	while (timer.ticks < target)
+		read_timer();
+}
+
+int timer_init(void)
+{
+	struct timer_regs *timer_regs = (struct timer_regs *)TIMER_BASE;
+
+	/* use timer 3 with 508KHz and free running, not enabled now */
+	writel(TIMER_CLKSEL, &timer_regs->timer3.control);
+
+	/* set initial timer value */
+	writel(TIMER_MAX_VAL, &timer_regs->timer3.load);
+
+	/* Enable the timer */
+	writel(TIMER_ENABLE | TIMER_CLKSEL,
+		&timer_regs->timer3.control);
+
+	reset_timer_masked();
+
+	return 0;
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+unsigned long get_tbclk(void)
+{
+	return CONFIG_SYS_HZ;
+}

arch/arm/cpu/arm920t/ep93xx/u-boot.lds

@@ -0,0 +1,59 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  arch/arm/cpu/arm920t/start.o	(.text)
+		/* the EP93xx expects to find the pattern 'CRUS' at 0x1000 */
+	  . = 0x1000;
+	  LONG(0x53555243)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}

arch/arm/cpu/arm920t/imx/Makefile

@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).o
+
+COBJS	+= generic.o
+COBJS	+= speed.o
+COBJS	+= timer.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

arch/arm/cpu/arm920t/ks8695/Makefile

@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).o
+
+SOBJS	= lowlevel_init.o
+
+COBJS	= timer.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

arch/arm/cpu/arm920t/s3c24x0/Makefile

@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).o
+
+COBJS-$(CONFIG_USE_IRQ) += interrupts.o
+COBJS-y	+= speed.o
+COBJS-y	+= timer.o
+COBJS-y	+= usb.o
+COBJS-y	+= usb_ohci.o
+
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

arch/arm/cpu/arm920t/s3c24x0/speed.c

@@ -0,0 +1,118 @@
+/*
+ * (C) Copyright 2001-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* This code should work for both the S3C2400 and the S3C2410
+ * as they seem to have the same PLL and clock machinery inside.
+ * The different address mapping is handled by the s3c24xx.h files below.
+ */
+
+#include <common.h>
+#ifdef CONFIG_S3C24X0
+
+#include <asm/io.h>
+#include <asm/arch/s3c24x0_cpu.h>
+
+#define MPLL 0
+#define UPLL 1
+
+/* ------------------------------------------------------------------------- */
+/* NOTE: This describes the proper use of this file.
+ *
+ * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
+ *
+ * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
+ * the specified bus in HZ.
+ */
+/* ------------------------------------------------------------------------- */
+
+static ulong get_PLLCLK(int pllreg)
+{
+	struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
+	ulong r, m, p, s;
+
+	if (pllreg == MPLL)
+		r = readl(&clk_power->mpllcon);
+	else if (pllreg == UPLL)
+		r = readl(&clk_power->upllcon);
+	else
+		hang();
+
+	m = ((r & 0xFF000) >> 12) + 8;
+	p = ((r & 0x003F0) >> 4) + 2;
+	s = r & 0x3;
+
+#if defined(CONFIG_S3C2440)
+	if (pllreg == MPLL)
+		return 2 * m * (CONFIG_SYS_CLK_FREQ / (p << s));
+#endif
+	return (CONFIG_SYS_CLK_FREQ * m) / (p << s);
+
+}
+
+/* return FCLK frequency */
+ulong get_FCLK(void)
+{
+	return get_PLLCLK(MPLL);
+}
+
+/* return HCLK frequency */
+ulong get_HCLK(void)
+{
+	struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
+#ifdef CONFIG_S3C2440
+	switch (readl(&clk_power->clkdivn) & 0x6) {
+	default:
+	case 0:
+		return get_FCLK();
+	case 2:
+		return get_FCLK() / 2;
+	case 4:
+		return (readl(&clk_power->camdivn) & (1 << 9)) ?
+			get_FCLK() / 8 : get_FCLK() / 4;
+	case 6:
+		return (readl(&clk_power->camdivn) & (1 << 8)) ?
+			get_FCLK() / 6 : get_FCLK() / 3;
+	}
+#else
+	return (readl(&clk_power->clkdivn) & 2) ? get_FCLK() / 2 : get_FCLK();
+#endif
+}
+
+/* return PCLK frequency */
+ulong get_PCLK(void)
+{
+	struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
+
+	return (readl(&clk_power->clkdivn) & 1) ? get_HCLK() / 2 : get_HCLK();
+}
+
+/* return UCLK frequency */
+ulong get_UCLK(void)
+{
+	return get_PLLCLK(UPLL);
+}
+
+#endif /* CONFIG_S3C24X0 */