Prepare v2011.06

Signed-off-by: Wolfgang Denk <wd@denx.de>

MAINTAINERS

@@ -569,8 +569,8 @@ Stefano Babic <sbabic@denx.de>
 	ea20		davinci
 	mx35pdk		i.MX35
 	mx51evk		i.MX51
-	polaris		xscale
-	trizepsiv	xscale
+	polaris		xscale/pxa
+	trizepsiv	xscale/pxa
  	vision2		i.MX51
 
 Jason Liu <r64343@freescale.com>
@@ -603,7 +603,7 @@ Andreas Bie
 
 Cliff Brake <cliff.brake@gmail.com>
 
-	pxa255_idp	xscale
+	pxa255_idp	xscale/pxa
 
 Rick Bronson <rick@efn.org>
 
@@ -677,7 +677,6 @@ Grazvydas Ignotas <notasas@gmail.com>
 Gary Jennejohn <garyj@denx.de>
 
 	smdk2400	ARM920T
-	trab		ARM920T
 
 Matthias Kaehlcke <matthias@kaehlcke.net>
 	edb9301			ARM920T (EP9301)
@@ -718,7 +717,7 @@ Sergey Kubushyn <ksi@koi8.net>
 
 Prakash Kumar <prakash@embedx.com>
 
-	cerf250		xscale
+	cerf250		xscale/pxa
 
 Vipin Kumar <vipin.kumar@st.com>
 
@@ -796,9 +795,9 @@ John Rigby <jcrigby@gmail.com>
 
 Stefan Roese <sr@denx.de>
 
-	ixdpg425	xscale
-	pdnb3		xscale
-	scpu		xscale
+	ixdpg425	xscale/ixp
+	pdnb3		xscale/ixp
+	scpu		xscale/ixp
 
 Alessandro Rubini <rubini@unipv.it>
 Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com>
@@ -824,15 +823,16 @@ Heiko Schocher <hs@denx.de>
 
 Robert Schwebel <r.schwebel@pengutronix.de>
 
-	csb226		xscale
-	innokom		xscale
+	csb226		xscale/pxa
+	innokom		xscale/pxa
 
 Michael Schwingen <michael@schwingen.org>
 
-	actux1		xscale
-	actux2		xscale
-	actux3		xscale
-	actux4		xscale
+	actux1		xscale/ixp
+	actux2		xscale/ixp
+	actux3		xscale/ixp
+	actux4		xscale/ixp
+	dvlhost		xscale/ixp
 
 Andrea Scian <andrea.scian@dave-tech.it>
 
@@ -856,12 +856,12 @@ Greg Ungerer <greg.ungerer@opengear.com>
 
 Marek Vasut <marek.vasut@gmail.com>
 
-	balloon3	xscale
-	colibri_pxa270	xscale
-	palmld		xscale
-	palmtc		xscale
-	vpac270		xscale
-	zipitz2		xscale
+	balloon3	xscale/pxa
+	colibri_pxa270	xscale/pxa
+	palmld		xscale/pxa
+	palmtc		xscale/pxa
+	vpac270		xscale/pxa
+	zipitz2		xscale/pxa
  	efikamx		i.MX51
 
 Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
@@ -912,9 +912,9 @@ Sughosh Ganu <urwithsughosh@gmail.com>
 Unknown / orphaned boards:
  	Board		CPU	Last known maintainer / Comment
 .........................................................................
-	cradle		xscale	Kyle Harris <kharris@nexus-tech.net> / dead address
-	ixdp425		xscale	Kyle Harris <kharris@nexus-tech.net> / dead address
-	lubbock		xscale	Kyle Harris <kharris@nexus-tech.net> / dead address
+	cradle		xscale/pxa	Kyle Harris <kharris@nexus-tech.net> / dead address
+	ixdp425		xscale/ixp	Kyle Harris <kharris@nexus-tech.net> / dead address
+	lubbock		xscale/pxa	Kyle Harris <kharris@nexus-tech.net> / dead address
 
 	imx31_phycore_eet i.MX31  Guennadi Liakhovetski <g.liakhovetski@gmx.de> / resigned
 	mx31ads		  i.MX31  Guennadi Liakhovetski <g.liakhovetski@gmx.de> / resigned

MAKEALL

@@ -374,7 +374,6 @@ LIST_ARM9="			\
 	spear320		\
 	spear600		\
 	suen3			\
-	trab			\
 	VCMA9			\
 	versatile		\
 	versatileab		\

Makefile

@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2000-2010
+# (C) Copyright 2000-2011
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
@@ -24,7 +24,7 @@
 VERSION = 2011
 PATCHLEVEL = 06
 SUBLEVEL =
-EXTRAVERSION = -rc3
+EXTRAVERSION =
 ifneq "$(SUBLEVEL)" ""
 U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
 else
@@ -140,7 +140,7 @@ SUBDIRS	= tools \
 	  examples/standalone \
 	  examples/api
 
-.PHONY : $(SUBDIRS)
+.PHONY : $(SUBDIRS) $(VERSION_FILE)
 
 ifeq ($(obj)include/config.mk,$(wildcard $(obj)include/config.mk))
 
@@ -163,6 +163,36 @@ endif
 # load other configuration
 include $(TOPDIR)/config.mk
 
+# If board code explicitly specified LDSCRIPT or CONFIG_SYS_LDSCRIPT, use
+# that (or fail if absent).  Otherwise, search for a linker script in a
+# standard location.
+
+ifndef LDSCRIPT
+	#LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds.debug
+	ifdef CONFIG_SYS_LDSCRIPT
+		# need to strip off double quotes
+		LDSCRIPT := $(subst ",,$(CONFIG_SYS_LDSCRIPT))
+	endif
+endif
+
+ifndef LDSCRIPT
+	ifeq ($(CONFIG_NAND_U_BOOT),y)
+		LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds
+		ifeq ($(wildcard $(LDSCRIPT)),)
+			LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
+		endif
+	endif
+	ifeq ($(wildcard $(LDSCRIPT)),)
+		LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
+	endif
+	ifeq ($(wildcard $(LDSCRIPT)),)
+		LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot.lds
+	endif
+	ifeq ($(wildcard $(LDSCRIPT)),)
+$(error could not find linker script)
+	endif
+endif
+
 #########################################################################
 # U-Boot objects....order is important (i.e. start must be first)
 
@@ -236,7 +266,7 @@ endif
 LIBS += drivers/rtc/librtc.o
 LIBS += drivers/serial/libserial.o
 LIBS += drivers/twserial/libtws.o
-LIBS += drivers/usb/eth/libusb_eth.a
+LIBS += drivers/usb/eth/libusb_eth.o
 LIBS += drivers/usb/gadget/libusb_gadget.o
 LIBS += drivers/usb/host/libusb_host.o
 LIBS += drivers/usb/musb/libusb_musb.o
@@ -263,7 +293,7 @@ LIBS += $(CPUDIR)/s5p-common/libs5p-common.o
 endif
 
 LIBS := $(addprefix $(obj),$(sort $(LIBS)))
-.PHONY : $(LIBS) $(TIMESTAMP_FILE) $(VERSION_FILE)
+.PHONY : $(LIBS) $(TIMESTAMP_FILE)
 
 LIBBOARD = board/$(BOARDDIR)/lib$(BOARD).o
 LIBBOARD := $(addprefix $(obj),$(LIBBOARD))
@@ -422,19 +452,6 @@ mmc_spl:	$(TIMESTAMP_FILE) $(VERSION_FILE) depend
 
 $(obj)mmc_spl/u-boot-mmc-spl.bin:	mmc_spl
 
-$(VERSION_FILE):
-		@( localvers='$(shell $(TOPDIR)/tools/setlocalversion $(TOPDIR))' ; \
-		   printf '#define PLAIN_VERSION "%s%s"\n' \
-			"$(U_BOOT_VERSION)" "$${localvers}" ; \
-		   printf '#define U_BOOT_VERSION "U-Boot %s%s"\n' \
-			"$(U_BOOT_VERSION)" "$${localvers}" ; \
-		) > $@.tmp
-		@( printf '#define CC_VERSION_STRING "%s"\n' \
-		 '$(shell $(CC) --version | head -n 1)' )>>  $@.tmp
-		@( printf '#define LD_VERSION_STRING "%s"\n' \
-		 '$(shell $(LD) -v | head -n 1)' )>>  $@.tmp
-		@cmp -s $@ $@.tmp && rm -f $@.tmp || mv -f $@.tmp $@
-
 $(TIMESTAMP_FILE):
 		@LC_ALL=C date +'#define U_BOOT_DATE "%b %d %C%y"' > $@
 		@LC_ALL=C date +'#define U_BOOT_TIME "%T"' >> $@
@@ -509,20 +526,33 @@ $(obj)lib/asm-offsets.s:	$(obj)include/autoconf.mk.dep \
 else	# !config.mk
 all $(obj)u-boot.hex $(obj)u-boot.srec $(obj)u-boot.bin \
 $(obj)u-boot.img $(obj)u-boot.dis $(obj)u-boot \
-$(filter-out tools,$(SUBDIRS)) $(TIMESTAMP_FILE) $(VERSION_FILE) \
+$(filter-out tools,$(SUBDIRS)) $(TIMESTAMP_FILE) \
 updater depend dep tags ctags etags cscope $(obj)System.map:
 	@echo "System not configured - see README" >&2
 	@ exit 1
 
-tools:
+tools: $(VERSION_FILE)
 	$(MAKE) -C $@ all
 endif	# config.mk
 
+$(VERSION_FILE):
+		@( localvers='$(shell $(TOPDIR)/tools/setlocalversion $(TOPDIR))' ; \
+		   printf '#define PLAIN_VERSION "%s%s"\n' \
+			"$(U_BOOT_VERSION)" "$${localvers}" ; \
+		   printf '#define U_BOOT_VERSION "U-Boot %s%s"\n' \
+			"$(U_BOOT_VERSION)" "$${localvers}" ; \
+		) > $@.tmp
+		@( printf '#define CC_VERSION_STRING "%s"\n' \
+		 '$(shell $(CC) --version | head -n 1)' )>>  $@.tmp
+		@( printf '#define LD_VERSION_STRING "%s"\n' \
+		 '$(shell $(LD) -v | head -n 1)' )>>  $@.tmp
+		@cmp -s $@ $@.tmp && rm -f $@.tmp || mv -f $@.tmp $@
+
 easylogo env gdb:
 	$(MAKE) -C tools/$@ all MTD_VERSION=${MTD_VERSION}
 gdbtools: gdb
 
-tools-all: easylogo env gdb
+tools-all: easylogo env gdb $(VERSION_FILE)
 	$(MAKE) -C tools HOST_TOOLS_ALL=y
 
 .PHONY : CHANGELOG
@@ -937,29 +967,6 @@ SX1_config:		unconfig
 	fi;
 	@$(MKCONFIG) -n $@ SX1 arm arm925t sx1
 
-# TRAB default configuration:	8 MB Flash, 32 MB RAM
-trab_config \
-trab_bigram_config \
-trab_bigflash_config \
-trab_old_config:	unconfig
-	@mkdir -p $(obj)include
-	@mkdir -p $(obj)board/trab
-	@[ -z "$(findstring _bigram,$@)" ] || \
-		{ echo "#define CONFIG_FLASH_8MB"  >>$(obj)include/config.h ; \
-		  echo "#define CONFIG_RAM_32MB"   >>$(obj)include/config.h ; \
-		}
-	@[ -z "$(findstring _bigflash,$@)" ] || \
-		{ echo "#define CONFIG_FLASH_16MB" >>$(obj)include/config.h ; \
-		  echo "#define CONFIG_RAM_16MB"   >>$(obj)include/config.h ; \
-		  echo "CONFIG_SYS_TEXT_BASE = 0x0CF40000" >$(obj)board/trab/config.tmp ; \
-		}
-	@[ -z "$(findstring _old,$@)" ] || \
-		{ echo "#define CONFIG_FLASH_8MB"  >>$(obj)include/config.h ; \
-		  echo "#define CONFIG_RAM_16MB"   >>$(obj)include/config.h ; \
-		  echo "CONFIG_SYS_TEXT_BASE = 0x0CF40000" >$(obj)board/trab/config.tmp ; \
-		}
-	@$(MKCONFIG) -n $@ -a trab arm arm920t trab - s3c24x0
-
 tx25_config	: unconfig
 	@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
 	@$(MKCONFIG) $@ arm arm926ejs tx25 karo mx25
@@ -1079,7 +1086,7 @@ clean:
 	@rm -f $(obj)board/cray/L1/{bootscript.c,bootscript.image}	  \
 	       $(obj)board/matrix_vision/*/bootscript.img		  \
 	       $(obj)board/netstar/{eeprom,crcek,crcit,*.srec,*.bin}	  \
-	       $(obj)board/trab/trab_fkt   $(obj)board/voiceblue/eeprom   \
+	       $(obj)board/voiceblue/eeprom 				  \
 	       $(obj)board/armltd/{integratorap,integratorcp}/u-boot.lds  \
 	       $(obj)u-boot.lds						  \
 	       $(obj)arch/blackfin/cpu/bootrom-asm-offsets.[chs]

README

@@ -716,7 +716,6 @@ The following options need to be configured:
 		CONFIG_CMD_SPI		* SPI serial bus support
 		CONFIG_CMD_TFTPSRV	* TFTP transfer in server mode
 		CONFIG_CMD_USB		* USB support
-		CONFIG_CMD_VFD		* VFD support (TRAB)
 		CONFIG_CMD_CDP		* Cisco Discover Protocol support
 		CONFIG_CMD_FSL		* Microblaze FSL support
 
@@ -2230,7 +2229,7 @@ FIT uImage format:
 Modem Support:
 --------------
 
-[so far only for SMDK2400 and TRAB boards]
+[so far only for SMDK2400 boards]
 
 - Modem support enable:
 		CONFIG_MODEM_SUPPORT

arch/arm/config.mk

@@ -62,6 +62,13 @@ PLATFORM_LIBS += $(OBJTREE)/arch/arm/lib/eabi_compat.o
 endif
 endif
 
+ifdef CONFIG_SYS_LDSCRIPT
+# need to strip off double quotes
+LDSCRIPT := $(subst ",,$(CONFIG_SYS_LDSCRIPT))
+else
+LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds
+endif
+
 # needed for relocation
 ifndef CONFIG_NAND_SPL
 LDFLAGS_u-boot += -pie

arch/arm/cpu/arm920t/s3c24x0/timer.c

@@ -177,7 +177,7 @@ ulong get_tbclk(void)
 {
 	ulong tbclk;
 
-#if defined(CONFIG_SMDK2400) || defined(CONFIG_TRAB)
+#if defined(CONFIG_SMDK2400)
 	tbclk = timer_load_val * 100;
 #elif defined(CONFIG_SBC2410X) || \
       defined(CONFIG_SMDK2410) || \
@@ -198,12 +198,6 @@ void reset_cpu(ulong ignored)
 {
 	struct s3c24x0_watchdog *watchdog;
 
-#ifdef CONFIG_TRAB
-	extern void disable_vfd(void);
-
-	disable_vfd();
-#endif
-
 	watchdog = s3c24x0_get_base_watchdog();
 
 	/* Disable watchdog */

arch/arm/cpu/ixp/config.mk

@@ -27,6 +27,11 @@ BIG_ENDIAN = y
 PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float -mbig-endian
 
 PLATFORM_CPPFLAGS += -mbig-endian -march=armv5te -mtune=strongarm1100
+
+# -fdata-sections triggers "section .bss overlaps section .rel.dyn" linker error
+PLATFORM_RELFLAGS += -ffunction-sections
+LDFLAGS_u-boot += --gc-sections
+
 # =========================================================================
 #
 # Supply options according to compiler version

arch/arm/cpu/ixp/cpu.c

@@ -36,8 +36,6 @@
 #include <asm/arch/ixp425.h>
 #include <asm/system.h>
 
-ulong loops_per_jiffy;
-
 static void cache_flush(void);
 
 #if defined(CONFIG_DISPLAY_CPUINFO)
@@ -51,17 +49,14 @@ int print_cpuinfo (void)
 	puts("CPU:   Intel IXP425 at ");
 	switch ((id & 0x000003f0) >> 4) {
 	case 0x1c:
-		loops_per_jiffy = 887467;
 		speed = 533;
 		break;
 
 	case 0x1d:
-		loops_per_jiffy = 666016;
 		speed = 400;
 		break;
 
 	case 0x1f:
-		loops_per_jiffy = 442901;
 		speed = 266;
 		break;
 	}

arch/arm/cpu/ixp/npe/Makefile

@@ -27,6 +27,7 @@ LIB := $(obj)libnpe.o
 
 LOCAL_CFLAGS  += -I$(TOPDIR)/arch/arm/cpu/ixp/npe/include -DCONFIG_IXP425_COMPONENT_ETHDB -D__linux
 CFLAGS  += $(LOCAL_CFLAGS)
+CPPFLAGS  += $(LOCAL_CFLAGS) # needed for depend
 HOSTCFLAGS  += $(LOCAL_CFLAGS)
 
 COBJS-$(CONFIG_IXP4XX_NPE) := npe.o \

arch/arm/cpu/ixp/npe/npe.c

@@ -359,36 +359,53 @@ static int npe_init(struct eth_device *dev, bd_t * bis)
 
 	debug("%s: 1\n", __FUNCTION__);
 
-	miiphy_read (dev->name, p_npe->phy_no, MII_BMSR, &reg_short);
+#ifdef CONFIG_MII_NPE0_FIXEDLINK
+	if (0 == p_npe->eth_id) {
+		speed = CONFIG_MII_NPE0_SPEED;
+		duplex = CONFIG_MII_NPE0_FULLDUPLEX ? FULL : HALF;
+	} else
+#endif
+#ifdef CONFIG_MII_NPE1_FIXEDLINK
+	if (1 == p_npe->eth_id) {
+		speed = CONFIG_MII_NPE1_SPEED;
+		duplex = CONFIG_MII_NPE1_FULLDUPLEX ? FULL : HALF;
+	} else
+#endif
+	{
+		miiphy_read(dev->name, p_npe->phy_no, MII_BMSR, &reg_short);
 
-	/*
-	 * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
-	 */
-	if ((reg_short & BMSR_ANEGCAPABLE) && !(reg_short & BMSR_ANEGCOMPLETE)) {
-		puts ("Waiting for PHY auto negotiation to complete");
-		i = 0;
-		while (!(reg_short & BMSR_ANEGCOMPLETE)) {
-			/*
-			 * Timeout reached ?
-			 */
-			if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
-				puts (" TIMEOUT !\n");
-				break;
-			}
+		/*
+		 * Wait if PHY is capable of autonegotiation and
+		 * autonegotiation is not complete
+		 */
+		if ((reg_short & BMSR_ANEGCAPABLE) &&
+		    !(reg_short & BMSR_ANEGCOMPLETE)) {
+			puts("Waiting for PHY auto negotiation to complete");
+			i = 0;
+			while (!(reg_short & BMSR_ANEGCOMPLETE)) {
+				/*
+				 * Timeout reached ?
+				 */
+				if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
+					puts(" TIMEOUT !\n");
+					break;
+				}
 
-			if ((i++ % 1000) == 0) {
-				putc ('.');
-				miiphy_read (dev->name, p_npe->phy_no, MII_BMSR, &reg_short);
+				if ((i++ % 1000) == 0) {
+					putc('.');
+					miiphy_read(dev->name, p_npe->phy_no,
+						     MII_BMSR, &reg_short);
+				}
+				udelay(1000);	/* 1 ms */
 			}
-			udelay (1000);	/* 1 ms */
+			puts(" done\n");
+			/* another 500 ms (results in faster booting) */
+			udelay(500000);
 		}
-		puts (" done\n");
-		udelay (500000);	/* another 500 ms (results in faster booting) */
+		speed = miiphy_speed(dev->name, p_npe->phy_no);
+		duplex = miiphy_duplex(dev->name, p_npe->phy_no);
 	}
 
-	speed = miiphy_speed (dev->name, p_npe->phy_no);
-	duplex = miiphy_duplex (dev->name, p_npe->phy_no);
-
 	if (p_npe->print_speed) {
 		p_npe->print_speed = 0;
 		printf ("ENET Speed is %d Mbps - %s duplex connection\n",
@@ -621,9 +638,12 @@ int npe_initialize(bd_t * bis)
 			if (ixFeatureCtrlDeviceRead() == IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X) {
 				switch (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK) {
 				case IX_FEATURE_CTRL_SILICON_TYPE_B0:
+				default: /* newer than B0 */
 					/*
-					 * If it is B0 Silicon, we only enable port when its corresponding
-					 * Eth Coprocessor is available.
+					 * If it is B0 or newer Silicon, we
+					 * only enable port when its
+					 * corresponding Eth Coprocessor is
+					 * available.
 					 */
 					if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0) ==
 					    IX_FEATURE_CTRL_COMPONENT_ENABLED)

arch/arm/cpu/ixp/start.S

@@ -65,7 +65,8 @@
 	.endm
 
 .globl _start
-_start: b	reset
+_start:
+	ldr	pc, _reset
 	ldr	pc, _undefined_instruction
 	ldr	pc, _software_interrupt
 	ldr	pc, _prefetch_abort
@@ -74,6 +75,7 @@ _start: b	reset
 	ldr	pc, _irq
 	ldr	pc, _fiq
 
+_reset:                 .word reset
 _undefined_instruction: .word undefined_instruction
 _software_interrupt:	.word software_interrupt
 _prefetch_abort:	.word prefetch_abort
@@ -167,12 +169,6 @@ reset:
 	str     r1, [r2]
 
 	/* make sure flash is visible at 0 */
-#if 0
-	ldr	r2, =IXP425_EXP_CFG0
-	ldr     r1, [r2]
-	orr     r1, r1, #0x80000000
-	str     r1, [r2]
-#endif
 	mov	r1, #CONFIG_SYS_SDR_CONFIG
 	ldr     r2, =IXP425_SDR_CONFIG
 	str     r1, [r2]
@@ -216,19 +212,6 @@ reset:
 	str	r1, [r4]
 	DELAY_FOR 0x4000, r0
 
-	/* copy */
-	mov     r0, #0
-	mov     r4, r0
-	add     r2, r0, #CONFIG_SYS_MONITOR_LEN
-	mov     r1, #0x10000000
-	mov     r5, r1
-
-    30:
-	ldr     r3, [r0], #4
-	str     r3, [r1], #4
-	cmp     r0, r2
-	bne     30b
-
 	/* invalidate I & D caches & BTB */
 	mcr	p15, 0, r0, c7, c7, 0
 	CPWAIT	r0
@@ -241,19 +224,12 @@ reset:
 	mcr	p15, 0, r0, c7, c10, 4
 	CPWAIT	r0
 
-	/* move flash to 0x50000000 */
+	/* remove flash mirror at 0x00000000 */
 	ldr	r2, =IXP425_EXP_CFG0
 	ldr     r1, [r2]
 	bic     r1, r1, #0x80000000
 	str     r1, [r2]
 
-	nop
-	nop
-	nop
-	nop
-	nop
-	nop
-
 	/* invalidate I & Data TLB */
 	mcr	p15, 0, r0, c8, c7, 0
 	CPWAIT r0
@@ -269,7 +245,7 @@ reset:
 	orr	r0,r0,#0x13
 	msr	cpsr,r0
 
-/* Set stackpointer in internal RAM to call board_init_f */
+/* Set initial stackpointer in SDRAM to call board_init_f */
 call_board_init_f:
 	ldr	sp, =(CONFIG_SYS_INIT_SP_ADDR)
 	bic	sp, sp, #7 /* 8-byte alignment for ABI compliance */
@@ -575,33 +551,5 @@ reset_cpu:
 	str     r1, [r2]
 	b	reset_endless
 
-
 reset_endless:
-
 	b	reset_endless
-
-#ifdef CONFIG_USE_IRQ
-
-.LC0:		.word	loops_per_jiffy
-
-/*
- * 0 <= r0 <= 2000
- */
-.globl __udelay
-__udelay:
-	mov	r2,     #0x6800
-	orr	r2, r2, #0x00db
-	mul	r0, r2, r0
-	ldr	r2, .LC0
-	ldr	r2, [r2]		@ max = 0x0fffffff
-	mov	r0, r0, lsr #11		@ max = 0x00003fff
-	mov	r2, r2, lsr #11		@ max = 0x0003ffff
-	mul	r0, r2, r0		@ max = 2^32-1
-	movs	r0, r0, lsr #6
-
-delay_loop:
-	subs	r0, r0, #1
-	bne	delay_loop
-	mov	pc, lr
-
-#endif /* CONFIG_USE_IRQ */

arch/arm/cpu/ixp/timer.c

@@ -1,4 +1,7 @@
 /*
+ * (C) Copyright 2010
+ * Michael Schwingen, michael@schwingen.org
+ *
  * (C) Copyright 2006
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
@@ -31,105 +34,94 @@
 
 #include <common.h>
 #include <asm/arch/ixp425.h>
+#include <asm/io.h>
+#include <div64.h>
 
-#ifdef CONFIG_TIMER_IRQ
-
-#define FREQ		66666666
-#define CLOCK_TICK_RATE	(((FREQ / CONFIG_SYS_HZ & ~IXP425_OST_RELOAD_MASK) + 1) * CONFIG_SYS_HZ)
-#define LATCH		((CLOCK_TICK_RATE + CONFIG_SYS_HZ/2) / CONFIG_SYS_HZ)	/* For divider */
+DECLARE_GLOBAL_DATA_PTR;
 
 /*
- * When interrupts are enabled, use timer 2 for time/delay generation...
+ * The IXP42x time-stamp timer runs at 2*OSC_IN (66.666MHz when using a
+ * 33.333MHz crystal).
  */
-
-static volatile ulong timestamp;
-
-static void timer_isr(void *data)
+static inline unsigned long long tick_to_time(unsigned long long tick)
 {
-	unsigned int *pTime = (unsigned int *)data;
-
-	(*pTime)++;
-
-	/*
-	 * Reset IRQ source
-	 */
-	*IXP425_OSST = IXP425_OSST_TIMER_2_PEND;
+	tick *= CONFIG_SYS_HZ;
+	do_div(tick, CONFIG_IXP425_TIMER_CLK);
+	return tick;
 }
 
-ulong get_timer (ulong base)
+static inline unsigned long long time_to_tick(unsigned long long time)
 {
-	return timestamp - base;
+	time *= CONFIG_IXP425_TIMER_CLK;
+	do_div(time, CONFIG_SYS_HZ);
+	return time;
 }
 
-void reset_timer (void)
+static inline unsigned long long us_to_tick(unsigned long long us)
 {
-	timestamp = 0;
+	us = us * CONFIG_IXP425_TIMER_CLK + 999999;
+	do_div(us, 1000000);
+	return us;
 }
 
-int timer_init (void)
+unsigned long long get_ticks(void)
 {
-	/* install interrupt handler for timer */
-	irq_install_handler(IXP425_TIMER_2_IRQ, timer_isr, (void *)&timestamp);
+	ulong now = readl(IXP425_OSTS_B);
 
-	/* setup the Timer counter value */
-	*IXP425_OSRT2 = (LATCH & ~IXP425_OST_RELOAD_MASK) | IXP425_OST_ENABLE;
-
-	/* enable timer irq */
-	*IXP425_ICMR = (1 << IXP425_TIMER_2_IRQ);
-
-	return 0;
-}
-#else
-ulong get_timer (ulong base)
-{
-       return get_timer_masked () - base;
-}
-
-void ixp425_udelay(unsigned long usec)
-{
-	/*
-	 * This function has a max usec, but since it is called from udelay
-	 * we should not have to worry... be happy
-	 */
-	unsigned long usecs = CONFIG_SYS_HZ/1000000L & ~IXP425_OST_RELOAD_MASK;
-
-	*IXP425_OSST = IXP425_OSST_TIMER_1_PEND;
-	usecs |= IXP425_OST_ONE_SHOT | IXP425_OST_ENABLE;
-	*IXP425_OSRT1 = usecs;
-	while (!(*IXP425_OSST & IXP425_OSST_TIMER_1_PEND));
-}
-
-void __udelay (unsigned long usec)
-{
-	while (usec--) ixp425_udelay(1);
-}
-
-static ulong reload_constant = 0xfffffff0;
-
-void reset_timer_masked (void)
-{
-	ulong reload = reload_constant | IXP425_OST_ONE_SHOT | IXP425_OST_ENABLE;
-
-	*IXP425_OSST = IXP425_OSST_TIMER_1_PEND;
-	*IXP425_OSRT1 = reload;
-}
-
-ulong get_timer_masked (void)
-{
-	/*
-	 * Note that it is possible for this to wrap!
-	 * In this case we return max.
-	 */
-	ulong current = *IXP425_OST1;
-	if (*IXP425_OSST & IXP425_OSST_TIMER_1_PEND)
-	{
-		return reload_constant;
+	if (readl(IXP425_OSST) & IXP425_OSST_TIMER_TS_PEND) {
+		/* rollover of timestamp timer register */
+		gd->timestamp += (0xFFFFFFFF - gd->lastinc) + now + 1;
+		writel(IXP425_OSST_TIMER_TS_PEND, IXP425_OSST);
+	} else {
+		/* move stamp forward with absolut diff ticks */
+		gd->timestamp += (now - gd->lastinc);
 	}
-	return (reload_constant - current);
+	gd->lastinc = now;
+	return gd->timestamp;
+}
+
+
+void reset_timer_masked(void)
+{
+	/* capture current timestamp counter */
+	gd->lastinc = readl(IXP425_OSTS_B);
+	/* start "advancing" time stamp from 0 */
+	gd->timestamp = 0;
+}
+
+void reset_timer(void)
+{
+	reset_timer_masked();
+}
+
+ulong get_timer_masked(void)
+{
+	return tick_to_time(get_ticks());
+}
+
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+void set_timer(ulong t)
+{
+	gd->timestamp = time_to_tick(t);
+}
+
+/* delay x useconds AND preserve advance timestamp value */
+void __udelay(unsigned long usec)
+{
+	unsigned long long tmp;
+
+	tmp = get_ticks() + us_to_tick(usec);
+
+	while (get_ticks() < tmp)
+		;
 }
 
 int timer_init(void)
 {
+	writel(IXP425_OSST_TIMER_TS_PEND, IXP425_OSST);
 	return 0;
 }
-#endif

arch/arm/cpu/ixp/u-boot.lds

@@ -31,8 +31,8 @@ SECTIONS
 	. = ALIGN(4);
 	.text :
 	{
-		arch/arm/cpu/ixp/start.o(.text)
-		*(.text)
+		arch/arm/cpu/ixp/start.o(.text*)
+		*(.text*)
 	}
 
 	. = ALIGN(4);
@@ -40,7 +40,7 @@ SECTIONS
 
 	. = ALIGN(4);
 	.data : {
-		*(.data)
+		*(.data*)
 	}
 
 	. = ALIGN(4);
@@ -67,7 +67,7 @@ SECTIONS
 
 	.bss __rel_dyn_start (OVERLAY) : {
 		__bss_start = .;
-		*(.bss)
+		*(.bss*)
 		 . = ALIGN(4);
 		__bss_end__ = .;
 	}

arch/arm/include/asm/arch-ixp/ixp425.h

@@ -391,9 +391,8 @@
 #define IXP425_TIMER_REG(x) (IXP425_TIMER_BASE_PHYS+(x))
 #endif
 
-#if 0 /* test-only: also defined in npe/include/... */
-#define IXP425_OSTS	IXP425_TIMER_REG(IXP425_OSTS_OFFSET)
-#endif
+/* _B to avoid collision: also defined in npe/include/... */
+#define IXP425_OSTS_B	IXP425_TIMER_REG(IXP425_OSTS_OFFSET)
 #define IXP425_OST1	IXP425_TIMER_REG(IXP425_OST1_OFFSET)
 #define IXP425_OSRT1	IXP425_TIMER_REG(IXP425_OSRT1_OFFSET)
 #define IXP425_OST2	IXP425_TIMER_REG(IXP425_OST2_OFFSET)

arch/arm/include/asm/arch-ixp/ixp425pci.h

@@ -22,88 +22,21 @@
  * MA 02111-1307 USA
  */
 
-#ifndef _IXP425PCI_H_
-#define _IXP425PCI_H_
+#ifndef _IXP425PCI_H
+#define _IXP425PCI_H
 
-#define TRUE	1
-#define FALSE	0
 #define OK	0
 #define ERROR	-1
-#define BOOL	int
 
-#define IXP425_PCI_MAX_BAR_PER_FUNC  6
-#define IXP425_PCI_MAX_BAR (IXP425_PCI_MAX_BAR_PER_FUNC * \
-			    IXP425_PCI_MAX_FUNC_ON_BUS)
-
-enum PciBarId
-{
-	CSR_BAR=0,
-	IO_BAR,
-	SD_BAR,
-	NO_BAR
-};
-
-/*Base address register descriptor*/
-typedef struct
-{
-	unsigned int size;
-	unsigned int address;
-} PciBar;
-
-typedef struct
-{
-	unsigned int bus;
-	unsigned int device;
-	unsigned int func;
-	unsigned int irq;
-	BOOL error;
-	unsigned short vendor_id;
-	unsigned short device_id;
-	/*We need an extra entry in this array for dummy placeholder*/
-	PciBar bar[IXP425_PCI_MAX_BAR_PER_FUNC + 1];
-} PciDevice;
+struct pci_controller;
+extern void pci_ixp_init(struct pci_controller *hose);
 
 /* Mask definitions*/
-#define IXP425_PCI_TOP_WORD_OF_LONG_MASK	0xffff0000
-#define IXP425_PCI_TOP_BYTE_OF_LONG_MASK	0xff000000
-#define IXP425_PCI_BOTTOM_WORD_OF_LONG_MASK	0x0000ffff
-#define IXP425_PCI_BOTTOM_TRIBYTES_OF_LONG_MASK 0x00ffffff
 #define IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK	0x0000000f
-#define IXP425_PCI_MAX_UINT32			0xffffffff
-
-
-#define IXP425_PCI_BAR_QUERY			0xffffffff
-
-#define IXP425_PCI_BAR_MEM_BASE 0x100000
-#define IXP425_PCI_BAR_IO_BASE	0x000000
-
-/*define the maximum number of bus segments - we support a single segment*/
-#define IXP425_PCI_MAX_BUS  1
-/*define the maximum number of cards per bus segment*/
-#define IXP425_PCI_MAX_DEV  4
-/*define the maximum number of functions per device*/
-#define IXP425_PCI_MAX_FUNC 8
-/* define the maximum number of separate functions that we can
-   potentially have on the bus*/
-#define IXP425_PCI_MAX_FUNC_ON_BUS (1+ IXP425_PCI_MAX_FUNC *	\
-				    IXP425_PCI_MAX_DEV *	\
-				    IXP425_PCI_MAX_BUS)
-/*define the maximum number of BARs per function*/
-#define IXP425_PCI_MAX_BAR_PER_FUNC  6
-#define IXP425_PCI_MAX_BAR (IXP425_PCI_MAX_BAR_PER_FUNC *	\
-			    IXP425_PCI_MAX_FUNC_ON_BUS)
 
 #define PCI_NP_CBE_BESL	 (4)
 #define PCI_NP_AD_FUNCSL (8)
 
-#define REG_WRITE(b,o,v) (*(volatile unsigned int*)((b+o))=(v))
-#define REG_READ(b,o,v)	 ((v)=(*(volatile unsigned int*)((b+o))))
-
-#define PCI_DELAY	500
-#define USEC_LOOP_COUNT 533
-#define PCI_SETTLE_USEC 200
-#define PCI_MIN_RESET_ASSERT_USEC 2000
-
 /*Register addressing definitions for PCI controller configuration
   and status registers*/
 
@@ -150,28 +83,6 @@ typedef struct
 #define NP_CMD_CONFIGWRITE (0xb)
 */
 
-/*define the default setting of the AHB memory base reg*/
-#define IXP425_PCI_AHBMEMBASE_DEFAULT 0x00010203
-#define IXP425_PCI_AHBIOBASE_DEFAULT  0x0
-#define IXP425_PCI_PCIMEMBASE_DEFAULT 0x0
-
-/*define the default settings for the controller's BARs*/
-#ifdef IXP425_PCI_SIMPLE_MAPPING
-#define IXP425_PCI_BAR_0_DEFAULT 0x00000000
-#define IXP425_PCI_BAR_1_DEFAULT 0x01000000
-#define IXP425_PCI_BAR_2_DEFAULT 0x02000000
-#define IXP425_PCI_BAR_3_DEFAULT 0x03000000
-#define IXP425_PCI_BAR_4_DEFAULT 0x00000000
-#define IXP425_PCI_BAR_5_DEFAULT 0x00000000
-#else
-#define IXP425_PCI_BAR_0_DEFAULT 0x40000000
-#define IXP425_PCI_BAR_1_DEFAULT 0x41000000
-#define IXP425_PCI_BAR_2_DEFAULT 0x42000000
-#define IXP425_PCI_BAR_3_DEFAULT 0x43000000
-#define IXP425_PCI_BAR_4_DEFAULT 0x00000000
-#define IXP425_PCI_BAR_5_DEFAULT 0x00000000
-#endif
-
 /*Configuration Port register bit definitions*/
 #define PCI_CRP_WRITE BIT(16)
 
@@ -228,17 +139,6 @@ typedef struct
 #define PCI_CFG_SPECIAL_USE	0x41
 #define PCI_CFG_MODE		0x43
 
-/*Specify the initial command we send to PCI devices*/
-#define INITIAL_PCI_CMD (PCI_CMD_IO_ENABLE	   \
-			 | PCI_CMD_MEM_ENABLE	   \
-			 | PCI_CMD_MASTER_ENABLE   \
-			 | PCI_CMD_WI_ENABLE)
-
-/*define the sub vendor and subsystem to be used */
-#define IXP425_PCI_SUB_VENDOR_SYSTEM 0x00000000
-
-#define PCI_IRQ_LINES		4
-
 #define PCI_CMD_IO_ENABLE	0x0001	/* IO access enable */
 #define PCI_CMD_MEM_ENABLE	0x0002	/* memory access enable */
 #define PCI_CMD_MASTER_ENABLE	0x0004	/* bus master enable */
@@ -287,26 +187,4 @@ typedef struct
 #define PCI_DMACTRL_PADC1   BIT(14)
 #define PCI_DMACTRL_PADE1   BIT(15)
 
-/* GPIO related register */
-#undef IXP425_GPIO_GPOUTR
-#undef IXP425_GPIO_GPOER
-#undef IXP425_GPIO_GPINR
-#undef IXP425_GPIO_GPISR
-#undef IXP425_GPIO_GPIT1R
-#undef IXP425_GPIO_GPIT2R
-#undef IXP425_GPIO_GPCLKR
-
-#define IXP425_GPIO_GPOUTR	0xC8004000
-#define IXP425_GPIO_GPOER	0xC8004004
-#define IXP425_GPIO_GPINR	0xC8004008
-#define IXP425_GPIO_GPISR	0xC800400C
-#define IXP425_GPIO_GPIT1R	0xC8004010
-#define IXP425_GPIO_GPIT2R	0xC8004014
-#define IXP425_GPIO_GPCLKR	0xC8004018
-
-#define READ_GPIO_REG(addr,val) \
-		(val) = *((volatile int *)(addr));
-#define WRITE_GPIO_REG(addr,val) \
-		*((volatile int *)(addr)) = (val);
-
 #endif

arch/arm/include/asm/global_data.h

@@ -41,9 +41,6 @@ typedef	struct	global_data {
 	unsigned long	env_addr;	/* Address  of Environment struct */
 	unsigned long	env_valid;	/* Checksum of Environment valid? */
 	unsigned long	fb_base;	/* base address of frame buffer */
-#ifdef CONFIG_VFD
-	unsigned char	vfd_type;	/* display type */
-#endif
 #ifdef CONFIG_FSL_ESDHC
 	unsigned long	sdhc_clk;
 #endif
@@ -63,6 +60,9 @@ typedef	struct	global_data {
 	unsigned long	tbu;
 	unsigned long long	timer_reset_value;
 	unsigned long	lastinc;
+#endif
+#ifdef CONFIG_IXP425
+	unsigned long	timestamp;
 #endif
 	unsigned long	relocaddr;	/* Start address of U-Boot in RAM */
 	phys_size_t	ram_size;	/* RAM size */

arch/arm/lib/board.c

@@ -262,9 +262,6 @@ init_fnc_t *init_sequence[] = {
 	init_func_i2c,
 #endif
 	dram_init,		/* configure available RAM banks */
-#if defined(CONFIG_CMD_PCI) || defined (CONFIG_PCI)
-	arm_pci_init,
-#endif
 	NULL,
 };
 
@@ -344,17 +341,6 @@ void board_init_f (ulong bootflag)
 	addr &= ~(4096 - 1);
 	debug ("Top of RAM usable for U-Boot at: %08lx\n", addr);
 
-#ifdef CONFIG_VFD
-#	ifndef PAGE_SIZE
-#	  define PAGE_SIZE 4096
-#	endif
-	/*
-	 * reserve memory for VFD display (always full pages)
-	 */
-	addr -= vfd_setmem (addr);
-	gd->fb_base = addr;
-#endif /* CONFIG_VFD */
-
 #ifdef CONFIG_LCD
 #ifdef CONFIG_FB_ADDR
 	gd->fb_base = CONFIG_FB_ADDR;
@@ -533,10 +519,9 @@ void board_init_r (gd_t *id, ulong dest_addr)
 	/* initialize environment */
 	env_relocate ();
 
-#ifdef CONFIG_VFD
-	/* must do this after the framebuffer is allocated */
-	drv_vfd_init();
-#endif /* CONFIG_VFD */
+#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
+	arm_pci_init();
+#endif
 
 	/* IP Address */
 	gd->bd->bi_ip_addr = getenv_IPaddr ("ipaddr");

board/actux1/actux1.c

@@ -37,49 +37,57 @@
 #include <asm/arch/ixp425.h>
 #include <asm/io.h>
 #include <miiphy.h>
+#ifdef CONFIG_PCI
+#include <pci.h>
+#include <asm/arch/ixp425pci.h>
+#endif
 
 #include "actux1_hw.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int board_init (void)
+int board_early_init_f(void)
+{
+	/* CS5: Debug port */
+	writel(0x9d520003, IXP425_EXP_CS5);
+	/* CS6: HwRel */
+	writel(0x81860001, IXP425_EXP_CS6);
+	/* CS7: LEDs */
+	writel(0x80900003, IXP425_EXP_CS7);
+	return 0;
+}
+
+int board_init(void)
 {
 	gd->bd->bi_arch_number = MACH_TYPE_ACTUX1;
 
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = 0x00000100;
 
-	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST);
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_IORST);
+	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST);
 
-	/* Setup GPIO's for PCI INTA */
-	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_PCI1_INTA);
-	GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_PCI1_INTA);
+	/* Setup GPIOs for PCI INTA */
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI1_INTA);
+	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI1_INTA);
 
-	/* Setup GPIO's for 33MHz clock output */
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_PCI_CLK);
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_EXTBUS_CLK);
-	*IXP425_GPIO_GPCLKR = 0x011001FF;
+	/* Setup GPIOs for 33MHz clock output */
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK);
+	writel(0x011001FF, IXP425_GPIO_GPCLKR);
 
-	/* CS5: Debug port */
-	*IXP425_EXP_CS5 = 0x9d520003;
-	/* CS6: HwRel */
-	*IXP425_EXP_CS6 = 0x81860001;
-	/* CS7: LEDs */
-	*IXP425_EXP_CS7 = 0x80900003;
+	udelay(533);
+	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST);
 
-	udelay (533);
-	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST);
+	ACTUX1_LED1(2);
+	ACTUX1_LED2(2);
+	ACTUX1_LED3(0);
+	ACTUX1_LED4(0);
+	ACTUX1_LED5(0);
+	ACTUX1_LED6(0);
+	ACTUX1_LED7(0);
 
-	ACTUX1_LED1 (2);
-	ACTUX1_LED2 (2);
-	ACTUX1_LED3 (0);
-	ACTUX1_LED4 (0);
-	ACTUX1_LED5 (0);
-	ACTUX1_LED6 (0);
-	ACTUX1_LED7 (0);
-
-	ACTUX1_HS (ACTUX1_HS_DCD);
+	ACTUX1_HS(ACTUX1_HS_DCD);
 
 	return 0;
 }
@@ -87,21 +95,21 @@ int board_init (void)
 /*
  * Check Board Identity
  */
-int checkboard (void)
+int checkboard(void)
 {
 	char buf[64];
 	int i = getenv_f("serial#", buf, sizeof(buf));
 
-	puts ("Board: AcTux-1 rev.");
-	putc (ACTUX1_BOARDREL + 'A' - 1);
+	puts("Board: AcTux-1 rev.");
+	putc(ACTUX1_BOARDREL + 'A' - 1);
 
 	if (i > 0) {
 		puts(", serial# ");
 		puts(buf);
 	}
-	putc ('\n');
+	putc('\n');
 
-	return (0);
+	return 0;
 }
 
 /*************************************************************************
@@ -110,39 +118,36 @@ int checkboard (void)
  * 1 = Rev. A
  * 2 = Rev. B
  *************************************************************************/
-u32 get_board_rev (void)
+u32 get_board_rev(void)
 {
 	return ACTUX1_BOARDREL;
 }
 
-int dram_init (void)
+int dram_init(void)
 {
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
-	return (0);
+	gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20);
+	return 0;
 }
 
-#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
-extern struct pci_controller hose;
-extern void pci_ixp_init (struct pci_controller *hose);
 
-void pci_init_board (void)
+#ifdef CONFIG_PCI
+struct pci_controller hose;
+
+void pci_init_board(void)
 {
-	extern void pci_ixp_init (struct pci_controller *hose);
-	pci_ixp_init (&hose);
+	pci_ixp_init(&hose);
 }
 #endif
 
-void reset_phy (void)
+void reset_phy(void)
 {
 	u16 id1, id2;
 
 	/* initialize the PHY */
-	miiphy_reset ("NPE0", CONFIG_PHY_ADDR);
+	miiphy_reset("NPE0", CONFIG_PHY_ADDR);
 
-	miiphy_read ("NPE0", CONFIG_PHY_ADDR, MII_PHYSID1, &id1);
-	miiphy_read ("NPE0", CONFIG_PHY_ADDR, MII_PHYSID2, &id2);
+	miiphy_read("NPE0", CONFIG_PHY_ADDR, MII_PHYSID1, &id1);
+	miiphy_read("NPE0", CONFIG_PHY_ADDR, MII_PHYSID2, &id2);
 
 	id2 &= 0xFFF0;		/* mask out revision bits */
 
@@ -153,9 +158,9 @@ void reset_phy (void)
 		 * LED2 (unused) = LINK,
 		 * LED3(red) = Coll
 		 */
-		miiphy_write ("NPE0", CONFIG_PHY_ADDR, 20, 0xD432);
+		miiphy_write("NPE0", CONFIG_PHY_ADDR, 20, 0xD432);
 	} else if (id1 == 0x143 && id2 == 0xbc30) {
 		/* BCM5241: default values are OK */
 	} else
-		printf ("unknown ethernet PHY ID: %x %x\n", id1, id2);
+		printf("unknown ethernet PHY ID: %x %x\n", id1, id2);
 }

board/actux1/config.mk

@@ -1,4 +0,0 @@
-CONFIG_SYS_TEXT_BASE = 0x00e00000
-
-# include NPE ethernet driver
-BOARDLIBS = arch/arm/cpu/ixp/npe/libnpe.o

board/actux1/u-boot.lds

@@ -30,15 +30,15 @@ SECTIONS
 
 	. = ALIGN (4);
 	.text : {
-		arch/arm/cpu/ixp/start.o(.text)
-		lib/string.o(.text)
-		lib/vsprintf.o(.text)
-		arch/arm/lib/board.o(.text)
-		common/dlmalloc.o(.text)
-		arch/arm/cpu/ixp/cpu.o(.text)
+		arch/arm/cpu/ixp/start.o(.text*)
+		net/libnet.o(.text*)
+		board/actux1/libactux1.o(.text*)
+		arch/arm/cpu/ixp/libixp.o(.text*)
+		drivers/serial/libserial.o(.text*)
+
 		. = env_offset;
 		common/env_embedded.o(.ppcenv)
-		* (.text)
+		*(.text*)
 	}
 
 	. = ALIGN (4);
@@ -47,7 +47,7 @@ SECTIONS
 	}
 	. = ALIGN (4);
 	.data : {
-		*(.data)
+		*(.data*)
 	}
 	. = ALIGN (4);
 	.got : {
@@ -61,10 +61,27 @@ SECTIONS
 	__u_boot_cmd_end =.;
 
 	. = ALIGN (4);
-	__bss_start =.;
-	.bss (NOLOAD): {
-		*(.bss)
-		. = ALIGN(4);
+	.rel.dyn : {
+		__rel_dyn_start = .;
+		*(.rel*)
+		__rel_dyn_end = .;
+	}
+
+	.dynsym : {
+		__dynsym_start = .;
+		*(.dynsym)
+	}
+
+	.bss __rel_dyn_start (OVERLAY) : {
+		__bss_start = .;
+		*(.bss*)
+		 . = ALIGN(4);
+		_end = .;
 	}
 	__bss_end__ =.;
+	/DISCARD/ : { *(.dynstr*) }
+	/DISCARD/ : { *(.dynamic*) }
+	/DISCARD/ : { *(.plt*) }
+	/DISCARD/ : { *(.interp*) }
+	/DISCARD/ : { *(.gnu*) }
 }

board/actux2/actux2.c

@@ -43,50 +43,55 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int board_init (void)
+int board_early_init_f(void)
+{
+	/* CS1: IPAC-X */
+	writel(0x94d10013, IXP425_EXP_CS1);
+	/* CS5: Debug port */
+	writel(0x9d520003, IXP425_EXP_CS5);
+	/* CS6: HW release register */
+	writel(0x81860001, IXP425_EXP_CS6);
+	/* CS7: LEDs */
+	writel(0x80900003, IXP425_EXP_CS7);
+
+	return 0;
+}
+
+int board_init(void)
 {
 	gd->bd->bi_arch_number = MACH_TYPE_ACTUX2;
 
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = 0x00000100;
 
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_IORST);
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_ETHRST);
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_DSR);
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_DCD);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_ETHRST);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DSR);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DCD);
 
-	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST);
-	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_ETHRST);
+	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST);
+	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_ETHRST);
 
-	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_DSR);
-	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_DCD);
+	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DSR);
+	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_DCD);
 
-	/* Setup GPIO's for Interrupt inputs */
-	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_DBGINT);
-	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_ETHINT);
+	/* Setup GPIOs for Interrupt inputs */
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_DBGINT);
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_ETHINT);
 
-	/* Setup GPIO's for 33MHz clock output */
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_PCI_CLK);
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_EXTBUS_CLK);
-	*IXP425_GPIO_GPCLKR = 0x011001FF;
+	/* Setup GPIOs for 33MHz clock output */
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK);
+	writel(0x011001FF, IXP425_GPIO_GPCLKR);
 
-	/* CS1: IPAC-X */
-	*IXP425_EXP_CS1 = 0x94d10013;
-	/* CS5: Debug port */
-	*IXP425_EXP_CS5 = 0x9d520003;
-	/* CS6: HW release register */
-	*IXP425_EXP_CS6 = 0x81860001;
-	/* CS7: LEDs */
-	*IXP425_EXP_CS7 = 0x80900003;
+	udelay(533);
+	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST);
+	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_ETHRST);
 
-	udelay (533);
-	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST);
-	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_ETHRST);
-
-	ACTUX2_LED1 (1);
-	ACTUX2_LED2 (0);
-	ACTUX2_LED3 (0);
-	ACTUX2_LED4 (0);
+	ACTUX2_LED1(1);
+	ACTUX2_LED2(0);
+	ACTUX2_LED3(0);
+	ACTUX2_LED4(0);
 
 	return 0;
 }
@@ -94,29 +99,27 @@ int board_init (void)
 /*
  * Check Board Identity
  */
-int checkboard (void)
+int checkboard(void)
 {
 	char buf[64];
 	int i = getenv_f("serial#", buf, sizeof(buf));
 
-	puts ("Board: AcTux-2 rev.");
-	putc (ACTUX2_BOARDREL + 'A' - 1);
+	puts("Board: AcTux-2 rev.");
+	putc(ACTUX2_BOARDREL + 'A' - 1);
 
 	if (i > 0) {
 		puts(", serial# ");
 		puts(buf);
 	}
-	putc ('\n');
+	putc('\n');
 
-	return (0);
+	return 0;
 }
 
-int dram_init (void)
+int dram_init(void)
 {
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
-	return (0);
+	gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20);
+	return 0;
 }
 
 /*************************************************************************
@@ -125,13 +128,13 @@ int dram_init (void)
  * 1 = Rev. A
  * 2 = Rev. B
  *************************************************************************/
-u32 get_board_rev (void)
+u32 get_board_rev(void)
 {
 	return ACTUX2_BOARDREL;
 }
 
-void reset_phy (void)
+void reset_phy(void)
 {
 	/* init IcPlus IP175C ethernet switch to native IP175C mode */
-	miiphy_write ("NPE0", 29, 31, 0x175C);
+	miiphy_write("NPE0", 29, 31, 0x175C);
 }

board/actux2/config.mk

@@ -1,4 +0,0 @@
-CONFIG_SYS_TEXT_BASE = 0x00e00000
-
-# include NPE ethernet driver
-BOARDLIBS = arch/arm/cpu/ixp/npe/libnpe.o

board/actux2/u-boot.lds

@@ -30,34 +30,29 @@ SECTIONS
 
 	. = ALIGN (4);
 	.text : {
-		arch/arm/cpu/ixp/start.o(.text)
-		lib/string.o(.text)
-		lib/vsprintf.o(.text)
-		arch/arm/lib/board.o(.text)
-		common/dlmalloc.o(.text)
-		arch/arm/cpu/ixp/cpu.o(.text)
+		arch/arm/cpu/ixp/start.o(.text*)
+		net/libnet.o(.text*)
+		board/actux2/libactux2.o(.text*)
+		arch/arm/cpu/ixp/libixp.o(.text*)
+		drivers/serial/libserial.o(.text*)
 
 		. = env_offset;
-		common/env_embedded.o (.ppcenv)
-
-		* (.text)
+		common/env_embedded.o(.ppcenv)
+		*(.text*)
 	}
 
 	. = ALIGN (4);
 	.rodata : {
 		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
 	}
-
 	. = ALIGN (4);
 	.data : {
-		*(.data)
+		*(.data*)
 	}
-
 	. = ALIGN (4);
 	.got : {
 		*(.got)
 	}
-
 	. =.;
 	__u_boot_cmd_start =.;
 	.u_boot_cmd : {
@@ -66,10 +61,27 @@ SECTIONS
 	__u_boot_cmd_end =.;
 
 	. = ALIGN (4);
-	__bss_start =.;
-	.bss (NOLOAD): {
-		*(.bss)
-		. = ALIGN(4);
+	.rel.dyn : {
+		__rel_dyn_start = .;
+		*(.rel*)
+		__rel_dyn_end = .;
+	}
+
+	.dynsym : {
+		__dynsym_start = .;
+		*(.dynsym)
+	}
+
+	.bss __rel_dyn_start (OVERLAY) : {
+		__bss_start = .;
+		*(.bss*)
+		 . = ALIGN(4);
+		_end = .;
 	}
 	__bss_end__ =.;
+	/DISCARD/ : { *(.dynstr*) }
+	/DISCARD/ : { *(.dynamic*) }
+	/DISCARD/ : { *(.plt*) }
+	/DISCARD/ : { *(.interp*) }
+	/DISCARD/ : { *(.gnu*) }
 }

board/actux3/actux3.c

@@ -36,72 +36,76 @@
 #include <malloc.h>
 #include <asm/arch/ixp425.h>
 #include <asm/io.h>
-
 #include <miiphy.h>
-
 #include "actux3_hw.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int board_init (void)
+int board_early_init_f(void)
+{
+	/* CS1: IPAC-X */
+	writel(0x94d10013, IXP425_EXP_CS1);
+	/* CS5: Debug port */
+	writel(0x9d520003, IXP425_EXP_CS5);
+	/* CS6: Release/Option register */
+	writel(0x81860001, IXP425_EXP_CS6);
+	/* CS7: LEDs */
+	writel(0x80900003, IXP425_EXP_CS7);
+
+	return 0;
+}
+
+int board_init(void)
 {
 	gd->bd->bi_arch_number = MACH_TYPE_ACTUX3;
 
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = 0x00000100;
 
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_IORST);
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_ETHRST);
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_DSR);
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_DCD);
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED5_GN);
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED6_RT);
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED6_GN);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_ETHRST);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DSR);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DCD);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED5_GN);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED6_RT);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED6_GN);
 
-	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST);
-	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_ETHRST);
+	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST);
+	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_ETHRST);
 
-	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_DSR);
-	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_DCD);
+	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DSR);
+	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_DCD);
 
-	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_LED5_GN);
-	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_LED6_RT);
-	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_LED6_GN);
+	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_LED5_GN);
+	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_LED6_RT);
+	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_LED6_GN);
 
 	/*
 	 * Setup GPIO's for Interrupt inputs
 	 */
-	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_DBGINT);
-	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_ETHINT);
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_DBGINT);
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_ETHINT);
 
 	/*
 	 * Setup GPIO's for 33MHz clock output
 	 */
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_PCI_CLK);
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_EXTBUS_CLK);
-	*IXP425_GPIO_GPCLKR = 0x011001FF;
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK);
+	writel(0x011001FF, IXP425_GPIO_GPCLKR);
 
-	/* CS1: IPAC-X */
-	*IXP425_EXP_CS1 = 0x94d10013;
-	/* CS5: Debug port */
-	*IXP425_EXP_CS5 = 0x9d520003;
-	/* CS6: Release/Option register */
-	*IXP425_EXP_CS6 = 0x81860001;
-	/* CS7: LEDs */
-	*IXP425_EXP_CS7 = 0x80900003;
+	/* we need a minimum PCI reset pulse width after enabling the clock */
+	udelay(533);
+	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST);
+	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_ETHRST);
 
-	udelay (533);
-	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST);
-	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_ETHRST);
-
-	ACTUX3_LED1_RT (1);
-	ACTUX3_LED1_GN (0);
-	ACTUX3_LED2_RT (0);
-	ACTUX3_LED2_GN (0);
-	ACTUX3_LED3_RT (0);
-	ACTUX3_LED3_GN (0);
-	ACTUX3_LED4_GN (0);
-	ACTUX3_LED5_RT (0);
+	ACTUX3_LED1_RT(1);
+	ACTUX3_LED1_GN(0);
+	ACTUX3_LED2_RT(0);
+	ACTUX3_LED2_GN(0);
+	ACTUX3_LED3_RT(0);
+	ACTUX3_LED3_GN(0);
+	ACTUX3_LED4_GN(0);
+	ACTUX3_LED5_RT(0);
 
 	return 0;
 }
@@ -109,21 +113,21 @@ int board_init (void)
 /*
  * Check Board Identity
  */
-int checkboard (void)
+int checkboard(void)
 {
 	char buf[64];
 	int i = getenv_f("serial#", buf, sizeof(buf));
 
-	puts ("Board: AcTux-3 rev.");
-	putc (ACTUX3_BOARDREL + 'A' - 1);
+	puts("Board: AcTux-3 rev.");
+	putc(ACTUX3_BOARDREL + 'A' - 1);
 
 	if (i > 0) {
 		puts (", serial# ");
 		puts (buf);
 	}
-	putc ('\n');
+	putc('\n');
 
-	return (0);
+	return 0;
 }
 
 /*************************************************************************
@@ -132,34 +136,32 @@ int checkboard (void)
  * 1 = Rev. A
  * 2 = Rev. B
  *************************************************************************/
-u32 get_board_rev (void)
+u32 get_board_rev(void)
 {
 	return ACTUX3_BOARDREL;
 }
 
-int dram_init (void)
+int dram_init(void)
 {
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
-	return (0);
+	gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20);
+	return 0;
 }
 
-void reset_phy (void)
+void reset_phy(void)
 {
 	int i;
 
 	/* initialize the PHY */
-	miiphy_reset ("NPE0", CONFIG_PHY_ADDR);
+	miiphy_reset("NPE0", CONFIG_PHY_ADDR);
 
 	/* all LED outputs = Link/Act */
-	miiphy_write ("NPE0", CONFIG_PHY_ADDR, 0x16, 0x0AAA);
+	miiphy_write("NPE0", CONFIG_PHY_ADDR, 0x16, 0x0AAA);
 
 	/*
 	 * The Marvell 88E6060 switch comes up with all ports disabled.
 	 * set all ethernet switch ports to forwarding state
 	*/
 	for (i = 1; i <= 5; i++)
-		miiphy_write ("NPE0", CONFIG_PHY_ADDR + 8 + i, 0x04, 0x03);
+		miiphy_write("NPE0", CONFIG_PHY_ADDR + 8 + i, 0x04, 0x03);
 
 }

board/actux3/config.mk

@@ -1,4 +0,0 @@
-CONFIG_SYS_TEXT_BASE = 0x00e00000
-
-# include NPE ethernet driver
-BOARDLIBS = arch/arm/cpu/ixp/npe/libnpe.o

board/actux3/u-boot.lds

@@ -30,34 +30,29 @@ SECTIONS
 
 	. = ALIGN (4);
 	.text : {
-		arch/arm/cpu/ixp/start.o (.text)
-		lib/string.o (.text)
-		lib/vsprintf.o (.text)
-		arch/arm/lib/board.o (.text)
-		common/dlmalloc.o (.text)
-		arch/arm/cpu/ixp/cpu.o (.text)
+		arch/arm/cpu/ixp/start.o(.text*)
+		net/libnet.o(.text*)
+		board/actux3/libactux3.o(.text*)
+		arch/arm/cpu/ixp/libixp.o(.text*)
+		drivers/serial/libserial.o(.text*)
 
 		. = env_offset;
-		common/env_embedded.o (.ppcenv)
-
-		* (.text)
+		common/env_embedded.o(.ppcenv)
+		*(.text*)
 	}
 
-	. = ALIGN (4);
+	. = ALIGN(4);
 	.rodata : {
 		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
 	}
-
-	. = ALIGN (4);
+	. = ALIGN(4);
 	.data : {
-		*(.data)
+		*(.data*)
 	}
-
-	. = ALIGN (4);
+	. = ALIGN(4);
 	.got : {
 		*(.got)
 	}
-
 	. =.;
 	__u_boot_cmd_start =.;
 	.u_boot_cmd : {
@@ -66,10 +61,27 @@ SECTIONS
 	__u_boot_cmd_end =.;
 
 	. = ALIGN (4);
-	__bss_start =.;
-	.bss (NOLOAD): {
-		*(.bss)
-		. = ALIGN(4);
+	.rel.dyn : {
+		__rel_dyn_start = .;
+		*(.rel*)
+		__rel_dyn_end = .;
+	}
+
+	.dynsym : {
+		__dynsym_start = .;
+		*(.dynsym)
+	}
+
+	.bss __rel_dyn_start (OVERLAY) : {
+		__bss_start = .;
+		*(.bss*)
+		 . = ALIGN(4);
+		_end = .;
 	}
 	__bss_end__ =.;
+	/DISCARD/ : { *(.dynstr*) }
+	/DISCARD/ : { *(.dynamic*) }
+	/DISCARD/ : { *(.plt*) }
+	/DISCARD/ : { *(.interp*) }
+	/DISCARD/ : { *(.gnu*) }
 }

board/actux4/actux4.c

@@ -35,92 +35,107 @@
 #include <command.h>
 #include <malloc.h>
 #include <asm/arch/ixp425.h>
-
+#include <asm/io.h>
 #include <miiphy.h>
+#ifdef CONFIG_PCI
+#include <pci.h>
+#include <asm/arch/ixp425pci.h>
+#endif
 
 #include "actux4_hw.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int board_init (void)
+int board_early_init_f(void)
+{
+	writel(0xbd113c42, IXP425_EXP_CS1);
+	return 0;
+}
+
+int board_init(void)
 {
 	gd->bd->bi_arch_number = MACH_TYPE_ACTUX4;
 
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = 0x00000100;
 
-	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_nPWRON);
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_nPWRON);
+	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_nPWRON);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_nPWRON);
 
-	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST);
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_IORST);
+	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST);
 
 	/* led not populated on board*/
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED3);
-	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_LED3);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED3);
+	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_LED3);
 
 	/* middle LED */
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED2);
-	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_LED2);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED2);
+	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_LED2);
 
 	/* right LED */
 	/* weak pulldown = LED weak on */
-	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_LED1);
-	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_LED1);
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_LED1);
+	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_LED1);
 
 	/* Setup GPIO's for Interrupt inputs */
-	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_USBINTA);
-	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_USBINTB);
-	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_USBINTC);
-	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_RTCINT);
-	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_PCI_INTA);
-	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_PCI_INTB);
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_USBINTA);
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_USBINTB);
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_USBINTC);
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RTCINT);
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTA);
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTB);
 
-	GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_USBINTA);
-	GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_USBINTB);
-	GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_USBINTC);
-	GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_RTCINT);
-	GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_PCI_INTA);
-	GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_PCI_INTB);
+	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_USBINTA);
+	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_USBINTB);
+	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_USBINTC);
+	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RTCINT);
+	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTA);
+	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTB);
 
 	/* Setup GPIO's for 33MHz clock output */
-	*IXP425_GPIO_GPCLKR = 0x011001FF;
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_EXTBUS_CLK);
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_PCI_CLK);
+	writel(0x011001FF, IXP425_GPIO_GPCLKR);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK);
 
-	*IXP425_EXP_CS1 = 0xbd113c42;
-
-	udelay (10000);
-	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST);
-	udelay (10000);
-	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST);
-	udelay (10000);
-	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST);
+	udelay(10000);
+	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST);
+	udelay(10000);
+	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST);
+	udelay(10000);
+	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST);
 
 	return 0;
 }
 
 /* Check Board Identity */
-int checkboard (void)
+int checkboard(void)
 {
-	puts ("Board: AcTux-4\n");
-	return (0);
+	puts("Board: AcTux-4\n");
+	return 0;
 }
 
-int dram_init (void)
+int dram_init(void)
 {
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
-	return (0);
+	gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20);
+	return 0;
 }
 
+#ifdef CONFIG_PCI
+struct pci_controller hose;
+
+void pci_init_board(void)
+{
+	pci_ixp_init(&hose);
+}
+#endif
+
 /*
  * Hardcoded flash setup:
  * Flash 0 is a non-CFI SST 39VF020 flash, 8 bit flash / 8 bit bus.
  * Flash 1 is an Intel *16 flash using the CFI driver.
  */
-ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
 {
 	if (banknum == 0) {	/* non-CFI boot flash */
 		info->portwidth = 1;

board/actux4/config.mk

@@ -1,4 +0,0 @@
-CONFIG_SYS_TEXT_BASE = 0x00e00000
-
-# include NPE ethernet driver
-BOARDLIBS = arch/arm/cpu/ixp/npe/libnpe.o

board/dvlhost/Makefile

@@ -12,7 +12,7 @@
 #
 # This program is distributed in the hope that it will be useful,
 # but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 # GNU General Public License for more details.
 #
 # You should have received a copy of the GNU General Public License
@@ -25,38 +25,17 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).o
 
-COBJS	:= trab.o flash.o vfd.o cmd_trab.o memory.o tsc2000.o auto_update.o
-SOBJS	:= lowlevel_init.o
+COBJS	:= dvlhost.o watchdog.o
 
-COBJS_FKT := trab_fkt.o rs485.o tsc2000.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c) $(COBJS_FKT:.o=.c)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-OBJS_FKT := $(addprefix $(obj),$(COBJS_FKT))
-
-LOAD_ADDR = 0xc100000
-
-#########################################################################
-
-all:	$(LIB) $(obj)trab_fkt.srec $(obj)trab_fkt.bin
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-$(obj)trab_fkt.srec:	$(OBJS_FKT) $(LIB)
-	$(LD) -g -Ttext $(LOAD_ADDR) -o $(<:.o=) -e trab_fkt $^ $(LIB) \
-		-L$(obj)../../examples/standalone -lstubs \
-		-L$(obj)../../lib -lgeneric \
-		$(PLATFORM_LIBS)
-	$(OBJCOPY) -O srec $(<:.o=) $@
-
-$(obj)trab_fkt.bin:	$(obj)trab_fkt.srec
-	$(OBJCOPY) -I srec -O binary $< $@
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
 
 clean:
-	rm -f $(SOBJS) $(OBJS) $(OBJS_FKT)
+	rm -f $(SOBJS) $(OBJS)
 
 distclean:	clean
 	rm -f $(LIB) core *.bak $(obj).depend

board/dvlhost/dvlhost.c

@@ -0,0 +1,130 @@
+/*
+ * (C) Copyright 2009
+ * Michael Schwingen, michael@schwingen.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <malloc.h>
+#include <asm/arch/ixp425.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#ifdef CONFIG_PCI
+#include <pci.h>
+#include <asm/arch/ixp425pci.h>
+#endif
+
+#include "dvlhost_hw.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	/* CS1: LED Latch */
+	writel(0xBFFF0002, IXP425_EXP_CS1);
+	return 0;
+}
+
+int board_init(void)
+{
+	gd->bd->bi_arch_number = MACH_TYPE_DVLHOST;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x00000100;
+
+	/* Setup GPIOs used as output */
+	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_WDGTRIGGER);
+	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_DLAN_PAIRING);
+	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PCIRST);
+
+	/*
+	 * LED latch enable and watchdog enable are tied to the same GPIO,
+	 * so we need to trigger the watchdog if we want to enable the LEDs.
+	*/
+#ifdef CONFIG_HW_WATCHDOG
+	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_WDG_LED_EN);
+#else
+	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_WDG_LED_EN);
+#endif
+
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_WDGTRIGGER);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DLAN_PAIRING);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_WDG_LED_EN);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCIRST);
+
+	/* Setup GPIOs for Interrupt inputs */
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_BTN_WLAN);
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_BTN_PAIRING);
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_BTN_RESET);
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_IRQA);
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_IRQB);
+
+	/* Setup GPIO's for 33MHz clock output */
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK);
+	writel(0x01FF01FF, IXP425_GPIO_GPCLKR);
+
+	/* turn off all LEDs */
+	writew(0x0000, DVLHOST_LED_LATCH);
+
+	udelay(533);
+	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_PCIRST);
+
+	return 0;
+}
+
+/* Check Board Identity */
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+
+	puts("Board: dLAN 200AV (dvlhost)");
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20);
+	return 0;
+}
+
+#ifdef CONFIG_PCI
+struct pci_controller hose;
+
+void pci_init_board(void)
+{
+	pci_ixp_init(&hose);
+}
+#endif
+
+void reset_phy(void)
+{
+	/* init IcPlus IP175C ethernet switch to native IP175C mode */
+	miiphy_write("NPE1", 29, 31, 0x175C);
+}

board/dvlhost/dvlhost_hw.h

@@ -0,0 +1,47 @@
+/*
+ * (C) Copyright 2009
+ * Michael Schwingen, michael@schwingen.org
+ *
+ * hardware register definitions for the
+ * dLAN200 AV Wireless G ("dvlhost") board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _DVLHOST_HW_H
+#define _DVLHOST_HW_H
+
+/*
+ * GPIO settings
+ */
+#define CONFIG_SYS_GPIO_WDGTRIGGER	0 /* Out */
+#define CONFIG_SYS_GPIO_BTN_WLAN	1
+#define CONFIG_SYS_GPIO_BTN_PAIRING	6
+#define CONFIG_SYS_GPIO_DLAN_PAIRING	7 /* Out */
+#define CONFIG_SYS_GPIO_BTN_RESET	9
+#define CONFIG_SYS_GPIO_IRQB		10
+#define CONFIG_SYS_GPIO_IRQA		11
+#define CONFIG_SYS_GPIO_WDG_LED_EN	12 /* Out */
+#define CONFIG_SYS_GPIO_PCIRST		13 /* Out */
+#define CONFIG_SYS_GPIO_PCI_CLK		14 /* Out */
+#define CONFIG_SYS_GPIO_EXTBUS_CLK	15 /* Out */
+
+#define DVLHOST_LED_LATCH	IXP425_EXP_BUS_CS1_BASE_PHYS
+
+#endif

board/dvlhost/u-boot.lds

@@ -0,0 +1,87 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT ("elf32-bigarm", "elf32-bigarm", "elf32-bigarm")
+OUTPUT_ARCH (arm)
+ENTRY (_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN (4);
+	.text : {
+		arch/arm/cpu/ixp/start.o(.text*)
+		net/libnet.o(.text*)
+		board/dvlhost/libdvlhost.o(.text*)
+		arch/arm/cpu/ixp/libixp.o(.text*)
+		drivers/serial/libserial.o(.text*)
+
+		. = env_offset;
+		common/env_embedded.o(.ppcenv)
+		*(.text*)
+	}
+
+	. = ALIGN (4);
+	.rodata : {
+		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+	}
+	. = ALIGN (4);
+	.data : {
+		*(.data*)
+	}
+	. = ALIGN (4);
+	.got : {
+		*(.got)
+	}
+	. =.;
+	__u_boot_cmd_start =.;
+	.u_boot_cmd : {
+		*(.u_boot_cmd)
+	}
+	__u_boot_cmd_end =.;
+
+	. = ALIGN (4);
+	.rel.dyn : {
+		__rel_dyn_start = .;
+		*(.rel*)
+		__rel_dyn_end = .;
+	}
+
+	.dynsym : {
+		__dynsym_start = .;
+		*(.dynsym)
+	}
+
+	.bss __rel_dyn_start (OVERLAY) : {
+		__bss_start = .;
+		*(.bss*)
+		 . = ALIGN(4);
+		_end = .;
+	}
+	__bss_end__ =.;
+	/DISCARD/ : { *(.dynstr*) }
+	/DISCARD/ : { *(.dynamic*) }
+	/DISCARD/ : { *(.plt*) }
+	/DISCARD/ : { *(.interp*) }
+	/DISCARD/ : { *(.gnu*) }
+}

board/dvlhost/watchdog.c

@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2009
+ * Michael Schwingen, michael@schwingen.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include "dvlhost_hw.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_HW_WATCHDOG
+#include <watchdog.h>
+#include <asm/arch/ixp425.h>
+
+void hw_watchdog_reset(void)
+{
+	unsigned int x;
+	x = readl(IXP425_GPIO_GPOUTR);
+	x ^= (1 << (CONFIG_SYS_GPIO_WDGTRIGGER));
+	writel(x, IXP425_GPIO_GPOUTR);
+}
+
+#endif /* CONFIG_HW_WATCHDOG */

board/ixdp425/config.mk

@@ -1,2 +0,0 @@
-#
-CONFIG_SYS_TEXT_BASE = 0x00f80000

board/ixdp425/flash.c

@@ -1,427 +0,0 @@
-/*
- * (C) Copyright 2001
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <linux/byteorder/swab.h>
-
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips        */
-
-/* Board support for 1 or 2 flash devices */
-#undef FLASH_PORT_WIDTH32
-#define FLASH_PORT_WIDTH16
-
-#ifdef FLASH_PORT_WIDTH16
-#define FLASH_PORT_WIDTH	ushort
-#define FLASH_PORT_WIDTHV	vu_short
-#define SWAP(x)			x
-#else
-#define FLASH_PORT_WIDTH	ulong
-#define FLASH_PORT_WIDTHV	vu_long
-#define SWAP(x)			__swab32(x)
-#endif
-
-#define FPW	FLASH_PORT_WIDTH
-#define FPWV	FLASH_PORT_WIDTHV
-
-#define mb()	__asm__ __volatile__ ("" : : : "memory")
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (FPW * addr, flash_info_t * info);
-static int write_data (flash_info_t * info, ulong dest, FPW data);
-static void flash_get_offsets (ulong base, flash_info_t * info);
-void inline spin_wheel (void);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
-	int i;
-	ulong size = 0;
-
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
-		switch (i) {
-		case 0:
-			flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
-			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
-			break;
-		default:
-			panic ("configured too many flash banks!\n");
-			break;
-		}
-		size += flash_info[i].size;
-	}
-
-	/* Protect monitor and environment sectors
-	 */
-	flash_protect (FLAG_PROTECT_SET,
-		       CONFIG_SYS_FLASH_BASE,
-		       CONFIG_SYS_FLASH_BASE + _bss_start - _armboot_start,
-		       &flash_info[0]);
-
-	flash_protect (FLAG_PROTECT_SET,
-		       CONFIG_ENV_ADDR,
-		       CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
-
-	return size;
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t * info)
-{
-	int i;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		return;
-	}
-
-	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
-		for (i = 0; i < info->sector_count; i++) {
-			info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
-			info->protect[i] = 0;
-		}
-	}
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
-	int i;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf ("missing or unknown FLASH type\n");
-		return;
-	}
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-	case FLASH_MAN_INTEL:
-		printf ("INTEL ");
-		break;
-	default:
-		printf ("Unknown Vendor ");
-		break;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_28F128J3A:
-		printf ("28F128J3A\n");
-		break;
-	default:
-		printf ("Unknown Chip Type\n");
-		break;
-	}
-
-	printf ("  Size: %ld MB in %d Sectors\n",
-		info->size >> 20, info->sector_count);
-
-	printf ("  Sector Start Addresses:");
-	for (i = 0; i < info->sector_count; ++i) {
-		if ((i % 5) == 0)
-			printf ("\n   ");
-		printf (" %08lX%s",
-			info->start[i], info->protect[i] ? " (RO)" : "     ");
-	}
-	printf ("\n");
-	return;
-}
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size (FPW * addr, flash_info_t * info)
-{
-	volatile FPW value;
-
-	/* Write auto select command: read Manufacturer ID */
-	addr[0x5555] = (FPW) 0x00AA00AA;
-	addr[0x2AAA] = (FPW) 0x00550055;
-	addr[0x5555] = (FPW) 0x00900090;
-
-	mb ();
-	value = addr[0];
-
-	switch (value) {
-
-	case (FPW) INTEL_MANUFACT:
-		info->flash_id = FLASH_MAN_INTEL;
-		break;
-
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		info->sector_count = 0;
-		info->size = 0;
-		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
-		return (0);	/* no or unknown flash  */
-	}
-
-	mb ();
-	value = addr[1];	/* device ID            */
-
-	switch (value) {
-
-	case (FPW) INTEL_ID_28F128J3A:
-		info->flash_id += FLASH_28F128J3A;
-		info->sector_count = 128;
-		info->size = 0x02000000;
-		break;		/* => 16 MB     */
-
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		break;
-	}
-
-	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
-		printf ("** ERROR: sector count %d > max (%d) **\n",
-			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
-		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
-	}
-
-	addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
-
-	return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
-	int flag, prot, sect;
-	ulong type;
-	int rcode = 0;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN) {
-			printf ("- missing\n");
-		} else {
-			printf ("- no sectors to erase\n");
-		}
-		return 1;
-	}
-
-	type = (info->flash_id & FLASH_VENDMASK);
-	if ((type != FLASH_MAN_INTEL)) {
-		printf ("Can't erase unknown flash type %08lx - aborted\n",
-			info->flash_id);
-		return 1;
-	}
-
-	prot = 0;
-	for (sect = s_first; sect <= s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-
-	if (prot) {
-		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
-	} else {
-		printf ("\n");
-	}
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts ();
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect <= s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			FPWV *addr = (FPWV *) (info->start[sect]);
-			FPW status;
-
-			printf ("Erasing sector %2d ... ", sect);
-
-			/* arm simple, non interrupt dependent timer */
-			reset_timer_masked ();
-
-			*addr = (FPW) 0x00500050;	/* clear status register */
-			*addr = (FPW) 0x00200020;	/* erase setup */
-			*addr = (FPW) 0x00D000D0;	/* erase confirm */
-
-			while (((status =
-				 *addr) & (FPW) 0x00800080) !=
-			       (FPW) 0x00800080) {
-				if (get_timer_masked () >
-				    CONFIG_SYS_FLASH_ERASE_TOUT) {
-					printf ("Timeout\n");
-					*addr = (FPW) 0x00B000B0;	/* suspend erase         */
-					*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
-					rcode = 1;
-					break;
-				}
-			}
-
-			*addr = (FPW) 0x00500050;	/* clear status register cmd.   */
-			*addr = (FPW) 0x00FF00FF;	/* resest to read mode          */
-
-			printf (" done\n");
-		}
-	}
-	return rcode;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 4 - Flash not identified
- */
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
-	ulong cp, wp;
-	FPW data;
-	int count, i, l, rc, port_width;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		return 4;
-	}
-
-/* get lower word aligned address */
-#ifdef FLASH_PORT_WIDTH16
-	wp = (addr & ~1);
-	port_width = 2;
-#else
-	wp = (addr & ~3);
-	port_width = 4;
-#endif
-
-	/*
-	 * handle unaligned start bytes
-	 */
-	if ((l = addr - wp) != 0) {
-		data = 0;
-		for (i = 0, cp = wp; i < l; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *) cp);
-		}
-		for (; i < port_width && cnt > 0; ++i) {
-			data = (data << 8) | *src++;
-			--cnt;
-			++cp;
-		}
-		for (; cnt == 0 && i < port_width; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *) cp);
-		}
-
-		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
-			return (rc);
-		}
-		wp += port_width;
-	}
-
-	/*
-	 * handle word aligned part
-	 */
-	count = 0;
-	while (cnt >= port_width) {
-		data = 0;
-		for (i = 0; i < port_width; ++i) {
-			data = (data << 8) | *src++;
-		}
-		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
-			return (rc);
-		}
-		wp += port_width;
-		cnt -= port_width;
-		if (count++ > 0x800) {
-			spin_wheel ();
-			count = 0;
-		}
-	}
-
-	if (cnt == 0) {
-		return (0);
-	}
-
-	/*
-	 * handle unaligned tail bytes
-	 */
-	data = 0;
-	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
-		data = (data << 8) | *src++;
-		--cnt;
-	}
-	for (; i < port_width; ++i, ++cp) {
-		data = (data << 8) | (*(uchar *) cp);
-	}
-
-	return (write_data (info, wp, SWAP (data)));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word or halfword to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_data (flash_info_t * info, ulong dest, FPW data)
-{
-	FPWV *addr = (FPWV *) dest;
-	ulong status;
-	int flag;
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*addr & data) != data) {
-		printf ("not erased at %08lx (%lx)\n", (ulong) addr,
-			(ulong) * addr);
-		return (2);
-	}
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts ();
-
-	*addr = (FPW) 0x00400040;	/* write setup */
-	*addr = data;
-
-	/* arm simple, non interrupt dependent timer */
-	reset_timer_masked ();
-
-	/* wait while polling the status register */
-	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
-		if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
-			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
-			return (1);
-		}
-	}
-
-	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
-
-	return (0);
-}
-
-void inline spin_wheel (void)
-{
-	static int p = 0;
-	static char w[] = "\\/-";
-
-	printf ("\010%c", w[p]);
-	(++p == 3) ? (p = 0) : 0;
-}

board/ixdp425/ixdp425.c

@@ -33,24 +33,82 @@
 #include <malloc.h>
 #include <netdev.h>
 #include <asm/arch/ixp425.h>
+#include <asm/io.h>
+#ifdef CONFIG_PCI
+#include <pci.h>
+#include <asm/arch/ixp425pci.h>
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define IXDP425_LED_PORT 0x52000000 /* 4-digit hex display */
+
+int board_early_init_f(void)
+{
+	/* CS2: LED port */
+	writel(0xbcff0002, IXP425_EXP_CS2);
+	writew(0x0001, IXDP425_LED_PORT); /* output postcode to LEDs */
+
+	return 0;
+}
+
+#ifdef CONFIG_PCI
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_ixpdp425_config_table[] = {
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, PCI_ANY_ID,
+	  pci_cfgfunc_config_device,
+	  { 0x400,
+	    0x40000000,
+	    PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER } },
+
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x01, PCI_ANY_ID,
+	  pci_cfgfunc_config_device,
+	  { 0x800,
+	    0x40010000,
+	    PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER } },
+
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x02, PCI_ANY_ID,
+	  pci_cfgfunc_config_device,
+	  { 0xc00,
+	    0x40020000,
+	    PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER } },
+
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x03, PCI_ANY_ID,
+	  pci_cfgfunc_config_device,
+	  { 0x1000,
+	    0x40030000,
+	    PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER } },
+	{ }
+};
+#endif
+
+struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table: pci_ixpdp425_config_table,
+#endif
+};
+#endif /* CONFIG_PCI */
+
+
 /*
  * Miscelaneous platform dependent initialisations
  */
-int board_init (void)
+int board_init(void)
 {
+	writew(0x0002, IXDP425_LED_PORT); /* output postcode to LEDs */
+
+#ifdef CONFIG_IXDPG425
+	/* arch number of IXDP */
+	gd->bd->bi_arch_number = MACH_TYPE_IXDPG425;
+#else
 	/* arch number of IXDP */
 	gd->bd->bi_arch_number = MACH_TYPE_IXDP425;
+#endif
 
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = 0x00000100;
 
 #ifdef CONFIG_IXDPG425
-	/* arch number of IXDP */
-	gd->bd->bi_arch_number = MACH_TYPE_IXDPG425;
-
 	/*
 	 * Get realtek RTL8305 switch and SLIC out of reset
 	 */
@@ -60,19 +118,56 @@ int board_init (void)
 	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_SLIC_RESET_N);
 
 	/*
-	 * Setup GPIO's for PCI INTA & INTB
+	 * Setup GPIOs for PCI INTA & INTB
 	 */
 	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTA_N);
 	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTA_N);
 	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTB_N);
 	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTB_N);
 
-	/*
-	 * Setup GPIO's for 33MHz clock output
-	 */
-	*IXP425_GPIO_GPCLKR = 0x01FF01FF;
+	/* Setup GPIOs for 33MHz clock output */
+	writel(0x01FF01FF, IXP425_GPIO_GPCLKR);
+
 	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK);
 	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK);
+
+	/* set GPIO8..11 interrupt type to active low */
+	writel((0x1 << 9) | (0x1 << 6) | (0x1 << 3) | 0x1, IXP425_GPIO_GPIT2R);
+
+	/* clear pending interrupts */
+	writel(-1, IXP425_GPIO_GPISR);
+
+	/* assert PCI reset */
+	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_SLIC_RESET_N);
+
+	udelay(533);
+
+	/* deassert PCI reset */
+	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_SLIC_RESET_N);
+
+	udelay(533);
+
+#else /* IXDP425 */
+	/* Setup GPIOs for 33MHz ExpBus and PCI clock output */
+	writel(0x01FF01FF, IXP425_GPIO_GPCLKR);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_RESET_N);
+
+	/* set GPIO8..11 interrupt type to active low */
+	writel((0x1 << 9) | (0x1 << 6) | (0x1 << 3) | 0x1, IXP425_GPIO_GPIT2R);
+	/* clear pending interrupts */
+	writel(-1, IXP425_GPIO_GPISR);
+
+	/* assert PCI reset */
+	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PCI_RESET_N);
+
+	udelay(533);
+
+	/* deassert PCI reset */
+	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_PCI_RESET_N);
+
+	udelay(533);
 #endif
 
 	return 0;
@@ -98,30 +193,46 @@ int checkboard(void)
 	}
 	putc('\n');
 
-	return (0);
+	return 0;
 }
 
-int dram_init (void)
+int dram_init(void)
 {
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
-
-	return (0);
+	/* we can only map 64MB via PCI, so we limit memory
+	   until a better solution is implemented. */
+#ifdef CONFIG_PCI
+	gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 64<<20);
+#else
+	gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 256<<20);
+#endif
+	return 0;
 }
 
-#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
-extern struct pci_controller hose;
-extern void pci_ixp_init(struct pci_controller * hose);
-
+#ifdef CONFIG_PCI
 void pci_init_board(void)
 {
-	extern void pci_ixp_init (struct pci_controller *hose);
-
 	pci_ixp_init(&hose);
 }
+
+/*
+ * dev 0 on the PCI bus is not the host bridge, so we have to override
+ * these functions in order to not skip PCI slot 0 during configuration.
+*/
+int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
+{
+	return 0;
+}
+int pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
+{
+	return 1;
+}
+
 #endif
 
 int board_eth_init(bd_t *bis)
 {
-	return pci_eth_init(bis);
+#ifdef CONFIG_PCI
+	pci_eth_init(bis);
+#endif
+	return cpu_eth_init(bis);
 }

board/prodrive/pdnb3/config.mk

@@ -1,2 +0,0 @@
-#
-CONFIG_SYS_TEXT_BASE = 0x01f00000

board/trab/Pt1000_temp_data.h

@@ -1,71 +0,0 @@
-/*
- * Data file for tsc2000 driver.
- * Copyright (C) 2002, 2003 DENX Software Engineering, Wolfgang Denk, wd@denx.de
- */
-
-#ifndef _PT1000_TEMP_DATA_H
-#define _PT1000_TEMP_DATA_H
-
-long Pt1000_temp_table[][2] = {
-	/* For quick range checking the largest element
-	 * is placed at index 0.
-	 * U, nV    T, C*100
-	 */
-	{ 44000000 , 12165 },
-	{ -10000000 , -2644 },
-	{ -9000000 , -2381 },
-	{ -8000000 , -2118 },
-	{ -7000000 , -1855 },
-	{ -6000000 , -1591 },
-	{ -5000000 , -1327 },
-	{ -4000000 , -1063 },
-	{ -3000000 , -798 },
-	{ -2000000 , -532 },
-	{ -1000000 , -266 },
-	{ 0 , 000 },
-	{ 1000000 , 267 },
-	{ 2000000 , 534 },
-	{ 3000000 , 802 },
-	{ 4000000 , 1070 },
-	{ 5000000 , 1338 },
-	{ 6000000 , 1607 },
-	{ 7000000 , 1876 },
-	{ 8000000 , 2146 },
-	{ 9000000 , 2416 },
-	{ 10000000 , 2687 },
-	{ 11000000 , 2958 },
-	{ 12000000 , 3230 },
-	{ 13000000 , 3502 },
-	{ 14000000 , 3774 },
-	{ 15000000 , 4047 },
-	{ 16000000 , 4321 },
-	{ 17000000 , 4595 },
-	{ 18000000 , 4869 },
-	{ 19000000 , 5144 },
-	{ 20000000 , 5419 },
-	{ 21000000 , 5694 },
-	{ 22000000 , 5971 },
-	{ 23000000 , 6247 },
-	{ 24000000 , 6524 },
-	{ 25000000 , 6802 },
-	{ 26000000 , 7080 },
-	{ 27000000 , 7358 },
-	{ 28000000 , 7637 },
-	{ 29000000 , 7916 },
-	{ 30000000 , 8196 },
-	{ 31000000 , 8476 },
-	{ 32000000 , 8757 },
-	{ 33000000 , 9039 },
-	{ 34000000 , 9320 },
-	{ 35000000 , 9602 },
-	{ 36000000 , 9885 },
-	{ 37000000 , 10168 },
-	{ 38000000 , 10452 },
-	{ 39000000 , 10736 },
-	{ 40000000 , 11021 },
-	{ 41000000 , 11306 },
-	{ 42000000 , 11592 },
-	{ 43000000 , 11879 },
-	{ 44000000 , 12165 },
-};
-#endif /* _PT1000_TEMP_DATA_H */

board/trab/README.kbd

@@ -1,44 +0,0 @@
-
-The TRAB keyboard implementation is similar to that for LWMON and
-R360MPI boards. The only difference concerns key naming. There are 4
-keys on TRAB: 1, 2, 3, 4.
-
-1) The "kbd" command provides information about the current state of
-   the keys. For example,
-
-	TRAB # kbd
-	Keys: 1 0 1 0
-
-   means that keys 1 and 3 are pressed. The keyboard status is also
-   stored in the "keybd" environment variable. In this example we get
-
-	keybd=1010
-
-2) The "preboot" variable is set according to current environment
-   settings and keys pressed. This is an example:
-
-	TRAB # setenv magic_keys XY
-	TRAB # setenv key_magicX 12
-	TRAB # setenv key_cmdX echo ## Keys 1 + 2 pressed ##\;echo
-	TRAB # setenv key_magicY 13
-	TRAB # setenv key_cmdY echo ## Keys 1 + 3 pressed ##\;echo
-
-   Here "magic_keys=XY" means that the "key_magicX" and "key_magicY"
-   variables will be checked for a match. Each variable "key_magic*"
-   defines a set of keys. In the our example, if keys 1 and 3 are
-   pressed during reset, then "key_magicY" matches, so the "preboot"
-   variable will be set to the contents of "key_cmdY":
-
-	preboot=echo ## Keys 1 + 3 pressed ##;echo
-
-3) The TRAB board has optional modem support. When a certain key
-   combination is pressed on the keyboard at power-on, the firmware
-   performs the necessary initialization of the modem and allows for
-   dial-in. The key combination is specified in the
-   "include/configs/trab.h" file. For example:
-
-	#define        CONFIG_MODEM_KEY_MAGIC  "23"
-
-   means that modem will be initialized if and only if both keys 2, 3
-   are pressed. Note that the format of this string is similar to the
-   format of "key_magic*" environment variables described above.

board/trab/auto_update.c

@@ -1,676 +0,0 @@
-/*
- * (C) Copyright 2003
- * Gary Jennejohn, DENX Software Engineering, garyj@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <command.h>
-#include <malloc.h>
-#include <image.h>
-#include <asm/byteorder.h>
-#include <usb.h>
-
-#ifdef CONFIG_SYS_HUSH_PARSER
-#include <hush.h>
-#endif
-
-#ifdef CONFIG_AUTO_UPDATE
-
-#ifndef CONFIG_USB_OHCI_NEW
-#error "must define CONFIG_USB_OHCI"
-#endif
-
-#ifndef CONFIG_USB_STORAGE
-#error "must define CONFIG_USB_STORAGE"
-#endif
-
-#ifndef CONFIG_SYS_HUSH_PARSER
-#error "must define CONFIG_SYS_HUSH_PARSER"
-#endif
-
-#if !defined(CONFIG_CMD_FAT)
-#error "must define CONFIG_CMD_FAT"
-#endif
-
-/*
- * Check whether a USB memory stick is plugged in.
- * If one is found:
- *	1) if prepare.img ist found load it into memory. If it is
- *		valid then run it.
- *	2) if preinst.img is found load it into memory. If it is
- *		valid then run it. Update the EEPROM.
- *	3) if firmw_01.img is found load it into memory. If it is valid,
- *		burn it into FLASH and update the EEPROM.
- *	4) if kernl_01.img is found load it into memory. If it is valid,
- *		burn it into FLASH and update the EEPROM.
- *	5) if app.img is found load it into memory. If it is valid,
- *		burn it into FLASH and update the EEPROM.
- *	6) if disk.img is found load it into memory. If it is valid,
- *		burn it into FLASH and update the EEPROM.
- *	7) if postinst.img is found load it into memory. If it is
- *		valid then run it. Update the EEPROM.
- */
-
-#undef AU_DEBUG
-
-#undef debug
-#ifdef	AU_DEBUG
-#define debug(fmt,args...)	printf (fmt ,##args)
-#else
-#define debug(fmt,args...)
-#endif	/* AU_DEBUG */
-
-/* possible names of files on the USB stick. */
-#define AU_PREPARE	"prepare.img"
-#define AU_PREINST	"preinst.img"
-#define AU_FIRMWARE	"firmw_01.img"
-#define AU_KERNEL	"kernl_01.img"
-#define AU_APP		"app.img"
-#define AU_DISK		"disk.img"
-#define AU_POSTINST	"postinst.img"
-
-struct flash_layout
-{
-	long start;
-	long end;
-};
-
-/* layout of the FLASH. ST = start address, ND = end address. */
-#ifndef CONFIG_FLASH_8MB			/* 16 MB Flash, 32 MB RAM */
-#define AU_FL_FIRMWARE_ST	0x00000000
-#define AU_FL_FIRMWARE_ND	0x0009FFFF
-#define AU_FL_VFD_ST		0x000A0000
-#define AU_FL_VFD_ND		0x000BFFFF
-#define AU_FL_KERNEL_ST		0x000C0000
-#define AU_FL_KERNEL_ND		0x001BFFFF
-#define AU_FL_APP_ST		0x001C0000
-#define AU_FL_APP_ND		0x005BFFFF
-#define AU_FL_DISK_ST		0x005C0000
-#define AU_FL_DISK_ND		0x00FFFFFF
-#else						/*  8 MB Flash, 32 MB RAM */
-#define AU_FL_FIRMWARE_ST	0x00000000
-#define AU_FL_FIRMWARE_ND	0x0005FFFF
-#define AU_FL_KERNEL_ST		0x00060000
-#define AU_FL_KERNEL_ND		0x0013FFFF
-#define AU_FL_APP_ST		0x00140000
-#define AU_FL_APP_ND		0x0067FFFF
-#define AU_FL_DISK_ST		0x00680000
-#define AU_FL_DISK_ND		0x007DFFFF
-#define AU_FL_VFD_ST		0x007E0000
-#define AU_FL_VFD_ND		0x007FFFFF
-#endif	/* CONFIG_FLASH_8MB */
-
-/* a structure with the offsets to values in the EEPROM */
-struct eeprom_layout
-{
-	int time;
-	int size;
-	int dcrc;
-};
-
-/* layout of the EEPROM - offset from the start. All entries are 32 bit. */
-#define AU_EEPROM_TIME_PREINST	64
-#define AU_EEPROM_SIZE_PREINST	68
-#define AU_EEPROM_DCRC_PREINST	72
-#define AU_EEPROM_TIME_FIRMWARE	76
-#define AU_EEPROM_SIZE_FIRMWARE	80
-#define AU_EEPROM_DCRC_FIRMWARE	84
-#define AU_EEPROM_TIME_KERNEL	88
-#define AU_EEPROM_SIZE_KERNEL	92
-#define AU_EEPROM_DCRC_KERNEL	96
-#define AU_EEPROM_TIME_APP	100
-#define AU_EEPROM_SIZE_APP	104
-#define AU_EEPROM_DCRC_APP	108
-#define AU_EEPROM_TIME_DISK	112
-#define AU_EEPROM_SIZE_DISK	116
-#define AU_EEPROM_DCRC_DISK	120
-#define AU_EEPROM_TIME_POSTINST 124
-#define AU_EEPROM_SIZE_POSTINST 128
-#define AU_EEPROM_DCRC_POSTINST 132
-
-static int au_usb_stor_curr_dev; /* current device */
-
-/* index of each file in the following arrays */
-#define IDX_PREPARE	0
-#define IDX_PREINST	1
-#define IDX_FIRMWARE	2
-#define IDX_KERNEL	3
-#define IDX_APP		4
-#define IDX_DISK	5
-#define IDX_POSTINST	6
-/* max. number of files which could interest us */
-#define AU_MAXFILES 7
-/* pointers to file names */
-char *aufile[AU_MAXFILES];
-/* sizes of flash areas for each file */
-long ausize[AU_MAXFILES];
-/* offsets into the EEEPROM */
-struct eeprom_layout auee_off[AU_MAXFILES] = { \
-	{0}, \
-	{AU_EEPROM_TIME_PREINST, AU_EEPROM_SIZE_PREINST, AU_EEPROM_DCRC_PREINST,}, \
-	{AU_EEPROM_TIME_FIRMWARE, AU_EEPROM_SIZE_FIRMWARE, AU_EEPROM_DCRC_FIRMWARE,}, \
-	{AU_EEPROM_TIME_KERNEL, AU_EEPROM_SIZE_KERNEL, AU_EEPROM_DCRC_KERNEL,}, \
-	{AU_EEPROM_TIME_APP, AU_EEPROM_SIZE_APP, AU_EEPROM_DCRC_APP,}, \
-	{AU_EEPROM_TIME_DISK, AU_EEPROM_SIZE_DISK, AU_EEPROM_DCRC_DISK,}, \
-	{AU_EEPROM_TIME_POSTINST, AU_EEPROM_SIZE_POSTINST, AU_EEPROM_DCRC_POSTINST,} \
-	};
-/* array of flash areas start and end addresses */
-struct flash_layout aufl_layout[AU_MAXFILES - 3] = { \
-	{AU_FL_FIRMWARE_ST, AU_FL_FIRMWARE_ND,}, \
-	{AU_FL_KERNEL_ST, AU_FL_KERNEL_ND,}, \
-	{AU_FL_APP_ST, AU_FL_APP_ND,}, \
-	{AU_FL_DISK_ST, AU_FL_DISK_ND,}, \
-};
-/* convert the index into aufile[] to an index into aufl_layout[] */
-#define FIDX_TO_LIDX(idx) ((idx) - 2)
-
-/* where to load files into memory */
-#define LOAD_ADDR ((unsigned char *)0x0C100000)
-/* the app is the largest image */
-#define MAX_LOADSZ ausize[IDX_APP]
-
-/* externals */
-extern int fat_register_device(block_dev_desc_t *, int);
-extern int file_fat_detectfs(void);
-extern long file_fat_read(const char *, void *, unsigned long);
-extern int i2c_read (unsigned char, unsigned int, int , unsigned char* , int);
-extern int i2c_write (uchar, uint, int , uchar* , int);
-#ifdef CONFIG_VFD
-extern int trab_vfd (ulong);
-extern int transfer_pic(unsigned char, unsigned char *, int, int);
-#endif
-extern int flash_sect_erase(ulong, ulong);
-extern int flash_sect_protect (int, ulong, ulong);
-extern int flash_write (char *, ulong, ulong);
-/* change char* to void* to shutup the compiler */
-extern int i2c_write_multiple (uchar, uint, int, void *, int);
-extern int i2c_read_multiple (uchar, uint, int, void *, int);
-extern int u_boot_hush_start(void);
-
-int
-au_check_cksum_valid(int idx, long nbytes)
-{
-	image_header_t *hdr;
-
-	hdr = (image_header_t *)LOAD_ADDR;
-#if defined(CONFIG_FIT)
-	if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
-		puts ("Non legacy image format not supported\n");
-		return -1;
-	}
-#endif
-
-	if (nbytes != image_get_image_size (hdr)) {
-		printf ("Image %s bad total SIZE\n", aufile[idx]);
-		return -1;
-	}
-	/* check the data CRC */
-	if (!image_check_dcrc (hdr)) {
-		printf ("Image %s bad data checksum\n", aufile[idx]);
-		return -1;
-	}
-	return 0;
-}
-
-int
-au_check_header_valid(int idx, long nbytes)
-{
-	image_header_t *hdr;
-	unsigned long checksum;
-	unsigned char buf[4];
-
-	hdr = (image_header_t *)LOAD_ADDR;
-#if defined(CONFIG_FIT)
-	if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
-		puts ("Non legacy image format not supported\n");
-		return -1;
-	}
-#endif
-
-	/* check the easy ones first */
-#undef CHECK_VALID_DEBUG
-#ifdef CHECK_VALID_DEBUG
-	printf("magic %#x %#x ", image_get_magic (hdr), IH_MAGIC);
-	printf("arch %#x %#x ", image_get_arch (hdr), IH_ARCH_ARM);
-	printf("size %#x %#lx ", image_get_data_size (hdr), nbytes);
-	printf("type %#x %#x ", image_get_type (hdr), IH_TYPE_KERNEL);
-#endif
-	if (nbytes < image_get_header_size ()) {
-		printf ("Image %s bad header SIZE\n", aufile[idx]);
-		return -1;
-	}
-	if (!image_check_magic (hdr) || !image_check_arch (hdr, IH_ARCH_ARM)) {
-		printf ("Image %s bad MAGIC or ARCH\n", aufile[idx]);
-		return -1;
-	}
-	/* check the hdr CRC */
-	if (!image_check_hcrc (hdr)) {
-		printf ("Image %s bad header checksum\n", aufile[idx]);
-		return -1;
-	}
-	/* check the type - could do this all in one gigantic if() */
-	if ((idx == IDX_FIRMWARE) &&
-		!image_check_type (hdr, IH_TYPE_FIRMWARE)) {
-		printf ("Image %s wrong type\n", aufile[idx]);
-		return -1;
-	}
-	if ((idx == IDX_KERNEL) && !image_check_type (hdr, IH_TYPE_KERNEL)) {
-		printf ("Image %s wrong type\n", aufile[idx]);
-		return -1;
-	}
-	if ((idx == IDX_DISK) && !image_check_type (hdr, IH_TYPE_FILESYSTEM)) {
-		printf ("Image %s wrong type\n", aufile[idx]);
-		return -1;
-	}
-	if ((idx == IDX_APP) && !image_check_type (hdr, IH_TYPE_RAMDISK)
-		&& !image_check_type (hdr, IH_TYPE_FILESYSTEM)) {
-		printf ("Image %s wrong type\n", aufile[idx]);
-		return -1;
-	}
-	if ((idx == IDX_PREPARE || idx == IDX_PREINST || idx == IDX_POSTINST)
-		&& !image_check_type (hdr, IH_TYPE_SCRIPT)) {
-		printf ("Image %s wrong type\n", aufile[idx]);
-		return -1;
-	}
-	/* special case for prepare.img */
-	if (idx == IDX_PREPARE)
-		return 0;
-	/* recycle checksum */
-	checksum = image_get_data_size (hdr);
-	/* for kernel and app the image header must also fit into flash */
-	if ((idx != IDX_DISK) && (idx != IDX_FIRMWARE))
-		checksum += image_get_header_size ();
-	/* check the size does not exceed space in flash. HUSH scripts */
-	/* all have ausize[] set to 0 */
-	if ((ausize[idx] != 0) && (ausize[idx] < checksum)) {
-		printf ("Image %s is bigger than FLASH\n", aufile[idx]);
-		return -1;
-	}
-	/* check the time stamp from the EEPROM */
-	/* read it in */
-	i2c_read_multiple(0x54, auee_off[idx].time, 1, buf, sizeof(buf));
-#ifdef CHECK_VALID_DEBUG
-	printf ("buf[0] %#x buf[1] %#x buf[2] %#x buf[3] %#x "
-		"as int %#x time %#x\n",
-		buf[0], buf[1], buf[2], buf[3],
-		*((unsigned int *)buf), image_get_time (hdr));
-#endif
-	/* check it */
-	if (*((unsigned int *)buf) >= image_get_time (hdr)) {
-		printf ("Image %s is too old\n", aufile[idx]);
-		return -1;
-	}
-
-	return 0;
-}
-
-/* power control defines */
-#define CPLD_VFD_BK ((volatile char *)0x04038002)
-#define POWER_OFF (1 << 1)
-
-int
-au_do_update(int idx, long sz)
-{
-	image_header_t *hdr;
-	char *addr;
-	long start, end;
-	int off, rc;
-	uint nbytes;
-
-	hdr = (image_header_t *)LOAD_ADDR;
-#if defined(CONFIG_FIT)
-	if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
-		puts ("Non legacy image format not supported\n");
-		return -1;
-	}
-#endif
-
-	/* disable the power switch */
-	*CPLD_VFD_BK |= POWER_OFF;
-
-	/* execute a script */
-	if (image_check_type (hdr, IH_TYPE_SCRIPT)) {
-		addr = (char *)((char *)hdr + image_get_header_size ());
-		/* stick a NULL at the end of the script, otherwise */
-		/* parse_string_outer() runs off the end. */
-		addr[image_get_data_size (hdr)] = 0;
-		addr += 8;
-		parse_string_outer(addr, FLAG_PARSE_SEMICOLON);
-		return 0;
-	}
-
-	start = aufl_layout[FIDX_TO_LIDX(idx)].start;
-	end = aufl_layout[FIDX_TO_LIDX(idx)].end;
-
-	/* unprotect the address range */
-	/* this assumes that ONLY the firmware is protected! */
-	if (idx == IDX_FIRMWARE) {
-#undef AU_UPDATE_TEST
-#ifdef AU_UPDATE_TEST
-		/* erase it where Linux goes */
-		start = aufl_layout[1].start;
-		end = aufl_layout[1].end;
-#endif
-		flash_sect_protect(0, start, end);
-	}
-
-	/*
-	 * erase the address range.
-	 */
-	debug ("flash_sect_erase(%lx, %lx);\n", start, end);
-	flash_sect_erase(start, end);
-	wait_ms(100);
-	/* strip the header - except for the kernel and ramdisk */
-	if (image_check_type (hdr, IH_TYPE_KERNEL) ||
-			image_check_type (hdr, IH_TYPE_RAMDISK)) {
-		addr = (char *)hdr;
-		off = image_get_header_size ();
-		nbytes = image_get_image_size (hdr);
-	} else {
-		addr = (char *)((char *)hdr + image_get_header_size ());
-#ifdef AU_UPDATE_TEST
-		/* copy it to where Linux goes */
-		if (idx == IDX_FIRMWARE)
-			start = aufl_layout[1].start;
-#endif
-		off = 0;
-		nbytes = image_get_data_size (hdr);
-	}
-
-	/* copy the data from RAM to FLASH */
-	debug ("flash_write(%p, %lx %x)\n", addr, start, nbytes);
-	rc = flash_write(addr, start, nbytes);
-	if (rc != 0) {
-		printf("Flashing failed due to error %d\n", rc);
-		return -1;
-	}
-
-	/* check the dcrc of the copy */
-	if (crc32 (0, (uchar *)(start + off), image_get_data_size (hdr)) !=
-	    image_get_dcrc (hdr)) {
-		printf ("Image %s Bad Data Checksum After COPY\n", aufile[idx]);
-		return -1;
-	}
-
-	/* protect the address range */
-	/* this assumes that ONLY the firmware is protected! */
-	if (idx == IDX_FIRMWARE)
-		flash_sect_protect(1, start, end);
-	return 0;
-}
-
-int
-au_update_eeprom(int idx)
-{
-	image_header_t *hdr;
-	int off;
-	uint32_t val;
-
-	/* special case for prepare.img */
-	if (idx == IDX_PREPARE) {
-		/* enable the power switch */
-		*CPLD_VFD_BK &= ~POWER_OFF;
-		return 0;
-	}
-
-	hdr = (image_header_t *)LOAD_ADDR;
-#if defined(CONFIG_FIT)
-	if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
-		puts ("Non legacy image format not supported\n");
-		return -1;
-	}
-#endif
-
-	/* write the time field into EEPROM */
-	off = auee_off[idx].time;
-	val = image_get_time (hdr);
-	i2c_write_multiple(0x54, off, 1, &val, sizeof(val));
-	/* write the size field into EEPROM */
-	off = auee_off[idx].size;
-	val = image_get_data_size (hdr);
-	i2c_write_multiple(0x54, off, 1, &val, sizeof(val));
-	/* write the dcrc field into EEPROM */
-	off = auee_off[idx].dcrc;
-	val = image_get_dcrc (hdr);
-	i2c_write_multiple(0x54, off, 1, &val, sizeof(val));
-	/* enable the power switch */
-	*CPLD_VFD_BK &= ~POWER_OFF;
-	return 0;
-}
-
-/*
- * this is called from board_init() after the hardware has been set up
- * and is usable. That seems like a good time to do this.
- * Right now the return value is ignored.
- */
-int
-do_auto_update(void)
-{
-	block_dev_desc_t *stor_dev;
-	long sz;
-	int i, res = 0, bitmap_first, cnt, old_ctrlc, got_ctrlc;
-	char *env;
-	long start, end;
-
-#undef ERASE_EEPROM
-#ifdef ERASE_EEPROM
-	int arr[18];
-	memset(arr, 0, sizeof(arr));
-	i2c_write_multiple(0x54, 64, 1, arr, sizeof(arr));
-#endif
-	au_usb_stor_curr_dev = -1;
-	/* start USB */
-	if (usb_stop() < 0) {
-		debug ("usb_stop failed\n");
-		return -1;
-	}
-	if (usb_init() < 0) {
-		debug ("usb_init failed\n");
-		return -1;
-	}
-	/*
-	 * check whether a storage device is attached (assume that it's
-	 * a USB memory stick, since nothing else should be attached).
-	 */
-	au_usb_stor_curr_dev = usb_stor_scan(0);
-	if (au_usb_stor_curr_dev == -1) {
-		debug ("No device found. Not initialized?\n");
-		res = -1;
-		goto xit;
-	}
-	/* check whether it has a partition table */
-	stor_dev = get_dev("usb", 0);
-	if (stor_dev == NULL) {
-		debug ("uknown device type\n");
-		res = -1;
-		goto xit;
-	}
-	if (fat_register_device(stor_dev, 1) != 0) {
-		debug ("Unable to use USB %d:%d for fatls\n",
-			au_usb_stor_curr_dev, 1);
-		res = -1;
-		goto xit;
-	}
-	if (file_fat_detectfs() != 0) {
-		debug ("file_fat_detectfs failed\n");
-	}
-
-	/* initialize the array of file names */
-	memset(aufile, 0, sizeof(aufile));
-	aufile[IDX_PREPARE] = AU_PREPARE;
-	aufile[IDX_PREINST] = AU_PREINST;
-	aufile[IDX_FIRMWARE] = AU_FIRMWARE;
-	aufile[IDX_KERNEL] = AU_KERNEL;
-	aufile[IDX_APP] = AU_APP;
-	aufile[IDX_DISK] = AU_DISK;
-	aufile[IDX_POSTINST] = AU_POSTINST;
-	/* initialize the array of flash sizes */
-	memset(ausize, 0, sizeof(ausize));
-	ausize[IDX_FIRMWARE] = (AU_FL_FIRMWARE_ND + 1) - AU_FL_FIRMWARE_ST;
-	ausize[IDX_KERNEL] = (AU_FL_KERNEL_ND + 1) - AU_FL_KERNEL_ST;
-	ausize[IDX_APP] = (AU_FL_APP_ND + 1) - AU_FL_APP_ST;
-	ausize[IDX_DISK] = (AU_FL_DISK_ND + 1) - AU_FL_DISK_ST;
-	/*
-	 * now check whether start and end are defined using environment
-	 * variables.
-	 */
-	start = -1;
-	end = 0;
-	env = getenv("firmware_st");
-	if (env != NULL)
-		start = simple_strtoul(env, NULL, 16);
-	env = getenv("firmware_nd");
-	if (env != NULL)
-		end = simple_strtoul(env, NULL, 16);
-	if (start >= 0 && end && end > start) {
-		ausize[IDX_FIRMWARE] = (end + 1) - start;
-		aufl_layout[0].start = start;
-		aufl_layout[0].end = end;
-	}
-	start = -1;
-	end = 0;
-	env = getenv("kernel_st");
-	if (env != NULL)
-		start = simple_strtoul(env, NULL, 16);
-	env = getenv("kernel_nd");
-	if (env != NULL)
-		end = simple_strtoul(env, NULL, 16);
-	if (start >= 0 && end && end > start) {
-		ausize[IDX_KERNEL] = (end + 1) - start;
-		aufl_layout[1].start = start;
-		aufl_layout[1].end = end;
-	}
-	start = -1;
-	end = 0;
-	env = getenv("app_st");
-	if (env != NULL)
-		start = simple_strtoul(env, NULL, 16);
-	env = getenv("app_nd");
-	if (env != NULL)
-		end = simple_strtoul(env, NULL, 16);
-	if (start >= 0 && end && end > start) {
-		ausize[IDX_APP] = (end + 1) - start;
-		aufl_layout[2].start = start;
-		aufl_layout[2].end = end;
-	}
-	start = -1;
-	end = 0;
-	env = getenv("disk_st");
-	if (env != NULL)
-		start = simple_strtoul(env, NULL, 16);
-	env = getenv("disk_nd");
-	if (env != NULL)
-		end = simple_strtoul(env, NULL, 16);
-	if (start >= 0 && end && end > start) {
-		ausize[IDX_DISK] = (end + 1) - start;
-		aufl_layout[3].start = start;
-		aufl_layout[3].end = end;
-	}
-	/* make certain that HUSH is runnable */
-	u_boot_hush_start();
-	/* make sure that we see CTRL-C and save the old state */
-	old_ctrlc = disable_ctrlc(0);
-
-	bitmap_first = 0;
-	/* just loop thru all the possible files */
-	for (i = 0; i < AU_MAXFILES; i++) {
-		/* just read the header */
-		sz = file_fat_read(aufile[i], LOAD_ADDR, image_get_header_size ());
-		debug ("read %s sz %ld hdr %d\n",
-			aufile[i], sz, image_get_header_size ());
-		if (sz <= 0 || sz < image_get_header_size ()) {
-			debug ("%s not found\n", aufile[i]);
-			continue;
-		}
-		if (au_check_header_valid(i, sz) < 0) {
-			debug ("%s header not valid\n", aufile[i]);
-			continue;
-		}
-		sz = file_fat_read(aufile[i], LOAD_ADDR, MAX_LOADSZ);
-		debug ("read %s sz %ld hdr %d\n",
-			aufile[i], sz, image_get_header_size ());
-		if (sz <= 0 || sz <= image_get_header_size ()) {
-			debug ("%s not found\n", aufile[i]);
-			continue;
-		}
-		if (au_check_cksum_valid(i, sz) < 0) {
-			debug ("%s checksum not valid\n", aufile[i]);
-			continue;
-		}
-#ifdef CONFIG_VFD
-		/* now that we have a valid file we can display the */
-		/* bitmap. */
-		if (bitmap_first == 0) {
-			env = getenv("bitmap2");
-			if (env == NULL) {
-				trab_vfd(0);
-			} else {
-				/* not so simple - bitmap2 is supposed to */
-				/* contain the address of the bitmap */
-				env = (char *)simple_strtoul(env, NULL, 16);
-/* NOTE: these are taken from vfd_logo.h. If that file changes then */
-/* these defines MUST also be updated! These may be wrong for bitmap2. */
-#define VFD_LOGO_WIDTH 112
-#define VFD_LOGO_HEIGHT 72
-				/* must call transfer_pic directly */
-				transfer_pic(3, (unsigned char *)env,
-					     VFD_LOGO_HEIGHT, VFD_LOGO_WIDTH);
-			}
-			bitmap_first = 1;
-		}
-#endif
-		/* this is really not a good idea, but it's what the */
-		/* customer wants. */
-		cnt = 0;
-		got_ctrlc = 0;
-		do {
-			res = au_do_update(i, sz);
-			/* let the user break out of the loop */
-			if (ctrlc() || had_ctrlc()) {
-				clear_ctrlc();
-				if (res < 0)
-					got_ctrlc = 1;
-				break;
-			}
-			cnt++;
-#ifdef AU_TEST_ONLY
-		} while (res < 0 && cnt < 3);
-		if (cnt < 3)
-#else
-		} while (res < 0);
-#endif
-		/*
-		 * it doesn't make sense to update the EEPROM if the
-		 * update was interrupted by the user due to errors.
-		 */
-		if (got_ctrlc == 0)
-			au_update_eeprom(i);
-		else
-			/* enable the power switch */
-			*CPLD_VFD_BK &= ~POWER_OFF;
-	}
-	/* restore the old state */
-	disable_ctrlc(old_ctrlc);
-xit:
-	usb_stop();
-	return res;
-}
-#endif /* CONFIG_AUTO_UPDATE */

board/trab/cmd_trab.c

@@ -1,879 +0,0 @@
-/*
- * (C) Copyright 2003
- * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#undef DEBUG
-
-#include <common.h>
-#include <command.h>
-#include <asm/arch/s3c24x0_cpu.h>
-#include <rtc.h>
-
-/*
- * TRAB board specific commands. Especially commands for burn-in and function
- * test.
- */
-#if defined(CONFIG_CMD_BSP)
-
-/* limits for valid range of VCC5V in mV  */
-#define VCC5V_MIN       4500
-#define VCC5V_MAX       5500
-
-/*
- * Test strings for EEPROM test. Length of string 2 must not exceed length of
- * string 1. Otherwise a buffer overrun could occur!
- */
-#define EEPROM_TEST_STRING_1    "0987654321 :tset a si siht"
-#define EEPROM_TEST_STRING_2    "this is a test: 1234567890"
-
-/*
- * min/max limits for valid contact temperature during burn in test (in
- * degree Centigrade * 100)
- */
-#define MIN_CONTACT_TEMP        -1000
-#define MAX_CONTACT_TEMP        +9000
-
-/* blinking frequency of status LED */
-#define LED_BLINK_FREQ          5
-
-/* delay time between burn in cycles in seconds */
-#ifndef BURN_IN_CYCLE_DELAY     /* if not defined in include/configs/trab.h */
-#define BURN_IN_CYCLE_DELAY     5
-#endif
-
-/* physical SRAM parameters */
-#define SRAM_ADDR       0x02000000 /* GCS1 */
-#define SRAM_SIZE       0x40000 /* 256 kByte */
-
-/* CPLD-Register for controlling TRAB hardware functions */
-#define CPLD_BUTTONS            ((volatile unsigned long *)0x04020000)
-#define CPLD_FILL_LEVEL         ((volatile unsigned long *)0x04008000)
-#define CPLD_ROTARY_SWITCH      ((volatile unsigned long *)0x04018000)
-#define CPLD_RS485_RE           ((volatile unsigned long *)0x04028000)
-
-/* I2C EEPROM device address */
-#define I2C_EEPROM_DEV_ADDR     0x54
-
-/* EEPROM address map */
-#define EE_ADDR_TEST                    192
-#define EE_ADDR_MAX_CYCLES              256
-#define EE_ADDR_STATUS                  258
-#define EE_ADDR_PASS_CYCLES             259
-#define EE_ADDR_FIRST_ERROR_CYCLE       261
-#define EE_ADDR_FIRST_ERROR_NUM         263
-#define EE_ADDR_FIRST_ERROR_NAME        264
-#define EE_ADDR_ACT_CYCLE               280
-
-/* Bit definitions for ADCCON */
-#define ADC_ENABLE_START     0x1
-#define ADC_READ_START       0x2
-#define ADC_STDBM            0x4
-#define ADC_INP_AIN0         (0x0 << 3)
-#define ADC_INP_AIN1         (0x1 << 3)
-#define ADC_INP_AIN2         (0x2 << 3)
-#define ADC_INP_AIN3         (0x3 << 3)
-#define ADC_INP_AIN4         (0x4 << 3)
-#define ADC_INP_AIN5         (0x5 << 3)
-#define ADC_INP_AIN6         (0x6 << 3)
-#define ADC_INP_AIN7         (0x7 << 3)
-#define ADC_PRSCEN           0x4000
-#define ADC_ECFLG            0x800
-
-/* misc */
-
-/* externals */
-extern int memory_post_tests (unsigned long start, unsigned long size);
-extern int i2c_write (uchar, uint, int , uchar* , int);
-extern int i2c_read (uchar, uint, int , uchar* , int);
-extern void tsc2000_reg_init (void);
-extern s32 tsc2000_contact_temp (void);
-extern void tsc2000_spi_init(void);
-
-/* function declarations */
-int do_dip (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
-int do_vcc5v (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
-int do_burn_in (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
-int do_contact_temp (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
-int do_burn_in_status (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
-int i2c_write_multiple (uchar chip, uint addr, int alen,
-			uchar *buffer, int len);
-int i2c_read_multiple (uchar chip, uint addr, int alen,
-			uchar *buffer, int len);
-int do_temp_log (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
-
-/* helper functions */
-static void adc_init (void);
-static int adc_read (unsigned int channel);
-static int read_dip (void);
-static int read_vcc5v (void);
-static int test_dip (void);
-static int test_vcc5v (void);
-static int test_rotary_switch (void);
-static int test_sram (void);
-static int test_eeprom (void);
-static int test_contact_temp (void);
-static void led_set (unsigned int);
-static void led_blink (void);
-static void led_init (void);
-static void sdelay (unsigned long seconds); /* delay in seconds */
-static int dummy (void);
-static int read_max_cycles(void);
-static void test_function_table_init (void);
-static void global_vars_init (void);
-static int global_vars_write_to_eeprom (void);
-
-/* globals */
-u16 max_cycles;
-u8 status;
-u16 pass_cycles;
-u16 first_error_cycle;
-u8 first_error_num;
-char first_error_name[16];
-u16 act_cycle;
-
-typedef struct test_function_s {
-	char *name;
-	int (*pf)(void);
-} test_function_t;
-
-/* max number of Burn In Functions */
-#define BIF_MAX 6
-
-/* table with burn in functions */
-test_function_t test_function[BIF_MAX];
-
-
-int do_burn_in (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	int i;
-	int cycle_status;
-
-	if (argc > 1)
-		return cmd_usage(cmdtp);
-
-	led_init ();
-	global_vars_init ();
-	test_function_table_init ();
-	tsc2000_spi_init ();
-
-	if (global_vars_write_to_eeprom () != 0) {
-		printf ("%s: error writing global_vars to eeprom\n",
-			__FUNCTION__);
-		return (1);
-	}
-
-	if (read_max_cycles () != 0) {
-		printf ("%s: error reading max_cycles from eeprom\n",
-			__FUNCTION__);
-		return (1);
-	}
-
-	if (max_cycles == 0) {
-		printf ("%s: error, burn in max_cycles = 0\n", __FUNCTION__);
-		return (1);
-	}
-
-	status = 0;
-	for (act_cycle = 1; act_cycle <= max_cycles; act_cycle++) {
-
-		cycle_status = 0;
-
-		/*
-		 * avoid timestamp overflow problem after about 68 minutes of
-		 * udelay() time.
-		 */
-		reset_timer_masked ();
-		for (i = 0; i < BIF_MAX; i++) {
-
-			/* call test function */
-			if ((*test_function[i].pf)() != 0) {
-				printf ("error in %s test\n",
-					test_function[i].name);
-
-				/* is it the first error? */
-				if (status == 0) {
-					status = 1;
-					first_error_cycle = act_cycle;
-
-					/* do not use error_num 0 */
-					first_error_num = i+1;
-					strncpy (first_error_name,
-						 test_function[i].name,
-						 sizeof (first_error_name));
-					led_set (0);
-				}
-				cycle_status = 1;
-			}
-		}
-		/* were all tests of actual cycle OK? */
-		if (cycle_status == 0)
-			pass_cycles++;
-
-		/* set status LED if no error is occoured since yet */
-		if (status == 0)
-			led_set (1);
-
-		printf ("%s: cycle %d finished\n", __FUNCTION__, act_cycle);
-
-		/* pause between cycles */
-		sdelay (BURN_IN_CYCLE_DELAY);
-	}
-
-	if (global_vars_write_to_eeprom () != 0) {
-		led_set (0);
-		printf ("%s: error writing global_vars to eeprom\n",
-			__FUNCTION__);
-		status = 1;
-	}
-
-	if (status == 0) {
-		led_blink ();   /* endless loop!! */
-		return (0);
-	} else {
-		led_set (0);
-		return (1);
-	}
-}
-
-U_BOOT_CMD(
-	burn_in,	1,	1,	do_burn_in,
-	"start burn-in test application on TRAB",
-	"\n"
-	"    -  start burn-in test application\n"
-	"       The burn-in test could took a while to finish!\n"
-	"       The content of the onboard EEPROM is modified!"
-);
-
-
-int do_dip (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	int i, dip;
-
-	if (argc > 1)
-		return cmd_usage(cmdtp);
-
-	if ((dip = read_dip ()) == -1)
-		return 1;
-
-	for (i = 0; i < 4; i++) {
-		if ((dip & (1 << i)) == 0)
-			printf("0");
-		else
-			printf("1");
-	}
-	printf("\n");
-
-	return 0;
-}
-
-U_BOOT_CMD(
-	dip,	1,	1,	do_dip,
-	"read dip switch on TRAB",
-	"\n"
-	"    - read state of dip switch (S1) on TRAB board\n"
-	"      read sequence: 1-2-3-4; ON=1; OFF=0; e.g.: \"0100\""
-);
-
-
-int do_vcc5v (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	int vcc5v;
-
-	if (argc > 1)
-		return cmd_usage(cmdtp);
-
-	if ((vcc5v = read_vcc5v ()) == -1)
-		return (1);
-
-	printf ("%d", (vcc5v / 1000));
-	printf (".%d", (vcc5v % 1000) / 100);
-	printf ("%d V\n", (vcc5v % 100) / 10) ;
-
-	return 0;
-}
-
-U_BOOT_CMD(
-	vcc5v,	1,	1,	do_vcc5v,
-	"read VCC5V on TRAB",
-	"\n"
-	"    - read actual value of voltage VCC5V"
-);
-
-
-int do_contact_temp (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	int contact_temp;
-
-	if (argc > 1)
-		return cmd_usage(cmdtp);
-
-	tsc2000_spi_init ();
-
-	contact_temp = tsc2000_contact_temp();
-	printf ("%d degree C * 100\n", contact_temp) ;
-
-	return 0;
-}
-
-U_BOOT_CMD(
-	c_temp,	1,	1,	do_contact_temp,
-	"read contact temperature on TRAB",
-	""
-	"    -  reads the onboard temperature (=contact temperature)\n"
-);
-
-
-int do_burn_in_status (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	if (argc > 1)
-		return cmd_usage(cmdtp);
-
-	if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_STATUS, 1,
-				(unsigned char*) &status, 1))
-		return (1);
-
-	if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_PASS_CYCLES, 1,
-				(unsigned char*) &pass_cycles, 2))
-		return (1);
-
-	if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_CYCLE,
-				1, (unsigned char*) &first_error_cycle, 2))
-		return (1);
-
-	if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_NUM,
-				1, (unsigned char*) &first_error_num, 1))
-		return (1);
-
-	if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_NAME,
-			       1, (unsigned char*)first_error_name,
-			       sizeof (first_error_name)))
-		return (1);
-
-	if (read_max_cycles () != 0)
-		return (1);
-
-	printf ("max_cycles = %d\n", max_cycles);
-	printf ("status = %d\n", status);
-	printf ("pass_cycles = %d\n", pass_cycles);
-	printf ("first_error_cycle = %d\n", first_error_cycle);
-	printf ("first_error_num = %d\n", first_error_num);
-	printf ("first_error_name = %.*s\n",(int) sizeof(first_error_name),
-		first_error_name);
-
-	return 0;
-}
-
-U_BOOT_CMD(
-	bis,	1,	1,	do_burn_in_status,
-	"print burn in status on TRAB",
-	"\n"
-	"    -  prints the status variables of the last burn in test\n"
-	"       stored in the onboard EEPROM on TRAB board"
-);
-
-static int read_dip (void)
-{
-	unsigned int result = 0;
-	int adc_val;
-	int i;
-
-	/***********************************************************
-	 DIP switch connection (according to wa4-cpu.sp.301.pdf, page 3):
-	   SW1 - AIN4
-	   SW2 - AIN5
-	   SW3 - AIN6
-	   SW4 - AIN7
-
-	   "On" DIP switch position short-circuits the voltage from
-	   the input channel (i.e. '0' conversion result means "on").
-	*************************************************************/
-
-	for (i = 7; i > 3; i--) {
-
-		if ((adc_val = adc_read (i)) == -1) {
-			printf ("%s: Channel %d could not be read\n",
-				 __FUNCTION__, i);
-			return (-1);
-		}
-
-		/*
-		 * Input voltage (switch open) is 1.8 V.
-		 * (Vin_High/VRef)*adc_res = (1,8V/2,5V)*1023) = 736
-		 * Set trigger at halve that value.
-		 */
-		if (adc_val < 368)
-			result |= (1 << (i-4));
-	}
-	return (result);
-}
-
-
-static int read_vcc5v (void)
-{
-	s32 result;
-
-	/* VCC5V is connected to channel 2 */
-
-	if ((result = adc_read (2)) == -1) {
-		printf ("%s: VCC5V could not be read\n", __FUNCTION__);
-		return (-1);
-	}
-	/*
-	 * Calculate voltage value. Split in two parts because there is no
-	 * floating point support.  VCC5V is connected over an resistor divider:
-	 * VCC5V=ADCval*2,5V/1023*(10K+30K)/10K.
-	 */
-	result = result * 10 * 1000 / 1023; /* result in mV */
-
-	return (result);
-}
-
-
-static int test_dip (void)
-{
-	static int first_run = 1;
-	static int first_dip;
-
-	if (first_run) {
-		if ((first_dip = read_dip ()) == -1) {
-			return (1);
-		}
-		first_run = 0;
-		debug ("%s: first_dip=%d\n", __FUNCTION__, first_dip);
-	}
-	if (first_dip != read_dip ()) {
-		return (1);
-	} else {
-		return (0);
-	}
-}
-
-
-static int test_vcc5v (void)
-{
-	int vcc5v;
-
-	if ((vcc5v = read_vcc5v ()) == -1) {
-		return (1);
-	}
-
-	if ((vcc5v > VCC5V_MAX) || (vcc5v < VCC5V_MIN)) {
-		printf ("%s: vcc5v[V/100]=%d\n", __FUNCTION__, vcc5v);
-		return (1);
-	} else {
-		return (0);
-	}
-}
-
-
-static int test_rotary_switch (void)
-{
-	static int first_run = 1;
-	static int first_rs;
-
-	if (first_run) {
-		/*
-		 * clear bits in CPLD, because they have random values after
-		 * power-up or reset.
-		 */
-		*CPLD_ROTARY_SWITCH |= (1 << 16) | (1 << 17);
-
-		first_rs = ((*CPLD_ROTARY_SWITCH >> 16) & 0x7);
-		first_run = 0;
-		debug ("%s: first_rs=%d\n", __FUNCTION__, first_rs);
-	}
-
-	if (first_rs != ((*CPLD_ROTARY_SWITCH >> 16) & 0x7)) {
-		return (1);
-	} else {
-		return (0);
-	}
-}
-
-
-static int test_sram (void)
-{
-	return (memory_post_tests (SRAM_ADDR, SRAM_SIZE));
-}
-
-
-static int test_eeprom (void)
-{
-	unsigned char temp[sizeof (EEPROM_TEST_STRING_1)];
-	int result = 0;
-
-	/* write test string 1, read back and verify */
-	if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_TEST, 1,
-				(unsigned char*)EEPROM_TEST_STRING_1,
-				sizeof (EEPROM_TEST_STRING_1))) {
-		return (1);
-	}
-
-	if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_TEST, 1,
-			       temp, sizeof (EEPROM_TEST_STRING_1))) {
-		return (1);
-	}
-
-	if (strcmp ((char *)temp, EEPROM_TEST_STRING_1) != 0) {
-		result = 1;
-		printf ("%s: error; read_str = \"%s\"\n", __FUNCTION__, temp);
-	}
-
-	/* write test string 2, read back and verify */
-	if (result == 0) {
-		if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_TEST, 1,
-					(unsigned char*)EEPROM_TEST_STRING_2,
-					sizeof (EEPROM_TEST_STRING_2))) {
-			return (1);
-		}
-
-		if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_TEST, 1,
-				       temp, sizeof (EEPROM_TEST_STRING_2))) {
-			return (1);
-		}
-
-		if (strcmp ((char *)temp, EEPROM_TEST_STRING_2) != 0) {
-			result = 1;
-			printf ("%s: error; read str = \"%s\"\n",
-				__FUNCTION__, temp);
-		}
-	}
-	return (result);
-}
-
-
-static int test_contact_temp (void)
-{
-	int contact_temp;
-
-	contact_temp = tsc2000_contact_temp ();
-
-	if ((contact_temp < MIN_CONTACT_TEMP)
-	    || (contact_temp > MAX_CONTACT_TEMP))
-		return (1);
-	else
-		return (0);
-}
-
-
-int i2c_write_multiple (uchar chip, uint addr, int alen,
-			uchar *buffer, int len)
-{
-	int i;
-
-	if (alen != 1) {
-		printf ("%s: addr len other than 1 not supported\n",
-			 __FUNCTION__);
-		return (1);
-	}
-
-	for (i = 0; i < len; i++) {
-		if (i2c_write (chip, addr+i, alen, buffer+i, 1)) {
-			printf ("%s: could not write to i2c device %d"
-				 ", addr %d\n", __FUNCTION__, chip, addr);
-			return (1);
-		}
-#if 0
-		printf ("chip=%#x, addr+i=%#x+%d=%p, alen=%d, *buffer+i="
-			"%#x+%d=%p=\"%.1s\"\n", chip, addr, i, addr+i,
-			alen, buffer, i, buffer+i, buffer+i);
-#endif
-
-		udelay (30000);
-	}
-	return (0);
-}
-
-
-int i2c_read_multiple ( uchar chip, uint addr, int alen,
-			uchar *buffer, int len)
-{
-	int i;
-
-	if (alen != 1) {
-		printf ("%s: addr len other than 1 not supported\n",
-			 __FUNCTION__);
-		return (1);
-	}
-
-	for (i = 0; i < len; i++) {
-		if (i2c_read (chip, addr+i, alen, buffer+i, 1)) {
-			printf ("%s: could not read from i2c device %#x"
-				 ", addr %d\n", __FUNCTION__, chip, addr);
-			return (1);
-		}
-	}
-	return (0);
-}
-
-
-static int adc_read (unsigned int channel)
-{
-	int j = 1000; /* timeout value for wait loop in us */
-	int result;
-	struct s3c2400_adc *padc;
-
-	padc = s3c2400_get_base_adc();
-	channel &= 0x7;
-
-	adc_init ();
-
-	padc->adccon &= ~ADC_STDBM; /* select normal mode */
-	padc->adccon &= ~(0x7 << 3); /* clear the channel bits */
-	padc->adccon |= ((channel << 3) | ADC_ENABLE_START);
-
-	while (j--) {
-		if ((padc->adccon & ADC_ENABLE_START) == 0)
-			break;
-		udelay (1);
-	}
-
-	if (j == 0) {
-		printf("%s: ADC timeout\n", __FUNCTION__);
-		padc->adccon |= ADC_STDBM; /* select standby mode */
-		return -1;
-	}
-
-	result = padc->adcdat & 0x3FF;
-
-	padc->adccon |= ADC_STDBM; /* select standby mode */
-
-	debug ("%s: channel %d, result[DIGIT]=%d\n", __FUNCTION__,
-	       (padc->adccon >> 3) & 0x7, result);
-
-	/*
-	 * Wait for ADC to be ready for next conversion. This delay value was
-	 * estimated, because the datasheet does not specify a value.
-	 */
-	udelay (1000);
-
-	return (result);
-}
-
-
-static void adc_init (void)
-{
-	struct s3c2400_adc *padc;
-
-	padc = s3c2400_get_base_adc();
-
-	padc->adccon &= ~(0xff << 6); /* clear prescaler bits */
-	padc->adccon |= ((65 << 6) | ADC_PRSCEN); /* set prescaler */
-
-	/*
-	 * Wait some time to avoid problem with very first call of
-	 * adc_read(). Without this delay, sometimes the first read
-	 * adc value is 0. Perhaps because the adjustment of prescaler
-	 * takes some clock cycles?
-	 */
-	udelay (1000);
-
-	return;
-}
-
-
-static void led_set (unsigned int state)
-{
-	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
-
-	led_init ();
-
-	switch (state) {
-	case 0: /* turn LED off */
-		gpio->padat |= (1 << 12);
-		break;
-	case 1: /* turn LED on */
-		gpio->padat &= ~(1 << 12);
-		break;
-	default:
-		break;
-	}
-}
-
-static void led_blink (void)
-{
-	led_init ();
-
-	/* blink LED. This function does not return! */
-	while (1) {
-		reset_timer_masked ();
-		led_set (1);
-		udelay (1000000 / LED_BLINK_FREQ / 2);
-		led_set (0);
-		udelay (1000000 / LED_BLINK_FREQ / 2);
-	}
-}
-
-
-static void led_init (void)
-{
-	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
-
-	/* configure GPA12 as output and set to High -> LED off */
-	gpio->pacon &= ~(1 << 12);
-	gpio->padat |= (1 << 12);
-}
-
-
-static void sdelay (unsigned long seconds)
-{
-	unsigned long i;
-
-	for (i = 0; i < seconds; i++) {
-		udelay (1000000);
-	}
-}
-
-
-static int global_vars_write_to_eeprom (void)
-{
-	if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_STATUS, 1,
-				(unsigned char*) &status, 1)) {
-		return (1);
-	}
-	if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_PASS_CYCLES, 1,
-				(unsigned char*) &pass_cycles, 2)) {
-		return (1);
-	}
-	if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_CYCLE,
-				1, (unsigned char*) &first_error_cycle, 2)) {
-		return (1);
-	}
-	if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_NUM,
-				1, (unsigned char*) &first_error_num, 1)) {
-		return (1);
-	}
-	if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_NAME,
-				1, (unsigned char*) first_error_name,
-				sizeof(first_error_name))) {
-		return (1);
-	}
-	return (0);
-}
-
-static void global_vars_init (void)
-{
-	status                  = 1; /* error */
-	pass_cycles             = 0;
-	first_error_cycle       = 0;
-	first_error_num         = 0;
-	first_error_name[0]     = '\0';
-	act_cycle               = 0;
-	max_cycles              = 0;
-}
-
-
-static void test_function_table_init (void)
-{
-	int i;
-
-	for (i = 0; i < BIF_MAX; i++)
-		test_function[i].pf = dummy;
-
-	/*
-	 * the length of "name" must not exceed 16, including the '\0'
-	 * termination. See also the EEPROM address map.
-	 */
-	test_function[0].pf = test_dip;
-	test_function[0].name = "dip";
-
-	test_function[1].pf = test_vcc5v;
-	test_function[1].name = "vcc5v";
-
-	test_function[2].pf = test_rotary_switch;
-	test_function[2].name = "rotary_switch";
-
-	test_function[3].pf = test_sram;
-	test_function[3].name = "sram";
-
-	test_function[4].pf = test_eeprom;
-	test_function[4].name = "eeprom";
-
-	test_function[5].pf = test_contact_temp;
-	test_function[5].name = "contact_temp";
-}
-
-
-static int read_max_cycles (void)
-{
-	if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_MAX_CYCLES, 1,
-			       (unsigned char *) &max_cycles, 2) != 0) {
-		return (1);
-	}
-
-	return (0);
-}
-
-static int dummy(void)
-{
-	return (0);
-}
-
-int do_temp_log (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	int contact_temp;
-	int delay = 0;
-#if defined(CONFIG_CMD_DATE)
-	struct rtc_time tm;
-#endif
-
-	if (argc > 2)
-		return cmd_usage(cmdtp);
-
-	if (argc > 1)
-		delay = simple_strtoul(argv[1], NULL, 10);
-
-	tsc2000_spi_init ();
-	while (1) {
-
-#if defined(CONFIG_CMD_DATE)
-		rtc_get (&tm);
-		printf ("%4d-%02d-%02d %2d:%02d:%02d - ",
-			tm.tm_year, tm.tm_mon, tm.tm_mday,
-			tm.tm_hour, tm.tm_min, tm.tm_sec);
-#endif
-
-		contact_temp = tsc2000_contact_temp();
-		printf ("%d\n", contact_temp) ;
-
-		if (delay != 0)
-			/*
-			 * reset timer to avoid timestamp overflow problem
-			 * after about 68 minutes of udelay() time.
-			 */
-			reset_timer_masked ();
-			sdelay (delay);
-	}
-
-	return 0;
-}
-
-U_BOOT_CMD(
-	tlog,	2,	1,	do_temp_log,
-	"log contact temperature [1/100 C] to console (endlessly)",
-	"delay\n"
-	"    - contact temperature [1/100 C] is printed endlessly to console\n"
-	"      <delay> specifies the seconds to wait between two measurements\n"
-	"      For each measurment a timestamp is printeted"
-);
-
-#endif

board/trab/config.mk

@@ -1,26 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# TRAB board with S3C2400X (arm920t) cpu
-#
-# see http://www.samsung.com/ for more information on SAMSUNG
-#
-
-#
-# TRAB has 1 bank of 16 MB or 32 MB DRAM
-#
-# 0c00'0000 to 0e00'0000
-#
-# Linux-Kernel is expected to be at 0c00'8000, entry 0c00'8000
-#
-# we load ourself to 0CF0'0000	/ 0DF0'0000
-#
-# download areas is 0C80'0000
-#
-
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
-ifndef CONFIG_SYS_TEXT_BASE
-CONFIG_SYS_TEXT_BASE = 0x0DF40000
-endif

board/trab/flash.c

@@ -1,569 +0,0 @@
-/*
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/* #define DEBUG */
-
-#include <common.h>
-#include <environment.h>
-
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-
-#define CMD_READ_ARRAY		0x00F000F0
-#define CMD_UNLOCK1		0x00AA00AA
-#define CMD_UNLOCK2		0x00550055
-#define CMD_ERASE_SETUP		0x00800080
-#define CMD_ERASE_CONFIRM	0x00300030
-#define CMD_PROGRAM		0x00A000A0
-#define CMD_UNLOCK_BYPASS	0x00200020
-#define CMD_READ_MANF_ID	0x00900090
-#define CMD_UNLOCK_BYPASS_RES1	0x00900090
-#define CMD_UNLOCK_BYPASS_RES2	0x00000000
-
-#define MEM_FLASH_ADDR		(*(volatile u32 *)CONFIG_SYS_FLASH_BASE)
-#define MEM_FLASH_ADDR1		(*(volatile u32 *)(CONFIG_SYS_FLASH_BASE + (0x00000555 << 2)))
-#define MEM_FLASH_ADDR2		(*(volatile u32 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA << 2)))
-
-#define BIT_ERASE_DONE		0x00800080
-#define BIT_RDY_MASK		0x00800080
-#define BIT_PROGRAM_ERROR	0x00200020
-#define BIT_TIMEOUT		0x80000000	/* our flag */
-
-#define READY 1
-#define ERR   2
-#define TMO   4
-
-/*-----------------------------------------------------------------------
- */
-
-ulong flash_init (void)
-{
-	int i, j;
-	ulong size = 0;
-
-	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
-		ulong flashbase = 0;
-		flash_info_t *info = &flash_info[i];
-
-		/* Init: no FLASHes known */
-		info->flash_id = FLASH_UNKNOWN;
-
-		size += flash_get_size (CONFIG_SYS_FLASH_BASE, info);
-
-		if (i == 0)
-			flashbase = CONFIG_SYS_FLASH_BASE;
-		else
-			panic ("configured too many flash banks!\n");
-		for (j = 0; j < info->sector_count; j++) {
-
-			info->protect[j] = 0;
-			info->start[j] = flashbase;
-
-			switch (info->flash_id & FLASH_TYPEMASK) {
-			case (FLASH_AM320B & FLASH_TYPEMASK):
-			case (FLASH_MXLV320B & FLASH_TYPEMASK):
-				/* Boot sector type: 8 x 8 + N x 128 kB */
-				flashbase += (j < 8) ? 0x4000 : 0x20000;
-				break;
-			case (FLASH_AM640U & FLASH_TYPEMASK):
-				/* Uniform sector type: 128 kB */
-				flashbase += 0x20000;
-				break;
-			default:
-				printf ("## Bad flash chip type 0x%04lX\n",
-					info->flash_id & FLASH_TYPEMASK);
-			}
-		}
-	}
-
-	/*
-	 * Protect monitor and environment sectors
-	 */
-	flash_protect ( FLAG_PROTECT_SET,
-			CONFIG_SYS_FLASH_BASE,
-			CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
-			&flash_info[0]);
-
-	flash_protect ( FLAG_PROTECT_SET,
-			CONFIG_ENV_ADDR,
-			CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, &flash_info[0]);
-
-#ifdef CONFIG_ENV_ADDR_REDUND
-	flash_protect ( FLAG_PROTECT_SET,
-			CONFIG_ENV_ADDR_REDUND,
-			CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
-			&flash_info[0]);
-#endif
-
-	return size;
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
-	int i;
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-	case (FLASH_MAN_AMD & FLASH_VENDMASK):
-			printf ("AMD ");		break;
-	case (FLASH_MAN_FUJ & FLASH_VENDMASK):
-			printf ("FUJITSU ");		break;
-	case (FLASH_MAN_MX  & FLASH_VENDMASK):
-			printf ("MACRONIX ");		break;
-	default:	printf ("Unknown Vendor ");	break;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case (FLASH_AM320B & FLASH_TYPEMASK):
-		printf ("2x Am29LV320DB (32Mbit)\n");
-		break;
-	case (FLASH_MXLV320B & FLASH_TYPEMASK):
-		printf ("2x MX29LV320DB (32Mbit)\n");
-		break;
-	case (FLASH_AM640U & FLASH_TYPEMASK):
-		printf ("2x Am29LV640D (64Mbit)\n");
-		break;
-	default:
-		printf ("Unknown Chip Type\n");
-		goto Done;
-		break;
-	}
-
-	printf ("  Size: %ld MB in %d Sectors\n",
-			info->size >> 20, info->sector_count);
-
-	printf ("  Sector Start Addresses:");
-	for (i = 0; i < info->sector_count; i++) {
-		if ((i % 5) == 0) {
-			printf ("\n   ");
-		}
-		printf (" %08lX%s",
-			info->start[i],
-			info->protect[i] ? " (RO)" : "     ");
-	}
-	printf ("\n");
-
-Done:	;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
-	ulong result;
-
-#if 0
-	int cflag;
-#endif
-	int iflag, prot, sect;
-	int rc = ERR_OK;
-	int chip1, chip2;
-
-	debug ("flash_erase: s_first %d  s_last %d\n", s_first, s_last);
-
-	/* first look for protection bits */
-
-	if (info->flash_id == FLASH_UNKNOWN)
-		return ERR_UNKNOWN_FLASH_TYPE;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		return ERR_INVAL;
-	}
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-	case (FLASH_MAN_AMD & FLASH_VENDMASK):	break;	/* OK */
-	case (FLASH_MAN_FUJ & FLASH_VENDMASK):	break;	/* OK */
-	case (FLASH_MAN_MX  & FLASH_VENDMASK):	break;	/* OK */
-	default:
-		debug ("## flash_erase: unknown manufacturer\n");
-		return (ERR_UNKNOWN_FLASH_VENDOR);
-	}
-
-	prot = 0;
-	for (sect = s_first; sect <= s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-
-	if (prot) {
-		printf ("- Warning: %d protected sectors will not be erased!\n",
-			prot);
-	} else {
-		printf ("\n");
-	}
-
-	/*
-	 * Disable interrupts which might cause a timeout
-	 * here. Remember that our exception vectors are
-	 * at address 0 in the flash, and we don't want a
-	 * (ticker) exception to happen while the flash
-	 * chip is in programming mode.
-	 */
-#if 0
-	cflag = icache_status ();
-	icache_disable ();
-#endif
-	iflag = disable_interrupts ();
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
-
-		debug ("Erasing sector %2d @ %08lX... ",
-			sect, info->start[sect]);
-
-		/* arm simple, non interrupt dependent timer */
-		reset_timer_masked ();
-
-		if (info->protect[sect] == 0) {	/* not protected */
-			vu_long *addr = (vu_long *) (info->start[sect]);
-
-			MEM_FLASH_ADDR1 = CMD_UNLOCK1;
-			MEM_FLASH_ADDR2 = CMD_UNLOCK2;
-			MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
-
-			MEM_FLASH_ADDR1 = CMD_UNLOCK1;
-			MEM_FLASH_ADDR2 = CMD_UNLOCK2;
-			*addr = CMD_ERASE_CONFIRM;
-
-			/* wait until flash is ready */
-			chip1 = chip2 = 0;
-
-			do {
-				result = *addr;
-
-				/* check timeout */
-				if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
-					MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
-					chip1 = TMO;
-					break;
-				}
-
-				if (!chip1 && (result & 0xFFFF) & BIT_ERASE_DONE)
-					chip1 = READY;
-
-				if (!chip1 && (result & 0xFFFF) & BIT_PROGRAM_ERROR)
-					chip1 = ERR;
-
-				if (!chip2 && (result >> 16) & BIT_ERASE_DONE)
-					chip2 = READY;
-
-				if (!chip2 && (result >> 16) & BIT_PROGRAM_ERROR)
-					chip2 = ERR;
-
-			} while (!chip1 || !chip2);
-
-			MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
-
-			if (chip1 == ERR || chip2 == ERR) {
-				rc = ERR_PROG_ERROR;
-				printf ("Flash erase error\n");
-				goto outahere;
-			}
-			if (chip1 == TMO) {
-				rc = ERR_TIMOUT;
-				printf ("Flash erase timeout error\n");
-				goto outahere;
-			}
-		}
-	}
-
-outahere:
-	/* allow flash to settle - wait 10 ms */
-	udelay_masked (10000);
-
-	if (iflag)
-		enable_interrupts ();
-
-#if 0
-	if (cflag)
-		icache_enable ();
-#endif
-	return rc;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash
- */
-
-static int write_word (flash_info_t * info, ulong dest, ulong data)
-{
-	vu_long *addr = (vu_long *) dest;
-	ulong result;
-	int rc = ERR_OK;
-
-#if 0
-	int cflag;
-#endif
-	int iflag;
-	int chip1, chip2;
-
-	/*
-	 * Check if Flash is (sufficiently) erased
-	 */
-	result = *addr;
-	if ((result & data) != data)
-		return ERR_NOT_ERASED;
-
-	/*
-	 * Disable interrupts which might cause a timeout
-	 * here. Remember that our exception vectors are
-	 * at address 0 in the flash, and we don't want a
-	 * (ticker) exception to happen while the flash
-	 * chip is in programming mode.
-	 */
-#if 0
-	cflag = icache_status ();
-	icache_disable ();
-#endif
-	iflag = disable_interrupts ();
-
-	MEM_FLASH_ADDR1 = CMD_UNLOCK1;
-	MEM_FLASH_ADDR2 = CMD_UNLOCK2;
-	MEM_FLASH_ADDR1 = CMD_PROGRAM;
-	*addr = data;
-
-	/* arm simple, non interrupt dependent timer */
-	reset_timer_masked ();
-
-	/* wait until flash is ready */
-	chip1 = chip2 = 0;
-	do {
-		result = *addr;
-
-		/* check timeout */
-		if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
-			chip1 = ERR | TMO;
-			break;
-		}
-		if (!chip1 && ((result & 0x80) == (data & 0x80)))
-			chip1 = READY;
-
-		if (!chip1 && ((result & 0xFFFF) & BIT_PROGRAM_ERROR)) {
-			result = *addr;
-
-			if ((result & 0x80) == (data & 0x80))
-				chip1 = READY;
-			else
-				chip1 = ERR;
-		}
-
-		if (!chip2 && ((result & (0x80 << 16)) == (data & (0x80 << 16))))
-			chip2 = READY;
-
-		if (!chip2 && ((result >> 16) & BIT_PROGRAM_ERROR)) {
-			result = *addr;
-
-			if ((result & (0x80 << 16)) == (data & (0x80 << 16)))
-				chip2 = READY;
-			else
-				chip2 = ERR;
-		}
-
-	} while (!chip1 || !chip2);
-
-	*addr = CMD_READ_ARRAY;
-
-	if (chip1 == ERR || chip2 == ERR || *addr != data) {
-		rc = ERR_PROG_ERROR;
-		printf ("Flash program error\n");
-		debug ("chip1: %#x, chip2: %#x, addr: %#lx *addr: %#lx, "
-		       "data: %#lx\n",
-		       chip1, chip2, addr, *addr, data);
-	}
-
-	if (iflag)
-		enable_interrupts ();
-
-#if 0
-	if (cflag)
-		icache_enable ();
-#endif
-
-	return rc;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash.
- */
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
-	ulong cp, wp, data;
-	int l;
-	int i, rc;
-
-	wp = (addr & ~3);	/* get lower word aligned address */
-
-	/*
-	 * handle unaligned start bytes
-	 */
-	if ((l = addr - wp) != 0) {
-		data = 0;
-		for (i = 0, cp = wp; i < l; ++i, ++cp) {
-			data = (data >> 8) | (*(uchar *) cp << 24);
-		}
-		for (; i < 4 && cnt > 0; ++i) {
-			data = (data >> 8) | (*src++ << 24);
-			--cnt;
-			++cp;
-		}
-		for (; cnt == 0 && i < 4; ++i, ++cp) {
-			data = (data >> 8) | (*(uchar *) cp << 24);
-		}
-
-		if ((rc = write_word (info, wp, data)) != 0) {
-			goto Done;
-		}
-		wp += 4;
-	}
-
-	/*
-	 * handle word aligned part
-	 */
-	while (cnt >= 4) {
-		if (((ulong)src) & 0x3) {
-			for (i = 0; i < 4; i++) {
-				((char *)&data)[i] = ((vu_char *)src)[i];
-			}
-		}
-		else {
-			data = *((vu_long *) src);
-		}
-
-		if ((rc = write_word (info, wp, data)) != 0) {
-			goto Done;
-		}
-		src += 4;
-		wp += 4;
-		cnt -= 4;
-	}
-
-	if (cnt == 0) {
-		rc = ERR_OK;
-		goto Done;
-	}
-
-	/*
-	 * handle unaligned tail bytes
-	 */
-	data = 0;
-	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
-		data = (data >> 8) | (*src++ << 24);
-		--cnt;
-	}
-	for (; i < 4; ++i, ++cp) {
-		data = (data >> 8) | (*(uchar *) cp << 24);
-	}
-
-	rc = write_word (info, wp, data);
-
-	Done:
-
-	return (rc);
-}
-
-/*-----------------------------------------------------------------------
- */
-
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
-	ulong value;
-
-	/* Write auto select command sequence and read Manufacturer ID */
-	addr[0x0555] = CMD_UNLOCK1;
-	addr[0x02AA] = CMD_UNLOCK2;
-	addr[0x0555] = CMD_READ_MANF_ID;
-
-	value = addr[0];
-
-	debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value);
-
-	switch (value) {
-	case AMD_MANUFACT:
-		info->flash_id = FLASH_MAN_AMD;
-		break;
-	case FUJ_MANUFACT:
-		info->flash_id = FLASH_MAN_FUJ;
-		break;
-	case MX_MANUFACT:
-		info->flash_id = FLASH_MAN_MX;
-		break;
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		info->sector_count = 0;
-		info->size = 0;
-		addr[0] = CMD_READ_ARRAY;	/* restore read mode */
-		debug ("## flash_init: unknown manufacturer\n");
-		return (0);			/* no or unknown flash	*/
-	}
-
-	value = addr[1];			/* device ID		*/
-
-	debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value);
-
-	switch (value) {
-	case AMD_ID_LV320B:
-		info->flash_id += FLASH_AM320B;
-		info->sector_count = 71;
-		info->size = 0x00800000;
-
-		addr[0] = CMD_READ_ARRAY;	/* restore read mode */
-		break;				/* =>  8 MB		*/
-
-	case AMD_ID_LV640U:
-		info->flash_id += FLASH_AM640U;
-		info->sector_count = 128;
-		info->size = 0x01000000;
-
-		addr[0] = CMD_READ_ARRAY;	/* restore read mode */
-		break;				/* => 16 MB		*/
-
-	case MX_ID_LV320B:
-		info->flash_id += FLASH_MXLV320B;
-		info->sector_count = 71;
-		info->size = 0x00800000;
-
-		addr[0] = CMD_READ_ARRAY;	/* restore read mode */
-		break;				/* =>  8 MB		*/
-
-	default:
-		debug ("## flash_init: unknown flash chip\n");
-		info->flash_id = FLASH_UNKNOWN;
-		addr[0] = CMD_READ_ARRAY;	/* restore read mode */
-		return (0);			/* => no or unknown flash */
-
-	}
-
-	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
-		printf ("** ERROR: sector count %d > max (%d) **\n",
-			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
-		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
-	}
-
-	return (info->size);
-}

board/trab/lowlevel_init.S

@@ -1,182 +0,0 @@
-/*
- * Memory Setup stuff - taken from blob memsetup.S
- *
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
- *                     Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
- *
- * Modified for the TRAB board by
- * (C) Copyright 2002-2003
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include <config.h>
-#include <version.h>
-
-
-/* some parameters for the board */
-
-/*
- *
- * Copied from linux/arch/arm/boot/compressed/head-s3c2400.S
- *
- * Copyright (C) 2001 Samsung Electronics by chc, 010406
- *
- * TRAB specific tweaks.
- *
- */
-
-/* memory controller */
-#define BWSCON 0x14000000
-
-/* Bank0 */
-#define B0_Tacs	0x1	/* 1 clk */
-#define B0_Tcos	0x1	/* 1 clk */
-#define B0_Tacc	0x5	/* 8 clk */
-#define B0_Tcoh	0x1	/* 1 clk */
-#define B0_Tah	0x1	/* 1 clk */
-#define B0_Tacp	0x0
-#define B0_PMC	0x0	/* normal */
-
-/* Bank1 - SRAM */
-#define B1_Tacs	0x1	/* 1 clk */
-#define B1_Tcos	0x1	/* 1 clk */
-#define B1_Tacc	0x5	/* 8 clk */
-#define B1_Tcoh	0x1	/* 1 clk */
-#define B1_Tah	0x1	/* 1 clk */
-#define B1_Tacp	0x0
-#define B1_PMC	0x0	/* normal */
-
-/* Bank2 - CPLD */
-#define B2_Tacs	0x1	/* 1 clk */
-#define B2_Tcos	0x1	/* 1 clk */
-#define B2_Tacc	0x5	/* 8 clk */
-#define B2_Tcoh	0x1	/* 1 clk */
-#define B2_Tah	0x1	/* 1 clk */
-#define B2_Tacp	0x0
-#define B2_PMC	0x0	/* normal */
-
-/* Bank3 - setup for the cs8900 */
-#define B3_Tacs	0x3	/* 4 clk */
-#define B3_Tcos	0x3	/* 4 clk */
-#define B3_Tacc	0x7	/* 14 clk */
-#define B3_Tcoh	0x1	/* 1 clk */
-#define B3_Tah	0x0	/* 0 clk */
-#define B3_Tacp	0x3	/* 6 clk */
-#define B3_PMC	0x0	/* normal */
-
-/* Bank4 */
-#define B4_Tacs	0x0	/* 0 clk */
-#define B4_Tcos	0x0	/* 0 clk */
-#define B4_Tacc	0x7	/* 14 clk */
-#define B4_Tcoh	0x0	/* 0 clk */
-#define B4_Tah	0x0	/* 0 clk */
-#define B4_Tacp	0x0
-#define B4_PMC	0x0	/* normal */
-
-/* Bank5 */
-#define B5_Tacs	0x0	/* 0 clk */
-#define B5_Tcos	0x0	/* 0 clk */
-#define B5_Tacc	0x7	/* 14 clk */
-#define B5_Tcoh	0x0	/* 0 clk */
-#define B5_Tah	0x0	/* 0 clk */
-#define B5_Tacp	0x0
-#define B5_PMC	0x0	/* normal */
-
-#ifndef CONFIG_RAM_16MB		/* 32 MB RAM */
-/* Bank6 */
-#define	B6_MT	0x3	/* SDRAM */
-#define	B6_Trcd	0x0	/* 2clk */
-#define	B6_SCAN	0x1	/* 9 bit */
-
-/* Bank7 */
-#define	B7_MT	0x3	/* SDRAM */
-#define	B7_Trcd	0x0	/* 2clk */
-#define	B7_SCAN	0x1	/* 9 bit */
-#else	/* CONFIG_RAM_16MB	=  16 MB RAM */
-/* Bank6 */
-#define	B6_MT	0x3	/* SDRAM */
-#define	B6_Trcd	0x1	/* 2clk */
-#define	B6_SCAN	0x0	/* 8 bit */
-
-/* Bank7 */
-#define	B7_MT	0x3	/* SDRAM */
-#define	B7_Trcd	0x1	/* 2clk */
-#define	B7_SCAN	0x0	/* 8 bit */
-#endif	/* CONFIG_RAM_16MB */
-
-/* refresh parameter */
-#define REFEN	0x1	/* enable refresh */
-#define TREFMD	0x0	/* CBR(CAS before RAS)/auto refresh */
-#define Trp	0x0	/* 2 clk */
-#define Trc	0x3	/* 7 clk */
-#define Tchr	0x2	/* 3 clk */
-
-#ifdef CONFIG_TRAB_50MHZ
-#define REFCNT	1269	/* period=15.6 us, HCLK=50Mhz, (2048+1-15.6*50) */
-#else
-#define REFCNT	1011	/* period=15.6 us, HCLK=66.5Mhz, (2048+1-15.6*66.5) */
-#endif
-
-
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE
-
-.globl lowlevel_init
-lowlevel_init:
-	/* memory control configuration */
-	/* make r0 relative the current location so that it */
-	/* reads SMRDATA out of FLASH rather than memory ! */
-	ldr     r0, =SMRDATA
-	ldr	r1, _TEXT_BASE
-	sub	r0, r0, r1
-	ldr	r1, =BWSCON	/* Bus Width Status Controller */
-	add     r2, r0, #52
-0:
-	ldr     r3, [r0], #4
-	str     r3, [r1], #4
-	cmp     r2, r0
-	bne     0b
-
-	/* everything is fine now */
-	mov	pc, lr
-
-	.ltorg
-/* the literal pools origin */
-
-SMRDATA:
-	.word	0x2211d644	/* d->Ethernet, 6->CPLD, 4->SRAM, 4->FLASH */
-	.word	((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) /* GCS0 */
-	.word	((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) /* GCS1 */
-	.word	((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) /* GCS2 */
-	.word	((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) /* GCS3 */
-	.word	((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) /* GCS4 */
-	.word	((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) /* GCS5 */
-	.word	((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) /* GCS6 */
-	.word	((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) /* GCS7 */
-	.word	((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
-#ifndef CONFIG_RAM_16MB		/* 32 MB RAM */
-	.word	0x10	/* BUSWIDTH=32, SCLK power saving mode, BANKSIZE 32M/32M */
-#else	/* CONFIG_RAM_16MB	=  16 MB RAM */
-	.word	0x17	/* BUSWIDTH=32, SCLK power saving mode, BANKSIZE 16M/16M */
-#endif	/* CONFIG_RAM_16MB */
-	.word	0x20	/* MRSR6, CL=2clk */
-	.word	0x20	/* MRSR7 */

board/trab/memory.c

@@ -1,486 +0,0 @@
-/*
- * (C) Copyright 2002-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-/* Memory test
- *
- * General observations:
- * o The recommended test sequence is to test the data lines: if they are
- *   broken, nothing else will work properly.  Then test the address
- *   lines.  Finally, test the cells in the memory now that the test
- *   program knows that the address and data lines work properly.
- *   This sequence also helps isolate and identify what is faulty.
- *
- * o For the address line test, it is a good idea to use the base
- *   address of the lowest memory location, which causes a '1' bit to
- *   walk through a field of zeros on the address lines and the highest
- *   memory location, which causes a '0' bit to walk through a field of
- *   '1's on the address line.
- *
- * o Floating buses can fool memory tests if the test routine writes
- *   a value and then reads it back immediately.  The problem is, the
- *   write will charge the residual capacitance on the data bus so the
- *   bus retains its state briefely.  When the test program reads the
- *   value back immediately, the capacitance of the bus can allow it
- *   to read back what was written, even though the memory circuitry
- *   is broken.  To avoid this, the test program should write a test
- *   pattern to the target location, write a different pattern elsewhere
- *   to charge the residual capacitance in a differnt manner, then read
- *   the target location back.
- *
- * o Always read the target location EXACTLY ONCE and save it in a local
- *   variable.  The problem with reading the target location more than
- *   once is that the second and subsequent reads may work properly,
- *   resulting in a failed test that tells the poor technician that
- *   "Memory error at 00000000, wrote aaaaaaaa, read aaaaaaaa" which
- *   doesn't help him one bit and causes puzzled phone calls.  Been there,
- *   done that.
- *
- * Data line test:
- * ---------------
- * This tests data lines for shorts and opens by forcing adjacent data
- * to opposite states. Because the data lines could be routed in an
- * arbitrary manner the must ensure test patterns ensure that every case
- * is tested. By using the following series of binary patterns every
- * combination of adjacent bits is test regardless of routing.
- *
- *     ...101010101010101010101010
- *     ...110011001100110011001100
- *     ...111100001111000011110000
- *     ...111111110000000011111111
- *
- * Carrying this out, gives us six hex patterns as follows:
- *
- *     0xaaaaaaaaaaaaaaaa
- *     0xcccccccccccccccc
- *     0xf0f0f0f0f0f0f0f0
- *     0xff00ff00ff00ff00
- *     0xffff0000ffff0000
- *     0xffffffff00000000
- *
- * To test for short and opens to other signals on our boards, we
- * simply test with the 1's complemnt of the paterns as well, resulting
- * in twelve patterns total.
- *
- * After writing a test pattern. a special pattern 0x0123456789ABCDEF is
- * written to a different address in case the data lines are floating.
- * Thus, if a byte lane fails, you will see part of the special
- * pattern in that byte lane when the test runs.  For example, if the
- * xx__xxxxxxxxxxxx byte line fails, you will see aa23aaaaaaaaaaaa
- * (for the 'a' test pattern).
- *
- * Address line test:
- * ------------------
- *  This function performs a test to verify that all the address lines
- *  hooked up to the RAM work properly.  If there is an address line
- *  fault, it usually shows up as two different locations in the address
- *  map (related by the faulty address line) mapping to one physical
- *  memory storage location.  The artifact that shows up is writing to
- *  the first location "changes" the second location.
- *
- * To test all address lines, we start with the given base address and
- * xor the address with a '1' bit to flip one address line.  For each
- * test, we shift the '1' bit left to test the next address line.
- *
- * In the actual code, we start with address sizeof(ulong) since our
- * test pattern we use is a ulong and thus, if we tried to test lower
- * order address bits, it wouldn't work because our pattern would
- * overwrite itself.
- *
- * Example for a 4 bit address space with the base at 0000:
- *   0000 <- base
- *   0001 <- test 1
- *   0010 <- test 2
- *   0100 <- test 3
- *   1000 <- test 4
- * Example for a 4 bit address space with the base at 0010:
- *   0010 <- base
- *   0011 <- test 1
- *   0000 <- (below the base address, skipped)
- *   0110 <- test 2
- *   1010 <- test 3
- *
- * The test locations are successively tested to make sure that they are
- * not "mirrored" onto the base address due to a faulty address line.
- * Note that the base and each test location are related by one address
- * line flipped.  Note that the base address need not be all zeros.
- *
- * Memory tests 1-4:
- * -----------------
- * These tests verify RAM using sequential writes and reads
- * to/from RAM. There are several test cases that use different patterns to
- * verify RAM. Each test case fills a region of RAM with one pattern and
- * then reads the region back and compares its contents with the pattern.
- * The following patterns are used:
- *
- *  1a) zero pattern (0x00000000)
- *  1b) negative pattern (0xffffffff)
- *  1c) checkerboard pattern (0x55555555)
- *  1d) checkerboard pattern (0xaaaaaaaa)
- *  2)  bit-flip pattern ((1 << (offset % 32))
- *  3)  address pattern (offset)
- *  4)  address pattern (~offset)
- *
- * Being run in normal mode, the test verifies only small 4Kb
- * regions of RAM around each 1Mb boundary. For example, for 64Mb
- * RAM the following areas are verified: 0x00000000-0x00000800,
- * 0x000ff800-0x00100800, 0x001ff800-0x00200800, ..., 0x03fff800-
- * 0x04000000. If the test is run in slow-test mode, it verifies
- * the whole RAM.
- */
-
-/* #ifdef CONFIG_POST */
-
-#include <post.h>
-#include <watchdog.h>
-
-/* #if CONFIG_POST & CONFIG_SYS_POST_MEMORY */
-
-/*
- * Define INJECT_*_ERRORS for testing error detection in the presence of
- * _good_ hardware.
- */
-#undef  INJECT_DATA_ERRORS
-#undef  INJECT_ADDRESS_ERRORS
-
-#ifdef INJECT_DATA_ERRORS
-#warning "Injecting data line errors for testing purposes"
-#endif
-
-#ifdef INJECT_ADDRESS_ERRORS
-#warning "Injecting address line errors for testing purposes"
-#endif
-
-
-/*
- * This function performs a double word move from the data at
- * the source pointer to the location at the destination pointer.
- * This is helpful for testing memory on processors which have a 64 bit
- * wide data bus.
- *
- * On those PowerPC with FPU, use assembly and a floating point move:
- * this does a 64 bit move.
- *
- * For other processors, let the compiler generate the best code it can.
- */
-static void move64(const unsigned long long *src, unsigned long long *dest)
-{
-#if defined(CONFIG_MPC8260) || defined(CONFIG_MPC824X)
-	asm ("lfd  0, 0(3)\n\t" /* fpr0	  =  *scr	*/
-	 "stfd 0, 0(4)"		/* *dest  =  fpr0	*/
-	 : : : "fr0" );		/* Clobbers fr0		*/
-    return;
-#else
-	*dest = *src;
-#endif
-}
-
-/*
- * This is 64 bit wide test patterns.  Note that they reside in ROM
- * (which presumably works) and the tests write them to RAM which may
- * not work.
- *
- * The "otherpattern" is written to drive the data bus to values other
- * than the test pattern.  This is for detecting floating bus lines.
- *
- */
-const static unsigned long long pattern[] = {
-	0xaaaaaaaaaaaaaaaaULL,
-	0xccccccccccccccccULL,
-	0xf0f0f0f0f0f0f0f0ULL,
-	0xff00ff00ff00ff00ULL,
-	0xffff0000ffff0000ULL,
-	0xffffffff00000000ULL,
-	0x00000000ffffffffULL,
-	0x0000ffff0000ffffULL,
-	0x00ff00ff00ff00ffULL,
-	0x0f0f0f0f0f0f0f0fULL,
-	0x3333333333333333ULL,
-	0x5555555555555555ULL,
-};
-const unsigned long long otherpattern = 0x0123456789abcdefULL;
-
-
-static int memory_post_dataline(unsigned long long * pmem)
-{
-	unsigned long long temp64;
-	int num_patterns = sizeof(pattern)/ sizeof(pattern[0]);
-	int i;
-	unsigned int hi, lo, pathi, patlo;
-	int ret = 0;
-
-	for ( i = 0; i < num_patterns; i++) {
-		move64(&(pattern[i]), pmem++);
-		/*
-		 * Put a different pattern on the data lines: otherwise they
-		 * may float long enough to read back what we wrote.
-		 */
-		move64(&otherpattern, pmem--);
-		move64(pmem, &temp64);
-
-#ifdef INJECT_DATA_ERRORS
-		temp64 ^= 0x00008000;
-#endif
-
-		if (temp64 != pattern[i]){
-			pathi = (pattern[i]>>32) & 0xffffffff;
-			patlo = pattern[i] & 0xffffffff;
-
-			hi = (temp64>>32) & 0xffffffff;
-			lo = temp64 & 0xffffffff;
-
-			printf ("Memory (date line) error at %08lx, "
-				  "wrote %08x%08x, read %08x%08x !\n",
-					  (ulong)pmem, pathi, patlo, hi, lo);
-			ret = -1;
-		}
-	}
-	return ret;
-}
-
-static int memory_post_addrline(ulong *testaddr, ulong *base, ulong size)
-{
-	ulong *target;
-	ulong *end;
-	ulong readback;
-	ulong xor;
-	int   ret = 0;
-
-	end = (ulong *)((ulong)base + size);	/* pointer arith! */
-	xor = 0;
-	for(xor = sizeof(ulong); xor > 0; xor <<= 1) {
-		target = (ulong *)((ulong)testaddr ^ xor);
-		if((target >= base) && (target < end)) {
-			*testaddr = ~*target;
-			readback  = *target;
-
-#ifdef INJECT_ADDRESS_ERRORS
-			if(xor == 0x00008000) {
-				readback = *testaddr;
-			}
-#endif
-			if(readback == *testaddr) {
-				printf ("Memory (address line) error at %08lx<->%08lx, "
-					"XOR value %08lx !\n",
-					(ulong)testaddr, (ulong)target,
-					xor);
-				ret = -1;
-			}
-		}
-	}
-	return ret;
-}
-
-static int memory_post_test1 (unsigned long start,
-			      unsigned long size,
-			      unsigned long val)
-{
-	unsigned long i;
-	ulong *mem = (ulong *) start;
-	ulong readback;
-	int ret = 0;
-
-	for (i = 0; i < size / sizeof (ulong); i++) {
-		mem[i] = val;
-		if (i % 1024 == 0)
-			WATCHDOG_RESET ();
-	}
-
-	for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) {
-		readback = mem[i];
-		if (readback != val) {
-			printf ("Memory error at %08lx, "
-				  "wrote %08lx, read %08lx !\n",
-					  (ulong)(mem + i), val, readback);
-
-			ret = -1;
-			break;
-		}
-		if (i % 1024 == 0)
-			WATCHDOG_RESET ();
-	}
-
-	return ret;
-}
-
-static int memory_post_test2 (unsigned long start, unsigned long size)
-{
-	unsigned long i;
-	ulong *mem = (ulong *) start;
-	ulong readback;
-	int ret = 0;
-
-	for (i = 0; i < size / sizeof (ulong); i++) {
-		mem[i] = 1 << (i % 32);
-		if (i % 1024 == 0)
-			WATCHDOG_RESET ();
-	}
-
-	for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) {
-		readback = mem[i];
-		if (readback != (1 << (i % 32))) {
-			printf ("Memory error at %08lx, "
-				  "wrote %08x, read %08lx !\n",
-					  (ulong)(mem + i), 1 << (i % 32), readback);
-
-			ret = -1;
-			break;
-		}
-		if (i % 1024 == 0)
-			WATCHDOG_RESET ();
-	}
-
-	return ret;
-}
-
-static int memory_post_test3 (unsigned long start, unsigned long size)
-{
-	unsigned long i;
-	ulong *mem = (ulong *) start;
-	ulong readback;
-	int ret = 0;
-
-	for (i = 0; i < size / sizeof (ulong); i++) {
-		mem[i] = i;
-		if (i % 1024 == 0)
-			WATCHDOG_RESET ();
-	}
-
-	for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) {
-		readback = mem[i];
-		if (readback != i) {
-			printf ("Memory error at %08lx, "
-				  "wrote %08lx, read %08lx !\n",
-					  (ulong)(mem + i), i, readback);
-
-			ret = -1;
-			break;
-		}
-		if (i % 1024 == 0)
-			WATCHDOG_RESET ();
-	}
-
-	return ret;
-}
-
-static int memory_post_test4 (unsigned long start, unsigned long size)
-{
-	unsigned long i;
-	ulong *mem = (ulong *) start;
-	ulong readback;
-	int ret = 0;
-
-	for (i = 0; i < size / sizeof (ulong); i++) {
-		mem[i] = ~i;
-		if (i % 1024 == 0)
-			WATCHDOG_RESET ();
-	}
-
-	for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) {
-		readback = mem[i];
-		if (readback != ~i) {
-			printf ("Memory error at %08lx, "
-				  "wrote %08lx, read %08lx !\n",
-					  (ulong)(mem + i), ~i, readback);
-
-			ret = -1;
-			break;
-		}
-		if (i % 1024 == 0)
-			WATCHDOG_RESET ();
-	}
-
-	return ret;
-}
-
-int memory_post_tests (unsigned long start, unsigned long size)
-{
-	int ret = 0;
-
-	if (ret == 0)
-		ret = memory_post_dataline ((unsigned long long *)start);
-	WATCHDOG_RESET ();
-	if (ret == 0)
-		ret = memory_post_addrline ((ulong *)start, (ulong *)start, size);
-	WATCHDOG_RESET ();
-	if (ret == 0)
-		ret = memory_post_addrline ((ulong *)(start + size - 8),
-					    (ulong *)start, size);
-	WATCHDOG_RESET ();
-	if (ret == 0)
-		ret = memory_post_test1 (start, size, 0x00000000);
-	WATCHDOG_RESET ();
-	if (ret == 0)
-		ret = memory_post_test1 (start, size, 0xffffffff);
-	WATCHDOG_RESET ();
-	if (ret == 0)
-		ret = memory_post_test1 (start, size, 0x55555555);
-	WATCHDOG_RESET ();
-	if (ret == 0)
-		ret = memory_post_test1 (start, size, 0xaaaaaaaa);
-	WATCHDOG_RESET ();
-	if (ret == 0)
-		ret = memory_post_test2 (start, size);
-	WATCHDOG_RESET ();
-	if (ret == 0)
-		ret = memory_post_test3 (start, size);
-	WATCHDOG_RESET ();
-	if (ret == 0)
-		ret = memory_post_test4 (start, size);
-	WATCHDOG_RESET ();
-
-	return ret;
-}
-
-#if 0
-DECLARE_GLOBAL_DATA_PTR;
-
-int memory_post_test (int flags)
-{
-	int ret = 0;
-	bd_t *bd = gd->bd;
-	phys_size_t memsize = (bd->bi_memsize >= 256 << 20 ?
-				 256 << 20 : bd->bi_memsize) - (1 << 20);
-
-
-	if (flags & POST_SLOWTEST) {
-		ret = memory_post_tests (CONFIG_SYS_SDRAM_BASE, memsize);
-	} else {			/* POST_NORMAL */
-
-		unsigned long i;
-
-		for (i = 0; i < (memsize >> 20) && ret == 0; i++) {
-			if (ret == 0)
-				ret = memory_post_tests (i << 20, 0x800);
-			if (ret == 0)
-				ret = memory_post_tests ((i << 20) + 0xff800, 0x800);
-		}
-	}
-
-	return ret;
-}
-#endif /* 0 */
-
-/* #endif */ /* CONFIG_POST & CONFIG_SYS_POST_MEMORY */
-/* #endif */ /* CONFIG_POST */

board/trab/rs485.c

@@ -1,205 +0,0 @@
-/*
- * (C) Copyright 2003
- * Martin Krause, TQ-Systems GmbH, <martin.krause@tqs.de>
- *
- * Based on arch/arm/cpu/arm920t/serial.c, by Gary Jennejohn
- * (C) Copyright 2002 Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- */
-
-#include <common.h>
-#include <asm/arch/s3c24x0_cpu.h>
-#include "rs485.h"
-
-static void rs485_setbrg (void);
-static void rs485_cfgio (void);
-static void set_rs485re(unsigned char rs485re_state);
-static void set_rs485de(unsigned char rs485de_state);
-static void rs485_setbrg (void);
-#ifdef	NOT_USED
-static void trab_rs485_disable_tx(void);
-static void trab_rs485_disable_rx(void);
-#endif
-
-#define UART_NR	S3C24X0_UART1
-
-/* CPLD-Register for controlling TRAB hardware functions */
-#define CPLD_RS485_RE           ((volatile unsigned long *)0x04028000)
-
-static void rs485_setbrg (void)
-{
-	struct s3c24x0_uart * const uart = s3c24x0_get_base_uart(UART_NR);
-	int i;
-	unsigned int reg = 0;
-
-	/* value is calculated so : (int)(PCLK/16./baudrate) -1 */
-	/* reg = (33000000 / (16 * gd->baudrate)) - 1; */
-	reg = (33000000 / (16 * 38400)) - 1;
-
-	/* FIFO enable, Tx/Rx FIFO clear */
-	uart->ufcon = 0x07;
-	uart->umcon = 0x0;
-	/* Normal,No parity,1 stop,8 bit */
-	uart->ulcon = 0x3;
-	/*
-	 * tx=level,rx=edge,disable timeout int.,enable rx error int.,
-	 * normal,interrupt or polling
-	 */
-	uart->ucon = 0x245;
-	uart->ubrdiv = reg;
-
-	for (i = 0; i < 100; i++);
-}
-
-static void rs485_cfgio (void)
-{
-	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
-
-	gpio->pfcon &= ~(0x3 << 2);
-	gpio->pfcon |=  (0x2 << 2); /* configure GPF1 as RXD1 */
-
-	gpio->pfcon &= ~(0x3 << 6);
-	gpio->pfcon |=  (0x2 << 6); /* configure GPF3 as TXD1 */
-
-	gpio->pfup |= (1 << 1); /* disable pullup on GPF1 */
-	gpio->pfup |= (1 << 3); /* disable pullup on GPF3 */
-
-	gpio->pacon &= ~(1 << 11); /* set GPA11 (RS485_DE) to output */
-}
-
-/*
- * Initialise the rs485 port with the given baudrate. The settings
- * are always 8 data bits, no parity, 1 stop bit, no start bits.
- *
- */
-int rs485_init (void)
-{
-	rs485_cfgio ();
-	rs485_setbrg ();
-
-	return (0);
-}
-
-/*
- * Read a single byte from the rs485 port. Returns 1 on success, 0
- * otherwise. When the function is succesfull, the character read is
- * written into its argument c.
- */
-int rs485_getc (void)
-{
-	struct s3c24x0_uart * const uart = s3c24x0_get_base_uart(UART_NR);
-
-	/* wait for character to arrive */
-	while (!(uart->utrstat & 0x1))
-		;
-
-	return uart->urxh & 0xff;
-}
-
-/*
- * Output a single byte to the rs485 port.
- */
-void rs485_putc (const char c)
-{
-	struct s3c24x0_uart * const uart = s3c24x0_get_base_uart(UART_NR);
-
-	/* wait for room in the tx FIFO */
-	while (!(uart->utrstat & 0x2))
-		;
-
-	uart->utxh = c;
-
-	/* If \n, also do \r */
-	if (c == '\n')
-		rs485_putc ('\r');
-}
-
-/*
- * Test whether a character is in the RX buffer
- */
-int rs485_tstc (void)
-{
-	struct s3c24x0_uart * const uart = s3c24x0_get_base_uart(UART_NR);
-
-	return uart->utrstat & 0x1;
-}
-
-void rs485_puts (const char *s)
-{
-	while (*s) {
-		rs485_putc (*s++);
-	}
-}
-
-
-/*
- * State table:
- *	RE	DE	Result
- *	1	1	XMIT
- *	0	0	RCV
- *	1	0	Shutdown
- */
-
-/* function that controls the receiver enable for the rs485 */
-/* rs485re_state reflects the level (0/1) of the RE pin */
-
-static void set_rs485re(unsigned char rs485re_state)
-{
-	if(rs485re_state)
-		*CPLD_RS485_RE = 0x010000;
-	else
-		*CPLD_RS485_RE = 0x0;
-}
-
-/* function that controls the sender enable for the rs485 */
-/* rs485de_state reflects the level (0/1) of the DE pin */
-
-static void set_rs485de(unsigned char rs485de_state)
-{
-	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
-
-	/* This is on PORT A bit 11 */
-	if(rs485de_state)
-		gpio->padat |= (1 << 11);
-	else
-		gpio->padat &= ~(1 << 11);
-}
-
-
-void trab_rs485_enable_tx(void)
-{
-	set_rs485de(1);
-	set_rs485re(1);
-}
-
-void trab_rs485_enable_rx(void)
-{
-	set_rs485re(0);
-	set_rs485de(0);
-}
-
-#ifdef	NOT_USED
-static void trab_rs485_disable_tx(void)
-{
-	set_rs485de(0);
-}
-
-static void trab_rs485_disable_rx(void)
-{
-	set_rs485re(1);
-}
-#endif

board/trab/rs485.h

@@ -1,37 +0,0 @@
-/*
- * (C) Copyright 2003
- * Martin Krause, TQ-Systems GmbH, <martin.krause@tqs.de>
- *
- * Based on arch/arm/cpu/arm920t/serial.c, by Gary Jennejohn
- * (C) Copyright 2002 Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- */
-
-#ifndef _RS485_H_
-#define _RS485_H_
-
-#include <asm/arch/s3c24x0_cpu.h>
-
-int rs485_init (void);
-int rs485_getc (void);
-void rs485_putc (const char c);
-int rs485_tstc (void);
-void rs485_puts (const char *s);
-void trab_rs485_enable_tx(void);
-void trab_rs485_enable_rx(void);
-
-#endif	/* _RS485_H_ */

board/trab/trab.c

@@ -1,436 +0,0 @@
-/*
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/* #define DEBUG */
-
-#include <common.h>
-#include <netdev.h>
-#include <malloc.h>
-#include <asm/arch/s3c24x0_cpu.h>
-#include <command.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_SYS_BRIGHTNESS
-static void spi_init(void);
-static void wait_transmit_done(void);
-static void tsc2000_write(unsigned int page, unsigned int reg,
-						  unsigned int data);
-static void tsc2000_set_brightness(void);
-#endif
-#ifdef CONFIG_MODEM_SUPPORT
-static int key_pressed(void);
-extern void disable_putc(void);
-extern int do_mdm_init; /* defined in common/main.c */
-
-/*
- * We need a delay of at least 500 us after turning on the VFD clock
- * before we can read any useful information for the CPLD controlling
- * the keyboard switches. Let's play safe and wait 5 ms. The problem
- * is that timers are not available yet, so we use a manually timed
- * loop.
- */
-#define KBD_MDELAY	5000
-static void udelay_no_timer (int usec)
-{
-	int i;
-	int delay = usec * 3;
-
-	for (i = 0; i < delay; i ++) gd->bd->bi_arch_number = MACH_TYPE_TRAB;
-}
-#endif /* CONFIG_MODEM_SUPPORT */
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-
-int board_init ()
-{
-#if defined(CONFIG_VFD)
-	extern int vfd_init_clocks(void);
-#endif
-	struct s3c24x0_clock_power * const clk_power =
-					s3c24x0_get_base_clock_power();
-	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
-
-	/* memory and cpu-speed are setup before relocation */
-#ifdef CONFIG_TRAB_50MHZ
-	/* change the clock to be 50 MHz 1:1:1 */
-	/* MDIV:0x5c PDIV:4 SDIV:2 */
-	clk_power->mpllcon = 0x5c042;
-	clk_power->clkdivn = 0;
-#else
-	/* change the clock to be 133 MHz 1:2:4 */
-	/* MDIV:0x7d PDIV:4 SDIV:1 */
-	clk_power->mpllcon = 0x7d041;
-	clk_power->clkdivn = 3;
-#endif
-
-	/* set up the I/O ports */
-	gpio->pacon = 0x3ffff;
-	gpio->pbcon = 0xaaaaaaaa;
-	gpio->pbup  = 0xffff;
-	/* INPUT nCTS0 nRTS0 TXD[1] TXD[0] RXD[1] RXD[0]	*/
-	/*  00,    10,      10,      10,      10,      10,      10	*/
-	gpio->pfcon = (2<<0) | (2<<2) | (2<<4) | (2<<6) | (2<<8) | (2<<10);
-#ifdef CONFIG_HWFLOW
-	/* do not pull up RXD0, RXD1, TXD0, TXD1, CTS0, RTS0 */
-	gpio->pfup  = (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5);
-#else
-	/* do not pull up RXD0, RXD1, TXD0, TXD1 */
-	gpio->pfup  = (1<<0) | (1<<1) | (1<<2) | (1<<3);
-#endif
-	gpio->pgcon = 0x0;
-	gpio->pgup  = 0x0;
-	gpio->opencr = 0x0;
-
-	/* suppress flicker of the VFDs */
-	gpio->misccr = 0x40;
-	gpio->pfcon |= (2<<12);
-
-	gd->bd->bi_arch_number = MACH_TYPE_TRAB;
-
-	/* adress of boot parameters */
-	gd->bd->bi_boot_params = 0x0c000100;
-
-	/* Make sure both buzzers are turned off */
-	gpio->pdcon |= 0x5400;
-	gpio->pddat &= ~0xE0;
-
-#ifdef CONFIG_VFD
-	vfd_init_clocks();
-#endif /* CONFIG_VFD */
-
-#ifdef CONFIG_MODEM_SUPPORT
-	udelay_no_timer (KBD_MDELAY);
-
-	if (key_pressed()) {
-		disable_putc();	/* modem doesn't understand banner etc */
-		do_mdm_init = 1;
-	}
-#endif	/* CONFIG_MODEM_SUPPORT */
-
-#ifdef CONFIG_DRIVER_S3C24X0_I2C
-	/* Configure I/O ports PG5 und PG6 for I2C */
-	gpio->pgcon = (gpio->pgcon & 0x003c00) | 0x003c00;
-#endif /* CONFIG_DRIVER_S3C24X0_I2C */
-
-	return 0;
-}
-
-int dram_init (void)
-{
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-	return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Keyboard Controller
- */
-
-/* Maximum key number */
-#define KEYBD_KEY_NUM		4
-
-#define KBD_DATA	(((*(volatile ulong *)0x04020000) >> 16) & 0xF)
-
-static char *key_match (ulong);
-
-int misc_init_r (void)
-{
-	ulong kbd_data = KBD_DATA;
-	char *str;
-	char keybd_env[KEYBD_KEY_NUM + 1];
-	int i;
-
-#ifdef CONFIG_VERSION_VARIABLE
-	{
-		/* Set version variable. Please note, that this variable is
-		 * also set in main_loop() later in the boot process. The
-		 * version variable has to be set this early, because so it
-		 * could be used in script files on an usb stick, which
-		 * might be called during do_auto_update() */
-		extern char version_string[];
-
-		setenv ("ver", version_string);
-	}
-#endif /* CONFIG_VERSION_VARIABLE */
-
-#ifdef CONFIG_AUTO_UPDATE
-	{
-		extern int do_auto_update(void);
-		/* this has priority over all else */
-		do_auto_update();
-	}
-#endif
-
-	for (i = 0; i < KEYBD_KEY_NUM; ++i) {
-		keybd_env[i] = '0' + ((kbd_data >> i) & 1);
-	}
-	keybd_env[i] = '\0';
-	debug ("** Setting keybd=\"%s\"\n", keybd_env);
-	setenv ("keybd", keybd_env);
-
-	str = strdup (key_match (kbd_data));	/* decode keys */
-
-#ifdef CONFIG_PREBOOT	/* automatically configure "preboot" command on key match */
-	debug ("** Setting preboot=\"%s\"\n", str);
-	setenv ("preboot", str);	/* set or delete definition */
-#endif /* CONFIG_PREBOOT */
-	if (str != NULL) {
-		free (str);
-	}
-
-#ifdef CONFIG_SYS_BRIGHTNESS
-	tsc2000_set_brightness();
-#endif
-	return (0);
-}
-
-#ifdef CONFIG_PREBOOT
-
-static uchar kbd_magic_prefix[] = "key_magic";
-static uchar kbd_command_prefix[] = "key_cmd";
-
-static int compare_magic (ulong kbd_data, char *str)
-{
-	uchar key_mask;
-
-	debug ("compare_magic: kbd: %04lx  str: \"%s\"\n",kbd_data,str);
-	for (; *str; str++)
-	{
-		uchar c = *str - '1';
-
-		if (c >= KEYBD_KEY_NUM)		/* bad key number */
-			return -1;
-
-		key_mask = 1 << c;
-
-		if (!(kbd_data & key_mask)) {	/* key not pressed */
-			debug ( "compare_magic: "
-				"kbd: %04lx mask: %04lx - key not pressed\n",
-				kbd_data, key_mask );
-			return -1;
-		}
-
-		kbd_data &= ~key_mask;
-	}
-
-	if (kbd_data) {				/* key(s) not released */
-		debug ( "compare_magic: "
-			"kbd: %04lx - key(s) not released\n", kbd_data);
-		return -1;
-	}
-
-	return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Check if pressed key(s) match magic sequence,
- * and return the command string associated with that key(s).
- *
- * If no key press was decoded, NULL is returned.
- *
- * Note: the first character of the argument will be overwritten with
- * the "magic charcter code" of the decoded key(s), or '\0'.
- *
- *
- * Note: the string points to static environment data and must be
- * saved before you call any function that modifies the environment.
- */
-static char *key_match (ulong kbd_data)
-{
-	char magic[sizeof (kbd_magic_prefix) + 1];
-	char cmd_name[sizeof (kbd_command_prefix) + 1];
-	char *suffix;
-	char *kbd_magic_keys;
-
-	/*
-	 * The following string defines the characters that can pe appended
-	 * to "key_magic" to form the names of environment variables that
-	 * hold "magic" key codes, i. e. such key codes that can cause
-	 * pre-boot actions. If the string is empty (""), then only
-	 * "key_magic" is checked (old behaviour); the string "125" causes
-	 * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
-	 */
-	if ((kbd_magic_keys = getenv ("magic_keys")) == NULL)
-		kbd_magic_keys = "";
-
-	debug ("key_match: magic_keys=\"%s\"\n", kbd_magic_keys);
-
-	/* loop over all magic keys;
-	 * use '\0' suffix in case of empty string
-	 */
-	for (suffix=kbd_magic_keys; *suffix || suffix==kbd_magic_keys; ++suffix)
-	{
-		sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
-
-		debug ("key_match: magic=\"%s\"\n",
-			getenv(magic) ? getenv(magic) : "<UNDEFINED>");
-
-		if (compare_magic(kbd_data, getenv(magic)) == 0)
-		{
-			sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
-			debug ("key_match: cmdname %s=\"%s\"\n",
-				cmd_name,
-				getenv (cmd_name) ?
-					getenv (cmd_name) :
-					"<UNDEFINED>");
-			return (getenv (cmd_name));
-		}
-	}
-	debug ("key_match: no match\n");
-	return (NULL);
-}
-#endif							/* CONFIG_PREBOOT */
-
-/* Read Keyboard status */
-int do_kbd (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
-	ulong kbd_data = KBD_DATA;
-	char keybd_env[KEYBD_KEY_NUM + 1];
-	int i;
-
-	puts ("Keys:");
-	for (i = 0; i < KEYBD_KEY_NUM; ++i) {
-		keybd_env[i] = '0' + ((kbd_data >> i) & 1);
-		printf (" %c", keybd_env[i]);
-	}
-	keybd_env[i] = '\0';
-	putc ('\n');
-	setenv ("keybd", keybd_env);
-	return 0;
-}
-
-U_BOOT_CMD(
-	kbd,	1,	1,	do_kbd,
-	"read keyboard status",
-	""
-);
-
-#ifdef CONFIG_MODEM_SUPPORT
-static int key_pressed(void)
-{
-	return (compare_magic(KBD_DATA, CONFIG_MODEM_KEY_MAGIC) == 0);
-}
-#endif	/* CONFIG_MODEM_SUPPORT */
-
-#ifdef CONFIG_SYS_BRIGHTNESS
-
-static inline void SET_CS_TOUCH(void)
-{
-	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
-
-	gpio->pddat &= 0x5FF;
-}
-
-static inline void CLR_CS_TOUCH(void)
-{
-	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
-
-	gpio->pddat |= 0x200;
-}
-
-static void spi_init(void)
-{
-	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
-	struct s3c24x0_spi * const spi = s3c24x0_get_base_spi();
-	int i;
-
-	/* Configure I/O ports. */
-	gpio->pdcon = (gpio->pdcon & 0xF3FFFF) | 0x040000;
-	gpio->pgcon = (gpio->pgcon & 0x0F3FFF) | 0x008000;
-	gpio->pgcon = (gpio->pgcon & 0x0CFFFF) | 0x020000;
-	gpio->pgcon = (gpio->pgcon & 0x03FFFF) | 0x080000;
-
-	CLR_CS_TOUCH();
-
-	spi->ch[0].sppre = 0x1F; /* Baudrate ca. 514kHz */
-	spi->ch[0].sppin = 0x01;  /* SPI-MOSI holds Level after last bit */
-	spi->ch[0].spcon = 0x1A; /* Polling, Prescale, Master, CPOL=0, CPHA=1 */
-
-	/* Dummy byte ensures clock to be low. */
-	for (i = 0; i < 10; i++) {
-		spi->ch[0].sptdat = 0xFF;
-	}
-	wait_transmit_done();
-}
-
-static void wait_transmit_done(void)
-{
-	struct s3c24x0_spi * const spi = s3c24x0_get_base_spi();
-
-	while (!(spi->ch[0].spsta & 0x01)) /* wait until transfer is done */
-		;
-}
-
-static void tsc2000_write(unsigned int page, unsigned int reg,
-						  unsigned int data)
-{
-	struct s3c24x0_spi * const spi = s3c24x0_get_base_spi();
-	unsigned int command;
-
-	SET_CS_TOUCH();
-	command = 0x0000;
-	command |= (page << 11);
-	command |= (reg << 5);
-
-	spi->ch[0].sptdat = (command & 0xFF00) >> 8;
-	wait_transmit_done();
-	spi->ch[0].sptdat = (command & 0x00FF);
-	wait_transmit_done();
-	spi->ch[0].sptdat = (data & 0xFF00) >> 8;
-	wait_transmit_done();
-	spi->ch[0].sptdat = (data & 0x00FF);
-	wait_transmit_done();
-
-	CLR_CS_TOUCH();
-}
-
-static void tsc2000_set_brightness(void)
-{
-	char tmp[10];
-	int i, br;
-
-	spi_init();
-	tsc2000_write(1, 2, 0x0); /* Power up DAC */
-
-	i = getenv_f("brightness", tmp, sizeof(tmp));
-	br = (i > 0)
-		? (int) simple_strtoul (tmp, NULL, 10)
-		: CONFIG_SYS_BRIGHTNESS;
-
-	tsc2000_write(0, 0xb, br & 0xff);
-}
-#endif
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
-	int rc = 0;
-#ifdef CONFIG_CS8900
-	rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
-#endif
-	return rc;
-}
-#endif

board/trab/tsc2000.c

@@ -1,366 +0,0 @@
-/*
- * Functions to access the TSC2000 controller on TRAB board (used for scanning
- * thermo sensors)
- *
- * Copyright (C) 2003 Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
- *
- * Copyright (C) 2002 DENX Software Engineering, Wolfgang Denk, wd@denx.de
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/s3c24x0_cpu.h>
-#include <asm/io.h>
-#include <div64.h>
-#include "tsc2000.h"
-
-#include "Pt1000_temp_data.h"
-
-/* helper function */
-#define abs(value) (((value) < 0) ? ((value)*-1) : (value))
-
-/*
- * Maximal allowed deviation between two immediate meassurments of an analog
- * thermo channel. 1 DIGIT = 0.0276 °C. This is used to filter sporadic
- * "jumps" in measurment.
- */
-#define MAX_DEVIATION	18	/* unit: DIGITs of adc; 18 DIGIT = 0.5 °C */
-
-void tsc2000_spi_init(void)
-{
-	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
-	struct s3c24x0_spi * const spi = s3c24x0_get_base_spi();
-	int i;
-
-	/* Configure I/O ports. */
-	gpio->pdcon = (gpio->pdcon & 0xF3FFFF) | 0x040000;
-	gpio->pgcon = (gpio->pgcon & 0x0F3FFF) | 0x008000;
-	gpio->pgcon = (gpio->pgcon & 0x0CFFFF) | 0x020000;
-	gpio->pgcon = (gpio->pgcon & 0x03FFFF) | 0x080000;
-
-	CLR_CS_TOUCH();
-
-	spi->ch[0].sppre = 0x1F; /* Baud-rate ca. 514kHz */
-	spi->ch[0].sppin = 0x01; /* SPI-MOSI holds Level after last bit */
-	spi->ch[0].spcon = 0x1A; /* Polling, Prescaler, Master, CPOL=0,
-				    CPHA=1 */
-
-	/* Dummy byte ensures clock to be low. */
-	for (i = 0; i < 10; i++) {
-		spi->ch[0].sptdat = 0xFF;
-	}
-	spi_wait_transmit_done();
-}
-
-
-void spi_wait_transmit_done(void)
-{
-	struct s3c24x0_spi * const spi = s3c24x0_get_base_spi();
-
-	while (!(spi->ch[0].spsta & 0x01)) /* wait until transfer is done */
-		;
-}
-
-
-void tsc2000_write(unsigned short reg, unsigned short data)
-{
-	struct s3c24x0_spi * const spi = s3c24x0_get_base_spi();
-	unsigned int command;
-
-	SET_CS_TOUCH();
-	command = reg;
-	spi->ch[0].sptdat = (command & 0xFF00) >> 8;
-	spi_wait_transmit_done();
-	spi->ch[0].sptdat = (command & 0x00FF);
-	spi_wait_transmit_done();
-	spi->ch[0].sptdat = (data & 0xFF00) >> 8;
-	spi_wait_transmit_done();
-	spi->ch[0].sptdat = (data & 0x00FF);
-	spi_wait_transmit_done();
-
-	CLR_CS_TOUCH();
-}
-
-
-unsigned short tsc2000_read (unsigned short reg)
-{
-	unsigned short command, data;
-	struct s3c24x0_spi * const spi = s3c24x0_get_base_spi();
-
-	SET_CS_TOUCH();
-	command = 0x8000 | reg;
-
-	spi->ch[0].sptdat = (command & 0xFF00) >> 8;
-	spi_wait_transmit_done();
-	spi->ch[0].sptdat = (command & 0x00FF);
-	spi_wait_transmit_done();
-
-	spi->ch[0].sptdat = 0xFF;
-	spi_wait_transmit_done();
-	data = spi->ch[0].sprdat;
-	spi->ch[0].sptdat = 0xFF;
-	spi_wait_transmit_done();
-
-	CLR_CS_TOUCH();
-	return (spi->ch[0].sprdat & 0x0FF) | (data << 8);
-}
-
-
-void tsc2000_set_mux (unsigned int channel)
-{
-	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
-
-	CLR_MUX1_ENABLE; CLR_MUX2_ENABLE;
-	CLR_MUX3_ENABLE; CLR_MUX4_ENABLE;
-	switch (channel) {
-	case 0:
-		CLR_MUX0; CLR_MUX1;
-		SET_MUX1_ENABLE;
-		break;
-	case 1:
-		SET_MUX0; CLR_MUX1;
-		SET_MUX1_ENABLE;
-		break;
-	case 2:
-		CLR_MUX0; SET_MUX1;
-		SET_MUX1_ENABLE;
-		break;
-	case 3:
-		SET_MUX0; SET_MUX1;
-		SET_MUX1_ENABLE;
-		break;
-	case 4:
-		CLR_MUX0; CLR_MUX1;
-		SET_MUX2_ENABLE;
-		break;
-	case 5:
-		SET_MUX0; CLR_MUX1;
-		SET_MUX2_ENABLE;
-		break;
-	case 6:
-		CLR_MUX0; SET_MUX1;
-		SET_MUX2_ENABLE;
-		break;
-	case 7:
-		SET_MUX0; SET_MUX1;
-		SET_MUX2_ENABLE;
-		break;
-	case 8:
-		CLR_MUX0; CLR_MUX1;
-		SET_MUX3_ENABLE;
-		break;
-	case 9:
-		SET_MUX0; CLR_MUX1;
-		SET_MUX3_ENABLE;
-		break;
-	case 10:
-		CLR_MUX0; SET_MUX1;
-		SET_MUX3_ENABLE;
-		break;
-	case 11:
-		SET_MUX0; SET_MUX1;
-		SET_MUX3_ENABLE;
-		break;
-	case 12:
-		CLR_MUX0; CLR_MUX1;
-		SET_MUX4_ENABLE;
-		break;
-	case 13:
-		SET_MUX0; CLR_MUX1;
-		SET_MUX4_ENABLE;
-		break;
-	case 14:
-		CLR_MUX0; SET_MUX1;
-		SET_MUX4_ENABLE;
-		break;
-	case 15:
-		SET_MUX0; SET_MUX1;
-		SET_MUX4_ENABLE;
-		break;
-	default:
-		CLR_MUX0; CLR_MUX1;
-	}
-}
-
-
-void tsc2000_set_range (unsigned int range)
-{
-	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
-
-	switch (range) {
-	case 1:
-		CLR_SEL_TEMP_V_0; SET_SEL_TEMP_V_1;
-		CLR_SEL_TEMP_V_2; CLR_SEL_TEMP_V_3;
-		break;
-	case 2:
-		CLR_SEL_TEMP_V_0; CLR_SEL_TEMP_V_1;
-		CLR_SEL_TEMP_V_2; SET_SEL_TEMP_V_3;
-		break;
-	case 3:
-		SET_SEL_TEMP_V_0; CLR_SEL_TEMP_V_1;
-		SET_SEL_TEMP_V_2; CLR_SEL_TEMP_V_3;
-		break;
-	}
-}
-
-
-u16 tsc2000_read_channel (unsigned int channel)
-{
-	u16 res;
-
-	tsc2000_set_mux(channel);
-	udelay(20 * TSC2000_DELAY_BASE);
-
-	tsc2000_write(TSC2000_REG_ADC, 0x2036);
-	adc_wait_conversion_done ();
-	res = tsc2000_read(TSC2000_REG_AUX1);
-	return res;
-}
-
-
-s32 tsc2000_contact_temp (void)
-{
-	long adc_pt1000, offset;
-	long u_pt1000;
-	long contact_temp;
-	long temp1, temp2;
-
-	tsc2000_reg_init ();
-	tsc2000_set_range (3);
-
-	/*
-	 * Because of sporadic "jumps" in the measured adc values every
-	 * channel is read two times. If there is a significant difference
-	 * between the two measurements, then print an error and do a third
-	 * measurement, because it is very unlikely that a successive third
-	 * measurement goes also wrong.
-	 */
-	temp1 = tsc2000_read_channel (14);
-	temp2 = tsc2000_read_channel (14);
-	if (abs(temp2 - temp1) < MAX_DEVIATION)
-		adc_pt1000 = temp2;
-	else {
-		printf ("%s: read adc value (channel 14) exceeded max allowed "
-			"deviation: %d * 0.0276 °C\n",
-			__FUNCTION__, MAX_DEVIATION);
-		printf ("adc value 1: %ld DIGITs\nadc value 2: %ld DIGITs\n",
-			temp1, temp2);
-		adc_pt1000 = tsc2000_read_channel (14);
-		printf ("use (third read) adc value: adc_pt1000 = "
-			"%ld DIGITs\n",	adc_pt1000);
-	}
-	debug ("read channel 14 (pt1000 adc value): %ld\n", adc_pt1000);
-
-	temp1 = tsc2000_read_channel (15);
-	temp2 = tsc2000_read_channel (15);
-	if (abs(temp2 - temp1) < MAX_DEVIATION)
-		offset = temp2;
-	else {
-		printf ("%s: read adc value (channel 15) exceeded max allowed "
-			"deviation: %d * 0.0276 °C\n",
-			__FUNCTION__, MAX_DEVIATION);
-		printf ("adc value 1: %ld DIGITs\nadc value 2: %ld DIGITs\n",
-			temp1, temp2);
-		offset = tsc2000_read_channel (15);
-		printf ("use (third read) adc value: offset = %ld DIGITs\n",
-			offset);
-	}
-	debug ("read channel 15 (offset): %ld\n", offset);
-
-	/*
-	 * Formula for calculating voltage drop on PT1000 resistor: u_pt1000 =
-	 * x_range3 * (adc_raw - offset) / 10. Formula to calculate x_range3:
-	 * x_range3 = (2500 * (1000000 + err_vref + err_amp3)) / (4095*6). The
-	 * error correction Values err_vref and err_amp3 are assumed as 0 in
-	 * u-boot, because this could cause only a very small error (< 1%).
-	 */
-	u_pt1000 = (101750 * (adc_pt1000 - offset)) / 10;
-	debug ("u_pt1000: %ld\n", u_pt1000);
-
-	if (tsc2000_interpolate(u_pt1000, Pt1000_temp_table,
-				&contact_temp) == -1) {
-		printf ("%s: error interpolating PT1000 vlaue\n",
-			 __FUNCTION__);
-		return (-1000);
-	}
-	debug ("contact_temp: %ld\n", contact_temp);
-
-	return contact_temp;
-}
-
-
-void tsc2000_reg_init (void)
-{
-	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
-
-	tsc2000_write(TSC2000_REG_ADC, 0x2036);
-	tsc2000_write(TSC2000_REG_REF, 0x0011);
-	tsc2000_write(TSC2000_REG_DACCTL, 0x0000);
-
-	CON_MUX0;
-	CON_MUX1;
-
-	CON_MUX1_ENABLE;
-	CON_MUX2_ENABLE;
-	CON_MUX3_ENABLE;
-	CON_MUX4_ENABLE;
-
-	CON_SEL_TEMP_V_0;
-	CON_SEL_TEMP_V_1;
-	CON_SEL_TEMP_V_2;
-	CON_SEL_TEMP_V_3;
-
-	tsc2000_set_mux(0);
-	tsc2000_set_range(0);
-}
-
-
-int tsc2000_interpolate(long value, long data[][2], long *result)
-{
-	int i;
-	unsigned long long val;
-
-	/* the data is sorted and the first element is upper
-	 * limit so we can easily check for out-of-band values
-	 */
-	if (data[0][0] < value || data[1][0] > value)
-		return -1;
-
-	i = 1;
-	while (data[i][0] < value)
-		i++;
-
-	/* To prevent overflow we have to store the intermediate
-	   result in 'long long'.
-	*/
-
-	val = ((unsigned long long)(data[i][1] - data[i-1][1])
-		   * (unsigned long long)(value - data[i-1][0]));
-	do_div(val, (data[i][0] - data[i-1][0]));
-	*result = data[i-1][1] + val;
-
-	return 0;
-}
-
-
-void adc_wait_conversion_done(void)
-{
-	while (!(tsc2000_read(TSC2000_REG_ADC) & (1 << 14)));
-}

board/trab/tsc2000.h

@@ -1,148 +0,0 @@
-/*
- * Functions to access the TSC2000 controller on TRAB board (used for scanning
- * thermo sensors)
- *
- * Copyright (C) 2003 Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
- *
- * Copyright (C) 2002 DENX Software Engineering, Wolfgang Denk, wd@denx.de
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _TSC2000_H_
-#define _TSC2000_H_
-
-/* temperature channel multiplexer definitions */
-#define CON_MUX0	(gpio->pccon = (gpio->pccon & 0x0FFFFFCFF) | 0x00000100)
-#define CLR_MUX0	(gpio->pcdat &= 0x0FFEF)
-#define SET_MUX0	(gpio->pcdat |= 0x00010)
-
-#define CON_MUX1	(gpio->pccon = (gpio->pccon & 0x0FFFFF3FF) | 0x00000400)
-#define CLR_MUX1	(gpio->pcdat &= 0x0FFDF)
-#define SET_MUX1	(gpio->pcdat |= 0x00020)
-
-#define CON_MUX1_ENABLE	(gpio->pccon = (gpio->pccon & 0x0FFFFCFFF) | 0x00001000)
-#define CLR_MUX1_ENABLE	(gpio->pcdat |= 0x00040)
-#define SET_MUX1_ENABLE	(gpio->pcdat &= 0x0FFBF)
-
-#define CON_MUX2_ENABLE	(gpio->pccon = (gpio->pccon & 0x0FFFF3FFF) | 0x00004000)
-#define CLR_MUX2_ENABLE	(gpio->pcdat |= 0x00080)
-#define SET_MUX2_ENABLE	(gpio->pcdat &= 0x0FF7F)
-
-#define CON_MUX3_ENABLE	(gpio->pccon = (gpio->pccon & 0x0FFFCFFFF) | 0x00010000)
-#define CLR_MUX3_ENABLE	(gpio->pcdat |= 0x00100)
-#define SET_MUX3_ENABLE	(gpio->pcdat &= 0x0FEFF)
-
-#define CON_MUX4_ENABLE	(gpio->pccon = (gpio->pccon & 0x0FFF3FFFF) | 0x00040000)
-#define CLR_MUX4_ENABLE	(gpio->pcdat |= 0x00200)
-#define SET_MUX4_ENABLE	(gpio->pcdat &= 0x0FDFF)
-
-#define CON_SEL_TEMP_V_0	(gpio->pccon = (gpio->pccon & 0x0FFCFFFFF) | \
-							0x00100000)
-#define CLR_SEL_TEMP_V_0	(gpio->pcdat &= 0x0FBFF)
-#define SET_SEL_TEMP_V_0	(gpio->pcdat |= 0x00400)
-
-#define CON_SEL_TEMP_V_1	(gpio->pccon = (gpio->pccon & 0x0FF3FFFFF) | \
-		0x00400000)
-#define CLR_SEL_TEMP_V_1	(gpio->pcdat &= 0x0F7FF)
-#define SET_SEL_TEMP_V_1	(gpio->pcdat |= 0x00800)
-
-#define CON_SEL_TEMP_V_2	(gpio->pccon = (gpio->pccon & 0x0FCFFFFFF) | \
-		0x01000000)
-#define CLR_SEL_TEMP_V_2	(gpio->pcdat &= 0x0EFFF)
-#define SET_SEL_TEMP_V_2	(gpio->pcdat |= 0x01000)
-
-#define CON_SEL_TEMP_V_3	(gpio->pccon = (gpio->pccon & 0x0F3FFFFFF) | \
-		0x04000000)
-#define CLR_SEL_TEMP_V_3	(gpio->pcdat &= 0x0DFFF)
-#define SET_SEL_TEMP_V_3	(gpio->pcdat |= 0x02000)
-
-/* TSC2000 register definition */
-#define TSC2000_REG_X		((0 << 11) | (0 << 5))
-#define TSC2000_REG_Y		((0 << 11) | (1 << 5))
-#define TSC2000_REG_Z1		((0 << 11) | (2 << 5))
-#define TSC2000_REG_Z2		((0 << 11) | (3 << 5))
-#define TSC2000_REG_BAT1	((0 << 11) | (5 << 5))
-#define TSC2000_REG_BAT2	((0 << 11) | (6 << 5))
-#define TSC2000_REG_AUX1	((0 << 11) | (7 << 5))
-#define TSC2000_REG_AUX2	((0 << 11) | (8 << 5))
-#define TSC2000_REG_TEMP1	((0 << 11) | (9 << 5))
-#define TSC2000_REG_TEMP2	((0 << 11) | (0xA << 5))
-#define TSC2000_REG_DAC		((0 << 11) | (0xB << 5))
-#define TSC2000_REG_ZERO	((0 << 11) | (0x10 << 5))
-#define TSC2000_REG_ADC		((1 << 11) | (0 << 5))
-#define TSC2000_REG_DACCTL	((1 << 11) | (2 << 5))
-#define TSC2000_REG_REF		((1 << 11) | (3 << 5))
-#define TSC2000_REG_RESET	((1 << 11) | (4 << 5))
-#define TSC2000_REG_CONFIG	((1 << 11) | (5 << 5))
-
-/* bit definition of TSC2000 ADC register */
-#define TC_PSM			(1 << 15)
-#define TC_STS			(1 << 14)
-#define TC_AD3			(1 << 13)
-#define TC_AD2			(1 << 12)
-#define TC_AD1			(1 << 11)
-#define TC_AD0			(1 << 10)
-#define TC_RS1			(1 << 9)
-#define TC_RS0			(1 << 8)
-#define TC_AV1			(1 << 7)
-#define TC_AV0			(1 << 6)
-#define TC_CL1			(1 << 5)
-#define TC_CL0			(1 << 4)
-#define TC_PV2			(1 << 3)
-#define TC_PV1			(1 << 2)
-#define TC_PV0			(1 << 1)
-
-/* default value for TSC2000 ADC register for use with touch functions */
-#define DEFAULT_ADC		(TC_PV1 | TC_AV0 | TC_AV1 | TC_RS0)
-
-#define TSC2000_DELAY_BASE	500
-#define TSC2000_NO_SENSOR	-0x10000
-
-#define ERROR_BATTERY		220	/* must be adjusted, if R68 is changed on TRAB */
-
-void tsc2000_write(unsigned short, unsigned short);
-unsigned short tsc2000_read (unsigned short);
-u16 tsc2000_read_channel (unsigned int);
-void tsc2000_set_mux (unsigned int);
-void tsc2000_set_range (unsigned int);
-void tsc2000_reg_init (void);
-s32 tsc2000_contact_temp (void);
-void spi_wait_transmit_done (void);
-void tsc2000_spi_init(void);
-int tsc2000_interpolate(long value, long data[][2], long *result);
-void adc_wait_conversion_done(void);
-
-
-static inline void SET_CS_TOUCH(void)
-{
-	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
-
-	gpio->pddat &= 0x5FF;
-}
-
-
-static inline void CLR_CS_TOUCH(void)
-{
-	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
-
-	gpio->pddat |= 0x200;
-}
-
-#endif	/* _TSC2000_H_ */

board/trab/u-boot.lds

@@ -1,64 +0,0 @@
-/*
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text      :
-	{
-	  arch/arm/cpu/arm920t/start.o	(.text)
-	  lib/zlib.o	(.text)
-	  lib/crc32.o	(.text)
-	  lib/string.o	(.text)
-
-	. = DEFINED(env_offset) ? env_offset : .;
-	  common/env_embedded.o	(.ppcenv)
-
-	  *(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-	. = ALIGN(4);
-	.data : { *(.data) }
-
-	. = ALIGN(4);
-	.got : { *(.got) }
-
-	. = .;
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
-
-	. = ALIGN(4);
-	__bss_start = .;
-	.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
-	__bss_end__ = .;
-}

board/trab/vfd.c

@@ -1,574 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering -- wd@denx.de
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/************************************************************************/
-/* ** DEBUG SETTINGS							*/
-/************************************************************************/
-
-/* #define DEBUG	*/
-
-/************************************************************************/
-/* ** HEADER FILES							*/
-/************************************************************************/
-
-#include <config.h>
-#include <common.h>
-#include <version.h>
-#include <stdarg.h>
-#include <linux/types.h>
-#include <stdio_dev.h>
-#include <asm/arch/s3c24x0_cpu.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_VFD
-
-/************************************************************************/
-/* ** CONFIG STUFF -- should be moved to board config file		*/
-/************************************************************************/
-
-/************************************************************************/
-
-#ifndef PAGE_SIZE
-#define	PAGE_SIZE	4096
-#endif
-
-#define ROT	0x09
-#define BLAU	0x0C
-#define VIOLETT	0X0D
-
-/* MAGIC */
-#define	FRAME_BUF_SIZE	((256*4*56)/8)
-#define frame_buf_offs 4
-
-/* defines for starting Timer3 as CPLD-Clk */
-#define START3			(1 << 16)
-#define UPDATE3			(1 << 17)
-#define INVERT3			(1 << 18)
-#define RELOAD3			(1 << 19)
-
-/* CPLD-Register for controlling vfd-blank-signal */
-#define VFD_DISABLE	(*(volatile uchar *)0x04038000=0x0000)
-#define VFD_ENABLE	(*(volatile uchar *)0x04038000=0x0001)
-
-/* Supported VFD Types */
-#define	VFD_TYPE_T119C		1	/* Noritake T119C VFD */
-#define	VFD_TYPE_MN11236	2
-
-/*#define NEW_CPLD_CLK*/
-
-int vfd_board_id;
-
-/* taken from armboot/common/vfd.c */
-unsigned long adr_vfd_table[112][18][2][4][2];
-unsigned char bit_vfd_table[112][18][2][4][2];
-
-/*
- * initialize the values for the VFD-grid-control in the framebuffer
- */
-void init_grid_ctrl(void)
-{
-	ulong adr, grid_cycle;
-	unsigned int bit, display;
-	unsigned char temp, bit_nr;
-
-	/*
-	 * clear frame buffer (logical clear => set to "black")
-	 */
-	memset ((void *)(gd->fb_base), 0, FRAME_BUF_SIZE);
-
-	switch (gd->vfd_type) {
-	case VFD_TYPE_T119C:
-	    for (display=0; display<4; display++) {
-		for(grid_cycle=0; grid_cycle<56; grid_cycle++) {
-			bit = grid_cycle * 256  * 4 +
-			     (grid_cycle + 200) * 4 +
-			     frame_buf_offs + display;
-			/* wrap arround if offset (see manual S3C2400) */
-			if (bit>=FRAME_BUF_SIZE*8)
-				bit = bit - (FRAME_BUF_SIZE * 8);
-			adr = gd->fb_base + (bit/32) * 4 + (3 - (bit%32) / 8);
-			bit_nr = bit % 8;
-			bit_nr = (bit_nr > 3) ? bit_nr-4 : bit_nr+4;
-			temp=(*(volatile unsigned char*)(adr));
-			temp |=  (1<<bit_nr);
-			(*(volatile unsigned char*)(adr))=temp;
-
-			if(grid_cycle<55)
-				bit = grid_cycle*256*4+(grid_cycle+201)*4+frame_buf_offs+display;
-			else
-				bit = grid_cycle*256*4+200*4+frame_buf_offs+display-4;	/* grid nr. 0 */
-			/* wrap arround if offset (see manual S3C2400) */
-			if (bit>=FRAME_BUF_SIZE*8)
-				bit = bit-(FRAME_BUF_SIZE*8);
-			adr = gd->fb_base+(bit/32)*4+(3-(bit%32)/8);
-			bit_nr = bit%8;
-			bit_nr = (bit_nr>3)?bit_nr-4:bit_nr+4;
-			temp=(*(volatile unsigned char*)(adr));
-			temp |=  (1<<bit_nr);
-			(*(volatile unsigned char*)(adr))=temp;
-		}
-	    }
-	    break;
-	case VFD_TYPE_MN11236:
-	    for (display=0; display<4; display++) {
-		for (grid_cycle=0; grid_cycle<38; grid_cycle++) {
-			bit = grid_cycle * 256  * 4 +
-			     (253 - grid_cycle) * 4 +
-			     frame_buf_offs + display;
-			/* wrap arround if offset (see manual S3C2400) */
-			if (bit>=FRAME_BUF_SIZE*8)
-				bit = bit - (FRAME_BUF_SIZE * 8);
-			adr = gd->fb_base + (bit/32) * 4 + (3 - (bit%32) / 8);
-			bit_nr = bit % 8;
-			bit_nr = (bit_nr > 3) ? bit_nr-4 : bit_nr+4;
-			temp=(*(volatile unsigned char*)(adr));
-			temp |=  (1<<bit_nr);
-			(*(volatile unsigned char*)(adr))=temp;
-
-			if(grid_cycle<37)
-				bit = grid_cycle*256*4+(252-grid_cycle)*4+frame_buf_offs+display;
-
-			/* wrap arround if offset (see manual S3C2400) */
-			if (bit>=FRAME_BUF_SIZE*8)
-				bit = bit-(FRAME_BUF_SIZE*8);
-			adr = gd->fb_base+(bit/32)*4+(3-(bit%32)/8);
-			bit_nr = bit%8;
-			bit_nr = (bit_nr>3)?bit_nr-4:bit_nr+4;
-			temp=(*(volatile unsigned char*)(adr));
-			temp |=  (1<<bit_nr);
-			(*(volatile unsigned char*)(adr))=temp;
-		}
-	    }
-	    break;
-	default:
-	    printf ("Warning: unknown display type\n");
-	    break;
-	}
-}
-
-/*
- *create translation table for getting easy the right position in the
- *physical framebuffer for some x/y-coordinates of the VFDs
- */
-void create_vfd_table(void)
-{
-	unsigned long vfd_table[112][18][2][4][2];
-	unsigned int x, y, color, display, entry, pixel;
-	unsigned int x_abcdef = 0;
-
-	switch (gd->vfd_type) {
-	case VFD_TYPE_T119C:
-	    for(y=0; y<=17; y++) {	/* Line */
-		for(x=0; x<=111; x++) {	/* Column */
-		    for(display=0; display <=3; display++) {
-
-			    /* Display 0 blue pixels */
-			    vfd_table[x][y][0][display][0] =
-				(x==0) ? y*16+display
-				       : (x%4)*4+y*16+((x-1)/2)*1024+display;
-			    /* Display 0 red pixels */
-			    vfd_table[x][y][1][display][0] =
-				(x==0) ? y*16+512+display
-				       : (x%4)*4+y*16+((x-1)/2)*1024+512+display;
-		    }
-		}
-	    }
-	    break;
-	case VFD_TYPE_MN11236:
-	    for(y=0; y<=17; y++) {	/* Line */
-		for(x=0; x<=111; x++) {	/* Column */
-		    for(display=0; display <=3; display++) {
-
-			    vfd_table[x][y][0][display][0]=0;
-			    vfd_table[x][y][0][display][1]=0;
-			    vfd_table[x][y][1][display][0]=0;
-			    vfd_table[x][y][1][display][1]=0;
-
-			    switch (x%6) {
-			    case 0: x_abcdef=0; break; /* a -> a */
-			    case 1: x_abcdef=2; break; /* b -> c */
-			    case 2: x_abcdef=4; break; /* c -> e */
-			    case 3: x_abcdef=5; break; /* d -> f */
-			    case 4: x_abcdef=3; break; /* e -> d */
-			    case 5: x_abcdef=1; break; /* f -> b */
-			    }
-
-			    /* blue pixels */
-			    vfd_table[x][y][0][display][0] =
-				(x>1) ? x_abcdef*4+((x-1)/3)*1024+y*48+display
-				      : x_abcdef*4+             0+y*48+display;
-			    /* blue pixels */
-			    if (x>1 && (x-1)%3)
-				    vfd_table[x][y][0][display][1] = x_abcdef*4+((x-1)/3+1)*1024+y*48+display;
-
-			    /* red pixels */
-			    vfd_table[x][y][1][display][0] =
-				(x>1) ? x_abcdef*4+24+((x-1)/3)*1024+y*48+display
-				      : x_abcdef*4+24+             0+y*48+display;
-			    /* red pixels */
-			    if (x>1 && (x-1)%3)
-				    vfd_table[x][y][1][display][1] = x_abcdef*4+24+((x-1)/3+1)*1024+y*48+display;
-		    }
-		}
-	    }
-	    break;
-	default:
-	    /* do nothing */
-	    return;
-	}
-
-	/*
-	 * Create table with entries for physical byte adresses and
-	 * bit-number within the byte
-	 * from table with bit-numbers within the total framebuffer
-	 */
-	for(y=0;y<18;y++) {
-	    for(x=0;x<112;x++) {
-		for(color=0;color<2;color++) {
-		    for(display=0;display<4;display++) {
-			for(entry=0;entry<2;entry++) {
-			    unsigned long adr  = gd->fb_base;
-			    unsigned int bit_nr = 0;
-
-			    pixel  = vfd_table[x][y][color][display][entry] + frame_buf_offs;
-			    /*
-			     * wrap arround if offset
-			     * (see manual S3C2400)
-			     */
-			    if (pixel>=FRAME_BUF_SIZE*8)
-				    pixel = pixel-(FRAME_BUF_SIZE*8);
-			    adr    = gd->fb_base+(pixel/32)*4+(3-(pixel%32)/8);
-			    bit_nr = pixel%8;
-			    bit_nr = (bit_nr>3)?bit_nr-4:bit_nr+4;
-
-			    adr_vfd_table[x][y][color][display][entry] = adr;
-			    bit_vfd_table[x][y][color][display][entry] = bit_nr;
-			}
-		    }
-		}
-	    }
-	}
-}
-
-/*
- * Set/clear pixel of the VFDs
- */
-void set_vfd_pixel(unsigned char x, unsigned char y,
-		   unsigned char color, unsigned char display,
-		   unsigned char value)
-{
-	ulong adr;
-	unsigned char bit_nr, temp;
-
-	if (! gd->vfd_type) {
-		/* Unknown type. */
-		return;
-	}
-
-	/* Pixel-Eintrag Nr. 1 */
-	adr = adr_vfd_table[x][y][color][display][0];
-	/* Pixel-Eintrag Nr. 1 */
-	bit_nr = bit_vfd_table[x][y][color][display][0];
-	temp=(*(volatile unsigned char*)(adr));
-
-	if (value)
-		temp |=  (1<<bit_nr);
-	else
-		temp &= ~(1<<bit_nr);
-
-	(*(volatile unsigned char*)(adr))=temp;
-}
-
-/*
- * transfer image from BMP-File
- */
-void transfer_pic(int display, unsigned char *adr, int height, int width)
-{
-	int x, y;
-	unsigned char temp;
-
-	for (; height > 0; height -= 18)
-	{
-		if (height > 18)
-			y = 18;
-		else
-			y = height;
-		for (; y > 0; y--)
-		{
-			for (x = 0; x < width; x += 2)
-			{
-				temp = *adr++;
-				set_vfd_pixel(x, y-1, 0, display, 0);
-				set_vfd_pixel(x, y-1, 1, display, 0);
-				if ((temp >> 4) == BLAU)
-					set_vfd_pixel(x, y-1, 0, display, 1);
-				else if ((temp >> 4) == ROT)
-					set_vfd_pixel(x, y-1, 1, display, 1);
-				else if ((temp >> 4) == VIOLETT)
-				{
-					set_vfd_pixel(x, y-1, 0, display, 1);
-					set_vfd_pixel(x, y-1, 1, display, 1);
-				}
-				set_vfd_pixel(x+1, y-1, 0, display, 0);
-				set_vfd_pixel(x+1, y-1, 1, display, 0);
-				if ((temp & 0x0F) == BLAU)
-					set_vfd_pixel(x+1, y-1, 0, display, 1);
-				else if ((temp & 0x0F) == ROT)
-					set_vfd_pixel(x+1, y-1, 1, display, 1);
-				else if ((temp & 0x0F) == VIOLETT)
-				{
-					set_vfd_pixel(x+1, y-1, 0, display, 1);
-					set_vfd_pixel(x+1, y-1, 1, display, 1);
-				}
-			}
-		}
-		if (display > 0)
-			display--;
-		else
-			display = 3;
-	}
-}
-
-/*
- * This function initializes VFD clock that is needed for the CPLD that
- * manages the keyboard.
- */
-int vfd_init_clocks (void)
-{
-	int i;
-
-	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
-	struct s3c24x0_timers * const timers = s3c24x0_get_base_timers();
-	struct s3c24x0_lcd * const lcd = s3c24x0_get_base_lcd();
-
-	/* try to determine display type from the value
-	 * defined by pull-ups
-	 */
-	gpio->pcup = (gpio->pcup & 0xFFF0); /* activate  GPC0...GPC3 pullups */
-	gpio->pccon = (gpio->pccon & 0xFFFFFF00); /* cfg GPC0...GPC3 inputs */
-	/* allow signals to settle */
-	for (i=0; i<10000; i++)	/* udelay isn't working yet at this point! */
-		__asm__("NOP");
-	vfd_board_id = (~gpio->pcdat) & 0x000F;	/* read GPC0...GPC3 port pins */
-
-	VFD_DISABLE;				/* activate blank for the vfd */
-
-#define	NEW_CPLD_CLK
-
-#ifdef NEW_CPLD_CLK
-	if (vfd_board_id) {
-		/* If new board revision, then use PWM 3 as cpld-clock */
-		/* Enable 500 Hz timer for fill level sensor to operate properly */
-		/* Configure TOUT3 as functional pin, disable pull-up */
-		gpio->pdcon &= ~0x30000;
-		gpio->pdcon |= 0x20000;
-		gpio->pdup |= (1 << 8);
-
-		/* Configure the prescaler */
-		timers->tcfg0 &= ~0xff00;
-		timers->tcfg0 |= 0x0f00;
-
-		/* Select MUX input (divider) for timer3 (1/16) */
-		timers->tcfg1 &= ~0xf000;
-		timers->tcfg1 |= 0x3000;
-
-		/* Enable autoreload and set the counter and compare
-		 * registers to values for the 500 Hz clock
-		 * (for a given  prescaler (15) and divider (16)):
-		 * counter = (66000000 / 500) >> 9;
-		 */
-		timers->ch[3].tcntb = 0x101;
-		timers->ch[3].tcmpb = 0x101 / 2;
-
-		/* Start timer */
-		timers->tcon = (timers->tcon | UPDATE3 | RELOAD3) & ~INVERT3;
-		timers->tcon = (timers->tcon | START3) & ~UPDATE3;
-	}
-#endif
-	/* If old board revision, then use vm-signal as cpld-clock */
-	lcd->lcdcon2 = 0x00FFC000;
-	lcd->lcdcon3 = 0x0007FF00;
-	lcd->lcdcon4 = 0x00000000;
-	lcd->lcdcon5 = 0x00000400;
-	lcd->lcdcon1 = 0x00000B75;
-	/* VM (GPD1) is used as clock for the CPLD */
-	gpio->pdcon = (gpio->pdcon & 0xFFFFFFF3) | 0x00000008;
-
-	return 0;
-}
-
-/*
- * initialize LCD-Controller of the S3C2400 for using VFDs
- *
- * VFD detection depends on the board revision:
- * starting from Rev. 200 a type code can be read from the data pins,
- * driven by some pull-up resistors; all earlier systems must be
- * manually configured. The type is set in the "vfd_type" environment
- * variable.
- */
-int drv_vfd_init(void)
-{
-	struct s3c24x0_lcd * const lcd = s3c24x0_get_base_lcd();
-	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
-	char *tmp;
-	ulong palette;
-	static int vfd_init_done = 0;
-	int vfd_inv_data = 0;
-
-	if (vfd_init_done != 0)
-		return (0);
-	vfd_init_done = 1;
-
-	debug("Detecting Revison of WA4-VFD: ID=0x%X\n", vfd_board_id);
-
-	switch (vfd_board_id) {
-	case 0:			/* board revision < Rev.200 */
-		if ((tmp = getenv ("vfd_type")) == NULL) {
-			break;
-		}
-		if (strcmp(tmp, "T119C") == 0) {
-			gd->vfd_type = VFD_TYPE_T119C;
-		} else if (strcmp(tmp, "MN11236") == 0) {
-			gd->vfd_type = VFD_TYPE_MN11236;
-		} else {
-			/* cannot use printf for a warning here */
-			gd->vfd_type = 0;	/* unknown */
-		}
-
-		break;
-	default:		/* default to MN11236, data inverted */
-		gd->vfd_type = VFD_TYPE_MN11236;
-		vfd_inv_data = 1;
-		setenv ("vfd_type", "MN11236");
-	}
-	debug ("VFD type: %s%s\n",
-		(gd->vfd_type == VFD_TYPE_T119C)   ? "T119C" :
-		(gd->vfd_type == VFD_TYPE_MN11236) ? "MN11236" :
-		"unknown",
-		vfd_inv_data ? ", inverted data" : "");
-
-	gd->fb_base = gd->fb_base;
-	create_vfd_table();
-	init_grid_ctrl();
-
-	for (palette=0; palette < 16; palette++)
-		(*(volatile unsigned int*)(PALETTE+(palette*4)))=palette;
-	for (palette=16; palette < 256; palette++)
-		(*(volatile unsigned int*)(PALETTE+(palette*4)))=0x00;
-
-	/*
-	 * Hinweis: Der Framebuffer ist um genau ein Nibble verschoben
-	 * Das erste angezeigte Pixel wird aus dem zweiten Nibble geholt
-	 * das letzte angezeigte Pixel wird aus dem ersten Nibble geholt
-	 * (wrap around)
-	 * see manual S3C2400
-	 */
-	/* Stopp LCD-Controller */
-	lcd->lcdcon1 = 0x00000000;
-	/* frame buffer startadr */
-	lcd->lcdsaddr1 = gd->fb_base >> 1;
-	/* frame buffer endadr */
-	lcd->lcdsaddr2 = (gd->fb_base + FRAME_BUF_SIZE) >> 1;
-	lcd->lcdsaddr3 = ((256/4));
-	lcd->lcdcon2 = 0x000DC000;
-	if(gd->vfd_type == VFD_TYPE_MN11236)
-		lcd->lcdcon2 = 37 << 14;	/* MN11236: 38 lines */
-	else
-		lcd->lcdcon2 = 55 << 14;	/* T119C:   56 lines */
-	lcd->lcdcon3 = 0x0051000A;
-	lcd->lcdcon4 = 0x00000001;
-	if (gd->vfd_type && vfd_inv_data)
-		lcd->lcdcon5 = 0x000004C0;
-	else
-		lcd->lcdcon5 = 0x00000440;
-
-	/* Port pins as LCD output */
-	gpio->pccon =   (gpio->pccon & 0xFFFFFF00) | 0x000000AA;
-	gpio->pdcon =   (gpio->pdcon & 0xFFFFFF03) | 0x000000A8;
-
-	/* Synchronize VFD enable with LCD controller to avoid flicker	*/
-	lcd->lcdcon1 = 0x00000B75; /* Start LCD-Controller	*/
-	while ((lcd->lcdcon5 & 0x180000) != 0x100000) /* Wait for VSYNC end */
-		;
-	while ((lcd->lcdcon5 & 0x060000) != 0x040000) /* Wait for next HSYNC */
-		;
-	while ((lcd->lcdcon5 & 0x060000) == 0x040000)
-		;
-	while ((lcd->lcdcon5 & 0x060000) != 0x000000)
-		;
-	if(gd->vfd_type)
-		VFD_ENABLE;
-
-	debug("LCDSADDR1: %lX\n", lcd->lcdsaddr1);
-	debug("LCDSADDR2: %lX\n", lcd->lcdsaddr2);
-	debug("LCDSADDR3: %lX\n", lcd->lcdsaddr3);
-
-	return 0;
-}
-
-/*
- * Disable VFD: should be run before resetting the system:
- * disable VM, enable pull-up
- */
-void disable_vfd (void)
-{
-	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
-
-	VFD_DISABLE;
-	gpio->pdcon &= ~0xC;
-	gpio->pdup  &= ~0x2;
-}
-
-/************************************************************************/
-/* ** ROM capable initialization part - needed to reserve FB memory	*/
-/************************************************************************/
-
-/*
- * This is called early in the system initialization to grab memory
- * for the VFD controller.
- *
- * Note that this is running from ROM, so no write access to global data.
- */
-ulong vfd_setmem (ulong addr)
-{
-	ulong size;
-
-	/* Round up to nearest full page */
-	size = (FRAME_BUF_SIZE + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
-
-	debug ("Reserving %ldk for VFD Framebuffer at: %08lx\n", size>>10, addr);
-
-	return (size);
-}
-
-/*
- * Calculate fb size for VIDEOLFB_ATAG. Size returned contains fb,
- * descriptors and palette areas.
- */
-ulong calc_fbsize (void)
-{
-	return FRAME_BUF_SIZE;
-}
-
-#endif /* CONFIG_VFD */

boards.cfg

@@ -164,12 +164,16 @@ smdkv310		     arm	 armv7	     smdkv310		 samsung	s5pc2xx
 harmony                      arm         armv7       harmony             nvidia         tegra2
 seaboard                     arm         armv7       seaboard            nvidia         tegra2
 u8500_href                   arm         armv7       u8500               st-ericsson    u8500
-actux1                       arm         ixp
+actux1_4_16                  arm         ixp         actux1              -              -           actux1:FLASH2X2
+actux1_8_16                  arm         ixp         actux1              -              -           actux1:FLASH1X8
+actux1_4_32                  arm         ixp         actux1              -              -           actux1:FLASH2X2,RAM_32MB
+actux1_8_32                  arm         ixp         actux1              -              -           actux1:FLASH1X8,RAM_32MB
 actux2                       arm         ixp
 actux3                       arm         ixp
 actux4                       arm         ixp
+dvlhost                      arm         ixp
 ixdp425                      arm         ixp
-ixdpg425                     arm         ixp
+ixdpg425                     arm         ixp         ixdp425
 lpd7a400                     arm         lh7a40x     lpd7a40x
 lpd7a404                     arm         lh7a40x     lpd7a40x
 balloon3                     arm         pxa

common/Makefile

@@ -160,7 +160,6 @@ COBJS-$(CONFIG_USB_STORAGE) += usb_storage.o
 endif
 COBJS-$(CONFIG_CMD_XIMG) += cmd_ximg.o
 COBJS-$(CONFIG_YAFFS2) += cmd_yaffs2.o
-COBJS-$(CONFIG_VFD) += cmd_vfd.o
 
 # others
 COBJS-$(CONFIG_DDR_SPD) += ddr_spd.o

common/cmd_vfd.c

@@ -1,102 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * Command to load a splash screen to the VFDs.
- * NOTE that this will be controlled by a key combination when
- * the keyboard stuff works. For now the user has to enter a
- * bitmap number (only VFD_TEST_LOGO is supported now - 16.10.2002).
- * Added VFD_REMOTE_LOGO (same as VFD_TEST_LOGO but a different color)
- * on 20.10.2002.
- *
- * This rather crudely requires that each bitmap be included as a
- * header file.
- */
-#include <common.h>
-#include <command.h>
-
-#if defined(CONFIG_CMD_VFD)
-
-#include <vfd_logo.h>
-#define VFD_TEST_LOGO_BMPNR 0
-#define VFD_REMOTE_LOGO_BMPNR 1
-
-extern int transfer_pic(unsigned char, unsigned char *, int, int);
-
-int trab_vfd (ulong bitmap);
-
-int do_vfd (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	ulong bitmap;
-
-	if (argc != 2)
-		return cmd_usage(cmdtp);
-
-	if (argv[1][0] == '/') {	/* select bitmap by number */
-		bitmap = simple_strtoul(argv[1]+1, NULL, 10);
-		return (trab_vfd(bitmap));
-	}
-
-	/* display bitmap at given address */
-	bitmap = simple_strtoul(argv[1], NULL, 16);
-	transfer_pic(3, (uchar *)bitmap, VFD_LOGO_HEIGHT, VFD_LOGO_WIDTH);
-	return 0;
-}
-
-U_BOOT_CMD(
-	vfd,	2,	0,	do_vfd,
-	"load a bitmap to the VFDs on TRAB",
-	"/N\n"
-	"    - load bitmap N to the VFDs (N is _decimal_ !!!)\n"
-	"vfd ADDR\n"
-	"    - load bitmap at address ADDR"
-);
-#endif
-
-int trab_vfd (ulong bitmap)
-{
-	uchar *addr;
-	char *s;
-
-	switch (bitmap) {
-	case VFD_TEST_LOGO_BMPNR:
-		if ((s = getenv ("bitmap0")) != NULL) {
-			addr = (uchar *)simple_strtoul (s, NULL, 16);
-		} else {
-			addr = &vfd_test_logo_bitmap[0];
-		}
-		break;
-	case VFD_REMOTE_LOGO_BMPNR:
-		if ((s = getenv ("bitmap1")) != NULL) {
-			addr = (uchar *)simple_strtoul (s, NULL, 16);
-		} else {
-			addr = &vfd_remote_logo_bitmap[0];
-		}
-		break;
-	default:
-		printf("Unknown bitmap %ld\n", bitmap);
-		return 1;
-	}
-	transfer_pic(3, addr, VFD_LOGO_HEIGHT, VFD_LOGO_WIDTH);
-	return 0;
-}

common/main.c

@@ -288,17 +288,6 @@ void main_loop (void)
 	char bcs_set[16];
 #endif /* CONFIG_BOOTCOUNT_LIMIT */
 
-#if defined(CONFIG_VFD) && defined(VFD_TEST_LOGO)
-	ulong bmp = 0;		/* default bitmap */
-	extern int trab_vfd (ulong bitmap);
-
-#ifdef CONFIG_MODEM_SUPPORT
-	if (do_mdm_init)
-		bmp = 1;	/* alternate bitmap */
-#endif
-	trab_vfd (bmp);
-#endif	/* CONFIG_VFD && VFD_TEST_LOGO */
-
 #ifdef CONFIG_BOOTCOUNT_LIMIT
 	bootcount = bootcount_load();
 	bootcount++;

config.mk

@@ -154,36 +154,6 @@ RELFLAGS= $(PLATFORM_RELFLAGS)
 DBGFLAGS= -g # -DDEBUG
 OPTFLAGS= -Os #-fomit-frame-pointer
 
-# If board code explicitly specified LDSCRIPT or CONFIG_SYS_LDSCRIPT, use
-# that (or fail if absent).  Otherwise, search for a linker script in a
-# standard location.
-
-ifndef LDSCRIPT
-	#LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds.debug
-	ifdef CONFIG_SYS_LDSCRIPT
-		# need to strip off double quotes
-		LDSCRIPT := $(subst ",,$(CONFIG_SYS_LDSCRIPT))
-	endif
-endif
-
-ifndef LDSCRIPT
-	ifeq ($(CONFIG_NAND_U_BOOT),y)
-		LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds
-		ifeq ($(wildcard $(LDSCRIPT)),)
-			LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
-		endif
-	endif
-	ifeq ($(wildcard $(LDSCRIPT)),)
-		LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
-	endif
-	ifeq ($(wildcard $(LDSCRIPT)),)
-		LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot.lds
-	endif
-	ifeq ($(wildcard $(LDSCRIPT)),)
-$(error could not find linker script)
-	endif
-endif
-
 OBJCFLAGS += --gap-fill=0xff
 
 gccincdir := $(shell $(CC) -print-file-name=include)

doc/README.scrapyard

@@ -11,11 +11,12 @@ easily if here is something they might want to dig for...
 
 Board	Arch	CPU	removed	    Commit	last known maintainer/contact
 =============================================================================
+trab	arm	S3C2400	-	  2011-05-01	Gary Jennejohn <garyj@denx.de>
 xsengine ARM	PXA2xx	4262a7c   2010-10-20
 wepep250 ARM	PXA2xx	7369478   2010-10-20	Peter Figuli <peposh@etc.sk>
 delta	ARM	PXA2xx	75e2035   2010-10-20
 mp2usb	ARM	AT91RM2900 	ee986e2	2011-01-25	Eric Bénard <eric@eukrea.com>
-barco	powerpc	MPC8245	-	  2010-11-23	Marc Leeman <marc.leeman@barco.com>
+barco	powerpc	MPC8245	afaa27b	  2010-11-23	Marc Leeman <marc.leeman@barco.com>
 ERIC	powerpc	405GP	d9ba451	  2010-11-21	Swen Anderson <sand@peppercon.de>
 VoVPN-GW_100MHz	powerpc	MPC8260 26fe3d2 2010-10-24	Juergen Selent <j.selent@elmeg.de>
 NC650	powerpc	MPC852	333d86d   2010-10-19	Wolfgang Denk <wd@denx.de>

drivers/pci/pci.c

@@ -50,7 +50,6 @@ PCI_HOSE_OP(write, byte, u8)
 PCI_HOSE_OP(write, word, u16)
 PCI_HOSE_OP(write, dword, u32)
 
-#ifndef CONFIG_IXP425
 #define PCI_OP(rw, size, type, error_code)				\
 int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value)	\
 {									\
@@ -71,7 +70,6 @@ PCI_OP(read, dword, u32 *, *value = 0xffffffff)
 PCI_OP(write, byte, u8, )
 PCI_OP(write, word, u16, )
 PCI_OP(write, dword, u32, )
-#endif	/* CONFIG_IXP425 */
 
 #define PCI_READ_VIA_DWORD_OP(size, type, off_mask)			\
 int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
@@ -190,7 +188,6 @@ int pci_last_busno(void)
 	return hose->last_busno;
 }
 
-#ifndef CONFIG_IXP425
 pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
 {
 	struct pci_controller * hose;
@@ -246,7 +243,6 @@ pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
 
 	return (-1);
 }
-#endif	/* CONFIG_IXP425 */
 
 pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index)
 {

drivers/pci/pci_indirect.c

@@ -11,7 +11,7 @@
 
 #include <common.h>
 
-#if (!defined(__I386__) && !defined(CONFIG_IXDP425))
+#if !defined(__I386__)
 
 #include <asm/processor.h>
 #include <asm/io.h>
@@ -20,15 +20,6 @@
 #define cfg_read(val, addr, type, op)	*val = op((type)(addr))
 #define cfg_write(val, addr, type, op)	op((type *)(addr), (val))
 
-#ifdef CONFIG_IXP425
-extern unsigned char	in_8 (volatile unsigned *addr);
-extern unsigned short	in_le16 (volatile unsigned *addr);
-extern unsigned		in_le32 (volatile unsigned *addr);
-extern void		out_8 (volatile unsigned *addr, char val);
-extern void		out_le16 (volatile unsigned *addr, unsigned short val);
-extern void		out_le32 (volatile unsigned *addr, unsigned int val);
-#endif	/* CONFIG_IXP425 */
-
 #if defined(CONFIG_MPC8260)
 #define INDIRECT_PCI_OP(rw, size, type, op, mask)			 \
 static int								 \
@@ -134,4 +125,4 @@ void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data)
 	hose->cfg_data = (unsigned char *) cfg_data;
 }
 
-#endif	/* !__I386__ && !CONFIG_IXDP425 */
+#endif	/* !__I386__ */

drivers/pci/pci_ixp.c

@@ -1,5 +1,8 @@
 /*
  * IXP PCI Init
+ *
+ * (C) Copyright 2011
+ * Michael Schwingen, michael@schwingen.org
  * (C) Copyright 2004 eslab.whut.edu.cn
  * Yue Hu(huyue_whut@yahoo.com.cn), Ligong Xue(lgxue@hotmail.com)
  *
@@ -22,7 +25,6 @@
  * MA 02111-1307 USA
  */
 
-
 #include <common.h>
 #include <asm/processor.h>
 #include <asm/io.h>
@@ -30,542 +32,336 @@
 #include <asm/arch/ixp425.h>
 #include <asm/arch/ixp425pci.h>
 
-static void non_prefetch_read (unsigned int addr, unsigned int cmd,
-			       unsigned int *data);
-static void non_prefetch_write (unsigned int addr, unsigned int cmd,
-				unsigned int data);
-static void configure_pins (void);
-static void sys_pci_gpio_clock_config (void);
-static void pci_bus_scan (void);
-static int pci_device_exists (unsigned int deviceNo);
-static void sys_pci_bar_info_get (unsigned int devnum, unsigned int bus,
-				  unsigned int dev, unsigned int func);
-static void sys_pci_device_bars_write (void);
-static void calc_bars (PciBar * Bars[], unsigned int nBars,
-		       unsigned int startAddr);
+DECLARE_GLOBAL_DATA_PTR;
+
+static void non_prefetch_read(unsigned int addr, unsigned int cmd,
+			      unsigned int *data);
+static void non_prefetch_write(unsigned int addr, unsigned int cmd,
+			       unsigned int data);
+
+/*define the sub vendor and subsystem to be used */
+#define IXP425_PCI_SUB_VENDOR_SYSTEM 0x00000000
 
 #define PCI_MEMORY_BUS		0x00000000
-#define PCI_MEMORY_PHY		0x48000000
+#define PCI_MEMORY_PHY		0x00000000
 #define PCI_MEMORY_SIZE		0x04000000
 
-#define PCI_MEM_BUS		0x40000000
+#define PCI_MEM_BUS		0x48000000
 #define PCI_MEM_PHY		0x00000000
 #define PCI_MEM_SIZE		0x04000000
 
-#define	PCI_IO_BUS		0x40000000
-#define PCI_IO_PHY		0x50000000
-#define PCI_IO_SIZE		0x10000000
+#define	PCI_IO_BUS		0x00000000
+#define PCI_IO_PHY		0x00000000
+#define PCI_IO_SIZE		0x00010000
 
-struct pci_controller hose;
+/* build address value for config sycle */
+static unsigned int pci_config_addr(pci_dev_t bdf, unsigned int reg)
+{
+	unsigned int bus = PCI_BUS(bdf);
+	unsigned int dev = PCI_DEV(bdf);
+	unsigned int func = PCI_FUNC(bdf);
+	unsigned int addr;
 
-unsigned int nDevices;
-unsigned int nMBars;
-unsigned int nIOBars;
-PciBar *memBars[IXP425_PCI_MAX_BAR];
-PciBar *ioBars[IXP425_PCI_MAX_BAR];
-PciDevice devices[IXP425_PCI_MAX_FUNC_ON_BUS];
+	if (bus) { /* secondary bus, use type 1 config cycle */
+		addr = bdf | (reg & ~3) | 1;
+	} else {
+		/*
+		  primary bus, type 0 config cycle. address bits 31:28
+		  specify the device 10:8 specify the function
+		*/
+		addr = BIT((31 - dev)) | (func << 8) | (reg & ~3);
+	}
 
-int pci_read_config_dword (pci_dev_t dev, int where, unsigned int *val)
+	return addr;
+}
+
+static int pci_config_status(void)
+{
+	unsigned int regval;
+
+	regval = readl(PCI_CSR_BASE + PCI_ISR_OFFSET);
+	if ((regval & PCI_ISR_PFE) == 0)
+		return OK;
+
+	/* no device present, make sure that the master abort bit is reset */
+	writel(PCI_ISR_PFE, PCI_CSR_BASE + PCI_ISR_OFFSET);
+	return ERROR;
+}
+
+static int pci_ixp_hose_read_config_dword(struct pci_controller *hose,
+				   pci_dev_t bdf, int where, unsigned int *val)
 {
 	unsigned int retval;
 	unsigned int addr;
+	int stat;
 
-	/*address bits 31:28 specify the device 10:8 specify the function */
+	debug("pci_ixp_hose_read_config_dword: bdf %x, reg %x", bdf, where);
 	/*Set the address to be read */
-	addr = BIT ((31 - dev)) | (where & ~3);
-	non_prefetch_read (addr, NP_CMD_CONFIGREAD, &retval);
-
+	addr = pci_config_addr(bdf, where);
+	non_prefetch_read(addr, NP_CMD_CONFIGREAD, &retval);
 	*val = retval;
 
-	return (OK);
+	stat = pci_config_status();
+	if (stat < 0)
+		*val = -1;
+	debug("-> val %x, status %x\n", *val, stat);
+	return stat;
 }
 
-int pci_read_config_word (pci_dev_t dev, int where, unsigned short *val)
+static int pci_ixp_hose_read_config_word(struct pci_controller *hose,
+				  pci_dev_t bdf, int where, unsigned short *val)
 {
 	unsigned int n;
 	unsigned int retval;
 	unsigned int addr;
 	unsigned int byteEnables;
+	int stat;
 
+	debug("pci_ixp_hose_read_config_word: bdf %x, reg %x", bdf, where);
 	n = where % 4;
 	/*byte enables are 4 bits active low, the position of each
 	   bit maps to the byte that it enables */
 	byteEnables =
-		(~(BIT (n) | BIT ((n + 1)))) &
+		(~(BIT(n) | BIT((n + 1)))) &
 		IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
 	byteEnables = byteEnables << PCI_NP_CBE_BESL;
-	/*address bits 31:28 specify the device 10:8 specify the function */
 	/*Set the address to be read */
-	addr = BIT ((31 - dev)) | (where & ~3);
-	non_prefetch_read (addr, byteEnables | NP_CMD_CONFIGREAD, &retval);
+	addr = pci_config_addr(bdf, where);
+	non_prefetch_read(addr, byteEnables | NP_CMD_CONFIGREAD, &retval);
 
 	/*Pick out the word we are interested in */
-	*val = (retval >> (8 * n));
+	*val = retval >> (8 * n);
 
-	return (OK);
+	stat = pci_config_status();
+	if (stat < 0)
+		*val = -1;
+	debug("-> val %x, status %x\n", *val, stat);
+	return stat;
 }
 
-int pci_read_config_byte (pci_dev_t dev, int where, unsigned char *val)
+static int pci_ixp_hose_read_config_byte(struct pci_controller *hose,
+				  pci_dev_t bdf, int where, unsigned char *val)
 {
 	unsigned int retval;
 	unsigned int n;
 	unsigned int byteEnables;
 	unsigned int addr;
+	int stat;
 
+	debug("pci_ixp_hose_read_config_byte: bdf %x, reg %x", bdf, where);
 	n = where % 4;
 	/*byte enables are 4 bits, active low, the position of each
 	   bit maps to the byte that it enables */
-	byteEnables = (~BIT (n)) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
+	byteEnables = (~BIT(n)) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
 	byteEnables = byteEnables << PCI_NP_CBE_BESL;
 
-	/*address bits 31:28 specify the device, 10:8 specify the function */
 	/*Set the address to be read */
-	addr = BIT ((31 - dev)) | (where & ~3);
-	non_prefetch_read (addr, byteEnables | NP_CMD_CONFIGREAD, &retval);
+	addr = pci_config_addr(bdf, where);
+	non_prefetch_read(addr, byteEnables | NP_CMD_CONFIGREAD, &retval);
 	/*Pick out the byte we are interested in */
-	*val = (retval >> (8 * n));
+	*val = retval >> (8 * n);
 
-	return (OK);
+	stat = pci_config_status();
+	if (stat < 0)
+		*val = -1;
+	debug("-> val %x, status %x\n", *val, stat);
+	return stat;
 }
 
-int pci_write_config_byte (pci_dev_t dev, int where, unsigned char val)
+static int pci_ixp_hose_write_config_byte(struct pci_controller *hose,
+				   pci_dev_t bdf, int where, unsigned char val)
 {
 	unsigned int addr;
 	unsigned int byteEnables;
 	unsigned int n;
 	unsigned int ldata;
+	int stat;
 
+	debug("pci_ixp_hose_write_config_byte: bdf %x, reg %x, val %x",
+	      bdf, where, val);
 	n = where % 4;
 	/*byte enables are 4 bits active low, the position of each
 	   bit maps to the byte that it enables */
-	byteEnables = (~BIT (n)) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
+	byteEnables = (~BIT(n)) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
 	byteEnables = byteEnables << PCI_NP_CBE_BESL;
 	ldata = val << (8 * n);
-	/*address bits 31:28 specify the device 10:8 specify the function */
 	/*Set the address to be written */
-	addr = BIT ((31 - dev)) | (where & ~3);
-	non_prefetch_write (addr, byteEnables | NP_CMD_CONFIGWRITE, ldata);
+	addr = pci_config_addr(bdf, where);
+	non_prefetch_write(addr, byteEnables | NP_CMD_CONFIGWRITE, ldata);
 
-	return (OK);
+	stat = pci_config_status();
+	debug("-> status %x\n", stat);
+	return stat;
 }
 
-int pci_write_config_word (pci_dev_t dev, int where, unsigned short val)
+static int pci_ixp_hose_write_config_word(struct pci_controller *hose,
+				   pci_dev_t bdf, int where, unsigned short val)
 {
 	unsigned int addr;
 	unsigned int byteEnables;
 	unsigned int n;
 	unsigned int ldata;
+	int stat;
 
+	debug("pci_ixp_hose_write_config_word: bdf %x, reg %x, val %x",
+	      bdf, where, val);
 	n = where % 4;
 	/*byte enables are 4 bits active low, the position of each
 	   bit maps to the byte that it enables */
 	byteEnables =
-		(~(BIT (n) | BIT ((n + 1)))) &
+		(~(BIT(n) | BIT((n + 1)))) &
 		IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
 	byteEnables = byteEnables << PCI_NP_CBE_BESL;
 	ldata = val << (8 * n);
-	/*address bits 31:28 specify the device 10:8 specify the function */
 	/*Set the address to be written */
-	addr = BIT (31 - dev) | (where & ~3);
-	non_prefetch_write (addr, byteEnables | NP_CMD_CONFIGWRITE, ldata);
+	addr = pci_config_addr(bdf, where);
+	non_prefetch_write(addr, byteEnables | NP_CMD_CONFIGWRITE, ldata);
 
-	return (OK);
+	stat = pci_config_status();
+	debug("-> status %x\n", stat);
+	return stat;
 }
 
-int pci_write_config_dword (pci_dev_t dev, int where, unsigned int val)
+static int pci_ixp_hose_write_config_dword(struct pci_controller *hose,
+				    pci_dev_t bdf, int where, unsigned int val)
 {
 	unsigned int addr;
+	int stat;
 
-	/*address bits 31:28 specify the device 10:8 specify the function */
+	debug("pci_ixp_hose_write_config_dword: bdf %x, reg %x, val %x",
+	      bdf, where, val);
 	/*Set the address to be written */
-	addr = BIT (31 - dev) | (where & ~3);
-	non_prefetch_write (addr, NP_CMD_CONFIGWRITE, val);
+	addr = pci_config_addr(bdf, where);
+	non_prefetch_write(addr, NP_CMD_CONFIGWRITE, val);
 
-	return (OK);
+	stat = pci_config_status();
+	debug("-> status %x\n", stat);
+	return stat;
 }
 
-void non_prefetch_read (unsigned int addr,
-			unsigned int cmd, unsigned int *data)
+static void non_prefetch_read(unsigned int addr,
+		       unsigned int cmd, unsigned int *data)
 {
-	REG_WRITE (PCI_CSR_BASE, PCI_NP_AD_OFFSET, addr);
+	writel(addr, PCI_CSR_BASE + PCI_NP_AD_OFFSET);
 
 	/*set up and execute the read */
-	REG_WRITE (PCI_CSR_BASE, PCI_NP_CBE_OFFSET, cmd);
+	writel(cmd, PCI_CSR_BASE + PCI_NP_CBE_OFFSET);
 
 	/*The result of the read is now in np_rdata */
-	REG_READ (PCI_CSR_BASE, PCI_NP_RDATA_OFFSET, *data);
+	*data = readl(PCI_CSR_BASE + PCI_NP_RDATA_OFFSET);
 
 	return;
 }
 
-void non_prefetch_write (unsigned int addr,
-			 unsigned int cmd, unsigned int data)
+static void non_prefetch_write(unsigned int addr,
+			unsigned int cmd, unsigned int data)
 {
 
-	REG_WRITE (PCI_CSR_BASE, PCI_NP_AD_OFFSET, addr);
+	writel(addr, PCI_CSR_BASE + PCI_NP_AD_OFFSET);
 	/*set up the write */
-	REG_WRITE (PCI_CSR_BASE, PCI_NP_CBE_OFFSET, cmd);
+	writel(cmd, PCI_CSR_BASE + PCI_NP_CBE_OFFSET);
 	/*Execute the write by writing to NP_WDATA */
-	REG_WRITE (PCI_CSR_BASE, PCI_NP_WDATA_OFFSET, data);
+	writel(data, PCI_CSR_BASE + PCI_NP_WDATA_OFFSET);
 
 	return;
 }
 
-/*
- * PCI controller config registers are accessed through these functions
- * i.e. these allow us to set up our own BARs etc.
- */
-void crp_read (unsigned int offset, unsigned int *data)
+static void crp_write(unsigned int offset, unsigned int data)
 {
-	REG_WRITE (PCI_CSR_BASE, PCI_CRP_AD_CBE_OFFSET, offset);
-	REG_READ (PCI_CSR_BASE, PCI_CRP_RDATA_OFFSET, *data);
+	/*
+	 * The CRP address register bit 16 indicates that we want to do a
+	 * write
+	 */
+	writel(PCI_CRP_WRITE | offset, PCI_CSR_BASE + PCI_CRP_AD_CBE_OFFSET);
+	writel(data, PCI_CSR_BASE + PCI_CRP_WDATA_OFFSET);
 }
 
-void crp_write (unsigned int offset, unsigned int data)
+void pci_ixp_init(struct pci_controller *hose)
 {
-	/*The CRP address register bit 16 indicates that we want to do a write */
-	REG_WRITE (PCI_CSR_BASE, PCI_CRP_AD_CBE_OFFSET,
-		   PCI_CRP_WRITE | offset);
-	REG_WRITE (PCI_CSR_BASE, PCI_CRP_WDATA_OFFSET, data);
-}
+	unsigned int csr;
 
-/*struct pci_controller *hose*/
-void pci_ixp_init (struct pci_controller *hose)
-{
-	unsigned int regval;
+	/*
+	 * Specify that the AHB bus is operating in big endian mode. Set up
+	 * byte lane swapping between little-endian PCI and the big-endian
+	 * AHB bus
+	 */
+#ifdef __ARMEB__
+	csr =  PCI_CSR_ABE | PCI_CSR_PDS | PCI_CSR_ADS;
+#else
+	csr = PCI_CSR_ABE;
+#endif
+	writel(csr, PCI_CSR_BASE + PCI_CSR_OFFSET);
+
+	writel(0, PCI_CSR_BASE + PCI_INTEN_OFFSET);
+
+	/*
+	 * We configure the PCI inbound memory windows to be
+	 * 1:1 mapped to SDRAM
+	 */
+	crp_write(PCI_CFG_BASE_ADDRESS_0, 0x00000000);
+	crp_write(PCI_CFG_BASE_ADDRESS_1, 0x01000000);
+	crp_write(PCI_CFG_BASE_ADDRESS_2, 0x02000000);
+	crp_write(PCI_CFG_BASE_ADDRESS_3, 0x03000000);
+
+	/*
+	 * Enable CSR window at 64 MiB to allow PCI masters
+	 * to continue prefetching past 64 MiB boundary.
+	 */
+	crp_write(PCI_CFG_BASE_ADDRESS_4, 0x04000000);
+	/*
+	 * Enable the IO window to be way up high, at 0xfffffc00
+	 */
+	crp_write(PCI_CFG_BASE_ADDRESS_5, 0xfffffc01);
+
+	/*Setup PCI-AHB and AHB-PCI address mappings */
+	writel(0x00010203, PCI_CSR_BASE + PCI_AHBMEMBASE_OFFSET);
+
+	writel(0x00000000, PCI_CSR_BASE + PCI_AHBIOBASE_OFFSET);
+
+	writel(0x48494a4b, PCI_CSR_BASE + PCI_PCIMEMBASE_OFFSET);
+
+	crp_write(PCI_CFG_SUB_VENDOR_ID, IXP425_PCI_SUB_VENDOR_SYSTEM);
+
+	crp_write(PCI_CFG_COMMAND, PCI_CFG_CMD_MAE | PCI_CFG_CMD_BME);
+	udelay(1000);
+
+	/* clear error bits in status register */
+	writel(PCI_ISR_PSE | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE,
+	       PCI_CSR_BASE + PCI_ISR_OFFSET);
+
+	/*
+	 * Set Initialize Complete in PCI Control Register: allow IXP4XX to
+	 * respond to PCI configuration cycles.
+	 */
+	csr |= PCI_CSR_IC;
+	writel(csr, PCI_CSR_BASE + PCI_CSR_OFFSET);
 
 	hose->first_busno = 0;
-	hose->last_busno = 0x00;
+	hose->last_busno = 0;
 
 	/* System memory space */
-	pci_set_region (hose->regions + 0,
-			PCI_MEMORY_BUS,
-			PCI_MEMORY_PHY, PCI_MEMORY_SIZE, PCI_REGION_SYS_MEMORY);
+	pci_set_region(hose->regions + 0,
+		       PCI_MEMORY_BUS,
+		       PCI_MEMORY_PHY, PCI_MEMORY_SIZE, PCI_REGION_SYS_MEMORY);
 
 	/* PCI memory space */
-	pci_set_region (hose->regions + 1,
-			PCI_MEM_BUS,
-			PCI_MEM_PHY, PCI_MEM_SIZE, PCI_REGION_MEM);
+	pci_set_region(hose->regions + 1,
+		       PCI_MEM_BUS,
+		       PCI_MEM_PHY, PCI_MEM_SIZE, PCI_REGION_MEM);
 	/* PCI I/O space */
-	pci_set_region (hose->regions + 2,
-			PCI_IO_BUS, PCI_IO_PHY, PCI_IO_SIZE, PCI_REGION_IO);
+	pci_set_region(hose->regions + 2,
+		       PCI_IO_BUS, PCI_IO_PHY, PCI_IO_SIZE, PCI_REGION_IO);
 
 	hose->region_count = 3;
 
-	pci_register_hose (hose);
+	pci_set_ops(hose,
+		    pci_ixp_hose_read_config_byte,
+		    pci_ixp_hose_read_config_word,
+		    pci_ixp_hose_read_config_dword,
+		    pci_ixp_hose_write_config_byte,
+		    pci_ixp_hose_write_config_word,
+		    pci_ixp_hose_write_config_dword);
 
-/*
- ==========================================================
-		Init IXP PCI
- ==========================================================
-*/
-	REG_READ (PCI_CSR_BASE, PCI_CSR_OFFSET, regval);
-	regval |= 1 << 2;
-	REG_WRITE (PCI_CSR_BASE, PCI_CSR_OFFSET, regval);
-
-	configure_pins ();
-
-	READ_GPIO_REG (IXP425_GPIO_GPOUTR, regval);
-	WRITE_GPIO_REG (IXP425_GPIO_GPOUTR, regval & (~(1 << 13)));
-	udelay (533);
-	sys_pci_gpio_clock_config ();
-	REG_WRITE (PCI_CSR_BASE, PCI_INTEN_OFFSET, 0);
-	udelay (100);
-	READ_GPIO_REG (IXP425_GPIO_GPOUTR, regval);
-	WRITE_GPIO_REG (IXP425_GPIO_GPOUTR, regval | (1 << 13));
-	udelay (533);
-	crp_write (PCI_CFG_BASE_ADDRESS_0, IXP425_PCI_BAR_0_DEFAULT);
-	crp_write (PCI_CFG_BASE_ADDRESS_1, IXP425_PCI_BAR_1_DEFAULT);
-	crp_write (PCI_CFG_BASE_ADDRESS_2, IXP425_PCI_BAR_2_DEFAULT);
-	crp_write (PCI_CFG_BASE_ADDRESS_3, IXP425_PCI_BAR_3_DEFAULT);
-	crp_write (PCI_CFG_BASE_ADDRESS_4, IXP425_PCI_BAR_4_DEFAULT);
-	crp_write (PCI_CFG_BASE_ADDRESS_5, IXP425_PCI_BAR_5_DEFAULT);
-	/*Setup PCI-AHB and AHB-PCI address mappings */
-	REG_WRITE (PCI_CSR_BASE, PCI_AHBMEMBASE_OFFSET,
-		   IXP425_PCI_AHBMEMBASE_DEFAULT);
-
-	REG_WRITE (PCI_CSR_BASE, PCI_AHBIOBASE_OFFSET,
-		   IXP425_PCI_AHBIOBASE_DEFAULT);
-
-	REG_WRITE (PCI_CSR_BASE, PCI_PCIMEMBASE_OFFSET,
-		   IXP425_PCI_PCIMEMBASE_DEFAULT);
-
-	crp_write (PCI_CFG_SUB_VENDOR_ID, IXP425_PCI_SUB_VENDOR_SYSTEM);
-
-	REG_READ (PCI_CSR_BASE, PCI_CSR_OFFSET, regval);
-	regval |= PCI_CSR_IC | PCI_CSR_ABE | PCI_CSR_PDS;
-	REG_WRITE (PCI_CSR_BASE, PCI_CSR_OFFSET, regval);
-	crp_write (PCI_CFG_COMMAND, PCI_CFG_CMD_MAE | PCI_CFG_CMD_BME);
-	udelay (1000);
-
-	pci_write_config_word (0, PCI_CFG_COMMAND, INITIAL_PCI_CMD);
-	REG_WRITE (PCI_CSR_BASE, PCI_ISR_OFFSET, PCI_ISR_PSE
-		   | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE);
-#ifdef CONFIG_PCI_SCAN_SHOW
-	printf ("Device  bus  dev  func  deviceID  vendorID \n");
-#endif
-	pci_bus_scan ();
-}
-
-void configure_pins (void)
-{
-	unsigned int regval;
-
-	/* Disable clock on GPIO PIN 14 */
-	READ_GPIO_REG (IXP425_GPIO_GPCLKR, regval);
-	WRITE_GPIO_REG (IXP425_GPIO_GPCLKR, regval & (~(1 << 8)));
-	READ_GPIO_REG (IXP425_GPIO_GPCLKR, regval);
-
-	READ_GPIO_REG (IXP425_GPIO_GPOER, regval);
-	WRITE_GPIO_REG (IXP425_GPIO_GPOER,
-			(((~(3 << 13)) & regval) | (0xf << 8)));
-	READ_GPIO_REG (IXP425_GPIO_GPOER, regval);
-
-	READ_GPIO_REG (IXP425_GPIO_GPIT2R, regval);
-	WRITE_GPIO_REG (IXP425_GPIO_GPIT2R,
-			(regval &
-			 ((0x1 << 9) | (0x1 << 6) | (0x1 << 3) | 0x1)));
-	READ_GPIO_REG (IXP425_GPIO_GPIT2R, regval);
-
-	READ_GPIO_REG (IXP425_GPIO_GPISR, regval);
-	WRITE_GPIO_REG (IXP425_GPIO_GPISR, (regval | (0xf << 8)));
-	READ_GPIO_REG (IXP425_GPIO_GPISR, regval);
-}
-
-void sys_pci_gpio_clock_config (void)
-{
-	unsigned int regval;
-
-	READ_GPIO_REG (IXP425_GPIO_GPCLKR, regval);
-	regval |= 0x1 << 4;
-	WRITE_GPIO_REG (IXP425_GPIO_GPCLKR, regval);
-	READ_GPIO_REG (IXP425_GPIO_GPCLKR, regval);
-	regval |= 0x1 << 8;
-	WRITE_GPIO_REG (IXP425_GPIO_GPCLKR, regval);
-}
-
-void pci_bus_scan (void)
-{
-	unsigned int bus = 0, dev, func = 0;
-	unsigned short data16;
-	unsigned int data32;
-	unsigned char intPin;
-
-	/* Assign first device to ourselves */
-	devices[0].bus = 0;
-	devices[0].device = 0;
-	devices[0].func = 0;
-
-	crp_read (PCI_CFG_VENDOR_ID, &data32);
-
-	devices[0].vendor_id = data32 & IXP425_PCI_BOTTOM_WORD_OF_LONG_MASK;
-	devices[0].device_id = data32 >> 16;
-	devices[0].error = FALSE;
-	devices[0].bar[NO_BAR].size = 0;	/*dummy - required */
-
-	nDevices = 1;
-
-	nMBars = 0;
-	nIOBars = 0;
-
-	for (dev = 0; dev < IXP425_PCI_MAX_DEV; dev++) {
-
-		/*Check whether a device is present */
-		if (pci_device_exists (dev) != TRUE) {
-
-			/*Clear error bits in ISR, write 1 to clear */
-			REG_WRITE (PCI_CSR_BASE, PCI_ISR_OFFSET, PCI_ISR_PSE
-				   | PCI_ISR_PFE | PCI_ISR_PPE |
-				   PCI_ISR_AHBE);
-			continue;
-		}
-
-		/*A device is present, add an entry to the array */
-		devices[nDevices].bus = bus;
-		devices[nDevices].device = dev;
-		devices[nDevices].func = func;
-
-		pci_read_config_word (dev, PCI_CFG_VENDOR_ID, &data16);
-
-		devices[nDevices].vendor_id = data16;
-
-		pci_read_config_word (dev, PCI_CFG_DEVICE_ID, &data16);
-		devices[nDevices].device_id = data16;
-
-		/*The device is functioning correctly, set error to FALSE */
-		devices[nDevices].error = FALSE;
-
-		/*Figure out what BARs are on this device */
-		sys_pci_bar_info_get (nDevices, bus, dev, func);
-		/*Figure out what INTX# line the card uses */
-		pci_read_config_byte (dev, PCI_CFG_DEV_INT_PIN, &intPin);
-
-		/*assign the appropriate irq line */
-		if (intPin > PCI_IRQ_LINES) {
-			devices[nDevices].error = TRUE;
-		} else if (intPin != 0) {
-			/*This device uses an interrupt line */
-			/*devices[nDevices].irq = ixp425PciIntTranslate[dev][intPin-1]; */
-			devices[nDevices].irq = intPin;
-		}
-#ifdef CONFIG_PCI_SCAN_SHOW
-		printf ("%06d    %03d %03d %04d  %08d      %08x\n", nDevices,
-			devices[nDevices].vendor_id);
-#endif
-		nDevices++;
-
-	}
-
-	calc_bars (memBars, nMBars, IXP425_PCI_BAR_MEM_BASE);
-	sys_pci_device_bars_write ();
-
-	REG_WRITE (PCI_CSR_BASE, PCI_ISR_OFFSET, PCI_ISR_PSE
-		   | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE);
-}
-
-void sys_pci_bar_info_get (unsigned int devnum,
-			   unsigned int bus,
-			   unsigned int dev, unsigned int func)
-{
-	unsigned int data32;
-	unsigned int tmp;
-	unsigned int size;
-
-	pci_write_config_dword (devnum,
-				PCI_CFG_BASE_ADDRESS_0, IXP425_PCI_BAR_QUERY);
-	pci_read_config_dword (devnum, PCI_CFG_BASE_ADDRESS_0, &data32);
-
-	devices[devnum].bar[0].address = (data32 & 1);
-
-	if (data32 & 1) {
-		/* IO space */
-		tmp = data32 & ~0x3;
-		size = ~(tmp - 1);
-		devices[devnum].bar[0].size = size;
-
-		if (nIOBars < IXP425_PCI_MAX_BAR) {
-			ioBars[nIOBars++] = &devices[devnum].bar[0];
-		}
-	} else {
-		/* Mem space */
-		tmp = data32 & ~IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
-		size = ~(tmp - 1);
-		devices[devnum].bar[0].size = size;
-
-		if (nMBars < IXP425_PCI_MAX_BAR) {
-			memBars[nMBars++] = &devices[devnum].bar[0];
-		} else {
-			devices[devnum].error = TRUE;
-		}
-
-	}
-
-	devices[devnum].bar[1].size = 0;
-}
-
-void sortBars (PciBar * Bars[], unsigned int nBars)
-{
-	unsigned int i, j;
-	PciBar *tmp;
-
-	if (nBars == 0) {
-		return;
-	}
-
-	/* Sort biggest to smallest */
-	for (i = 0; i < nBars - 1; i++) {
-		for (j = i + 1; j < nBars; j++) {
-			if (Bars[j]->size > Bars[i]->size) {
-				/* swap them */
-				tmp = Bars[i];
-				Bars[i] = Bars[j];
-				Bars[j] = tmp;
-			}
-		}
-	}
-}
-
-void calc_bars (PciBar * Bars[], unsigned int nBars, unsigned int startAddr)
-{
-	unsigned int i;
-
-	if (nBars == 0) {
-		return;
-	}
-
-	for (i = 0; i < nBars; i++) {
-		Bars[i]->address |= startAddr;
-		startAddr += Bars[i]->size;
-	}
-}
-
-void sys_pci_device_bars_write (void)
-{
-	unsigned int i;
-	int addr;
-
-	for (i = 1; i < nDevices; i++) {
-		if (devices[i].error) {
-			continue;
-		}
-
-		pci_write_config_dword (devices[i].device,
-					PCI_CFG_BASE_ADDRESS_0,
-					devices[i].bar[0].address);
-		addr = BIT (31 - devices[i].device) |
-			(0 << PCI_NP_AD_FUNCSL) |
-			(PCI_CFG_BASE_ADDRESS_0 & ~3);
-		pci_write_config_dword (devices[i].device,
-					PCI_CFG_DEV_INT_LINE, devices[i].irq);
-
-		pci_write_config_word (devices[i].device,
-				       PCI_CFG_COMMAND, INITIAL_PCI_CMD);
-
-	}
-}
-
-
-int pci_device_exists (unsigned int deviceNo)
-{
-	unsigned int vendorId;
-	unsigned int regval;
-
-	pci_read_config_dword (deviceNo, PCI_CFG_VENDOR_ID, &vendorId);
-
-	/* There are two ways to find out an empty device.
-	 *   1. check Master Abort bit after the access.
-	 *   2. check whether the vendor id read back is 0x0.
-	 */
-	REG_READ (PCI_CSR_BASE, PCI_ISR_OFFSET, regval);
-	if ((vendorId != 0x0) && ((regval & PCI_ISR_PFE) == 0)) {
-		return TRUE;
-	}
-	/*no device present, make sure that the master abort bit is reset */
-
-	REG_WRITE (PCI_CSR_BASE, PCI_ISR_OFFSET, PCI_ISR_PFE);
-	return FALSE;
-}
-
-pci_dev_t pci_find_devices (struct pci_device_id * ids, int devNo)
-{
-	unsigned int i;
-	unsigned int devdidvid;
-	unsigned int didvid;
-	unsigned int vendorId, deviceId;
-
-	vendorId = ids->vendor;
-	deviceId = ids->device;
-	didvid = ((deviceId << 16) & IXP425_PCI_TOP_WORD_OF_LONG_MASK) |
-		(vendorId & IXP425_PCI_BOTTOM_WORD_OF_LONG_MASK);
-
-	for (i = devNo + 1; i < nDevices; i++) {
-
-		pci_read_config_dword (devices[i].device, PCI_CFG_VENDOR_ID,
-				       &devdidvid);
-
-		if (devdidvid == didvid) {
-			return devices[i].device;
-		}
-	}
-	return -1;
+	pci_register_hose(hose);
+	hose->last_busno = pci_hose_scan(hose);
 }

drivers/serial/serial_ixp.c

@@ -30,6 +30,7 @@
 
 #include <common.h>
 #include <asm/arch/ixp425.h>
+#include <watchdog.h>
 
 /*
  *               14.7456 MHz
@@ -85,7 +86,8 @@ int serial_init (void)
 void serial_putc (const char c)
 {
 	/* wait for room in the tx FIFO on UART */
-	while ((LSR(CONFIG_SYS_IXP425_CONSOLE) & LSR_TEMT) == 0);
+	while ((LSR(CONFIG_SYS_IXP425_CONSOLE) & LSR_TEMT) == 0)
+		WATCHDOG_RESET();	/* Reset HW Watchdog, if needed */
 
 	THR(CONFIG_SYS_IXP425_CONSOLE) = c;
 
@@ -111,7 +113,8 @@ int serial_tstc (void)
  */
 int serial_getc (void)
 {
-	while (!(LSR(CONFIG_SYS_IXP425_CONSOLE) & LSR_DR));
+	while (!(LSR(CONFIG_SYS_IXP425_CONSOLE) & LSR_DR))
+		WATCHDOG_RESET();	/* Reset HW Watchdog, if needed */
 
 	return (char) RBR(CONFIG_SYS_IXP425_CONSOLE) & 0xff;
 }

drivers/serial/serial_s3c24x0.c

@@ -27,15 +27,9 @@ DECLARE_GLOBAL_DATA_PTR;
 #define UART_NR	S3C24X0_UART0
 
 #elif defined(CONFIG_SERIAL2)
-# if defined(CONFIG_TRAB)
-#  error "TRAB supports only CONFIG_SERIAL1"
-# endif
 #define UART_NR	S3C24X0_UART1
 
 #elif defined(CONFIG_SERIAL3)
-# if defined(CONFIG_TRAB)
-#  error "TRAB supports only CONFIG_SERIAL1"
-# endif
 #define UART_NR	S3C24X0_UART2
 
 #else

drivers/usb/eth/Makefile

@@ -21,7 +21,7 @@
 
 include $(TOPDIR)/config.mk
 
-LIB	:= $(obj)libusb_eth.a
+LIB	:= $(obj)libusb_eth.o
 
 # new USB host ethernet layer dependencies
 COBJS-$(CONFIG_USB_HOST_ETHER) += usb_ether.o
@@ -36,7 +36,7 @@ OBJS	:= $(addprefix $(obj),$(COBJS))
 all:	$(LIB)
 
 $(LIB):	$(obj).depend $(OBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
 
 #########################################################################
 

drivers/usb/host/ehci-pci.c

@@ -42,7 +42,6 @@ static struct pci_device_id ehci_pci_ids[] = {
 int ehci_hcd_init(void)
 {
 	pci_dev_t pdev;
-	uint32_t addr;
 
 	pdev = pci_find_devices(ehci_pci_ids, CONFIG_PCI_EHCI_DEVICE);
 	if (pdev == -1) {
@@ -50,8 +49,8 @@ int ehci_hcd_init(void)
 		return -1;
 	}
 
-	pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &addr);
-	hccr = (struct ehci_hccr *)addr;
+	hccr = (struct ehci_hccr *)pci_map_bar(pdev,
+			PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
 	hcor = (struct ehci_hcor *)((uint32_t) hccr +
 			HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
 

drivers/usb/musb/musb_hcd.c

@@ -853,8 +853,11 @@ int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
 
 #ifdef MUSB_NO_MULTIPOINT
 	/* Control message is for the HUB? */
-	if (devnum == rh_devnum)
-		return musb_submit_rh_msg(dev, pipe, buffer, len, setup);
+	if (devnum == rh_devnum) {
+		int stat = musb_submit_rh_msg(dev, pipe, buffer, len, setup);
+		if (stat)
+			return stat;
+	}
 #endif
 
 	/* select control endpoint */

include/common.h

@@ -606,9 +606,6 @@ void mii_init (void);
 /* $(CPU)/.../lcd.c */
 ulong	lcd_setmem (ulong);
 
-/* $(CPU)/.../vfd.c */
-ulong	vfd_setmem (ulong);
-
 /* $(CPU)/.../video.c */
 ulong	video_setmem (ulong);
 

include/config_cmd_all.h

@@ -87,7 +87,6 @@
 #define CONFIG_CMD_UNIVERSE	/* Tundra Universe Support	*/
 #define CONFIG_CMD_UNZIP	/* unzip from memory to memory	*/
 #define CONFIG_CMD_USB		/* USB Support			*/
-#define CONFIG_CMD_VFD		/* VFD support (TRAB)		*/
 #define CONFIG_CMD_XIMG		/* Load part of Multi Image	*/
 
 #endif	/* _CONFIG_CMD_ALL_H */

include/configs/actux1.h

@@ -26,13 +26,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-/* 1: modified board with 32MB DRAM */
-#define CONFIG_ACTUX1_32MB		0
-/* 1: 2*2MB FLASH (standard) */
-#define CONFIG_ACTUX1_FLASH2X2		1
-/* 1: 1*8MB FLASH (upgraded boards) */
-#define CONFIG_ACTUX1_FLASH1X8		0
-
 #define CONFIG_IXP425			1
 #define CONFIG_ACTUX1			1
 
@@ -44,12 +37,12 @@
 #define CONFIG_BAUDRATE			115200
 #define CONFIG_BOOTDELAY		3
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_BOARD_EARLY_INIT_F	1
+#define CONFIG_SYS_LDSCRIPT	"board/actux1/u-boot.lds"
 
 /***************************************************************
  * U-boot generic defines start here.
  ***************************************************************/
-#undef CONFIG_USE_IRQ
-
 /*
  * Size of malloc() pool
  */
@@ -62,8 +55,13 @@
 #include <config_cmd_default.h>
 
 #define CONFIG_CMD_ELF
-#undef CONFIG_CMD_PCI
-#undef CONFIG_PCI
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_IXP_PCI
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_CMD_PCI_ENUM
+#endif
 
 #define CONFIG_BOOTCOMMAND		"run boot_flash"
 /* enable passing of ATAGs */
@@ -93,8 +91,9 @@
 #define CONFIG_SYS_MEMTEST_START		0x00400000
 #define CONFIG_SYS_MEMTEST_END			0x00800000
 
-/* spec says 66.666 MHz, but it appears to be 33 */
-#define CONFIG_SYS_HZ				3333333
+/* timer clock - 2* OSC_IN system clock */
+#define CONFIG_IXP425_TIMER_CLK                 66666666
+#define CONFIG_SYS_HZ				1000
 
 /* default load address */
 #define CONFIG_SYS_LOAD_ADDR			0x00010000
@@ -109,10 +108,6 @@
  * The stack sizes are set up in start.S using the settings below
  */
 #define CONFIG_STACKSIZE		(128*1024)	/* regular stack */
-#ifdef CONFIG_USE_IRQ
-# define CONFIG_STACKSIZE_IRQ		(4*1024)	/* IRQ stack */
-# define CONFIG_STACKSIZE_FIQ		(4*1024)	/* FIQ stack */
-#endif
 
 /* Expansion bus settings */
 #define CONFIG_SYS_EXP_CS0			0xbd113842
@@ -120,9 +115,9 @@
 /* SDRAM settings */
 #define CONFIG_NR_DRAM_BANKS		1
 #define PHYS_SDRAM_1			0x00000000
-#define CONFIG_SYS_DRAM_BASE			0x00000000
+#define CONFIG_SYS_SDRAM_BASE			0x00000000
 
-#if CONFIG_ACTUX1_32MB
+#ifdef CONFIG_RAM_32MB
 # define CONFIG_SYS_SDR_CONFIG			0x18
 # define PHYS_SDRAM_1_SIZE		0x02000000
 # define CONFIG_SYS_SDRAM_REFRESH_CNT		0x81a
@@ -137,7 +132,8 @@
 #endif
 
 /* FLASH organization */
-#if CONFIG_ACTUX1_FLASH2X2
+#define CONFIG_SYS_TEXT_BASE		0x50000000
+#ifdef CONFIG_FLASH2X2
 # define CONFIG_SYS_MAX_FLASH_BANKS		2
 /* max number of sectors on one chip */
 # define CONFIG_SYS_MAX_FLASH_SECT		40
@@ -145,7 +141,7 @@
 # define PHYS_FLASH_2			0x50200000
 # define CONFIG_SYS_FLASH_BANKS_LIST		{ PHYS_FLASH_1, PHYS_FLASH_2 }
 #endif
-#if CONFIG_ACTUX1_FLASH1X8
+#ifdef CONFIG_FLASH1X8
 # define CONFIG_SYS_MAX_FLASH_BANKS		1
 /* max number of sectors on one chip */
 # define CONFIG_SYS_MAX_FLASH_SECT		140
@@ -156,6 +152,7 @@
 #define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
 #define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1
 #define CONFIG_SYS_MONITOR_LEN			(256 << 10)
+#define CONFIG_BOARD_SIZE_LIMIT			262144
 
 /* Use common CFI driver */
 #define CONFIG_SYS_FLASH_CFI
@@ -172,12 +169,16 @@
 #define CONFIG_NET_MULTI		1
 /* NPE0 PHY address */
 #define	CONFIG_PHY_ADDR			0
+/* NPE1 PHY address (HW Release E only) */
+#define	CONFIG_PHY1_ADDR		1
 /* MII PHY management */
 #define CONFIG_MII			1
 /* Number of ethernet rx buffers & descriptors */
 #define CONFIG_SYS_RX_ETH_BUFFER		16
 #define CONFIG_RESET_PHY_R		1
 
+#define CONFIG_HAS_ETH1			1
+
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_MII
@@ -202,17 +203,19 @@
 #define CONFIG_ENV_ADDR			(PHYS_FLASH_1 + 0x4000)
 #define CONFIG_SYS_USE_PPCENV			1
 
-#define CONFIG_EXTRA_ENV_SETTINGS \
+#define CONFIG_EXTRA_ENV_SETTINGS					\
 	"npe_ucode=50040000\0"						\
 	"mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \
 	"kerneladdr=50050000\0"						\
+	"kernelfile=actux1/uImage\0"					\
+	"rootfile=actux1/rootfs\0"					\
 	"rootaddr=50170000\0"						\
 	"loadaddr=10000\0"						\
 	"updateboot_ser=mw.b 10000 ff 40000;"				\
 	" loady ${loadaddr};"						\
 	" run eraseboot writeboot\0"					\
 	"updateboot_net=mw.b 10000 ff 40000;"				\
-	" tftp ${loadaddr} u-boot.bin;"					\
+	" tftp ${loadaddr} actux1/u-boot.bin;"				\
 	" run eraseboot writeboot\0"					\
 	"eraseboot=protect off 50000000 50003fff;"			\
 	" protect off 50006000 5003ffff;"				\
@@ -220,8 +223,9 @@
 	" erase 50006000 5003ffff\0"					\
 	"writeboot=cp.b 10000 50000000 4000;"				\
 	" cp.b 16000 50006000 3a000\0"					\
-	"eraseenv=protect off 50004000 50005fff;"			\
-	" erase 50004000 50005fff\0"					\
+	"updateucode=loady;"						\
+	" era ${npe_ucode} +${filesize};"				\
+	" cp.b ${loadaddr} ${npe_ucode} ${filesize}\0"			\
 	"updateroot=tftp ${loadaddr} ${rootfile};"			\
 	" era ${rootaddr} +${filesize};"				\
 	" cp.b ${loadaddr} ${rootaddr} ${filesize}\0"			\
@@ -232,7 +236,7 @@
 	" rootfstype=squashfs,jffs2 init=/etc/preinit\0"		\
 	"netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3"	\
 	" rootfstype=squashfs,jffs2 init=/etc/preinit\0"		\
-	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
+	"addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0" \
 	"addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0"	\
 	"boot_flash=run flashargs addtty addeth;"			\
 	" bootm ${kerneladdr}\0"					\
@@ -240,4 +244,8 @@
 	" tftpboot ${loadaddr} ${kernelfile};"				\
 	" bootm\0"
 
+/* additions for new relocation code, must be added to all boards */
+#define CONFIG_SYS_INIT_SP_ADDR						\
+	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
 #endif /* __CONFIG_H */

include/configs/actux2.h

@@ -37,12 +37,12 @@
 #define CONFIG_BAUDRATE			115200
 #define CONFIG_BOOTDELAY		5
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_BOARD_EARLY_INIT_F	1
+#define CONFIG_SYS_LDSCRIPT	"board/actux2/u-boot.lds"
 
 /***************************************************************
  * U-boot generic defines start here.
  ***************************************************************/
-#undef CONFIG_USE_IRQ
-
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN			(CONFIG_ENV_SIZE + 128*1024)
 
@@ -84,8 +84,9 @@
 #define CONFIG_SYS_MEMTEST_START		0x00400000
 #define CONFIG_SYS_MEMTEST_END			0x00800000
 
-/* spec says 66.666 MHz, but it appears to be 33 */
-#define CONFIG_SYS_HZ				3333333
+/* timer clock - 2* OSC_IN system clock */
+#define CONFIG_IXP425_TIMER_CLK                 66666666
+#define CONFIG_SYS_HZ				1000
 
 /* default load address */
 #define CONFIG_SYS_LOAD_ADDR			0x00010000
@@ -100,10 +101,6 @@
  * The stack sizes are set up in start.S using the settings below
  */
 #define CONFIG_STACKSIZE		(128*1024)	/* regular stack */
-#ifdef CONFIG_USE_IRQ
-# define CONFIG_STACKSIZE_IRQ		(4*1024)	/* IRQ stack */
-# define CONFIG_STACKSIZE_FIQ		(4*1024)	/* FIQ stack */
-#endif
 
 /* Expansion bus settings */
 #define CONFIG_SYS_EXP_CS0			0xbd113042
@@ -111,7 +108,7 @@
 /* SDRAM settings */
 #define CONFIG_NR_DRAM_BANKS		1
 #define PHYS_SDRAM_1			0x00000000
-#define CONFIG_SYS_DRAM_BASE			0x00000000
+#define CONFIG_SYS_SDRAM_BASE			0x00000000
 
 /* 16MB SDRAM */
 #define CONFIG_SYS_SDR_CONFIG			0x3A
@@ -121,6 +118,7 @@
 #define CONFIG_SYS_DRAM_SIZE			0x01000000
 
 /* FLASH organization */
+#define CONFIG_SYS_TEXT_BASE		0x50000000
 #define CONFIG_SYS_MAX_FLASH_BANKS		1
 /* max number of sectors on one chip */
 #define CONFIG_SYS_MAX_FLASH_SECT		140
@@ -130,6 +128,7 @@
 #define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
 #define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1
 #define CONFIG_SYS_MONITOR_LEN			(256 << 10)
+#define CONFIG_BOARD_SIZE_LIMIT			262144
 
 /* Use common CFI driver */
 #define CONFIG_SYS_FLASH_CFI
@@ -149,6 +148,11 @@
 #define	CONFIG_PHY_ADDR			0x00
 /* MII PHY management */
 #define CONFIG_MII			1
+/* fixed-speed switch without standard PHY registers on MII */
+#define CONFIG_MII_NPE0_FIXEDLINK       1
+#define CONFIG_MII_NPE0_SPEED           100
+#define CONFIG_MII_NPE0_FULLDUPLEX      1
+
 /* Number of ethernet rx buffers & descriptors */
 #define CONFIG_SYS_RX_ETH_BUFFER		16
 #define CONFIG_RESET_PHY_R		1
@@ -183,13 +187,15 @@
 	"npe_ucode=50040000\0"						\
 	"mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \
 	"kerneladdr=50050000\0"						\
+	"kernelfile=actux2/uImage\0"					\
+	"rootfile=actux2/rootfs\0"					\
 	"rootaddr=50170000\0"						\
 	"loadaddr=10000\0"						\
 	"updateboot_ser=mw.b 10000 ff 40000;"				\
 	" loady ${loadaddr};"						\
 	" run eraseboot writeboot\0"					\
 	"updateboot_net=mw.b 10000 ff 40000;"				\
-	" tftp ${loadaddr} u-boot.bin;"					\
+	" tftp ${loadaddr} actux2/u-boot.bin;"				\
 	" run eraseboot writeboot\0"					\
 	"eraseboot=protect off 50000000 50003fff;"			\
 	" protect off 50006000 5003ffff;"				\
@@ -197,8 +203,9 @@
 	" erase 50006000 5003ffff\0"					\
 	"writeboot=cp.b 10000 50000000 4000;"				\
 	" cp.b 16000 50006000 3a000\0"					\
-	"eraseenv=protect off 50004000 50005fff;"			\
-	" erase 50004000 50005fff\0"					\
+	"updateucode=loady;"						\
+	" era ${npe_ucode} +${filesize};"				\
+	" cp.b ${loadaddr} ${npe_ucode} ${filesize}\0"			\
 	"updateroot=tftp ${loadaddr} ${rootfile};"			\
 	" era ${rootaddr} +${filesize};"				\
 	" cp.b ${loadaddr} ${rootaddr} ${filesize}\0"			\
@@ -217,4 +224,8 @@
 	" tftpboot ${loadaddr} ${kernelfile};"				\
 	" bootm\0"
 
+/* additions for new relocation code, must be added to all boards */
+#define CONFIG_SYS_INIT_SP_ADDR						\
+	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
 #endif /* __CONFIG_H */

include/configs/actux3.h

@@ -37,12 +37,12 @@
 #define CONFIG_BAUDRATE			115200
 #define CONFIG_BOOTDELAY		3
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_BOARD_EARLY_INIT_F	1
+#define CONFIG_SYS_LDSCRIPT	"board/actux3/u-boot.lds"
 
 /***************************************************************
  * U-boot generic defines start here.
  ***************************************************************/
-#undef CONFIG_USE_IRQ
-
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN			(CONFIG_ENV_SIZE + 128*1024)
 
@@ -82,8 +82,9 @@
 #define CONFIG_SYS_MEMTEST_START		0x00400000
 #define CONFIG_SYS_MEMTEST_END			0x00800000
 
-/* spec says 66.666 MHz, but it appears to be 33 */
-#define CONFIG_SYS_HZ				3333333
+/* timer clock - 2* OSC_IN system clock */
+#define CONFIG_IXP425_TIMER_CLK                 66666666
+#define CONFIG_SYS_HZ				1000
 
 /* default load address */
 #define CONFIG_SYS_LOAD_ADDR			0x00010000
@@ -99,10 +100,6 @@
  * The stack sizes are set up in start.S using the settings below
  */
 #define CONFIG_STACKSIZE		(128*1024)	/* regular stack */
-#ifdef CONFIG_USE_IRQ
-# define CONFIG_STACKSIZE_IRQ		(4*1024)	/* IRQ stack */
-# define CONFIG_STACKSIZE_FIQ		(4*1024)	/* FIQ stack */
-#endif
 
 /* Expansion bus settings */
 #define CONFIG_SYS_EXP_CS0			0xbd113442
@@ -110,7 +107,7 @@
 /* SDRAM settings */
 #define CONFIG_NR_DRAM_BANKS		1
 #define PHYS_SDRAM_1			0x00000000
-#define CONFIG_SYS_DRAM_BASE			0x00000000
+#define CONFIG_SYS_SDRAM_BASE			0x00000000
 
 /* 16MB SDRAM */
 #define CONFIG_SYS_SDR_CONFIG			0x3A
@@ -120,6 +117,7 @@
 #define CONFIG_SYS_DRAM_SIZE			0x01000000
 
 /* FLASH organization */
+#define CONFIG_SYS_TEXT_BASE		0x50000000
 #define CONFIG_SYS_MAX_FLASH_BANKS		1
 /* max number of sectors on one chip */
 #define CONFIG_SYS_MAX_FLASH_SECT		140
@@ -129,6 +127,7 @@
 #define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
 #define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1
 #define CONFIG_SYS_MONITOR_LEN			(256 << 10)
+#define CONFIG_BOARD_SIZE_LIMIT			262144
 
 /* Use common CFI driver */
 #define CONFIG_SYS_FLASH_CFI
@@ -149,6 +148,11 @@
 #define	CONFIG_PHY_ADDR			0x10
 /* MII PHY management */
 #define CONFIG_MII			1
+/* fixed-speed switch without standard PHY registers on MII */
+#define CONFIG_MII_NPE0_FIXEDLINK       1
+#define CONFIG_MII_NPE0_SPEED           100
+#define CONFIG_MII_NPE0_FULLDUPLEX      1
+
 /* Number of ethernet rx buffers & descriptors */
 #define CONFIG_SYS_RX_ETH_BUFFER		16
 #define CONFIG_RESET_PHY_R		1
@@ -183,13 +187,15 @@
 	"npe_ucode=50040000\0"						\
 	"mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \
 	"kerneladdr=50050000\0"						\
+	"kernelfile=actux3/uImage\0"					\
+	"rootfile=actux3/rootfs\0"					\
 	"rootaddr=50170000\0"						\
 	"loadaddr=10000\0"						\
 	"updateboot_ser=mw.b 10000 ff 40000;"				\
 	" loady ${loadaddr};"						\
 	" run eraseboot writeboot\0"					\
 	"updateboot_net=mw.b 10000 ff 40000;"				\
-	" tftp ${loadaddr} u-boot.bin;"					\
+	" tftp ${loadaddr} actux3/u-boot.bin;"				\
 	" run eraseboot writeboot\0"					\
 	"eraseboot=protect off 50000000 50003fff;"			\
 	" protect off 50006000 5003ffff;"				\
@@ -197,8 +203,9 @@
 	" erase 50006000 5003ffff\0"					\
 	"writeboot=cp.b 10000 50000000 4000;"				\
 	" cp.b 16000 50006000 3a000\0"					\
-	"eraseenv=protect off 50004000 50005fff;"			\
-	" erase 50004000 50005fff\0"					\
+	"updateucode=loady;"						\
+	" era ${npe_ucode} +${filesize};"				\
+	" cp.b ${loadaddr} ${npe_ucode} ${filesize}\0"			\
 	"updateroot=tftp ${loadaddr} ${rootfile};"			\
 	" era ${rootaddr} +${filesize};"				\
 	" cp.b ${loadaddr} ${rootaddr} ${filesize}\0"			\
@@ -209,7 +216,7 @@
 	" rootfstype=squashfs,jffs2 init=/etc/preinit\0"		\
 	"netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3"	\
 	" rootfstype=squashfs,jffs2 init=/etc/preinit\0"		\
-	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
+	"addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0" \
 	"addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0"	\
 	"boot_flash=run flashargs addtty addeth;"			\
 	" bootm ${kerneladdr}\0"					\
@@ -217,4 +224,8 @@
 	" tftpboot ${loadaddr} ${kernelfile};"				\
 	" bootm\0"
 
+/* additions for new relocation code, must be added to all boards */
+#define CONFIG_SYS_INIT_SP_ADDR						\
+	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
 #endif /* __CONFIG_H */

include/configs/actux4.h

@@ -37,12 +37,11 @@
 #define CONFIG_BAUDRATE			115200
 #define CONFIG_BOOTDELAY		3
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_BOARD_EARLY_INIT_F	1
 
 /***************************************************************
  * U-boot generic defines start here.
  ***************************************************************/
-#undef CONFIG_USE_IRQ
-
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN			(CONFIG_ENV_SIZE + 128*1024)
 
@@ -54,6 +53,15 @@
 
 #define CONFIG_CMD_ELF
 
+#define CONFIG_PCI
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_IXP_PCI
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_CMD_PCI_ENUM
+#endif
+
 #define CONFIG_BOOTCOMMAND		"run boot_flash"
 /* enable passing of ATAGs */
 #define CONFIG_CMDLINE_TAG		1
@@ -81,8 +89,9 @@
 #define CONFIG_SYS_MEMTEST_START		0x00400000
 #define CONFIG_SYS_MEMTEST_END			0x00800000
 
-/* spec says 66.666 MHz, but it appears to be 33 */
-#define CONFIG_SYS_HZ				3333333
+/* timer clock - 2* OSC_IN system clock */
+#define CONFIG_IXP425_TIMER_CLK                 66000000
+#define CONFIG_SYS_HZ				1000
 
 /* default load address */
 #define CONFIG_SYS_LOAD_ADDR			0x00010000
@@ -97,10 +106,6 @@
  * The stack sizes are set up in start.S using the settings below
  */
 #define CONFIG_STACKSIZE		(128*1024)	/* regular stack */
-#ifdef CONFIG_USE_IRQ
-# define CONFIG_STACKSIZE_IRQ		(4*1024)	/* IRQ stack */
-# define CONFIG_STACKSIZE_FIQ		(4*1024)	/* FIQ stack */
-#endif
 
 /* Expansion bus settings */
 #define CONFIG_SYS_EXP_CS0			0xbd113003
@@ -108,7 +113,7 @@
 /* SDRAM settings */
 #define CONFIG_NR_DRAM_BANKS		1
 #define PHYS_SDRAM_1			0x00000000
-#define CONFIG_SYS_DRAM_BASE			0x00000000
+#define CONFIG_SYS_SDRAM_BASE			0x00000000
 
 /* 32MB SDRAM */
 #define CONFIG_SYS_SDR_CONFIG			0x18
@@ -118,6 +123,7 @@
 #define CONFIG_SYS_DRAM_SIZE			0x02000000
 
 /* FLASH organization */
+#define CONFIG_SYS_TEXT_BASE		0x50000000
 #define CONFIG_SYS_MAX_FLASH_BANKS		2
 /* max # of sectors per chip */
 #define CONFIG_SYS_MAX_FLASH_SECT		70
@@ -128,6 +134,7 @@
 #define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
 #define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1
 #define CONFIG_SYS_MONITOR_LEN			(252 << 10)
+#define CONFIG_BOARD_SIZE_LIMIT			258048
 
 /* Use common CFI driver */
 #define CONFIG_SYS_FLASH_CFI
@@ -152,6 +159,7 @@
 #define	CONFIG_PHY_ADDR			0x1C
 /* MII PHY management */
 #define CONFIG_MII			1
+
 /* Number of ethernet rx buffers & descriptors */
 #define CONFIG_SYS_RX_ETH_BUFFER		16
 
@@ -180,19 +188,22 @@
 	"mtd=IXP4XX-Flash.0:252k(uboot),4k(uboot_env);"			\
 	"IXP4XX-Flash.1:128k(ucode),1280k(linux),-(root)\0"		\
 	"kerneladdr=51020000\0"						\
+	"kernelfile=actux4/uImage\0"					\
+	"rootfile=actux4/rootfs\0"					\
 	"rootaddr=51160000\0"						\
 	"loadaddr=10000\0"						\
 	"updateboot_ser=mw.b 10000 ff 40000;"				\
 	" loady ${loadaddr};"						\
 	" run eraseboot writeboot\0"					\
 	"updateboot_net=mw.b 10000 ff 40000;"				\
-	" tftp ${loadaddr} u-boot.bin;"					\
+	" tftp ${loadaddr} actux4/u-boot.bin;"					\
 	" run eraseboot writeboot\0"					\
 	"eraseboot=protect off 50000000 5003efff;"			\
 	" erase 50000000 +${filesize}\0"				\
 	"writeboot=cp.b 10000 50000000 ${filesize}\0"			\
-	"eraseenv=protect off 5003f000 5003ffff;"			\
-	" erase 5003f000 5003ffff\0"					\
+	"updateucode=loady;"						\
+	" era ${npe_ucode} +${filesize};"				\
+	" cp.b ${loadaddr} ${npe_ucode} ${filesize}\0"			\
 	"updateroot=tftp ${loadaddr} ${rootfile};"			\
 	" era ${rootaddr} +${filesize};"				\
 	" cp.b ${loadaddr} ${rootaddr} ${filesize}\0"			\
@@ -211,4 +222,8 @@
 	" tftpboot ${loadaddr} ${kernelfile};"				\
 	" bootm\0"
 
+/* additions for new relocation code, must be added to all boards */
+#define CONFIG_SYS_INIT_SP_ADDR						\
+	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
 #endif /* __CONFIG_H */

include/configs/dvlhost.h

@@ -0,0 +1,248 @@
+/*
+ * (C) Copyright 2009
+ * Michael Schwingen, michael@schwingen.org
+ *
+ * Configuration settings for the
+ * dLAN200 AV Wireless G ("dvlhost") board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_IXP425			1
+#define CONFIG_DVLHOST			1
+
+#define CONFIG_DISPLAY_CPUINFO		1
+#define CONFIG_DISPLAY_BOARDINFO	1
+
+#define CONFIG_IXP_SERIAL
+#define CONFIG_SYS_IXP425_CONSOLE	IXP425_UART2
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_BOOTDELAY		3
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_BOARD_EARLY_INIT_F	1
+#define CONFIG_SYS_LDSCRIPT	"board/dvlhost/u-boot.lds"
+
+/***************************************************************
+ * U-boot generic defines start here.
+ ***************************************************************/
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN			(CONFIG_ENV_SIZE + 128*1024)
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Command line configuration. */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ELF
+#define CONFIG_PCI
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_IXP_PCI
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_CMD_PCI_ENUM
+#endif
+
+#define CONFIG_BOOTCOMMAND		"run boot_flash"
+/* enable passing of ATAGs */
+#define CONFIG_CMDLINE_TAG		1
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+
+#if defined(CONFIG_CMD_KGDB)
+# define CONFIG_KGDB_BAUDRATE		230400
+/* which serial port to use */
+# define CONFIG_KGDB_SER_INDEX		1
+#endif
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT		"=> "
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		256
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS		16
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START	0x00000000
+#define CONFIG_SYS_MEMTEST_END		0x01D80000
+
+/* timer clock - 2* OSC_IN system clock */
+#define CONFIG_IXP425_TIMER_CLK         66666666
+#define CONFIG_SYS_HZ			1000
+
+/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x00010000
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, \
+					  115200, 230400 }
+#define CONFIG_SERIAL_RTS_ACTIVE	1
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE		(128*1024)	/* regular stack */
+
+/* Expansion bus settings */
+#define CONFIG_SYS_EXP_CS0		0xbd113442
+
+/* SDRAM settings */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM_1			0x00000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+
+/* 32MB SDRAM: 2* 8Mx16, CL3 */
+#define CONFIG_SYS_SDR_CONFIG		0x18
+#define PHYS_SDRAM_1_SIZE		0x02000000
+#define CONFIG_SYS_SDRAM_REFRESH_CNT	0x800
+#define CONFIG_SYS_SDR_MODE_CONFIG	0x1
+#define CONFIG_SYS_DRAM_SIZE		PHYS_SDRAM_1_SIZE
+
+/* FLASH organization: one Spansion S29AL032D-04 Flash */
+#define CONFIG_SYS_TEXT_BASE		0x50000000
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_SECT	140
+#define PHYS_FLASH_1			0x50000000
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ PHYS_FLASH_1 }
+
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)
+#define CONFIG_BOARD_SIZE_LIMIT         262144
+
+/* Use common CFI driver */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+/* no byte writes on IXP4xx */
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+
+/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+/* Ethernet */
+
+/* include IXP4xx NPE support */
+#define CONFIG_IXP4XX_NPE		1
+
+#define CONFIG_NET_MULTI		1
+/* NPE0 PHY: MII dLAN200 AVmodule, 100BaseT-FDX fixed */
+#define	CONFIG_PHY_ADDR			0x18
+/* NPE1 PHY: MII IP175 switch, port 5 is host port */
+#define	CONFIG_PHY1_ADDR		0x05
+/* MII PHY management */
+#define CONFIG_MII			1
+/* fixed-speed powerline modem without standard PHY registers on MII */
+#define CONFIG_MII_NPE0_FIXEDLINK       1
+#define CONFIG_MII_NPE0_SPEED           100
+#define CONFIG_MII_NPE0_FULLDUPLEX      1
+/* fixed-speed switch without standard PHY registers on MII */
+#define CONFIG_MII_NPE1_FIXEDLINK       1
+#define CONFIG_MII_NPE1_SPEED           100
+#define CONFIG_MII_NPE1_FULLDUPLEX      1
+
+/* Number of ethernet rx buffers & descriptors */
+#define CONFIG_SYS_RX_ETH_BUFFER	16
+#define CONFIG_RESET_PHY_R		1
+/* ethernet switch connected to MII port */
+#define CONFIG_MII_ETHSWITCH		1
+#define CONFIG_HAS_ETH1			1
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#undef  CONFIG_CMD_NFS
+
+/* BOOTP options */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/* Cache Configuration */
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
+/*
+ * environment organization:
+ * one flash sector, embedded in uboot area (bottom bootblock flash)
+ */
+#define	CONFIG_ENV_IS_IN_FLASH		1
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_ADDR			(PHYS_FLASH_1 + 0x4000)
+#define CONFIG_SYS_USE_PPCENV		1
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"npe_ucode=50040000\0"						\
+	"ethprime=NPE1\0"						\
+	"ethrotate=no\0"						\
+	"mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root),\0" \
+	"kerneladdr=50050000\0"						\
+	"kernelfile=dvlhost/uImage\0"					\
+	"rootfile=dvlhost/rootfs\0"					\
+	"rootaddr=50170000\0"						\
+	"loadaddr=10000\0"						\
+	"updateboot_ser=mw.b 10000 ff 40000;"				\
+	" loady ${loadaddr};"						\
+	" run eraseboot writeboot\0"					\
+	"updateboot_net=mw.b 10000 ff 40000;"				\
+	" tftp ${loadaddr} dvlhost/u-boot.bin;"				\
+	" run eraseboot writeboot\0"					\
+	"eraseboot=protect off 50000000 50003fff;"			\
+	" protect off 50006000 5003ffff;"				\
+	" erase 50000000 50003fff;"					\
+	" erase 50006000 5003ffff\0"					\
+	"writeboot=cp.b 10000 50000000 4000;"				\
+	" cp.b 16000 50006000 3a000\0"					\
+	"updateucode=loady;"						\
+	" era ${npe_ucode} +${filesize};"				\
+	" cp.b ${loadaddr} ${npe_ucode} ${filesize}\0"			\
+	"updateroot=tftp ${loadaddr} ${rootfile};"			\
+	" era ${rootaddr} +${filesize};"				\
+	" cp.b ${loadaddr} ${rootaddr} ${filesize}\0"			\
+	"updatekern=tftp ${loadaddr} ${kernelfile};"			\
+	" era ${kerneladdr} +${filesize};"				\
+	" cp.b ${loadaddr} ${kerneladdr} ${filesize}\0"			\
+	"flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3"	\
+	" rootfstype=squashfs,jffs2 init=/etc/preinit\0"		\
+	"netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3"	\
+	" rootfstype=squashfs,jffs2 init=/etc/preinit\0"		\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
+	"addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0"	\
+	"boot_flash=run flashargs addtty addeth;"			\
+	" bootm ${kerneladdr}\0"					\
+	"boot_net=run netargs addtty addeth;"				\
+	" tftpboot ${loadaddr} ${kernelfile};"				\
+	" bootm\0"
+
+/* additions for new relocation code, must be added to all boards */
+#define CONFIG_SYS_INIT_SP_ADDR						\
+	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
+#endif /* __CONFIG_H */

include/configs/ixdp425.h

@@ -36,12 +36,19 @@
 #define CONFIG_DISPLAY_CPUINFO	1	/* display cpu info (and speed)	*/
 #define CONFIG_DISPLAY_BOARDINFO 1	/* display board info		*/
 
+/*
+ * select serial console configuration
+ */
+#define CONFIG_IXP_SERIAL
+#define CONFIG_SYS_IXP425_CONSOLE	IXP425_UART1
+#define CONFIG_BAUDRATE         115200
+
+#define CONFIG_BOARD_EARLY_INIT_F	1
+
 /***************************************************************
  * U-boot generic defines start here.
  ***************************************************************/
 
-#undef CONFIG_USE_IRQ                   /* we don't need IRQ/FIQ stuff */
-
 /*
  * Size of malloc() pool
  */
@@ -50,9 +57,6 @@
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 
-#define CONFIG_BAUDRATE         115200
-
-
 /*
  * BOOTP options
  */
@@ -61,38 +65,33 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-
-/*
- * Command line configuration.
- */
+/* Command line configuration. */
 #include <config_cmd_default.h>
 
 #define CONFIG_CMD_ELF
-#define CONFIG_CMD_PCI
-
 
 #define CONFIG_PCI
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_PCI
+#define CONFIG_PCI_PNP
 #define CONFIG_IXP_PCI
-#define CONFIG_NET_MULTI
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_CMD_PCI_ENUM
 #define CONFIG_EEPRO100
+#endif
 
-#define CONFIG_BOOTDELAY        3
-/*#define CONFIG_ETHADDR          08:00:3e:26:0a:5b*/
-#define CONFIG_NETMASK          255.255.255.0
-#define CONFIG_IPADDR           192.168.0.21
-#define CONFIG_SERVERIP         192.168.0.148
-#define CONFIG_BOOTCOMMAND      "bootm 50040000"
-#define CONFIG_BOOTARGS         "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
-#define CONFIG_CMDLINE_TAG
+#define CONFIG_BOOTCOMMAND		"run boot_flash"
+/* enable passing of ATAGs */
+#define CONFIG_CMDLINE_TAG		1
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE    230400          /* speed to run kgdb serial port */
 #define CONFIG_KGDB_SER_INDEX   2               /* which serial port to use */
 #endif
 
-/*
- * Miscellaneous configurable options
- */
+/* Miscellaneous configurable options */
 #define CONFIG_SYS_LONGHELP                            /* undef to save memory         */
 #define CONFIG_SYS_PROMPT              "=> "   /* Monitor Command Prompt       */
 #define CONFIG_SYS_CBSIZE              256             /* Console I/O Buffer Size      */
@@ -103,10 +102,13 @@
 #define CONFIG_SYS_MEMTEST_START       0x00400000      /* memtest works on     */
 #define CONFIG_SYS_MEMTEST_END         0x00800000      /* 4 ... 8 MB in DRAM   */
 
-#define CONFIG_SYS_LOAD_ADDR           0x00010000      /* default load address */
+/* timer clock - 2* OSC_IN system clock */
+#define CONFIG_IXP425_TIMER_CLK                 66666666
+#define CONFIG_SYS_HZ				1000
+
+/* default load address */
+#define CONFIG_SYS_LOAD_ADDR			0x00010000
 
-#define CONFIG_SYS_HZ                  3333333         /* spec says 66.666 MHz, but it appears to be 33 */
-						/* valid baudrates */
 #define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 
 /*
@@ -115,10 +117,6 @@
  * The stack sizes are set up in start.S using the settings below
  */
 #define CONFIG_STACKSIZE        (128*1024)      /* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ    (4*1024)        /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ    (4*1024)        /* FIQ stack */
-#endif
 
 /***************************************************************
  * Platform/Board specific defines start here.
@@ -128,72 +126,143 @@
  * Hardware drivers
  */
 
-
-/*
- * select serial console configuration
- */
-#define CONFIG_IXP_SERIAL
-#define CONFIG_SYS_IXP425_CONSOLE	IXP425_UART1   /* we use UART1 for console */
-
 /*
  * Physical Memory Map
  */
-#define CONFIG_NR_DRAM_BANKS    1          /* we have 2 banks of DRAM */
-#define PHYS_SDRAM_1            0x00000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE       0x01000000 /* 16 MB */
+#define CONFIG_SYS_TEXT_BASE	0x50000000
 
 #define PHYS_FLASH_1            0x50000000 /* Flash Bank #1 */
 #define PHYS_FLASH_SIZE         0x00800000 /* 8 MB */
 #define PHYS_FLASH_BANK_SIZE    0x00800000 /* 8 MB Banks */
 #define PHYS_FLASH_SECT_SIZE    0x00020000 /* 128 KB sectors (x1) */
 
-#define CONFIG_SYS_DRAM_BASE           0x00000000
-#define CONFIG_SYS_DRAM_SIZE           0x01000000
-
 #define CONFIG_SYS_FLASH_BASE          PHYS_FLASH_1
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_BOARD_SIZE_LIMIT		262144
 
-/*
- * Expansion bus settings
- */
-#define CONFIG_SYS_EXP_CS0				0xbcd23c42
+/* Expansion bus settings */
+#define CONFIG_SYS_EXP_CS0	0xbcd23c42
+
+/* SDRAM settings */
+#define CONFIG_NR_DRAM_BANKS    1          /* we have 2 banks of DRAM */
+#define PHYS_SDRAM_1            0x00000000 /* SDRAM Bank #1 */
+#define CONFIG_SYS_SDRAM_BASE	0x00000000
 
-/*
- * SDRAM settings
- */
 #define CONFIG_SYS_SDR_CONFIG		0xd
 #define CONFIG_SYS_SDR_MODE_CONFIG	0x1
 #define CONFIG_SYS_SDRAM_REFRESH_CNT	0x81a
 
-/*
- * GPIO settings
- */
-
-/*
- * FLASH and environment organization
- */
 /*
  * FLASH and environment organization
  */
 #define CONFIG_SYS_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 #define CONFIG_SYS_MAX_FLASH_SECT      128	/* max number of sectors on one chip    */
 
-#define CONFIG_SYS_FLASH_CFI				/* The flash is CFI compatible	*/
-#define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/
 #define	CONFIG_ENV_IS_IN_FLASH	1
 
 #define CONFIG_SYS_FLASH_BANKS_LIST	{ PHYS_FLASH_1 }
 
-#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT	/* no byte writes on IXP4xx	*/
-
 #define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-
 #define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector	*/
-#define CONFIG_ENV_ADDR		(PHYS_FLASH_1 + 0x20000)
+#define CONFIG_ENV_ADDR		(PHYS_FLASH_1 + 0x40000)
 #define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
 
+/* Use common CFI driver */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+/* no byte writes on IXP4xx */
+#define CONFIG_SYS_FLASH_CFI_WIDTH		FLASH_CFI_16BIT
+/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+/* Ethernet */
+
+/* include IXP4xx NPE support */
+#define CONFIG_IXP4XX_NPE		1
+#define CONFIG_NET_MULTI		1
+/* NPE0 PHY address */
+#define	CONFIG_PHY_ADDR			0
+/* NPE1 PHY address (HW Release E only) */
+#define	CONFIG_PHY1_ADDR		1
+/* MII PHY management */
+#define CONFIG_MII			1
+/* Number of ethernet rx buffers & descriptors */
+#define CONFIG_SYS_RX_ETH_BUFFER		16
+
+#define CONFIG_HAS_ETH1			1
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#undef  CONFIG_CMD_NFS
+
+/* Cache Configuration */
+#define CONFIG_SYS_CACHELINE_SIZE		32
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"npe_ucode=50060000\0"						\
+	"mtd=IXP4XX-Flash.0:256k(uboot),128k(env),128k(ucode),2048k(linux),-(root)\0" \
+	"kerneladdr=50080000\0"						\
+	"kernelfile=ixdp425/uImage\0"					\
+	"rootfile=ixdp425/rootfs\0"					\
+	"rootaddr=50280000\0"						\
+	"loadaddr=10000\0"						\
+	"updateboot_ser=mw.b 10000 ff 40000;"				\
+	" loady ${loadaddr};"						\
+	" run eraseboot writeboot\0"					\
+	"updateboot_net=mw.b 10000 ff 40000;"				\
+	" tftp ${loadaddr} ixdp425/u-boot.bin;"				\
+	" run eraseboot writeboot\0"					\
+	"eraseboot=protect off 50000000 5003ffff;"			\
+	" erase 50000000 5003ffff\0"					\
+	"writeboot=cp.b 10000 50000000 ${filesize}\0"			\
+	"updateucode=loady;"						\
+	" era ${npe_ucode} +${filesize};"				\
+	" cp.b ${loadaddr} ${npe_ucode} ${filesize}\0"			\
+	"updateroot=tftp ${loadaddr} ${rootfile};"			\
+	" era ${rootaddr} +${filesize};"				\
+	" cp.b ${loadaddr} ${rootaddr} ${filesize}\0"			\
+	"updatekern=tftp ${loadaddr} ${kernelfile};"			\
+	" era ${kerneladdr} +${filesize};"				\
+	" cp.b ${loadaddr} ${kerneladdr} ${filesize}\0"			\
+	"flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock4"	\
+	" rootfstype=squashfs,jffs2 init=/etc/preinit\0"		\
+	"netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock4"	\
+	" rootfstype=squashfs,jffs2 init=/etc/preinit\0"		\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
+	"addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0"	\
+	"boot_flash=run flashargs addtty addeth;"			\
+	" bootm ${kerneladdr}\0"					\
+	"boot_net=run netargs addtty addeth;"				\
+	" tftpboot ${loadaddr} ${kernelfile};"				\
+	" bootm\0"
+
+/* additions for new relocation code, must be added to all boards */
+#define CONFIG_SYS_INIT_SP_ADDR						\
+	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
+/*
+ * GPIO settings
+ */
+#define CONFIG_SYS_GPIO_UTOPIA_GPIO1    0
+#define CONFIG_SYS_GPIO_UTOPIA_IRQ_N    1
+#define CONFIG_SYS_GPIO_HSS1_IRQ_N      2
+#define CONFIG_SYS_GPIO_HSS0_IRQ_N      3
+#define CONFIG_SYS_GPIO_ETH0_IRQ_N      4
+#define CONFIG_SYS_GPIO_ETH1_IRQ_N      5
+#define CONFIG_SYS_GPIO_I2C_SCL	        6
+#define CONFIG_SYS_GPIO_I2C_SDA	        7
+#define CONFIG_SYS_GPIO_PCI_INTD_N	8
+#define CONFIG_SYS_GPIO_PCI_INTC_N	9
+#define CONFIG_SYS_GPIO_PCI_INTB_N	10
+#define CONFIG_SYS_GPIO_PCI_INTA_N	11
+#define CONFIG_SYS_GPIO_UTOPIA_GPIO0	12
+#define CONFIG_SYS_GPIO_PCI_RESET_N	13
+#define CONFIG_SYS_GPIO_PCI_CLK	        14
+#define CONFIG_SYS_GPIO_EXTBUS_CLK	15
+
 #endif  /* __CONFIG_H */

include/configs/ixdpg425.h

@@ -53,9 +53,6 @@
 /*
  * Misc configuration options
  */
-#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
-#define CONFIG_USE_IRQ          1	/* we need IRQ stuff for timer	*/
-#define CONFIG_TIMER_IRQ
 
 #define CONFIG_BOOTCOUNT_LIMIT		/* support for bootcount limit	*/
 #define CONFIG_SYS_BOOTCOUNT_ADDR	0x60003000 /* inside qmrg sram		*/
@@ -115,6 +112,7 @@
 #define CONFIG_SYS_MEMTEST_END         0x00800000      /* 4 ... 8 MB in DRAM   */
 #define CONFIG_SYS_LOAD_ADDR           0x00010000      /* default load address */
 
+#define CONFIG_IXP425_TIMER_CLK		66666666
 #define CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks */
 
 						/* valid baudrates */
@@ -179,6 +177,8 @@
 #define PHYS_SDRAM_1            0x00000000 /* SDRAM Bank #1 */
 #define PHYS_SDRAM_1_SIZE       0x02000000 /* 32 MB */
 
+#define CONFIG_SYS_TEXT_BASE	0x50000000
+
 #define PHYS_FLASH_1            0x50000000 /* Flash Bank #1 */
 #define PHYS_FLASH_SIZE         0x01000000 /* 16 MB */
 #define PHYS_FLASH_BANK_SIZE    0x01000000 /* 16 MB Banks */
@@ -248,4 +248,9 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE	32
 
+/* additions for new relocation code, must be added to all boards */
+#define CONFIG_SYS_SDRAM_BASE 0
+#define CONFIG_SYS_INIT_SP_ADDR						\
+	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
 #endif  /* __CONFIG_H */

include/configs/mx1fs2.h

@@ -88,7 +88,6 @@
 #define CONFIG_CMDLINE_TAG	     1	 /* send commandline to Kernel	     */
 #define CONFIG_SETUP_MEMORY_TAGS     1	 /* send memory definition to kernel */
 #define	 CONFIG_INITRD_TAG	     1	   /* send initrd params	*/
-#undef	CONFIG_VFD			 /* do not send framebuffer setup    */
 
 /*
  * Malloc pool need to host env + 128 Kb reserve for other allocations.

include/configs/pdnb3.h

@@ -50,9 +50,6 @@
 /*
  * Misc configuration options
  */
-#define CONFIG_USE_IRQ          1	/* we need IRQ stuff for timer	*/
-#define CONFIG_TIMER_IRQ
-
 #define CONFIG_BOOTCOUNT_LIMIT		/* support for bootcount limit	*/
 #define CONFIG_SYS_BOOTCOUNT_ADDR	0x60003000 /* inside qmrg sram		*/
 
@@ -117,6 +114,7 @@
 #define CONFIG_SYS_MEMTEST_END         0x00800000      /* 4 ... 8 MB in DRAM   */
 #define CONFIG_SYS_LOAD_ADDR           0x00010000      /* default load address */
 
+#define CONFIG_IXP425_TIMER_CLK		66666666
 #define CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks */
 						/* valid baudrates */
 #define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
@@ -188,6 +186,7 @@
 #define PHYS_SDRAM_1            0x00000000 /* SDRAM Bank #1 */
 #define PHYS_SDRAM_1_SIZE       0x02000000 /* 32 MB */
 
+#define CONFIG_SYS_TEXT_BASE	       0x50000000
 #define CONFIG_SYS_FLASH_BASE          0x50000000
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
 #if defined(CONFIG_SCPU)
@@ -345,4 +344,9 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE	32
 
+/* additions for new relocation code, must be added to all boards */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_INIT_SP_ADDR        \
+	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
 #endif  /* __CONFIG_H */

include/configs/scb9328.h

@@ -95,7 +95,6 @@
 #define CONFIG_CMDLINE_TAG	     1	 /* send commandline to Kernel	     */
 #define CONFIG_SETUP_MEMORY_TAGS     1	 /* send memory definition to kernel */
 #define CONFIG_INITRD_TAG	     1	 /* send initrd params		     */
-#undef	CONFIG_VFD			 /* do not send framebuffer setup    */
 
 /*
  * Malloc pool need to host env + 128 Kb reserve for other allocations.

include/configs/trab.h

@@ -1,419 +0,0 @@
-/*
- * (C) Copyright 2002-2005
- * Gary Jennejohn <garyj@denx.de>
- *
- * Configuation settings for the TRAB board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * Default configuration is with 8 MB Flash, 32 MB RAM
- */
-#if (!defined(CONFIG_FLASH_8MB)) && (!defined(CONFIG_FLASH_16MB))
-# define CONFIG_FLASH_8MB	/*  8 MB Flash	*/
-#endif
-#if (!defined(CONFIG_RAM_16MB)) && (!defined(CONFIG_RAM_32MB))
-# define CONFIG_RAM_32MB	/* 32 MB SDRAM	*/
-#endif
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_ARM920T	1	/* This is an arm920t CPU	*/
-#define CONFIG_S3C24X0	1	/* in a SAMSUNG S3C24x0-type SoC	*/
-#define CONFIG_S3C2400	1	/* specifically a SAMSUNG S3C2400 SoC	*/
-#define CONFIG_TRAB	1	/* on a TRAB Board		*/
-#undef CONFIG_TRAB_50MHZ	/* run the CPU at 50 MHz	*/
-
-/* automatic software updates (see board/trab/auto_update.c) */
-#define CONFIG_AUTO_UPDATE	1
-
-/* input clock of PLL */
-#define CONFIG_SYS_CLK_FREQ	12000000 /* TRAB has 12 MHz input clock */
-
-#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
-
-#define CONFIG_CMDLINE_TAG	 1	/* enable passing of ATAGs	*/
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG	 1
-
-#define CONFIG_SYS_DEVICE_NULLDEV	 1	/* enble null device		*/
-#define CONFIG_SILENT_CONSOLE	 1	/* enable silent startup	*/
-
-#define CONFIG_VERSION_VARIABLE	1       /* include version env variable */
-
-/***********************************************************
- * I2C stuff:
- * the TRAB is equipped with an ATMEL 24C04 EEPROM at
- * address 0x54 with 8bit addressing
- ***********************************************************/
-#define CONFIG_HARD_I2C			/* I2C with hardware support */
-#define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed */
-#define CONFIG_SYS_I2C_SLAVE		0x7F	/* I2C slave addr */
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR	0x54	/* EEPROM address */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1	/* 1 address byte */
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3	/* 8 bytes page write mode on 24C04 */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-/* USB stuff */
-#define CONFIG_USB_OHCI_NEW	1
-#define CONFIG_USB_STORAGE	1
-#define CONFIG_DOS_PARTITION	1
-
-#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
-#define CONFIG_SYS_USB_OHCI_CPU_INIT	1
-
-#define CONFIG_SYS_USB_OHCI_REGS_BASE	0x14200000
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"s3c2400"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-
-/*
- * Hardware drivers
- */
-#define CONFIG_NET_MULTI
-#define CONFIG_CS8900		/* we have a CS8900 on-board */
-#define CONFIG_CS8900_BASE	0x07000300 /* agrees with WIN CE PA */
-#define CONFIG_CS8900_BUS16	/* the Linux driver does accesses as shorts */
-
-#define CONFIG_DRIVER_S3C24X0_I2C 1	/* we use the buildin I2C controller */
-
-#define CONFIG_VFD		1	/* VFD linear frame buffer driver */
-#define VFD_TEST_LOGO		1	/* output a test logo to the VFDs */
-
-/*
- * select serial console configuration
- */
-#define CONFIG_S3C24X0_SERIAL
-#define CONFIG_SERIAL1		1	/* we use SERIAL 1 on TRAB */
-
-#define CONFIG_HWFLOW			/* include RTS/CTS flow control support	*/
-
-#define CONFIG_MODEM_SUPPORT	1	/* enable modem initialization stuff */
-
-#define	CONFIG_MODEM_KEY_MAGIC	"23"	/* hold down these keys to enable modem */
-
-/*
- * The following enables modem debugging stuff. The dbg() and
- * 'char screen[1024]' are used for debug printfs. Unfortunately,
- * it is usable only from BDI
- */
-#undef CONFIG_MODEM_SUPPORT_DEBUG
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BAUDRATE		115200
-
-#define	CONFIG_TIMESTAMP	1	/* Print timestamp info for images */
-
-/* Use s3c2400's RTC */
-#define CONFIG_RTC_S3C24X0	1
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_BSP
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_SNTP
-#define CONFIG_CMD_USB
-
-#ifdef CONFIG_HWFLOW
-    #define CONFIG_CMD_HWFLOW
-#endif
-
-#ifdef	CONFIG_VFD
-    #define CONFIG_CMD_VFD
-#endif
-
-#ifdef CONFIG_DRIVER_S3C24X0_I2C
-    #define CONFIG_CMD_EEPROM
-    #define CONFIG_CMD_I2C
-#endif
-
-#ifndef USE_920T_MMU
-    #undef CONFIG_CMD_CACHE
-#endif
-
-
-/* moved up */
-#define CONFIG_SYS_HUSH_PARSER		1	/* use "hush" command parser	*/
-
-#define CONFIG_BOOTDELAY	5
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* allow to break in always */
-#define CONFIG_PREBOOT		"echo;echo *** booting ***;echo"
-#define CONFIG_BOOTARGS		"console=ttyS0"
-#define CONFIG_NETMASK		255.255.0.0
-#define CONFIG_IPADDR		192.168.3.68
-#define CONFIG_HOSTNAME		trab
-#define CONFIG_SERVERIP		192.168.3.1
-#define CONFIG_BOOTCOMMAND	"burn_in"
-
-#ifndef CONFIG_FLASH_8MB	/* current config: 16 MB flash */
-#ifdef CONFIG_SYS_HUSH_PARSER
-#define	CONFIG_EXTRA_ENV_SETTINGS	\
-	"nfs_args=setenv bootargs root=/dev/nfs rw " \
-		"nfsroot=$serverip:$rootpath\0" \
-	"rootpath=/opt/eldk/arm_920TDI\0" \
-	"ram_args=setenv bootargs root=/dev/ram rw\0" \
-	"add_net=setenv bootargs $bootargs ethaddr=$ethaddr " \
-		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \
-	"add_misc=setenv bootargs $bootargs console=ttyS0 panic=1\0" \
-	"u-boot=/tftpboot/TRAB/u-boot.bin\0" \
-	"load=tftp C100000 ${u-boot}\0" \
-	"update=protect off 0 5FFFF;era 0 5FFFF;" \
-		"cp.b C100000 0 $filesize\0" \
-	"loadfile=/tftpboot/TRAB/uImage\0" \
-	"loadaddr=c400000\0" \
-	"net_load=tftpboot $loadaddr $loadfile\0" \
-	"net_nfs=run net_load nfs_args add_net add_misc;bootm\0" \
-	"kernel_addr=00060000\0" \
-	"flash_nfs=run nfs_args add_net add_misc;bootm $kernel_addr\0" \
-	"mdm_init1=ATZ\0" \
-	"mdm_init2=ATS0=1\0" \
-	"mdm_flow_control=rts/cts\0"
-#else /* !CONFIG_SYS_HUSH_PARSER */
-#define	CONFIG_EXTRA_ENV_SETTINGS	\
-	"nfs_args=setenv bootargs root=/dev/nfs rw " \
-		"nfsroot=${serverip}:${rootpath}\0" \
-	"rootpath=/opt/eldk/arm_920TDI\0" \
-	"ram_args=setenv bootargs root=/dev/ram rw\0" \
-	"add_net=setenv bootargs ${bootargs} ethaddr=${ethaddr} " \
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" \
-	"add_misc=setenv bootargs ${bootargs} console=ttyS0 panic=1\0" \
-	"u-boot=/tftpboot/TRAB/u-boot.bin\0" \
-	"load=tftp C100000 ${u-boot}\0" \
-	"update=protect off 0 5FFFF;era 0 5FFFF;" \
-		"cp.b C100000 0 ${filesize}\0" \
-	"loadfile=/tftpboot/TRAB/uImage\0" \
-	"loadaddr=c400000\0" \
-	"net_load=tftpboot ${loadaddr} ${loadfile}\0" \
-	"net_nfs=run net_load nfs_args add_net add_misc;bootm\0" \
-	"kernel_addr=000C0000\0" \
-	"flash_nfs=run nfs_args add_net add_misc;bootm ${kernel_addr}\0" \
-	"mdm_init1=ATZ\0" \
-	"mdm_init2=ATS0=1\0" \
-	"mdm_flow_control=rts/cts\0"
-#endif	/* CONFIG_SYS_HUSH_PARSER */
-#else	/* CONFIG_FLASH_8MB	 => 8 MB flash */
-#ifdef CONFIG_SYS_HUSH_PARSER
-#define	CONFIG_EXTRA_ENV_SETTINGS	\
-	"nfs_args=setenv bootargs root=/dev/nfs rw " \
-		"nfsroot=$serverip:$rootpath\0" \
-	"rootpath=/opt/eldk/arm_920TDI\0" \
-	"ram_args=setenv bootargs root=/dev/ram rw\0" \
-	"add_net=setenv bootargs $bootargs ethaddr=$ethaddr " \
-		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \
-	"add_misc=setenv bootargs $bootargs console=ttyS0 panic=1\0" \
-	"u-boot=/tftpboot/TRAB/u-boot.bin\0" \
-	"load=tftp C100000 ${u-boot}\0" \
-	"update=protect off 0 3FFFF;era 0 3FFFF;" \
-		"cp.b C100000 0 $filesize;" \
-		"setenv filesize;saveenv\0" \
-	"loadfile=/tftpboot/TRAB/uImage\0" \
-	"loadaddr=C400000\0" \
-	"net_load=tftpboot $loadaddr $loadfile\0" \
-	"net_nfs=run net_load nfs_args add_net add_misc;bootm\0" \
-	"kernel_addr=000C0000\0" \
-	"flash_nfs=run nfs_args add_net add_misc;bootm $kernel_addr\0" \
-	"mdm_init1=ATZ\0" \
-	"mdm_init2=ATS0=1\0" \
-	"mdm_flow_control=rts/cts\0"
-#else /* !CONFIG_SYS_HUSH_PARSER */
-#define	CONFIG_EXTRA_ENV_SETTINGS	\
-	"nfs_args=setenv bootargs root=/dev/nfs rw " \
-		"nfsroot=${serverip}:${rootpath}\0" \
-	"rootpath=/opt/eldk/arm_920TDI\0" \
-	"ram_args=setenv bootargs root=/dev/ram rw\0" \
-	"add_net=setenv bootargs ${bootargs} ethaddr=${ethaddr} " \
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" \
-	"add_misc=setenv bootargs ${bootargs} console=ttyS0 panic=1\0" \
-	"u-boot=/tftpboot/TRAB/u-boot.bin\0" \
-	"load=tftp C100000 ${u-boot}\0" \
-	"update=protect off 0 3FFFF;era 0 3FFFF;" \
-		"cp.b C100000 0 ${filesize};" \
-		"setenv filesize;saveenv\0" \
-	"loadfile=/tftpboot/TRAB/uImage\0" \
-	"loadaddr=C400000\0" \
-	"net_load=tftpboot ${loadaddr} ${loadfile}\0" \
-	"net_nfs=run net_load nfs_args add_net add_misc;bootm\0" \
-	"kernel_addr=000C0000\0" \
-	"flash_nfs=run nfs_args add_net add_misc;bootm ${kernel_addr}\0" \
-	"mdm_init1=ATZ\0" \
-	"mdm_init2=ATS0=1\0" \
-	"mdm_flow_control=rts/cts\0"
-#endif /* CONFIG_SYS_HUSH_PARSER */
-#endif	/* CONFIG_FLASH_8MB */
-
-#if 1	/* feel free to disable for development */
-#define	CONFIG_AUTOBOOT_KEYED		/* Enable password protection	*/
-#define CONFIG_AUTOBOOT_PROMPT		\
-	"\nEnter password - autoboot in %d sec...\n", bootdelay
-#define CONFIG_AUTOBOOT_DELAY_STR	"R"	/* 1st "password"	*/
-#endif
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	115200		/* speed to run kgdb serial port */
-/* what's this ? it's not used anywhere */
-#define CONFIG_KGDB_SER_INDEX	1		/* which serial port to use */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define	CONFIG_SYS_LONGHELP				/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT		"TRAB # "	/* Monitor Command Prompt	*/
-#ifdef	CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
-#endif
-
-#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define	CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x0C000000	/* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END		0x0D000000	/* 16 MB in DRAM	*/
-
-#define	CONFIG_SYS_LOAD_ADDR		0x0CF00000	/* default load address	*/
-
-#define	CONFIG_SYS_HZ			1000
-
-/* valid baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-#define CONFIG_MISC_INIT_R		/* have misc_init_r() function	*/
-
-/*-----------------------------------------------------------------------
- * burn-in test stuff.
- *
- * BURN_IN_CYCLE_DELAY defines the seconds to wait between each burn-in cycle
- * Because the burn-in test itself causes also an delay of about 4 seconds,
- * this time must be subtracted from the desired overall burn-in cycle time.
- */
-#define BURN_IN_CYCLE_DELAY	296	/* seconds between burn-in cycles */
-
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
-#endif
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1		0x0C000000	/* SDRAM Bank #1 */
-#ifndef CONFIG_RAM_16MB
-#define PHYS_SDRAM_1_SIZE	0x02000000	/* 32 MB */
-#else
-#define PHYS_SDRAM_1_SIZE	0x01000000	/* 16 MB */
-#endif
-
-#define CONFIG_SYS_FLASH_BASE		0x00000000	/* Flash Bank #1 */
-
-/* The following #defines are needed to get flash environment right */
-#define	CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
-#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)
-
-/* Dynamic MTD partition support */
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
-#define CONFIG_FLASH_CFI_MTD
-#define MTDIDS_DEFAULT		"nor0=0"
-
-/* production flash layout */
-#define MTDPARTS_DEFAULT	"mtdparts=0:16k(Firmware1)ro,"		\
-						"16k(Env1),"		\
-						"16k(Env2),"		\
-						"336k(Firmware2)ro,"	\
-						"896k(Kernel),"		\
-						"5376k(Root-FS),"	\
-						"1408k(JFFS2),"		\
-						"-(VFD)"
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#ifndef CONFIG_FLASH_8MB
-#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max number of sectors on one chip */
-#else
-#define CONFIG_SYS_MAX_FLASH_SECT	71	/* max number of sectors on one chip */
-#endif
-
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT	(15*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	(2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
-
-#define	CONFIG_ENV_IS_IN_FLASH	1
-
-/* Address and size of Primary Environment Sector	*/
-#ifndef CONFIG_FLASH_8MB
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x60000)
-#define CONFIG_ENV_SIZE		0x4000
-#define CONFIG_ENV_SECT_SIZE	0x20000
-#else
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x4000)
-#define CONFIG_ENV_SIZE		0x4000
-#define CONFIG_ENV_SECT_SIZE	0x4000
-#endif
-
-/* Address and size of Redundant Environment Sector	*/
-#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
-
-#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
-
-/* Initial value of the on-board touch screen brightness */
-#define CONFIG_SYS_BRIGHTNESS 0x20
-
-#endif	/* __CONFIG_H */

include/configs/xm250.h

@@ -139,7 +139,6 @@
 #define CONFIG_CMDLINE_TAG	 1	 /* send commandline to Kernel		*/
 #define CONFIG_SETUP_MEMORY_TAGS 1	 /* send memory definition to kernel	*/
 #define	CONFIG_INITRD_TAG	 1	 /* do not send initrd params		*/
-#undef	CONFIG_VFD			 /* do not send framebuffer setup	*/
 
 /*
  * Stack sizes

include/stdio_dev.h

@@ -105,9 +105,6 @@ int drv_arm_dcc_init(void);
 #ifdef CONFIG_LCD
 int	drv_lcd_init (void);
 #endif
-#ifdef CONFIG_VFD
-int	drv_vfd_init (void);
-#endif
 #if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
 int	drv_video_init (void);
 #endif

tools/Makefile

@@ -48,17 +48,21 @@ CONFIG_NETCONSOLE = y
 CONFIG_SHA1_CHECK_UB_IMG = y
 endif
 
+# Merge all the different vars for envcrc into one
+ENVCRC-$(CONFIG_ENV_IS_EMBEDDED) = y
+ENVCRC-$(CONFIG_ENV_IS_IN_DATAFLASH) = y
+ENVCRC-$(CONFIG_ENV_IS_IN_EEPROM) = y
+ENVCRC-$(CONFIG_ENV_IS_IN_FLASH) = y
+ENVCRC-$(CONFIG_ENV_IS_IN_ONENAND) = y
+ENVCRC-$(CONFIG_ENV_IS_IN_NAND) = y
+ENVCRC-$(CONFIG_ENV_IS_IN_NVRAM) = y
+ENVCRC-$(CONFIG_ENV_IS_IN_SPI_FLASH) = y
+CONFIG_BUILD_ENVCRC ?= $(ENVCRC-y)
+
 # Generated executable files
 BIN_FILES-$(CONFIG_LCD_LOGO) += bmp_logo$(SFX)
 BIN_FILES-$(CONFIG_VIDEO_LOGO) += bmp_logo$(SFX)
-BIN_FILES-$(CONFIG_ENV_IS_EMBEDDED) += envcrc$(SFX)
-BIN_FILES-$(CONFIG_ENV_IS_IN_DATAFLASH) += envcrc$(SFX)
-BIN_FILES-$(CONFIG_ENV_IS_IN_EEPROM) += envcrc$(SFX)
-BIN_FILES-$(CONFIG_ENV_IS_IN_FLASH) += envcrc$(SFX)
-BIN_FILES-$(CONFIG_ENV_IS_IN_ONENAND) += envcrc$(SFX)
-BIN_FILES-$(CONFIG_ENV_IS_IN_NAND) += envcrc$(SFX)
-BIN_FILES-$(CONFIG_ENV_IS_IN_NVRAM) += envcrc$(SFX)
-BIN_FILES-$(CONFIG_ENV_IS_IN_SPI_FLASH) += envcrc$(SFX)
+BIN_FILES-$(CONFIG_BUILD_ENVCRC) += envcrc$(SFX)
 BIN_FILES-$(CONFIG_CMD_NET) += gen_eth_addr$(SFX)
 BIN_FILES-$(CONFIG_CMD_LOADS) += img2srec$(SFX)
 BIN_FILES-$(CONFIG_INCA_IP) += inca-swap-bytes$(SFX)
@@ -67,7 +71,7 @@ BIN_FILES-$(CONFIG_NETCONSOLE) += ncb$(SFX)
 BIN_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1$(SFX)
 
 # Source files which exist outside the tools directory
-EXT_OBJ_FILES-y += common/env_embedded.o
+EXT_OBJ_FILES-$(CONFIG_BUILD_ENVCRC) += common/env_embedded.o
 EXT_OBJ_FILES-y += common/image.o
 EXT_OBJ_FILES-y += lib/crc32.o
 EXT_OBJ_FILES-y += lib/md5.o
@@ -77,7 +81,7 @@ EXT_OBJ_FILES-y += lib/sha1.o
 OBJ_FILES-$(CONFIG_LCD_LOGO) += bmp_logo.o
 OBJ_FILES-$(CONFIG_VIDEO_LOGO) += bmp_logo.o
 NOPED_OBJ_FILES-y += default_image.o
-OBJ_FILES-y += envcrc.o
+OBJ_FILES-$(CONFIG_BUILD_ENVCRC) += envcrc.o
 NOPED_OBJ_FILES-y += fit_image.o
 OBJ_FILES-$(CONFIG_CMD_NET) += gen_eth_addr.o
 OBJ_FILES-$(CONFIG_CMD_LOADS) += img2srec.o

tools/env/README

@@ -34,9 +34,6 @@ following lines are relevant:
 #define DEVICE2_ESIZE     0x4000
 #define DEVICE2_ENVSECTORS     2
 
-Current configuration matches the environment layout of the TRAB
-board.
-
 Un-define HAVE_REDUND, if you want to use the utlities on a system
 that does not have support for redundant environment enabled.
 If HAVE_REDUND is undefined, DEVICE2_NAME is ignored,

tools/env/fw_env.h

@@ -24,7 +24,7 @@
 /*
  * To build the utility with the run-time configuration
  * uncomment the next line.
- * See included "fw_env.config" sample file (TRAB board)
+ * See included "fw_env.config" sample file
  * for notes on configuration.
  */
 #define CONFIG_FILE     "/etc/fw_env.config"