Prepare v2012.04

Also tiny style cleanup to tools/patman/README

Signed-off-by: Wolfgang Denk <wd@denx.de>

.gitignore

@@ -10,6 +10,7 @@
 *.orig
 *.a
 *.o
+*.su
 *~
 *.swp
 *.patch
@@ -35,6 +36,7 @@
 /u-boot.dis
 /u-boot.lds
 /u-boot.ubl
+/u-boot.ais
 /u-boot.dtb
 /u-boot.sb
 

MAINTAINERS

@@ -41,6 +41,10 @@ Reinhard Arlt <reinhard.arlt@esd-electronics.com>
 
 	CPCI750		PPC750FX/GX
 
+Peter Barada <peter.barada@logicpd.com>
+
+	omap3_logic	ARM ARMV7 (Logic OMAP35xx/DM37xx)
+
 Yuli Barcohen <yuli@arabellasw.com>
 
 	Adder		MPC87x/MPC852T
@@ -436,11 +440,13 @@ Heiko Schocher <hs@denx.de>
 	municse		MPC5200
 	sc3		PPC405GP
 	suvd3		MPC8321
-	tuda1		MPC8321
-	tuxa1		MPC8321
 	uc101		MPC5200
 	ve8313		MPC8313
 
+Holger Brunck <holger.brunck@keymile.com>
+	tuge1		MPC8321
+	tuxx1		MPC8321
+
 Peter De Schrijver <p2@mind.be>
 
 	ML2		PPC4xx
@@ -568,10 +574,12 @@ Stefano Babic <sbabic@denx.de>
 
 	ea20		davinci
 	flea3		i.MX35
+	mt_ventoux	omap3
 	mx35pdk		i.MX35
 	mx51evk		i.MX51
 	polaris		xscale/pxa
 	trizepsiv	xscale/pxa
+	twister		omap3
  	vision2		i.MX51
 
 Jason Liu <r64343@freescale.com>
@@ -579,16 +587,13 @@ Jason Liu <r64343@freescale.com>
 	mx53evk         i.MX53
 	mx53loco        i.MX53
 	mx6qarm2	i.MX6Q
+	mx6qsabrelite   i.MX6Q
 
 Enric Balletbo i Serra <eballetbo@iseebcn.com>
 
 	igep0020	ARM ARMV7 (OMAP3xx SoC)
 	igep0030	ARM ARMV7 (OMAP3xx SoC)
 
-Dirk Behme <dirk.behme@gmail.com>
-
-	omap3_beagle	ARM ARMV7 (OMAP3530 SoC)
-
 Eric Benard <eric@eukrea.com>
 
 	cpuat91		ARM920T
@@ -639,6 +644,7 @@ Kristoffer Ericson <kristoffer.ericson@gmail.com>
 Fabio Estevam <fabio.estevam@freescale.com>
 
 	mx25pdk		i.MX25
+	mx28evk		i.MX28
 	mx31pdk		i.MX31
 	mx53ard		i.MX53
 	mx53smd		i.MX53
@@ -663,10 +669,9 @@ Igor Grinberg <grinberg@compulab.co.il>
 
 	cm-t35		ARM ARMV7 (OMAP3xx Soc)
 
-Kshitij Gupta <kshitij@ti.com>
+Stefan Herbrechtsmeier <stefan@code.herbrechtsmeier.net>
 
-	omap1510inn	ARM925T
-	omap1610inn	ARM926EJS
+	dns325		ARM926EJS (Kirkwood SoC)
 
 Vaibhav Hiremath <hvaibhav@ti.com>
 
@@ -704,6 +709,11 @@ Chander Kashyap <k.chander@samsung.com>
 
 	origen			ARM ARMV7 (EXYNOS4210 SoC)
 	SMDKV310		ARM ARMV7 (EXYNOS4210 SoC)
+	SMDK5250		ARM ARMV7 (EXYNOS5250 SoC)
+
+Heungjun Kim <riverful.kim@samsung.com>
+
+	trats			ARM ARMV7 (EXYNOS4210 SoC)
 
 Torsten Koschorrek <koschorrek@synertronixx.de>
 	scb9328		ARM920T (i.MXL)
@@ -748,10 +758,6 @@ Nagendra T S  <nagendra@mistralsolutions.com>
 
    am3517_crane    ARM ARMV7 (AM35x SoC)
 
-Chandan Nath <chandan.nath@ti.com>
-
-	am335x_evm	ARM ARMV7 (AM33xx Soc)
-
 Kyungmin Park <kyungmin.park@samsung.com>
 
 	apollon		ARM1136EJS
@@ -782,8 +788,20 @@ Stelian Pop <stelian@popies.net>
 	at91sam9263ek	ARM926EJS (AT91SAM9263 SoC)
 	at91sam9rlek	ARM926EJS (AT91SAM9RL SoC)
 
+Thierry Reding <thierry.reding@avionic-design.de>
+
+	plutux		Tegra2 (ARM7 & A9 Dual Core)
+	medcom		Tegra2 (ARM7 & A9 Dual Core)
+
+Christian Riesch <christian.riesch@omicron.at>
+Manfred Rudigier <manfred.rudigier@omicron.at>
+
+	calimain	ARM926EJS (AM1808 SoC)
+
 Tom Rini <trini@ti.com>
 
+	am335x_evm	ARM ARMV7 (AM33xx Soc)
+	omap3_beagle	ARM ARMV7 (OMAP3xx SoC)
 	omap3_evm	ARM ARMV7 (OMAP3xx SoC)
 
 Tom Rix <Tom.Rix@windriver.com>
@@ -885,10 +903,12 @@ Tom Warren <twarren@nvidia.com>
 Stephen Warren <swarren@nvidia.com>
 
 	ventana		Tegra2 (ARM7 & A9 Dual Core)
+	paz00		Tegra2 (ARM7 & A9 Dual Core)
 
 Thomas Weber <weber@corscience.de>
 
 	devkit8000	ARM ARMV7 (OMAP3530 SoC)
+	tricorder	ARM ARMV7 (OMAP3503 SoC)
 
 Lei Wen <leiwen@marvell.com>
 
@@ -903,6 +923,10 @@ Richard Woodruff <r-woodruff2@ti.com>
 
 	omap2420h4	ARM1136EJS
 
+Ilya Yanok <yanok@emcraft.com>
+
+	mcx		ARM ARMV7 (AM35x SoC)
+
 Syed Mohammed Khasim <sm.khasim@gmail.com>
 Sughosh Ganu <urwithsughosh@gmail.com>
 
@@ -913,6 +937,9 @@ Sughosh Ganu <urwithsughosh@gmail.com>
 Unknown / orphaned boards:
  	Board		CPU	Last known maintainer / Comment
 .........................................................................
+
+	omap1510inn	ARM925T         Kshitij Gupta <kshitij@ti.com>
+
 	lubbock		xscale/pxa	Kyle Harris <kharris@nexus-tech.net> / dead address
 
 	imx31_phycore_eet i.MX31  Guennadi Liakhovetski <g.liakhovetski@gmx.de> / resigned
@@ -1148,6 +1175,11 @@ Chong Huang <chuang@ucrobotics.com>
 
 	bf525-ucr2	BF525
 
+Dimitar Penev <dpn@switchfin.org>
+
+	BR4 Appliance	BF537
+	PR1 Appliance	BF537
+
 #########################################################################
 # NDS32 Systems:							#
 #									#
@@ -1160,6 +1192,17 @@ Macpaul Lin <macpaul@andestech.com>
 	ADP-AG101	N1213 (AG101 SoC)
 	ADP-AG101P	N1213 (AG101P XC5 FPGA)
 
+#########################################################################
+# OpenRISC Systems:							#
+#									#
+# Maintainer Name, Email Address					#
+#	Board		CPU						#
+#########################################################################
+
+Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
+
+	openrisc-generic	OpenRISC
+
 #########################################################################
 # End of MAINTAINERS list						#
 #########################################################################

MAKEALL

@@ -17,6 +17,8 @@ usage()
 	  -v VENDOR, --vendor VENDOR   Build all boards with vendor VENDOR
 	  -s SOC,    --soc SOC         Build all boards with soc SOC
 	  -l,        --list            List all targets to be built
+	  -m,        --maintainers     List all targets and maintainer email
+	  -M,        --mails           List all targets and all affilated emails
 	  -h,        --help            This help output
 
 	Selections by these options are logically ANDed; if the same option
@@ -48,8 +50,8 @@ usage()
 	exit ${ret}
 }
 
-SHORT_OPTS="ha:c:v:s:l"
-LONG_OPTS="help,arch:,cpu:,vendor:,soc:,list"
+SHORT_OPTS="ha:c:v:s:lmM"
+LONG_OPTS="help,arch:,cpu:,vendor:,soc:,list,maintainers,mails"
 
 # Option processing based on util-linux-2.13/getopt-parse.bash
 
@@ -67,6 +69,8 @@ eval set -- "$TEMP"
 
 SELECTED=''
 ONLY_LIST=''
+PRINT_MAINTS=''
+MAINTAINERS_ONLY=''
 
 while true ; do
 	case "$1" in
@@ -109,6 +113,15 @@ while true ; do
 	-l|--list)
 		ONLY_LIST='y'
 		shift ;;
+	-m|--maintainers)
+		ONLY_LIST='y'
+		PRINT_MAINTS='y'
+		MAINTAINERS_ONLY='y'
+		shift ;;
+	-M|--mails)
+		ONLY_LIST='y'
+		PRINT_MAINTS='y'
+		shift ;;
 	-h|--help)
 		usage ;;
 	--)
@@ -409,6 +422,11 @@ LIST_mips_el="			\
 	${LIST_xburst_el}	\
 	${LIST_au1xx0_el}	\
 "
+#########################################################################
+## OpenRISC Systems
+#########################################################################
+
+LIST_openrisc="$(boards_by_arch openrisc)"
 
 #########################################################################
 ## x86 Systems
@@ -478,11 +496,107 @@ LIST_nds32="$(boards_by_arch nds32)"
 
 #-----------------------------------------------------------------------
 
+get_target_location() {
+	local target=$1
+	local BOARD_NAME=""
+	local CONFIG_NAME=""
+	local board=""
+	local vendor=""
+
+	# Automatic mode
+	local line=`egrep -i "^[[:space:]]*${target}[[:space:]]" boards.cfg`
+
+	if [ -z "${line}" ] ; then echo "" ; return ; fi
+
+	set ${line}
+
+	# add default board name if needed
+	[ $# = 3 ] && set ${line} ${1}
+
+	CONFIG_NAME="${1%_config}"
+
+	[ "${BOARD_NAME}" ] || BOARD_NAME="${1%_config}"
+
+	if [ "$4" = "-" ] ; then
+		board=${BOARD_NAME}
+	else
+		board="$4"
+	fi
+
+	[ $# -gt 4 ] && [ "$5" != "-" ] && vendor="$5"
+	[ $# -gt 6 ] && [ "$7" != "-" ] && {
+		tmp="${7%:*}"
+		if [ "$tmp" ] ; then
+			CONFIG_NAME="$tmp"
+		fi
+	}
+
+	# Assign board directory to BOARDIR variable
+	if [ -z "${vendor}" ] ; then
+	    BOARDDIR=${board}
+	else
+	    BOARDDIR=${vendor}/${board}
+	fi
+
+	echo "${CONFIG_NAME}:${BOARDDIR}"
+}
+
+get_target_maintainers() {
+	local name=`echo $1 | cut -d : -f 1`
+
+	if ! grep -qsi "[[:blank:]]${name}[[:blank:]]" MAINTAINERS ; then
+		echo ""
+		return ;
+	fi
+
+	local line=`tac MAINTAINERS | grep -ni "[[:blank:]]${name}[[:blank:]]" | cut -d : -f 1`
+	local mail=`tac MAINTAINERS | tail -n +${line} | \
+		sed -n ":start /.*@.*/ { b mail } ; n ; b start ; :mail /.*@.*/ { p ; n ; b mail } ; q" | \
+		sed "s/^.*<//;s/>.*$//"`
+	echo "$mail"
+}
+
+list_target() {
+	if [ "$PRINT_MAINTS" != 'y' ] ; then
+		echo "$1"
+		return
+	fi
+
+	echo -n "$1:"
+
+	local loc=`get_target_location $1`
+
+	if [ -z "${loc}" ] ; then echo "ERROR" ; return ; fi
+
+	local maintainers_result=`get_target_maintainers ${loc} | tr " " "\n"`
+
+	if [ "$MAINTAINERS_ONLY" != 'y' ] ; then
+
+		local dir=`echo ${loc} | cut -d ":" -f 2`
+		local cfg=`echo ${loc} | cut -d ":" -f 1`
+		local git_result=`git log --format=%aE board/${dir} \
+				include/configs/${cfg}.h | grep "@"`
+		local git_result_recent=`echo ${git_result} | tr " " "\n" | \
+						head -n 3`
+		local git_result_top=`echo ${git_result} | tr " " "\n" | \
+			sort | uniq -c | sort -nr | head -n 3 | \
+			sed "s/^ \+[0-9]\+ \+//"`
+
+		echo -e "$git_result_recent\n$git_result_top\n$maintainers_result" | \
+			sort -u | tr "\n" " " | sed "s/ $//" ;
+	else
+		echo -e "$maintainers_result" | sort -u | tr "\n" " " | \
+						sed "s/ $//" ;
+	fi
+
+	echo ""
+}
+
 build_target() {
 	target=$1
 
 	if [ "$ONLY_LIST" == 'y' ] ; then
-		echo "$target"
+		list_target ${target}
 		return
 	fi
 
@@ -506,8 +620,12 @@ build_target() {
 
 	TOTAL_CNT=$((TOTAL_CNT + 1))
 
-	${CROSS_COMPILE}size ${BUILD_DIR}/u-boot \
-				| tee -a ${LOG_DIR}/$target.MAKELOG
+	OBJS=${BUILD_DIR}/u-boot
+	if [ -e ${BUILD_DIR}/spl/u-boot-spl ]; then
+		OBJS="${OBJS} ${BUILD_DIR}/spl/u-boot-spl"
+	fi
+
+	${CROSS_COMPILE}size ${OBJS} | tee -a ${LOG_DIR}/$target.MAKELOG
 }
 build_targets() {
 	for t in "$@" ; do

Makefile

@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2000-2011
+# (C) Copyright 2000-2012
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
@@ -21,8 +21,8 @@
 # MA 02111-1307 USA
 #
 
-VERSION = 2011
-PATCHLEVEL = 12
+VERSION = 2012
+PATCHLEVEL = 04
 SUBLEVEL =
 EXTRAVERSION =
 ifneq "$(SUBLEVEL)" ""
@@ -174,6 +174,8 @@ include $(TOPDIR)/config.mk
 # that (or fail if absent).  Otherwise, search for a linker script in a
 # standard location.
 
+LDSCRIPT_MAKEFILE_DIR = $(dir $(LDSCRIPT))
+
 ifndef LDSCRIPT
 	#LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds.debug
 	ifdef CONFIG_SYS_LDSCRIPT
@@ -182,6 +184,7 @@ ifndef LDSCRIPT
 	endif
 endif
 
+# If there is no specified link script, we look in a number of places for it
 ifndef LDSCRIPT
 	ifeq ($(CONFIG_NAND_U_BOOT),y)
 		LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds
@@ -195,6 +198,11 @@ ifndef LDSCRIPT
 	ifeq ($(wildcard $(LDSCRIPT)),)
 		LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot.lds
 	endif
+	ifeq ($(wildcard $(LDSCRIPT)),)
+		LDSCRIPT := $(TOPDIR)/arch/$(ARCH)/cpu/u-boot.lds
+		# We don't expect a Makefile here
+		LDSCRIPT_MAKEFILE_DIR =
+	endif
 	ifeq ($(wildcard $(LDSCRIPT)),)
 $(error could not find linker script)
 	endif
@@ -294,7 +302,7 @@ LIBS += lib/libfdt/libfdt.o
 LIBS += api/libapi.o
 LIBS += post/libpost.o
 
-ifneq ($(CONFIG_AM335X)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
+ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
 LIBS += $(CPUDIR)/omap-common/libomap-common.o
 endif
 
@@ -336,6 +344,7 @@ export PLATFORM_LIBS
 # on the fly.
 LDPPFLAGS += \
 	-include $(TOPDIR)/include/u-boot/u-boot.lds.h \
+	-DCPUDIR=$(CPUDIR) \
 	$(shell $(LD) --version | \
 	  sed -ne 's/GNU ld version \([0-9][0-9]*\)\.\([0-9][0-9]*\).*/-DLD_MAJOR=\1 -DLD_MINOR=\2/p')
 
@@ -366,7 +375,6 @@ ALL-y += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map
 ALL-$(CONFIG_NAND_U_BOOT) += $(obj)u-boot-nand.bin
 ALL-$(CONFIG_ONENAND_U_BOOT) += $(obj)u-boot-onenand.bin
 ONENAND_BIN ?= $(obj)onenand_ipl/onenand-ipl-2k.bin
-ALL-$(CONFIG_MMC_U_BOOT) += $(obj)mmc_spl/u-boot-mmc-spl.bin
 ALL-$(CONFIG_SPL) += $(obj)spl/u-boot-spl.bin
 ALL-$(CONFIG_OF_SEPARATE) += $(obj)u-boot.dtb $(obj)u-boot-dtb.bin
 
@@ -429,6 +437,18 @@ $(obj)u-boot.ubl:       $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
 		rm $(obj)u-boot-ubl.bin
 		rm $(obj)spl/u-boot-spl-pad.bin
 
+$(obj)u-boot.ais:       $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
+		$(obj)tools/mkimage -s -n /dev/null -T aisimage \
+			-e $(CONFIG_SPL_TEXT_BASE) \
+			-d $(obj)spl/u-boot-spl.bin \
+			$(obj)spl/u-boot-spl.ais
+		$(OBJCOPY) ${OBJCFLAGS} -I binary \
+			--pad-to=$(CONFIG_SPL_MAX_SIZE) -O binary \
+			$(obj)spl/u-boot-spl.ais $(obj)spl/u-boot-spl-pad.ais
+		cat $(obj)spl/u-boot-spl-pad.ais $(obj)u-boot.bin > \
+			$(obj)u-boot.ais
+		rm $(obj)spl/u-boot-spl{,-pad}.ais
+
 $(obj)u-boot.sb:       $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin
 		elftosb -zdf imx28 -c $(TOPDIR)/board/$(BOARDDIR)/u-boot.bd \
 			-o $(obj)u-boot.sb
@@ -490,11 +510,6 @@ onenand_ipl:	$(TIMESTAMP_FILE) $(VERSION_FILE) $(obj)include/autoconf.mk
 $(obj)u-boot-onenand.bin:	onenand_ipl $(obj)u-boot.bin
 		cat $(ONENAND_BIN) $(obj)u-boot.bin > $(obj)u-boot-onenand.bin
 
-mmc_spl:	$(TIMESTAMP_FILE) $(VERSION_FILE) depend
-		$(MAKE) -C mmc_spl/board/$(BOARDDIR) all
-
-$(obj)mmc_spl/u-boot-mmc-spl.bin:	mmc_spl
-
 $(obj)spl/u-boot-spl.bin:	$(SUBDIR_TOOLS) depend
 		$(MAKE) -C spl all
 
@@ -507,7 +522,7 @@ depend dep:	$(TIMESTAMP_FILE) $(VERSION_FILE) \
 		$(obj)include/autoconf.mk \
 		$(obj)include/generated/generic-asm-offsets.h \
 		$(obj)include/generated/asm-offsets.h
-		for dir in $(SUBDIRS) $(CPUDIR) $(dir $(LDSCRIPT)) ; do \
+		for dir in $(SUBDIRS) $(CPUDIR) $(LDSCRIPT_MAKEFILE_DIR) ; do \
 			$(MAKE) -C $$dir _depend ; done
 
 TAG_SUBDIRS = $(SUBDIRS)
@@ -517,6 +532,11 @@ TAG_SUBDIRS += include
 FIND := find
 FINDFLAGS := -L
 
+checkstack:
+		$(CROSS_COMPILE)objdump -d $(obj)u-boot \
+			`$(FIND) $(obj) -name u-boot-spl -print` | \
+			perl $(src)tools/checkstack.pl $(ARCH)
+
 tags ctags:
 		ctags -w -o $(obj)ctags `$(FIND) $(FINDFLAGS) $(TAG_SUBDIRS) \
 						-name '*.[chS]' -print`
@@ -655,14 +675,6 @@ ucname	= $(shell echo $(1) | sed -e 's/\(.*\)_config/\U\1/')
 # ARM
 #========================================================================
 
-spear300_config \
-spear310_config \
-spear320_config :	unconfig
-	@$(MKCONFIG) -n $@ -t $@ spear3xx arm arm926ejs $(@:_config=) spear spear
-
-spear600_config :	unconfig
-	@$(MKCONFIG) -n $@ -t $@ spear6xx arm arm926ejs $(@:_config=) spear spear
-
 SX1_stdout_serial_config \
 SX1_config:		unconfig
 	@mkdir -p $(obj)include
@@ -673,18 +685,6 @@ SX1_config:		unconfig
 	fi;
 	@$(MKCONFIG) -n $@ SX1 arm arm925t sx1
 
-#########################################################################
-## XScale Systems
-#########################################################################
-
-pdnb3_config \
-scpu_config:	unconfig
-	@mkdir -p $(obj)include
-	@if [ "$(findstring scpu_,$@)" ] ; then \
-		echo "#define CONFIG_SCPU"	>>$(obj)include/config.h ; \
-	fi
-	@$(MKCONFIG) -n $@ -a pdnb3 arm ixp pdnb3 prodrive
-
 #########################################################################
 ## ARM1176 Systems
 #########################################################################
@@ -723,6 +723,7 @@ clean:
 	       $(obj)tools/gdb/{astest,gdbcont,gdbsend}			  \
 	       $(obj)tools/gen_eth_addr    $(obj)tools/img2srec		  \
 	       $(obj)tools/mk{env,}image   $(obj)tools/mpc86x_clk	  \
+	       $(obj)tools/mk{smdk5250,}spl				  \
 	       $(obj)tools/ncb		   $(obj)tools/ubsha1
 	@rm -f $(obj)board/cray/L1/{bootscript.c,bootscript.image}	  \
 	       $(obj)board/matrix_vision/*/bootscript.img		  \
@@ -737,14 +738,13 @@ clean:
 	@rm -f $(obj)$(CPUDIR)/$(SOC)/asm-offsets.s
 	@rm -f $(obj)nand_spl/{u-boot.lds,u-boot-nand_spl.lds,u-boot-spl,u-boot-spl.map,System.map}
 	@rm -f $(obj)onenand_ipl/onenand-{ipl,ipl.bin,ipl.map}
-	@rm -f $(obj)mmc_spl/{u-boot.lds,u-boot-spl,u-boot-spl.map,u-boot-spl.bin,u-boot-mmc-spl.bin}
 	@rm -f $(ONENAND_BIN)
 	@rm -f $(obj)onenand_ipl/u-boot.lds
 	@rm -f $(obj)spl/{u-boot-spl,u-boot-spl.bin,u-boot-spl.lds,u-boot-spl.map}
 	@rm -f $(obj)MLO
 	@rm -f $(TIMESTAMP_FILE) $(VERSION_FILE)
 	@find $(OBJTREE) -type f \
-		\( -name 'core' -o -name '*.bak' -o -name '*~' \
+		\( -name 'core' -o -name '*.bak' -o -name '*~' -o -name '*.su' \
 		-o -name '*.o'	-o -name '*.a' -o -name '*.exe'	\) -print \
 		| xargs rm -f
 
@@ -762,6 +762,7 @@ clobber:	tidy
 	@rm -f $(obj)u-boot.kwb
 	@rm -f $(obj)u-boot.imx
 	@rm -f $(obj)u-boot.ubl
+	@rm -f $(obj)u-boot.ais
 	@rm -f $(obj)u-boot.dtb
 	@rm -f $(obj)u-boot.sb
 	@rm -f $(obj)tools/inca-swap-bytes
@@ -771,7 +772,6 @@ clobber:	tidy
 	@rm -fr $(obj)include/generated
 	@[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -name "*" -type l -print | xargs rm -f
 	@[ ! -d $(obj)onenand_ipl ] || find $(obj)onenand_ipl -name "*" -type l -print | xargs rm -f
-	@[ ! -d $(obj)mmc_spl ] || find $(obj)mmc_spl -name "*" -type l -print | xargs rm -f
 	@rm -f $(obj)dts/*.tmp
 
 mrproper \

README

@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2000 - 2011
+# (C) Copyright 2000 - 2012
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
@@ -374,6 +374,12 @@ The following options need to be configured:
 		Defines the string to utilize when trying to match PCIe device
 		tree nodes for the given platform.
 
+- Generic CPU options:
+		CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
+
+		Defines the endianess of the CPU. Implementation of those
+		values is arch specific.
+
 - Intel Monahans options:
 		CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
 
@@ -420,6 +426,12 @@ The following options need to be configured:
 		XWAY SoCs for booting from NOR flash. The U-Boot image needs to
 		be swapped if a flash programmer is used.
 
+- ARM options:
+		CONFIG_SYS_EXCEPTION_VECTORS_HIGH
+
+		Select high exception vectors of the ARM core, e.g., do not
+		clear the V bit of the c1 register of CP15.
+
 - Linux Kernel Interface:
 		CONFIG_CLOCKS_IN_MHZ
 
@@ -638,22 +650,14 @@ The following options need to be configured:
 		'Sane' compilers will generate smaller code if
 		CONFIG_PRE_CON_BUF_SZ is a power of 2
 
-- Pre-console putc():
-		Prior to the console being initialised, console output is
-		normally silently discarded. This can be annoying if a
-		panic() happens in this time.
-
-		If the CONFIG_PRE_CONSOLE_PUTC option is defined, then
-		U-Boot will call board_pre_console_putc() for each output
-		character in this case, This function should try to output
-		the character if possible, perhaps on all available UARTs
-		(it will need to do this directly, since the console code
-		is not functional yet). Note that if the panic happens
-		early enough, then it is possible that board_init_f()
-		(or even arch_cpu_init() on ARM) has not been called yet.
-		You should init all clocks, GPIOs, etc. that are needed
-		to get the character out. Baud rates will need to default
-		to something sensible.
+- Safe printf() functions
+		Define CONFIG_SYS_VSNPRINTF to compile in safe versions of
+		the printf() functions. These are defined in
+		include/vsprintf.h and include snprintf(), vsnprintf() and
+		so on. Code size increase is approximately 300-500 bytes.
+		If this option is not given then these functions will
+		silently discard their buffer size argument - this means
+		you are not getting any overflow checking in this case.
 
 - Boot Delay:	CONFIG_BOOTDELAY - in seconds
 		Delay before automatically booting the default image;
@@ -800,6 +804,7 @@ The following options need to be configured:
 					  (requires CONFIG_CMD_I2C)
 		CONFIG_CMD_SETGETDCR	  Support for DCR Register access
 					  (4xx only)
+		CONFIG_CMD_SF		* Read/write/erase SPI NOR flash
 		CONFIG_CMD_SHA1SUM	  print sha1 memory digest
 					  (requires CONFIG_CMD_MEMORY)
 		CONFIG_CMD_SOURCE	  "source" command Support
@@ -1020,6 +1025,9 @@ The following options need to be configured:
 			If this defined, the driver is quiet.
 			The driver doen't show link status messages.
 
+		CONFIG_CALXEDA_XGMAC
+		Support for the Calxeda XGMAC device
+
 		CONFIG_DRIVER_LAN91C96
 		Support for SMSC's LAN91C96 chips.
 
@@ -1123,6 +1131,9 @@ The following options need to be configured:
 				May be defined to allow interrupt polling
 				instead of using asynchronous interrupts
 
+		CONFIG_USB_EHCI_TXFIFO_THRESH enables setting of the
+		txfilltuning field in the EHCI controller on reset.
+
 - USB Device:
 		Define the below if you wish to use the USB console.
 		Once firmware is rebuilt from a serial console issue the
@@ -1146,6 +1157,14 @@ The following options need to be configured:
 			Define this to have a tty type of device available to
 			talk to the UDC device
 
+			CONFIG_USBD_HS
+			Define this to enable the high speed support for usb
+			device and usbtty. If this feature is enabled, a routine
+			int is_usbd_high_speed(void)
+			also needs to be defined by the driver to dynamically poll
+			whether the enumeration has succeded at high speed or full
+			speed.
+
 			CONFIG_SYS_CONSOLE_IS_IN_ENV
 			Define this if you want stdin, stdout &/or stderr to
 			be set to usbtty.
@@ -1231,8 +1250,12 @@ The following options need to be configured:
 
 - FAT(File Allocation Table) filesystem write function support:
 		CONFIG_FAT_WRITE
-		Support for saving memory data as a file
-		in FAT formatted partition
+
+		Define this to enable support for saving memory data as a
+		file in FAT formatted partition.
+
+		This will also enable the command "fatwrite" enabling the
+		user to write files to FAT.
 
 - Keyboard Support:
 		CONFIG_ISA_KEYBOARD
@@ -2179,6 +2202,25 @@ The following options need to be configured:
 		allows to read/write in Dataflash via the standard
 		commands cp, md...
 
+- Serial Flash support
+		CONFIG_CMD_SF
+
+		Defining this option enables SPI flash commands
+		'sf probe/read/write/erase/update'.
+
+		Usage requires an initial 'probe' to define the serial
+		flash parameters, followed by read/write/erase/update
+		commands.
+
+		The following defaults may be provided by the platform
+		to handle the common case when only a single serial
+		flash is present on the system.
+
+		CONFIG_SF_DEFAULT_BUS		Bus identifier
+		CONFIG_SF_DEFAULT_CS		Chip-select
+		CONFIG_SF_DEFAULT_MODE 		(see include/spi.h)
+		CONFIG_SF_DEFAULT_SPEED		in Hz
+
 - SystemACE Support:
 		CONFIG_SYSTEMACE
 
@@ -2223,6 +2265,31 @@ The following options need to be configured:
 		example, some LED's) on your board. At the moment,
 		the following checkpoints are implemented:
 
+- Detailed boot stage timing
+		CONFIG_BOOTSTAGE
+		Define this option to get detailed timing of each stage
+		of the boot process.
+
+		CONFIG_BOOTSTAGE_USER_COUNT
+		This is the number of available user bootstage records.
+		Each time you call bootstage_mark(BOOTSTAGE_ID_ALLOC, ...)
+		a new ID will be allocated from this stash. If you exceed
+		the limit, recording will stop.
+
+		CONFIG_BOOTSTAGE_REPORT
+		Define this to print a report before boot, similar to this:
+
+		Timer summary in microseconds:
+		       Mark    Elapsed  Stage
+			  0          0  reset
+		  3,575,678  3,575,678  board_init_f start
+		  3,575,695         17  arch_cpu_init A9
+		  3,575,777         82  arch_cpu_init done
+		  3,659,598     83,821  board_init_r start
+		  3,910,375    250,777  main_loop
+		 29,916,167 26,005,792  bootm_start
+		 30,361,327    445,160  start_kernel
+
 Legacy uImage format:
 
   Arg	Where			When
@@ -2418,11 +2485,29 @@ FIT uImage format:
 		CONFIG_SPL
 		Enable building of SPL globally.
 
+		CONFIG_SPL_LDSCRIPT
+		LDSCRIPT for linking the SPL binary.
+
+		CONFIG_SPL_MAX_SIZE
+		Maximum binary size (text, data and rodata) of the SPL binary.
+
 		CONFIG_SPL_TEXT_BASE
 		TEXT_BASE for linking the SPL binary.
 
-		CONFIG_SPL_LDSCRIPT
-		LDSCRIPT for linking the SPL binary.
+		CONFIG_SPL_BSS_START_ADDR
+		Link address for the BSS within the SPL binary.
+
+		CONFIG_SPL_BSS_MAX_SIZE
+		Maximum binary size of the BSS section of the SPL binary.
+
+		CONFIG_SPL_STACK
+		Adress of the start of the stack SPL will use
+
+		CONFIG_SYS_SPL_MALLOC_START
+		Starting address of the malloc pool used in SPL.
+
+		CONFIG_SYS_SPL_MALLOC_SIZE
+		The size of the malloc pool used in SPL.
 
 		CONFIG_SPL_LIBCOMMON_SUPPORT
 		Support for common/libcommon.o in SPL binary
@@ -2439,6 +2524,45 @@ FIT uImage format:
 		CONFIG_SPL_MMC_SUPPORT
 		Support for drivers/mmc/libmmc.o in SPL binary
 
+		CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR,
+		CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS,
+		CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION
+		Address, size and partition on the MMC to load U-Boot from
+		when the MMC is being used in raw mode.
+
+		CONFIG_SPL_FAT_SUPPORT
+		Support for fs/fat/libfat.o in SPL binary
+
+		CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME
+		Filename to read to load U-Boot when reading from FAT
+
+		CONFIG_SPL_NAND_SIMPLE
+		Support for drivers/mtd/nand/libnand.o in SPL binary
+
+		CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_COUNT,
+		CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE,
+		CONFIG_SYS_NAND_BLOCK_SIZE, CONFIG_SYS_NAND_BAD_BLOCK_POS,
+		CONFIG_SYS_NAND_ECCPOS, CONFIG_SYS_NAND_ECCSIZE,
+		CONFIG_SYS_NAND_ECCBYTES
+		Defines the size and behavior of the NAND that SPL uses
+		to read U-Boot with CONFIG_SPL_NAND_SIMPLE
+
+		CONFIG_SYS_NAND_U_BOOT_OFFS
+		Location in NAND for CONFIG_SPL_NAND_SIMPLE to read U-Boot
+		from.
+
+		CONFIG_SYS_NAND_U_BOOT_START
+		Location in memory for CONFIG_SPL_NAND_SIMPLE to load U-Boot
+		to.
+
+		CONFIG_SYS_NAND_HW_ECC_OOBFIRST
+		Define this if you need to first read the OOB and then the
+		data. This is used for example on davinci plattforms.
+
+		CONFIG_SPL_OMAP3_ID_NAND
+		Support for an OMAP3-specific set of functions to return the
+		ID and MFR of the first attached NAND chip, if present.
+
 		CONFIG_SPL_SERIAL_SUPPORT
 		Support for drivers/serial/libserial.o in SPL binary
 
@@ -2448,9 +2572,6 @@ FIT uImage format:
 		CONFIG_SPL_SPI_SUPPORT
 		Support for drivers/spi/libspi.o in SPL binary
 
-		CONFIG_SPL_FAT_SUPPORT
-		Support for fs/fat/libfat.o in SPL binary
-
 		CONFIG_SPL_LIBGENERIC_SUPPORT
 		Support for lib/libgeneric.o in SPL binary
 
@@ -3298,11 +3419,6 @@ Low Level (hardware related) configuration options:
 		that is executed before the actual U-Boot. E.g. when
 		compiling a NAND SPL.
 
-- CONFIG_SYS_NAND_HW_ECC_OOBFIRST
-		define this, if you want to read first the oob data
-		and then the data. This is used for example on
-		davinci plattforms.
-
 - CONFIG_USE_ARCH_MEMCPY
   CONFIG_USE_ARCH_MEMSET
 		If these options are used a optimized version of memcpy/memset will
@@ -3383,7 +3499,7 @@ is done by typing:
 	make NAME_config
 
 where "NAME_config" is the name of one of the existing configu-
-rations; see the main Makefile for supported names.
+rations; see boards.cfg for supported names.
 
 Note: for some board special configuration names may exist; check if
       additional information is available from the board vendor; for
@@ -3438,10 +3554,8 @@ to port U-Boot to your hardware platform. To do this, follow these
 steps:
 
 1.  Add a new configuration option for your board to the toplevel
-    "Makefile" and to the "MAKEALL" script, using the existing
-    entries as examples. Note that here and at many other places
-    boards and other names are listed in alphabetical sort order. Please
-    keep this order.
+    "boards.cfg" file, using the existing entries as examples.
+    Follow the instructions there to keep the boards in order.
 2.  Create a new directory to hold your board specific code. Add any
     files you need. In your board directory, you will need at least
     the "Makefile", a "<board>.c", "flash.c" and "u-boot.lds".
@@ -3507,6 +3621,7 @@ go	- start application at address 'addr'
 run	- run commands in an environment variable
 bootm	- boot application image from memory
 bootp	- boot image via network using BootP/TFTP protocol
+bootz   - boot zImage from memory
 tftpboot- boot image via network using TFTP protocol
 	       and env variables "ipaddr" and "serverip"
 	       (and eventually "gatewayip")
@@ -3627,6 +3742,14 @@ List of environment variables (most likely not complete):
 
   fdt_high	- if set this restricts the maximum address that the
 		  flattened device tree will be copied into upon boot.
+		  For example, if you have a system with 1 GB memory
+		  at physical address 0x10000000, while Linux kernel
+		  only recognizes the first 704 MB as low memory, you
+		  may need to set fdt_high as 0x3C000000 to have the
+		  device tree blob be copied to the maximum address
+		  of the 704 MB low memory, so that Linux kernel can
+		  access it during the boot procedure.
+
 		  If this is set to the special value 0xFFFFFFFF then
 		  the fdt will not be copied at all on boot.  For this
 		  to work it must reside in writable memory, have
@@ -4319,6 +4442,18 @@ U-Boot supports the following image types:
 	useful when you configure U-Boot to use a real shell (hush)
 	as command interpreter.
 
+Booting the Linux zImage:
+-------------------------
+
+On some platforms, it's possible to boot Linux zImage. This is done
+using the "bootz" command. The syntax of "bootz" command is the same
+as the syntax of "bootm" command.
+
+Note, defining the CONFIG_SUPPORT_INITRD_RAW allows user to supply
+kernel with raw initrd images. The syntax is slightly different, the
+address of the initrd must be augmented by it's size, in the following
+format: "<initrd addres>:<initrd size>".
+
 
 Standalone HOWTO:
 =================

arch/arm/config.mk

@@ -70,13 +70,6 @@ PLATFORM_LIBS := $(OBJTREE)/arch/arm/lib/eabi_compat.o \
 endif
 endif
 
-ifdef CONFIG_SYS_LDSCRIPT
-# need to strip off double quotes
-LDSCRIPT := $(subst ",,$(CONFIG_SYS_LDSCRIPT))
-else
-LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds
-endif
-
 # needed for relocation
 ifndef CONFIG_NAND_SPL
 LDFLAGS_u-boot += -pie

arch/arm/cpu/arm1136/cpu.c

@@ -70,8 +70,105 @@ int cleanup_before_linux (void)
 static void cache_flush(void)
 {
 	unsigned long i = 0;
-
-	asm ("mcr p15, 0, %0, c7, c10, 0": :"r" (i)); /* clean entire data cache */
-	asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));  /* invalidate both caches and flush btb */
-	asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); /* mem barrier to sync things */
+	/* clean entire data cache */
+	asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (i));
+	/* invalidate both caches and flush btb */
+	asm volatile("mcr p15, 0, %0, c7, c7, 0" : : "r" (i));
+	/* mem barrier to sync things */
+	asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (i));
 }
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+
+#ifndef CONFIG_SYS_CACHELINE_SIZE
+#define CONFIG_SYS_CACHELINE_SIZE	32
+#endif
+
+void invalidate_dcache_all(void)
+{
+	asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
+}
+
+void flush_dcache_all(void)
+{
+	asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (0));
+	asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
+}
+
+static inline int bad_cache_range(unsigned long start, unsigned long stop)
+{
+	int ok = 1;
+
+	if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
+		ok = 0;
+
+	if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
+		ok = 0;
+
+	if (!ok)
+		debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
+			start, stop);
+
+	return ok;
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+	if (bad_cache_range(start, stop))
+		return;
+
+	while (start < stop) {
+		asm volatile("mcr p15, 0, %0, c7, c6, 1" : : "r" (start));
+		start += CONFIG_SYS_CACHELINE_SIZE;
+	}
+}
+
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+	if (bad_cache_range(start, stop))
+		return;
+
+	while (start < stop) {
+		asm volatile("mcr p15, 0, %0, c7, c14, 1" : : "r" (start));
+		start += CONFIG_SYS_CACHELINE_SIZE;
+	}
+
+	asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
+}
+
+void flush_cache(unsigned long start, unsigned long size)
+{
+	flush_dcache_range(start, start + size);
+}
+
+void enable_caches(void)
+{
+#ifndef CONFIG_SYS_ICACHE_OFF
+	icache_enable();
+#endif
+#ifndef CONFIG_SYS_DCACHE_OFF
+	dcache_enable();
+#endif
+}
+
+#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
+void invalidate_dcache_all(void)
+{
+}
+
+void flush_dcache_all(void)
+{
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+}
+
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+}
+
+void flush_cache(unsigned long start, unsigned long size)
+{
+}
+#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */

arch/arm/cpu/arm1136/mx31/generic.c

@@ -101,6 +101,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
 	case MXC_IPG_PERCLK:
 	case MXC_CSPI_CLK:
 	case MXC_UART_CLK:
+	case MXC_ESDHC_CLK:
 		return mx31_get_ipg_clk();
 	case MXC_IPU_CLK:
 		return mx31_get_hsp_clk();
@@ -209,6 +210,8 @@ static char *get_reset_cause(void)
 		return "WDOG";
 	case 0x0006:
 		return "JTAG";
+	case 0x0007:
+		return "ARM11P power gating";
 	default:
 		return "unknown reset";
 	}

arch/arm/cpu/arm1136/mx31/timer.c

@@ -153,6 +153,15 @@ void __udelay(unsigned long usec)
 		 /*NOP*/;
 }
 
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	return CONFIG_MX31_CLK32;
+}
+
 void reset_cpu(ulong addr)
 {
 	struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE;

arch/arm/cpu/arm1136/mx35/generic.c

@@ -393,7 +393,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
 /*
  * The MX35 has no fuse for MAC, return a NULL MAC
  */
-void imx_get_mac_from_fuse(unsigned char *mac)
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 {
 	memset(mac, 0, 6);
 }
@@ -422,6 +422,7 @@ U_BOOT_CMD(
 	""
 );
 
+#if defined(CONFIG_DISPLAY_CPUINFO)
 static char *get_reset_cause(void)
 {
 	/* read RCSR register from CCM module */
@@ -444,7 +445,6 @@ static char *get_reset_cause(void)
 	}
 }
 
-#if defined(CONFIG_DISPLAY_CPUINFO)
 int print_cpuinfo(void)
 {
 	u32 srev = get_cpu_rev();

arch/arm/cpu/arm1136/mx35/timer.c

@@ -25,7 +25,14 @@
 
 #include <common.h>
 #include <asm/io.h>
+#include <div64.h>
 #include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp	(gd->tbl)
+#define lastinc		(gd->lastinc)
 
 /* General purpose timers bitfields */
 #define GPTCR_SWR       (1<<15)	/* Software reset */
@@ -33,7 +40,24 @@
 #define GPTCR_CLKSOURCE_32   (0x100<<6)	/* Clock source */
 #define GPTCR_CLKSOURCE_IPG (0x001<<6)	/* Clock source */
 #define GPTCR_TEN       (1)	/* Timer enable */
-#define GPTPR_VAL	(66)
+
+#define	TIMER_FREQ_HZ	mxc_get_clock(MXC_IPG_CLK)
+
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+	tick *= CONFIG_SYS_HZ;
+	do_div(tick, TIMER_FREQ_HZ);
+
+	return tick;
+}
+
+static inline unsigned long long us_to_tick(unsigned long long usec)
+{
+	usec *= TIMER_FREQ_HZ;
+	do_div(usec, 1000000);
+
+	return usec;
+}
 
 int timer_init(void)
 {
@@ -45,7 +69,7 @@ int timer_init(void)
 	for (i = 0; i < 100; i++)
 		writel(0, &gpt->ctrl);	/* We have no udelay by now */
 
-	writel(GPTPR_VAL, &gpt->pre);
+	writel(0, &gpt->pre);
 	/* Freerun Mode, PERCLK1 input */
 	writel(readl(&gpt->ctrl) |
 		GPTCR_CLKSOURCE_IPG | GPTCR_TEN,
@@ -54,58 +78,59 @@ int timer_init(void)
 	return 0;
 }
 
-void reset_timer_masked(void)
+unsigned long long get_ticks(void)
 {
 	struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR;
+	ulong now = readl(&gpt->counter); /* current tick value */
 
-	writel(0, &gpt->ctrl);
-	/* Freerun Mode, PERCLK1 input */
-	writel(GPTCR_CLKSOURCE_IPG | GPTCR_TEN,
-		&gpt->ctrl);
+	if (now >= lastinc) {
+		/*
+		 * normal mode (non roll)
+		 * move stamp forward with absolut diff ticks
+		 */
+		timestamp += (now - lastinc);
+	} else {
+		/* we have rollover of incrementer */
+		timestamp += (0xFFFFFFFF - lastinc) + now;
+	}
+	lastinc = now;
+	return timestamp;
 }
 
-inline ulong get_timer_masked(void)
+ulong get_timer_masked(void)
 {
-
-	struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR;
-	ulong val = readl(&gpt->counter);
-
-	return val;
+	/*
+	 * get_ticks() returns a long long (64 bit), it wraps in
+	 * 2^64 / CONFIG_MX25_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
+	 * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
+	 * 5 * 10^6 days - long enough.
+	 */
+	return tick_to_time(get_ticks());
 }
 
 ulong get_timer(ulong base)
 {
-	ulong tmp;
+	return get_timer_masked() - base;
+}
 
-	tmp = get_timer_masked();
+/* delay x useconds AND preserve advance timstamp value */
+void __udelay(unsigned long usec)
+{
+	unsigned long long tmp;
+	ulong tmo;
 
-	if (tmp <= (base * 1000)) {
-		/* Overflow */
-		tmp += (0xffffffff -  base);
-	}
+	tmo = us_to_tick(usec);
+	tmp = get_ticks() + tmo;	/* get current timestamp */
 
-	return (tmp / 1000) - base;
+	while (get_ticks() < tmp)	/* loop till event */
+		 /*NOP*/;
 }
 
 /*
- * delay x useconds AND preserve advance timstamp value
- * GPTCNT is now supposed to tick 1 by 1 us.
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
  */
-void __udelay(unsigned long usec)
+ulong get_tbclk(void)
 {
-	ulong tmp;
-
-	tmp = get_timer_masked();	/* get current timestamp */
-
-	/* if setting this forward will roll time stamp */
-	if ((usec + tmp + 1) < tmp) {
-		/* reset "advancing" timestamp to 0, set lastinc value */
-		reset_timer_masked();
-	} else {
-		/* else, set advancing stamp wake up time */
-		tmp += usec;
-	}
-
-	while (get_timer_masked() < tmp)	/* loop till event */
-		 /*NOP*/;
+	return TIMER_FREQ_HZ;
 }

arch/arm/cpu/arm1136/u-boot.lds

@@ -1,89 +0,0 @@
-/*
- * (C) Copyright 2009
- * Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
- *
- * Copyright (C) 2005-2007 Samsung Electronics
- * Kyungin Park <kyugnmin.park@samsung.com>
- *
- * Copyright (c) 2004 Texas Instruments
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text :
-	{
-		arch/arm/cpu/arm1136/start.o	(.text)
-		*(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-	. = ALIGN(4);
-	.data : {
-		*(.data)
-	}
-
-	. = ALIGN(4);
-
-	. = .;
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
-
-	. = ALIGN(4);
-
-	.rel.dyn : {
-		__rel_dyn_start = .;
-		*(.rel*)
-		__rel_dyn_end = .;
-	}
-
-	.dynsym : {
-		__dynsym_start = .;
-		*(.dynsym)
-	}
-
-	_end = .;
-
-	.bss __rel_dyn_start (OVERLAY) : {
-		__bss_start = .;
-		*(.bss)
-		 . = ALIGN(4);
-		__bss_end__ = .;
-	}
-
-	/DISCARD/ : { *(.dynstr*) }
-	/DISCARD/ : { *(.dynamic*) }
-	/DISCARD/ : { *(.plt*) }
-	/DISCARD/ : { *(.interp*) }
-	/DISCARD/ : { *(.gnu*) }
-}

arch/arm/cpu/arm1176/u-boot.lds

@@ -1,78 +0,0 @@
-/*
- * (C) Copyright 2002-2004
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text :
-	{
-		arch/arm/cpu/arm1176/start.o	(.text)
-		*(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-	. = ALIGN(4);
-	.data : {
-		*(.data)
-	}
-
-	. = .;
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
-
-	. = ALIGN(4);
-
-	.rel.dyn : {
-		__rel_dyn_start = .;
-		*(.rel*)
-		__rel_dyn_end = .;
-	}
-
-	.dynsym : {
-		__dynsym_start = .;
-		*(.dynsym)
-	}
-
-	_end = .;
-
-	.bss __rel_dyn_start (OVERLAY) : {
-		__bss_start = .;
-		*(.bss)
-		 . = ALIGN(4);
-		__bss_end__ = .;
-	}
-
-	/DISCARD/ : { *(.dynstr*) }
-	/DISCARD/ : { *(.dynamic*) }
-	/DISCARD/ : { *(.plt*) }
-	/DISCARD/ : { *(.interp*) }
-	/DISCARD/ : { *(.gnu*) }
-}

arch/arm/cpu/arm720t/u-boot.lds

@@ -1,79 +0,0 @@
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text :
-	{
-		arch/arm/cpu/arm720t/start.o	(.text)
-		*(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-	. = ALIGN(4);
-	.data : {
-	}
-
-	. = ALIGN(4);
-
-	. = .;
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
-
-	. = ALIGN(4);
-
-	.rel.dyn : {
-		__rel_dyn_start = .;
-		*(.rel*)
-		__rel_dyn_end = .;
-	}
-
-	.dynsym : {
-		__dynsym_start = .;
-		*(.dynsym)
-	}
-
-	_end = .;
-
-	.bss __rel_dyn_start (OVERLAY) : {
-		__bss_start = .;
-		*(.bss)
-		 . = ALIGN(4);
-		__bss_end__ = .;
-	}
-
-	/DISCARD/ : { *(.dynstr*) }
-	/DISCARD/ : { *(.dynamic*) }
-	/DISCARD/ : { *(.plt*) }
-	/DISCARD/ : { *(.interp*) }
-	/DISCARD/ : { *(.gnu*) }
-}

arch/arm/cpu/arm920t/s3c24x0/timer.c

@@ -35,19 +35,7 @@
 #include <asm/io.h>
 #include <asm/arch/s3c24x0_cpu.h>
 
-int timer_load_val = 0;
-static ulong timer_clk;
-
-/* macro to read the 16 bit timer */
-static inline ulong READ_TIMER(void)
-{
-	struct s3c24x0_timers *timers = s3c24x0_get_base_timers();
-
-	return readl(&timers->tcnto4) & 0xffff;
-}
-
-static ulong timestamp;
-static ulong lastdec;
+DECLARE_GLOBAL_DATA_PTR;
 
 int timer_init(void)
 {
@@ -57,27 +45,27 @@ int timer_init(void)
 	/* use PWM Timer 4 because it has no output */
 	/* prescaler for Timer 4 is 16 */
 	writel(0x0f00, &timers->tcfg0);
-	if (timer_load_val == 0) {
+	if (gd->tbu == 0) {
 		/*
 		 * for 10 ms clock period @ PCLK with 4 bit divider = 1/2
 		 * (default) and prescaler = 16. Should be 10390
 		 * @33.25MHz and 15625 @ 50 MHz
 		 */
-		timer_load_val = get_PCLK() / (2 * 16 * 100);
-		timer_clk = get_PCLK() / (2 * 16);
+		gd->tbu = get_PCLK() / (2 * 16 * 100);
+		gd->timer_rate_hz = get_PCLK() / (2 * 16);
 	}
 	/* load value for 10 ms timeout */
-	lastdec = timer_load_val;
-	writel(timer_load_val, &timers->tcntb4);
+	writel(gd->tbu, &timers->tcntb4);
 	/* auto load, manual update of timer 4 */
 	tmr = (readl(&timers->tcon) & ~0x0700000) | 0x0600000;
 	writel(tmr, &timers->tcon);
 	/* auto load, start timer 4 */
 	tmr = (tmr & ~0x0700000) | 0x0500000;
 	writel(tmr, &timers->tcon);
-	timestamp = 0;
+	gd->lastinc = 0;
+	gd->tbl = 0;
 
-	return (0);
+	return 0;
 }
 
 /*
@@ -94,7 +82,7 @@ void __udelay (unsigned long usec)
 	ulong start = get_ticks();
 
 	tmo = usec / 1000;
-	tmo *= (timer_load_val * 100);
+	tmo *= (gd->tbu * 100);
 	tmo /= 1000;
 
 	while ((ulong) (get_ticks() - start) < tmo)
@@ -105,7 +93,7 @@ ulong get_timer_masked(void)
 {
 	ulong tmr = get_ticks();
 
-	return tmr / (timer_clk / CONFIG_SYS_HZ);
+	return tmr / (gd->timer_rate_hz / CONFIG_SYS_HZ);
 }
 
 void udelay_masked(unsigned long usec)
@@ -116,10 +104,10 @@ void udelay_masked(unsigned long usec)
 
 	if (usec >= 1000) {
 		tmo = usec / 1000;
-		tmo *= (timer_load_val * 100);
+		tmo *= (gd->tbu * 100);
 		tmo /= 1000;
 	} else {
-		tmo = usec * (timer_load_val * 100);
+		tmo = usec * (gd->tbu * 100);
 		tmo /= (1000 * 1000);
 	}
 
@@ -137,18 +125,19 @@ void udelay_masked(unsigned long usec)
  */
 unsigned long long get_ticks(void)
 {
-	ulong now = READ_TIMER();
+	struct s3c24x0_timers *timers = s3c24x0_get_base_timers();
+	ulong now = readl(&timers->tcnto4) & 0xffff;
 
-	if (lastdec >= now) {
+	if (gd->lastinc >= now) {
 		/* normal mode */
-		timestamp += lastdec - now;
+		gd->tbl += gd->lastinc - now;
 	} else {
 		/* we have an overflow ... */
-		timestamp += lastdec + timer_load_val - now;
+		gd->tbl += gd->lastinc + gd->tbu - now;
 	}
-	lastdec = now;
+	gd->lastinc = now;
 
-	return timestamp;
+	return gd->tbl;
 }
 
 /*
@@ -157,20 +146,7 @@ unsigned long long get_ticks(void)
  */
 ulong get_tbclk(void)
 {
-	ulong tbclk;
-
-#if defined(CONFIG_SMDK2400)
-	tbclk = timer_load_val * 100;
-#elif defined(CONFIG_SBC2410X) || \
-      defined(CONFIG_SMDK2410) || \
-	defined(CONFIG_S3C2440) || \
-      defined(CONFIG_VCMA9)
-	tbclk = CONFIG_SYS_HZ;
-#else
-#	error "tbclk not configured"
-#endif
-
-	return tbclk;
+	return CONFIG_SYS_HZ;
 }
 
 /*

arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c

@@ -1057,7 +1057,7 @@ static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
 	pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)",
 		  usb_pipein(pipe));
 #else
-	wait_ms(1);
+	mdelay(1);
 #endif
 	if (usb_pipeint(pipe)) {
 		info("Root-Hub submit IRQ: NOT implemented");
@@ -1260,7 +1260,7 @@ static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
 #ifdef	DEBUG
 	ohci_dump_roothub(&gohci, 1);
 #else
-	wait_ms(1);
+	mdelay(1);
 #endif
 
 	len = min_t(int, len, leni);
@@ -1275,7 +1275,7 @@ static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
 	pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)",
 		  0 /*usb_pipein(pipe) */);
 #else
-	wait_ms(1);
+	mdelay(1);
 #endif
 
 	return stat;
@@ -1302,7 +1302,7 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
 	pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB",
 		  usb_pipein(pipe));
 #else
-	wait_ms(1);
+	mdelay(1);
 #endif
 	if (!maxsize) {
 		err("submit_common_message: pipesize for pipe %lx is zero",
@@ -1316,7 +1316,7 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
 		return -1;
 	}
 
-	wait_ms(10);
+	mdelay(10);
 	/* ohci_dump_status(&gohci); */
 
 	/* allow more time for a BULK device to react - some are slow */
@@ -1351,7 +1351,7 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
 		}
 
 		if (--timeout) {
-			wait_ms(1);
+			mdelay(1);
 			if (!urb_finished)
 				dbg("\%");
 
@@ -1396,7 +1396,7 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
 	pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)",
 		  usb_pipein(pipe));
 #else
-	wait_ms(1);
+	mdelay(1);
 #endif
 
 	/* free TDs in urb_priv */
@@ -1423,7 +1423,7 @@ int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
 	pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB",
 		  usb_pipein(pipe));
 #else
-	wait_ms(1);
+	mdelay(1);
 #endif
 	if (!maxsize) {
 		err("submit_control_message: pipesize for pipe %lx is zero",
@@ -1463,7 +1463,7 @@ static int hc_reset(struct ohci *ohci)
 		writel(OHCI_OCR, &ohci->regs->cmdstatus);
 		info("USB HC TakeOver from SMM");
 		while (readl(&ohci->regs->control) & OHCI_CTRL_IR) {
-			wait_ms(10);
+			mdelay(10);
 			if (--smm_timeout == 0) {
 				err("USB HC TakeOver failed!");
 				return -1;
@@ -1600,7 +1600,7 @@ static int hc_interrupt(void)
 #ifdef	DEBUG
 		ohci_dump(ohci, 1);
 #else
-		wait_ms(1);
+		mdelay(1);
 #endif
 		/* FIXME: be optimistic, hope that bug won't repeat often. */
 		/* Make some non-interrupt context restart the controller. */
@@ -1611,7 +1611,7 @@ static int hc_interrupt(void)
 	}
 
 	if (ints & OHCI_INTR_WDH) {
-		wait_ms(1);
+		mdelay(1);
 
 		writel(OHCI_INTR_WDH, &regs->intrdisable);
 		stat = dl_done_list(&gohci, dl_reverse_done_list(&gohci));
@@ -1627,7 +1627,7 @@ static int hc_interrupt(void)
 	/* FIXME:  this assumes SOF (1/ms) interrupts don't get lost... */
 	if (ints & OHCI_INTR_SF) {
 		unsigned int frame = m16_swap(ohci->hcca->frame_no) & 1;
-		wait_ms(1);
+		mdelay(1);
 		writel(OHCI_INTR_SF, &regs->intrdisable);
 		if (ohci->ed_rm_list[frame] != NULL)
 			writel(OHCI_INTR_SF, &regs->intrenable);
@@ -1718,7 +1718,7 @@ int usb_lowlevel_init(void)
 	/* FIXME this is a second HC reset; why?? */
 	gohci.hc_control = OHCI_USB_RESET;
 	writel(gohci.hc_control, &gohci.regs->control);
-	wait_ms(10);
+	mdelay(10);
 
 	if (hc_start(&gohci) < 0) {
 		err("can't start usb-%s", gohci.slot_name);
@@ -1730,7 +1730,7 @@ int usb_lowlevel_init(void)
 #ifdef	DEBUG
 	ohci_dump(&gohci, 1);
 #else
-	wait_ms(1);
+	mdelay(1);
 #endif
 	ohci_inited = 1;
 	urb_finished = 1;

arch/arm/cpu/arm920t/u-boot.lds

@@ -1,88 +0,0 @@
-/*
- * (c) Copyright 2004
- * Techware Information Technology, Inc.
- * Ming-Len Wu <minglen_wu@techware.com.tw>
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text :
-	{
-		arch/arm/cpu/arm920t/start.o	(.text)
-		*(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-	. = ALIGN(4);
-	.data : {
-		*(.data)
-	}
-
-	. = ALIGN(4);
-
-	. = .;
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
-
-	. = ALIGN(4);
-
-	.rel.dyn : {
-		__rel_dyn_start = .;
-		*(.rel*)
-		__rel_dyn_end = .;
-	}
-
-	.dynsym : {
-		__dynsym_start = .;
-		*(.dynsym)
-	}
-
-	_end = .;
-
-	.bss __rel_dyn_start (OVERLAY) : {
-		__bss_start = .;
-		*(.bss)
-		 . = ALIGN(4);
-		__bss_end__ = .;
-	}
-
-	/DISCARD/ : { *(.dynstr*) }
-	/DISCARD/ : { *(.dynamic*) }
-	/DISCARD/ : { *(.plt*) }
-	/DISCARD/ : { *(.interp*) }
-	/DISCARD/ : { *(.gnu*) }
-}

arch/arm/cpu/arm925t/u-boot.lds

@@ -1,83 +0,0 @@
-/*
- * (C) Copyright 2004
- * Wolfgang Denk, DENX Software Engineering, <wg@denx.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text :
-	{
-		arch/arm/cpu/arm925t/start.o	(.text)
-		*(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-	. = ALIGN(4);
-	.data : {
-		*(.data)
-	}
-
-	. = ALIGN(4);
-
-	. = .;
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
-
-	. = ALIGN(4);
-
-	.rel.dyn : {
-		__rel_dyn_start = .;
-		*(.rel*)
-		__rel_dyn_end = .;
-	}
-
-	.dynsym : {
-		__dynsym_start = .;
-		*(.dynsym)
-	}
-
-	_end = .;
-
-	.bss __rel_dyn_start (OVERLAY) : {
-		__bss_start = .;
-		*(.bss)
-		 . = ALIGN(4);
-		__bss_end__ = .;
-	}
-
-	/DISCARD/ : { *(.dynstr*) }
-	/DISCARD/ : { *(.dynamic*) }
-	/DISCARD/ : { *(.plt*) }
-	/DISCARD/ : { *(.interp*) }
-	/DISCARD/ : { *(.gnu*) }
-}

arch/arm/cpu/arm926ejs/armada100/timer.c

@@ -190,3 +190,21 @@ void reset_cpu (unsigned long ignored)
 
 	while(1);
 }
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{
+	return (ulong)CONFIG_SYS_HZ;
+}

arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c

@@ -196,7 +196,7 @@ void at91_macb_hw_init(void)
 }
 #endif
 
-#if defined(CONFIG_ATMEL_MCI) || defined(CONFIG_GENERIC_ATMEL_MCI)
+#if defined(CONFIG_GENERIC_ATMEL_MCI)
 void at91_mci_hw_init(void)
 {
 	at91_set_a_periph(AT91_PIO_PORTA, 8, 1);	/* MCCK */

arch/arm/cpu/arm926ejs/cache.c

@@ -23,29 +23,71 @@
 #include <common.h>
 
 #ifndef CONFIG_SYS_DCACHE_OFF
-static inline void dcache_noop(void)
-{
-	if (dcache_status()) {
-		puts("WARNING: cache operations are not implemented!\n"
-		     "WARNING: disabling D-Cache now, you can re-enable it"
-		     "later with 'dcache on' command\n");
-		dcache_disable();
-	}
-}
+
+#ifndef CONFIG_SYS_CACHELINE_SIZE
+#define CONFIG_SYS_CACHELINE_SIZE	32
+#endif
 
 void invalidate_dcache_all(void)
 {
-	dcache_noop();
+	asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0));
+}
+
+void flush_dcache_all(void)
+{
+	asm volatile(
+		"0:"
+		"mrc p15, 0, r15, c7, c14, 3\n"
+		"bne 0b\n"
+		"mcr p15, 0, %0, c7, c10, 4\n"
+		 : : "r"(0) : "memory"
+	);
+}
+
+static int check_cache_range(unsigned long start, unsigned long stop)
+{
+	int ok = 1;
+
+	if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
+		ok = 0;
+
+	if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
+		ok = 0;
+
+	if (!ok)
+		debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
+			start, stop);
+
+	return ok;
 }
 
 void invalidate_dcache_range(unsigned long start, unsigned long stop)
 {
-	dcache_noop();
+	if (!check_cache_range(start, stop))
+		return;
+
+	while (start < stop) {
+		asm volatile("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(start));
+		start += CONFIG_SYS_CACHELINE_SIZE;
+	}
 }
 
 void flush_dcache_range(unsigned long start, unsigned long stop)
 {
-	dcache_noop();
+	if (!check_cache_range(start, stop))
+		return;
+
+	while (start < stop) {
+		asm volatile("mcr p15, 0, %0, c7, c14, 1\n" : : "r"(start));
+		start += CONFIG_SYS_CACHELINE_SIZE;
+	}
+
+	asm volatile("mcr p15, 0, %0, c7, c10, 4\n" : : "r"(0));
+}
+
+void flush_cache(unsigned long start, unsigned long size)
+{
+	flush_dcache_range(start, start + size);
 }
 #else /* #ifndef CONFIG_SYS_DCACHE_OFF */
 void invalidate_dcache_all(void)
@@ -64,7 +106,15 @@ void flush_dcache_range(unsigned long start, unsigned long stop)
 {
 }
 
-void  flush_cache(unsigned long start, unsigned long size)
+void flush_cache(unsigned long start, unsigned long size)
 {
 }
 #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+
+/*
+ * Stub implementations for l2 cache operations
+ */
+void __l2_cache_disable(void) {}
+
+void l2_cache_disable(void)
+	__attribute__((weak, alias("__l2_cache_disable")));

arch/arm/cpu/arm926ejs/cpu.c

@@ -50,6 +50,8 @@ int cleanup_before_linux (void)
 	/* turn off I/D-cache */
 	icache_disable();
 	dcache_disable();
+	l2_cache_disable();
+
 	/* flush I/D-cache */
 	cache_flush();
 

arch/arm/cpu/arm926ejs/davinci/Makefile

@@ -38,7 +38,8 @@ COBJS-$(CONFIG_DRIVER_TI_EMAC)	+= lxt972.o dp83848.o et1011c.o ksz8873.o
 
 ifdef CONFIG_SPL_BUILD
 COBJS-y	+= spl.o
-COBJS-y	+= dm365_lowlevel.o
+COBJS-$(CONFIG_SOC_DM365)	+= dm365_lowlevel.o
+COBJS-$(CONFIG_SOC_DA8XX)	+= da850_lowlevel.o
 endif
 
 SOBJS	= reset.o

arch/arm/cpu/arm926ejs/davinci/cpu.c

@@ -25,6 +25,8 @@
 #include <asm/arch/hardware.h>
 #include <asm/io.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* offsets from PLL controller base */
 #define PLLC_PLLCTL	0x100
 #define PLLC_PLLM	0x110
@@ -115,21 +117,8 @@ int clk_get(enum davinci_clk_ids id)
 out:
 	return pll_out;
 }
-#ifdef CONFIG_DISPLAY_CPUINFO
-int print_cpuinfo(void)
-{
-	printf("Cores: ARM %d MHz",
-			clk_get(DAVINCI_ARM_CLKID) / 1000000);
-	printf("\nDDR:   %d MHz\n",
-			/* DDR PHY uses an x2 input clock */
-			clk_get(0x10001) / 1000000);
-	return 0;
-}
-#endif
 #else /* CONFIG_SOC_DA8XX */
 
-#ifdef CONFIG_DISPLAY_CPUINFO
-
 static unsigned pll_div(volatile void *pllbase, unsigned offset)
 {
 	u32	div;
@@ -167,7 +156,7 @@ static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div)
 {
 	volatile void	*pllbase = (volatile void *) pll_addr;
 #ifdef CONFIG_SOC_DM646X
-	unsigned	base = CFG_REFCLK_FREQ / 1000;
+	unsigned	base = CONFIG_REFCLK_FREQ / 1000;
 #else
 	unsigned	base = CONFIG_SYS_HZ_CLOCK / 1000;
 #endif
@@ -185,36 +174,6 @@ static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div)
 	return DIV_ROUND_UP(base, 1000 * pll_div(pllbase, div));
 }
 
-int print_cpuinfo(void)
-{
-	/* REVISIT fetch and display CPU ID and revision information
-	 * too ... that will matter as more revisions appear.
-	 */
-#if defined(CONFIG_SOC_DM365)
-	printf("Cores: ARM %d MHz",
-			pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, ARM_PLLDIV));
-#else
-	printf("Cores: ARM %d MHz",
-			pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV));
-#endif
-
-#ifdef DSP_PLLDIV
-	printf(", DSP %d MHz",
-			pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DSP_PLLDIV));
-#endif
-
-	printf("\nDDR:   %d MHz\n",
-			/* DDR PHY uses an x2 input clock */
-#if defined(CONFIG_SOC_DM365)
-			pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DDR_PLLDIV)
-				/ 2);
-#else
-			pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, DDR_PLLDIV)
-				/ 2);
-#endif
-	return 0;
-}
-
 #ifdef DAVINCI_DM6467EVM
 unsigned int davinci_arm_clk_get()
 {
@@ -228,9 +187,38 @@ unsigned int davinci_clk_get(unsigned int div)
 	return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, div) * 1000000;
 }
 #endif
-#endif /* CONFIG_DISPLAY_CPUINFO */
 #endif /* !CONFIG_SOC_DA8XX */
 
+int set_cpu_clk_info(void)
+{
+#ifdef CONFIG_SOC_DA8XX
+	gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 1000000;
+	/* DDR PHY uses an x2 input clock */
+	gd->bd->bi_ddr_freq = clk_get(0x10001) / 1000000;
+#else
+
+	unsigned int pllbase = DAVINCI_PLL_CNTRL0_BASE;
+#if defined(CONFIG_SOC_DM365)
+	pllbase = DAVINCI_PLL_CNTRL1_BASE;
+#endif
+	gd->bd->bi_arm_freq = pll_sysclk_mhz(pllbase, ARM_PLLDIV);
+
+#ifdef DSP_PLLDIV
+	gd->bd->bi_dsp_freq =
+		pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DSP_PLLDIV);
+#else
+	gd->bd->bi_dsp_freq = 0;
+#endif
+
+	pllbase = DAVINCI_PLL_CNTRL1_BASE;
+#if defined(CONFIG_SOC_DM365)
+	pllbase = DAVINCI_PLL_CNTRL0_BASE;
+#endif
+	gd->bd->bi_ddr_freq = pll_sysclk_mhz(pllbase, DDR_PLLDIV) / 2;
+#endif
+	return 0;
+}
+
 /*
  * Initializes on-chip ethernet controllers.
  * to override, implement board_eth_init()

arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c

@@ -32,6 +32,7 @@
 #include <asm/arch/emif_defs.h>
 #include <asm/arch/pll_defs.h>
 
+#if defined(CONFIG_SYS_DA850_PLL_INIT)
 void da850_waitloop(unsigned long loopcnt)
 {
 	unsigned long	i;
@@ -85,6 +86,13 @@ int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult)
 	/* Enable the PLL from Disable Mode PLLDIS bit to 0 */
 	clrbits_le32(&reg->pllctl, PLLCTL_PLLDIS);
 
+#if defined(CONFIG_SYS_DA850_PLL0_PREDIV)
+	/* program the prediv */
+	if (reg == davinci_pllc0_regs && CONFIG_SYS_DA850_PLL0_PREDIV)
+		writel((PLL_DIVEN | CONFIG_SYS_DA850_PLL0_PREDIV),
+			&reg->prediv);
+#endif
+
 	/* Program the required multiplier value in PLLM */
 	writel(pllmult, &reg->pllm);
 
@@ -156,7 +164,9 @@ int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult)
 
 	return 0;
 }
+#endif /* CONFIG_SYS_DA850_PLL_INIT */
 
+#if defined(CONFIG_SYS_DA850_DDR_INIT)
 int da850_ddr_setup(void)
 {
 	unsigned long	tmp;
@@ -235,6 +245,7 @@ int da850_ddr_setup(void)
 
 	return 0;
 }
+#endif /* CONFIG_SYS_DA850_DDR_INIT */
 
 __attribute__((weak))
 void board_gpio_init(void)
@@ -242,10 +253,6 @@ void board_gpio_init(void)
 	return;
 }
 
-/* pinmux_resource[] vector is defined in the board specific file */
-extern const struct pinmux_resource pinmuxes[];
-extern const int pinmuxes_size;
-
 int arch_cpu_init(void)
 {
 	/* Unlock kick registers */
@@ -259,13 +266,11 @@ int arch_cpu_init(void)
 	if (davinci_configure_pin_mux_items(pinmuxes, pinmuxes_size))
 		return 1;
 
+#if defined(CONFIG_SYS_DA850_PLL_INIT)
 	/* PLL setup */
 	da850_pll_init(davinci_pllc0_regs, CONFIG_SYS_DA850_PLL0_PLLM);
 	da850_pll_init(davinci_pllc1_regs, CONFIG_SYS_DA850_PLL1_PLLM);
-
-	/* GPIO setup */
-	board_gpio_init();
-
+#endif
 	/* setup CSn config */
 #if defined(CONFIG_SYS_DA850_CS2CFG)
 	writel(CONFIG_SYS_DA850_CS2CFG, &davinci_emif_regs->ab1cr);
@@ -274,7 +279,12 @@ int arch_cpu_init(void)
 	writel(CONFIG_SYS_DA850_CS3CFG, &davinci_emif_regs->ab2cr);
 #endif
 
-	lpsc_on(CONFIG_SYS_DA850_LPSC_UART);
+	da8xx_configure_lpsc_items(lpsc, lpsc_size);
+
+	/* GPIO setup */
+	board_gpio_init();
+
+
 	NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1),
 			CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
 
@@ -286,6 +296,9 @@ int arch_cpu_init(void)
 		DAVINCI_UART_PWREMU_MGMT_UTRST),
 	       &davinci_uart2_ctrl_regs->pwremu_mgmt);
 
+#if defined(CONFIG_SYS_DA850_DDR_INIT)
 	da850_ddr_setup();
+#endif
+
 	return 0;
 }

arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c

@@ -254,7 +254,7 @@ int dm365_ddr_setup(void)
 	return 0;
 }
 
-void dm365_vpss_sync_reset(void)
+static void dm365_vpss_sync_reset(void)
 {
 	unsigned int PdNum = 0;
 
@@ -276,11 +276,52 @@ void dm365_vpss_sync_reset(void)
 		;
 }
 
-void dm365_por_reset(void)
+static void dm365_por_reset(void)
 {
+	struct davinci_timer *wdog =
+		(struct davinci_timer *)DAVINCI_WDOG_BASE;
+
 	if (readl(&dv_pll0_regs->rstype) &
-		(PLL_RSTYPE_POR | PLL_RSTYPE_XWRST))
+		(PLL_RSTYPE_POR | PLL_RSTYPE_XWRST)) {
 		dm365_vpss_sync_reset();
+
+		writel(DV_TMPBUF_VAL, TMPBUF);
+		setbits_le32(TMPSTATUS, FLAG_PORRST);
+		writel(DV_WDT_ENABLE_SYS_RESET, &wdog->na1);
+		writel(DV_WDT_TRIGGER_SYS_RESET, &wdog->na2);
+
+		while (1);
+	}
+}
+
+static void dm365_wdt_reset(void)
+{
+	struct davinci_timer *wdog =
+		(struct davinci_timer *)DAVINCI_WDOG_BASE;
+
+	if (readl(TMPBUF) != DV_TMPBUF_VAL) {
+		writel(DV_TMPBUF_VAL, TMPBUF);
+		setbits_le32(TMPSTATUS, FLAG_PORRST);
+		setbits_le32(TMPSTATUS, FLAG_FLGOFF);
+
+		dm365_waitloop(100);
+
+		dm365_vpss_sync_reset();
+
+		writel(DV_WDT_ENABLE_SYS_RESET, &wdog->na1);
+		writel(DV_WDT_TRIGGER_SYS_RESET, &wdog->na2);
+
+		while (1);
+	}
+}
+
+static void dm365_wdt_flag_on(void)
+{
+	/* VPSS_CLKMD 1:2 */
+	clrbits_le32(&dv_sys_module_regs->vpss_clkctl,
+		VPSS_CLK_CTL_VPSS_CLKMD);
+	writel(0, TMPBUF);
+	setbits_le32(TMPSTATUS, FLAG_FLGON);
 }
 
 void dm365_psc_init(void)
@@ -382,6 +423,9 @@ void dm36x_lowlevel_init(ulong bootflag)
 	writel(0xffffffff, &dv_aintc_regs->irq0);
 	writel(0xffffffff, &dv_aintc_regs->irq1);
 
+	dm365_por_reset();
+	dm365_wdt_reset();
+
 	/* System PSC setup - enable all */
 	dm365_psc_init();
 
@@ -418,6 +462,8 @@ void dm36x_lowlevel_init(ulong bootflag)
 	puts("emif init\n");
 	dm365_emif_init();
 
+	dm365_wdt_flag_on();
+
 #if defined(CONFIG_POST)
 	/*
 	 * Do memory tests, calls arch_memory_failure_handle()

arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S

@@ -49,6 +49,7 @@
 
 .globl	lowlevel_init
 lowlevel_init:
+#ifdef CONFIG_SOC_DM644X
 
 	/*-------------------------------------------------------*
 	 * Mask all IRQs by setting all bits in the EINT default *
@@ -707,3 +708,6 @@ DDR2_START_ADDR:
 	.word	0x80000000
 DUMMY_VAL:
 	.word	0xa55aa55a
+#else /* CONFIG_SOC_DM644X */
+	mov pc, lr
+#endif

arch/arm/cpu/arm926ejs/davinci/misc.c

@@ -101,9 +101,10 @@ void davinci_emac_mii_mode_sel(int mode_sel)
 void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr)
 {
 	uint8_t env_enetaddr[6];
+	int ret;
 
-	eth_getenv_enetaddr_by_index("eth", 0, env_enetaddr);
-	if (!memcmp(env_enetaddr, "\0\0\0\0\0\0", 6)) {
+	ret = eth_getenv_enetaddr_by_index("eth", 0, env_enetaddr);
+	if (ret) {
 		/*
 		 * There is no MAC address in the environment, so we
 		 * initialize it from the value in the EEPROM.
@@ -111,8 +112,10 @@ void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr)
 		debug("### Setting environment from EEPROM MAC address = "
 			"\"%pM\"\n",
 			env_enetaddr);
-		eth_setenv_enetaddr("ethaddr", rom_enetaddr);
+		ret = !eth_setenv_enetaddr("ethaddr", rom_enetaddr);
 	}
+	if (!ret)
+		printf("Failed to set mac address from EEPROM\n");
 }
 #endif	/* CONFIG_DRIVER_TI_EMAC */
 

arch/arm/cpu/arm926ejs/davinci/spl.c

@@ -26,6 +26,17 @@
 #include <nand.h>
 #include <asm/arch/dm365_lowlevel.h>
 #include <ns16550.h>
+#include <malloc.h>
+#include <spi_flash.h>
+
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+
+DECLARE_GLOBAL_DATA_PTR;
+/* Define global data structure pointer to it*/
+static gd_t gdata __attribute__ ((section(".data")));
+static bd_t bdata __attribute__ ((section(".data")));
+
+#else
 
 void puts(const char *str)
 {
@@ -41,6 +52,8 @@ void putc(char c)
 	NS16550_putc((NS16550_t)(CONFIG_SYS_NS16550_COM1), c);
 }
 
+#endif /* CONFIG_SPL_LIBCOMMON_SUPPORT */
+
 inline void hang(void)
 {
 	puts("### ERROR ### Please RESET the board ###\n");
@@ -50,14 +63,34 @@ inline void hang(void)
 
 void board_init_f(ulong dummy)
 {
+#ifdef CONFIG_SOC_DM365
 	dm36x_lowlevel_init(0);
+#endif
+#ifdef CONFIG_SOC_DA8XX
+	arch_cpu_init();
+#endif
 	relocate_code(CONFIG_SPL_STACK, NULL, CONFIG_SPL_TEXT_BASE);
 }
 
 void board_init_r(gd_t *id, ulong dummy)
 {
-
+#ifdef CONFIG_SPL_NAND_LOAD
 	nand_init();
 	puts("Nand boot...\n");
 	nand_boot();
+#endif
+#ifdef CONFIG_SPL_SPI_LOAD
+	mem_malloc_init(CONFIG_SYS_TEXT_BASE - CONFIG_SYS_MALLOC_LEN,
+			CONFIG_SYS_MALLOC_LEN);
+
+	gd = &gdata;
+	gd->bd = &bdata;
+	gd->flags |= GD_FLG_RELOC;
+	gd->baudrate = CONFIG_BAUDRATE;
+	serial_init();          /* serial communications setup */
+	gd->have_console = 1;
+
+	puts("SPI boot...\n");
+	spi_boot();
+#endif
 }

arch/arm/cpu/arm926ejs/kirkwood/Makefile

@@ -30,6 +30,7 @@ COBJS-y	= cpu.o
 COBJS-y	+= dram.o
 COBJS-y	+= mpp.o
 COBJS-y	+= timer.o
+COBJS-y	+= cache.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))

arch/arm/cpu/arm926ejs/kirkwood/cache.c

@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2012 Michael Walle
+ * Michael Walle <michael@walle.cc>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+#include <common.h>
+#include <asm/arch/cpu.h>
+
+#define FEROCEON_EXTRA_FEATURE_L2C_EN (1<<22)
+
+void l2_cache_disable()
+{
+	u32 ctrl;
+
+	ctrl = readfr_extra_feature_reg();
+	ctrl &= ~FEROCEON_EXTRA_FEATURE_L2C_EN;
+	writefr_extra_feature_reg(ctrl);
+}

arch/arm/cpu/arm926ejs/kirkwood/cpu.c

@@ -226,12 +226,7 @@ static void kw_sysrst_action(void)
 	}
 
 	debug("Starting %s process...\n", __FUNCTION__);
-#if !defined(CONFIG_SYS_HUSH_PARSER)
-	ret = run_command (s, 0);
-#else
-	ret = parse_string_outer(s, FLAG_PARSE_SEMICOLON
-				  | FLAG_EXIT_FROM_LOOP);
-#endif
+	ret = run_command(s, 0);
 	if (ret < 0)
 		debug("Error.. %s failed\n", __FUNCTION__);
 	else

arch/arm/cpu/arm926ejs/kirkwood/timer.c

@@ -153,3 +153,21 @@ int timer_init(void)
 
 	return 0;
 }
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{
+	return (ulong)CONFIG_SYS_HZ;
+}

arch/arm/cpu/arm926ejs/mx25/generic.c

@@ -312,7 +312,7 @@ void mx25_fec_init_pins(void)
 
 }
 
-void imx_get_mac_from_fuse(unsigned char *mac)
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 {
 	int i;
 	struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;

arch/arm/cpu/arm926ejs/mx27/generic.c

@@ -23,6 +23,7 @@
 #include <netdev.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
 #ifdef CONFIG_MXC_MMC
 #include <asm/arch/mxcmmc.h>
 #endif
@@ -34,7 +35,7 @@
  *  f = 2 * f_ref * --------------------
  *                        pd + 1
  */
-unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
+static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
 {
 	unsigned int mfi = (pll >> 10) & 0xf;
 	unsigned int mfn = pll & 0x3ff;
@@ -64,7 +65,7 @@ static ulong clk_in_26m(void)
 	}
 }
 
-ulong imx_get_mpllclk(void)
+static ulong imx_get_mpllclk(void)
 {
 	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
 	ulong cscr = readl(&pll->cscr);
@@ -78,7 +79,7 @@ ulong imx_get_mpllclk(void)
 	return imx_decode_pll(readl(&pll->mpctl0), fref);
 }
 
-ulong imx_get_armclk(void)
+static ulong imx_get_armclk(void)
 {
 	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
 	ulong cscr = readl(&pll->cscr);
@@ -93,7 +94,7 @@ ulong imx_get_armclk(void)
 	return lldiv(fref, div);
 }
 
-ulong imx_get_ahbclk(void)
+static ulong imx_get_ahbclk(void)
 {
 	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
 	ulong cscr = readl(&pll->cscr);
@@ -105,7 +106,7 @@ ulong imx_get_ahbclk(void)
 	return lldiv(fref * 2, 3 * div);
 }
 
-ulong imx_get_spllclk(void)
+static __attribute__((unused)) ulong imx_get_spllclk(void)
 {
 	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
 	ulong cscr = readl(&pll->cscr);
@@ -124,34 +125,50 @@ static ulong imx_decode_perclk(ulong div)
 	return lldiv((imx_get_mpllclk() * 2), (div * 3));
 }
 
-ulong imx_get_perclk1(void)
+static ulong imx_get_perclk1(void)
 {
 	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
 
 	return imx_decode_perclk((readl(&pll->pcdr1) & 0x3f) + 1);
 }
 
-ulong imx_get_perclk2(void)
+static ulong imx_get_perclk2(void)
 {
 	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
 
 	return imx_decode_perclk(((readl(&pll->pcdr1) >> 8) & 0x3f) + 1);
 }
 
-ulong imx_get_perclk3(void)
+static __attribute__((unused)) ulong imx_get_perclk3(void)
 {
 	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
 
 	return imx_decode_perclk(((readl(&pll->pcdr1) >> 16) & 0x3f) + 1);
 }
 
-ulong imx_get_perclk4(void)
+static __attribute__((unused)) ulong imx_get_perclk4(void)
 {
 	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
 
 	return imx_decode_perclk(((readl(&pll->pcdr1) >> 24) & 0x3f) + 1);
 }
 
+unsigned int mxc_get_clock(enum mxc_clock clk)
+{
+	switch (clk) {
+	case MXC_ARM_CLK:
+		return imx_get_armclk();
+	case MXC_UART_CLK:
+		return imx_get_perclk1();
+	case MXC_FEC_CLK:
+		return imx_get_ahbclk();
+	case MXC_ESDHC_CLK:
+		return imx_get_perclk2();
+	}
+	return -1;
+}
+
+
 #if defined(CONFIG_DISPLAY_CPUINFO)
 int print_cpuinfo (void)
 {
@@ -314,7 +331,7 @@ void mx27_fec_init_pins(void)
 		imx_gpio_mode(mode[i]);
 }
 
-void imx_get_mac_from_fuse(unsigned char *mac)
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 {
 	int i;
 	struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;

arch/arm/cpu/arm926ejs/mx27/timer.c

@@ -171,3 +171,8 @@ void __udelay(unsigned long usec)
 	while (get_ticks() < tmp)	/* loop till event */
 		 /*NOP*/;
 }
+
+ulong get_tbclk(void)
+{
+	return CONFIG_MX27_CLK32;
+}

arch/arm/cpu/arm926ejs/mx28/clock.c

@@ -46,8 +46,8 @@ static uint32_t mx28_get_pclk(void)
 	struct mx28_clkctrl_regs *clkctrl_regs =
 		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
 
-	uint32_t clkctrl, clkseq, clkfrac;
-	uint32_t frac, div;
+	uint32_t clkctrl, clkseq, div;
+	uint8_t clkfrac, frac;
 
 	clkctrl = readl(&clkctrl_regs->hw_clkctrl_cpu);
 
@@ -67,8 +67,8 @@ static uint32_t mx28_get_pclk(void)
 	}
 
 	/* REF Path */
-	clkfrac = readl(&clkctrl_regs->hw_clkctrl_frac0);
-	frac = clkfrac & CLKCTRL_FRAC0_CPUFRAC_MASK;
+	clkfrac = readb(&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU]);
+	frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK;
 	div = clkctrl & CLKCTRL_CPU_DIV_CPU_MASK;
 	return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
 }
@@ -96,8 +96,8 @@ static uint32_t mx28_get_emiclk(void)
 	struct mx28_clkctrl_regs *clkctrl_regs =
 		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
 
-	uint32_t frac, div;
-	uint32_t clkctrl, clkseq, clkfrac;
+	uint32_t clkctrl, clkseq, div;
+	uint8_t clkfrac, frac;
 
 	clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq);
 	clkctrl = readl(&clkctrl_regs->hw_clkctrl_emi);
@@ -109,11 +109,9 @@ static uint32_t mx28_get_emiclk(void)
 		return XTAL_FREQ_MHZ / div;
 	}
 
-	clkfrac = readl(&clkctrl_regs->hw_clkctrl_frac0);
-
 	/* REF Path */
-	frac = (clkfrac & CLKCTRL_FRAC0_EMIFRAC_MASK) >>
-		CLKCTRL_FRAC0_EMIFRAC_OFFSET;
+	clkfrac = readb(&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_EMI]);
+	frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK;
 	div = clkctrl & CLKCTRL_EMI_DIV_EMI_MASK;
 	return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
 }
@@ -123,8 +121,8 @@ static uint32_t mx28_get_gpmiclk(void)
 	struct mx28_clkctrl_regs *clkctrl_regs =
 		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
 
-	uint32_t frac, div;
-	uint32_t clkctrl, clkseq, clkfrac;
+	uint32_t clkctrl, clkseq, div;
+	uint8_t clkfrac, frac;
 
 	clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq);
 	clkctrl = readl(&clkctrl_regs->hw_clkctrl_gpmi);
@@ -135,11 +133,9 @@ static uint32_t mx28_get_gpmiclk(void)
 		return XTAL_FREQ_MHZ / div;
 	}
 
-	clkfrac = readl(&clkctrl_regs->hw_clkctrl_frac1);
-
 	/* REF Path */
-	frac = (clkfrac & CLKCTRL_FRAC1_GPMIFRAC_MASK) >>
-		CLKCTRL_FRAC1_GPMIFRAC_OFFSET;
+	clkfrac = readb(&clkctrl_regs->hw_clkctrl_frac1[CLKCTRL_FRAC1_GPMI]);
+	frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK;
 	div = clkctrl & CLKCTRL_GPMI_DIV_MASK;
 	return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
 }
@@ -152,11 +148,12 @@ void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq)
 	struct mx28_clkctrl_regs *clkctrl_regs =
 		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
 	uint32_t div;
+	int io_reg;
 
 	if (freq == 0)
 		return;
 
-	if (io > MXC_IOCLK1)
+	if ((io < MXC_IOCLK0) || (io > MXC_IOCLK1))
 		return;
 
 	div = (PLL_FREQ_KHZ * PLL_FREQ_COEF) / freq;
@@ -167,23 +164,13 @@ void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq)
 	if (div > 35)
 		div = 35;
 
-	if (io == MXC_IOCLK0) {
-		writel(CLKCTRL_FRAC0_CLKGATEIO0,
-			&clkctrl_regs->hw_clkctrl_frac0_set);
-		clrsetbits_le32(&clkctrl_regs->hw_clkctrl_frac0,
-				CLKCTRL_FRAC0_IO0FRAC_MASK,
-				div << CLKCTRL_FRAC0_IO0FRAC_OFFSET);
-		writel(CLKCTRL_FRAC0_CLKGATEIO0,
-			&clkctrl_regs->hw_clkctrl_frac0_clr);
-	} else {
-		writel(CLKCTRL_FRAC0_CLKGATEIO1,
-			&clkctrl_regs->hw_clkctrl_frac0_set);
-		clrsetbits_le32(&clkctrl_regs->hw_clkctrl_frac0,
-				CLKCTRL_FRAC0_IO1FRAC_MASK,
-				div << CLKCTRL_FRAC0_IO1FRAC_OFFSET);
-		writel(CLKCTRL_FRAC0_CLKGATEIO1,
-			&clkctrl_regs->hw_clkctrl_frac0_clr);
-	}
+	io_reg = CLKCTRL_FRAC0_IO0 - io;	/* Register order is reversed */
+	writeb(CLKCTRL_FRAC_CLKGATE,
+		&clkctrl_regs->hw_clkctrl_frac0_set[io_reg]);
+	writeb(CLKCTRL_FRAC_CLKGATE | (div & CLKCTRL_FRAC_FRAC_MASK),
+		&clkctrl_regs->hw_clkctrl_frac0[io_reg]);
+	writeb(CLKCTRL_FRAC_CLKGATE,
+		&clkctrl_regs->hw_clkctrl_frac0_clr[io_reg]);
 }
 
 /*
@@ -193,19 +180,16 @@ static uint32_t mx28_get_ioclk(enum mxs_ioclock io)
 {
 	struct mx28_clkctrl_regs *clkctrl_regs =
 		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
-	uint32_t tmp, ret;
+	uint8_t ret;
+	int io_reg;
 
-	if (io > MXC_IOCLK1)
+	if ((io < MXC_IOCLK0) || (io > MXC_IOCLK1))
 		return 0;
 
-	tmp = readl(&clkctrl_regs->hw_clkctrl_frac0);
+	io_reg = CLKCTRL_FRAC0_IO0 - io;	/* Register order is reversed */
 
-	if (io == MXC_IOCLK0)
-		ret = (tmp & CLKCTRL_FRAC0_IO0FRAC_MASK) >>
-			CLKCTRL_FRAC0_IO0FRAC_OFFSET;
-	else
-		ret = (tmp & CLKCTRL_FRAC0_IO1FRAC_MASK) >>
-			CLKCTRL_FRAC0_IO1FRAC_OFFSET;
+	ret = readb(&clkctrl_regs->hw_clkctrl_frac0[io_reg]) &
+		CLKCTRL_FRAC_FRAC_MASK;
 
 	return (PLL_FREQ_KHZ * PLL_FREQ_COEF) / ret;
 }
@@ -223,7 +207,7 @@ void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)
 		return;
 
 	clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) +
-			(ssp * sizeof(struct mx28_register));
+			(ssp * sizeof(struct mx28_register_32));
 
 	clrbits_le32(clkreg, CLKCTRL_SSP_CLKGATE);
 	while (readl(clkreg) & CLKCTRL_SSP_CLKGATE)
@@ -272,7 +256,7 @@ static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp)
 		return XTAL_FREQ_KHZ;
 
 	clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) +
-			(ssp * sizeof(struct mx28_register));
+			(ssp * sizeof(struct mx28_register_32));
 
 	tmp = readl(clkreg) & CLKCTRL_SSP_DIV_MASK;
 

arch/arm/cpu/arm926ejs/mx28/iomux.c

@@ -43,7 +43,7 @@ int mxs_iomux_setup_pad(iomux_cfg_t pad)
 {
 	u32 reg, ofs, bp, bm;
 	void *iomux_base = (void *)MXS_PINCTRL_BASE;
-	struct mx28_register *mxs_reg;
+	struct mx28_register_32 *mxs_reg;
 
 	/* muxsel */
 	ofs = 0x100;
@@ -70,7 +70,7 @@ int mxs_iomux_setup_pad(iomux_cfg_t pad)
 	/* vol */
 	if (PAD_VOL_VALID(pad)) {
 		bp = PAD_PIN(pad) % 8 * 4 + 2;
-		mxs_reg = (struct mx28_register *)(iomux_base + ofs);
+		mxs_reg = (struct mx28_register_32 *)(iomux_base + ofs);
 		if (PAD_VOL(pad))
 			writel(1 << bp, &mxs_reg->reg_set);
 		else
@@ -82,7 +82,7 @@ int mxs_iomux_setup_pad(iomux_cfg_t pad)
 		ofs = PULL_OFFSET;
 		ofs += PAD_BANK(pad) * 0x10;
 		bp = PAD_PIN(pad);
-		mxs_reg = (struct mx28_register *)(iomux_base + ofs);
+		mxs_reg = (struct mx28_register_32 *)(iomux_base + ofs);
 		if (PAD_PULL(pad))
 			writel(1 << bp, &mxs_reg->reg_set);
 		else

arch/arm/cpu/arm926ejs/mx28/mx28.c

@@ -30,6 +30,7 @@
 #include <asm/errno.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
+#include <asm/arch/dma.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/iomux.h>
 #include <asm/arch/imx-regs.h>
@@ -63,7 +64,17 @@ void reset_cpu(ulong ignored)
 		;
 }
 
-int mx28_wait_mask_set(struct mx28_register *reg, uint32_t mask, int timeout)
+void enable_caches(void)
+{
+#ifndef CONFIG_SYS_ICACHE_OFF
+	icache_enable();
+#endif
+#ifndef CONFIG_SYS_DCACHE_OFF
+	dcache_enable();
+#endif
+}
+
+int mx28_wait_mask_set(struct mx28_register_32 *reg, uint32_t mask, int timeout)
 {
 	while (--timeout) {
 		if ((readl(&reg->reg) & mask) == mask)
@@ -74,7 +85,7 @@ int mx28_wait_mask_set(struct mx28_register *reg, uint32_t mask, int timeout)
 	return !timeout;
 }
 
-int mx28_wait_mask_clr(struct mx28_register *reg, uint32_t mask, int timeout)
+int mx28_wait_mask_clr(struct mx28_register_32 *reg, uint32_t mask, int timeout)
 {
 	while (--timeout) {
 		if ((readl(&reg->reg) & mask) == 0)
@@ -85,7 +96,7 @@ int mx28_wait_mask_clr(struct mx28_register *reg, uint32_t mask, int timeout)
 	return !timeout;
 }
 
-int mx28_reset_block(struct mx28_register *reg)
+int mx28_reset_block(struct mx28_register_32 *reg)
 {
 	/* Clear SFTRST */
 	writel(MX28_BLOCK_SFTRST, &reg->reg_clr);
@@ -162,6 +173,11 @@ int arch_cpu_init(void)
 	 */
 	mxs_gpio_init();
 
+#ifdef	CONFIG_APBH_DMA
+	/* Start APBH DMA */
+	mxs_dma_init();
+#endif
+
 	return 0;
 }
 #endif
@@ -169,7 +185,8 @@ int arch_cpu_init(void)
 #if defined(CONFIG_DISPLAY_CPUINFO)
 int print_cpuinfo(void)
 {
-	printf("Freescale i.MX28 family\n");
+	printf("Freescale i.MX28 family at %d MHz\n",
+			mxc_get_clock(MXC_ARM_CLK) / 1000000);
 	return 0;
 }
 #endif
@@ -214,6 +231,73 @@ int cpu_eth_init(bd_t *bis)
 }
 #endif
 
+static void __mx28_adjust_mac(int dev_id, unsigned char *mac)
+{
+	mac[0] = 0x00;
+	mac[1] = 0x04; /* Use FSL vendor MAC address by default */
+
+	if (dev_id == 1) /* Let MAC1 be MAC0 + 1 by default */
+		mac[5] += 1;
+}
+
+void mx28_adjust_mac(int dev_id, unsigned char *mac)
+	__attribute__((weak, alias("__mx28_adjust_mac")));
+
+#ifdef	CONFIG_MX28_FEC_MAC_IN_OCOTP
+
+#define	MXS_OCOTP_MAX_TIMEOUT	1000000
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+{
+	struct mx28_ocotp_regs *ocotp_regs =
+		(struct mx28_ocotp_regs *)MXS_OCOTP_BASE;
+	uint32_t data;
+
+	memset(mac, 0, 6);
+
+	writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set);
+
+	if (mx28_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
+				MXS_OCOTP_MAX_TIMEOUT)) {
+		printf("MXS FEC: Can't get MAC from OCOTP\n");
+		return;
+	}
+
+	data = readl(&ocotp_regs->hw_ocotp_cust0);
+
+	mac[2] = (data >> 24) & 0xff;
+	mac[3] = (data >> 16) & 0xff;
+	mac[4] = (data >> 8) & 0xff;
+	mac[5] = data & 0xff;
+	mx28_adjust_mac(dev_id, mac);
+}
+#else
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+{
+	memset(mac, 0, 6);
+}
+#endif
+
+int mx28_dram_init(void)
+{
+	struct mx28_digctl_regs *digctl_regs =
+		(struct mx28_digctl_regs *)MXS_DIGCTL_BASE;
+	uint32_t sz[2];
+
+	sz[0] = readl(&digctl_regs->hw_digctl_scratch0);
+	sz[1] = readl(&digctl_regs->hw_digctl_scratch1);
+
+	if (sz[0] != sz[1]) {
+		printf("MX28:\n"
+			"Error, the RAM size in HW_DIGCTRL_SCRATCH0 and\n"
+			"HW_DIGCTRL_SCRATCH1 is not the same. Please\n"
+			"verify these two registers contain valid RAM size!\n");
+		hang();
+	}
+
+	gd->ram_size = sz[0];
+	return 0;
+}
+
 U_BOOT_CMD(
 	clocks,	CONFIG_SYS_MAXARGS, 1, do_mx28_showclocks,
 	"display clocks",

arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c

@@ -32,44 +32,54 @@
 #include "mx28_init.h"
 
 uint32_t dram_vals[] = {
-	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-	0x00000000, 0x00000000, 0x00000100, 0x00000000, 0x00000000,
-	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-	0x00000000, 0x00010101, 0x01010101, 0x000f0f01, 0x0f02020a,
-	0x00000000, 0x00010101, 0x00000100, 0x00000100, 0x00000000,
-	0x00000002, 0x01010000, 0x05060302, 0x06005003, 0x0a0000c8,
-	0x02009c40, 0x0000030c, 0x0036a609, 0x031a0612, 0x02030202,
-	0x00c8001c, 0x00000000, 0x00000000, 0x00012100, 0xffff0303,
-	0x00012100, 0xffff0303, 0x00012100, 0xffff0303, 0x00012100,
-	0xffff0303, 0x00000003, 0x00000000, 0x00000000, 0x00000000,
-	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-	0x00000000, 0x00000612, 0x01000F02, 0x06120612, 0x00000200,
-	0x00020007, 0xf5014b27, 0xf5014b27, 0xf5014b27, 0xf5014b27,
-	0x07000300, 0x07000300, 0x07000300, 0x07000300, 0x00000006,
-	0x00000000, 0x00000000, 0x01000000, 0x01020408, 0x08040201,
-	0x000f1133, 0x00000000, 0x00001f04, 0x00001f04, 0x00001f04,
-	0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04,
-	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-	0x00000000, 0x00000000, 0x00010000, 0x00020304, 0x00000004,
-	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-	0x00000000, 0x01010000, 0x01000000, 0x03030000, 0x00010303,
-	0x01020202, 0x00000000, 0x02040303, 0x21002103, 0x00061200,
-	0x06120612, 0x04320432, 0x04320432, 0x00040004, 0x00040004,
-	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00010001
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000100, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00010101, 0x01010101,
+	0x000f0f01, 0x0f02010a, 0x00000000, 0x00010101,
+	0x00000100, 0x00000100, 0x00000000, 0x00000002,
+	0x01010000, 0x05060302, 0x06005003, 0x0a0000c8,
+	0x02009c40, 0x0000030c, 0x0036a609, 0x031a0612,
+	0x02030202, 0x00c8001c, 0x00000000, 0x00000000,
+	0x00012100, 0xffff0303, 0x00012100, 0xffff0303,
+	0x00012100, 0xffff0303, 0x00012100, 0xffff0303,
+	0x00000003, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000612, 0x01000F02,
+	0x06120612, 0x00000200, 0x00020007, 0xf5014b27,
+	0xf5014b27, 0xf5014b27, 0xf5014b27, 0x07000300,
+	0x07000300, 0x07000300, 0x07000300, 0x00000006,
+	0x00000000, 0x00000000, 0x01000000, 0x01020408,
+	0x08040201, 0x000f1133, 0x00000000, 0x00001f04,
+	0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04,
+	0x00001f04, 0x00001f04, 0x00001f04, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00010000, 0x00020304,
+	0x00000004, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x01010000,
+	0x01000000, 0x03030000, 0x00010303, 0x01020202,
+	0x00000000, 0x02040303, 0x21002103, 0x00061200,
+	0x06120612, 0x04320432, 0x04320432, 0x00040004,
+	0x00040004, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00010001
 };
 
 void init_m28_200mhz_ddr2(void)
@@ -86,22 +96,20 @@ void mx28_mem_init_clock(void)
 		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
 
 	/* Gate EMI clock */
-	writel(CLKCTRL_FRAC0_CLKGATEEMI,
-		&clkctrl_regs->hw_clkctrl_frac0_set);
+	writeb(CLKCTRL_FRAC_CLKGATE,
+		&clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_EMI]);
 
-	/* EMI = 205MHz */
-	writel(CLKCTRL_FRAC0_EMIFRAC_MASK,
-		&clkctrl_regs->hw_clkctrl_frac0_set);
-	writel((0x2a << CLKCTRL_FRAC0_EMIFRAC_OFFSET) &
-		CLKCTRL_FRAC0_EMIFRAC_MASK,
-		&clkctrl_regs->hw_clkctrl_frac0_clr);
+	/* Set fractional divider for ref_emi to 480 * 18 / 21 = 411MHz */
+	writeb(CLKCTRL_FRAC_CLKGATE | (21 & CLKCTRL_FRAC_FRAC_MASK),
+		&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_EMI]);
 
 	/* Ungate EMI clock */
-	writel(CLKCTRL_FRAC0_CLKGATEEMI,
-		&clkctrl_regs->hw_clkctrl_frac0_clr);
+	writeb(CLKCTRL_FRAC_CLKGATE,
+		&clkctrl_regs->hw_clkctrl_frac0_clr[CLKCTRL_FRAC0_EMI]);
 
 	early_delay(11000);
 
+	/* Set EMI clock divider for EMI clock to 411 / 2 = 205MHz */
 	writel((2 << CLKCTRL_EMI_DIV_EMI_OFFSET) |
 		(1 << CLKCTRL_EMI_DIV_XTAL_OFFSET),
 		&clkctrl_regs->hw_clkctrl_emi);
@@ -118,10 +126,10 @@ void mx28_mem_setup_cpu_and_hbus(void)
 	struct mx28_clkctrl_regs *clkctrl_regs =
 		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
 
-	/* CPU = 454MHz and ungate CPU clock */
-	clrsetbits_le32(&clkctrl_regs->hw_clkctrl_frac0,
-		CLKCTRL_FRAC0_CPUFRAC_MASK | CLKCTRL_FRAC0_CLKGATECPU,
-		19 << CLKCTRL_FRAC0_CPUFRAC_OFFSET);
+	/* Set fractional divider for ref_cpu to 480 * 18 / 19 = 454MHz
+	 * and ungate CPU clock */
+	writeb(19 & CLKCTRL_FRAC_FRAC_MASK,
+		(uint8_t *)&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU]);
 
 	/* Set CPU bypass */
 	writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
@@ -165,26 +173,22 @@ void mx28_mem_setup_vddd(void)
 		&power_regs->hw_power_vdddctrl);
 }
 
-#define	HW_DIGCTRL_SCRATCH0	0x8001c280
-#define	HW_DIGCTRL_SCRATCH1	0x8001c290
-void data_abort_memdetect_handler(void) __attribute__((naked));
-void data_abort_memdetect_handler(void)
-{
-	asm volatile("subs pc, r14, #4");
-}
-
 void mx28_mem_get_size(void)
 {
+	struct mx28_digctl_regs *digctl_regs =
+		(struct mx28_digctl_regs *)MXS_DIGCTL_BASE;
 	uint32_t sz, da;
 	uint32_t *vt = (uint32_t *)0x20;
+	/* The following is "subs pc, r14, #4", used as return from DABT. */
+	const uint32_t data_abort_memdetect_handler = 0xe25ef004;
 
 	/* Replace the DABT handler. */
 	da = vt[4];
-	vt[4] = (uint32_t)&data_abort_memdetect_handler;
+	vt[4] = data_abort_memdetect_handler;
 
 	sz = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
-	writel(sz, HW_DIGCTRL_SCRATCH0);
-	writel(sz, HW_DIGCTRL_SCRATCH1);
+	writel(sz, &digctl_regs->hw_digctl_scratch0);
+	writel(sz, &digctl_regs->hw_digctl_scratch1);
 
 	/* Restore the old DABT handler. */
 	vt[4] = da;

arch/arm/cpu/arm926ejs/mx28/spl_power_init.c

@@ -240,8 +240,8 @@ void mx28_enable_4p2_dcdc_input(int xfer)
 		clrbits_le32(&power_regs->hw_power_minpwr, POWER_MINPWR_PWD_BO);
 
 	while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ)
-		clrbits_le32(&power_regs->hw_power_ctrl,
-				POWER_CTRL_VBUS_VALID_IRQ);
+		writel(POWER_CTRL_VBUS_VALID_IRQ,
+			&power_regs->hw_power_ctrl_clr);
 
 	if (prev_5v_brnout) {
 		writel(POWER_5VCTRL_PWDN_5VBRNOUT,
@@ -256,8 +256,8 @@ void mx28_enable_4p2_dcdc_input(int xfer)
 	}
 
 	while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VDD5V_DROOP_IRQ)
-		clrbits_le32(&power_regs->hw_power_ctrl,
-				POWER_CTRL_VDD5V_DROOP_IRQ);
+		writel(POWER_CTRL_VDD5V_DROOP_IRQ,
+			&power_regs->hw_power_ctrl_clr);
 
 	if (prev_5v_droop)
 		clrbits_le32(&power_regs->hw_power_ctrl,
@@ -726,8 +726,10 @@ void mx28_power_set_vddio(uint32_t new_target, uint32_t new_brownout)
 			clrsetbits_le32(&power_regs->hw_power_vddioctrl,
 				POWER_VDDIOCTRL_TRG_MASK, diff);
 
-			if (powered_by_linreg)
-				early_delay(1500);
+			if (powered_by_linreg ||
+				(readl(&power_regs->hw_power_sts) &
+					POWER_STS_VDD5V_GT_VDDIO))
+				early_delay(500);
 			else {
 				while (!(readl(&power_regs->hw_power_sts) &
 					POWER_STS_DC_OK))
@@ -761,8 +763,10 @@ void mx28_power_set_vddio(uint32_t new_target, uint32_t new_brownout)
 			clrsetbits_le32(&power_regs->hw_power_vddioctrl,
 				POWER_VDDIOCTRL_TRG_MASK, diff);
 
-			if (powered_by_linreg)
-				early_delay(1500);
+			if (powered_by_linreg ||
+				(readl(&power_regs->hw_power_sts) &
+					POWER_STS_VDD5V_GT_VDDIO))
+				early_delay(500);
 			else {
 				while (!(readl(&power_regs->hw_power_sts) &
 					POWER_STS_DC_OK))
@@ -819,8 +823,10 @@ void mx28_power_set_vddd(uint32_t new_target, uint32_t new_brownout)
 			clrsetbits_le32(&power_regs->hw_power_vdddctrl,
 				POWER_VDDDCTRL_TRG_MASK, diff);
 
-			if (powered_by_linreg)
-				early_delay(1500);
+			if (powered_by_linreg ||
+				(readl(&power_regs->hw_power_sts) &
+					POWER_STS_VDD5V_GT_VDDIO))
+				early_delay(500);
 			else {
 				while (!(readl(&power_regs->hw_power_sts) &
 					POWER_STS_DC_OK))
@@ -854,8 +860,10 @@ void mx28_power_set_vddd(uint32_t new_target, uint32_t new_brownout)
 			clrsetbits_le32(&power_regs->hw_power_vdddctrl,
 					POWER_VDDDCTRL_TRG_MASK, diff);
 
-			if (powered_by_linreg)
-				early_delay(1500);
+			if (powered_by_linreg ||
+				(readl(&power_regs->hw_power_sts) &
+					POWER_STS_VDD5V_GT_VDDIO))
+				early_delay(500);
 			else {
 				while (!(readl(&power_regs->hw_power_sts) &
 					POWER_STS_DC_OK))

arch/arm/cpu/arm926ejs/mx28/start.S

@@ -40,12 +40,6 @@
 #include <common.h>
 #include <version.h>
 
-#if defined(CONFIG_OMAP1610)
-#include <./configs/omap1510.h>
-#elif defined(CONFIG_OMAP730)
-#include <./configs/omap730.h>
-#endif
-
 /*
  *************************************************************************
  *
@@ -173,10 +167,15 @@ _reset:
 	 */
 	push	{r0-r12,r14}
 
+	/* save control register c1 */
+	mrc	p15, 0, r0, c1, c0, 0
+	push	{r0}
+
 	/*
-	 * set the cpu to SVC32 mode
+	 * set the cpu to SVC32 mode and store old CPSR register content
 	 */
 	mrs	r0,cpsr
+	push	{r0}
 	bic	r0,r0,#0x1f
 	orr	r0,r0,#0xd3
 	msr	cpsr,r0
@@ -191,6 +190,20 @@ _reset:
 
 	bl	board_init_ll
 
+	/*
+	 * restore bootrom's cpu mode (especially FIQ)
+	 */
+	pop	{r0}
+	msr	cpsr,r0
+
+	/*
+	 * restore c1 register
+	 * (especially set exception vector location back to
+	 * bootrom space which is required by bootrom for USB boot)
+	 */
+	pop	{r0}
+	mcr	p15, 0, r0, c1, c0, 0
+
 	pop	{r0-r12,r14}
 	bx	lr
 

arch/arm/cpu/arm926ejs/mx28/timer.c

@@ -82,7 +82,7 @@ int timer_init(void)
 	return 0;
 }
 
-ulong get_timer(ulong base)
+unsigned long long get_ticks(void)
 {
 	struct mx28_timrot_regs *timrot_regs =
 		(struct mx28_timrot_regs *)MXS_TIMROT_BASE;
@@ -103,7 +103,17 @@ ulong get_timer(ulong base)
 	}
 	lastdec = now;
 
-	return tick_to_time(timestamp) - base;
+	return timestamp;
+}
+
+ulong get_timer_masked(void)
+{
+	return tick_to_time(get_ticks());
+}
+
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
 }
 
 /* We use the HW_DIGCTL_MICROSECONDS register for sub-millisecond timer. */
@@ -139,3 +149,8 @@ void __udelay(unsigned long usec)
 		old = new;
 	}
 }
+
+ulong get_tbclk(void)
+{
+	return MX28_INCREMENTER_HZ;
+}

arch/arm/cpu/arm926ejs/nomadik/timer.c

@@ -75,3 +75,13 @@ void __udelay(unsigned long usec)
 	while ((signed)(end - READ_TIMER()) > 0)
 		;
 }
+
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+ulong get_tbclk(void)
+{
+	return CONFIG_SYS_HZ;
+}

arch/arm/cpu/arm926ejs/orion5x/timer.c

@@ -167,3 +167,21 @@ void timer_init_r(void)
 	lastdec = read_timer();
 	timestamp = 0;
 }
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{
+	return (ulong)CONFIG_SYS_HZ;
+}

arch/arm/cpu/arm926ejs/pantheon/timer.c

@@ -197,3 +197,21 @@ void reset_cpu (unsigned long ignored)
 	/*enable functional WDT clock */
 	writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr);
 }
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{
+	return (ulong)CONFIG_SYS_HZ;
+}

arch/arm/cpu/arm926ejs/start.S

@@ -194,7 +194,9 @@ reset:
 	 * we do sys-critical inits only at reboot,
 	 * not when booting from ram!
 	 */
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
 	bl	cpu_init_crit
+#endif
 
 /* Set stackpointer in internal RAM to call board_init_f */
 call_board_init_f:
@@ -353,33 +355,45 @@ _dynsym_start_ofs:
  *
  *************************************************************************
  */
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
 cpu_init_crit:
 	/*
-	 * flush v4 I/D caches
+	 * flush D cache before disabling it
 	 */
 	mov	r0, #0
-	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
-	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
+flush_dcache:
+	mrc	p15, 0, r15, c7, c10, 3
+	bne	flush_dcache
+
+	mcr	p15, 0, r0, c8, c7, 0	/* invalidate TLB */
+	mcr	p15, 0, r0, c7, c5, 0	/* invalidate I Cache */
 
 	/*
-	 * disable MMU stuff and caches
+	 * disable MMU and D cache
+	 * enable I cache if CONFIG_SYS_ICACHE_OFF is not defined
 	 */
 	mrc	p15, 0, r0, c1, c0, 0
-	bic	r0, r0, #0x00002300	/* clear bits 13, 9:8 (--V- --RS) */
+	bic	r0, r0, #0x00000300	/* clear bits 9:8 (---- --RS) */
 	bic	r0, r0, #0x00000087	/* clear bits 7, 2:0 (B--- -CAM) */
+#ifdef CONFIG_SYS_EXCEPTION_VECTORS_HIGH
+	orr	r0, r0, #0x00002000	/* set bit 13 (--V- ----) */
+#else
+	bic	r0, r0, #0x00002000	/* clear bit 13 (--V- ----) */
+#endif
 	orr	r0, r0, #0x00000002	/* set bit 2 (A) Align */
+#ifndef CONFIG_SYS_ICACHE_OFF
 	orr	r0, r0, #0x00001000	/* set bit 12 (I) I-Cache */
+#endif
 	mcr	p15, 0, r0, c1, c0, 0
 
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
 	/*
 	 * Go setup Memory and board specific bits prior to relocation.
 	 */
 	mov	ip, lr		/* perserve link reg across call */
 	bl	lowlevel_init	/* go setup pll,mux,memory */
 	mov	lr, ip		/* restore link */
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
 	mov	pc, lr		/* back to my caller */
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
 
 #ifndef CONFIG_SPL_BUILD
 /*

arch/arm/cpu/arm926ejs/u-boot.lds

@@ -1,80 +0,0 @@
-/*
- * (C) Copyright 2002-2004
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text :
-	{
-		arch/arm/cpu/arm926ejs/start.o	(.text)
-		*(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-	. = ALIGN(4);
-	.data : {
-		*(.data)
-	}
-
-	. = ALIGN(4);
-
-	. = .;
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
-
-	. = ALIGN(4);
-
-	.rel.dyn : {
-		__rel_dyn_start = .;
-		*(.rel*)
-		__rel_dyn_end = .;
-	}
-
-	.dynsym : {
-		__dynsym_start = .;
-		*(.dynsym)
-	}
-
-	_end = .;
-
-	.bss __rel_dyn_start (OVERLAY) : {
-		__bss_start = .;
-		*(.bss)
-		 . = ALIGN(4);
-		__bss_end__ = .;
-	}
-
-	/DISCARD/ : { *(.dynstr*) }
-	/DISCARD/ : { *(.dynamic*) }
-	/DISCARD/ : { *(.plt*) }
-	/DISCARD/ : { *(.interp*) }
-	/DISCARD/ : { *(.gnu*) }
-}

arch/arm/cpu/arm_intcm/u-boot.lds

@@ -1,80 +0,0 @@
-/*
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text :
-	{
-		arch/arm/cpu/arm_intcm/start.o	(.text)
-		*(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-	. = ALIGN(4);
-	.data : {
-		*(.data)
-	}
-
-	. = ALIGN(4);
-
-	. = .;
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
-
-	. = ALIGN(4);
-
-	.rel.dyn : {
-		__rel_dyn_start = .;
-		*(.rel*)
-		__rel_dyn_end = .;
-	}
-
-	.dynsym : {
-		__dynsym_start = .;
-		*(.dynsym)
-	}
-
-	_end = .;
-
-	.bss __rel_dyn_start (OVERLAY) : {
-		__bss_start = .;
-		*(.bss)
-		 . = ALIGN(4);
-		__bss_end__ = .;
-	}
-
-	/DISCARD/ : { *(.dynstr*) }
-	/DISCARD/ : { *(.dynamic*) }
-	/DISCARD/ : { *(.plt*) }
-	/DISCARD/ : { *(.interp*) }
-	/DISCARD/ : { *(.gnu*) }
-}

arch/arm/cpu/armv7/Makefile

@@ -27,9 +27,7 @@ LIB	= $(obj)lib$(CPU).o
 
 START	:= start.o
 
-ifndef CONFIG_SPL_BUILD
 COBJS	+= cache_v7.o
-endif
 
 COBJS	+= cpu.o
 COBJS	+= syslib.o

arch/arm/cpu/armv7/am33xx/Makefile

@@ -16,8 +16,6 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(SOC).o
 
-SOBJS	:= lowlevel_init.o
-
 COBJS	+= clock.o
 COBJS	+= sys_info.o
 COBJS	+= ddr.o

arch/arm/cpu/armv7/am33xx/board.c

@@ -19,19 +19,31 @@
 #include <common.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
 #include <asm/arch/ddr_defs.h>
 #include <asm/arch/clock.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/common_def.h>
 #include <asm/io.h>
+#include <asm/omap_common.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
-struct timer_reg *timerreg = (struct timer_reg *)DM_TIMER2_BASE;
+struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE;
+struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
+
+/* UART Defines */
+#ifdef CONFIG_SPL_BUILD
+#define UART_RESET		(0x1 << 1)
+#define UART_CLK_RUNNING_MASK	0x1
+#define UART_SMART_IDLE_EN	(0x1 << 0x3)
+#endif
 
 /*
  * early system init of muxing and clocks.
  */
-void s_init(u32 in_ddr)
+void s_init(void)
 {
 	/* WDT1 is already running when the bootloader gets control
 	 * Disable it to avoid "random" resets
@@ -43,24 +55,62 @@ void s_init(u32 in_ddr)
 	while (readl(&wdtimer->wdtwwps) != 0x0)
 		;
 
+#ifdef CONFIG_SPL_BUILD
 	/* Setup the PLLs and the clocks for the peripherals */
-#ifdef CONFIG_SETUP_PLL
 	pll_init();
+
+	/* UART softreset */
+	u32 regVal;
+
+	enable_uart0_pin_mux();
+
+	regVal = readl(&uart_base->uartsyscfg);
+	regVal |= UART_RESET;
+	writel(regVal, &uart_base->uartsyscfg);
+	while ((readl(&uart_base->uartsyssts) &
+		UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
+		;
+
+	/* Disable smart idle */
+	regVal = readl(&uart_base->uartsyscfg);
+	regVal |= UART_SMART_IDLE_EN;
+	writel(regVal, &uart_base->uartsyscfg);
+
+	/* Initialize the Timer */
+	init_timer();
+
+	preloader_console_init();
+
+	config_ddr();
 #endif
-	if (!in_ddr)
-		config_ddr();
+
+	/* Enable MMC0 */
+	enable_mmc0_pin_mux();
 }
 
 /* Initialize timer */
 void init_timer(void)
 {
 	/* Reset the Timer */
-	writel(0x2, (&timerreg->tsicrreg));
+	writel(0x2, (&timer_base->tscir));
 
 	/* Wait until the reset is done */
-	while (readl(&timerreg->tiocpcfgreg) & 1)
+	while (readl(&timer_base->tiocp_cfg) & 1)
 		;
 
 	/* Start the Timer */
-	writel(0x1, (&timerreg->tclrreg));
+	writel(0x1, (&timer_base->tclr));
+}
+
+#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
+int board_mmc_init(bd_t *bis)
+{
+	return omap_mmc_init(0);
+}
+#endif
+
+void setup_clocks_for_console(void)
+{
+	/* Not yet implemented */
+	return;
 }

arch/arm/cpu/armv7/am33xx/clock.c

@@ -101,10 +101,23 @@ static void enable_per_clocks(void)
 	while (readl(&cmper->timer2clkctrl) != PRCM_MOD_EN)
 		;
 
+	/* Select the Master osc 24 MHZ as Timer2 clock source */
+	writel(0x1, &cmdpll->clktimer2clk);
+
 	/* UART0 */
 	writel(PRCM_MOD_EN, &cmwkup->wkup_uart0ctrl);
 	while (readl(&cmwkup->wkup_uart0ctrl) != PRCM_MOD_EN)
 		;
+
+	/* MMC0*/
+	writel(PRCM_MOD_EN, &cmper->mmc0clkctrl);
+	while (readl(&cmper->mmc0clkctrl) != PRCM_MOD_EN)
+		;
+
+	/* i2c0 */
+	writel(PRCM_MOD_EN, &cmwkup->wkup_i2c0ctrl);
+	while (readl(&cmwkup->wkup_i2c0ctrl) != PRCM_MOD_EN)
+		;
 }
 
 static void mpu_pll_config(void)

arch/arm/cpu/armv7/am33xx/config.mk

@@ -0,0 +1,18 @@
+#
+# Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed "as is" WITHOUT ANY WARRANTY of any
+# kind, whether express or implied; without even the implied warranty
+# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+ifdef CONFIG_SPL_BUILD
+ALL-y	+= $(OBJTREE)/MLO
+else
+ALL-y	+= $(obj)u-boot.img
+endif

arch/arm/cpu/armv7/am33xx/emif4.c

@@ -46,7 +46,7 @@ void dram_init_banksize(void)
 }
 
 
-#ifdef CONFIG_AM335X_CONFIG_DDR
+#ifdef CONFIG_SPL_BUILD
 static void data_macro_config(int dataMacroNum)
 {
 	struct ddr_data data;

arch/arm/cpu/armv7/am33xx/lowlevel_init.S

@@ -1,72 +0,0 @@
-/*
- * lowlevel_init.S
- *
- * AM33XX low level initialization.
- *
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
- *
- * Initial Code by:
- * Mansoor Ahamed  <mansoor.ahamed@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <config.h>
-#include <asm/arch/hardware.h>
-
-_mark1:
-	.word mark1
-_lowlevel_init1:
-	.word lowlevel_init
-_s_init_start:
-	.word s_init_start
-
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE	/* sdram load addr from config.mk */
-
-/*****************************************************************************
- * lowlevel_init: - Platform low level init.
- ****************************************************************************/
-.globl lowlevel_init
-lowlevel_init:
-
-	/* The link register is saved in ip by start.S */
-	mov r6, ip
-	/* check if we are already running from RAM */
-	ldr r2, _lowlevel_init1
-	ldr r3, _TEXT_BASE
-	sub r4, r2, r3
-	sub r0, pc, r4
-	ldr sp, SRAM_STACK
-mark1:
-	ldr r5, _mark1
-	sub r5, r5, r2 /* bytes between mark1 and lowlevel_init */
-	sub r0, r0, r5 /* r0 <- _start w.r.t current place of execution */
-	mov r10, #0x0 /* r10 has in_ddr used by s_init() */
-
-	ands r0, r0, #0xC0000000
-	/* MSB 2 bits <> 0 then we are in ocmc or DDR */
-	cmp r0, #0x80000000
-	bne s_init_start
-	mov r10, #0x01
-	b s_init_start
-
-s_init_start:
-	mov r0, r10 /* passing in_ddr in r0 */
-	bl s_init
-	/* back to arch calling code */
-	mov pc, r6
-	/* the literal pools origin */
-	.ltorg
-
-SRAM_STACK:
-	/* Place stack at the top */
-	.word LOW_LEVEL_SRAM_STACK

arch/arm/cpu/armv7/config.mk

@@ -31,3 +31,6 @@ PLATFORM_CPPFLAGS += -march=armv5
 # =========================================================================
 PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
 PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
+ifneq ($(CONFIG_IMX_CONFIG),)
+ALL-y	+= $(obj)u-boot.imx
+endif

arch/arm/cpu/armv7/cpu.c

@@ -52,7 +52,9 @@ int cleanup_before_linux(void)
 	 *
 	 * we turn off caches etc ...
 	 */
+#ifndef CONFIG_SPL_BUILD
 	disable_interrupts();
+#endif
 
 	/*
 	 * Turn off I-cache and invalidate it

arch/arm/cpu/armv7/exynos/clock.c

@@ -26,10 +26,6 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/clk.h>
 
-#ifndef CONFIG_SYS_CLK_FREQ_C210
-#define CONFIG_SYS_CLK_FREQ_C210	24000000
-#endif
-
 /* exynos4: return pll clock frequency */
 static unsigned long exynos4_get_pll_clk(int pllreg)
 {
@@ -76,7 +72,73 @@ static unsigned long exynos4_get_pll_clk(int pllreg)
 	/* SDIV [2:0] */
 	s = r & 0x7;
 
-	freq = CONFIG_SYS_CLK_FREQ_C210;
+	freq = CONFIG_SYS_CLK_FREQ;
+
+	if (pllreg == EPLL) {
+		k = k & 0xffff;
+		/* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
+		fout = (m + k / 65536) * (freq / (p * (1 << s)));
+	} else if (pllreg == VPLL) {
+		k = k & 0xfff;
+		/* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */
+		fout = (m + k / 1024) * (freq / (p * (1 << s)));
+	} else {
+		if (s < 1)
+			s = 1;
+		/* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
+		fout = m * (freq / (p * (1 << (s - 1))));
+	}
+
+	return fout;
+}
+
+/* exynos5: return pll clock frequency */
+static unsigned long exynos5_get_pll_clk(int pllreg)
+{
+	struct exynos5_clock *clk =
+		(struct exynos5_clock *)samsung_get_base_clock();
+	unsigned long r, m, p, s, k = 0, mask, fout;
+	unsigned int freq;
+
+	switch (pllreg) {
+	case APLL:
+		r = readl(&clk->apll_con0);
+		break;
+	case MPLL:
+		r = readl(&clk->mpll_con0);
+		break;
+	case EPLL:
+		r = readl(&clk->epll_con0);
+		k = readl(&clk->epll_con1);
+		break;
+	case VPLL:
+		r = readl(&clk->vpll_con0);
+		k = readl(&clk->vpll_con1);
+		break;
+	default:
+		printf("Unsupported PLL (%d)\n", pllreg);
+		return 0;
+	}
+
+	/*
+	 * APLL_CON: MIDV [25:16]
+	 * MPLL_CON: MIDV [25:16]
+	 * EPLL_CON: MIDV [24:16]
+	 * VPLL_CON: MIDV [24:16]
+	 */
+	if (pllreg == APLL || pllreg == MPLL)
+		mask = 0x3ff;
+	else
+		mask = 0x1ff;
+
+	m = (r >> 16) & mask;
+
+	/* PDIV [13:8] */
+	p = (r >> 8) & 0x3f;
+	/* SDIV [2:0] */
+	s = r & 0x7;
+
+	freq = CONFIG_SYS_CLK_FREQ;
 
 	if (pllreg == EPLL) {
 		k = k & 0xffff;
@@ -102,17 +164,42 @@ static unsigned long exynos4_get_arm_clk(void)
 	struct exynos4_clock *clk =
 		(struct exynos4_clock *)samsung_get_base_clock();
 	unsigned long div;
-	unsigned long dout_apll;
-	unsigned int apll_ratio;
+	unsigned long armclk;
+	unsigned int core_ratio;
+	unsigned int core2_ratio;
 
 	div = readl(&clk->div_cpu0);
 
-	/* APLL_RATIO: [26:24] */
-	apll_ratio = (div >> 24) & 0x7;
+	/* CORE_RATIO: [2:0], CORE2_RATIO: [30:28] */
+	core_ratio = (div >> 0) & 0x7;
+	core2_ratio = (div >> 28) & 0x7;
 
-	dout_apll = get_pll_clk(APLL) / (apll_ratio + 1);
+	armclk = get_pll_clk(APLL) / (core_ratio + 1);
+	armclk /= (core2_ratio + 1);
 
-	return dout_apll;
+	return armclk;
+}
+
+/* exynos5: return ARM clock frequency */
+static unsigned long exynos5_get_arm_clk(void)
+{
+	struct exynos5_clock *clk =
+		(struct exynos5_clock *)samsung_get_base_clock();
+	unsigned long div;
+	unsigned long armclk;
+	unsigned int arm_ratio;
+	unsigned int arm2_ratio;
+
+	div = readl(&clk->div_cpu0);
+
+	/* ARM_RATIO: [2:0], ARM2_RATIO: [30:28] */
+	arm_ratio = (div >> 0) & 0x7;
+	arm2_ratio = (div >> 28) & 0x7;
+
+	armclk = get_pll_clk(APLL) / (arm_ratio + 1);
+	armclk /= (arm2_ratio + 1);
+
+	return armclk;
 }
 
 /* exynos4: return pwm clock frequency */
@@ -158,6 +245,27 @@ static unsigned long exynos4_get_pwm_clk(void)
 	return pclk;
 }
 
+/* exynos5: return pwm clock frequency */
+static unsigned long exynos5_get_pwm_clk(void)
+{
+	struct exynos5_clock *clk =
+		(struct exynos5_clock *)samsung_get_base_clock();
+	unsigned long pclk, sclk;
+	unsigned int ratio;
+
+	/*
+	 * CLK_DIV_PERIC3
+	 * PWM_RATIO [3:0]
+	 */
+	ratio = readl(&clk->div_peric3);
+	ratio = ratio & 0xf;
+	sclk = get_pll_clk(MPLL);
+
+	pclk = sclk / (ratio + 1);
+
+	return pclk;
+}
+
 /* exynos4: return uart clock frequency */
 static unsigned long exynos4_get_uart_clk(int dev_index)
 {
@@ -205,6 +313,53 @@ static unsigned long exynos4_get_uart_clk(int dev_index)
 	return uclk;
 }
 
+/* exynos5: return uart clock frequency */
+static unsigned long exynos5_get_uart_clk(int dev_index)
+{
+	struct exynos5_clock *clk =
+		(struct exynos5_clock *)samsung_get_base_clock();
+	unsigned long uclk, sclk;
+	unsigned int sel;
+	unsigned int ratio;
+
+	/*
+	 * CLK_SRC_PERIC0
+	 * UART0_SEL [3:0]
+	 * UART1_SEL [7:4]
+	 * UART2_SEL [8:11]
+	 * UART3_SEL [12:15]
+	 * UART4_SEL [16:19]
+	 * UART5_SEL [23:20]
+	 */
+	sel = readl(&clk->src_peric0);
+	sel = (sel >> (dev_index << 2)) & 0xf;
+
+	if (sel == 0x6)
+		sclk = get_pll_clk(MPLL);
+	else if (sel == 0x7)
+		sclk = get_pll_clk(EPLL);
+	else if (sel == 0x8)
+		sclk = get_pll_clk(VPLL);
+	else
+		return 0;
+
+	/*
+	 * CLK_DIV_PERIC0
+	 * UART0_RATIO [3:0]
+	 * UART1_RATIO [7:4]
+	 * UART2_RATIO [8:11]
+	 * UART3_RATIO [12:15]
+	 * UART4_RATIO [16:19]
+	 * UART5_RATIO [23:20]
+	 */
+	ratio = readl(&clk->div_peric0);
+	ratio = (ratio >> (dev_index << 2)) & 0xf;
+
+	uclk = sclk / (ratio + 1);
+
+	return uclk;
+}
+
 /* exynos4: set the mmc clock */
 static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
 {
@@ -232,27 +387,69 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
 	writel(val, addr);
 }
 
+/* exynos5: set the mmc clock */
+static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
+{
+	struct exynos5_clock *clk =
+		(struct exynos5_clock *)samsung_get_base_clock();
+	unsigned int addr;
+	unsigned int val;
+
+	/*
+	 * CLK_DIV_FSYS1
+	 * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
+	 * CLK_DIV_FSYS2
+	 * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
+	 */
+	if (dev_index < 2) {
+		addr = (unsigned int)&clk->div_fsys1;
+	} else {
+		addr = (unsigned int)&clk->div_fsys2;
+		dev_index -= 2;
+	}
+
+	val = readl(addr);
+	val &= ~(0xff << ((dev_index << 4) + 8));
+	val |= (div & 0xff) << ((dev_index << 4) + 8);
+	writel(val, addr);
+}
+
 unsigned long get_pll_clk(int pllreg)
 {
-	return exynos4_get_pll_clk(pllreg);
+	if (cpu_is_exynos5())
+		return exynos5_get_pll_clk(pllreg);
+	else
+		return exynos4_get_pll_clk(pllreg);
 }
 
 unsigned long get_arm_clk(void)
 {
-	return exynos4_get_arm_clk();
+	if (cpu_is_exynos5())
+		return exynos5_get_arm_clk();
+	else
+		return exynos4_get_arm_clk();
 }
 
 unsigned long get_pwm_clk(void)
 {
-	return exynos4_get_pwm_clk();
+	if (cpu_is_exynos5())
+		return exynos5_get_pwm_clk();
+	else
+		return exynos4_get_pwm_clk();
 }
 
 unsigned long get_uart_clk(int dev_index)
 {
-	return exynos4_get_uart_clk(dev_index);
+	if (cpu_is_exynos5())
+		return exynos5_get_uart_clk(dev_index);
+	else
+		return exynos4_get_uart_clk(dev_index);
 }
 
 void set_mmc_clk(int dev_index, unsigned int div)
 {
-	exynos4_set_mmc_clk(dev_index, div);
+	if (cpu_is_exynos5())
+		exynos5_set_mmc_clk(dev_index, div);
+	else
+		exynos4_set_mmc_clk(dev_index, div);
 }

arch/arm/cpu/armv7/highbank/Makefile

@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(SOC).o
 
-COBJS	:= timer.o
+COBJS	:= timer.o bootcount.o
 SOBJS	:=
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)

arch/arm/cpu/armv7/highbank/bootcount.c

@@ -0,0 +1,36 @@
+/*
+ * Copyright 2011 Calxeda, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_BOOTCOUNT_LIMIT
+void bootcount_store(ulong a)
+{
+	writel((BOOTCOUNT_MAGIC & 0xffff0000) | a, CONFIG_SYS_BOOTCOUNT_ADDR);
+}
+
+ulong bootcount_load(void)
+{
+	u32 tmp = readl(CONFIG_SYS_BOOTCOUNT_ADDR);
+
+	if ((tmp & 0xffff0000) != (BOOTCOUNT_MAGIC & 0xffff0000))
+		return 0;
+	else
+		return tmp & 0x0000ffff;
+}
+#endif

arch/arm/cpu/armv7/highbank/config.mk

@@ -0,0 +1 @@
+PLATFORM_CPPFLAGS += -march=armv7-a

arch/arm/cpu/armv7/highbank/timer.c

@@ -66,10 +66,10 @@ static inline unsigned long long time_to_tick(unsigned long long time)
 
 static inline unsigned long long us_to_tick(unsigned long long us)
 {
-	unsigned long long tick = us << 16;
+	unsigned long long tick = us * 1000;
 	tick += NS_PER_TICK - 1;
 	do_div(tick, NS_PER_TICK);
-	return tick >> 16;
+	return tick;
 }
 
 unsigned long long get_ticks(void)
@@ -121,3 +121,8 @@ ulong get_timer_masked(void)
 {
 	return tick_to_time(get_ticks());
 }
+
+ulong get_tbclk(void)
+{
+	return CONFIG_SYS_HZ;
+}

arch/arm/cpu/armv7/imx-common/cpu.c

@@ -44,6 +44,7 @@ static char *get_reset_cause(void)
 
 	switch (cause) {
 	case 0x00001:
+	case 0x00011:
 		return "POR";
 	case 0x00004:
 		return "CSU";
@@ -63,13 +64,33 @@ static char *get_reset_cause(void)
 }
 
 #if defined(CONFIG_DISPLAY_CPUINFO)
+
+static char *get_imx_type(u32 imxtype)
+{
+	switch (imxtype) {
+	case 0x63:
+		return "6Q";	/* Quad-core version of the mx6 */
+	case 0x61:
+		return "6DS";	/* Dual/Solo version of the mx6 */
+	case 0x60:
+		return "6SL";	/* Solo-Lite version of the mx6 */
+	case 0x51:
+		return "51";
+	case 0x53:
+		return "53";
+	default:
+		return "unknown";
+	}
+}
+
 int print_cpuinfo(void)
 {
 	u32 cpurev;
 
 	cpurev = get_cpu_rev();
-	printf("CPU:   Freescale i.MX%x family rev%d.%d at %d MHz\n",
-		(cpurev & 0xFF000) >> 12,
+
+	printf("CPU:   Freescale i.MX%s rev%d.%d at %d MHz\n",
+		get_imx_type((cpurev & 0xFF000) >> 12),
 		(cpurev & 0x000F0) >> 4,
 		(cpurev & 0x0000F) >> 0,
 		mxc_get_clock(MXC_ARM_CLK) / 1000000);

arch/arm/cpu/armv7/imx-common/timer.c

@@ -25,6 +25,7 @@
 
 #include <common.h>
 #include <asm/io.h>
+#include <div64.h>
 #include <asm/arch/imx-regs.h>
 
 /* General purpose timers registers */
@@ -50,6 +51,22 @@ DECLARE_GLOBAL_DATA_PTR;
 #define timestamp (gd->tbl)
 #define lastinc (gd->lastinc)
 
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+	tick *= CONFIG_SYS_HZ;
+	do_div(tick, CLK_32KHZ);
+
+	return tick;
+}
+
+static inline unsigned long long us_to_tick(unsigned long long usec)
+{
+	usec *= CLK_32KHZ;
+	do_div(usec, 1000000);
+
+	return usec;
+}
+
 int timer_init(void)
 {
 	int i;
@@ -75,17 +92,33 @@ int timer_init(void)
 	return 0;
 }
 
+unsigned long long get_ticks(void)
+{
+	ulong now = __raw_readl(&cur_gpt->counter); /* current tick value */
+
+	if (now >= lastinc) {
+		/*
+		 * normal mode (non roll)
+		 * move stamp forward with absolut diff ticks
+		 */
+		timestamp += (now - lastinc);
+	} else {
+		/* we have rollover of incrementer */
+		timestamp += (0xFFFFFFFF - lastinc) + now;
+	}
+	lastinc = now;
+	return timestamp;
+}
+
 ulong get_timer_masked(void)
 {
-	ulong val = __raw_readl(&cur_gpt->counter);
-	val /= (CLK_32KHZ / CONFIG_SYS_HZ);
-	if (val >= lastinc)
-		timestamp += (val - lastinc);
-	else
-		timestamp += ((0xFFFFFFFF / (CLK_32KHZ / CONFIG_SYS_HZ))
-				- lastinc) + val;
-	lastinc = val;
-	return timestamp;
+	/*
+	 * get_ticks() returns a long long (64 bit), it wraps in
+	 * 2^64 / CONFIG_MX25_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
+	 * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
+	 * 5 * 10^6 days - long enough.
+	 */
+	return tick_to_time(get_ticks());
 }
 
 ulong get_timer(ulong base)
@@ -93,18 +126,24 @@ ulong get_timer(ulong base)
 	return get_timer_masked() - base;
 }
 
-/* delay x useconds AND preserve advance timestamp value */
+/* delay x useconds AND preserve advance timstamp value */
 void __udelay(unsigned long usec)
 {
-	unsigned long now, start, tmo;
-	tmo = usec * (CLK_32KHZ / 1000) / 1000;
+	unsigned long long tmp;
+	ulong tmo;
 
-	if (!tmo)
-		tmo = 1;
-
-	now = start = readl(&cur_gpt->counter);
-
-	while ((now - start) < tmo)
-		now = readl(&cur_gpt->counter);
+	tmo = us_to_tick(usec);
+	tmp = get_ticks() + tmo;	/* get current timestamp */
 
+	while (get_ticks() < tmp)	/* loop till event */
+		 /*NOP*/;
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	return CLK_32KHZ;
 }

arch/arm/cpu/armv7/mx5/lowlevel_init.S

@@ -284,10 +284,24 @@
 	ldr r1, =0x00C30321
 	str r1, [r0, #CLKCTL_CSCDR1]
 #elif defined(CONFIG_MX53)
+	/* Switch peripheral to PLL2 */
+	ldr r0, =CCM_BASE_ADDR
+	ldr r1, =0x00808145
+	orr r1, r1, #(2 << 10)
+	orr r1, r1, #(0 << 16)
+	orr r1, r1, #(1 << 19)
+	str r1, [r0, #CLKCTL_CBCDR]
+
+	ldr r1, =0x00016154
+	str r1, [r0, #CLKCTL_CBCMR]
+	/* Change uart clk parent to pll2*/
+	ldr r1, [r0, #CLKCTL_CSCMR1]
+	and r1, r1, #0xfcffffff
+	orr r1, r1, #0x01000000
+	str r1, [r0, #CLKCTL_CSCMR1]
 	ldr r1, [r0, #CLKCTL_CSCDR1]
-	orr r1, r1, #0x3f
-	eor r1, r1, #0x3f
-	orr r1, r1, #0x21
+	and r1, r1, #0xffffffc0
+	orr r1, r1, #0x0a
 	str r1, [r0, #CLKCTL_CSCDR1]
 #endif
 	/* make sure divider effective */

arch/arm/cpu/armv7/mx5/soc.c

@@ -72,7 +72,7 @@ u32 get_cpu_rev(void)
 }
 
 #if defined(CONFIG_FEC_MXC)
-void imx_get_mac_from_fuse(unsigned char *mac)
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 {
 	int i;
 	struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;

arch/arm/cpu/armv7/mx6/clock.c

@@ -36,6 +36,19 @@ enum pll_clocks {
 
 struct imx_ccm_reg *imx_ccm = (struct imx_ccm_reg *)CCM_BASE_ADDR;
 
+void enable_usboh3_clk(unsigned char enable)
+{
+	u32 reg;
+
+	reg = __raw_readl(&imx_ccm->CCGR6);
+	if (enable)
+		reg |= MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG0_OFFSET;
+	else
+		reg &= ~(MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG0_OFFSET);
+	__raw_writel(reg, &imx_ccm->CCGR6);
+
+}
+
 static u32 decode_pll(enum pll_clocks pll, u32 infreq)
 {
 	u32 div;
@@ -285,6 +298,11 @@ u32 imx_get_uartclk(void)
 	return get_uart_clk();
 }
 
+u32 imx_get_fecclk(void)
+{
+	return decode_pll(PLL_ENET, CONFIG_SYS_MX6_HCLK);
+}
+
 unsigned int mxc_get_clock(enum mxc_clock clk)
 {
 	switch (clk) {

arch/arm/cpu/armv7/mx6/soc.c

@@ -32,7 +32,13 @@
 
 u32 get_cpu_rev(void)
 {
-	int system_rev = 0x61000 | CHIP_REV_1_0;
+	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+	int reg = readl(&anatop->digprog);
+
+	/* Read mx6 variant: quad, dual or solo */
+	int system_rev = (reg >> 4) & 0xFF000;
+	/* Read mx6 silicon revision */
+	system_rev |= (reg & 0xFF) + 0x10;
 
 	return system_rev;
 }
@@ -40,18 +46,35 @@ u32 get_cpu_rev(void)
 #ifdef CONFIG_ARCH_CPU_INIT
 void init_aips(void)
 {
-	u32 reg = AIPS1_BASE_ADDR;
+	struct aipstz_regs *aips1, *aips2;
+
+	aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
+	aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
 
 	/*
 	 * Set all MPROTx to be non-bufferable, trusted for R/W,
 	 * not forced to user-mode.
 	 */
-	writel(0x77777777, reg + 0x00);
-	writel(0x77777777, reg + 0x04);
+	writel(0x77777777, &aips1->mprot0);
+	writel(0x77777777, &aips1->mprot1);
+	writel(0x77777777, &aips2->mprot0);
+	writel(0x77777777, &aips2->mprot1);
 
-	reg = AIPS2_BASE_ADDR;
-	writel(0x77777777, reg + 0x00);
-	writel(0x77777777, reg + 0x04);
+	/*
+	 * Set all OPACRx to be non-bufferable, not require
+	 * supervisor privilege level for access,allow for
+	 * write access and untrusted master access.
+	 */
+	writel(0x00000000, &aips1->opacr0);
+	writel(0x00000000, &aips1->opacr1);
+	writel(0x00000000, &aips1->opacr2);
+	writel(0x00000000, &aips1->opacr3);
+	writel(0x00000000, &aips1->opacr4);
+	writel(0x00000000, &aips2->opacr0);
+	writel(0x00000000, &aips2->opacr1);
+	writel(0x00000000, &aips2->opacr2);
+	writel(0x00000000, &aips2->opacr3);
+	writel(0x00000000, &aips2->opacr4);
 }
 
 int arch_cpu_init(void)
@@ -62,21 +85,31 @@ int arch_cpu_init(void)
 }
 #endif
 
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+	/* Enable D-cache. I-cache is already enabled in start.S */
+	dcache_enable();
+}
+#endif
+
 #if defined(CONFIG_FEC_MXC)
-void imx_get_mac_from_fuse(unsigned char *mac)
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 {
 	struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
 	struct fuse_bank *bank = &iim->bank[4];
 	struct fuse_bank4_regs *fuse =
 			(struct fuse_bank4_regs *)bank->fuse_regs;
 
-	u32 mac_lo = readl(&fuse->mac_addr_low);
-	u32 mac_hi = readl(&fuse->mac_addr_high);
+	u32 value = readl(&fuse->mac_addr_high);
+	mac[0] = (value >> 8);
+	mac[1] = value ;
 
-	*(u32 *)mac = mac_lo;
-
-	mac[4] = mac_hi & 0xff;
-	mac[5] = (mac_hi >> 8) & 0xff;
+	value = readl(&fuse->mac_addr_low);
+	mac[2] = value >> 24 ;
+	mac[3] = value >> 16 ;
+	mac[4] = value >> 8 ;
+	mac[5] = value ;
 
 }
 #endif

arch/arm/cpu/armv7/omap-common/Makefile

@@ -37,6 +37,10 @@ ifneq ($(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
 COBJS	+= hwinit-common.o
 COBJS	+= clocks-common.o
 COBJS	+= emif-common.o
+endif
+
+ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
+COBJS	+= boot-common.o
 SOBJS	+= lowlevel_init.o
 endif
 
@@ -48,6 +52,9 @@ endif
 ifdef CONFIG_SPL_MMC_SUPPORT
 COBJS	+= spl_mmc.o
 endif
+ifdef CONFIG_SPL_YMODEM_SUPPORT
+COBJS	+= spl_ymodem.o
+endif
 endif
 
 ifndef CONFIG_SPL_BUILD

arch/arm/cpu/armv7/omap-common/boot-common.c

@@ -0,0 +1,49 @@
+/*
+ * boot-common.c
+ *
+ * Common bootmode functions for omap based boards
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/omap_common.h>
+#include <asm/arch/omap.h>
+
+/*
+ * This is used to verify if the configuration header
+ * was executed by rom code prior to control of transfer
+ * to the bootloader. SPL is responsible for saving and
+ * passing the boot_params pointer to the u-boot.
+ */
+struct omap_boot_parameters boot_params __attribute__ ((section(".data")));
+
+#ifdef CONFIG_SPL_BUILD
+/*
+ * We use static variables because global data is not ready yet.
+ * Initialized data is available in SPL right from the beginning.
+ * We would not typically need to save these parameters in regular
+ * U-Boot. This is needed only in SPL at the moment.
+ */
+u32 omap_bootmode = MMCSD_MODE_FAT;
+
+u32 omap_boot_device(void)
+{
+	return (u32) (boot_params.omap_bootdevice);
+}
+
+u32 omap_boot_mode(void)
+{
+	return omap_bootmode;
+}
+#endif

arch/arm/cpu/armv7/omap-common/clocks-common.c

@@ -251,6 +251,35 @@ void configure_mpu_dpll(void)
 	debug("MPU DPLL locked\n");
 }
 
+#ifdef CONFIG_USB_EHCI_OMAP
+static void setup_usb_dpll(void)
+{
+	const struct dpll_params *params;
+	u32 sys_clk_khz, sd_div, num, den;
+
+	sys_clk_khz = get_sys_clk_freq() / 1000;
+	/*
+	 * USB:
+	 * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction
+	 * DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250)
+	 *      - where CLKINP is sys_clk in MHz
+	 * Use CLKINP in KHz and adjust the denominator accordingly so
+	 * that we have enough accuracy and at the same time no overflow
+	 */
+	params = get_usb_dpll_params();
+	num = params->m * sys_clk_khz;
+	den = (params->n + 1) * 250 * 1000;
+	num += den - 1;
+	sd_div = num / den;
+	clrsetbits_le32(&prcm->cm_clksel_dpll_usb,
+			CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK,
+			sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT);
+
+	/* Now setup the dpll with the regular function */
+	do_setup_dpll(&prcm->cm_clkmode_dpll_usb, params, DPLL_LOCK, "usb");
+}
+#endif
+
 static void setup_dplls(void)
 {
 	u32 temp;
@@ -282,17 +311,18 @@ static void setup_dplls(void)
 
 	/* MPU dpll */
 	configure_mpu_dpll();
+
+#ifdef CONFIG_USB_EHCI_OMAP
+	setup_usb_dpll();
+#endif
 }
 
 #ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
 static void setup_non_essential_dplls(void)
 {
-	u32 sys_clk_khz, abe_ref_clk;
-	u32 sd_div, num, den;
+	u32 abe_ref_clk;
 	const struct dpll_params *params;
 
-	sys_clk_khz = get_sys_clk_freq() / 1000;
-
 	/* IVA */
 	clrsetbits_le32(&prcm->cm_bypclk_dpll_iva,
 		CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2);
@@ -300,26 +330,6 @@ static void setup_non_essential_dplls(void)
 	params = get_iva_dpll_params();
 	do_setup_dpll(&prcm->cm_clkmode_dpll_iva, params, DPLL_LOCK, "iva");
 
-	/*
-	 * USB:
-	 * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction
-	 * DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250)
-	 *      - where CLKINP is sys_clk in MHz
-	 * Use CLKINP in KHz and adjust the denominator accordingly so
-	 * that we have enough accuracy and at the same time no overflow
-	 */
-	params = get_usb_dpll_params();
-	num = params->m * sys_clk_khz;
-	den = (params->n + 1) * 250 * 1000;
-	num += den - 1;
-	sd_div = num / den;
-	clrsetbits_le32(&prcm->cm_clksel_dpll_usb,
-			CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK,
-			sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT);
-
-	/* Now setup the dpll with the regular function */
-	do_setup_dpll(&prcm->cm_clkmode_dpll_usb, params, DPLL_LOCK, "usb");
-
 	/* Configure ABE dpll */
 	params = get_abe_dpll_params();
 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK

arch/arm/cpu/armv7/omap-common/gpio.c

@@ -36,7 +36,7 @@
  * published by the Free Software Foundation.
  */
 #include <common.h>
-#include <asm/arch/gpio.h>
+#include <asm/gpio.h>
 #include <asm/io.h>
 #include <asm/errno.h>
 
@@ -56,17 +56,17 @@ static inline int get_gpio_index(int gpio)
 static inline int gpio_valid(int gpio)
 {
 	if (gpio < 0)
-		return -EINVAL;
+		return -1;
 	if (gpio < 192)
 		return 0;
-	return -EINVAL;
+	return -1;
 }
 
 static int check_gpio(int gpio)
 {
 	if (gpio_valid(gpio) < 0) {
 		printf("ERROR : check_gpio: invalid GPIO %d\n", gpio);
-		return -EINVAL;
+		return -1;
 	}
 	return 0;
 }
@@ -106,7 +106,7 @@ static int _get_gpio_direction(const struct gpio_bank *bank, int gpio)
 		reg += OMAP_GPIO_OE;
 		break;
 	default:
-		return -EINVAL;
+		return -1;
 	}
 
 	v = __raw_readl(reg);
@@ -142,27 +142,29 @@ static void _set_gpio_dataout(const struct gpio_bank *bank, int gpio,
 /**
  * Set value of the specified gpio
  */
-void gpio_set_value(int gpio, int value)
+int gpio_set_value(unsigned gpio, int value)
 {
 	const struct gpio_bank *bank;
 
 	if (check_gpio(gpio) < 0)
-		return;
+		return -1;
 	bank = get_gpio_bank(gpio);
 	_set_gpio_dataout(bank, get_gpio_index(gpio), value);
+
+	return 0;
 }
 
 /**
  * Get value of the specified gpio
  */
-int gpio_get_value(int gpio)
+int gpio_get_value(unsigned gpio)
 {
 	const struct gpio_bank *bank;
 	void *reg;
 	int input;
 
 	if (check_gpio(gpio) < 0)
-		return -EINVAL;
+		return -1;
 	bank = get_gpio_bank(gpio);
 	reg = bank->base;
 	switch (bank->method) {
@@ -176,11 +178,11 @@ int gpio_get_value(int gpio)
 			reg += OMAP_GPIO_DATAOUT;
 			break;
 		default:
-			return -EINVAL;
+			return -1;
 		}
 		break;
 	default:
-		return -EINVAL;
+		return -1;
 	}
 	return (__raw_readl(reg)
 			& (1 << get_gpio_index(gpio))) != 0;
@@ -194,7 +196,7 @@ int gpio_direction_input(unsigned gpio)
 	const struct gpio_bank *bank;
 
 	if (check_gpio(gpio) < 0)
-		return -EINVAL;
+		return -1;
 
 	bank = get_gpio_bank(gpio);
 	_set_gpio_direction(bank, get_gpio_index(gpio), 1);
@@ -210,7 +212,7 @@ int gpio_direction_output(unsigned gpio, int value)
 	const struct gpio_bank *bank;
 
 	if (check_gpio(gpio) < 0)
-		return -EINVAL;
+		return -1;
 
 	bank = get_gpio_bank(gpio);
 	_set_gpio_dataout(bank, get_gpio_index(gpio), value);
@@ -224,10 +226,10 @@ int gpio_direction_output(unsigned gpio, int value)
  *
  * NOTE: Argument 'label' is unused.
  */
-int gpio_request(int gpio, const char *label)
+int gpio_request(unsigned gpio, const char *label)
 {
 	if (check_gpio(gpio) < 0)
-		return -EINVAL;
+		return -1;
 
 	return 0;
 }
@@ -235,6 +237,7 @@ int gpio_request(int gpio, const char *label)
 /**
  * Reset and free the gpio after using it.
  */
-void gpio_free(unsigned gpio)
+int gpio_free(unsigned gpio)
 {
+	return 0;
 }

arch/arm/cpu/armv7/omap-common/hwinit-common.c

@@ -35,34 +35,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-/*
- * This is used to verify if the configuration header
- * was executed by rom code prior to control of transfer
- * to the bootloader. SPL is responsible for saving and
- * passing the boot_params pointer to the u-boot.
- */
-struct omap_boot_parameters boot_params __attribute__ ((section(".data")));
-
-#ifdef CONFIG_SPL_BUILD
-/*
- * We use static variables because global data is not ready yet.
- * Initialized data is available in SPL right from the beginning.
- * We would not typically need to save these parameters in regular
- * U-Boot. This is needed only in SPL at the moment.
- */
-u32 omap_bootmode = MMCSD_MODE_FAT;
-
-u32 omap_boot_device(void)
-{
-	return (u32) (boot_params.omap_bootdevice);
-}
-
-u32 omap_boot_mode(void)
-{
-	return omap_bootmode;
-}
-#endif
-
 void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
 {
 	int i;
@@ -104,14 +76,14 @@ u32 cortex_rev(void)
 	return rev;
 }
 
-void omap_rev_string(char *omap_rev_string)
+void omap_rev_string(void)
 {
 	u32 omap_rev = omap_revision();
 	u32 omap_variant = (omap_rev & 0xFFFF0000) >> 16;
 	u32 major_rev = (omap_rev & 0x00000F00) >> 8;
 	u32 minor_rev = (omap_rev & 0x000000F0) >> 4;
 
-	sprintf(omap_rev_string, "OMAP%x ES%x.%x", omap_variant, major_rev,
+	printf("OMAP%x ES%x.%x\n", omap_variant, major_rev,
 		minor_rev);
 }
 
@@ -148,6 +120,8 @@ void s_init(void)
 #endif
 	prcm_init();
 #ifdef CONFIG_SPL_BUILD
+	timer_init();
+
 	/* For regular u-boot sdram_init() is called from dram_init() */
 	sdram_init();
 	init_boot_params();
@@ -251,10 +225,8 @@ u32 get_device_type(void)
  */
 int print_cpuinfo(void)
 {
-	char rev_string_buffer[50];
-
-	omap_rev_string(rev_string_buffer);
-	printf("CPU  : %s\n", rev_string_buffer);
+	puts("CPU  : ");
+	omap_rev_string();
 
 	return 0;
 }

arch/arm/cpu/armv7/omap-common/spl.c

@@ -35,6 +35,7 @@
 #include <i2c.h>
 #include <image.h>
 #include <malloc.h>
+#include <linux/compiler.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -64,6 +65,25 @@ void board_init_f(ulong dummy)
 	relocate_code(CONFIG_SPL_STACK, &gdata, CONFIG_SPL_TEXT_BASE);
 }
 
+/*
+ * Default function to determine if u-boot or the OS should
+ * be started. This implementation always returns 1.
+ *
+ * Please implement your own board specific funcion to do this.
+ *
+ * RETURN
+ * 0 to not start u-boot
+ * positive if u-boot should start
+ */
+#ifdef CONFIG_SPL_OS_BOOT
+__weak int spl_start_uboot(void)
+{
+	printf("SPL: Please implement spl_start_uboot() for your board\n");
+	printf("SPL: Direct Linux boot not active!\n");
+	return 1;
+}
+#endif
+
 void spl_parse_image_header(const struct image_header *header)
 {
 	u32 header_size = sizeof(struct image_header);
@@ -81,7 +101,7 @@ void spl_parse_image_header(const struct image_header *header)
 		/* Signature not found - assume u-boot.bin */
 		printf("mkimage signature not found - ih_magic = %x\n",
 			header->ih_magic);
-		puts("Assuming u-boot.bin ..\n");
+		debug("Assuming u-boot.bin ..\n");
 		/* Let's assume U-Boot will not be more than 200 KB */
 		spl_image.size = 200 * 1024;
 		spl_image.entry_point = CONFIG_SYS_TEXT_BASE;
@@ -91,9 +111,27 @@ void spl_parse_image_header(const struct image_header *header)
 	}
 }
 
-static void jump_to_image_no_args(void)
+/*
+ * This function jumps to an image with argument. Normally an FDT or ATAGS
+ * image.
+ * arg: Pointer to paramter image in RAM
+ */
+#ifdef CONFIG_SPL_OS_BOOT
+static void __noreturn jump_to_image_linux(void *arg)
 {
-	typedef void (*image_entry_noargs_t)(u32 *)__attribute__ ((noreturn));
+	debug("Entering kernel arg pointer: 0x%p\n", arg);
+	typedef void (*image_entry_arg_t)(int, int, void *)
+		__attribute__ ((noreturn));
+	image_entry_arg_t image_entry =
+		(image_entry_arg_t) spl_image.entry_point;
+	cleanup_before_linux();
+	image_entry(0, CONFIG_MACH_TYPE, arg);
+}
+#endif
+
+static void __noreturn jump_to_image_no_args(void)
+{
+	typedef void __noreturn (*image_entry_noargs_t)(u32 *);
 	image_entry_noargs_t image_entry =
 			(image_entry_noargs_t) spl_image.entry_point;
 
@@ -106,7 +144,6 @@ static void jump_to_image_no_args(void)
 	image_entry((u32 *)boot_params_ptr_addr);
 }
 
-void jump_to_image_no_args(void) __attribute__ ((noreturn));
 void board_init_r(gd_t *id, ulong dummy)
 {
 	u32 boot_device;
@@ -115,8 +152,6 @@ void board_init_r(gd_t *id, ulong dummy)
 	mem_malloc_init(CONFIG_SYS_SPL_MALLOC_START,
 			CONFIG_SYS_SPL_MALLOC_SIZE);
 
-	timer_init();
-
 #ifdef CONFIG_SPL_BOARD_INIT
 	spl_board_init();
 #endif
@@ -134,6 +169,11 @@ void board_init_r(gd_t *id, ulong dummy)
 	case BOOT_DEVICE_NAND:
 		spl_nand_load_image();
 		break;
+#endif
+#ifdef CONFIG_SPL_YMODEM_SUPPORT
+	case BOOT_DEVICE_UART:
+		spl_ymodem_load_image();
+		break;
 #endif
 	default:
 		printf("SPL: Un-supported Boot Device - %d!!!\n", boot_device);
@@ -146,6 +186,13 @@ void board_init_r(gd_t *id, ulong dummy)
 		debug("Jumping to U-Boot\n");
 		jump_to_image_no_args();
 		break;
+#ifdef CONFIG_SPL_OS_BOOT
+	case IH_OS_LINUX:
+		debug("Jumping to Linux\n");
+		spl_board_prepare_for_linux();
+		jump_to_image_linux((void *)CONFIG_SYS_SPL_ARGS_ADDR);
+		break;
+#endif
 	default:
 		puts("Unsupported OS image.. Jumping nevertheless..\n");
 		jump_to_image_no_args();
@@ -156,7 +203,6 @@ void board_init_r(gd_t *id, ulong dummy)
 void preloader_console_init(void)
 {
 	const char *u_boot_rev = U_BOOT_VERSION;
-	char rev_string_buffer[50];
 
 	gd = &gdata;
 	gd->bd = &bdata;
@@ -172,14 +218,10 @@ void preloader_console_init(void)
 
 	printf("\nU-Boot SPL %s (%s - %s)\n", u_boot_rev, U_BOOT_DATE,
 		U_BOOT_TIME);
-	omap_rev_string(rev_string_buffer);
-	printf("Texas Instruments %s\n", rev_string_buffer);
+	omap_rev_string();
 }
 
-void __omap_rev_string(char *str)
+void __weak omap_rev_string()
 {
-	sprintf(str, "Revision detection unimplemented");
+	printf("Texas Instruments Revision detection unimplemented\n");
 }
-
-void omap_rev_string(char *str)
-	__attribute__((weak, alias("__omap_rev_string")));

arch/arm/cpu/armv7/omap-common/spl_nand.c

@@ -24,14 +24,17 @@
 #include <asm/u-boot.h>
 #include <asm/utils.h>
 #include <asm/arch/sys_proto.h>
+#include <asm/io.h>
 #include <nand.h>
 #include <version.h>
 #include <asm/omap_common.h>
 
-
 void spl_nand_load_image(void)
 {
 	struct image_header *header;
+	int *src __attribute__((unused));
+	int *dst __attribute__((unused));
+
 	switch (omap_boot_mode()) {
 	case NAND_MODE_HW_ECC:
 		debug("spl: nand - using hw ecc\n");
@@ -45,19 +48,57 @@ void spl_nand_load_image(void)
 
 	/*use CONFIG_SYS_TEXT_BASE as temporary storage area */
 	header = (struct image_header *)(CONFIG_SYS_TEXT_BASE);
+#ifdef CONFIG_SPL_OS_BOOT
+	if (!spl_start_uboot()) {
+		/*
+		 * load parameter image
+		 * load to temp position since nand_spl_load_image reads
+		 * a whole block which is typically larger than
+		 * CONFIG_CMD_SAVEBP_WRITE_SIZE therefore may overwrite
+		 * following sections like BSS
+		 */
+		nand_spl_load_image(CONFIG_CMD_SPL_NAND_OFS,
+			CONFIG_CMD_SPL_WRITE_SIZE,
+			(void *)CONFIG_SYS_TEXT_BASE);
+		/* copy to destintion */
+		for (dst = (int *)CONFIG_SYS_SPL_ARGS_ADDR,
+				src = (int *)CONFIG_SYS_TEXT_BASE;
+				src < (int *)(CONFIG_SYS_TEXT_BASE +
+				CONFIG_CMD_SPL_WRITE_SIZE);
+				src++, dst++) {
+			writel(readl(src), dst);
+		}
 
+		/* load linux */
+		nand_spl_load_image(CONFIG_SYS_NAND_SPL_KERNEL_OFFS,
+			CONFIG_SYS_NAND_PAGE_SIZE, (void *)header);
+		spl_parse_image_header(header);
+		if (header->ih_os == IH_OS_LINUX) {
+			/* happy - was a linux */
+			nand_spl_load_image(CONFIG_SYS_NAND_SPL_KERNEL_OFFS,
+				spl_image.size, (void *)spl_image.load_addr);
+			nand_deselect();
+			return;
+		} else {
+			printf("The Expected Linux image was not"
+				"found. Please check your NAND"
+				"configuration.\n");
+			printf("Trying to start u-boot now...\n");
+		}
+	}
+#endif
 #ifdef CONFIG_NAND_ENV_DST
 	nand_spl_load_image(CONFIG_ENV_OFFSET,
 		CONFIG_SYS_NAND_PAGE_SIZE, (void *)header);
 	spl_parse_image_header(header);
 	nand_spl_load_image(CONFIG_ENV_OFFSET, spl_image.size,
-		(void *)image_load_addr);
+		(void *)spl_image.load_addr);
 #ifdef CONFIG_ENV_OFFSET_REDUND
 	nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND,
 		CONFIG_SYS_NAND_PAGE_SIZE, (void *)header);
 	spl_parse_image_header(header);
 	nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, spl_image.size,
-		(void *)image_load_addr);
+		(void *)spl_image.load_addr);
 #endif
 #endif
 	/* Load u-boot */

arch/arm/cpu/armv7/omap-common/spl_ymodem.c

@@ -0,0 +1,76 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2011
+ * Texas Instruments, <www.ti.com>
+ *
+ * Matt Porter <mporter@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <xyzModem.h>
+#include <asm/u-boot.h>
+#include <asm/utils.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/omap_common.h>
+
+#define BUF_SIZE 1024
+
+static int getcymodem(void) {
+	if (tstc())
+		return (getc());
+	return -1;
+}
+
+void spl_ymodem_load_image(void)
+{
+	int size = 0;
+	int err;
+	int res;
+	int ret;
+	connection_info_t info;
+	char buf[BUF_SIZE];
+	ulong store_addr = ~0;
+	ulong addr = 0;
+
+	info.mode = xyzModem_ymodem;
+	ret = xyzModem_stream_open(&info, &err);
+
+	if (!ret) {
+		while ((res =
+			xyzModem_stream_read(buf, BUF_SIZE, &err)) > 0) {
+			if (addr == 0)
+				spl_parse_image_header((struct image_header *)buf);
+			store_addr = addr + spl_image.load_addr;
+			size += res;
+			addr += res;
+			memcpy((char *)(store_addr), buf, res);
+		}
+	} else {
+		printf("spl: ymodem err - %s\n", xyzModem_error(err));
+		hang();
+	}
+
+	xyzModem_stream_close(&err);
+	xyzModem_stream_terminate(false, &getcymodem);
+
+	printf("Loaded %d bytes\n", size);
+}

arch/arm/cpu/armv7/omap3/board.c

@@ -92,7 +92,9 @@ u32 omap_boot_device(void)
 
 void spl_board_init(void)
 {
+#ifdef CONFIG_SPL_I2C_SUPPORT
 	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
 }
 #endif /* CONFIG_SPL_BUILD */
 
@@ -144,7 +146,7 @@ void secureworld_exit()
 {
 	unsigned long i;
 
-	/* configrue non-secure access control register */
+	/* configure non-secure access control register */
 	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
 	/* enabling co-processor CP10 and CP11 accesses in NS world */
 	__asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
@@ -228,8 +230,14 @@ void s_init(void)
 
 	per_clocks_enable();
 
+#ifdef CONFIG_USB_EHCI_OMAP
+	ehci_clocks_enable();
+#endif
+
 #ifdef CONFIG_SPL_BUILD
 	preloader_console_init();
+
+	timer_init();
 #endif
 
 	if (!in_sdram)
@@ -387,7 +395,7 @@ static void omap3_setup_aux_cr(void)
 {
 	/* Workaround for Cortex-A8 errata: #454179 #430973
 	 *	Set "IBE" bit
-	 *	Set "Disable Brach Size Mispredicts" bit
+	 *	Set "Disable Branch Size Mispredicts" bit
 	 * Workaround for erratum #621766
 	 *	Enable L1NEON bit
 	 * ACR |= (IBE | DBSM | L1NEON) => ACR |= 0xE0
@@ -424,7 +432,7 @@ void v7_outer_cache_enable(void)
 	omap3_update_aux_cr(0x2, 0);
 }
 
-void v7_outer_cache_disable(void)
+void omap3_outer_cache_disable(void)
 {
 	/* Clear L2EN */
 	omap3_update_aux_cr_secure(0, 0x2);

arch/arm/cpu/armv7/omap3/clock.c

@@ -626,6 +626,26 @@ void prcm_init(void)
 	sdelay(5000);
 }
 
+/*
+ * Enable usb ehci uhh, tll clocks
+ */
+void ehci_clocks_enable(void)
+{
+	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+
+	/* Enable USBHOST_L3_ICLK (USBHOST_MICLK) */
+	sr32(&prcm_base->iclken_usbhost, 0, 1, 1);
+	/*
+	 * Enable USBHOST_48M_FCLK (USBHOST_FCLK1)
+	 * and USBHOST_120M_FCLK (USBHOST_FCLK2)
+	 */
+	sr32(&prcm_base->fclken_usbhost, 0, 2, 3);
+	/* Enable USBTTL_ICLK */
+	sr32(&prcm_base->iclken3_core, 2, 1, 1);
+	/* Enable USBTTL_FCLK */
+	sr32(&prcm_base->fclken3_core, 2, 1, 1);
+}
+
 /******************************************************************************
  * peripheral_enable() - Enable the clks & power for perifs (GPT2, UART1,...)
  *****************************************************************************/

arch/arm/cpu/armv7/omap3/lowlevel_init.S

@@ -35,15 +35,15 @@
 _TEXT_BASE:
 	.word	CONFIG_SYS_TEXT_BASE	/* sdram load addr from config.mk */
 
+#ifdef CONFIG_SPL_BUILD
 .global save_boot_params
 save_boot_params:
-#ifdef CONFIG_SPL_BUILD
 	ldr	r4, =omap3_boot_device
 	ldr	r5, [r0, #0x4]
 	and	r5, r5, #0xff
 	str	r5, [r4]
-#endif
 	bx	lr
+#endif
 
 .global omap3_gp_romcode_call
 omap3_gp_romcode_call:

arch/arm/cpu/armv7/omap3/sdrc.c

@@ -102,7 +102,7 @@ u32 get_sdr_cs_offset(u32 cs)
 		return 0;
 
 	offset = readl(&sdrc_base->cs_cfg);
-	offset = (offset & 15) << 27 | (offset & 0x30) << 17;
+	offset = (offset & 15) << 27 | (offset & 0x300) << 17;
 
 	return offset;
 }
@@ -180,7 +180,7 @@ void do_sdrc_init(u32 cs, u32 early)
 		write_sdrc_timings(CS0, sdrc_actim_base0, mcfg, ctrla, ctrlb,
 				rfr_ctrl, mr);
 		make_cs1_contiguous();
-		write_sdrc_timings(CS0, sdrc_actim_base1, mcfg, ctrla, ctrlb,
+		write_sdrc_timings(CS1, sdrc_actim_base1, mcfg, ctrla, ctrlb,
 				rfr_ctrl, mr);
 #endif
 

arch/arm/cpu/armv7/omap3/sys_info.c

@@ -30,6 +30,7 @@
 #include <asm/arch/mem.h>	/* get mem tables */
 #include <asm/arch/sys_proto.h>
 #include <i2c.h>
+#include <linux/compiler.h>
 
 extern omap3_sysinfo sysinfo;
 static struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
@@ -197,7 +198,7 @@ u32 get_gpmc0_width(void)
  * get_board_rev() - setup to pass kernel board revision information
  * returns:(bit[0-3] sub version, higher bit[7-4] is higher version)
  *************************************************************************/
-u32 get_board_rev(void)
+u32 __weak get_board_rev(void)
 {
 	return 0x20;
 }

arch/arm/cpu/armv7/omap4/clocks.c

@@ -67,15 +67,15 @@ const u32 sys_clk_array[8] = {
  * Please use this tool for creating the table for any new frequency.
  */
 
-/* dpll locked at 1840 MHz MPU clk at 920 MHz(OPP Turbo 4460) - DCC OFF */
-static const struct dpll_params mpu_dpll_params_1840mhz[NUM_SYS_CLKS] = {
-	{230, 2, 1, -1, -1, -1, -1, -1},	/* 12 MHz   */
-	{920, 12, 1, -1, -1, -1, -1, -1},	/* 13 MHz   */
-	{219, 3, 1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
-	{575, 11, 1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
-	{460, 12, 1, -1, -1, -1, -1, -1},	/* 26 MHz   */
-	{920, 26, 1, -1, -1, -1, -1, -1},	/* 27 MHz   */
-	{575, 23, 1, -1, -1, -1, -1, -1}	/* 38.4 MHz */
+/* dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF */
+static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = {
+	{175, 2, 1, -1, -1, -1, -1, -1},	/* 12 MHz   */
+	{700, 12, 1, -1, -1, -1, -1, -1},	/* 13 MHz   */
+	{125, 2, 1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
+	{401, 10, 1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
+	{350, 12, 1, -1, -1, -1, -1, -1},	/* 26 MHz   */
+	{700, 26, 1, -1, -1, -1, -1, -1},	/* 27 MHz   */
+	{638, 34, 1, -1, -1, -1, -1, -1}	/* 38.4 MHz */
 };
 
 /* dpll locked at 1584 MHz - MPU clk at 792 MHz(OPP Turbo 4430) */
@@ -217,7 +217,7 @@ const struct dpll_params *get_mpu_dpll_params(void)
 	else if (omap_rev < OMAP4460_ES1_0)
 		return &mpu_dpll_params_1600mhz[sysclk_ind];
 	else
-		return &mpu_dpll_params_1840mhz[sysclk_ind];
+		return &mpu_dpll_params_1400mhz[sysclk_ind];
 }
 
 const struct dpll_params *get_core_dpll_params(void)
@@ -280,7 +280,7 @@ void scale_vcores(void)
 	omap_rev = omap_revision();
 	/* TPS - supplies vdd_mpu on 4460 */
 	if (omap_rev >= OMAP4460_ES1_0) {
-		volt = 1313;
+		volt = 1203;
 		do_scale_tps62361(TPS62361_REG_ADDR_SET1, volt);
 	}
 
@@ -342,6 +342,9 @@ void enable_basic_clocks(void)
 		&prcm->cm_l4per_gpio4_clkctrl,
 		&prcm->cm_l4per_gpio5_clkctrl,
 		&prcm->cm_l4per_gpio6_clkctrl,
+		&prcm->cm_l3init_usbphy_clkctrl,
+		&prcm->cm_clksel_usb_60mhz,
+		&prcm->cm_l3init_hsusbtll_clkctrl,
 		0
 	};
 
@@ -352,6 +355,8 @@ void enable_basic_clocks(void)
 		&prcm->cm_l4per_gptimer2_clkctrl,
 		&prcm->cm_wkup_wdtimer2_clkctrl,
 		&prcm->cm_l4per_uart3_clkctrl,
+		&prcm->cm_l3init_fsusb_clkctrl,
+		&prcm->cm_l3init_hsusbhost_clkctrl,
 		0
 	};
 

arch/arm/cpu/armv7/omap4/hwinit.c

@@ -110,10 +110,10 @@ void do_io_settings(void)
 	 *	i. unconditionally for all 4430
 	 *	ii. only if un-trimmed for 4460
 	 */
-	if ((omap4_rev < OMAP4460_ES1_0) || !readl(&ctrl->control_efuse_1))
+	if (!readl(&ctrl->control_efuse_1))
 		writel(CONTROL_EFUSE_1_OVERRIDE, &ctrl->control_efuse_1);
 
-	if (!readl(&ctrl->control_efuse_2))
+	if ((omap4_rev < OMAP4460_ES1_0) || !readl(&ctrl->control_efuse_2))
 		writel(CONTROL_EFUSE_2_OVERRIDE, &ctrl->control_efuse_2);
 }
 #endif

arch/arm/cpu/armv7/s5p-common/Makefile

@@ -28,6 +28,7 @@ LIB	= $(obj)libs5p-common.o
 COBJS-y		+= cpu_info.o
 COBJS-y		+= timer.o
 COBJS-y		+= sromc.o
+COBJS-y		+= wdt.o
 COBJS-$(CONFIG_PWM)	+= pwm.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)

arch/arm/cpu/armv7/s5p-common/wdt.c

@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/watchdog.h>
+
+#define PRESCALER_VAL 255
+
+void wdt_stop(void)
+{
+	struct s5p_watchdog *wdt =
+		(struct s5p_watchdog *)samsung_get_base_watchdog();
+	unsigned int wtcon;
+
+	wtcon = readl(&wdt->wtcon);
+	wtcon &= ~(WTCON_EN | WTCON_INT | WTCON_RESET);
+
+	writel(wtcon, &wdt->wtcon);
+}
+
+void wdt_start(unsigned int timeout)
+{
+	struct s5p_watchdog *wdt =
+		(struct s5p_watchdog *)samsung_get_base_watchdog();
+	unsigned int wtcon;
+
+	wdt_stop();
+
+	wtcon = readl(&wdt->wtcon);
+	wtcon |= (WTCON_EN | WTCON_CLK(WTCON_CLK_128));
+	wtcon &= ~WTCON_INT;
+	wtcon |= WTCON_RESET;
+	wtcon |= WTCON_PRESCALER(PRESCALER_VAL);
+
+	writel(timeout, &wdt->wtdat);
+	writel(timeout, &wdt->wtcnt);
+	writel(wtcon, &wdt->wtcon);
+}

arch/arm/cpu/armv7/tegra2/Makefile

@@ -33,8 +33,10 @@ include $(TOPDIR)/config.mk
 LIB	=  $(obj)lib$(SOC).o
 
 SOBJS	:= lowlevel_init.o
-COBJS	:= ap20.o board.o clock.o pinmux.o sys_info.o timer.o
+COBJS-y	:= ap20.o board.o clock.o funcmux.o pinmux.o sys_info.o timer.o
+COBJS-$(CONFIG_USB_EHCI_TEGRA) += usb.o
 
+COBJS	:= $(COBJS-y)
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
 

arch/arm/cpu/armv7/tegra2/ap20.c

@@ -105,14 +105,14 @@ static void enable_cpu_clock(int enable)
 
 static int is_cpu_powered(void)
 {
-	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE;
 
 	return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0;
 }
 
 static void remove_cpu_io_clamps(void)
 {
-	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE;
 	u32 reg;
 
 	/* Remove the clamps on the CPU I/O signals */
@@ -126,7 +126,7 @@ static void remove_cpu_io_clamps(void)
 
 static void powerup_cpu(void)
 {
-	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE;
 	u32 reg;
 	int timeout = IO_STABILIZATION_DELAY;
 
@@ -157,7 +157,7 @@ static void powerup_cpu(void)
 
 static void enable_cpu_power_rail(void)
 {
-	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE;
 	u32 reg;
 
 	reg = readl(&pmc->pmc_cntrl);
@@ -277,7 +277,7 @@ void enable_scu(void)
 
 void init_pmc_scratch(void)
 {
-	struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+	struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE;
 	int i;
 
 	/* SCRATCH0 is initialized by the boot ROM and shouldn't be cleared */
@@ -298,11 +298,11 @@ void tegra2_start(void)
 		writel(0xC0, &pmt->pmt_cfg_ctl);
 
 		/*
-		* If we are ARM7 - give it a different stack. We are about to
-		* start up the A9 which will want to use this one.
-		*/
-		asm volatile("ldr	sp, =%c0\n"
-			: : "i"(AVP_EARLY_BOOT_STACK_LIMIT));
+		 * If we are ARM7 - give it a different stack. We are about to
+		 * start up the A9 which will want to use this one.
+		 */
+		asm volatile("mov	sp, %0\n"
+			: : "r"(AVP_EARLY_BOOT_STACK_LIMIT));
 
 		start_cpu((u32)_start);
 		halt_avp();

arch/arm/cpu/armv7/tegra2/board.c

@@ -24,12 +24,22 @@
 #include <common.h>
 #include <asm/io.h>
 #include "ap20.h"
+#include <asm/arch/clock.h>
+#include <asm/arch/funcmux.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/tegra2.h>
 #include <asm/arch/pmc.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+enum {
+	/* UARTs which we can enable */
+	UARTA	= 1 << 0,
+	UARTB	= 1 << 1,
+	UARTD	= 1 << 3,
+	UART_COUNT = 4,
+};
+
 /*
  * Boot ROM initializes the odmdata in APBDEV_PMC_SCRATCH20_0,
  * so we are using this value to identify memory size.
@@ -37,7 +47,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 unsigned int query_sdram_size(void)
 {
-	struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+	struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE;
 	u32 reg;
 
 	reg = readl(&pmc->pmc_scratch20);
@@ -48,9 +58,9 @@ unsigned int query_sdram_size(void)
 	case 1:
 		return 0x10000000;	/* 256 MB */
 	case 2:
+	default:
 		return 0x20000000;	/* 512 MB */
 	case 3:
-	default:
 		return 0x40000000;	/* 1GB */
 	}
 }
@@ -80,6 +90,62 @@ int arch_cpu_init(void)
 {
 	/* Fire up the Cortex A9 */
 	tegra2_start();
+
+	/* We didn't do this init in start.S, so do it now */
+	cpu_init_cp15();
+
+	/* Initialize essential common plls */
+	clock_early_init();
+
 	return 0;
 }
 #endif
+
+/**
+ * Set up the specified uarts
+ *
+ * @param uarts_ids	Mask containing UARTs to init (UARTx)
+ */
+static void setup_uarts(int uart_ids)
+{
+	static enum periph_id id_for_uart[] = {
+		PERIPH_ID_UART1,
+		PERIPH_ID_UART2,
+		PERIPH_ID_UART3,
+		PERIPH_ID_UART4,
+	};
+	size_t i;
+
+	for (i = 0; i < UART_COUNT; i++) {
+		if (uart_ids & (1 << i)) {
+			enum periph_id id = id_for_uart[i];
+
+			funcmux_select(id, FUNCMUX_DEFAULT);
+			clock_ll_start_uart(id);
+		}
+	}
+}
+
+void board_init_uart_f(void)
+{
+	int uart_ids = 0;	/* bit mask of which UART ids to enable */
+
+#ifdef CONFIG_TEGRA2_ENABLE_UARTA
+	uart_ids |= UARTA;
+#endif
+#ifdef CONFIG_TEGRA2_ENABLE_UARTB
+	uart_ids |= UARTB;
+#endif
+#ifdef CONFIG_TEGRA2_ENABLE_UARTD
+	uart_ids |= UARTD;
+#endif
+	setup_uarts(uart_ids);
+}
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+	/* Enable D-cache. I-cache is already enabled in start.S */
+	dcache_enable();
+}
+#endif

arch/arm/cpu/armv7/tegra2/clock.c

@@ -28,6 +28,7 @@
 #include <asm/arch/tegra2.h>
 #include <common.h>
 #include <div64.h>
+#include <fdtdec.h>
 
 /*
  * This is our record of the current clock rate of each clock. We don't
@@ -67,6 +68,7 @@ enum clock_type_id {
 	CLOCK_TYPE_MCPT,
 	CLOCK_TYPE_PCM,
 	CLOCK_TYPE_PCMT,
+	CLOCK_TYPE_PCMT16,	/* CLOCK_TYPE_PCMT with 16-bit divider */
 	CLOCK_TYPE_PCXTS,
 	CLOCK_TYPE_PDCT,
 
@@ -98,6 +100,7 @@ static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX] = {
 	{ CLK(MEMORY),	CLK(CGENERAL),	CLK(PERIPH),	CLK(OSC)	},
 	{ CLK(PERIPH),	CLK(CGENERAL),	CLK(MEMORY),	CLK(NONE)	},
 	{ CLK(PERIPH),	CLK(CGENERAL),	CLK(MEMORY),	CLK(OSC)	},
+	{ CLK(PERIPH),	CLK(CGENERAL),	CLK(MEMORY),	CLK(OSC)	},
 	{ CLK(PERIPH),	CLK(CGENERAL),	CLK(XCPU),	CLK(OSC)	},
 	{ CLK(PERIPH),	CLK(DISPLAY),	CLK(CGENERAL),	CLK(OSC)	},
 };
@@ -211,8 +214,8 @@ static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
 
 	/* 0x08 */
 	TYPE(PERIPHC_XIO,	CLOCK_TYPE_PCMT),
-	TYPE(PERIPHC_I2C1,	CLOCK_TYPE_PCMT),
-	TYPE(PERIPHC_DVC_I2C,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_I2C1,	CLOCK_TYPE_PCMT16),
+	TYPE(PERIPHC_DVC_I2C,	CLOCK_TYPE_PCMT16),
 	TYPE(PERIPHC_TWC,	CLOCK_TYPE_PCMT),
 	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
 	TYPE(PERIPHC_SPI1,	CLOCK_TYPE_PCMT),
@@ -246,7 +249,7 @@ static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
 	TYPE(PERIPHC_HDMI,	CLOCK_TYPE_PDCT),
 	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
 	TYPE(PERIPHC_TVDAC,	CLOCK_TYPE_PDCT),
-	TYPE(PERIPHC_I2C2,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_I2C2,	CLOCK_TYPE_PCMT16),
 	TYPE(PERIPHC_EMC,	CLOCK_TYPE_MCPT),
 
 	/* 0x28 */
@@ -256,7 +259,7 @@ static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
 	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
 	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
 	TYPE(PERIPHC_SPI4,	CLOCK_TYPE_PCMT),
-	TYPE(PERIPHC_I2C3,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_I2C3,	CLOCK_TYPE_PCMT16),
 	TYPE(PERIPHC_SDMMC3,	CLOCK_TYPE_PCMT),
 
 	/* 0x30 */
@@ -518,14 +521,16 @@ void clock_ll_set_source(enum periph_id periph_id, unsigned source)
  * Given the parent's rate and the required rate for the children, this works
  * out the peripheral clock divider to use, in 7.1 binary format.
  *
+ * @param divider_bits	number of divider bits (8 or 16)
  * @param parent_rate	clock rate of parent clock in Hz
  * @param rate		required clock rate for this clock
  * @return divider which should be used
  */
-static int clk_div7_1_get_divider(unsigned long parent_rate,
-				  unsigned long rate)
+static int clk_get_divider(unsigned divider_bits, unsigned long parent_rate,
+			   unsigned long rate)
 {
 	u64 divider = parent_rate * 2;
+	unsigned max_divider = 1 << divider_bits;
 
 	divider += rate - 1;
 	do_div(divider, rate);
@@ -533,7 +538,7 @@ static int clk_div7_1_get_divider(unsigned long parent_rate,
 	if ((s64)divider - 2 < 0)
 		return 0;
 
-	if ((s64)divider - 2 > 255)
+	if ((s64)divider - 2 >= max_divider)
 		return -1;
 
 	return divider - 2;
@@ -571,6 +576,7 @@ unsigned long clock_get_periph_rate(enum periph_id periph_id,
  * required child clock rate. This function assumes that a second-stage
  * divisor is available which can divide by powers of 2 from 1 to 256.
  *
+ * @param divider_bits	number of divider bits (8 or 16)
  * @param parent_rate	clock rate of parent clock in Hz
  * @param rate		required clock rate for this clock
  * @param extra_div	value for the second-stage divisor (not set if this
@@ -578,8 +584,8 @@ unsigned long clock_get_periph_rate(enum periph_id periph_id,
  * @return divider which should be used, or -1 if nothing is valid
  *
  */
-static int find_best_divider(unsigned long parent_rate, unsigned long rate,
-		int *extra_div)
+static int find_best_divider(unsigned divider_bits, unsigned long parent_rate,
+			     unsigned long rate, int *extra_div)
 {
 	int shift;
 	int best_divider = -1;
@@ -588,7 +594,8 @@ static int find_best_divider(unsigned long parent_rate, unsigned long rate,
 	/* try dividers from 1 to 256 and find closest match */
 	for (shift = 0; shift <= 8 && best_error > 0; shift++) {
 		unsigned divided_parent = parent_rate >> shift;
-		int divider = clk_div7_1_get_divider(divided_parent, rate);
+		int divider = clk_get_divider(divider_bits, divided_parent,
+					      rate);
 		unsigned effective_rate = get_rate_from_divider(divided_parent,
 						       divider);
 		int error = rate - effective_rate;
@@ -614,10 +621,11 @@ static int find_best_divider(unsigned long parent_rate, unsigned long rate,
  * @param periph_id	peripheral to start
  * @param source	PLL id of required parent clock
  * @param mux_bits	Set to number of bits in mux register: 2 or 4
+ * @param divider_bits	Set to number of divider bits (8 or 16)
  * @return mux value (0-4, or -1 if not found)
  */
 static int get_periph_clock_source(enum periph_id periph_id,
-		enum clock_id parent, int *mux_bits)
+		enum clock_id parent, int *mux_bits, int *divider_bits)
 {
 	enum clock_type_id type;
 	enum periphc_internal_id internal_id;
@@ -631,11 +639,18 @@ static int get_periph_clock_source(enum periph_id periph_id,
 	type = clock_periph_type[internal_id];
 	assert(clock_type_id_isvalid(type));
 
-	/* Special case here for the clock with a 4-bit source mux */
+	/*
+	 * Special cases here for the clock with a 4-bit source mux and I2C
+	 * with its 16-bit divisor
+	 */
 	if (type == CLOCK_TYPE_PCXTS)
 		*mux_bits = 4;
 	else
 		*mux_bits = 2;
+	if (type == CLOCK_TYPE_PCMT16)
+		*divider_bits = 16;
+	else
+		*divider_bits = 8;
 
 	for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
 		if (clock_source[type][mux] == parent)
@@ -661,24 +676,22 @@ static int get_periph_clock_source(enum periph_id periph_id,
  * Adjust peripheral PLL to use the given divider and source.
  *
  * @param periph_id	peripheral to adjust
- * @param parent	Required parent clock (for source mux)
- * @param divider	Required divider in 7.1 format
+ * @param source	Source number (0-3 or 0-7)
+ * @param mux_bits	Number of mux bits (2 or 4)
+ * @param divider	Required divider in 7.1 or 15.1 format
  * @return 0 if ok, -1 on error (requesting a parent clock which is not valid
  *		for this peripheral)
  */
-static int adjust_periph_pll(enum periph_id periph_id,
-		enum clock_id parent, unsigned divider)
+static int adjust_periph_pll(enum periph_id periph_id, int source,
+			     int mux_bits, unsigned divider)
 {
 	u32 *reg = get_periph_source_reg(periph_id);
-	unsigned source;
-	int mux_bits;
 
 	clrsetbits_le32(reg, OUT_CLK_DIVISOR_MASK,
 			divider << OUT_CLK_DIVISOR_SHIFT);
 	udelay(1);
 
 	/* work out the source clock and set it */
-	source = get_periph_clock_source(periph_id, parent, &mux_bits);
 	if (source < 0)
 		return -1;
 	if (mux_bits == 4) {
@@ -696,14 +709,21 @@ unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
 		enum clock_id parent, unsigned rate, int *extra_div)
 {
 	unsigned effective_rate;
+	int mux_bits, divider_bits, source;
 	int divider;
 
+	/* work out the source clock and set it */
+	source = get_periph_clock_source(periph_id, parent, &mux_bits,
+					 &divider_bits);
+
 	if (extra_div)
-		divider = find_best_divider(pll_rate[parent], rate, extra_div);
+		divider = find_best_divider(divider_bits, pll_rate[parent],
+					    rate, extra_div);
 	else
-		divider = clk_div7_1_get_divider(pll_rate[parent], rate);
+		divider = clk_get_divider(divider_bits, pll_rate[parent],
+					  rate);
 	assert(divider >= 0);
-	if (adjust_periph_pll(periph_id, parent, divider))
+	if (adjust_periph_pll(periph_id, source, mux_bits, divider))
 		return -1U;
 	debug("periph %d, rate=%d, reg=%p = %x\n", periph_id, rate,
 		get_periph_source_reg(periph_id),
@@ -904,6 +924,77 @@ static int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon)
 	return 0;
 }
 
+void clock_ll_start_uart(enum periph_id periph_id)
+{
+	/* Assert UART reset and enable clock */
+	reset_set_enable(periph_id, 1);
+	clock_enable(periph_id);
+	clock_ll_set_source(periph_id, 0); /* UARTx_CLK_SRC = 00, PLLP_OUT0 */
+
+	/* wait for 2us */
+	udelay(2);
+
+	/* De-assert reset to UART */
+	reset_set_enable(periph_id, 0);
+}
+
+#ifdef CONFIG_OF_CONTROL
+/*
+ * Convert a device tree clock ID to our peripheral ID. They are mostly
+ * the same but we are very cautious so we check that a valid clock ID is
+ * provided.
+ *
+ * @param clk_id	Clock ID according to tegra2 device tree binding
+ * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
+ */
+static enum periph_id clk_id_to_periph_id(int clk_id)
+{
+	if (clk_id > 95)
+		return PERIPH_ID_NONE;
+
+	switch (clk_id) {
+	case 1:
+	case 2:
+	case 7:
+	case 10:
+	case 20:
+	case 30:
+	case 35:
+	case 49:
+	case 56:
+	case 74:
+	case 76:
+	case 77:
+	case 78:
+	case 79:
+	case 80:
+	case 81:
+	case 82:
+	case 83:
+	case 91:
+	case 95:
+		return PERIPH_ID_NONE;
+	default:
+		return clk_id;
+	}
+}
+
+int clock_decode_periph_id(const void *blob, int node)
+{
+	enum periph_id id;
+	u32 cell[2];
+	int err;
+
+	err = fdtdec_get_int_array(blob, node, "clocks", cell,
+				   ARRAY_SIZE(cell));
+	if (err)
+		return -1;
+	id = clk_id_to_periph_id(cell[1]);
+	assert(clock_periph_id_isvalid(id));
+	return id;
+}
+#endif /* CONFIG_OF_CONTROL */
+
 int clock_verify(void)
 {
 	struct clk_pll *pll = get_pll(CLOCK_ID_PERIPH);

arch/arm/cpu/armv7/tegra2/config.mk

@@ -29,3 +29,7 @@
 ifdef CONFIG_TEGRA2
 CFLAGS_arch/arm/lib/board.o += -march=armv4t
 endif
+
+USE_PRIVATE_LIBGCC = yes
+
+CONFIG_ARCH_DEVICE_TREE := tegra20

arch/arm/cpu/armv7/tegra2/funcmux.c

@@ -0,0 +1,184 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* Tegra2 high-level function multiplexing */
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/funcmux.h>
+#include <asm/arch/pinmux.h>
+
+int funcmux_select(enum periph_id id, int config)
+{
+	int bad_config = config != FUNCMUX_DEFAULT;
+
+	switch (id) {
+	case PERIPH_ID_UART1:
+		if (config == FUNCMUX_UART1_IRRX_IRTX) {
+			pinmux_set_func(PINGRP_IRRX, PMUX_FUNC_UARTA);
+			pinmux_set_func(PINGRP_IRTX, PMUX_FUNC_UARTA);
+			pinmux_tristate_disable(PINGRP_IRRX);
+			pinmux_tristate_disable(PINGRP_IRTX);
+			/*
+			 * Tegra appears to boot with function UARTA pre-
+			 * selected on mux group SDB. If two mux groups are
+			 * both set to the same function, it's unclear which
+			 * group's pins drive the RX signals into the HW.
+			 * For UARTA, SDB certainly overrides group IRTX in
+			 * practice. To solve this, configure some alternative
+			 * function on SDB to avoid the conflict. Also, tri-
+			 * state the group to avoid driving any signal onto it
+			 * until we know what's connected.
+			 */
+			pinmux_tristate_enable(PINGRP_SDB);
+			pinmux_set_func(PINGRP_SDB,  PMUX_FUNC_SDIO3);
+		}
+		break;
+
+	case PERIPH_ID_UART2:
+		if (config == FUNCMUX_UART2_IRDA) {
+			pinmux_set_func(PINGRP_UAD, PMUX_FUNC_IRDA);
+			pinmux_tristate_disable(PINGRP_UAD);
+		}
+		break;
+
+	case PERIPH_ID_UART4:
+		if (config == FUNCMUX_UART4_GMC) {
+			pinmux_set_func(PINGRP_GMC, PMUX_FUNC_UARTD);
+			pinmux_tristate_disable(PINGRP_GMC);
+		}
+		break;
+
+	case PERIPH_ID_DVC_I2C:
+		/* there is only one selection, pinmux_config is ignored */
+		if (config == FUNCMUX_DVC_I2CP) {
+			pinmux_set_func(PINGRP_I2CP, PMUX_FUNC_I2C);
+			pinmux_tristate_disable(PINGRP_I2CP);
+		}
+		break;
+
+	case PERIPH_ID_I2C1:
+		/* support pinmux_config of 0 for now, */
+		if (config == FUNCMUX_I2C1_RM) {
+			pinmux_set_func(PINGRP_RM, PMUX_FUNC_I2C);
+			pinmux_tristate_disable(PINGRP_RM);
+		}
+		break;
+	case PERIPH_ID_I2C2: /* I2C2 */
+		switch (config) {
+		case FUNCMUX_I2C2_DDC:	/* DDC pin group, select I2C2 */
+			pinmux_set_func(PINGRP_DDC, PMUX_FUNC_I2C2);
+			/* PTA to HDMI */
+			pinmux_set_func(PINGRP_PTA, PMUX_FUNC_HDMI);
+			pinmux_tristate_disable(PINGRP_DDC);
+			break;
+		case FUNCMUX_I2C2_PTA:	/* PTA pin group, select I2C2 */
+			pinmux_set_func(PINGRP_PTA, PMUX_FUNC_I2C2);
+			/* set DDC_SEL to RSVDx (RSVD2 works for now) */
+			pinmux_set_func(PINGRP_DDC, PMUX_FUNC_RSVD2);
+			pinmux_tristate_disable(PINGRP_PTA);
+			bad_config = 0;
+			break;
+		}
+		break;
+	case PERIPH_ID_I2C3: /* I2C3 */
+		/* support pinmux_config of 0 for now */
+		if (config == FUNCMUX_I2C3_DTF) {
+			pinmux_set_func(PINGRP_DTF, PMUX_FUNC_I2C3);
+			pinmux_tristate_disable(PINGRP_DTF);
+		}
+		break;
+
+	case PERIPH_ID_SDMMC2:
+		if (config == FUNCMUX_SDMMC2_DTA_DTD_8BIT) {
+			pinmux_set_func(PINGRP_DTA, PMUX_FUNC_SDIO2);
+			pinmux_set_func(PINGRP_DTD, PMUX_FUNC_SDIO2);
+
+			pinmux_tristate_disable(PINGRP_DTA);
+			pinmux_tristate_disable(PINGRP_DTD);
+		}
+		break;
+
+	case PERIPH_ID_SDMMC3:
+		switch (config) {
+		case FUNCMUX_SDMMC3_SDB_SLXA_8BIT:
+			pinmux_set_func(PINGRP_SLXA, PMUX_FUNC_SDIO3);
+			pinmux_set_func(PINGRP_SLXC, PMUX_FUNC_SDIO3);
+			pinmux_set_func(PINGRP_SLXD, PMUX_FUNC_SDIO3);
+			pinmux_set_func(PINGRP_SLXK, PMUX_FUNC_SDIO3);
+
+			pinmux_tristate_disable(PINGRP_SLXA);
+			pinmux_tristate_disable(PINGRP_SLXC);
+			pinmux_tristate_disable(PINGRP_SLXD);
+			pinmux_tristate_disable(PINGRP_SLXK);
+			/* fall through */
+
+		case FUNCMUX_SDMMC3_SDB_4BIT:
+			pinmux_set_func(PINGRP_SDB, PMUX_FUNC_SDIO3);
+			pinmux_set_func(PINGRP_SDC, PMUX_FUNC_SDIO3);
+			pinmux_set_func(PINGRP_SDD, PMUX_FUNC_SDIO3);
+
+			pinmux_tristate_disable(PINGRP_SDB);
+			pinmux_tristate_disable(PINGRP_SDC);
+			pinmux_tristate_disable(PINGRP_SDD);
+			bad_config = 0;
+			break;
+		}
+		break;
+
+	case PERIPH_ID_SDMMC4:
+		switch (config) {
+		case FUNCMUX_SDMMC4_ATC_ATD_8BIT:
+			pinmux_set_func(PINGRP_ATC, PMUX_FUNC_SDIO4);
+			pinmux_set_func(PINGRP_ATD, PMUX_FUNC_SDIO4);
+
+			pinmux_tristate_disable(PINGRP_ATC);
+			pinmux_tristate_disable(PINGRP_ATD);
+			break;
+
+		case FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT:
+			pinmux_set_func(PINGRP_GME, PMUX_FUNC_SDIO4);
+			pinmux_tristate_disable(PINGRP_GME);
+			/* fall through */
+
+		case FUNCMUX_SDMMC4_ATB_GMA_4_BIT:
+			pinmux_set_func(PINGRP_ATB, PMUX_FUNC_SDIO4);
+			pinmux_set_func(PINGRP_GMA, PMUX_FUNC_SDIO4);
+
+			pinmux_tristate_disable(PINGRP_ATB);
+			pinmux_tristate_disable(PINGRP_GMA);
+			bad_config = 0;
+			break;
+		}
+		break;
+
+	default:
+		debug("%s: invalid periph_id %d", __func__, id);
+		return -1;
+	}
+
+	if (bad_config) {
+		debug("%s: invalid config %d for periph_id %d", __func__,
+		      config, id);
+		return -1;
+	}
+
+	return 0;
+}

arch/arm/cpu/armv7/tegra2/usb.c

@@ -0,0 +1,460 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2010,2011 NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm-generic/gpio.h>
+#include <asm/arch/tegra2.h>
+#include <asm/arch/clk_rst.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/uart.h>
+#include <asm/arch/usb.h>
+#include <libfdt.h>
+#include <fdtdec.h>
+
+enum {
+	USB_PORTS_MAX	= 4,			/* Maximum ports we allow */
+};
+
+/* Parameters we need for USB */
+enum {
+	PARAM_DIVN,                     /* PLL FEEDBACK DIVIDer */
+	PARAM_DIVM,                     /* PLL INPUT DIVIDER */
+	PARAM_DIVP,                     /* POST DIVIDER (2^N) */
+	PARAM_CPCON,                    /* BASE PLLC CHARGE Pump setup ctrl */
+	PARAM_LFCON,                    /* BASE PLLC LOOP FILter setup ctrl */
+	PARAM_ENABLE_DELAY_COUNT,       /* PLL-U Enable Delay Count */
+	PARAM_STABLE_COUNT,             /* PLL-U STABLE count */
+	PARAM_ACTIVE_DELAY_COUNT,       /* PLL-U Active delay count */
+	PARAM_XTAL_FREQ_COUNT,          /* PLL-U XTAL frequency count */
+	PARAM_DEBOUNCE_A_TIME,          /* 10MS DELAY for BIAS_DEBOUNCE_A */
+	PARAM_BIAS_TIME,                /* 20US DELAY AFter bias cell op */
+
+	PARAM_COUNT
+};
+
+/* Possible port types (dual role mode) */
+enum dr_mode {
+	DR_MODE_NONE = 0,
+	DR_MODE_HOST,		/* supports host operation */
+	DR_MODE_DEVICE,		/* supports device operation */
+	DR_MODE_OTG,		/* supports both */
+};
+
+/* Information about a USB port */
+struct fdt_usb {
+	struct usb_ctlr *reg;	/* address of registers in physical memory */
+	unsigned utmi:1;	/* 1 if port has external tranceiver, else 0 */
+	unsigned enabled:1;	/* 1 to enable, 0 to disable */
+	unsigned has_legacy_mode:1; /* 1 if this port has legacy mode */
+	enum dr_mode dr_mode;	/* dual role mode */
+	enum periph_id periph_id;/* peripheral id */
+	struct fdt_gpio_state vbus_gpio;	/* GPIO for vbus enable */
+};
+
+static struct fdt_usb port[USB_PORTS_MAX];	/* List of valid USB ports */
+static unsigned port_count;			/* Number of available ports */
+static int port_current;			/* Current port (-1 = none) */
+
+/*
+ * This table has USB timing parameters for each Oscillator frequency we
+ * support. There are four sets of values:
+ *
+ * 1. PLLU configuration information (reference clock is osc/clk_m and
+ * PLLU-FOs are fixed at 12MHz/60MHz/480MHz).
+ *
+ *  Reference frequency     13.0MHz      19.2MHz      12.0MHz      26.0MHz
+ *  ----------------------------------------------------------------------
+ *      DIVN                960 (0x3c0)  200 (0c8)    960 (3c0h)   960 (3c0)
+ *      DIVM                13 (0d)      4 (04)       12 (0c)      26 (1a)
+ * Filter frequency (MHz)   1            4.8          6            2
+ * CPCON                    1100b        0011b        1100b        1100b
+ * LFCON0                   0            0            0            0
+ *
+ * 2. PLL CONFIGURATION & PARAMETERS for different clock generators:
+ *
+ * Reference frequency     13.0MHz         19.2MHz         12.0MHz     26.0MHz
+ * ---------------------------------------------------------------------------
+ * PLLU_ENABLE_DLY_COUNT   02 (0x02)       03 (03)         02 (02)     04 (04)
+ * PLLU_STABLE_COUNT       51 (33)         75 (4B)         47 (2F)    102 (66)
+ * PLL_ACTIVE_DLY_COUNT    05 (05)         06 (06)         04 (04)     09 (09)
+ * XTAL_FREQ_COUNT        127 (7F)        187 (BB)        118 (76)    254 (FE)
+ *
+ * 3. Debounce values IdDig, Avalid, Bvalid, VbusValid, VbusWakeUp, and
+ * SessEnd. Each of these signals have their own debouncer and for each of
+ * those one out of two debouncing times can be chosen (BIAS_DEBOUNCE_A or
+ * BIAS_DEBOUNCE_B).
+ *
+ * The values of DEBOUNCE_A and DEBOUNCE_B are calculated as follows:
+ *    0xffff -> No debouncing at all
+ *    <n> ms = <n> *1000 / (1/19.2MHz) / 4
+ *
+ * So to program a 1 ms debounce for BIAS_DEBOUNCE_A, we have:
+ * BIAS_DEBOUNCE_A[15:0] = 1000 * 19.2 / 4  = 4800 = 0x12c0
+ *
+ * We need to use only DebounceA for BOOTROM. We don't need the DebounceB
+ * values, so we can keep those to default.
+ *
+ * 4. The 20 microsecond delay after bias cell operation.
+ */
+static const unsigned usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = {
+	/* DivN, DivM, DivP, CPCON, LFCON, Delays             Debounce, Bias */
+	{ 0x3C0, 0x0D, 0x00, 0xC,   0,  0x02, 0x33, 0x05, 0x7F, 0x7EF4, 5 },
+	{ 0x0C8, 0x04, 0x00, 0x3,   0,  0x03, 0x4B, 0x06, 0xBB, 0xBB80, 7 },
+	{ 0x3C0, 0x0C, 0x00, 0xC,   0,  0x02, 0x2F, 0x04, 0x76, 0x7530, 5 },
+	{ 0x3C0, 0x1A, 0x00, 0xC,   0,  0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 }
+};
+
+/* UTMIP Idle Wait Delay */
+static const u8 utmip_idle_wait_delay = 17;
+
+/* UTMIP Elastic limit */
+static const u8 utmip_elastic_limit = 16;
+
+/* UTMIP High Speed Sync Start Delay */
+static const u8 utmip_hs_sync_start_delay = 9;
+
+/* Put the port into host mode (this only works for OTG ports) */
+static void set_host_mode(struct fdt_usb *config)
+{
+	if (config->dr_mode == DR_MODE_OTG) {
+		/* Check whether remote host from USB1 is driving VBus */
+		if (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS)
+			return;
+
+		/*
+		 * If not driving, we set the GPIO to enable VBUS. We assume
+		 * that the pinmux is set up correctly for this.
+		 */
+		if (fdt_gpio_isvalid(&config->vbus_gpio)) {
+			fdtdec_setup_gpio(&config->vbus_gpio);
+			gpio_direction_output(config->vbus_gpio.gpio, 1);
+			debug("set_host_mode: GPIO %d high\n",
+			      config->vbus_gpio.gpio);
+		}
+	}
+}
+
+void usbf_reset_controller(struct fdt_usb *config, struct usb_ctlr *usbctlr)
+{
+	/* Reset the USB controller with 2us delay */
+	reset_periph(config->periph_id, 2);
+
+	/*
+	 * Set USB1_NO_LEGACY_MODE to 1, Registers are accessible under
+	 * base address
+	 */
+	if (config->has_legacy_mode)
+		setbits_le32(&usbctlr->usb1_legacy_ctrl, USB1_NO_LEGACY_MODE);
+
+	/* Put UTMIP1/3 in reset */
+	setbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET);
+
+	/* Enable the UTMIP PHY */
+	if (config->utmi)
+		setbits_le32(&usbctlr->susp_ctrl, UTMIP_PHY_ENB);
+
+	/*
+	 * TODO: where do we take the USB1 out of reset? The old code would
+	 * take USB3 out of reset, but not USB1. This code doesn't do either.
+	 */
+}
+
+/* set up the USB controller with the parameters provided */
+static int init_usb_controller(struct fdt_usb *config,
+				struct usb_ctlr *usbctlr, const u32 timing[])
+{
+	u32 val;
+	int loop_count;
+
+	clock_enable(config->periph_id);
+
+	/* Reset the usb controller */
+	usbf_reset_controller(config, usbctlr);
+
+	/* Stop crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN low */
+	clrbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN);
+
+	/* Follow the crystal clock disable by >100ns delay */
+	udelay(1);
+
+	/*
+	 * To Use the A Session Valid for cable detection logic, VBUS_WAKEUP
+	 * mux must be switched to actually use a_sess_vld threshold.
+	 */
+	if (fdt_gpio_isvalid(&config->vbus_gpio)) {
+		clrsetbits_le32(&usbctlr->usb1_legacy_ctrl,
+			VBUS_SENSE_CTL_MASK,
+			VBUS_SENSE_CTL_A_SESS_VLD << VBUS_SENSE_CTL_SHIFT);
+	}
+
+	/*
+	 * PLL Delay CONFIGURATION settings. The following parameters control
+	 * the bring up of the plls.
+	 */
+	val = readl(&usbctlr->utmip_misc_cfg1);
+	clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK,
+		timing[PARAM_STABLE_COUNT] << UTMIP_PLLU_STABLE_COUNT_SHIFT);
+	clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK,
+		timing[PARAM_ACTIVE_DELAY_COUNT] <<
+			UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT);
+	writel(val, &usbctlr->utmip_misc_cfg1);
+
+	/* Set PLL enable delay count and crystal frequency count */
+	val = readl(&usbctlr->utmip_pll_cfg1);
+	clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK,
+		timing[PARAM_ENABLE_DELAY_COUNT] <<
+			UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT);
+	clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK,
+		timing[PARAM_XTAL_FREQ_COUNT] <<
+			UTMIP_XTAL_FREQ_COUNT_SHIFT);
+	writel(val, &usbctlr->utmip_pll_cfg1);
+
+	/* Setting the tracking length time */
+	clrsetbits_le32(&usbctlr->utmip_bias_cfg1,
+		UTMIP_BIAS_PDTRK_COUNT_MASK,
+		timing[PARAM_BIAS_TIME] << UTMIP_BIAS_PDTRK_COUNT_SHIFT);
+
+	/* Program debounce time for VBUS to become valid */
+	clrsetbits_le32(&usbctlr->utmip_debounce_cfg0,
+		UTMIP_DEBOUNCE_CFG0_MASK,
+		timing[PARAM_DEBOUNCE_A_TIME] << UTMIP_DEBOUNCE_CFG0_SHIFT);
+
+	setbits_le32(&usbctlr->utmip_tx_cfg0, UTMIP_FS_PREAMBLE_J);
+
+	/* Disable battery charge enabling bit */
+	setbits_le32(&usbctlr->utmip_bat_chrg_cfg0, UTMIP_PD_CHRG);
+
+	clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_XCVR_LSBIAS_SE);
+	setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL);
+
+	/*
+	 * Configure the UTMIP_IDLE_WAIT and UTMIP_ELASTIC_LIMIT
+	 * Setting these fields, together with default values of the
+	 * other fields, results in programming the registers below as
+	 * follows:
+	 *         UTMIP_HSRX_CFG0 = 0x9168c000
+	 *         UTMIP_HSRX_CFG1 = 0x13
+	 */
+
+	/* Set PLL enable delay count and Crystal frequency count */
+	val = readl(&usbctlr->utmip_hsrx_cfg0);
+	clrsetbits_le32(&val, UTMIP_IDLE_WAIT_MASK,
+		utmip_idle_wait_delay << UTMIP_IDLE_WAIT_SHIFT);
+	clrsetbits_le32(&val, UTMIP_ELASTIC_LIMIT_MASK,
+		utmip_elastic_limit << UTMIP_ELASTIC_LIMIT_SHIFT);
+	writel(val, &usbctlr->utmip_hsrx_cfg0);
+
+	/* Configure the UTMIP_HS_SYNC_START_DLY */
+	clrsetbits_le32(&usbctlr->utmip_hsrx_cfg1,
+		UTMIP_HS_SYNC_START_DLY_MASK,
+		utmip_hs_sync_start_delay << UTMIP_HS_SYNC_START_DLY_SHIFT);
+
+	/* Preceed the crystal clock disable by >100ns delay. */
+	udelay(1);
+
+	/* Resuscitate crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN */
+	setbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN);
+
+	/* Finished the per-controller init. */
+
+	/* De-assert UTMIP_RESET to bring out of reset. */
+	clrbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET);
+
+	/* Wait for the phy clock to become valid in 100 ms */
+	for (loop_count = 100000; loop_count != 0; loop_count--) {
+		if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID)
+			break;
+		udelay(1);
+	}
+	if (loop_count == 100000)
+		return -1;
+
+	return 0;
+}
+
+static void power_up_port(struct usb_ctlr *usbctlr)
+{
+	/* Deassert power down state */
+	clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN |
+		UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN);
+	clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN |
+		UTMIP_FORCE_PDCHRP_POWERDOWN | UTMIP_FORCE_PDDR_POWERDOWN);
+}
+
+static void config_clock(const u32 timing[])
+{
+	clock_start_pll(CLOCK_ID_USB,
+		timing[PARAM_DIVM], timing[PARAM_DIVN], timing[PARAM_DIVP],
+		timing[PARAM_CPCON], timing[PARAM_LFCON]);
+}
+
+/**
+ * Add a new USB port to the list of available ports.
+ *
+ * @param config	USB port configuration
+ * @return 0 if ok, -1 if error (too many ports)
+ */
+static int add_port(struct fdt_usb *config, const u32 timing[])
+{
+	struct usb_ctlr *usbctlr = config->reg;
+
+	if (port_count == USB_PORTS_MAX) {
+		debug("tegrausb: Cannot register more than %d ports\n",
+		      USB_PORTS_MAX);
+		return -1;
+	}
+	if (init_usb_controller(config, usbctlr, timing)) {
+		debug("tegrausb: Cannot init port\n");
+		return -1;
+	}
+	if (config->utmi) {
+		/* Disable ICUSB FS/LS transceiver */
+		clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1);
+
+		/* Select UTMI parallel interface */
+		clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
+				PTS_UTMI << PTS_SHIFT);
+		clrbits_le32(&usbctlr->port_sc1, STS);
+		power_up_port(usbctlr);
+	}
+	port[port_count++] = *config;
+
+	return 0;
+}
+
+int tegrausb_start_port(unsigned portnum, u32 *hccr, u32 *hcor)
+{
+	struct usb_ctlr *usbctlr;
+
+	if (portnum >= port_count)
+		return -1;
+	tegrausb_stop_port();
+	set_host_mode(&port[portnum]);
+
+	usbctlr = port[portnum].reg;
+	*hccr = (u32)&usbctlr->cap_length;
+	*hcor = (u32)&usbctlr->usb_cmd;
+	port_current = portnum;
+	return 0;
+}
+
+int tegrausb_stop_port(void)
+{
+	struct usb_ctlr *usbctlr;
+
+	if (port_current == -1)
+		return -1;
+
+	usbctlr = port[port_current].reg;
+
+	/* Stop controller */
+	writel(0, &usbctlr->usb_cmd);
+	udelay(1000);
+
+	/* Initiate controller reset */
+	writel(2, &usbctlr->usb_cmd);
+	udelay(1000);
+	port_current = -1;
+	return 0;
+}
+
+int fdt_decode_usb(const void *blob, int node, unsigned osc_frequency_mhz,
+		   struct fdt_usb *config)
+{
+	const char *phy, *mode;
+
+	config->reg = (struct usb_ctlr *)fdtdec_get_addr(blob, node, "reg");
+	mode = fdt_getprop(blob, node, "dr_mode", NULL);
+	if (mode) {
+		if (0 == strcmp(mode, "host"))
+			config->dr_mode = DR_MODE_HOST;
+		else if (0 == strcmp(mode, "peripheral"))
+			config->dr_mode = DR_MODE_DEVICE;
+		else if (0 == strcmp(mode, "otg"))
+			config->dr_mode = DR_MODE_OTG;
+		else {
+			debug("%s: Cannot decode dr_mode '%s'\n", __func__,
+			      mode);
+			return -FDT_ERR_NOTFOUND;
+		}
+	} else {
+		config->dr_mode = DR_MODE_HOST;
+	}
+
+	phy = fdt_getprop(blob, node, "phy_type", NULL);
+	config->utmi = phy && 0 == strcmp("utmi", phy);
+	config->enabled = fdtdec_get_is_enabled(blob, node);
+	config->has_legacy_mode = fdtdec_get_bool(blob, node,
+						  "nvidia,has-legacy-mode");
+	config->periph_id = clock_decode_periph_id(blob, node);
+	if (config->periph_id == PERIPH_ID_NONE) {
+		debug("%s: Missing/invalid peripheral ID\n", __func__);
+		return -FDT_ERR_NOTFOUND;
+	}
+	fdtdec_decode_gpio(blob, node, "nvidia,vbus-gpio", &config->vbus_gpio);
+	debug("enabled=%d, legacy_mode=%d, utmi=%d, periph_id=%d, vbus=%d, "
+	      "dr_mode=%d\n", config->enabled, config->has_legacy_mode,
+	      config->utmi, config->periph_id, config->vbus_gpio.gpio,
+	      config->dr_mode);
+
+	return 0;
+}
+
+int board_usb_init(const void *blob)
+{
+	struct fdt_usb config;
+	unsigned osc_freq = clock_get_rate(CLOCK_ID_OSC);
+	enum clock_osc_freq freq;
+	int node_list[USB_PORTS_MAX];
+	int node, count, i;
+
+	/* Set up the USB clocks correctly based on our oscillator frequency */
+	freq = clock_get_osc_freq();
+	config_clock(usb_pll[freq]);
+
+	/* count may return <0 on error */
+	count = fdtdec_find_aliases_for_id(blob, "usb",
+			COMPAT_NVIDIA_TEGRA20_USB, node_list, USB_PORTS_MAX);
+	for (i = 0; i < count; i++) {
+		debug("USB %d: ", i);
+		node = node_list[i];
+		if (!node)
+			continue;
+		if (fdt_decode_usb(blob, node, osc_freq, &config)) {
+			debug("Cannot decode USB node %s\n",
+			      fdt_get_name(blob, node, NULL));
+			return -1;
+		}
+
+		if (add_port(&config, usb_pll[freq]))
+			return -1;
+		set_host_mode(&config);
+	}
+	port_current = -1;
+
+	return 0;
+}

arch/arm/cpu/ixp/config.mk

@@ -28,6 +28,9 @@ PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float -mbig-endian
 
 PLATFORM_CPPFLAGS += -mbig-endian -march=armv5te -mtune=strongarm1100
 
+PLATFORM_LDFLAGS += -EB
+USE_PRIVATE_LIBGCC = yes
+
 # -fdata-sections triggers "section .bss overlaps section .rel.dyn" linker error
 PLATFORM_RELFLAGS += -ffunction-sections
 LDFLAGS_u-boot += --gc-sections

arch/arm/cpu/ixp/npe/IxEthAcc.c

@@ -102,7 +102,7 @@ PUBLIC IxEthAccStatus ixEthAccInit()
   /*
    * Initialize Control plane
    */
-  if (ixEthDBInit() != IX_ETH_ACC_SUCCESS)
+  if (ixEthDBInit() != IX_ETH_DB_SUCCESS)
   {
       IX_ETH_ACC_WARNING_LOG("ixEthAccInit: EthDB init failed\n", 0, 0, 0, 0, 0, 0);
 

arch/arm/cpu/ixp/npe/IxEthDBAPISupport.c

@@ -630,7 +630,6 @@ IX_ETH_DB_PUBLIC
 IxEthDBStatus ixEthDBPortAddressSet(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
 {
     IxNpeMhMessage message;
-    IxOsalMutex *ackPortAddressLock;
     IX_STATUS result;
 
     /* use this macro instead CHECK_PORT
@@ -644,8 +643,6 @@ IxEthDBStatus ixEthDBPortAddressSet(IxEthDBPortId portID, IxEthDBMacAddr *macAdd
         return IX_ETH_DB_PORT_UNINITIALIZED;
     }
 
-    ackPortAddressLock = &ixEthDBPortInfo[portID].npeAckLock;
-
     /* Operation stops here when Ethernet Learning is not enabled */
     if(IX_FEATURE_CTRL_SWCONFIG_DISABLED ==
        ixFeatureCtrlSwConfigurationCheck(IX_FEATURECTRL_ETH_LEARNING))

arch/arm/cpu/ixp/npe/IxQMgrDispatcher.c

@@ -1191,7 +1191,6 @@ ixQMgrLLPShow (int resetStats)
 {
 #ifndef NDEBUG
     UINT8 i = 0;
-    IxQMgrQInfo *q;
     UINT32 intEnableRegVal = 0;
 
     printf ("Livelock statistics are printed on the fly.\n");
@@ -1200,8 +1199,6 @@ ixQMgrLLPShow (int resetStats)
 
     for (i=0; i<= IX_QMGR_MAX_LOW_QUE_TABLE_INDEX; i++)
     {
-        q = &dispatchQInfo[i];
-
         if (ixQMgrQTypes[i] != IX_QMGR_TYPE_REALTIME_OTHER)
         {
             printf (" %2d ", i);

arch/arm/cpu/lh7a40x/u-boot.lds

@@ -1,80 +0,0 @@
-/*
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text :
-	{
-		arch/arm/cpu/lh7a40x/start.o	(.text)
-		*(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-	. = ALIGN(4);
-	.data : {
-		*(.data)
-	}
-
-	. = ALIGN(4);
-
-	. = .;
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
-
-	. = ALIGN(4);
-
-	.rel.dyn : {
-		__rel_dyn_start = .;
-		*(.rel*)
-		__rel_dyn_end = .;
-	}
-
-	.dynsym : {
-		__dynsym_start = .;
-		*(.dynsym)
-	}
-
-	_end = .;
-
-	.bss __rel_dyn_start (OVERLAY) : {
-		__bss_start = .;
-		*(.bss)
-		 . = ALIGN(4);
-		__bss_end__ = .;
-	}
-
-	/DISCARD/ : { *(.dynstr*) }
-	/DISCARD/ : { *(.dynamic*) }
-	/DISCARD/ : { *(.plt*) }
-	/DISCARD/ : { *(.interp*) }
-	/DISCARD/ : { *(.gnu*) }
-}

arch/arm/cpu/pxa/timer.c

@@ -94,3 +94,8 @@ void __udelay(unsigned long usec)
 	while (get_ticks() < tmp)	/* loop till event */
 		 /*NOP*/;
 }
+
+ulong get_tbclk(void)
+{
+	return TIMER_FREQ_HZ;
+}

arch/arm/cpu/pxa/u-boot.lds

@@ -1,86 +0,0 @@
-/*
- * (C) Copyright 2000-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text :
-	{
-		arch/arm/cpu/pxa/start.o	(.text)
-		*(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-	. = ALIGN(4);
-	.data : {
-		*(.data)
-	}
-
-	. = ALIGN(4);
-
-	. = .;
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
-
-	. = ALIGN(4);
-
-	.rel.dyn : {
-		__rel_dyn_start = .;
-		*(.rel*)
-		__rel_dyn_end = .;
-	}
-
-	.dynsym : {
-		__dynsym_start = .;
-		*(.dynsym)
-	}
-
-	. = ALIGN(4096);
-
-	.mmutable : {
-		*(.mmutable)
-	}
-
-	_end = .;
-
-	.bss __rel_dyn_start (OVERLAY) : {
-		__bss_start = .;
-		*(.bss)
-		 . = ALIGN(4);
-		__bss_end__ = .;
-	}
-
-	/DISCARD/ : { *(.dynstr*) }
-	/DISCARD/ : { *(.dynamic*) }
-	/DISCARD/ : { *(.plt*) }
-	/DISCARD/ : { *(.interp*) }
-	/DISCARD/ : { *(.gnu*) }
-}