Prepare v2012.07-rc2

Signed-off-by: Wolfgang Denk <wd@denx.de>

Makefile

@@ -24,7 +24,7 @@
 VERSION = 2012
 PATCHLEVEL = 07
 SUBLEVEL =
-EXTRAVERSION = -rc1
+EXTRAVERSION = -rc2
 ifneq "$(SUBLEVEL)" ""
 U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
 else

arch/arm/cpu/arm1136/cpu.c

@@ -95,7 +95,7 @@ void flush_dcache_all(void)
 	asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
 }
 
-static inline int bad_cache_range(unsigned long start, unsigned long stop)
+static int check_cache_range(unsigned long start, unsigned long stop)
 {
 	int ok = 1;
 
@@ -114,7 +114,7 @@ static inline int bad_cache_range(unsigned long start, unsigned long stop)
 
 void invalidate_dcache_range(unsigned long start, unsigned long stop)
 {
-	if (bad_cache_range(start, stop))
+	if (!check_cache_range(start, stop))
 		return;
 
 	while (start < stop) {
@@ -125,7 +125,7 @@ void invalidate_dcache_range(unsigned long start, unsigned long stop)
 
 void flush_dcache_range(unsigned long start, unsigned long stop)
 {
-	if (bad_cache_range(start, stop))
+	if (!check_cache_range(start, stop))
 		return;
 
 	while (start < stop) {

arch/arm/cpu/arm1136/start.S

@@ -251,10 +251,12 @@ clear_bss:
 	add	r1, r1, r4
 	mov	r2, #0x00000000		/* clear			    */
 
-clbss_l:str	r2, [r0]		/* clear loop...		    */
+clbss_l:cmp	r0, r1			/* clear loop... */
+	bhs	clbss_e			/* if reached end of bss, exit */
+	str	r2, [r0]
 	add	r0, r0, #4
-	cmp	r0, r1
-	bne	clbss_l
+	b	clbss_l
+clbss_e:
 #endif	/* #ifndef CONFIG_SPL_BUILD */
 
 /*

arch/arm/cpu/arm1176/start.S

@@ -351,11 +351,12 @@ clear_bss:
 	add	r1, r1, r4
 	mov	r2, #0x00000000		/* clear			    */
 
-clbss_l:str	r2, [r0]		/* clear loop...		    */
+clbss_l:cmp	r0, r1			/* clear loop... */
+	bhs	clbss_e			/* if reached end of bss, exit */
+	str	r2, [r0]
 	add	r0, r0, #4
-	cmp	r0, r1
-	bne	clbss_l
-
+	b	clbss_l
+clbss_e:
 #ifndef CONFIG_NAND_SPL
 	bl coloured_LED_init
 	bl red_led_on

arch/arm/cpu/arm720t/start.S

@@ -228,10 +228,12 @@ clear_bss:
 	add	r1, r1, r4
 	mov	r2, #0x00000000		/* clear			    */
 
-clbss_l:str	r2, [r0]		/* clear loop...		    */
+clbss_l:cmp	r0, r1			/* clear loop... */
+	bhs	clbss_e			/* if reached end of bss, exit */
+	str	r2, [r0]
 	add	r0, r0, #4
-	cmp	r0, r1
-	bne	clbss_l
+	b	clbss_l
+clbss_e:
 
 	bl coloured_LED_init
 	bl red_led_on

arch/arm/cpu/arm920t/start.S

@@ -271,10 +271,12 @@ clear_bss:
 	add	r1, r1, r4
 	mov	r2, #0x00000000		/* clear			    */
 
-clbss_l:str	r2, [r0]		/* clear loop...		    */
+clbss_l:cmp	r0, r1			/* clear loop... */
+	bhs	clbss_e			/* if reached end of bss, exit */
+	str	r2, [r0]
 	add	r0, r0, #4
-	cmp	r0, r1
-	bne	clbss_l
+	b	clbss_l
+clbss_e:
 
 	bl coloured_LED_init
 	bl red_led_on

arch/arm/cpu/arm925t/start.S

@@ -265,10 +265,12 @@ clear_bss:
 	add	r1, r1, r4
 	mov	r2, #0x00000000		/* clear			    */
 
-clbss_l:str	r2, [r0]		/* clear loop...		    */
+clbss_l:cmp	r0, r1			/* clear loop... */
+	bhs	clbss_e			/* if reached end of bss, exit */
+	str	r2, [r0]
 	add	r0, r0, #4
-	cmp	r0, r1
-	bne	clbss_l
+	b	clbss_l
+clbss_e:
 
 	bl coloured_LED_init
 	bl red_led_on

arch/arm/cpu/arm946es/start.S

@@ -236,10 +236,12 @@ clear_bss:
 	add	r1, r1, r4
 	mov	r2, #0x00000000		/* clear			    */
 
-clbss_l:str	r2, [r0]		/* clear loop...		    */
+clbss_l:cmp	r0, r1			/* clear loop... */
+	bhs	clbss_e			/* if reached end of bss, exit */
+	str	r2, [r0]
 	add	r0, r0, #4
-	cmp	r0, r1
-	blo	clbss_l
+	b	clbss_l
+clbss_e:
 #endif
 
 /*

arch/arm/cpu/arm_intcm/start.S

@@ -232,10 +232,12 @@ clear_bss:
 	add	r1, r1, r4
 	mov	r2, #0x00000000		/* clear			    */
 
-clbss_l:str	r2, [r0]		/* clear loop...		    */
+clbss_l:cmp	r0, r1			/* clear loop... */
+	bhs	clbss_e			/* if reached end of bss, exit */
+	str	r2, [r0]
 	add	r0, r0, #4
-	cmp	r0, r1
-	bne	clbss_l
+	b	clbss_l
+clbss_e:
 
 	bl coloured_LED_init
 	bl red_led_on

arch/arm/cpu/armv7/config.mk

@@ -26,6 +26,8 @@ PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
 # supported by more tool-chains
 PF_CPPFLAGS_ARMV7 := $(call cc-option, -march=armv7-a, -march=armv5)
 PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_ARMV7)
+PF_CPPFLAGS_NO_UNALIGNED := $(call cc-option, -mno-unaligned-access,)
+PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_NO_UNALIGNED)
 
 # =========================================================================
 #

arch/arm/cpu/armv7/start.S

@@ -259,10 +259,12 @@ clear_bss:
 #endif
 	mov	r2, #0x00000000		/* clear			    */
 
-clbss_l:str	r2, [r0]		/* clear loop...		    */
+clbss_l:cmp	r0, r1			/* clear loop... */
+	bhs	clbss_e			/* if reached end of bss, exit */
+	str	r2, [r0]
 	add	r0, r0, #4
-	cmp	r0, r1
-	bne	clbss_l
+	b	clbss_l
+clbss_e:
 
 /*
  * We are done. Do not return, instead branch to second part of board

arch/arm/cpu/ixp/start.S

@@ -334,10 +334,12 @@ clear_bss:
 	add	r1, r1, r4
 	mov	r2, #0x00000000		/* clear			    */
 
-clbss_l:str	r2, [r0]		/* clear loop...		    */
+clbss_l:cmp	r0, r1			/* clear loop... */
+	bhs	clbss_e			/* if reached end of bss, exit */
+	str	r2, [r0]
 	add	r0, r0, #4
-	cmp	r0, r1
-	bne	clbss_l
+	b	clbss_l
+clbss_e:
 
 	bl coloured_LED_init
 	bl red_led_on

arch/arm/cpu/lh7a40x/start.S

@@ -245,10 +245,12 @@ clear_bss:
 	add	r1, r1, r4
 	mov	r2, #0x00000000		/* clear			    */
 
-clbss_l:str	r2, [r0]		/* clear loop...		    */
+clbss_l:cmp	r0, r1			/* clear loop... */
+	bhs	clbss_e			/* if reached end of bss, exit */
+	str	r2, [r0]
 	add	r0, r0, #4
-	cmp	r0, r1
-	bne	clbss_l
+	b	clbss_l
+clbss_e:
 #endif
 
 /*

arch/arm/cpu/pxa/start.S

@@ -258,10 +258,12 @@ clear_bss:
 	add	r1, r1, r4
 	mov	r2, #0x00000000		/* clear			    */
 
-clbss_l:str	r2, [r0]		/* clear loop...		    */
+clbss_l:cmp	r0, r1			/* clear loop... */
+	bhs	clbss_e			/* if reached end of bss, exit */
+	str	r2, [r0]
 	add	r0, r0, #4
-	cmp	r0, r1
-	bne	clbss_l
+	b	clbss_l
+clbss_e:
 #endif	/* #ifndef CONFIG_SPL_BUILD */
 
 /*

arch/arm/cpu/s3c44b0/start.S

@@ -217,10 +217,12 @@ clear_bss:
 	add	r1, r1, r4
 	mov	r2, #0x00000000		/* clear			    */
 
-clbss_l:str	r2, [r0]		/* clear loop...		    */
+clbss_l:cmp	r0, r1			/* clear loop... */
+	bhs	clbss_e			/* if reached end of bss, exit */
+	str	r2, [r0]
 	add	r0, r0, #4
-	cmp	r0, r1
-	bne	clbss_l
+	b	clbss_l
+clbss_e:
 
 	bl coloured_LED_init
 	bl red_led_on

arch/arm/cpu/sa1100/start.S

@@ -221,10 +221,12 @@ clear_bss:
 	add	r1, r1, r4
 	mov	r2, #0x00000000		/* clear			    */
 
-clbss_l:str	r2, [r0]		/* clear loop...		    */
+clbss_l:cmp	r0, r1			/* clear loop... */
+	bhs	clbss_e			/* if reached end of bss, exit */
+	str	r2, [r0]
 	add	r0, r0, #4
-	cmp	r0, r1
-	bne	clbss_l
+	b	clbss_l
+clbss_e:
 #endif
 
 /*

arch/arm/include/asm/arch-mx31/imx-regs.h

@@ -606,6 +606,13 @@ struct esdc_regs {
 #define UART4_BASE	0x43FB0000
 #define UART5_BASE	0x43FB4000
 
+#define I2C1_BASE_ADDR          0x43f80000
+#define I2C1_CLK_OFFSET		26
+#define I2C2_BASE_ADDR          0x43F98000
+#define I2C2_CLK_OFFSET		28
+#define I2C3_BASE_ADDR          0x43f84000
+#define I2C3_CLK_OFFSET		30
+
 #define ESDCTL_SDE			(1 << 31)
 #define ESDCTL_CMD_RW			(0 << 28)
 #define ESDCTL_CMD_PRECHARGE		(1 << 28)

arch/arm/include/asm/arch-mx35/imx-regs.h

@@ -39,7 +39,7 @@
 #define MAX_BASE_ADDR           0x43F04000
 #define EVTMON_BASE_ADDR        0x43F08000
 #define CLKCTL_BASE_ADDR        0x43F0C000
-#define I2C_BASE_ADDR           0x43F80000
+#define I2C1_BASE_ADDR		0x43F80000
 #define I2C3_BASE_ADDR          0x43F84000
 #define ATA_BASE_ADDR           0x43F8C000
 #define UART1_BASE		0x43F90000

arch/arm/include/asm/arch-mx5/imx-regs.h

@@ -50,8 +50,6 @@
 #error "CPU_TYPE not defined"
 #endif
 
-#define IPU_CTRL_BASE_ADDR	IPU_SOC_BASE_ADDR + IPU_SOC_OFFSET
-
 #define IRAM_SIZE		0x00020000	/* 128 KB */
 
 /*

arch/arm/include/asm/arch-mx6/imx-regs.h

@@ -73,6 +73,9 @@
 #define MMDC1_ARB_BASE_ADDR             0x80000000
 #define MMDC1_ARB_END_ADDR              0xFFFFFFFF
 
+#define IPU_SOC_BASE_ADDR		IPU1_ARB_BASE_ADDR
+#define IPU_SOC_OFFSET			0x00200000
+
 /* Defines for Blocks connected via AIPS (SkyBlue) */
 #define ATZ1_BASE_ADDR              AIPS1_ARB_BASE_ADDR
 #define ATZ2_BASE_ADDR              AIPS2_ARB_BASE_ADDR

arch/arm/include/asm/arch-mx6/mx6x_pins.h

@@ -530,8 +530,8 @@ enum {
 	MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16	= IOMUX_PAD(0x046C, 0x0158, 1, 0x0000, 0, 0),
 	MX6Q_PAD_EIM_BCLK__GPIO_6_31		= IOMUX_PAD(0x046C, 0x0158, 5, 0x0000, 0, 0),
 	MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31	= IOMUX_PAD(0x046C, 0x0158, 6, 0x0000, 0, 0),
-	MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DSP_CLK = IOMUX_PAD(0x0470, 0x015C, 0, 0x0000, 0, 0),
-	MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DSP_CLK = IOMUX_PAD(0x0470, 0x015C, 1, 0x0000, 0, 0),
+	MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 0, 0x0000, 0, 0),
+	MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 1, 0x0000, 0, 0),
 	MX6Q_PAD_DI0_DISP_CLK__MIPI_CR_DPY_OT28 = IOMUX_PAD(0x0470, 0x015C, 3, 0x0000, 0, 0),
 	MX6Q_PAD_DI0_DISP_CLK__SDMA_DBG_CR_STA0 = IOMUX_PAD(0x0470, 0x015C, 4, 0x0000, 0, 0),
 	MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16	= IOMUX_PAD(0x0470, 0x015C, 5, 0x0000, 0, 0),

arch/arm/lib/board.c

@@ -224,10 +224,16 @@ void __dram_init_banksize(void)
 void dram_init_banksize(void)
 	__attribute__((weak, alias("__dram_init_banksize")));
 
+int __arch_cpu_init(void)
+{
+	return 0;
+}
+int arch_cpu_init(void)
+	__attribute__((weak, alias("__arch_cpu_init")));
+
 init_fnc_t *init_sequence[] = {
-#if defined(CONFIG_ARCH_CPU_INIT)
 	arch_cpu_init,		/* basic arch cpu dependent setup */
-#endif
+
 #if defined(CONFIG_BOARD_EARLY_INIT_F)
 	board_early_init_f,
 #endif

arch/nds32/cpu/n1213/ag101/cpu.c

@@ -82,115 +82,3 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 	/*NOTREACHED*/
 }
-
-static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache)
-{
-	if (cache == ICACHE)
-		return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \
-					>> ICM_CFG_OFF_ISZ) - 1);
-	else
-		return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \
-					>> DCM_CFG_OFF_DSZ) - 1);
-}
-
-void dcache_flush_range(unsigned long start, unsigned long end)
-{
-	unsigned long line_size;
-
-	line_size = CACHE_LINE_SIZE(DCACHE);
-
-	while (end > start) {
-		__asm__ volatile ("\n\tcctl %0, L1D_VA_WB" : : "r"(start));
-		__asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL" : : "r"(start));
-		start += line_size;
-	}
-}
-
-void icache_inval_range(unsigned long start, unsigned long end)
-{
-	unsigned long line_size;
-
-	line_size = CACHE_LINE_SIZE(ICACHE);
-	while (end > start) {
-		__asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL" : : "r"(start));
-		start += line_size;
-	}
-}
-
-void flush_cache(unsigned long addr, unsigned long size)
-{
-	dcache_flush_range(addr, addr + size);
-	icache_inval_range(addr, addr + size);
-}
-
-void icache_enable(void)
-{
-	__asm__ __volatile__ (
-		"mfsr	$p0, $mr8\n\t"
-		"ori	$p0, $p0, 0x01\n\t"
-		"mtsr	$p0, $mr8\n\t"
-		"isb\n\t"
-	);
-}
-
-void icache_disable(void)
-{
-	__asm__ __volatile__ (
-		"mfsr	$p0, $mr8\n\t"
-		"li	$p1, ~0x01\n\t"
-		"and	$p0, $p0, $p1\n\t"
-		"mtsr	$p0, $mr8\n\t"
-		"isb\n\t"
-	);
-}
-
-int icache_status(void)
-{
-	int ret;
-
-	 __asm__ __volatile__ (
-		"mfsr	$p0, $mr8\n\t"
-		"andi	%0,  $p0, 0x01\n\t"
-		: "=r" (ret)
-		:
-		: "memory"
-	);
-
-	 return ret;
-}
-
-void dcache_enable(void)
-{
-	 __asm__ __volatile__ (
-		"mfsr	$p0, $mr8\n\t"
-		"ori	$p0, $p0, 0x02\n\t"
-		"mtsr	$p0, $mr8\n\t"
-		"isb\n\t"
-	);
-}
-
-void dcache_disable(void)
-{
-	 __asm__ __volatile__ (
-		"mfsr	$p0, $mr8\n\t"
-		"li	$p1, ~0x02\n\t"
-		"and	$p0, $p0, $p1\n\t"
-		"mtsr	$p0, $mr8\n\t"
-		"isb\n\t"
-	);
-}
-
-int dcache_status(void)
-{
-	int ret;
-
-	__asm__ __volatile__ (
-		"mfsr	$p0, $mr8\n\t"
-		"andi	%0, $p0, 0x02\n\t"
-		: "=r" (ret)
-		:
-		: "memory"
-	 );
-
-	 return ret;
-}

arch/nds32/cpu/n1213/ag102/cpu.c

@@ -81,115 +81,3 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 	/*NOTREACHED*/
 }
-
-static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache)
-{
-	if (cache == ICACHE)
-		return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \
-					>> ICM_CFG_OFF_ISZ) - 1);
-	else
-		return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \
-					>> DCM_CFG_OFF_DSZ) - 1);
-}
-
-void dcache_flush_range(unsigned long start, unsigned long end)
-{
-	unsigned long line_size;
-
-	line_size = CACHE_LINE_SIZE(DCACHE);
-
-	while (end > start) {
-		__asm__ volatile ("\n\tcctl %0, L1D_VA_WB" : : "r"(start));
-		__asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL" : : "r"(start));
-		start += line_size;
-	}
-}
-
-void icache_inval_range(unsigned long start, unsigned long end)
-{
-	unsigned long line_size;
-
-	line_size = CACHE_LINE_SIZE(ICACHE);
-	while (end > start) {
-		__asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL" : : "r"(start));
-		start += line_size;
-	}
-}
-
-void flush_cache(unsigned long addr, unsigned long size)
-{
-	dcache_flush_range(addr, addr + size);
-	icache_inval_range(addr, addr + size);
-}
-
-void icache_enable(void)
-{
-	__asm__ __volatile__ (
-		"mfsr	$p0, $mr8\n\t"
-		"ori	$p0, $p0, 0x01\n\t"
-		"mtsr	$p0, $mr8\n\t"
-		"isb\n\t"
-	);
-}
-
-void icache_disable(void)
-{
-	__asm__ __volatile__ (
-		"mfsr	$p0, $mr8\n\t"
-		"li	$p1, ~0x01\n\t"
-		"and	$p0, $p0, $p1\n\t"
-		"mtsr	$p0, $mr8\n\t"
-		"isb\n\t"
-	);
-}
-
-int icache_status(void)
-{
-	int ret;
-
-	 __asm__ __volatile__ (
-		"mfsr	$p0, $mr8\n\t"
-		"andi	%0,  $p0, 0x01\n\t"
-		: "=r" (ret)
-		:
-		: "memory"
-	);
-
-	 return ret;
-}
-
-void dcache_enable(void)
-{
-	 __asm__ __volatile__ (
-		"mfsr	$p0, $mr8\n\t"
-		"ori	$p0, $p0, 0x02\n\t"
-		"mtsr	$p0, $mr8\n\t"
-		"isb\n\t"
-	);
-}
-
-void dcache_disable(void)
-{
-	 __asm__ __volatile__ (
-		"mfsr	$p0, $mr8\n\t"
-		"li	$p1, ~0x02\n\t"
-		"and	$p0, $p0, $p1\n\t"
-		"mtsr	$p0, $mr8\n\t"
-		"isb\n\t"
-	);
-}
-
-int dcache_status(void)
-{
-	int ret;
-
-	__asm__ __volatile__ (
-		"mfsr	$p0, $mr8\n\t"
-		"andi	%0, $p0, 0x02\n\t"
-		: "=r" (ret)
-		:
-		: "memory"
-	 );
-
-	 return ret;
-}

arch/nds32/lib/Makefile

@@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(ARCH).o
 
-OBJS	:= board.o bootm.o interrupts.o
+OBJS	:= board.o bootm.o cache.o interrupts.o
 
 all:	$(LIB)
 

arch/nds32/lib/cache.c

@@ -0,0 +1,157 @@
+/*
+ * Copyright (C) 2012 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307	 USA
+ *
+ */
+
+#include <common.h>
+
+static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache)
+{
+	if (cache == ICACHE)
+		return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \
+					>> ICM_CFG_OFF_ISZ) - 1);
+	else
+		return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \
+					>> DCM_CFG_OFF_DSZ) - 1);
+}
+
+void flush_dcache_range(unsigned long start, unsigned long end)
+{
+	unsigned long line_size;
+
+	line_size = CACHE_LINE_SIZE(DCACHE);
+
+	while (end > start) {
+		asm volatile (
+			"\n\tcctl %0, L1D_VA_WB"
+			"\n\tcctl %0, L1D_VA_INVAL"
+			:
+			: "r" (start)
+		);
+		start += line_size;
+	}
+}
+
+void invalidate_icache_range(unsigned long start, unsigned long end)
+{
+	unsigned long line_size;
+
+	line_size = CACHE_LINE_SIZE(ICACHE);
+	while (end > start) {
+		asm volatile (
+			"\n\tcctl %0, L1I_VA_INVAL"
+			:
+			: "r"(start)
+		);
+		start += line_size;
+	}
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long end)
+{
+	unsigned long line_size;
+
+	line_size = CACHE_LINE_SIZE(DCACHE);
+	while (end > start) {
+		asm volatile (
+			"\n\tcctl %0, L1D_VA_INVAL"
+			:
+			: "r"(start)
+		);
+		start += line_size;
+	}
+}
+
+void flush_cache(unsigned long addr, unsigned long size)
+{
+	flush_dcache_range(addr, addr + size);
+	invalidate_icache_range(addr, addr + size);
+}
+
+void icache_enable(void)
+{
+	asm volatile (
+		"mfsr	$p0, $mr8\n\t"
+		"ori	$p0, $p0, 0x01\n\t"
+		"mtsr	$p0, $mr8\n\t"
+		"isb\n\t"
+	);
+}
+
+void icache_disable(void)
+{
+	asm volatile (
+		"mfsr	$p0, $mr8\n\t"
+		"li	$p1, ~0x01\n\t"
+		"and	$p0, $p0, $p1\n\t"
+		"mtsr	$p0, $mr8\n\t"
+		"isb\n\t"
+	);
+}
+
+int icache_status(void)
+{
+	int ret;
+
+	asm volatile (
+		"mfsr	$p0, $mr8\n\t"
+		"andi	%0,  $p0, 0x01\n\t"
+		: "=r" (ret)
+		:
+		: "memory"
+	);
+
+	return ret;
+}
+
+void dcache_enable(void)
+{
+	asm volatile (
+		"mfsr	$p0, $mr8\n\t"
+		"ori	$p0, $p0, 0x02\n\t"
+		"mtsr	$p0, $mr8\n\t"
+		"isb\n\t"
+	);
+}
+
+void dcache_disable(void)
+{
+	asm volatile (
+		"mfsr	$p0, $mr8\n\t"
+		"li	$p1, ~0x02\n\t"
+		"and	$p0, $p0, $p1\n\t"
+		"mtsr	$p0, $mr8\n\t"
+		"isb\n\t"
+	);
+}
+
+int dcache_status(void)
+{
+	int ret;
+
+	asm volatile (
+		"mfsr	$p0, $mr8\n\t"
+		"andi	%0, $p0, 0x02\n\t"
+		: "=r" (ret)
+		:
+		: "memory"
+	);
+
+	return ret;
+}

arch/nios2/lib/board.c

@@ -87,17 +87,15 @@ void board_init (void)
 {
 	bd_t *bd;
 	init_fnc_t **init_fnc_ptr;
+	static gd_t gd_data;
+	static bd_t bd_data;
 
-	/* Pointer is writable since we allocated a register for it.
-	 * Nios treats CONFIG_SYS_GBL_DATA_OFFSET as an address.
-	 */
-	gd = (gd_t *)CONFIG_SYS_GBL_DATA_OFFSET;
+	/* Pointer is writable since we allocated a register for it. */
+	gd = &gd_data;
 	/* compiler optimization barrier needed for GCC >= 3.4 */
 	__asm__ __volatile__("": : :"memory");
 
-	memset( gd, 0, GENERATED_GBL_DATA_SIZE );
-
-	gd->bd = (bd_t *)(gd+1);	/* At end of global data */
+	gd->bd = &bd_data;
 	gd->baudrate = CONFIG_BAUDRATE;
 	gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
 

arch/powerpc/cpu/mpc83xx/Makefile

@@ -42,7 +42,7 @@ COBJS-$(CONFIG_PCIE) += pcie.o
 COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
 
 # Stub implementations of cache management functions for USB
-COBJS-$(CONFIG_USB_EHCI) += cache.o
+COBJS-y += cache.o
 
 ifdef CONFIG_FSL_DDR2
 COBJS_LN-$(CONFIG_MPC8349) += ddr-gen2.o

arch/powerpc/cpu/mpc85xx/Makefile

@@ -131,7 +131,7 @@ COBJS	+= tlb.o
 COBJS	+= traps.o
 
 # Stub implementations of cache management functions for USB
-COBJS-$(CONFIG_USB_EHCI) += cache.o
+COBJS += cache.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))

board/bc3450/cmd_bc3450.c

@@ -32,13 +32,6 @@
  */
 #if defined(CONFIG_CMD_BSP)
 
-#undef DEBUG
-#ifdef DEBUG
-# define dprintf(fmt,args...)	printf(fmt, ##args)
-#else
-# define dprintf(fmt,args...)
-#endif
-
 /*
  * Definitions for DS1620 chip
  */
@@ -52,7 +45,6 @@
 #define THERM_WRITE_TL		0x02
 #define THERM_WRITE_TH		0x01
 
-#define CONFIG_SYS_CPU			2
 #define CONFIG_SYS_1SHOT		1
 #define CONFIG_SYS_STANDALONE		0
 
@@ -129,7 +121,7 @@ int sm501_gpio_init (void)
 	static int init_done = 0;
 
 	if (init_done) {
-/*	dprintf("sm501_gpio_init: nothing to be done.\n"); */
+		debug("sm501_gpio_init: nothing to be done.\n");
 		return 1;
 	}
 
@@ -162,7 +154,8 @@ int sm501_gpio_init (void)
 		(PWR_OFF | BUZZER | FP_DATA_TRI);
 
 	init_done = 1;
-/*  dprintf("sm501_gpio_init: done.\n"); */
+	debug("sm501_gpio_init: done.\n");
+
 	return 0;
 }
 

board/bf527-ezkit/video.c

@@ -17,6 +17,10 @@
 #include <linux/types.h>
 #include <stdio_dev.h>
 
+#include <lzma/LzmaTypes.h>
+#include <lzma/LzmaDec.h>
+#include <lzma/LzmaTools.h>
+
 #include <asm/mach-common/bits/ppi.h>
 #include <asm/mach-common/bits/timer.h>
 
@@ -24,12 +28,9 @@
 #define LCD_Y_RES		240	/* Vertical Resolution */
 #define DMA_BUS_SIZE		16
 
-#ifdef CONFIG_BF527_EZKIT_REV_2_1 /* lq035q1 */
+#include EASYLOGO_HEADER
 
-#if !defined(CONFIG_LQ035Q1_USE_RGB888_8_BIT_PPI) && \
-    !defined(CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI)
-# define CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI
-#endif
+#ifdef CONFIG_BF527_EZKIT_REV_2_1 /* lq035q1 */
 
 /* Interface 16/18-bit TFT over an 8-bit wide PPI using a
  * small Programmable Logic Device (CPLD)
@@ -37,14 +38,12 @@
  */
 
 #ifdef CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI
-#include <asm/bfin_logo_rgb565_230x230.h>
 #define LCD_BPP		16	/* Bit Per Pixel */
 #define CLOCKS_PPIX	2	/* Clocks per pixel */
 #define CPLD_DELAY	3	/* RGB565 pipeline delay */
 #endif
 
 #ifdef CONFIG_LQ035Q1_USE_RGB888_8_BIT_PPI
-#include <asm/bfin_logo_230x230.h>
 #define LCD_BPP		24	/* Bit Per Pixel */
 #define CLOCKS_PPIX	3	/* Clocks per pixel */
 #define CPLD_DELAY	5	/* RGB888 pipeline delay */
@@ -96,7 +95,6 @@
 #endif
 
 #else /* t350mcqb */
-#include <asm/bfin_logo_230x230.h>
 
 #define LCD_BPP		24	/* Bit Per Pixel */
 #define CLOCKS_PPIX	3	/* Clocks per pixel */
@@ -419,13 +417,23 @@ int drv_video_init(void)
 #ifdef EASYLOGO_ENABLE_GZIP
 	unsigned char *data = EASYLOGO_DECOMP_BUFFER;
 	unsigned long src_len = EASYLOGO_ENABLE_GZIP;
-	if (gunzip(data, bfin_logo.size, bfin_logo.data, &src_len)) {
+	error = gunzip(data, bfin_logo.size, bfin_logo.data, &src_len);
+	bfin_logo.data = data;
+#elif defined(EASYLOGO_ENABLE_LZMA)
+	unsigned char *data = EASYLOGO_DECOMP_BUFFER;
+	SizeT lzma_len = bfin_logo.size;
+	error = lzmaBuffToBuffDecompress(data, &lzma_len,
+		bfin_logo.data, EASYLOGO_ENABLE_LZMA);
+	bfin_logo.data = data;
+#else
+	error = 0;
+#endif
+
+	if (error) {
 		puts("Failed to decompress logo\n");
 		free(dst);
 		return -1;
 	}
-	bfin_logo.data = data;
-#endif
 
 	memset(dst + ACTIVE_VIDEO_MEM_OFFSET, bfin_logo.data[0], fbmem_size - ACTIVE_VIDEO_MEM_OFFSET);
 

board/bf548-ezkit/video.c

@@ -18,11 +18,15 @@
 #include <linux/types.h>
 #include <stdio_dev.h>
 
+#include <lzma/LzmaTypes.h>
+#include <lzma/LzmaDec.h>
+#include <lzma/LzmaTools.h>
+
 #define DMA_SIZE16	2
 
 #include <asm/mach-common/bits/eppi.h>
 
-#include <asm/bfin_logo_230x230.h>
+#include EASYLOGO_HEADER
 
 #define LCD_X_RES		480	/*Horizontal Resolution */
 #define LCD_Y_RES		272	/* Vertical Resolution */
@@ -303,13 +307,23 @@ int drv_video_init(void)
 #ifdef EASYLOGO_ENABLE_GZIP
 	unsigned char *data = EASYLOGO_DECOMP_BUFFER;
 	unsigned long src_len = EASYLOGO_ENABLE_GZIP;
-	if (gunzip(data, bfin_logo.size, bfin_logo.data, &src_len)) {
+	error = gunzip(data, bfin_logo.size, bfin_logo.data, &src_len);
+	bfin_logo.data = data;
+#elif defined(EASYLOGO_ENABLE_LZMA)
+	unsigned char *data = EASYLOGO_DECOMP_BUFFER;
+	SizeT lzma_len = bfin_logo.size;
+	error = lzmaBuffToBuffDecompress(data, &lzma_len,
+		bfin_logo.data, EASYLOGO_ENABLE_LZMA);
+	bfin_logo.data = data;
+#else
+	error = 0;
+#endif
+
+	if (error) {
 		puts("Failed to decompress logo\n");
 		free(dst);
 		return -1;
 	}
-	bfin_logo.data = data;
-#endif
 
 	memset(dst + ACTIVE_VIDEO_MEM_OFFSET, bfin_logo.data[0], fbmem_size - ACTIVE_VIDEO_MEM_OFFSET);
 

board/cm-bf548/video.c

@@ -18,13 +18,15 @@
 #include <linux/types.h>
 #include <stdio_dev.h>
 
-#ifdef CONFIG_VIDEO
+#include <lzma/LzmaTypes.h>
+#include <lzma/LzmaDec.h>
+#include <lzma/LzmaTools.h>
 
 #define DMA_SIZE16	2
 
 #include <asm/mach-common/bits/eppi.h>
 
-#include <asm/bfin_logo_230x230.h>
+#include EASYLOGO_HEADER
 
 #define LCD_X_RES		480	/*Horizontal Resolution */
 #define LCD_Y_RES		272	/* Vertical Resolution */
@@ -303,16 +305,27 @@ int drv_video_init(void)
 		printf("Failed to alloc FB memory\n");
 		return -1;
 	}
+
 #ifdef EASYLOGO_ENABLE_GZIP
 	unsigned char *data = EASYLOGO_DECOMP_BUFFER;
 	unsigned long src_len = EASYLOGO_ENABLE_GZIP;
-	if (gunzip(data, bfin_logo.size, bfin_logo.data, &src_len)) {
+	error = gunzip(data, bfin_logo.size, bfin_logo.data, &src_len);
+	bfin_logo.data = data;
+#elif defined(EASYLOGO_ENABLE_LZMA)
+	unsigned char *data = EASYLOGO_DECOMP_BUFFER;
+	SizeT lzma_len = bfin_logo.size;
+	error = lzmaBuffToBuffDecompress(data, &lzma_len,
+		bfin_logo.data, EASYLOGO_ENABLE_LZMA);
+	bfin_logo.data = data;
+#else
+	error = 0;
+#endif
+
+	if (error) {
 		puts("Failed to decompress logo\n");
 		free(dst);
 		return -1;
 	}
-	bfin_logo.data = data;
-#endif
 
 	memset(dst + ACTIVE_VIDEO_MEM_OFFSET, bfin_logo.data[0],
 	       fbmem_size - ACTIVE_VIDEO_MEM_OFFSET);
@@ -335,5 +348,3 @@ int drv_video_init(void)
 
 	return (error == 0) ? devices : error;
 }
-
-#endif

board/freescale/mx28evk/iomux.c

@@ -159,6 +159,9 @@ const iomux_cfg_t iomux_setup[] = {
 	MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2,
 	MX28_PAD_SSP2_SS0__SSP2_D3 |
 		(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
+	/* I2C */
+	MX28_PAD_I2C0_SCL__I2C0_SCL,
+	MX28_PAD_I2C0_SDA__I2C0_SDA,
 };
 
 #define HW_DRAM_CTL29	(0x74 >> 2)

board/freescale/mx6qsabrelite/mx6qsabrelite.c

@@ -55,6 +55,11 @@ DECLARE_GLOBAL_DATA_PTR;
 	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |		\
 	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
 
+#define I2C_PAD_CTRL	(PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
+	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
 int dram_init(void)
 {
        gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
@@ -72,6 +77,11 @@ iomux_v3_cfg_t uart2_pads[] = {
        MX6Q_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 
+iomux_v3_cfg_t i2c3_pads[] = {
+	MX6Q_PAD_GPIO_5__I2C3_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
+	MX6Q_PAD_GPIO_16__I2C3_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
+};
+
 iomux_v3_cfg_t usdhc3_pads[] = {
        MX6Q_PAD_SD3_CLK__USDHC3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
        MX6Q_PAD_SD3_CMD__USDHC3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
@@ -336,6 +346,7 @@ int board_init(void)
 #ifdef CONFIG_MXC_SPI
 	setup_spi();
 #endif
+	imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads));
 
 #ifdef CONFIG_CMD_SATA
 	setup_sata();

board/freescale/p1010rdb/README

@@ -146,7 +146,6 @@ Build and burn u-boot to NAND flash
 3. Check SW4[1:4]= 1000 and SW6[4]=1, then power on.
 
 
-
 Build and burn u-boot to SPI flash
 ==================================
 1. Build u-boot-spi.bin image
@@ -166,7 +165,6 @@ Build and burn u-boot to SPI flash
 3. Check SW4[1:4]= 0110 and SW6[4]=0, then power on.
 
 
-
 CPLD POR setting registers
 ==========================
 1. Set POR switch selection register (addr 0xFFB00011) to 0.
@@ -197,7 +195,6 @@ Switch from NAND to NOR boot with Core/CCB/DDR (800/400/667 MHz):
 	=> reset
 
 
-
 Boot Linux from network using TFTP on P1010RDB
 ==============================================
 Place uImage, p1010rdb.dtb and rootfs files in the TFTP disk area.

board/ti/panda/panda_mux_data.h

@@ -62,7 +62,26 @@ const struct pad_conf_entry core_padconf_array_essential[] = {
 {UART3_CTS_RCTX, (PTU | IEN | M0)},			/* uart3_tx */
 {UART3_RTS_SD, (M0)},					/* uart3_rts_sd */
 {UART3_RX_IRRX, (IEN | M0)},				/* uart3_rx */
-{UART3_TX_IRTX, (M0)}					/* uart3_tx */
+{UART3_TX_IRTX, (M0)},					/* uart3_tx */
+{USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */
+{USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)},		/* usbb1_ulpiphy_stp */
+{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dir */
+{USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_nxt */
+{USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat0 */
+{USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat1 */
+{USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat2 */
+{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat3 */
+{USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat4 */
+{USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat5 */
+{USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat6 */
+{USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat7 */
+{USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* usbb1_hsic_data */
+{USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* usbb1_hsic_strobe */
+{USBC1_ICUSB_DP, (IEN | M0)},					/* usbc1_icusb_dp */
+{USBC1_ICUSB_DM, (IEN | M0)},					/* usbc1_icusb_dm */
+{UNIPRO_TY2, (PTU | IEN | M3)},					/* gpio_1 */
+{GPMC_WAIT1,  (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_62 */
+{FREF_CLK2_OUT, (PTU | IEN | M3)},				/* gpio_182 */
 
 };
 
@@ -70,7 +89,8 @@ const struct pad_conf_entry wkup_padconf_array_essential[] = {
 
 {PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */
 {PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */
-{PAD1_SYS_32K, (IEN | M0)}	 /* sys_32k */
+{PAD1_SYS_32K, (IEN | M0)},	 /* sys_32k */
+{PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */
 
 };
 
@@ -109,7 +129,6 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{GPMC_NBE0_CLE, (M3)},						/* gpio_59 */
 	{GPMC_NBE1, (PTD | M3)},					/* gpio_60 */
 	{GPMC_WAIT0, (PTU | IEN | M3)},					/* gpio_61 */
-	{GPMC_WAIT1,  (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_62 */
 	{C2C_DATA11, (PTD | M3)},					/* gpio_100 */
 	{C2C_DATA12, (PTU | IEN | M3)},					/* gpio_101 */
 	{C2C_DATA13, (PTD | M3)},					/* gpio_102 */
@@ -136,22 +155,6 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_shutter */
 	{CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_strobe */
 	{CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_83 */
-	{USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */
-	{USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)},		/* usbb1_ulpiphy_stp */
-	{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dir */
-	{USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_nxt */
-	{USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat0 */
-	{USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat1 */
-	{USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat2 */
-	{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat3 */
-	{USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat4 */
-	{USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat5 */
-	{USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat6 */
-	{USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat7 */
-	{USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* usbb1_hsic_data */
-	{USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* usbb1_hsic_strobe */
-	{USBC1_ICUSB_DP, (IEN | M0)},					/* usbc1_icusb_dp */
-	{USBC1_ICUSB_DM, (IEN | M0)},					/* usbc1_icusb_dm */
 	{ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* abe_mcbsp2_dr */
 	{ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp2_dx */
 	{ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_fsx */
@@ -211,7 +214,6 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col2 */
 	{UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col3 */
 	{UNIPRO_TX2, (PTU | IEN | M3)},					/* gpio_0 */
-	{UNIPRO_TY2, (PTU | IEN | M3)},					/* gpio_1 */
 	{UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row0 */
 	{UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row1 */
 	{UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row2 */
@@ -222,7 +224,6 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* usba0_otg_dp */
 	{USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* usba0_otg_dm */
 	{FREF_CLK1_OUT, (M0)},						/* fref_clk1_out */
-	{FREF_CLK2_OUT, (PTU | IEN | M3)},				/* gpio_182 */
 	{SYS_NIRQ1, (PTU | IEN | M0)},					/* sys_nirq1 */
 	{SYS_NIRQ2, (PTU | IEN | M0)},					/* sys_nirq2 */
 	{SYS_BOOT0, (PTU | IEN | M3)},					/* gpio_184 */
@@ -272,7 +273,6 @@ const struct pad_conf_entry wkup_padconf_array_non_essential[] = {
 	{PAD1_FREF_CLK_IOREQ, (M0)},		/* fref_clk_ioreq */
 	{PAD0_FREF_CLK0_OUT, (M2)},		/* sys_drm_msecure */
 	{PAD1_FREF_CLK3_REQ, M7},		/* safe mode */
-	{PAD0_FREF_CLK3_OUT, (M0)},		/* fref_clk3_out */
 	{PAD0_FREF_CLK4_OUT, (PTU | M3)},	/* led status_2 */
 	{PAD0_SYS_NRESPWRON, (M0)},		/* sys_nrespwron */
 	{PAD1_SYS_NRESWARM, (M0)},		/* sys_nreswarm */

common/lcd.c

@@ -76,42 +76,42 @@ DECLARE_GLOBAL_DATA_PTR;
 
 ulong lcd_setmem (ulong addr);
 
-static void lcd_drawchars (ushort x, ushort y, uchar *str, int count);
-static inline void lcd_puts_xy (ushort x, ushort y, uchar *s);
-static inline void lcd_putc_xy (ushort x, ushort y, uchar  c);
+static void lcd_drawchars(ushort x, ushort y, uchar *str, int count);
+static inline void lcd_puts_xy(ushort x, ushort y, uchar *s);
+static inline void lcd_putc_xy(ushort x, ushort y, uchar  c);
 
-static int lcd_init (void *lcdbase);
+static int lcd_init(void *lcdbase);
 
 static void *lcd_logo (void);
 
-static int lcd_getbgcolor (void);
-static void lcd_setfgcolor (int color);
-static void lcd_setbgcolor (int color);
+static int lcd_getbgcolor(void);
+static void lcd_setfgcolor(int color);
+static void lcd_setbgcolor(int color);
 
 char lcd_is_enabled = 0;
 
 #ifdef	NOT_USED_SO_FAR
-static void lcd_getcolreg (ushort regno,
+static void lcd_getcolreg(ushort regno,
 				ushort *red, ushort *green, ushort *blue);
-static int lcd_getfgcolor (void);
+static int lcd_getfgcolor(void);
 #endif	/* NOT_USED_SO_FAR */
 
 /************************************************************************/
 
 /*----------------------------------------------------------------------*/
 
-static void console_scrollup (void)
+static void console_scrollup(void)
 {
 	/* Copy up rows ignoring the first one */
-	memcpy (CONSOLE_ROW_FIRST, CONSOLE_ROW_SECOND, CONSOLE_SCROLL_SIZE);
+	memcpy(CONSOLE_ROW_FIRST, CONSOLE_ROW_SECOND, CONSOLE_SCROLL_SIZE);
 
 	/* Clear the last one */
-	memset (CONSOLE_ROW_LAST, COLOR_MASK(lcd_color_bg), CONSOLE_ROW_SIZE);
+	memset(CONSOLE_ROW_LAST, COLOR_MASK(lcd_color_bg), CONSOLE_ROW_SIZE);
 }
 
 /*----------------------------------------------------------------------*/
 
-static inline void console_back (void)
+static inline void console_back(void)
 {
 	if (--console_col < 0) {
 		console_col = CONSOLE_COLS-1 ;
@@ -120,14 +120,13 @@ static inline void console_back (void)
 		}
 	}
 
-	lcd_putc_xy (console_col * VIDEO_FONT_WIDTH,
-		     console_row * VIDEO_FONT_HEIGHT,
-		     ' ');
+	lcd_putc_xy(console_col * VIDEO_FONT_WIDTH,
+		console_row * VIDEO_FONT_HEIGHT, ' ');
 }
 
 /*----------------------------------------------------------------------*/
 
-static inline void console_newline (void)
+static inline void console_newline(void)
 {
 	++console_row;
 	console_col = 0;
@@ -135,61 +134,62 @@ static inline void console_newline (void)
 	/* Check if we need to scroll the terminal */
 	if (console_row >= CONSOLE_ROWS) {
 		/* Scroll everything up */
-		console_scrollup () ;
+		console_scrollup();
 		--console_row;
 	}
 }
 
 /*----------------------------------------------------------------------*/
 
-void lcd_putc (const char c)
+void lcd_putc(const char c)
 {
 	if (!lcd_is_enabled) {
 		serial_putc(c);
+
 		return;
 	}
 
 	switch (c) {
-	case '\r':	console_col = 0;
-			return;
+	case '\r':
+		console_col = 0;
 
-	case '\n':	console_newline();
-			return;
+		return;
+	case '\n':
+		console_newline();
 
+		return;
 	case '\t':	/* Tab (8 chars alignment) */
-			console_col +=  8;
-			console_col &= ~7;
+		console_col +=  8;
+		console_col &= ~7;
 
-			if (console_col >= CONSOLE_COLS) {
-				console_newline();
-			}
-			return;
+		if (console_col >= CONSOLE_COLS)
+			console_newline();
 
-	case '\b':	console_back();
-			return;
+		return;
+	case '\b':
+		console_back();
 
-	default:	lcd_putc_xy (console_col * VIDEO_FONT_WIDTH,
-				     console_row * VIDEO_FONT_HEIGHT,
-				     c);
-			if (++console_col >= CONSOLE_COLS) {
-				console_newline();
-			}
-			return;
+		return;
+	default:
+		lcd_putc_xy(console_col * VIDEO_FONT_WIDTH,
+			console_row * VIDEO_FONT_HEIGHT, c);
+		if (++console_col >= CONSOLE_COLS)
+			console_newline();
 	}
-	/* NOTREACHED */
 }
 
 /*----------------------------------------------------------------------*/
 
-void lcd_puts (const char *s)
+void lcd_puts(const char *s)
 {
 	if (!lcd_is_enabled) {
-		serial_puts (s);
+		serial_puts(s);
+
 		return;
 	}
 
 	while (*s) {
-		lcd_putc (*s++);
+		lcd_putc(*s++);
 	}
 }
 
@@ -211,7 +211,7 @@ void lcd_printf(const char *fmt, ...)
 /* ** Low-Level Graphics Routines					*/
 /************************************************************************/
 
-static void lcd_drawchars (ushort x, ushort y, uchar *str, int count)
+static void lcd_drawchars(ushort x, ushort y, uchar *str, int count)
 {
 	uchar *dest;
 	ushort row;
@@ -226,7 +226,7 @@ static void lcd_drawchars (ushort x, ushort y, uchar *str, int count)
 
 	dest = (uchar *)(lcd_base + y * lcd_line_length + x * (1 << LCD_BPP) / 8);
 
-	for (row=0;  row < VIDEO_FONT_HEIGHT;  ++row, dest += lcd_line_length)  {
+	for (row = 0; row < VIDEO_FONT_HEIGHT; ++row, dest += lcd_line_length) {
 		uchar *s = str;
 		int i;
 #if LCD_BPP == LCD_COLOR16
@@ -239,7 +239,7 @@ static void lcd_drawchars (ushort x, ushort y, uchar *str, int count)
 		uchar rest = *d & -(1 << (8-off));
 		uchar sym;
 #endif
-		for (i=0; i<count; ++i) {
+		for (i = 0; i < count; ++i) {
 			uchar c, bits;
 
 			c = *s++;
@@ -247,18 +247,18 @@ static void lcd_drawchars (ushort x, ushort y, uchar *str, int count)
 
 #if LCD_BPP == LCD_MONOCHROME
 			sym  = (COLOR_MASK(lcd_color_fg) & bits) |
-			       (COLOR_MASK(lcd_color_bg) & ~bits);
+				(COLOR_MASK(lcd_color_bg) & ~bits);
 
 			*d++ = rest | (sym >> off);
 			rest = sym << (8-off);
 #elif LCD_BPP == LCD_COLOR8
-			for (c=0; c<8; ++c) {
+			for (c = 0; c < 8; ++c) {
 				*d++ = (bits & 0x80) ?
 						lcd_color_fg : lcd_color_bg;
 				bits <<= 1;
 			}
 #elif LCD_BPP == LCD_COLOR16
-			for (c=0; c<8; ++c) {
+			for (c = 0; c < 8; ++c) {
 				*d++ = (bits & 0x80) ?
 						lcd_color_fg : lcd_color_bg;
 				bits <<= 1;
@@ -273,14 +273,14 @@ static void lcd_drawchars (ushort x, ushort y, uchar *str, int count)
 
 /*----------------------------------------------------------------------*/
 
-static inline void lcd_puts_xy (ushort x, ushort y, uchar *s)
+static inline void lcd_puts_xy(ushort x, ushort y, uchar *s)
 {
 	lcd_drawchars(x, y, s, strlen((char *)s));
 }
 
 /*----------------------------------------------------------------------*/
 
-static inline void lcd_putc_xy (ushort x, ushort y, uchar c)
+static inline void lcd_putc_xy(ushort x, ushort y, uchar c)
 {
 	lcd_drawchars(x, y, &c, 1);
 }
@@ -298,7 +298,7 @@ static int test_colors[N_BLK_HOR*N_BLK_VERT] = {
 	CONSOLE_COLOR_BLUE,	CONSOLE_COLOR_MAGENTA,	CONSOLE_COLOR_CYAN,
 };
 
-static void test_pattern (void)
+static void test_pattern(void)
 {
 	ushort v_max  = panel_info.vl_row;
 	ushort h_max  = panel_info.vl_col;
@@ -307,13 +307,13 @@ static void test_pattern (void)
 	ushort v, h;
 	uchar *pix = (uchar *)lcd_base;
 
-	printf ("[LCD] Test Pattern: %d x %d [%d x %d]\n",
+	printf("[LCD] Test Pattern: %d x %d [%d x %d]\n",
 		h_max, v_max, h_step, v_step);
 
 	/* WARNING: Code silently assumes 8bit/pixel */
-	for (v=0; v<v_max; ++v) {
+	for (v = 0; v < v_max; ++v) {
 		uchar iy = v / v_step;
-		for (h=0; h<h_max; ++h) {
+		for (h = 0; h < h_max; ++h) {
 			uchar ix = N_BLK_HOR * iy + (h/h_step);
 			*pix++ = test_colors[ix];
 		}
@@ -335,12 +335,12 @@ int drv_lcd_init (void)
 
 	lcd_line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8;
 
-	lcd_init (lcd_base);		/* LCD initialization */
+	lcd_init(lcd_base);		/* LCD initialization */
 
 	/* Device initialization */
-	memset (&lcddev, 0, sizeof (lcddev));
+	memset(&lcddev, 0, sizeof(lcddev));
 
-	strcpy (lcddev.name, "lcd");
+	strcpy(lcddev.name, "lcd");
 	lcddev.ext   = 0;			/* No extensions */
 	lcddev.flags = DEV_FLAGS_OUTPUT;	/* Output only */
 	lcddev.putc  = lcd_putc;		/* 'putc' function */
@@ -367,35 +367,35 @@ void lcd_clear(void)
 
 #elif LCD_BPP == LCD_COLOR8
 	/* Setting the palette */
-	lcd_setcolreg  (CONSOLE_COLOR_BLACK,       0,    0,    0);
-	lcd_setcolreg  (CONSOLE_COLOR_RED,	0xFF,    0,    0);
-	lcd_setcolreg  (CONSOLE_COLOR_GREEN,       0, 0xFF,    0);
-	lcd_setcolreg  (CONSOLE_COLOR_YELLOW,	0xFF, 0xFF,    0);
-	lcd_setcolreg  (CONSOLE_COLOR_BLUE,        0,    0, 0xFF);
-	lcd_setcolreg  (CONSOLE_COLOR_MAGENTA,	0xFF,    0, 0xFF);
-	lcd_setcolreg  (CONSOLE_COLOR_CYAN,	   0, 0xFF, 0xFF);
-	lcd_setcolreg  (CONSOLE_COLOR_GREY,	0xAA, 0xAA, 0xAA);
-	lcd_setcolreg  (CONSOLE_COLOR_WHITE,	0xFF, 0xFF, 0xFF);
+	lcd_setcolreg(CONSOLE_COLOR_BLACK, 0, 0, 0);
+	lcd_setcolreg(CONSOLE_COLOR_RED, 0xFF, 0, 0);
+	lcd_setcolreg(CONSOLE_COLOR_GREEN, 0, 0xFF, 0);
+	lcd_setcolreg(CONSOLE_COLOR_YELLOW, 0xFF, 0xFF, 0);
+	lcd_setcolreg(CONSOLE_COLOR_BLUE, 0, 0, 0xFF);
+	lcd_setcolreg(CONSOLE_COLOR_MAGENTA, 0xFF, 0, 0xFF);
+	lcd_setcolreg(CONSOLE_COLOR_CYAN, 0, 0xFF, 0xFF);
+	lcd_setcolreg(CONSOLE_COLOR_GREY, 0xAA, 0xAA, 0xAA);
+	lcd_setcolreg(CONSOLE_COLOR_WHITE, 0xFF, 0xFF, 0xFF);
 #endif
 
 #ifndef CONFIG_SYS_WHITE_ON_BLACK
-	lcd_setfgcolor (CONSOLE_COLOR_BLACK);
-	lcd_setbgcolor (CONSOLE_COLOR_WHITE);
+	lcd_setfgcolor(CONSOLE_COLOR_BLACK);
+	lcd_setbgcolor(CONSOLE_COLOR_WHITE);
 #else
-	lcd_setfgcolor (CONSOLE_COLOR_WHITE);
-	lcd_setbgcolor (CONSOLE_COLOR_BLACK);
+	lcd_setfgcolor(CONSOLE_COLOR_WHITE);
+	lcd_setbgcolor(CONSOLE_COLOR_BLACK);
 #endif	/* CONFIG_SYS_WHITE_ON_BLACK */
 
 #ifdef	LCD_TEST_PATTERN
 	test_pattern();
 #else
 	/* set framebuffer to background color */
-	memset ((char *)lcd_base,
+	memset((char *)lcd_base,
 		COLOR_MASK(lcd_getbgcolor()),
 		lcd_line_length*panel_info.vl_row);
 #endif
 	/* Paint the logo and retrieve LCD base address */
-	debug ("[LCD] Drawing the logo...\n");
+	debug("[LCD] Drawing the logo...\n");
 	lcd_console_address = lcd_logo ();
 
 	console_col = 0;
@@ -410,12 +410,12 @@ U_BOOT_CMD(
 
 /*----------------------------------------------------------------------*/
 
-static int lcd_init (void *lcdbase)
+static int lcd_init(void *lcdbase)
 {
 	/* Initialize the lcd controller */
-	debug ("[LCD] Initializing LCD frambuffer at %p\n", lcdbase);
+	debug("[LCD] Initializing LCD frambuffer at %p\n", lcdbase);
 
-	lcd_ctrl_init (lcdbase);
+	lcd_ctrl_init(lcdbase);
 	lcd_is_enabled = 1;
 	lcd_clear();
 	lcd_enable ();
@@ -442,13 +442,13 @@ static int lcd_init (void *lcdbase)
  *
  * Note that this is running from ROM, so no write access to global data.
  */
-ulong lcd_setmem (ulong addr)
+ulong lcd_setmem(ulong addr)
 {
 	ulong size;
-	int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8;
+	int line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8;
 
-	debug ("LCD panel info: %d x %d, %d bit/pix\n",
-		panel_info.vl_col, panel_info.vl_row, NBITS (panel_info.vl_bpix) );
+	debug("LCD panel info: %d x %d, %d bit/pix\n", panel_info.vl_col,
+		panel_info.vl_row, NBITS(panel_info.vl_bpix));
 
 	size = line_length * panel_info.vl_row;
 
@@ -458,21 +458,21 @@ ulong lcd_setmem (ulong addr)
 	/* Allocate pages for the frame buffer. */
 	addr -= size;
 
-	debug ("Reserving %ldk for LCD Framebuffer at: %08lx\n", size>>10, addr);
+	debug("Reserving %ldk for LCD Framebuffer at: %08lx\n", size>>10, addr);
 
-	return (addr);
+	return addr;
 }
 
 /*----------------------------------------------------------------------*/
 
-static void lcd_setfgcolor (int color)
+static void lcd_setfgcolor(int color)
 {
 	lcd_color_fg = color;
 }
 
 /*----------------------------------------------------------------------*/
 
-static void lcd_setbgcolor (int color)
+static void lcd_setbgcolor(int color)
 {
 	lcd_color_bg = color;
 }
@@ -480,7 +480,7 @@ static void lcd_setbgcolor (int color)
 /*----------------------------------------------------------------------*/
 
 #ifdef	NOT_USED_SO_FAR
-static int lcd_getfgcolor (void)
+static int lcd_getfgcolor(void)
 {
 	return lcd_color_fg;
 }
@@ -488,7 +488,7 @@ static int lcd_getfgcolor (void)
 
 /*----------------------------------------------------------------------*/
 
-static int lcd_getbgcolor (void)
+static int lcd_getbgcolor(void)
 {
 	return lcd_color_bg;
 }
@@ -499,7 +499,7 @@ static int lcd_getbgcolor (void)
 /* ** Chipset depending Bitmap / Logo stuff...                          */
 /************************************************************************/
 #ifdef CONFIG_LCD_LOGO
-void bitmap_plot (int x, int y)
+void bitmap_plot(int x, int y)
 {
 #ifdef CONFIG_ATMEL_LCD
 	uint *cmap;
@@ -517,7 +517,7 @@ void bitmap_plot (int x, int y)
 	volatile cpm8xx_t *cp = &(immr->im_cpm);
 #endif
 
-	debug ("Logo: width %d  height %d  colors %d  cmap %d\n",
+	debug("Logo: width %d  height %d  colors %d  cmap %d\n",
 		BMP_LOGO_WIDTH, BMP_LOGO_HEIGHT, BMP_LOGO_COLORS,
 		ARRAY_SIZE(bmp_logo_palette));
 
@@ -527,9 +527,9 @@ void bitmap_plot (int x, int y)
 	if (NBITS(panel_info.vl_bpix) < 12) {
 		/* Leave room for default color map */
 #if defined(CONFIG_CPU_PXA)
-		cmap = (ushort *)fbi->palette;
+		cmap = (ushort *) fbi->palette;
 #elif defined(CONFIG_MPC823)
-		cmap = (ushort *)&(cp->lcd_cmap[BMP_LOGO_OFFSET*sizeof(ushort)]);
+		cmap = (ushort *) &(cp->lcd_cmap[BMP_LOGO_OFFSET * sizeof(ushort)]);
 #elif defined(CONFIG_ATMEL_LCD)
 		cmap = (uint *) (panel_info.mmio + ATMEL_LCDC_LUT(0));
 #else
@@ -550,12 +550,12 @@ void bitmap_plot (int x, int y)
 			uint lut_entry;
 #ifdef CONFIG_ATMEL_LCD_BGR555
 			lut_entry = ((colreg & 0x000F) << 11) |
-				    ((colreg & 0x00F0) <<  2) |
-				    ((colreg & 0x0F00) >>  7);
+					((colreg & 0x00F0) <<  2) |
+					((colreg & 0x0F00) >>  7);
 #else /* CONFIG_ATMEL_LCD_RGB565 */
 			lut_entry = ((colreg & 0x000F) << 1) |
-				    ((colreg & 0x00F0) << 3) |
-				    ((colreg & 0x0F00) << 4);
+					((colreg & 0x00F0) << 3) |
+					((colreg & 0x0F00) << 4);
 #endif
 			*(cmap + BMP_LOGO_OFFSET) = lut_entry;
 			cmap++;
@@ -570,8 +570,8 @@ void bitmap_plot (int x, int y)
 
 		WATCHDOG_RESET();
 
-		for (i=0; i<BMP_LOGO_HEIGHT; ++i) {
-			memcpy (fb, bmap, BMP_LOGO_WIDTH);
+		for (i = 0; i < BMP_LOGO_HEIGHT; ++i) {
+			memcpy(fb, bmap, BMP_LOGO_WIDTH);
 			bmap += BMP_LOGO_WIDTH;
 			fb   += panel_info.vl_col;
 		}
@@ -579,8 +579,8 @@ void bitmap_plot (int x, int y)
 	else { /* true color mode */
 		u16 col16;
 		fb16 = (ushort *)(lcd_base + y * lcd_line_length + x);
-		for (i=0; i<BMP_LOGO_HEIGHT; ++i) {
-			for (j=0; j<BMP_LOGO_WIDTH; j++) {
+		for (i = 0; i < BMP_LOGO_HEIGHT; ++i) {
+			for (j = 0; j < BMP_LOGO_WIDTH; j++) {
 				col16 = bmp_logo_palette[(bmap[j]-16)];
 				fb16[j] =
 					((col16 & 0x000F) << 1) |
@@ -630,14 +630,15 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 	volatile cpm8xx_t *cp = &(immr->im_cpm);
 #endif
 
-	if (!((bmp->header.signature[0]=='B') &&
-		(bmp->header.signature[1]=='M'))) {
-		printf ("Error: no valid bmp image at %lx\n", bmp_image);
+	if (!((bmp->header.signature[0] == 'B') &&
+		(bmp->header.signature[1] == 'M'))) {
+		printf("Error: no valid bmp image at %lx\n", bmp_image);
+
 		return 1;
 	}
 
-	width = le32_to_cpu (bmp->header.width);
-	height = le32_to_cpu (bmp->header.height);
+	width = le32_to_cpu(bmp->header.width);
+	height = le32_to_cpu(bmp->header.height);
 	bmp_bpix = le16_to_cpu(bmp->header.bit_count);
 	colors = 1 << bmp_bpix;
 
@@ -646,6 +647,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 	if ((bpix != 1) && (bpix != 8) && (bpix != 16) && (bpix != 32)) {
 		printf ("Error: %d bit/pixel mode, but BMP has %d bit/pixel\n",
 			bpix, bmp_bpix);
+
 		return 1;
 	}
 
@@ -654,10 +656,11 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 		printf ("Error: %d bit/pixel mode, but BMP has %d bit/pixel\n",
 			bpix,
 			le16_to_cpu(bmp->header.bit_count));
+
 		return 1;
 	}
 
-	debug ("Display-bmp: %d x %d  with %d colors\n",
+	debug("Display-bmp: %d x %d  with %d colors\n",
 		(int)width, (int)height, (int)colors);
 
 #if !defined(CONFIG_MCC200)
@@ -674,7 +677,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 		cmap_base = cmap;
 
 		/* Set color map */
-		for (i=0; i<colors; ++i) {
+		for (i = 0; i < colors; ++i) {
 			bmp_color_table_entry_t cte = bmp->color_table[i];
 #if !defined(CONFIG_ATMEL_LCD)
 			ushort colreg =
@@ -709,8 +712,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 	 * specific.
 	 */
 #if defined(CONFIG_MCC200)
-	if (bpix==1)
-	{
+	if (bpix == 1) {
 		width = ((width + 7) & ~7) >> 3;
 		x     = ((x + 7) & ~7) >> 3;
 		pwidth= ((pwidth + 7) & ~7) >> 3;
@@ -731,12 +733,12 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 		y = max(0, panel_info.vl_row - height + y + 1);
 #endif /* CONFIG_SPLASH_SCREEN_ALIGN */
 
-	if ((x + width)>pwidth)
+	if ((x + width) > pwidth)
 		width = pwidth - x;
-	if ((y + height)>panel_info.vl_row)
+	if ((y + height) > panel_info.vl_row)
 		height = panel_info.vl_row - y;
 
-	bmap = (uchar *)bmp + le32_to_cpu (bmp->header.data_offset);
+	bmap = (uchar *)bmp + le32_to_cpu(bmp->header.data_offset);
 	fb   = (uchar *) (lcd_base +
 		(y + height - 1) * lcd_line_length + x * bpix / 8);
 
@@ -806,11 +808,11 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 		break;
 	};
 
-	return (0);
+	return 0;
 }
 #endif
 
-static void *lcd_logo (void)
+static void *lcd_logo(void)
 {
 #ifdef CONFIG_SPLASH_SCREEN
 	char *s;
@@ -823,13 +825,15 @@ static void *lcd_logo (void)
 
 		addr = simple_strtoul (s, NULL, 16);
 #ifdef CONFIG_SPLASH_SCREEN_ALIGN
-		if ((s = getenv ("splashpos")) != NULL) {
+		s = getenv("splashpos");
+		if (s != NULL) {
 			if (s[0] == 'm')
 				x = BMP_ALIGN_CENTER;
 			else
-				x = simple_strtol (s, NULL, 0);
+				x = simple_strtol(s, NULL, 0);
 
-			if ((s = strchr (s + 1, ',')) != NULL) {
+			s = strchr(s + 1, ',');
+			if (s != NULL) {
 				if (s[1] == 'm')
 					y = BMP_ALIGN_CENTER;
 				else
@@ -842,15 +846,14 @@ static void *lcd_logo (void)
 		bmp_image_t *bmp = (bmp_image_t *)addr;
 		unsigned long len;
 
-		if (!((bmp->header.signature[0]=='B') &&
-		      (bmp->header.signature[1]=='M'))) {
+		if (!((bmp->header.signature[0] == 'B') &&
+			(bmp->header.signature[1] == 'M'))) {
 			addr = (ulong)gunzip_bmp(addr, &len);
 		}
 #endif
 
-		if (lcd_display_bitmap (addr, x, y) == 0) {
-			return ((void *)lcd_base);
-		}
+		if (lcd_display_bitmap(addr, x, y) == 0)
+			return (void *)lcd_base;
 	}
 #endif /* CONFIG_SPLASH_SCREEN */
 
@@ -863,9 +866,9 @@ static void *lcd_logo (void)
 #endif /* CONFIG_LCD_INFO */
 
 #if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO)
-	return ((void *)((ulong)lcd_base + BMP_LOGO_HEIGHT * lcd_line_length));
+	return (void *)((ulong)lcd_base + BMP_LOGO_HEIGHT * lcd_line_length);
 #else
-	return ((void *)lcd_base);
+	return (void *)lcd_base;
 #endif /* CONFIG_LCD_LOGO && !CONFIG_LCD_INFO_BELOW_LOGO */
 }
 

common/usb.c

@@ -188,7 +188,8 @@ int usb_control_msg(struct usb_device *dev, unsigned int pipe,
 		   request, requesttype, value, index, size);
 	dev->status = USB_ST_NOT_PROC; /*not yet processed */
 
-	submit_control_msg(dev, pipe, data, size, setup_packet);
+	if (submit_control_msg(dev, pipe, data, size, setup_packet) < 0)
+		return -1;
 	if (timeout == 0)
 		return (int)size;
 
@@ -220,7 +221,8 @@ int usb_bulk_msg(struct usb_device *dev, unsigned int pipe,
 	if (len < 0)
 		return -1;
 	dev->status = USB_ST_NOT_PROC; /*not yet processed */
-	submit_bulk_msg(dev, pipe, data, len);
+	if (submit_bulk_msg(dev, pipe, data, len) < 0)
+		return -1;
 	while (timeout--) {
 		if (!((volatile unsigned long)dev->status & USB_ST_NOT_PROC))
 			break;
@@ -799,12 +801,13 @@ int usb_new_device(struct usb_device *dev)
 	dev->epmaxpacketin[0] = 8;
 	dev->epmaxpacketout[0] = 8;
 
-	err = usb_get_descriptor(dev, USB_DT_DEVICE, 0, &dev->descriptor, 8);
+	err = usb_get_descriptor(dev, USB_DT_DEVICE, 0, tmpbuf, 8);
 	if (err < 8) {
 		printf("\n      USB device not responding, " \
 		       "giving up (status=%lX)\n", dev->status);
 		return 1;
 	}
+	memcpy(&dev->descriptor, tmpbuf, 8);
 #else
 	/* This is a Windows scheme of initialization sequence, with double
 	 * reset of the device (Linux uses the same sequence)
@@ -893,7 +896,7 @@ int usb_new_device(struct usb_device *dev)
 	tmp = sizeof(dev->descriptor);
 
 	err = usb_get_descriptor(dev, USB_DT_DEVICE, 0,
-				 &dev->descriptor, sizeof(dev->descriptor));
+				 tmpbuf, sizeof(dev->descriptor));
 	if (err < tmp) {
 		if (err < 0)
 			printf("unable to get device descriptor (error=%d)\n",
@@ -903,6 +906,7 @@ int usb_new_device(struct usb_device *dev)
 				"(expected %i, got %i)\n", tmp, err);
 		return 1;
 	}
+	memcpy(&dev->descriptor, tmpbuf, sizeof(dev->descriptor));
 	/* correct le values */
 	le16_to_cpus(&dev->descriptor.bcdUSB);
 	le16_to_cpus(&dev->descriptor.idVendor);

common/usb_storage.c

@@ -150,12 +150,17 @@ struct us_data {
 	unsigned int	irqpipe;	 	/* pipe for release_irq */
 	unsigned char	irqmaxp;		/* max packed for irq Pipe */
 	unsigned char	irqinterval;		/* Intervall for IRQ Pipe */
-	unsigned long	max_xfer_blk;		/* Max blocks per xfer */
 	ccb		*srb;			/* current srb */
 	trans_reset	transport_reset;	/* reset routine */
 	trans_cmnd	transport;		/* transport routine */
 };
 
+/*
+ * The U-Boot EHCI driver cannot handle more than 5 page aligned buffers
+ * of 4096 bytes in a transfer without running itself out of qt_buffers
+ */
+#define USB_MAX_XFER_BLK(start, blksz)	(((4096 * 5) - (start % 4096)) / blksz)
+
 static struct us_data usb_stor[USB_MAX_STOR_DEV];
 
 
@@ -1041,7 +1046,7 @@ static void usb_bin_fixup(struct usb_device_descriptor descriptor,
 unsigned long usb_stor_read(int device, unsigned long blknr,
 			    unsigned long blkcnt, void *buffer)
 {
-	unsigned long start, blks, buf_addr;
+	unsigned long start, blks, buf_addr, max_xfer_blk;
 	unsigned short smallblks;
 	struct usb_device *dev;
 	struct us_data *ss;
@@ -1083,12 +1088,14 @@ unsigned long usb_stor_read(int device, unsigned long blknr,
 		/* XXX need some comment here */
 		retry = 2;
 		srb->pdata = (unsigned char *)buf_addr;
-		if (blks > ss->max_xfer_blk)
-			smallblks = ss->max_xfer_blk;
+		max_xfer_blk = USB_MAX_XFER_BLK(buf_addr,
+						usb_dev_desc[device].blksz);
+		if (blks > max_xfer_blk)
+			smallblks = (unsigned short) max_xfer_blk;
 		else
 			smallblks = (unsigned short) blks;
 retry_it:
-		if (smallblks == ss->max_xfer_blk)
+		if (smallblks == max_xfer_blk)
 			usb_show_progress();
 		srb->datalen = usb_dev_desc[device].blksz * smallblks;
 		srb->pdata = (unsigned char *)buf_addr;
@@ -1109,7 +1116,7 @@ retry_it:
 			start, smallblks, buf_addr);
 
 	usb_disable_asynch(0); /* asynch transfer allowed */
-	if (blkcnt >= ss->max_xfer_blk)
+	if (blkcnt >= max_xfer_blk)
 		debug("\n");
 	return blkcnt;
 }
@@ -1117,7 +1124,7 @@ retry_it:
 unsigned long usb_stor_write(int device, unsigned long blknr,
 				unsigned long blkcnt, const void *buffer)
 {
-	unsigned long start, blks, buf_addr;
+	unsigned long start, blks, buf_addr, max_xfer_blk;
 	unsigned short smallblks;
 	struct usb_device *dev;
 	struct us_data *ss;
@@ -1162,12 +1169,14 @@ unsigned long usb_stor_write(int device, unsigned long blknr,
 		 */
 		retry = 2;
 		srb->pdata = (unsigned char *)buf_addr;
-		if (blks > ss->max_xfer_blk)
-			smallblks = ss->max_xfer_blk;
+		max_xfer_blk = USB_MAX_XFER_BLK(buf_addr,
+						usb_dev_desc[device].blksz);
+		if (blks > max_xfer_blk)
+			smallblks = (unsigned short) max_xfer_blk;
 		else
 			smallblks = (unsigned short) blks;
 retry_it:
-		if (smallblks == ss->max_xfer_blk)
+		if (smallblks == max_xfer_blk)
 			usb_show_progress();
 		srb->datalen = usb_dev_desc[device].blksz * smallblks;
 		srb->pdata = (unsigned char *)buf_addr;
@@ -1188,7 +1197,7 @@ retry_it:
 			start, smallblks, buf_addr);
 
 	usb_disable_asynch(0); /* asynch transfer allowed */
-	if (blkcnt >= ss->max_xfer_blk)
+	if (blkcnt >= max_xfer_blk)
 		debug("\n");
 	return blkcnt;
 
@@ -1415,12 +1424,6 @@ int usb_stor_get_info(struct usb_device *dev, struct us_data *ss,
 	USB_STOR_PRINTF(" address %d\n", dev_desc->target);
 	USB_STOR_PRINTF("partype: %d\n", dev_desc->part_type);
 
-	/*
-	 * The U-Boot EHCI driver cannot handle more than 4096 * 5 bytes in a
-	 * transfer without running itself out of qt_buffers.
-	 */
-	ss->max_xfer_blk = (4096 * 5) / dev_desc->blksz;
-
 	init_part(dev_desc);
 
 	USB_STOR_PRINTF("partype: %d\n", dev_desc->part_type);

doc/README.mpc85xx

@@ -26,15 +26,15 @@ Major Config Switches during various boot Modes
 ----------------------------------------------
 
 NOR boot
-                !defined(CONFIG_SYS_RAMBOOT)
+		!defined(CONFIG_SYS_RAMBOOT)
 NOR boot Secure
-                !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
+		!defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
 RAMBOOT(SD, SPI & NAND boot)
-                 defined(CONFIG_SYS_RAMBOOT)
+		 defined(CONFIG_SYS_RAMBOOT)
 RAMBOOT Secure (SD, SPI & NAND)
-                 defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
+		 defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
 NAND SPL BOOT
-                 defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_NAND_SPL)
+		 defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_NAND_SPL)
 
 
 TLB Entries during u-boot execution
@@ -45,44 +45,44 @@ Note: Sequence number is in order of execution
 A) defined(CONFIG_SYS_RAMBOOT) i.e. SD, SPI, NAND RAMBOOT & NAND_SPL boot
 
    1) TLB entry to overcome e500 v1/v2 debug restriction
-       Location   : Label "_start_e500"
+       Location	  : Label "_start_e500"
        TLB Entry  : CONFIG_SYS_PPC_E500_DEBUG_TLB
        EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_MONITOR_BASE
        Properties : 256K, AS0, I, IPROT
 
    2) TLB entry for working in AS1
-       Location   : Label "create_init_ram_area"
+       Location	  : Label "create_init_ram_area"
        TLB Entry  : 15
        EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_MONITOR_BASE
        Properties : 1M, AS1, I, G, IPROT
 
    3) TLB entry for the stack during AS1
-       Location   : Lable "create_init_ram_area"
+       Location	  : Lable "create_init_ram_area"
        TLB Entry  : 14
        EPN -->RPN : CONFIG_SYS_INIT_RAM_ADDR --> CONFIG_SYS_INIT_RAM_ADDR
        Properties : 16K, AS1, IPROT
 
    4) TLB entry for CCSRBAR during AS1 execution
-       Location   : cpu_init_early_f
+       Location	  : cpu_init_early_f
        TLB Entry  : 13
        EPN -->RPN : CONFIG_SYS_CCSRBAR --> CONFIG_SYS_CCSRBAR
        Properties : 1M, AS1, I, G
 
    5) Invalidate unproctected TLB Entries
-       Location   : cpu_init_early_f
+       Location	  : cpu_init_early_f
        Invalidated: 13
 
    6) Create TLB entries as per boards/freescale/<board>/tlb.c
-       Location   : cpu_init_early_f --> init_tlbs()
+       Location	  : cpu_init_early_f --> init_tlbs()
        Properties : ..., AS0, ...
       Please note It can overwrites previous TLB Entries.
 
    7) Disable TLB Entries of AS1
-       Location   : cpu_init_f --> disable_tlb()
-       Disable    : 15, 14
+       Location	  : cpu_init_f --> disable_tlb()
+       Disable	  : 15, 14
 
    8) Update Flash's TLB entry
-       Location   : Board_init_r
+       Location	  : Board_init_r
        TLB entry  : Search from TLB entries
        EPN -->RPN : CONFIG_SYS_FLASH_BASE --> CONFIG_SYS_FLASH_BASE_PHYS
        Properties : Board specific size, AS0, I, G, IPROT
@@ -91,7 +91,7 @@ A) defined(CONFIG_SYS_RAMBOOT) i.e. SD, SPI, NAND RAMBOOT & NAND_SPL boot
 B) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot
 
    1) TLB entry to overcome e500 v1/v2 debug restriction
-       Location   : Label "_start_e500"
+       Location	  : Label "_start_e500"
        TLB Entry  : CONFIG_SYS_PPC_E500_DEBUG_TLB
 #if defined(CONFIG_SECURE_BOOT)
        EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW
@@ -102,7 +102,7 @@ B) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot
 #endif
 
    2) TLB entry for working in AS1
-       Location   : Label "create_init_ram_area"
+       Location	  : Label "create_init_ram_area"
        TLB Entry  : 15
 #if defined(CONFIG_SECURE_BOOT)
        EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW
@@ -113,54 +113,54 @@ B) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot
 #endif
 
    3) TLB entry for the stack during AS1
-       Location   : Lable "create_init_ram_area"
+       Location	  : Lable "create_init_ram_area"
        TLB Entry  : 14
        EPN -->RPN : CONFIG_SYS_INIT_RAM_ADDR --> CONFIG_SYS_INIT_RAM_ADDR
        Properties : 16K, AS1, IPROT
 
    4) TLB entry for CCSRBAR during AS1 execution
-       Location   : cpu_init_early_f
+       Location	  : cpu_init_early_f
        TLB Entry  : 13
        EPN -->RPN : CONFIG_SYS_CCSRBAR --> CONFIG_SYS_CCSRBAR
        Properties : 1M, AS1, I, G
 
    5) TLB entry for Errata workaround CONFIG_SYS_FSL_ERRATUM_IFC_A003399
-       Location   : cpu_init_early_f
+       Location	  : cpu_init_early_f
        TLB Entry  : 9
        EPN -->RPN : SRAM_BASE_ADDR --> SRAM_BASE_ADDR
        Properties : 1M, AS1, I
 
    6) CONFIG_SYS_FSL_ERRATUM_IFC_A003399 Adjust flash's phys addr
-       Location   : cpu_init_early_f --> setup_ifc
+       Location	  : cpu_init_early_f --> setup_ifc
        TLB Entry  : Get Flash TLB
        EPN -->RPN : Adjusted flash_phys --> Adjusted flash_phys
        Properties : 4M, AS1, I, G, IPROT
 
    7) CONFIG_SYS_FSL_ERRATUM_IFC_A003399: E500 v1,v2 debug restriction
-       Location   : cpu_init_early_f --> setup_ifc
+       Location	  : cpu_init_early_f --> setup_ifc
        TLB Entry  : CONFIG_SYS_PPC_E500_DEBUG_TLB
        EPN -->RPN : Adjusted flash_phys --> Adjusted flash_phys
        Properties : 4M, AS0, I, G, IPROT
 
    8) Invalidate unproctected TLB Entries
-       Location   : cpu_init_early_f
+       Location	  : cpu_init_early_f
        Invalidated: 13, 9
 
    9) Create TLB entries as per boards/freescale/<board>/tlb.c
-       Location   : cpu_init_early_f --> init_tlbs()
+       Location	  : cpu_init_early_f --> init_tlbs()
        Properties : ..., AS0, ...
       Note: It can overwrites previous TLB Entries
 
    10) Disable TLB Entries of AS1
-       Location   : cpu_init_f --> disable_tlb()
-       Disable    : 15, 14
+       Location	  : cpu_init_f --> disable_tlb()
+       Disable	  : 15, 14
 
    11) Create DDR's TLB entriy
-       Location   : Board_init_f -> init_func_ram -> initdram
+       Location	  : Board_init_f -> init_func_ram -> initdram
        TLB entry  : Search free TLB entry
 
    12) Update Flash's TLB entry
-       Location   : Board_init_r
+       Location	  : Board_init_r
        TLB entry  : Search from TLB entries
        EPN -->RPN : CONFIG_SYS_FLASH_BASE --> CONFIG_SYS_FLASH_BASE_PHYS
        Properties : Board specific size, AS0, I, G, IPROT

doc/README.mx28_common

@@ -19,6 +19,7 @@ Contents
 1) Prerequisites
 2) Compiling U-Boot for a MX28 based board
 3) Installation of U-Boot for a MX28 based board to SD card
+4) Installation of U-Boot into NAND flash
 
 1) Prerequisites
 ----------------
@@ -29,14 +30,14 @@ is the "mxsboot" tool found in U-Boot source tree.
 
 Firstly, obtain the elftosb archive from the following location:
 
-	http://foss.doredevelopment.dk/mirrors/imx/elftosb-10.12.01.tar.gz
+	ftp://ftp.denx.de/pub/tools/elftosb-10.12.01.tar.gz
 
 We use a $VER variable here to denote the current version. At the time of
 writing of this document, that is "10.12.01". To obtain the file from command
 line, use:
 
 	$ VER="10.12.01"
-	$ wget http://foss.doredevelopment.dk/mirrors/imx/elftosb-${VER}.tar.gz
+	$ wget ftp://ftp.denx.de/pub/tools/elftosb-${VER}.tar.gz
 
 Extract the file:
 
@@ -146,8 +147,8 @@ NOTE: If the user needs to adjust the start sector, the "mxsboot" tool contains
       a "-p" switch for that purpose. The "-p" switch takes the sector number as
       an argument.
 
-4) Installation of U-Boot for NAND flash
------------------------------------------------
+4) Installation of U-Boot into NAND flash
+-----------------------------------------
 
 To boot a MX28 based board from NAND, set the boot mode DIP switches according to i.MX28
 manual chapter 12.2.1 (Table 12-2), PORT=GPMI, NAND 1.8 V.

drivers/i2c/mxc_i2c.c

@@ -59,27 +59,10 @@ struct mxc_i2c_regs {
 #define I2SR_IIF	(1 << 1)
 #define I2SR_RX_NO_AK	(1 << 0)
 
-#if defined(CONFIG_SYS_I2C_MX31_PORT1)
-#define I2C_BASE	0x43f80000
-#define I2C_CLK_OFFSET	26
-#elif defined (CONFIG_SYS_I2C_MX31_PORT2)
-#define I2C_BASE	0x43f98000
-#define I2C_CLK_OFFSET	28
-#elif defined (CONFIG_SYS_I2C_MX31_PORT3)
-#define I2C_BASE	0x43f84000
-#define I2C_CLK_OFFSET	30
-#elif defined(CONFIG_SYS_I2C_MX53_PORT1)
-#define I2C_BASE        I2C1_BASE_ADDR
-#elif defined(CONFIG_SYS_I2C_MX53_PORT2)
-#define I2C_BASE        I2C2_BASE_ADDR
-#elif defined(CONFIG_SYS_I2C_MX35_PORT1)
-#define I2C_BASE	I2C_BASE_ADDR
-#elif defined(CONFIG_SYS_I2C_MX35_PORT2)
-#define I2C_BASE	I2C2_BASE_ADDR
-#elif defined(CONFIG_SYS_I2C_MX35_PORT3)
-#define I2C_BASE	I2C3_BASE_ADDR
+#ifdef CONFIG_SYS_I2C_BASE
+#define I2C_BASE	CONFIG_SYS_I2C_BASE
 #else
-#error "define CONFIG_SYS_I2C_MX<Processor>_PORTx to use the mx I2C driver"
+#error "define CONFIG_SYS_I2C_BASE to use the mxc_i2c driver"
 #endif
 
 #define I2C_MAX_TIMEOUT		10000
@@ -114,7 +97,7 @@ static uint8_t i2c_imx_get_clk(unsigned int rate)
 		(struct clock_control_regs *)CCM_BASE;
 
 	/* start the required I2C clock */
-	writel(readl(&sc_regs->cgr0) | (3 << I2C_CLK_OFFSET),
+	writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET),
 		&sc_regs->cgr0);
 #endif
 
@@ -248,12 +231,6 @@ int i2c_imx_start(void)
 	struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
 	unsigned int temp = 0;
 	int result;
-	int speed = i2c_get_bus_speed();
-	u8 clk_idx = i2c_imx_get_clk(speed);
-	u8 idx = i2c_clk_div[clk_idx][1];
-
-	/* Store divider value */
-	writeb(idx, &i2c_regs->ifdr);
 
 	/* Enable I2C controller */
 	writeb(0, &i2c_regs->i2sr);

drivers/i2c/mxs_i2c.c

@@ -97,7 +97,7 @@ void mxs_i2c_write(uchar chip, uint addr, int alen,
 
 	for (i = 0; i < alen; i++) {
 		data >>= 8;
-		data |= ((char *)&addr)[i] << 24;
+		data |= ((char *)&addr)[alen - i - 1] << 24;
 		if ((i & 3) == 2)
 			writel(data, &i2c_regs->hw_i2c_data);
 	}

drivers/mmc/fsl_esdhc.c

@@ -190,6 +190,10 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
 		esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
 		esdhc_write32(&regs->dsaddr, (u32)data->dest);
 	} else {
+		flush_dcache_range((ulong)data->src,
+				   (ulong)data->src+data->blocks
+					 *data->blocksize);
+
 		if (wml_value > WML_WR_WML_MAX)
 			wml_value = WML_WR_WML_MAX_VAL;
 		if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) {
@@ -249,7 +253,15 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
 	return 0;
 }
 
-
+static void check_and_invalidate_dcache_range
+	(struct mmc_cmd *cmd,
+	 struct mmc_data *data) {
+	unsigned start = (unsigned)data->dest ;
+	unsigned size = roundup(ARCH_DMA_MINALIGN,
+				data->blocks*data->blocksize);
+	unsigned end = start+size ;
+	invalidate_dcache_range(start, end);
+}
 /*
  * Sends a command out on the bus.  Takes the mmc pointer,
  * a command pointer, and an optional data pointer.
@@ -315,6 +327,9 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 	while (!(esdhc_read32(&regs->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE)))
 		;
 
+	if (data && (data->flags & MMC_DATA_READ))
+		check_and_invalidate_dcache_range(cmd, data);
+
 	irqstat = esdhc_read32(&regs->irqstat);
 	esdhc_write32(&regs->irqstat, irqstat);
 
@@ -528,6 +543,9 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
 	/* First reset the eSDHC controller */
 	esdhc_reset(regs);
 
+	esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
+				| SYSCTL_IPGEN | SYSCTL_CKEN);
+
 	mmc->priv = cfg;
 	mmc->send_cmd = esdhc_send_cmd;
 	mmc->set_ios = esdhc_set_ios;

drivers/mmc/mmc.c

@@ -333,6 +333,7 @@ mmc_berase(int dev_num, unsigned long start, lbaint_t blkcnt)
 	int err = 0;
 	struct mmc *mmc = find_mmc_device(dev_num);
 	lbaint_t blk = 0, blk_r = 0;
+	int timeout = 1000;
 
 	if (!mmc)
 		return -1;
@@ -352,6 +353,10 @@ mmc_berase(int dev_num, unsigned long start, lbaint_t blkcnt)
 			break;
 
 		blk += blk_r;
+
+		/* Waiting for the ready status */
+		if (mmc_send_status(mmc, timeout))
+			return 0;
 	}
 
 	return blk;
@@ -1195,9 +1200,9 @@ int mmc_startup(struct mmc *mmc)
 		}
 
 		if (mmc->card_caps & MMC_MODE_HS)
-			mmc_set_clock(mmc, 50000000);
+			mmc->tran_speed = 50000000;
 		else
-			mmc_set_clock(mmc, 25000000);
+			mmc->tran_speed = 25000000;
 	} else {
 		width = ((mmc->host_caps & MMC_MODE_MASK_WIDTH_BITS) >>
 			 MMC_MODE_WIDTH_BITS_SHIFT);
@@ -1234,13 +1239,14 @@ int mmc_startup(struct mmc *mmc)
 
 		if (mmc->card_caps & MMC_MODE_HS) {
 			if (mmc->card_caps & MMC_MODE_HS_52MHz)
-				mmc_set_clock(mmc, 52000000);
+				mmc->tran_speed = 52000000;
 			else
-				mmc_set_clock(mmc, 26000000);
-		} else
-			mmc_set_clock(mmc, 20000000);
+				mmc->tran_speed = 26000000;
+		}
 	}
 
+	mmc_set_clock(mmc, mmc->tran_speed);
+
 	/* fill in device description */
 	mmc->block_dev.lun = 0;
 	mmc->block_dev.type = 0;
@@ -1305,8 +1311,11 @@ int mmc_register(struct mmc *mmc)
 block_dev_desc_t *mmc_get_dev(int dev)
 {
 	struct mmc *mmc = find_mmc_device(dev);
+	if (!mmc)
+		return NULL;
 
-	return mmc ? &mmc->block_dev : NULL;
+	mmc_init(mmc);
+	return &mmc->block_dev;
 }
 #endif
 

drivers/mtd/spi/eon.c

@@ -11,17 +11,8 @@
 #include "spi_flash_internal.h"
 
 /* EN25Q128-specific commands */
-#define CMD_EN25Q128_WREN	0x06    /* Write Enable */
-#define CMD_EN25Q128_WRDI	0x04    /* Write Disable */
-#define CMD_EN25Q128_RDSR	0x05    /* Read Status Register */
-#define CMD_EN25Q128_WRSR	0x01    /* Write Status Register */
-#define CMD_EN25Q128_READ	0x03    /* Read Data Bytes */
-#define CMD_EN25Q128_FAST_READ	0x0b    /* Read Data Bytes at Higher Speed */
-#define CMD_EN25Q128_PP		0x02    /* Page Program */
 #define CMD_EN25Q128_SE		0x20    /* Sector Erase */
 #define CMD_EN25Q128_BE		0xd8    /* Block Erase */
-#define CMD_EN25Q128_DP		0xb9    /* Deep Power-down */
-#define CMD_EN25Q128_RES	0xab    /* Release from DP, and Read Signature */
 
 struct eon_spi_flash_params {
 	u8 idcode1;

drivers/mtd/spi/macronix.c

@@ -36,18 +36,9 @@
 #include "spi_flash_internal.h"
 
 /* MX25xx-specific commands */
-#define CMD_MX25XX_WREN		0x06	/* Write Enable */
-#define CMD_MX25XX_WRDI		0x04	/* Write Disable */
-#define CMD_MX25XX_RDSR		0x05	/* Read Status Register */
-#define CMD_MX25XX_WRSR		0x01	/* Write Status Register */
-#define CMD_MX25XX_READ		0x03	/* Read Data Bytes */
-#define CMD_MX25XX_FAST_READ	0x0b	/* Read Data Bytes at Higher Speed */
-#define CMD_MX25XX_PP		0x02	/* Page Program */
 #define CMD_MX25XX_SE		0x20	/* Sector Erase */
 #define CMD_MX25XX_BE		0xD8	/* Block Erase */
 #define CMD_MX25XX_CE		0xc7	/* Chip Erase */
-#define CMD_MX25XX_DP		0xb9	/* Deep Power-down */
-#define CMD_MX25XX_RES		0xab	/* Release from DP, and Read Signature */
 
 struct macronix_spi_flash_params {
 	u16 idcode;
@@ -128,7 +119,7 @@ static int macronix_write_status(struct spi_flash *flash, u8 sr)
 		return ret;
 	}
 
-	cmd = CMD_MX25XX_WRSR;
+	cmd = CMD_WRITE_STATUS;
 	ret = spi_flash_cmd_write(flash->spi, &cmd, 1, &sr, 1);
 	if (ret) {
 		debug("SF: fail to write status register\n");

drivers/mtd/spi/ramtron.c

@@ -54,19 +54,6 @@
 #include <spi_flash.h>
 #include "spi_flash_internal.h"
 
-/* RAMTRON commands common to all devices */
-#define CMD_RAMTRON_WREN	0x06	/* Write Enable */
-#define CMD_RAMTRON_WRDI	0x04	/* Write Disable */
-#define CMD_RAMTRON_RDSR	0x05	/* Read Status Register */
-#define CMD_RAMTRON_WRSR	0x01	/* Write Status Register */
-#define CMD_RAMTRON_READ	0x03	/* Read Data Bytes */
-#define CMD_RAMTRON_WRITE	0x02	/* Write Data Bytes */
-/* not all have those: */
-#define CMD_RAMTRON_FSTRD	0x0b	/* Fast Read (for compatibility - not used here) */
-#define CMD_RAMTRON_SLEEP	0xb9	/* Enter Sleep Mode */
-#define CMD_RAMTRON_RDID	0x9f	/* Read ID */
-#define CMD_RAMTRON_SNR		0xc3	/* Read Serial Number */
-
 /*
  * Properties of supported FRAMs
  * Note: speed is currently not used because we have no method to deliver that
@@ -196,7 +183,7 @@ static int ramtron_common(struct spi_flash *flash,
 		return ret;
 	}
 
-	if (command == CMD_RAMTRON_WRITE) {
+	if (command == CMD_PAGE_PROGRAM) {
 		/* send WREN */
 		ret = spi_flash_cmd_write_enable(flash);
 		if (ret < 0) {
@@ -206,7 +193,7 @@ static int ramtron_common(struct spi_flash *flash,
 	}
 
 	/* do the transaction */
-	if (command == CMD_RAMTRON_WRITE)
+	if (command == CMD_PAGE_PROGRAM)
 		ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len, buf, len);
 	else
 		ret = spi_flash_cmd_read(flash->spi, cmd, cmd_len, buf, len);
@@ -223,14 +210,14 @@ static int ramtron_read(struct spi_flash *flash,
 		u32 offset, size_t len, void *buf)
 {
 	return ramtron_common(flash, offset, len, buf,
-		CMD_RAMTRON_READ);
+		CMD_READ_ARRAY_SLOW);
 }
 
 static int ramtron_write(struct spi_flash *flash,
 		u32 offset, size_t len, const void *buf)
 {
 	return ramtron_common(flash, offset, len, (void *)buf,
-		CMD_RAMTRON_WRITE);
+		CMD_PAGE_PROGRAM);
 }
 
 static int ramtron_erase(struct spi_flash *flash, u32 offset, size_t len)
@@ -270,7 +257,7 @@ struct spi_flash *spi_fram_probe_ramtron(struct spi_slave *spi, u8 *idcode)
 		 * We COULD have a non JEDEC conformant FRAM here,
 		 * read the status register to verify
 		 */
-		ret = spi_flash_cmd(spi, CMD_RAMTRON_RDSR, &sr, 1);
+		ret = spi_flash_cmd(spi, CMD_READ_STATUS, &sr, 1);
 		if (ret)
 			return NULL;
 

drivers/mtd/spi/spansion.c

@@ -32,28 +32,8 @@
 #include "spi_flash_internal.h"
 
 /* S25FLxx-specific commands */
-#define CMD_S25FLXX_READ	0x03	/* Read Data Bytes */
-#define CMD_S25FLXX_FAST_READ	0x0b	/* Read Data Bytes at Higher Speed */
-#define CMD_S25FLXX_READID	0x90	/* Read Manufacture ID and Device ID */
-#define CMD_S25FLXX_WREN	0x06	/* Write Enable */
-#define CMD_S25FLXX_WRDI	0x04	/* Write Disable */
-#define CMD_S25FLXX_RDSR	0x05	/* Read Status Register */
-#define CMD_S25FLXX_WRSR	0x01	/* Write Status Register */
-#define CMD_S25FLXX_PP		0x02	/* Page Program */
 #define CMD_S25FLXX_SE		0xd8	/* Sector Erase */
 #define CMD_S25FLXX_BE		0xc7	/* Bulk Erase */
-#define CMD_S25FLXX_DP		0xb9	/* Deep Power-down */
-#define CMD_S25FLXX_RES		0xab	/* Release from DP, and Read Signature */
-
-#define SPSN_ID_S25FL008A	0x0213
-#define SPSN_ID_S25FL016A	0x0214
-#define SPSN_ID_S25FL032A	0x0215
-#define SPSN_ID_S25FL064A	0x0216
-#define SPSN_ID_S25FL128P	0x2018
-#define SPSN_EXT_ID_S25FL128P_256KB	0x0300
-#define SPSN_EXT_ID_S25FL128P_64KB	0x0301
-#define SPSN_EXT_ID_S25FL032P		0x4d00
-#define SPSN_EXT_ID_S25FL129P		0x4d01
 
 struct spansion_spi_flash_params {
 	u16 idcode1;
@@ -66,7 +46,7 @@ struct spansion_spi_flash_params {
 
 static const struct spansion_spi_flash_params spansion_spi_flash_table[] = {
 	{
-		.idcode1 = SPSN_ID_S25FL008A,
+		.idcode1 = 0x0213,
 		.idcode2 = 0,
 		.page_size = 256,
 		.pages_per_sector = 256,
@@ -74,7 +54,7 @@ static const struct spansion_spi_flash_params spansion_spi_flash_table[] = {
 		.name = "S25FL008A",
 	},
 	{
-		.idcode1 = SPSN_ID_S25FL016A,
+		.idcode1 = 0x0214,
 		.idcode2 = 0,
 		.page_size = 256,
 		.pages_per_sector = 256,
@@ -82,7 +62,7 @@ static const struct spansion_spi_flash_params spansion_spi_flash_table[] = {
 		.name = "S25FL016A",
 	},
 	{
-		.idcode1 = SPSN_ID_S25FL032A,
+		.idcode1 = 0x0215,
 		.idcode2 = 0,
 		.page_size = 256,
 		.pages_per_sector = 256,
@@ -90,7 +70,7 @@ static const struct spansion_spi_flash_params spansion_spi_flash_table[] = {
 		.name = "S25FL032A",
 	},
 	{
-		.idcode1 = SPSN_ID_S25FL064A,
+		.idcode1 = 0x0216,
 		.idcode2 = 0,
 		.page_size = 256,
 		.pages_per_sector = 256,
@@ -98,32 +78,32 @@ static const struct spansion_spi_flash_params spansion_spi_flash_table[] = {
 		.name = "S25FL064A",
 	},
 	{
-		.idcode1 = SPSN_ID_S25FL128P,
-		.idcode2 = SPSN_EXT_ID_S25FL128P_64KB,
+		.idcode1 = 0x2018,
+		.idcode2 = 0x0301,
 		.page_size = 256,
 		.pages_per_sector = 256,
 		.nr_sectors = 256,
 		.name = "S25FL128P_64K",
 	},
 	{
-		.idcode1 = SPSN_ID_S25FL128P,
-		.idcode2 = SPSN_EXT_ID_S25FL128P_256KB,
+		.idcode1 = 0x2018,
+		.idcode2 = 0x0300,
 		.page_size = 256,
 		.pages_per_sector = 1024,
 		.nr_sectors = 64,
 		.name = "S25FL128P_256K",
 	},
 	{
-		.idcode1 = SPSN_ID_S25FL032A,
-		.idcode2 = SPSN_EXT_ID_S25FL032P,
+		.idcode1 = 0x0215,
+		.idcode2 = 0x4d00,
 		.page_size = 256,
 		.pages_per_sector = 256,
 		.nr_sectors = 64,
 		.name = "S25FL032P",
 	},
 	{
-		.idcode1 = SPSN_ID_S25FL128P,
-		.idcode2 = SPSN_EXT_ID_S25FL129P,
+		.idcode1 = 0x2018,
+		.idcode2 = 0x4d01,
 		.page_size = 256,
 		.pages_per_sector = 256,
 		.nr_sectors = 256,

drivers/mtd/spi/spi_flash_internal.h

@@ -17,8 +17,8 @@
 
 #define CMD_READ_ARRAY_SLOW		0x03
 #define CMD_READ_ARRAY_FAST		0x0b
-#define CMD_READ_ARRAY_LEGACY		0xe8
 
+#define CMD_WRITE_STATUS		0x01
 #define CMD_PAGE_PROGRAM		0x02
 #define CMD_WRITE_DISABLE		0x04
 #define CMD_READ_STATUS			0x05

drivers/mtd/spi/sst.c

@@ -18,12 +18,6 @@
 
 #include "spi_flash_internal.h"
 
-#define CMD_SST_WREN		0x06	/* Write Enable */
-#define CMD_SST_WRDI		0x04	/* Write Disable */
-#define CMD_SST_RDSR		0x05	/* Read Status Register */
-#define CMD_SST_WRSR		0x01	/* Write Status Register */
-#define CMD_SST_READ		0x03	/* Read Data Bytes */
-#define CMD_SST_FAST_READ	0x0b	/* Read Data Bytes at Higher Speed */
 #define CMD_SST_BP		0x02	/* Byte Program */
 #define CMD_SST_AAI_WP		0xAD	/* Auto Address Increment Word Program */
 #define CMD_SST_SE		0x20	/* Sector Erase */
@@ -137,7 +131,7 @@ sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf)
 	};
 
 	debug("BP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
-		spi_w8r8(flash->spi, CMD_SST_RDSR), buf, cmd[0], offset);
+		spi_w8r8(flash->spi, CMD_READ_STATUS), buf, cmd[0], offset);
 
 	ret = sst_enable_writing(flash);
 	if (ret)
@@ -184,7 +178,7 @@ sst_write_wp(struct spi_flash *flash, u32 offset, size_t len, const void *buf)
 
 	for (; actual < len - 1; actual += 2) {
 		debug("WP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
-		     spi_w8r8(flash->spi, CMD_SST_RDSR), buf + actual, cmd[0],
+		     spi_w8r8(flash->spi, CMD_READ_STATUS), buf + actual, cmd[0],
 		     offset);
 
 		ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len,
@@ -232,13 +226,13 @@ sst_unlock(struct spi_flash *flash)
 	if (ret)
 		return ret;
 
-	cmd = CMD_SST_WRSR;
+	cmd = CMD_WRITE_STATUS;
 	status = 0;
 	ret = spi_flash_cmd_write(flash->spi, &cmd, 1, &status, 1);
 	if (ret)
 		debug("SF: Unable to set status byte\n");
 
-	debug("SF: sst: status = %x\n", spi_w8r8(flash->spi, CMD_SST_RDSR));
+	debug("SF: sst: status = %x\n", spi_w8r8(flash->spi, CMD_READ_STATUS));
 
 	return ret;
 }

drivers/mtd/spi/stmicro.c

@@ -34,16 +34,8 @@
 #include "spi_flash_internal.h"
 
 /* M25Pxx-specific commands */
-#define CMD_M25PXX_WREN		0x06	/* Write Enable */
-#define CMD_M25PXX_WRDI		0x04	/* Write Disable */
-#define CMD_M25PXX_RDSR		0x05	/* Read Status Register */
-#define CMD_M25PXX_WRSR		0x01	/* Write Status Register */
-#define CMD_M25PXX_READ		0x03	/* Read Data Bytes */
-#define CMD_M25PXX_FAST_READ	0x0b	/* Read Data Bytes at Higher Speed */
-#define CMD_M25PXX_PP		0x02	/* Page Program */
 #define CMD_M25PXX_SE		0xd8	/* Sector Erase */
 #define CMD_M25PXX_BE		0xc7	/* Bulk Erase */
-#define CMD_M25PXX_DP		0xb9	/* Deep Power-down */
 #define CMD_M25PXX_RES		0xab	/* Release from DP, and Read Signature */
 
 struct stmicro_spi_flash_params {

drivers/mtd/spi/winbond.c

@@ -11,18 +11,9 @@
 #include "spi_flash_internal.h"
 
 /* M25Pxx-specific commands */
-#define CMD_W25_WREN		0x06	/* Write Enable */
-#define CMD_W25_WRDI		0x04	/* Write Disable */
-#define CMD_W25_RDSR		0x05	/* Read Status Register */
-#define CMD_W25_WRSR		0x01	/* Write Status Register */
-#define CMD_W25_READ		0x03	/* Read Data Bytes */
-#define CMD_W25_FAST_READ	0x0b	/* Read Data Bytes at Higher Speed */
-#define CMD_W25_PP		0x02	/* Page Program */
 #define CMD_W25_SE		0x20	/* Sector (4K) Erase */
 #define CMD_W25_BE		0xd8	/* Block (64K) Erase */
 #define CMD_W25_CE		0xc7	/* Chip Erase */
-#define CMD_W25_DP		0xb9	/* Deep Power-down */
-#define CMD_W25_RES		0xab	/* Release from DP, and Read Signature */
 
 struct winbond_spi_flash_params {
 	uint16_t	id;

drivers/net/bfin_mac.c

@@ -190,8 +190,7 @@ static int bfin_EMAC_recv(struct eth_device *dev)
 
 		debug("%s: len = %d\n", __func__, length - 4);
 
-		NetRxPackets[rxIdx] =
-		    (volatile uchar *)(rxbuf[rxIdx]->FrmData->Dest);
+		NetRxPackets[rxIdx] = rxbuf[rxIdx]->FrmData->Dest;
 		NetReceive(NetRxPackets[rxIdx], length - 4);
 		bfin_write_DMA1_IRQ_STATUS(DMA_DONE | DMA_ERR);
 		rxbuf[rxIdx]->StatusWord = 0x00000000;

drivers/net/sh_eth.h

@@ -452,17 +452,16 @@ enum ECSR_STATUS_BIT {
 
 /* ECSIPR */
 enum ECSIPR_STATUS_MASK_BIT {
-#if defined(CONFIG_CPU_SH7724)
+#if defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7757)
+	ECSIPR_BRCRXIP = 0x20,
 	ECSIPR_PSRTOIP = 0x10,
-	ECSIPR_LCHNGIP = 0x04,
-	ECSIPR_ICDIP = 0x01,
 #elif defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
 	ECSIPR_PSRTOIP = 0x10,
 	ECSIPR_PHYIP = 0x08,
+#endif
 	ECSIPR_LCHNGIP = 0x04,
 	ECSIPR_MPDIP = 0x02,
 	ECSIPR_ICDIP = 0x01,
-#endif
 };
 
 #if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)

drivers/usb/eth/smsc95xx.c

@@ -153,13 +153,15 @@ static int curr_eth_dev; /* index for name of next device detected */
 static int smsc95xx_write_reg(struct ueth_data *dev, u32 index, u32 data)
 {
 	int len;
+	ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1);
 
 	cpu_to_le32s(&data);
+	tmpbuf[0] = data;
 
 	len = usb_control_msg(dev->pusb_dev, usb_sndctrlpipe(dev->pusb_dev, 0),
 		USB_VENDOR_REQUEST_WRITE_REGISTER,
 		USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
-		00, index, &data, sizeof(data), USB_CTRL_SET_TIMEOUT);
+		00, index, tmpbuf, sizeof(data), USB_CTRL_SET_TIMEOUT);
 	if (len != sizeof(data)) {
 		debug("smsc95xx_write_reg failed: index=%d, data=%d, len=%d",
 		      index, data, len);
@@ -171,11 +173,13 @@ static int smsc95xx_write_reg(struct ueth_data *dev, u32 index, u32 data)
 static int smsc95xx_read_reg(struct ueth_data *dev, u32 index, u32 *data)
 {
 	int len;
+	ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1);
 
 	len = usb_control_msg(dev->pusb_dev, usb_rcvctrlpipe(dev->pusb_dev, 0),
 		USB_VENDOR_REQUEST_READ_REGISTER,
 		USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
-		00, index, data, sizeof(data), USB_CTRL_GET_TIMEOUT);
+		00, index, tmpbuf, sizeof(data), USB_CTRL_GET_TIMEOUT);
+	*data = tmpbuf[0];
 	if (len != sizeof(data)) {
 		debug("smsc95xx_read_reg failed: index=%d, len=%d",
 		      index, len);
@@ -664,7 +668,8 @@ static int smsc95xx_send(struct eth_device *eth, void* packet, int length)
 	int actual_len;
 	u32 tx_cmd_a;
 	u32 tx_cmd_b;
-	unsigned char msg[PKTSIZE + sizeof(tx_cmd_a) + sizeof(tx_cmd_b)];
+	ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg,
+				 PKTSIZE + sizeof(tx_cmd_a) + sizeof(tx_cmd_b));
 
 	debug("** %s(), len %d, buf %#x\n", __func__, length, (int)msg);
 	if (length > PKTSIZE)
@@ -695,7 +700,7 @@ static int smsc95xx_send(struct eth_device *eth, void* packet, int length)
 static int smsc95xx_recv(struct eth_device *eth)
 {
 	struct ueth_data *dev = (struct ueth_data *)eth->priv;
-	static unsigned char  recv_buf[AX_RX_URB_SIZE];
+	DEFINE_CACHE_ALIGN_BUFFER(unsigned char, recv_buf, AX_RX_URB_SIZE);
 	unsigned char *buf_ptr;
 	int err;
 	int actual_len;

drivers/usb/host/ehci-hcd.c

@@ -34,7 +34,10 @@ struct ehci_hccr *hccr;	/* R/O registers, not need for volatile */
 volatile struct ehci_hcor *hcor;
 
 static uint16_t portreset;
-static struct QH qh_list __attribute__((aligned(32)));
+DEFINE_ALIGN_BUFFER(struct QH, qh_list, 1, USB_DMA_MINALIGN);
+
+#define ALIGN_END_ADDR(type, ptr, size)			\
+	((uint32_t)(ptr) + roundup((size) * sizeof(type), USB_DMA_MINALIGN))
 
 static struct descriptor {
 	struct usb_hub_descriptor hub;
@@ -172,18 +175,15 @@ static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz)
 {
 	uint32_t delta, next;
 	uint32_t addr = (uint32_t)buf;
-	size_t rsz = roundup(sz, 32);
 	int idx;
 
-	if (sz != rsz)
-		debug("EHCI-HCD: Misaligned buffer size (%08x)\n", sz);
-
-	if (addr & 31)
+	if (addr != ALIGN(addr, ARCH_DMA_MINALIGN))
 		debug("EHCI-HCD: Misaligned buffer address (%p)\n", buf);
 
+	flush_dcache_range(addr, ALIGN(addr + sz, ARCH_DMA_MINALIGN));
+
 	idx = 0;
 	while (idx < 5) {
-		flush_dcache_range(addr, addr + rsz);
 		td->qt_buffer[idx] = cpu_to_hc32(addr);
 		td->qt_buffer_hi[idx] = 0;
 		next = (addr + 4096) & ~4095;
@@ -196,7 +196,7 @@ static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz)
 	}
 
 	if (idx == 5) {
-		debug("out of buffer pointers (%u bytes left)\n", sz);
+		printf("out of buffer pointers (%u bytes left)\n", sz);
 		return -1;
 	}
 
@@ -207,8 +207,8 @@ static int
 ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
 		   int length, struct devrequest *req)
 {
-	static struct QH qh __attribute__((aligned(32)));
-	static struct qTD qtd[3] __attribute__((aligned (32)));
+	ALLOC_ALIGN_BUFFER(struct QH, qh, 1, USB_DMA_MINALIGN);
+	ALLOC_ALIGN_BUFFER(struct qTD, qtd, 3, USB_DMA_MINALIGN);
 	int qtd_counter = 0;
 
 	volatile struct qTD *vtd;
@@ -229,8 +229,8 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
 		      le16_to_cpu(req->value), le16_to_cpu(req->value),
 		      le16_to_cpu(req->index));
 
-	memset(&qh, 0, sizeof(struct QH));
-	memset(qtd, 0, sizeof(qtd));
+	memset(qh, 0, sizeof(struct QH));
+	memset(qtd, 0, 3 * sizeof(*qtd));
 
 	toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
 
@@ -244,7 +244,7 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
 	 *   qh_overlay.qt_next ...... 13-10 H
 	 * - qh_overlay.qt_altnext
 	 */
-	qh.qh_link = cpu_to_hc32((uint32_t)&qh_list | QH_LINK_TYPE_QH);
+	qh->qh_link = cpu_to_hc32((uint32_t)qh_list | QH_LINK_TYPE_QH);
 	c = (usb_pipespeed(pipe) != USB_SPEED_HIGH &&
 	     usb_pipeendpoint(pipe) == 0) ? 1 : 0;
 	endpt = (8 << 28) |
@@ -255,14 +255,14 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
 	    (usb_pipespeed(pipe) << 12) |
 	    (usb_pipeendpoint(pipe) << 8) |
 	    (0 << 7) | (usb_pipedevice(pipe) << 0);
-	qh.qh_endpt1 = cpu_to_hc32(endpt);
+	qh->qh_endpt1 = cpu_to_hc32(endpt);
 	endpt = (1 << 30) |
 	    (dev->portnr << 23) |
 	    (dev->parent->devnum << 16) | (0 << 8) | (0 << 0);
-	qh.qh_endpt2 = cpu_to_hc32(endpt);
-	qh.qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
+	qh->qh_endpt2 = cpu_to_hc32(endpt);
+	qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
 
-	tdp = &qh.qh_overlay.qt_next;
+	tdp = &qh->qh_overlay.qt_next;
 
 	if (req != NULL) {
 		/*
@@ -281,7 +281,7 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
 		    (0 << 15) | (0 << 12) | (3 << 10) | (2 << 8) | (0x80 << 0);
 		qtd[qtd_counter].qt_token = cpu_to_hc32(token);
 		if (ehci_td_buffer(&qtd[qtd_counter], req, sizeof(*req)) != 0) {
-			debug("unable construct SETUP td\n");
+			printf("unable construct SETUP td\n");
 			goto fail;
 		}
 		/* Update previous qTD! */
@@ -310,7 +310,7 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
 		    ((usb_pipein(pipe) ? 1 : 0) << 8) | (0x80 << 0);
 		qtd[qtd_counter].qt_token = cpu_to_hc32(token);
 		if (ehci_td_buffer(&qtd[qtd_counter], buffer, length) != 0) {
-			debug("unable construct DATA td\n");
+			printf("unable construct DATA td\n");
 			goto fail;
 		}
 		/* Update previous qTD! */
@@ -340,13 +340,16 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
 		tdp = &qtd[qtd_counter++].qt_next;
 	}
 
-	qh_list.qh_link = cpu_to_hc32((uint32_t)&qh | QH_LINK_TYPE_QH);
+	qh_list->qh_link = cpu_to_hc32((uint32_t)qh | QH_LINK_TYPE_QH);
 
 	/* Flush dcache */
-	flush_dcache_range((uint32_t)&qh_list,
-		(uint32_t)&qh_list + sizeof(struct QH));
-	flush_dcache_range((uint32_t)&qh, (uint32_t)&qh + sizeof(struct QH));
-	flush_dcache_range((uint32_t)qtd, (uint32_t)qtd + sizeof(qtd));
+	flush_dcache_range((uint32_t)qh_list,
+		ALIGN_END_ADDR(struct QH, qh_list, 1));
+	flush_dcache_range((uint32_t)qh, ALIGN_END_ADDR(struct QH, qh, 1));
+	flush_dcache_range((uint32_t)qtd, ALIGN_END_ADDR(struct qTD, qtd, 3));
+
+	/* Set async. queue head pointer. */
+	ehci_writel(&hcor->or_asynclistaddr, (uint32_t)qh_list);
 
 	usbsts = ehci_readl(&hcor->or_usbsts);
 	ehci_writel(&hcor->or_usbsts, (usbsts & 0x3f));
@@ -369,12 +372,12 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
 	timeout = USB_TIMEOUT_MS(pipe);
 	do {
 		/* Invalidate dcache */
-		invalidate_dcache_range((uint32_t)&qh_list,
-			(uint32_t)&qh_list + sizeof(struct QH));
-		invalidate_dcache_range((uint32_t)&qh,
-			(uint32_t)&qh + sizeof(struct QH));
+		invalidate_dcache_range((uint32_t)qh_list,
+			ALIGN_END_ADDR(struct QH, qh_list, 1));
+		invalidate_dcache_range((uint32_t)qh,
+			ALIGN_END_ADDR(struct QH, qh, 1));
 		invalidate_dcache_range((uint32_t)qtd,
-			(uint32_t)qtd + sizeof(qtd));
+			ALIGN_END_ADDR(struct qTD, qtd, 3));
 
 		token = hc32_to_cpu(vtd->qt_token);
 		if (!(token & 0x80))
@@ -382,9 +385,17 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
 		WATCHDOG_RESET();
 	} while (get_timer(ts) < timeout);
 
-	/* Invalidate the memory area occupied by buffer */
-	invalidate_dcache_range(((uint32_t)buffer & ~31),
-		((uint32_t)buffer & ~31) + roundup(length, 32));
+	/*
+	 * Invalidate the memory area occupied by buffer
+	 * Don't try to fix the buffer alignment, if it isn't properly
+	 * aligned it's upper layer's fault so let invalidate_dcache_range()
+	 * vow about it. But we have to fix the length as it's actual
+	 * transfer length and can be unaligned. This is potentially
+	 * dangerous operation, it's responsibility of the calling
+	 * code to make sure enough space is reserved.
+	 */
+	invalidate_dcache_range((uint32_t)buffer,
+		ALIGN((uint32_t)buffer + length, ARCH_DMA_MINALIGN));
 
 	/* Check that the TD processing happened */
 	if (token & 0x80) {
@@ -403,9 +414,7 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
 		goto fail;
 	}
 
-	qh_list.qh_link = cpu_to_hc32((uint32_t)&qh_list | QH_LINK_TYPE_QH);
-
-	token = hc32_to_cpu(qh.qh_overlay.qt_token);
+	token = hc32_to_cpu(qh->qh_overlay.qt_token);
 	if (!(token & 0x80)) {
 		debug("TOKEN=%#x\n", token);
 		switch (token & 0xfc) {
@@ -733,16 +742,13 @@ int usb_lowlevel_init(void)
 #endif
 
 	/* Set head of reclaim list */
-	memset(&qh_list, 0, sizeof(qh_list));
-	qh_list.qh_link = cpu_to_hc32((uint32_t)&qh_list | QH_LINK_TYPE_QH);
-	qh_list.qh_endpt1 = cpu_to_hc32((1 << 15) | (USB_SPEED_HIGH << 12));
-	qh_list.qh_curtd = cpu_to_hc32(QT_NEXT_TERMINATE);
-	qh_list.qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
-	qh_list.qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
-	qh_list.qh_overlay.qt_token = cpu_to_hc32(0x40);
-
-	/* Set async. queue head pointer. */
-	ehci_writel(&hcor->or_asynclistaddr, (uint32_t)&qh_list);
+	memset(qh_list, 0, sizeof(*qh_list));
+	qh_list->qh_link = cpu_to_hc32((uint32_t)qh_list | QH_LINK_TYPE_QH);
+	qh_list->qh_endpt1 = cpu_to_hc32((1 << 15) | (USB_SPEED_HIGH << 12));
+	qh_list->qh_curtd = cpu_to_hc32(QT_NEXT_TERMINATE);
+	qh_list->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
+	qh_list->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
+	qh_list->qh_overlay.qt_token = cpu_to_hc32(0x40);
 
 	reg = ehci_readl(&hccr->cr_hcsparams);
 	descriptor.hub.bNbrPorts = HCS_N_PORTS(reg);

drivers/usb/host/ehci-omap.c

@@ -246,7 +246,6 @@ int omap_ehci_hcd_init(struct omap_usbhs_board_data *usbhs_pdata)
 		if (is_ehci_phy_mode(usbhs_pdata->port_mode[i]))
 			omap_ehci_soft_phy_reset(i);
 
-	dcache_disable();
 	hccr = (struct ehci_hccr *)(OMAP_EHCI_BASE);
 	hcor = (struct ehci_hcor *)(OMAP_EHCI_BASE + 0x10);
 

drivers/usb/musb/musb_core.h

@@ -145,7 +145,7 @@ struct musb_regs {
 		struct musb_epN_regs epN;
 	} ep[16];
 
-} __attribute__((packed, aligned(32)));
+} __attribute__((packed, aligned(USB_DMA_MINALIGN)));
 #endif
 
 /*

drivers/video/Makefile

@@ -42,7 +42,7 @@ COBJS-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o
 COBJS-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o
 COBJS-$(CONFIG_VIDEO_MB86R0xGDC) += mb86r0xgdc.o videomodes.o
 COBJS-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o
-COBJS-$(CONFIG_VIDEO_MX5) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o
+COBJS-$(CONFIG_VIDEO_IPUV3) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o
 COBJS-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o
 COBJS-$(CONFIG_VIDEO_SED13806) += sed13806.o
 COBJS-$(CONFIG_VIDEO_SM501) += sm501.o

drivers/video/cfb_console.c

@@ -164,7 +164,7 @@
 /*
  * Defines for the i.MX31 driver (mx3fb.c)
  */
-#if defined(CONFIG_VIDEO_MX3) || defined(CONFIG_VIDEO_MX5)
+#if defined(CONFIG_VIDEO_MX3) || defined(CONFIG_VIDEO_IPUV3)
 #define VIDEO_FB_16BPP_WORD_SWAP
 #endif
 

drivers/video/ipu_common.c

@@ -163,6 +163,7 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
 
 static int clk_ipu_enable(struct clk *clk)
 {
+#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
 	u32 reg;
 
 	reg = __raw_readl(clk->enable_reg);
@@ -178,12 +179,13 @@ static int clk_ipu_enable(struct clk *clk)
 	reg = __raw_readl(&mxc_ccm->clpcr);
 	reg &= ~MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS;
 	__raw_writel(reg, &mxc_ccm->clpcr);
-
+#endif
 	return 0;
 }
 
 static void clk_ipu_disable(struct clk *clk)
 {
+#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
 	u32 reg;
 
 	reg = __raw_readl(clk->enable_reg);
@@ -202,13 +204,14 @@ static void clk_ipu_disable(struct clk *clk)
 	reg = __raw_readl(&mxc_ccm->clpcr);
 	reg |= MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS;
 	__raw_writel(reg, &mxc_ccm->clpcr);
+#endif
 }
 
 
 static struct clk ipu_clk = {
 	.name = "ipu_clk",
-	.rate = 133000000,
-	.enable_reg = (u32 *)(MXC_CCM_BASE +
+	.rate = CONFIG_IPUV3_CLK,
+	.enable_reg = (u32 *)(CCM_BASE_ADDR +
 		offsetof(struct mxc_ccm_reg, CCGR5)),
 	.enable_shift = MXC_CCM_CCGR5_CG5_OFFSET,
 	.enable = clk_ipu_enable,
@@ -216,8 +219,15 @@ static struct clk ipu_clk = {
 	.usecount = 0,
 };
 
+static struct clk ldb_clk = {
+	.name = "ldb_clk",
+	.rate = 65000000,
+	.usecount = 0,
+};
+
 /* Globals */
 struct clk *g_ipu_clk;
+struct clk *g_ldb_clk;
 unsigned char g_ipu_clk_enabled;
 struct clk *g_di_clk[2];
 struct clk *g_pixel_clk[2];
@@ -340,7 +350,7 @@ static int ipu_pixel_clk_set_parent(struct clk *clk, struct clk *parent)
 
 	if (parent == g_ipu_clk)
 		di_gen &= ~DI_GEN_DI_CLK_EXT;
-	else if (!IS_ERR(g_di_clk[clk->id]) && parent == g_di_clk[clk->id])
+	else if (!IS_ERR(g_di_clk[clk->id]) && parent == g_ldb_clk)
 		di_gen |= DI_GEN_DI_CLK_EXT;
 	else
 		return -EINVAL;
@@ -401,6 +411,7 @@ void ipu_reset(void)
 int ipu_probe(void)
 {
 	unsigned long ipu_base;
+#if defined CONFIG_MX51
 	u32 temp;
 
 	u32 *reg_hsc_mcd = (u32 *)MIPI_HSC_BASE_ADDR;
@@ -414,6 +425,7 @@ int ipu_probe(void)
 
 	temp = __raw_readl(reg_hsc_mxt_conf);
 	__raw_writel(temp | 0x10000, reg_hsc_mxt_conf);
+#endif
 
 	ipu_base = IPU_CTRL_BASE_ADDR;
 	ipu_cpmem_base = (u32 *)(ipu_base + IPU_CPMEM_REG_BASE);
@@ -424,7 +436,8 @@ int ipu_probe(void)
 
 	g_ipu_clk = &ipu_clk;
 	debug("ipu_clk = %u\n", clk_get_rate(g_ipu_clk));
-
+	g_ldb_clk = &ldb_clk;
+	debug("ldb_clk = %u\n", clk_get_rate(g_ldb_clk));
 	ipu_reset();
 
 	clk_set_parent(g_pixel_clk[0], g_ipu_clk);

drivers/video/ipu_disp.c

@@ -64,6 +64,7 @@ static int dmfc_size_28, dmfc_size_29, dmfc_size_24, dmfc_size_27, dmfc_size_23;
 int g_di1_tvout;
 
 extern struct clk *g_ipu_clk;
+extern struct clk *g_ldb_clk;
 extern struct clk *g_di_clk[2];
 extern struct clk *g_pixel_clk[2];
 
@@ -941,7 +942,7 @@ int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk,
 				udelay(10000);
 			}
 		}
-		clk_set_parent(g_pixel_clk[disp], g_di_clk[disp]);
+		clk_set_parent(g_pixel_clk[disp], g_ldb_clk);
 	} else {
 		if (clk_get_usecount(g_pixel_clk[disp]) != 0)
 			clk_set_parent(g_pixel_clk[disp], g_ipu_clk);

drivers/video/ipu_regs.h

@@ -47,14 +47,24 @@
 #define IPU_SMFC_REG_BASE	0x00050000
 #define IPU_DC_REG_BASE		0x00058000
 #define IPU_DMFC_REG_BASE	0x00060000
+#define IPU_VDI_REG_BASE	0x00680000
+#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
 #define IPU_CPMEM_REG_BASE	0x01000000
 #define IPU_LUT_REG_BASE	0x01020000
 #define IPU_SRM_REG_BASE	0x01040000
 #define IPU_TPM_REG_BASE	0x01060000
 #define IPU_DC_TMPL_REG_BASE	0x01080000
 #define IPU_ISP_TBPR_REG_BASE	0x010C0000
-#define IPU_VDI_REG_BASE	0x00680000
+#elif defined(CONFIG_MX6Q)
+#define IPU_CPMEM_REG_BASE	0x00100000
+#define IPU_LUT_REG_BASE	0x00120000
+#define IPU_SRM_REG_BASE	0x00140000
+#define IPU_TPM_REG_BASE	0x00160000
+#define IPU_DC_TMPL_REG_BASE	0x00180000
+#define IPU_ISP_TBPR_REG_BASE	0x001C0000
+#endif
 
+#define IPU_CTRL_BASE_ADDR	(IPU_SOC_BASE_ADDR + IPU_SOC_OFFSET)
 
 extern u32 *ipu_dc_tmpl_reg;
 

include/common.h

@@ -944,11 +944,25 @@ int cpu_release(int nr, int argc, char * const argv[]);
  * of a function scoped static buffer.  It can not be used to create a cache
  * line aligned global buffer.
  */
-#define ALLOC_CACHE_ALIGN_BUFFER(type, name, size)			\
-	char __##name[ROUND(size * sizeof(type), ARCH_DMA_MINALIGN) +	\
-		      ARCH_DMA_MINALIGN - 1];				\
+#define ALLOC_ALIGN_BUFFER(type, name, size, align)			\
+	char __##name[ROUND(size * sizeof(type), align) + (align - 1)];	\
 									\
-	type *name = (type *) ALIGN((uintptr_t)__##name, ARCH_DMA_MINALIGN)
+	type *name = (type *) ALIGN((uintptr_t)__##name, align)
+#define ALLOC_CACHE_ALIGN_BUFFER(type, name, size)			\
+	ALLOC_ALIGN_BUFFER(type, name, size, ARCH_DMA_MINALIGN)
+
+/*
+ * DEFINE_CACHE_ALIGN_BUFFER() is similar to ALLOC_CACHE_ALIGN_BUFFER, but it's
+ * purpose is to allow allocating aligned buffers outside of function scope.
+ * Usage of this macro shall be avoided or used with extreme care!
+ */
+#define DEFINE_ALIGN_BUFFER(type, name, size, align)			\
+	static char __##name[roundup(size * sizeof(type), align)]	\
+			__attribute__((aligned(align)));				\
+									\
+	static type *name = (type *)__##name
+#define DEFINE_CACHE_ALIGN_BUFFER(type, name, size)			\
+	DEFINE_ALIGN_BUFFER(type, name, size, ARCH_DMA_MINALIGN)
 
 /* Pull in stuff for the build system */
 #ifdef DO_DEPS_ONLY

include/configs/bf527-ezkit.h

@@ -156,6 +156,15 @@
 #ifdef CONFIG_BF527_EZKIT_REV_2_1
 # define CONFIG_LQ035Q1_SPI_BUS	0
 # define CONFIG_LQ035Q1_SPI_CS	7
+# define CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI
+#else
+# define CONFIG_LQ035Q1_USE_RGB888_8_BIT_PPI
+#endif
+
+#ifdef CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI
+# define EASYLOGO_HEADER <asm/bfin_logo_rgb565_230x230_lzma.h>
+#else
+# define EASYLOGO_HEADER <asm/bfin_logo_230x230_lzma.h>
 #endif
 
 

include/configs/bf548-ezkit.h

@@ -188,6 +188,7 @@
 /* Don't waste time transferring a logo over the UART */
 # if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART)
 #  define CONFIG_VIDEO
+#  define EASYLOGO_HEADER <asm/bfin_logo_230x230_gzip.h>
 # endif
 # define CONFIG_DEB_DMA_URGENT
 #endif

include/configs/cm-bf548.h

@@ -122,6 +122,7 @@
 /* Don't waste time transferring a logo over the UART */
 # if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART)
 #  define CONFIG_VIDEO
+#  define EASYLOGO_HEADER <asm/bfin_logo_230x230_gzip.h>
 # endif
 # define CONFIG_DEB_DMA_URGENT
 #endif

include/configs/flea3.h

@@ -66,7 +66,7 @@
  */
 #define CONFIG_HARD_I2C
 #define CONFIG_I2C_MXC
-#define CONFIG_SYS_I2C_MX35_PORT3
+#define CONFIG_SYS_I2C_BASE		I2C3_BASE_ADDR
 #define CONFIG_SYS_I2C_SPEED		100000
 #define CONFIG_SYS_I2C_SLAVE		0xfe
 #define CONFIG_MXC_SPI

include/configs/imx31_phycore.h

@@ -54,7 +54,8 @@
 
 #define CONFIG_HARD_I2C
 #define CONFIG_I2C_MXC
-#define CONFIG_SYS_I2C_MX31_PORT2
+#define CONFIG_SYS_I2C_BASE		I2C2_BASE_ADDR
+#define CONFIG_SYS_I2C_CLK_OFFSET	I2C2_CLK_OFFSET
 #define CONFIG_SYS_I2C_SPEED		100000
 
 #define CONFIG_MXC_UART

include/configs/mx28evk.h

@@ -68,6 +68,7 @@
 #define CONFIG_CMD_SPI
 #define CONFIG_CMD_USB
 #define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_I2C
 
 /*
  * Memory configurations
@@ -188,6 +189,13 @@
 #define	CONFIG_USB_STORAGE
 #endif
 
+/* I2C */
+#ifdef CONFIG_CMD_I2C
+#define CONFIG_I2C_MXS
+#define CONFIG_HARD_I2C
+#define CONFIG_SYS_I2C_SPEED	400000
+#endif
+
 /*
  * SPI
  */

include/configs/mx35pdk.h

@@ -57,7 +57,7 @@
  */
 #define CONFIG_HARD_I2C
 #define CONFIG_I2C_MXC
-#define CONFIG_SYS_I2C_MX35_PORT1
+#define CONFIG_SYS_I2C_BASE		I2C1_BASE_ADDR
 #define CONFIG_SYS_I2C_SPEED		100000
 #define CONFIG_MXC_SPI
 #define CONFIG_MXC_GPIO

include/configs/mx51evk.h

@@ -126,13 +126,14 @@
 /* Framebuffer and LCD */
 #define CONFIG_PREBOOT
 #define CONFIG_VIDEO
-#define CONFIG_VIDEO_MX5
+#define CONFIG_VIDEO_IPUV3
 #define CONFIG_CFB_CONSOLE
 #define CONFIG_VGA_AS_SINGLE_DEVICE
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_BMP_16BPP
 #define CONFIG_VIDEO_LOGO
+#define CONFIG_IPUV3_CLK	133000000
 
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE

include/configs/mx53ard.h

@@ -50,7 +50,7 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_HARD_I2C
 #define CONFIG_I2C_MXC
-#define CONFIG_SYS_I2C_MX53_PORT2
+#define CONFIG_SYS_I2C_BASE		I2C2_BASE_ADDR
 #define CONFIG_SYS_I2C_SPEED            100000
 
 /* MMC Configs */

include/configs/mx53evk.h

@@ -53,7 +53,7 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_HARD_I2C
 #define CONFIG_I2C_MXC
-#define CONFIG_SYS_I2C_MX53_PORT2       1
+#define CONFIG_SYS_I2C_BASE		I2C2_BASE_ADDR
 #define CONFIG_SYS_I2C_SPEED            100000
 
 /* PMIC Configs */

include/configs/mx53loco.h

@@ -89,7 +89,7 @@
 /* I2C Configs */
 #define CONFIG_HARD_I2C
 #define CONFIG_I2C_MXC
-#define CONFIG_SYS_I2C_MX53_PORT1
+#define CONFIG_SYS_I2C_BASE		I2C1_BASE_ADDR
 #define CONFIG_SYS_I2C_SPEED		100000
 
 /* PMIC Controller */
@@ -219,12 +219,13 @@
 /* Framebuffer and LCD */
 #define CONFIG_PREBOOT
 #define CONFIG_VIDEO
-#define CONFIG_VIDEO_MX5
+#define CONFIG_VIDEO_IPUV3
 #define CONFIG_CFB_CONSOLE
 #define CONFIG_VGA_AS_SINGLE_DEVICE
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_BMP_16BPP
 #define CONFIG_VIDEO_LOGO
+#define CONFIG_IPUV3_CLK	133000000
 
 #endif				/* __CONFIG_H */

include/configs/mx53smd.h

@@ -50,7 +50,7 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_HARD_I2C
 #define CONFIG_I2C_MXC
-#define CONFIG_SYS_I2C_MX53_PORT2
+#define CONFIG_SYS_I2C_BASE		I2C2_BASE_ADDR
 #define CONFIG_SYS_I2C_SPEED            100000
 
 /* MMC Configs */

include/configs/mx6qsabrelite.h

@@ -58,6 +58,14 @@
 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
 #endif
 
+/* I2C Configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_HARD_I2C
+#define CONFIG_I2C_MXC
+#define CONFIG_SYS_I2C_BASE		I2C3_BASE_ADDR
+#define CONFIG_SYS_I2C_SPEED            100000
+#define CONFIG_SYS_I2C_SLAVE            0xfe
+
 /* MMC Configs */
 #define CONFIG_FSL_ESDHC
 #define CONFIG_FSL_USDHC

include/configs/nios2-generic.h

@@ -117,10 +117,9 @@
 
 /*
  * MEMORY ORGANIZATION
- *	-Monitor at top of sdram.
- *	-The heap is placed below the monitor
- *	-Global data is placed below the heap.
- *	-The stack is placed below global data (&grows down).
+ * -Monitor at top of sdram.
+ * -The heap is placed below the monitor
+ * -The stack is placed below the heap (&grows down).
  */
 #define CONFIG_MONITOR_IS_IN_RAM
 #define CONFIG_SYS_MONITOR_LEN		0x40000	/* Reserve 256k */
@@ -130,10 +129,7 @@
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 0x20000)
 #define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MONITOR_BASE - \
 					 CONFIG_SYS_MALLOC_LEN)
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_MALLOC_BASE - \
-					 GENERATED_GBL_DATA_SIZE - \
-					 GENERATED_BD_INFO_SIZE)
-#define CONFIG_SYS_INIT_SP		CONFIG_SYS_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_SP		CONFIG_SYS_MALLOC_BASE
 
 /*
  * MISC

include/configs/vision2.h

@@ -212,12 +212,13 @@
  */
 #define CONFIG_PREBOOT
 #define CONFIG_VIDEO
-#define CONFIG_VIDEO_MX5
+#define CONFIG_VIDEO_IPUV3
 #define CONFIG_CFB_CONSOLE
 #define CONFIG_VGA_AS_SINGLE_DEVICE
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_CMD_BMP
 #define CONFIG_BMP_16BPP
+#define CONFIG_IPUV3_CLK	133000000
 
 #endif				/* __CONFIG_H */

include/usb.h

@@ -29,6 +29,16 @@
 #include <usb_defs.h>
 #include <usbdescriptors.h>
 
+/*
+ * The EHCI spec says that we must align to at least 32 bytes.  However,
+ * some platforms require larger alignment.
+ */
+#if ARCH_DMA_MINALIGN > 32
+#define USB_DMA_MINALIGN	ARCH_DMA_MINALIGN
+#else
+#define USB_DMA_MINALIGN	32
+#endif
+
 /* Everything is aribtrary */
 #define USB_ALTSETTINGALLOC		4
 #define USB_MAXALTSETTING		128	/* Hard limit */

net/arp.c

@@ -194,7 +194,7 @@ void ArpReceive(struct ethernet_hdr *et, struct ip_udp_hdr *ip, int len)
 #ifdef CONFIG_KEEP_SERVERADDR
 		if (NetServerIP == NetArpWaitPacketIP) {
 			char buf[20];
-			sprintf(buf, "%pM", arp->ar_sha);
+			sprintf(buf, "%pM", &arp->ar_sha);
 			setenv("serveraddr", buf);
 		}
 #endif

net/bootp.c

@@ -330,7 +330,7 @@ BootpTimeout(void)
 	if (BootpTry >= TIMEOUT_COUNT) {
 #ifdef CONFIG_BOOTP_MAY_FAIL
 		puts("\nRetry count exceeded\n");
-		NetSetState(NETLOOP_FAIL);
+		net_set_state(NETLOOP_FAIL);
 #else
 		puts("\nRetry count exceeded; starting again\n");
 		NetStartAgain();

net/link_local.c

@@ -225,8 +225,8 @@ void link_local_receive_arp(struct arp_hdr *arp, int len)
 			timeout_ms = diff | 1; /* never 0 */
 		}
 	}
-/*
- * XXX Don't bother with ethernet link just yet
+#if 0
+ /* XXX Don't bother with ethernet link just yet */
 	if ((fds[0].revents & POLLIN) == 0) {
 		if (fds[0].revents & POLLERR) {
 			/*
@@ -240,7 +240,7 @@ void link_local_receive_arp(struct arp_hdr *arp, int len)
 		}
 		continue;
 	}
-*/
+#endif
 
 	debug_cond(DEBUG_INT_STATE, "%s recv arp type=%d, op=%d,\n",
 		eth_get_name(), ntohs(arp->ar_pro),

tools/mingw_support.h

@@ -34,6 +34,14 @@
 #define MAP_SHARED	0x01		/* Share changes */
 #define MAP_PRIVATE	0x02		/* Changes are private */
 
+/* File perms */
+#ifndef S_IRGRP
+# define S_IRGRP 0
+#endif
+#ifndef S_IWGRP
+# define S_IWGRP 0
+#endif
+
 /* Windows 64-bit access macros */
 #define LODWORD(x) ((DWORD)((DWORDLONG)(x)))
 #define HIDWORD(x) ((DWORD)(((DWORDLONG)(x) >> 32) & 0xffffffff))

tools/mkenvimage.c

@@ -46,13 +46,6 @@
 
 #define CRC_SIZE sizeof(uint32_t)
 
-#ifdef __MINGW32__
-#define FILE_PERM		(S_IRUSR | S_IWUSR)
-#else
-#define FILE_PERM		(S_IRUSR | S_IWUSR | S_IRGRP |\
-					     S_IWGRP)
-#endif
-
 static void usage(const char *exec_name)
 {
 	fprintf(stderr, "%s [-h] [-r] [-b] [-p <byte>] -s <environment partition size> -o <output> <input file>\n"
@@ -300,7 +293,8 @@ int main(int argc, char **argv)
 	if (!bin_filename || strcmp(bin_filename, "-") == 0) {
 		bin_fd = STDOUT_FILENO;
 	} else {
-		bin_fd = creat(bin_filename, FILE_PERM);
+		bin_fd = creat(bin_filename, S_IRUSR | S_IWUSR | S_IRGRP |
+					     S_IWGRP);
 		if (bin_fd == -1) {
 			fprintf(stderr, "Can't open output file \"%s\": %s\n",
 					bin_filename, strerror(errno));