Prepare v2012.10

Signed-off-by: Tom Rini <trini@ti.com>

MAINTAINERS

@@ -78,10 +78,6 @@ Holger Brunck <holger.brunck@keymile.com>
 	tuge1		MPC8321
 	tuxx1		MPC8321
 
-Cyril Chemparathy <cyril@ti.com>
-
-	tnetv107x_evm	tnetv107x
-
 Conn Clark <clark@esteem.com>
 
 	ESTEEM192E	MPC8xx
@@ -255,6 +251,10 @@ Klaus Heydeck <heydeck@kieback-peter.de>
 	KUP4K		MPC855
 	KUP4X		MPC859
 
+Gabriel Huau <contact@huau-gabriel.fr>
+
+	mini2440	s3c2440
+
 Gary Jennejohn <garyj@denx.de>
 
 	quad100hd	PPC405EP
@@ -363,6 +363,10 @@ Frank Panno <fpanno@delphintech.com>
 
 	ep8260		MPC8260
 
+Chan-Taek Park <c-park@ti.com>
+
+	tnetv107x_evm	tnetv107x
+
 Denis Peter <d.peter@mpl.ch>
 
 	MIP405		PPC4xx
@@ -397,8 +401,6 @@ Stefan Roese <sr@denx.de>
 
 	uc100		MPC857
 
-	TQM85xx		MPC8540/8541/8555/8560
-
 	acadia		PPC405EZ
 	alpr		PPC440GX
 	bamboo		PPC440EP
@@ -727,7 +729,7 @@ Chander Kashyap <k.chander@samsung.com>
 	SMDKV310		ARM ARMV7 (EXYNOS4210 SoC)
 	SMDK5250		ARM ARMV7 (EXYNOS5250 SoC)
 
-Heungjun Kim <riverful.kim@samsung.com>
+Lukasz Majewski <l.majewski@samsung.com>
 
 	trats			ARM ARMV7 (EXYNOS4210 SoC)
 
@@ -777,6 +779,11 @@ Nagendra T S  <nagendra@mistralsolutions.com>
 
    am3517_crane    ARM ARMV7 (AM35x SoC)
 
+Dinh Nguyen <dinguyen@altera.com>
+Chin Liang See <clsee@altera.com>
+
+	socfpga		socfpga_cyclone5
+
 Sandeep Paulraj <s-paulraj@ti.com>
 
 	davinci_dm355evm	ARM926EJS
@@ -799,6 +806,7 @@ Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
 Luka Perkov <uboot@lukaperkov.net>
 
 	ib62x0		ARM926EJS
+	iconnect	ARM926EJS
 
 Dave Peverley <dpeverley@mpc-data.co.uk>
 
@@ -852,6 +860,8 @@ John Rigby <jcrigby@gmail.com>
 
 Stefan Roese <sr@denx.de>
 
+	x600		ARM926EJS (spear600 Soc)
+
 	pdnb3		xscale/ixp
 	scpu		xscale/ixp
 
@@ -890,6 +900,10 @@ Matt Sealey <matt@genesi-usa.com>
 Bo Shen <voice.shen@atmel.com>
 	at91sam9x5ek		ARM926EJS (AT91SAM9G15,G25,G35,X25,X35 SoC)
 
+Michal Simek <monstr@monstr.eu>
+
+	zynq		ARM ARMV7 (Zynq SoC)
+
 Nick Thompson <nick.thompson@gefanuc.com>
 
 	da830evm	ARM926EJS (DA830/OMAP-L137)
@@ -990,6 +1004,15 @@ Zhong Hongbo <bocui107@gmail.com>
 
 	SMDK6400	ARM1176 (S3C6400 SoC)
 
+Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+Tetsuyuki Kobayashi <koba@kmckk.co.jp>
+
+	kzm9g	SH73A0 (RMOBILE SoC)
+
+Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+
+	armadillo-800eva	R8A7740 (RMOBILE SoC)
+
 -------------------------------------------------------------------------
 
 Unknown / orphaned boards:

MAKEALL

@@ -333,6 +333,12 @@ LIST_ppc="		\
 
 LIST_SA="$(boards_by_cpu sa1100)"
 
+#########################################################################
+## ARM7 Systems
+#########################################################################
+
+LIST_ARM7="$(boards_by_cpu arm720t)"
+
 #########################################################################
 ## ARM9 Systems
 #########################################################################
@@ -340,12 +346,15 @@ LIST_SA="$(boards_by_cpu sa1100)"
 LIST_ARM9="$(boards_by_cpu arm920t)	\
 	$(boards_by_cpu arm926ejs)	\
 	$(boards_by_cpu arm925t)	\
+	$(boards_by_cpu arm946es)	\
 "
 
 #########################################################################
 ## ARM11 Systems
 #########################################################################
-LIST_ARM11="$(boards_by_cpu arm1136)"
+LIST_ARM11="$(boards_by_cpu arm1136)	\
+	$(boards_by_cpu arm1176)	\
+"
 
 #########################################################################
 ## ARMV7 Systems
@@ -371,16 +380,7 @@ LIST_ixp="$(boards_by_cpu ixp)"
 ## ARM groups
 #########################################################################
 
-LIST_arm="			\
-	${LIST_SA}		\
-	${LIST_ARM9}		\
-	${LIST_ARM10}		\
-	${LIST_ARM11}		\
-	${LIST_ARMV7}	\
-	${LIST_at91}		\
-	${LIST_pxa}		\
-	${LIST_ixp}		\
-"
+LIST_arm="$(boards_by_arch arm)"
 
 #########################################################################
 ## MIPS Systems		(default = big endian)
@@ -388,6 +388,9 @@ LIST_arm="			\
 
 LIST_mips4kc="		\
 	incaip		\
+	incaip_100MHz	\
+	incaip_133MHz	\
+	incaip_150MHz	\
 	qemu_mips	\
 	vct_platinum	\
 	vct_platinum_small	\
@@ -461,14 +464,7 @@ LIST_microblaze="$(boards_by_arch microblaze)"
 ## ColdFire Systems
 #########################################################################
 
-LIST_m68k="$(boards_by_arch m68k)
-	EB+MCF-EV123		\
-	EB+MCF-EV123_internal	\
-	M52277EVB		\
-	M5235EVB		\
-	M54451EVB		\
-	M54455EVB		\
-"
+LIST_m68k="$(boards_by_arch m68k)"
 LIST_coldfire=${LIST_m68k}
 
 #########################################################################

Makefile

@@ -24,7 +24,7 @@
 VERSION = 2012
 PATCHLEVEL = 10
 SUBLEVEL =
-EXTRAVERSION = -rc1
+EXTRAVERSION =
 ifneq "$(SUBLEVEL)" ""
 U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
 else
@@ -238,7 +238,7 @@ ifdef SOC
 LIBS-y += $(CPUDIR)/$(SOC)/lib$(SOC).o
 endif
 ifeq ($(CPU),ixp)
-LIBS-y += arch/arm/cpu/ixp/npe/libnpe.o
+LIBS-y += drivers/net/npe/libnpe.o
 endif
 LIBS-$(CONFIG_OF_EMBED) += dts/libdts.o
 LIBS-y += arch/$(ARCH)/lib/lib$(ARCH).o
@@ -438,6 +438,11 @@ $(obj)u-boot.kwb:       $(obj)u-boot.bin
 		$(obj)tools/mkimage -n $(CONFIG_SYS_KWD_CONFIG) -T kwbimage \
 		-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -d $< $@
 
+$(obj)u-boot.pbl:	$(obj)u-boot.bin
+		$(obj)tools/mkimage -n $(CONFIG_PBLRCW_CONFIG) \
+		-R $(CONFIG_PBLPBI_CONFIG) -T pblimage \
+		-d $< $@
+
 $(obj)u-boot.sha1:	$(obj)u-boot.bin
 		$(obj)tools/ubsha1 $(obj)u-boot.bin
 
@@ -452,7 +457,7 @@ $(obj)u-boot.ubl:       $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
 		rm $(obj)u-boot-ubl.bin
 		rm $(obj)spl/u-boot-spl-pad.bin
 
-$(obj)u-boot.ais:       $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
+$(obj)u-boot.ais:       $(obj)spl/u-boot-spl.bin $(obj)u-boot.img
 		$(obj)tools/mkimage -s -n $(if $(CONFIG_AIS_CONFIG_FILE),$(CONFIG_AIS_CONFIG_FILE),"/dev/null") \
 			-T aisimage \
 			-e $(CONFIG_SPL_TEXT_BASE) \
@@ -461,7 +466,7 @@ $(obj)u-boot.ais:       $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
 		$(OBJCOPY) ${OBJCFLAGS} -I binary \
 			--pad-to=$(CONFIG_SPL_MAX_SIZE) -O binary \
 			$(obj)spl/u-boot-spl.ais $(obj)spl/u-boot-spl-pad.ais
-		cat $(obj)spl/u-boot-spl-pad.ais $(obj)u-boot.bin > \
+		cat $(obj)spl/u-boot-spl-pad.ais $(obj)u-boot.img > \
 			$(obj)u-boot.ais
 
 # Specify the target for use in elftosb call
@@ -786,10 +791,6 @@ clean:
 	@rm -f $(obj)lib/asm-offsets.s
 	@rm -f $(obj)include/generated/asm-offsets.h
 	@rm -f $(obj)$(CPUDIR)/$(SOC)/asm-offsets.s
-	@rm -f $(obj)nand_spl/{u-boot.lds,u-boot-nand_spl.lds,u-boot-spl,u-boot-spl.map,System.map}
-	@rm -f $(ONENAND_BIN)
-	@rm -f $(obj)spl/{u-boot-spl,u-boot-spl.bin,u-boot-spl.lds,u-boot-spl.map}
-	@rm -f $(obj)MLO
 	@rm -f $(TIMESTAMP_FILE) $(VERSION_FILE)
 	@find $(OBJTREE) -type f \
 		\( -name 'core' -o -name '*.bak' -o -name '*~' -o -name '*.su' \
@@ -808,12 +809,16 @@ clobber:	tidy
 		$(obj)cscope.* $(obj)*.*~
 	@rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL-y)
 	@rm -f $(obj)u-boot.kwb
+	@rm -f $(obj)u-boot.pbl
 	@rm -f $(obj)u-boot.imx
 	@rm -f $(obj)u-boot.ubl
 	@rm -f $(obj)u-boot.ais
 	@rm -f $(obj)u-boot.dtb
 	@rm -f $(obj)u-boot.sb
 	@rm -f $(obj)u-boot.spr
+	@rm -f $(obj)nand_spl/{u-boot.lds,u-boot-nand_spl.lds,u-boot-spl,u-boot-spl.map,System.map}
+	@rm -f $(obj)spl/{u-boot-spl,u-boot-spl.bin,u-boot-spl.lds,u-boot-spl.map}
+	@rm -f $(obj)MLO
 	@rm -f $(obj)tools/xway-swap-bytes
 	@rm -f $(obj)arch/powerpc/cpu/mpc824x/bedbug_603e.c
 	@rm -f $(obj)arch/powerpc/cpu/mpc83xx/ddr-gen?.c

README

@@ -383,6 +383,31 @@ The following options need to be configured:
 		symbol should be set to the TLB1 entry to be used for this
 		purpose.
 
+		CONFIG_SYS_FSL_ERRATUM_A004510
+
+		Enables a workaround for erratum A004510.  If set,
+		then CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV and
+		CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY must be set.
+
+		CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
+		CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 (optional)
+
+		Defines one or two SoC revisions (low 8 bits of SVR)
+		for which the A004510 workaround should be applied.
+
+		The rest of SVR is either not relevant to the decision
+		of whether the erratum is present (e.g. p2040 versus
+		p2041) or is implied by the build target, which controls
+		whether CONFIG_SYS_FSL_ERRATUM_A004510 is set.
+
+		See Freescale App Note 4493 for more information about
+		this erratum.
+
+		CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
+
+		This is the value to write into CCSR offset 0x18600
+		according to the A004510 workaround.
+
 - Generic CPU options:
 		CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
 
@@ -679,6 +704,8 @@ The following options need to be configured:
 - Boot Delay:	CONFIG_BOOTDELAY - in seconds
 		Delay before automatically booting the default image;
 		set to -1 to disable autoboot.
+		set to -2 to autoboot with no delay and not check for abort
+		(even when CONFIG_ZERO_BOOTDELAY_CHECK is defined).
 
 		See doc/README.autoboot for these options that
 		work with CONFIG_BOOTDELAY. None are required.
@@ -789,6 +816,7 @@ The following options need to be configured:
 		CONFIG_CMD_IMLS		  List all found images
 		CONFIG_CMD_IMMAP	* IMMR dump support
 		CONFIG_CMD_IMPORTENV	* import an environment
+		CONFIG_CMD_INI		* import data from an ini file into the env
 		CONFIG_CMD_IRQ		* irqinfo
 		CONFIG_CMD_ITEST	  Integer/string test of 2 values
 		CONFIG_CMD_JFFS2	* JFFS2 Support
@@ -830,7 +858,8 @@ The following options need to be configured:
 		CONFIG_CMD_SPI		* SPI serial bus support
 		CONFIG_CMD_TFTPSRV	* TFTP transfer in server mode
 		CONFIG_CMD_TFTPPUT	* TFTP put command (upload)
-		CONFIG_CMD_TIME		* run command and report execution time
+		CONFIG_CMD_TIME		* run command and report execution time (ARM specific)
+		CONFIG_CMD_TIMER	* access to the system tick timer
 		CONFIG_CMD_USB		* USB support
 		CONFIG_CMD_CDP		* Cisco Discover Protocol support
 		CONFIG_CMD_MFSL		* Microblaze FSL support
@@ -1458,6 +1487,12 @@ The following options need to be configured:
 		can be displayed via the splashscreen support or the
 		bmp command.
 
+- Do compresssing for memory range:
+		CONFIG_CMD_ZIP
+
+		If this option is set, it would use zlib deflate method
+		to compress the specified memory at its best effort.
+
 - Compression support:
 		CONFIG_BZIP2
 
@@ -2572,6 +2607,15 @@ FIT uImage format:
 		CONFIG_SYS_SPL_MALLOC_SIZE
 		The size of the malloc pool used in SPL.
 
+		CONFIG_SPL_FRAMEWORK
+		Enable the SPL framework under common/.  This framework
+		supports MMC, NAND and YMODEM loading of U-Boot and NAND
+		NAND loading of the Linux Kernel.
+
+		CONFIG_SPL_DISPLAY_PRINT
+		For ARM, enable an optional function to print more information
+		about the running system.
+
 		CONFIG_SPL_LIBCOMMON_SUPPORT
 		Support for common/libcommon.o in SPL binary
 
@@ -2635,6 +2679,9 @@ FIT uImage format:
 		CONFIG_SPL_SPI_SUPPORT
 		Support for drivers/spi/libspi.o in SPL binary
 
+		CONFIG_SPL_RAM_DEVICE
+		Support for running image already present in ram, in SPL binary
+
 		CONFIG_SPL_LIBGENERIC_SUPPORT
 		Support for lib/libgeneric.o in SPL binary
 
@@ -3100,12 +3147,12 @@ to save the current settings.
 	  These two #defines specify the address and size of the
 	  environment area within the remote memory space. The
 	  local device can get the environment from remote memory
-	  space by SRIO or other links.
+	  space by SRIO or PCIE links.
 
 BE CAREFUL! For some special cases, the local device can not use
 "saveenv" command. For example, the local device will get the
-environment stored in a remote NOR flash by SRIO link, but it can
-not erase, write this NOR flash by SRIO interface.
+environment stored in a remote NOR flash by SRIO or PCIE link,
+but it can not erase, write this NOR flash by SRIO or PCIE interface.
 
 - CONFIG_ENV_IS_IN_NAND:
 
@@ -3553,9 +3600,9 @@ within that device.
 - CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 	Specifies that QE/FMAN firmware is located in the remote (master)
 	memory space.	CONFIG_SYS_FMAN_FW_ADDR is a virtual address which
-	can be mapped from slave TLB->slave LAW->slave SRIO outbound window
-	->master inbound window->master LAW->the ucode address in master's
-	NOR flash.
+	can be mapped from slave TLB->slave LAW->slave SRIO or PCIE outbound
+	window->master inbound window->master LAW->the ucode address in
+	master's memory space.
 
 Building the Software:
 ======================
@@ -4645,7 +4692,10 @@ Over time, many people have reported problems when trying to use the
 consider minicom to be broken, and recommend not to use it. Under
 Unix, I recommend to use C-Kermit for general purpose use (and
 especially for kermit binary protocol download ("loadb" command), and
-use "cu" for S-Record download ("loads" command).
+use "cu" for S-Record download ("loads" command).  See
+http://www.denx.de/wiki/view/DULG/SystemSetup#Section_4.3.
+for help with kermit.
+
 
 Nevertheless, if you absolutely want to use it try adding this
 configuration to your "File transfer protocols" section:

arch/arm/config.mk

@@ -87,3 +87,21 @@ endif
 ifndef CONFIG_NAND_SPL
 LDFLAGS_u-boot += -pie
 endif
+
+#
+# FIXME: binutils versions < 2.22 have a bug in the assembler where
+# branches to weak symbols can be incorrectly optimized in thumb mode
+# to a short branch (b.n instruction) that won't reach when the symbol
+# gets preempted
+#
+# http://sourceware.org/bugzilla/show_bug.cgi?id=12532
+#
+ifeq ($(CONFIG_SYS_THUMB_BUILD),y)
+ifeq ($(GAS_BUG_12532),)
+export GAS_BUG_12532:=$(shell if [ $(call binutils-version) -lt 0222 ] ; \
+	then echo y; else echo n; fi)
+endif
+ifeq ($(GAS_BUG_12532),y)
+PLATFORM_RELFLAGS += -fno-optimize-sibling-calls
+endif
+endif

arch/arm/cpu/arm1136/start.S

@@ -190,6 +190,7 @@ stack_setup:
 
 	adr	r0, _start
 	cmp	r0, r6
+	moveq	r9, #0		/* no relocation. relocation offset(r9) = 0 */
 	beq	clear_bss		/* skip relocation */
 	mov	r1, r6			/* r1 <- scratch for copy_loop */
 	ldr	r3, _bss_start_ofs

arch/arm/cpu/arm1176/bcm2835/Makefile

@@ -17,7 +17,7 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(SOC).o
 
 SOBJS	:= lowlevel_init.o
-COBJS	:= reset.o timer.o
+COBJS	:= init.o reset.o timer.o
 
 SRCS	:= $(SOBJS:.o=.c) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))

arch/arm/cpu/arm1176/bcm2835/init.c

@@ -0,0 +1,24 @@
+/*
+ * (C) Copyright 2012 Stephen Warren
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+
+int arch_cpu_init(void)
+{
+	icache_enable();
+
+	return 0;
+}

arch/arm/cpu/arm1176/cpu.c

@@ -65,10 +65,3 @@ static void cache_flush (void)
 	/* mem barrier to sync things */
 	asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (0));
 }
-
-int arch_cpu_init(void)
-{
-	icache_enable();
-
-	return 0;
-}

arch/arm/cpu/arm1176/start.S

@@ -252,6 +252,7 @@ stack_setup:
 
 	adr	r0, _start
 	cmp	r0, r6
+	moveq	r9, #0		/* no relocation. relocation offset(r9) = 0 */
 	beq	clear_bss		/* skip relocation */
 	mov	r1, r6			/* r1 <- scratch for copy_loop */
 	ldr	r3, _bss_start_ofs

arch/arm/cpu/arm920t/start.S

@@ -210,6 +210,7 @@ stack_setup:
 
 	adr	r0, _start
 	cmp	r0, r6
+	moveq	r9, #0		/* no relocation. relocation offset(r9) = 0 */
 	beq	clear_bss		/* skip relocation */
 	mov	r1, r6			/* r1 <- scratch for copy_loop */
 	ldr	r3, _bss_start_ofs

arch/arm/cpu/arm925t/start.S

@@ -204,6 +204,7 @@ stack_setup:
 
 	adr	r0, _start
 	cmp	r0, r6
+	moveq	r9, #0		/* no relocation. relocation offset(r9) = 0 */
 	beq	clear_bss		/* skip relocation */
 	mov	r1, r6			/* r1 <- scratch for copy_loop */
 	ldr	r3, _bss_start_ofs

arch/arm/cpu/arm926ejs/davinci/Makefile

@@ -37,7 +37,7 @@ COBJS-$(CONFIG_SOC_DA850)	+= da850_pinmux.o
 COBJS-$(CONFIG_DRIVER_TI_EMAC)	+= lxt972.o dp83848.o et1011c.o ksz8873.o
 
 ifdef CONFIG_SPL_BUILD
-COBJS-y	+= spl.o
+COBJS-$(CONFIG_SPL_FRAMEWORK)	+= spl.o
 COBJS-$(CONFIG_SOC_DM365)	+= dm365_lowlevel.o
 COBJS-$(CONFIG_SOC_DA8XX)	+= da850_lowlevel.o
 endif

arch/arm/cpu/arm926ejs/davinci/config.mk

@@ -0,0 +1,16 @@
+#
+# Copyright (C) 2012, Texas Instruments, Incorporated - http://www.ti.com/
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed "as is" WITHOUT ANY WARRANTY of any
+# kind, whether express or implied; without even the implied warranty
+# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+ifndef CONFIG_SPL_BUILD
+ALL-$(CONFIG_SPL_FRAMEWORK)	+= $(obj)u-boot.ais
+endif

arch/arm/cpu/arm926ejs/davinci/spl.c

@@ -21,6 +21,8 @@
  * MA 02111-1307 USA
  */
 #include <common.h>
+#include <config.h>
+#include <spl.h>
 #include <asm/u-boot.h>
 #include <asm/utils.h>
 #include <nand.h>
@@ -30,15 +32,9 @@
 #include <spi_flash.h>
 #include <mmc.h>
 
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
-
 DECLARE_GLOBAL_DATA_PTR;
-/* Define global data structure pointer to it*/
-static gd_t gdata __attribute__ ((section(".data")));
-static bd_t bdata __attribute__ ((section(".data")));
-
-#else
 
+#ifndef CONFIG_SPL_LIBCOMMON_SUPPORT
 void puts(const char *str)
 {
 	while (*str)
@@ -52,53 +48,49 @@ void putc(char c)
 
 	NS16550_putc((NS16550_t)(CONFIG_SYS_NS16550_COM1), c);
 }
-
 #endif /* CONFIG_SPL_LIBCOMMON_SUPPORT */
 
-inline void hang(void)
-{
-	puts("### ERROR ### Please RESET the board ###\n");
-	for (;;)
-		;
-}
-
 void board_init_f(ulong dummy)
 {
+	/* First, setup our stack pointer. */
+	asm volatile("mov sp, %0\n" : : "r"(CONFIG_SPL_STACK));
+
+	/* Second, perform our low-level init. */
 #ifdef CONFIG_SOC_DM365
 	dm36x_lowlevel_init(0);
 #endif
 #ifdef CONFIG_SOC_DA8XX
 	arch_cpu_init();
 #endif
-	relocate_code(CONFIG_SPL_STACK, NULL, CONFIG_SPL_TEXT_BASE);
-}
 
-void board_init_r(gd_t *id, ulong dummy)
-{
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
-	mem_malloc_init(CONFIG_SYS_TEXT_BASE - CONFIG_SYS_MALLOC_LEN,
-			CONFIG_SYS_MALLOC_LEN);
+	/* Third, we clear the BSS. */
+	memset(__bss_start, 0, __bss_end__ - __bss_start);
 
+	/* Finally, setup gd and move to the next step. */
 	gd = &gdata;
-	gd->bd = &bdata;
-	gd->flags |= GD_FLG_RELOC;
-	gd->baudrate = CONFIG_BAUDRATE;
-	serial_init();          /* serial communications setup */
-	gd->have_console = 1;
+	board_init_r(NULL, 0);
+}
 
-#endif
+void spl_board_init(void)
+{
+	preloader_console_init();
+}
 
-#ifdef CONFIG_SPL_NAND_LOAD
-	nand_init();
-	puts("Nand boot...\n");
-	nand_boot();
-#endif
-#ifdef CONFIG_SPL_SPI_LOAD
-	puts("SPI boot...\n");
-	spi_boot();
-#endif
-#ifdef CONFIG_SPL_MMC_LOAD
-	puts("MMC boot...\n");
-	spl_mmc_load();
+u32 spl_boot_mode(void)
+{
+	return MMCSD_MODE_RAW;
+}
+
+u32 spl_boot_device(void)
+{
+#ifdef CONFIG_SPL_NAND_SIMPLE
+	return BOOT_DEVICE_NAND;
+#elif defined(CONFIG_SPL_SPI_LOAD)
+	return BOOT_DEVICE_SPI;
+#elif defined(CONFIG_SPL_MMC_LOAD)
+	return BOOT_DEVICE_MMC1;
+#else
+	puts("Unknown boot device\n");
+	hang();
 #endif
 }

arch/arm/cpu/arm926ejs/kirkwood/dram.c

@@ -30,38 +30,84 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define KW_REG_CPUCS_WIN_BAR(x)		(KW_REGISTER(0x1500) + (x * 0x08))
-#define KW_REG_CPUCS_WIN_SZ(x)		(KW_REGISTER(0x1504) + (x * 0x08))
+struct kw_sdram_bank {
+	u32	win_bar;
+	u32	win_sz;
+};
+
+struct kw_sdram_addr_dec {
+	struct kw_sdram_bank	sdram_bank[4];
+};
+
+#define KW_REG_CPUCS_WIN_ENABLE		(1 << 0)
+#define KW_REG_CPUCS_WIN_WR_PROTECT	(1 << 1)
+#define KW_REG_CPUCS_WIN_WIN0_CS(x)	(((x) & 0x3) << 2)
+#define KW_REG_CPUCS_WIN_SIZE(x)	(((x) & 0xff) << 24)
+
 /*
  * kw_sdram_bar - reads SDRAM Base Address Register
  */
 u32 kw_sdram_bar(enum memory_bank bank)
 {
+	struct kw_sdram_addr_dec *base =
+		(struct kw_sdram_addr_dec *)KW_REGISTER(0x1500);
 	u32 result = 0;
-	u32 enable = 0x01 & readl(KW_REG_CPUCS_WIN_SZ(bank));
+	u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz);
 
 	if ((!enable) || (bank > BANK3))
 		return 0;
 
-	result = readl(KW_REG_CPUCS_WIN_BAR(bank));
+	result = readl(&base->sdram_bank[bank].win_bar);
 	return result;
 }
 
+/*
+ * kw_sdram_bs_set - writes SDRAM Bank size
+ */
+static void kw_sdram_bs_set(enum memory_bank bank, u32 size)
+{
+	struct kw_sdram_addr_dec *base =
+		(struct kw_sdram_addr_dec *)KW_REGISTER(0x1500);
+	/* Read current register value */
+	u32 reg = readl(&base->sdram_bank[bank].win_sz);
+
+	/* Clear window size */
+	reg &= ~KW_REG_CPUCS_WIN_SIZE(0xFF);
+
+	/* Set new window size */
+	reg |= KW_REG_CPUCS_WIN_SIZE((size - 1) >> 24);
+
+	writel(reg, &base->sdram_bank[bank].win_sz);
+}
+
 /*
  * kw_sdram_bs - reads SDRAM Bank size
  */
 u32 kw_sdram_bs(enum memory_bank bank)
 {
+	struct kw_sdram_addr_dec *base =
+		(struct kw_sdram_addr_dec *)KW_REGISTER(0x1500);
 	u32 result = 0;
-	u32 enable = 0x01 & readl(KW_REG_CPUCS_WIN_SZ(bank));
+	u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz);
 
 	if ((!enable) || (bank > BANK3))
 		return 0;
-	result = 0xff000000 & readl(KW_REG_CPUCS_WIN_SZ(bank));
+	result = 0xff000000 & readl(&base->sdram_bank[bank].win_sz);
 	result += 0x01000000;
 	return result;
 }
 
+void kw_sdram_size_adjust(enum memory_bank bank)
+{
+	u32 size;
+
+	/* probe currently equipped RAM size */
+	size = get_ram_size((void *)kw_sdram_bar(bank), kw_sdram_bs(bank));
+
+	/* adjust SDRAM window size accordingly */
+	kw_sdram_bs_set(bank, size);
+}
+
 #ifndef CONFIG_SYS_BOARD_DRAM_INIT
 int dram_init(void)
 {

arch/arm/cpu/arm926ejs/start.S

@@ -215,6 +215,7 @@ call_board_init_f:
 
 /*------------------------------------------------------------------------------*/
 
+#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_NAND_SPL)
 /*
  * void relocate_code (addr_sp, gd, addr_moni)
  *
@@ -235,6 +236,7 @@ stack_setup:
 	adr	r0, _start
 	sub	r9, r6, r0		/* r9 <- relocation offset */
 	cmp	r0, r6
+	moveq	r9, #0		/* no relocation. relocation offset(r9) = 0 */
 	beq	clear_bss		/* skip relocation */
 	mov	r1, r6			/* r1 <- scratch for copy loop */
 	ldr	r3, _bss_start_ofs
@@ -344,6 +346,7 @@ _rel_dyn_end_ofs:
 	.word __rel_dyn_end - _start
 _dynsym_start_ofs:
 	.word __dynsym_start - _start
+#endif
 
 /*
  *************************************************************************

arch/arm/cpu/arm946es/start.S

@@ -175,6 +175,7 @@ stack_setup:
 
 	adr	r0, _start
 	cmp	r0, r6
+	moveq	r9, #0		/* no relocation. relocation offset(r9) = 0 */
 	beq	clear_bss		/* skip relocation */
 	mov	r1, r6			/* r1 <- scratch for copy_loop */
 	ldr	r3, _bss_start_ofs

arch/arm/cpu/arm_intcm/start.S

@@ -171,6 +171,7 @@ stack_setup:
 
 	adr	r0, _start
 	cmp	r0, r6
+	moveq	r9, #0		/* no relocation. relocation offset(r9) = 0 */
 	beq	clear_bss		/* skip relocation */
 	mov	r1, r6			/* r1 <- scratch for copy_loop */
 	ldr	r3, _bss_start_ofs

arch/arm/cpu/armv7/am33xx/board.c

@@ -18,6 +18,7 @@
 
 #include <common.h>
 #include <errno.h>
+#include <spl.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/omap.h>
@@ -27,7 +28,6 @@
 #include <asm/arch/mmc_host_def.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/io.h>
-#include <asm/omap_common.h>
 #include <asm/emif.h>
 #include <asm/gpio.h>
 #include <i2c.h>
@@ -166,6 +166,8 @@ void s_init(void)
 	regVal |= UART_SMART_IDLE_EN;
 	writel(regVal, &uart_base->uartsyscfg);
 
+	gd = &gdata;
+
 	preloader_console_init();
 
 	/* Initalize the board header */

arch/arm/cpu/armv7/config.mk

@@ -26,6 +26,8 @@ PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
 # supported by more tool-chains
 PF_CPPFLAGS_ARMV7 := $(call cc-option, -march=armv7-a, -march=armv5)
 PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_ARMV7)
+PF_CPPFLAGS_NO_UNALIGNED := $(call cc-option, -mno-unaligned-access,)
+PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_NO_UNALIGNED)
 
 # =========================================================================
 #

arch/arm/cpu/armv7/highbank/config.mk

@@ -1 +0,0 @@
-PLATFORM_CPPFLAGS += -march=armv7-a

arch/arm/cpu/armv7/omap-common/Makefile

@@ -42,19 +42,6 @@ COBJS	+= boot-common.o
 SOBJS	+= lowlevel_init.o
 endif
 
-ifdef CONFIG_SPL_BUILD
-COBJS	+= spl.o
-ifdef CONFIG_SPL_NAND_SUPPORT
-COBJS	+= spl_nand.o
-endif
-ifdef CONFIG_SPL_MMC_SUPPORT
-COBJS	+= spl_mmc.o
-endif
-ifdef CONFIG_SPL_YMODEM_SUPPORT
-COBJS	+= spl_ymodem.o
-endif
-endif
-
 ifndef CONFIG_SPL_BUILD
 ifneq ($(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
 COBJS	+= mem-common.o

arch/arm/cpu/armv7/omap-common/boot-common.c

@@ -17,8 +17,10 @@
  */
 
 #include <common.h>
+#include <spl.h>
 #include <asm/omap_common.h>
 #include <asm/arch/omap.h>
+#include <asm/arch/mmc_host_def.h>
 
 /*
  * This is used to verify if the configuration header
@@ -37,13 +39,34 @@ struct omap_boot_parameters boot_params __attribute__ ((section(".data")));
  */
 u32 omap_bootmode = MMCSD_MODE_FAT;
 
-u32 omap_boot_device(void)
+u32 spl_boot_device(void)
 {
 	return (u32) (boot_params.omap_bootdevice);
 }
 
-u32 omap_boot_mode(void)
+u32 spl_boot_mode(void)
 {
 	return omap_bootmode;
 }
+
+void spl_board_init(void)
+{
+#ifdef CONFIG_SPL_NAND_SUPPORT
+	gpmc_init();
+#endif
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	switch (spl_boot_device()) {
+	case BOOT_DEVICE_MMC1:
+		omap_mmc_init(0, 0, 0);
+		break;
+	case BOOT_DEVICE_MMC2:
+	case BOOT_DEVICE_MMC2_2:
+		omap_mmc_init(1, 0, 0);
+		break;
+	}
+	return 0;
+}
 #endif

arch/arm/cpu/armv7/omap-common/config.mk

@@ -20,15 +20,6 @@
 # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 # MA 02111-1307 USA
 #
-PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
 
 # Make ARMv5 to allow more compilers to work, even though its v7a.
 PLATFORM_CPPFLAGS += -march=armv5
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,\
-			$(call cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)

arch/arm/cpu/armv7/omap-common/hwinit-common.c

@@ -28,10 +28,10 @@
  * MA 02111-1307 USA
  */
 #include <common.h>
+#include <spl.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/sizes.h>
 #include <asm/emif.h>
-#include <asm/omap_common.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -92,6 +92,11 @@ static void init_boot_params(void)
 {
 	boot_params_ptr = (u32 *) &boot_params;
 }
+
+void spl_display_print(void)
+{
+	omap_rev_string();
+}
 #endif
 
 /*
@@ -119,6 +124,9 @@ void s_init(void)
 	set_mux_conf_regs();
 #ifdef CONFIG_SPL_BUILD
 	setup_clocks_for_console();
+
+	gd = &gdata;
+
 	preloader_console_init();
 	do_io_settings();
 #endif

arch/arm/cpu/armv7/omap-common/lowlevel_init.S

@@ -27,6 +27,7 @@
  */
 
 #include <asm/arch/omap.h>
+#include <asm/arch/spl.h>
 #include <linux/linkage.h>
 
 ENTRY(save_boot_params)
@@ -52,18 +53,18 @@ ENTRY(save_boot_params)
 	ldr	r1, =boot_params
 	str	r0, [r1]
 #ifdef CONFIG_SPL_BUILD
-	/* Store the boot device in omap_boot_device */
+	/* Store the boot device in spl_boot_device */
 	ldrb	r2, [r0, #BOOT_DEVICE_OFFSET]	@ r1 <- value of boot device
 	and	r2, #BOOT_DEVICE_MASK
 	ldr	r3, =boot_params
-	strb	r2, [r3, #BOOT_DEVICE_OFFSET]	@ omap_boot_device <- r1
+	strb	r2, [r3, #BOOT_DEVICE_OFFSET]	@ spl_boot_device <- r1
 
 	/* boot mode is passed only for devices that can raw/fat mode */
-	cmp	r2, #2
+	cmp	r2, #BOOT_DEVICE_XIP
 	blt	2f
-	cmp	r2, #7
+	cmp	r2, #BOOT_DEVICE_MMC2
 	bgt	2f
-	/* Store the boot mode (raw/FAT) in omap_boot_mode */
+	/* Store the boot mode (raw/FAT) in omap_bootmode */
 	ldr	r2, [r0, #DEV_DESC_PTR_OFFSET]	@ get the device descriptor ptr
 	ldr	r2, [r2, #DEV_DATA_PTR_OFFSET]	@ get the pDeviceData ptr
 	ldr	r2, [r2, #BOOT_MODE_OFFSET]	@ get the boot mode

arch/arm/cpu/armv7/omap-common/u-boot-spl.lds

@@ -37,9 +37,9 @@ SECTIONS
 {
 	.text      :
 	{
-	__start = .;
-	  arch/arm/cpu/armv7/start.o	(.text)
-	  *(.text*)
+		__start = .;
+		arch/arm/cpu/armv7/start.o	(.text)
+		*(.text*)
 	} >.sram
 
 	. = ALIGN(4);

arch/arm/cpu/armv7/omap3/board.c

@@ -33,6 +33,7 @@
  * MA 02111-1307 USA
  */
 #include <common.h>
+#include <spl.h>
 #include <asm/io.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mem.h>
@@ -40,9 +41,12 @@
 #include <asm/armv7.h>
 #include <asm/arch/gpio.h>
 #include <asm/omap_common.h>
+#include <asm/arch/mmc_host_def.h>
 #include <i2c.h>
 #include <linux/compiler.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* Declarations */
 extern omap3_sysinfo sysinfo;
 static void omap3_setup_aux_cr(void);
@@ -69,30 +73,44 @@ const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;
 u32 omap3_boot_device = BOOT_DEVICE_NAND;
 
 /* auto boot mode detection is not possible for OMAP3 - hard code */
-u32 omap_boot_mode(void)
+u32 spl_boot_mode(void)
 {
-	switch (omap_boot_device()) {
+	switch (spl_boot_device()) {
 	case BOOT_DEVICE_MMC2:
 		return MMCSD_MODE_RAW;
 	case BOOT_DEVICE_MMC1:
 		return MMCSD_MODE_FAT;
 		break;
-	case BOOT_DEVICE_NAND:
-		return NAND_MODE_HW_ECC;
-		break;
 	default:
 		puts("spl: ERROR:  unknown device - can't select boot mode\n");
 		hang();
 	}
 }
 
-u32 omap_boot_device(void)
+u32 spl_boot_device(void)
 {
 	return omap3_boot_device;
 }
 
+int board_mmc_init(bd_t *bis)
+{
+	switch (spl_boot_device()) {
+	case BOOT_DEVICE_MMC1:
+		omap_mmc_init(0, 0, 0);
+		break;
+	case BOOT_DEVICE_MMC2:
+	case BOOT_DEVICE_MMC2_2:
+		omap_mmc_init(1, 0, 0);
+		break;
+	}
+	return 0;
+}
+
 void spl_board_init(void)
 {
+#ifdef CONFIG_SPL_NAND_SUPPORT
+	gpmc_init();
+#endif
 #ifdef CONFIG_SPL_I2C_SUPPORT
 	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 #endif
@@ -236,6 +254,8 @@ void s_init(void)
 #endif
 
 #ifdef CONFIG_SPL_BUILD
+	gd = &gdata;
+
 	preloader_console_init();
 
 	timer_init();

arch/arm/cpu/armv7/omap3/lowlevel_init.S

@@ -214,7 +214,7 @@ pll_div_val5:
 
 ENTRY(lowlevel_init)
 	ldr	sp, SRAM_STACK
-	str	ip, [sp]	/* stash old link register */
+	str	ip, [sp]	/* stash ip register */
 	mov	ip, lr		/* save link reg across call */
 #if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
 /*
@@ -224,12 +224,11 @@ ENTRY(lowlevel_init)
 	ldr	r1, =SRAM_CLK_CODE
 	bl	cpy_clk_code
 #endif /* NAND Boot */
-	bl	s_init		/* go setup pll, mux, memory */
-	ldr	ip, [sp]	/* restore save ip */
 	mov	lr, ip		/* restore link reg */
+	ldr	ip, [sp]	/* restore save ip */
+	/* tail-call s_init to setup pll, mux, memory */
+	b	s_init
 
-	/* back to arch calling code */
-	mov	pc, lr
 ENDPROC(lowlevel_init)
 
 	/* the literal pools origin */

arch/arm/cpu/armv7/rmobile/Makefile

@@ -0,0 +1,65 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).o
+
+SOBJS = lowlevel_init.o
+COBJS-y += cpu_info.o
+COBJS-y += emac.o
+
+COBJS-$(CONFIG_DISPLAY_BOARDINFO) += board.o
+COBJS-$(CONFIG_GLOBAL_TIMER) += timer.o
+COBJS-$(CONFIG_R8A7740) += cpu_info-r8a7740.o
+COBJS-$(CONFIG_R8A7740) += pfc-r8a7740.o
+COBJS-$(CONFIG_SH73A0) += cpu_info-sh73a0.o
+COBJS-$(CONFIG_SH73A0) += pfc-sh73a0.o
+COBJS_LN-$(CONFIG_TMU_TIMER) += sh_timer.o
+
+COBJS	:= $(COBJS-y)
+SRCS    := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS    := $(SOBJS:.o=.S) $(COBJS:.o=.c) $(addprefix $(obj),$(COBJS_LN-y:.o=.c))
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS) $(COBJS_LN-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+START	:= $(addprefix $(obj),$(START))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+# from arch/sh/lib/ directory
+$(obj)sh_timer.c:
+	@rm -f $(obj)sh_timer.c
+	ln -s $(SRCTREE)/arch/sh/lib/time.c $(obj)sh_timer.c
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
+

arch/arm/cpu/armv7/rmobile/board.c

@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * (C) Copyright 2012 Renesas Solutions Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+
+int checkboard(void)
+{
+	printf("Board: %s\n", sysinfo.board_string);
+	return 0;
+}

arch/arm/cpu/armv7/rmobile/config.mk

@@ -0,0 +1,26 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
+
+# Make ARMv5 to allow more compilers to work, even though its v7a.
+PLATFORM_CPPFLAGS += -march=armv5

arch/arm/cpu/armv7/rmobile/cpu_info-r8a7740.c

@@ -0,0 +1,48 @@
+/*
+ * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * (C) Copyright 2012 Renesas Solutions Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/io.h>
+
+u32 rmobile_get_cpu_type(void)
+{
+	u32 id;
+	u32 type;
+	struct r8a7740_hpb *hpb = (struct r8a7740_hpb *)HPB_BASE;
+
+	id = readl(hpb->cccr);
+	type = (id >> 8) & 0xFF;
+
+	return type;
+}
+
+u32 rmobile_get_cpu_rev(void)
+{
+	u32 id;
+	u32 rev;
+	struct r8a7740_hpb *hpb = (struct r8a7740_hpb *)HPB_BASE;
+
+	id = readl(hpb->cccr);
+	rev = (id >> 4) & 0xF;
+
+	return rev;
+}

arch/arm/cpu/armv7/rmobile/cpu_info-sh73a0.c

@@ -0,0 +1,60 @@
+/*
+ * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * (C) Copyright 2012 Renesas Solutions Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/io.h>
+
+u32 rmobile_get_cpu_type(void)
+{
+	u32 id;
+	u32 type;
+	struct sh73a0_hpb *hpb = (struct sh73a0_hpb *)HPB_BASE;
+
+	id = readl(&hpb->cccr);
+	type = (id >> 8) & 0xFF;
+
+	return type;
+}
+
+u32 rmobile_get_cpu_rev_integer(void)
+{
+	u32 id;
+	u32 rev;
+	struct sh73a0_hpb *hpb = (struct sh73a0_hpb *)HPB_BASE;
+
+	id = readl(&hpb->cccr);
+	rev = ((id >> 4) & 0xF) + 1;
+
+	return rev;
+}
+
+u32 rmobile_get_cpu_rev_fraction(void)
+{
+	u32 id;
+	u32 rev;
+	struct sh73a0_hpb *hpb = (struct sh73a0_hpb *)HPB_BASE;
+
+	id = readl(&hpb->cccr);
+	rev = id & 0xF;
+
+	return rev;
+}

arch/arm/cpu/armv7/rmobile/cpu_info.c

@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * (C) Copyright 2012 Renesas Solutions Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_ARCH_CPU_INIT
+int arch_cpu_init(void)
+{
+	icache_enable();
+	return 0;
+}
+#endif
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+	dcache_enable();
+}
+#endif
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+static u32 __rmobile_get_cpu_type(void)
+{
+	return 0x0;
+}
+u32 rmobile_get_cpu_type(void)
+		__attribute__((weak, alias("__rmobile_get_cpu_type")));
+
+static u32 __rmobile_get_cpu_rev_integer(void)
+{
+	return 0;
+}
+u32 rmobile_get_cpu_rev_integer(void)
+		__attribute__((weak, alias("__rmobile_get_cpu_rev_integer")));
+
+static u32 __rmobile_get_cpu_rev_fraction(void)
+{
+	return 0;
+}
+u32 rmobile_get_cpu_rev_fraction(void)
+		__attribute__((weak, alias("__rmobile_get_cpu_rev_fraction")));
+
+int print_cpuinfo(void)
+{
+	switch (rmobile_get_cpu_type()) {
+	case 0x37:
+		printf("CPU: Renesas Electronics SH73A0 rev %d.%d\n",
+		       rmobile_get_cpu_rev_integer(),
+		       rmobile_get_cpu_rev_fraction());
+		break;
+	case 0x40:
+		printf("CPU: Renesas Electronics R8A7740 rev %d.%d\n",
+		       rmobile_get_cpu_rev_integer(),
+		       rmobile_get_cpu_rev_fraction());
+		break;
+
+	default:
+		printf("CPU: Renesas Electronics CPU rev %d.%d\n",
+		       rmobile_get_cpu_rev_integer(),
+		       rmobile_get_cpu_rev_fraction());
+		break;
+	}
+	return 0;
+}
+#endif /* CONFIG_DISPLAY_CPUINFO */

arch/arm/cpu/armv7/rmobile/emac.c

@@ -0,0 +1,36 @@
+/*
+ * RMOBILE EtherMAC initialization.
+ *
+ * Copyright (C) 2012  Renesas Solutions Corp.
+ * Copyright (C) 2012  Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <netdev.h>
+
+int cpu_eth_init(bd_t *bis)
+{
+	int ret = -ENODEV;
+#ifdef CONFIG_SH_ETHER
+	ret = sh_eth_initialize(bis);
+#endif
+	return ret;
+}

arch/arm/cpu/armv7/rmobile/lowlevel_init.S

@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.Iwamatsu.yj@renesas.com>
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+
+ENTRY(lowlevel_init)
+	ldr		r0, =MERAM_BASE
+	mov		r1, #0x0
+	str		r1, [r0]
+
+	mrc		p15, 0, r0, c0, c0, 5
+	ands	r0, r0, #0xF
+	beq		lowlevel_init__
+	b		wait_interrupt
+
+	.pool
+	.align 4
+
+wait_interrupt:
+#ifdef ICCICR
+	ldr     r1, =ICCICR
+	mov     r2, #0x0
+	str     r2, [r1]
+	mov     r2, #0xF0
+	adds    r1, r1, #4 /* ICCPMR */
+	str     r2, [r1]
+	ldr     r1, =ICCICR
+	mov     r2, #0x1
+	str     r2, [r1]
+#endif
+
+wait_loop:
+	.long	0xE320F003 /* wfi */
+
+	ldr		r2, [r1, #0xC]
+	str		r2, [r1, #0x10]
+
+	ldr		r0, =MERAM_BASE
+	ldr		r2, [r0]
+	cmp		r2, #0
+	movne	pc, r2
+
+	b		wait_loop
+
+wait_loop_end:
+	.pool
+	.align 4
+
+lowlevel_init__:
+
+	mov r0, #0x200000
+
+loop0:
+	subs r0, r0, #1
+	bne  loop0
+
+	ldr sp, MERAM_STACK
+	b s_init
+
+	.pool
+	.align 4
+
+ENDPROC(lowlevel_init)
+	.ltorg
+
+MERAM_STACK:
+	.word LOW_LEVEL_MERAM_STACK

arch/arm/cpu/armv7/rmobile/timer.c

@@ -0,0 +1,97 @@
+/*
+ * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * (C) Copyright 2012 Renesas Solutions Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch-armv7/globaltimer.h>
+#include <asm/arch/rmobile.h>
+
+static struct globaltimer *global_timer = \
+		(struct globaltimer *)GLOBAL_TIMER_BASE_ADDR;
+
+#define CLK2MHZ(clk)	(clk / 1000 / 1000)
+static u64 get_cpu_global_timer(void)
+{
+	u32 low, high;
+	u64 timer;
+
+	u32 old = readl(&global_timer->cnt_h);
+	while (1) {
+		low = readl(&global_timer->cnt_l);
+		high = readl(&global_timer->cnt_h);
+		if (old == high)
+			break;
+		else
+			old = high;
+	}
+
+	timer = high;
+	return (u64)((timer << 32) | low);
+}
+
+static u64 get_time_us(void)
+{
+	u64 timer = get_cpu_global_timer();
+
+	timer = ((timer << 2) + (CLK2MHZ(CONFIG_SYS_CPU_CLK) >> 1));
+	timer /= (u64)CLK2MHZ(CONFIG_SYS_CPU_CLK);
+	return timer;
+}
+
+static ulong get_time_ms(void)
+{
+	return (ulong)(get_time_us() / 1000);
+}
+
+int timer_init(void)
+{
+	writel(0x01, &global_timer->ctl);
+	return 0;
+}
+
+void __udelay(unsigned long usec)
+{
+	u64 start, current;
+	u64 wait;
+
+	start = get_cpu_global_timer();
+	wait = (u64)((usec * CLK2MHZ(CONFIG_SYS_CPU_CLK)) >> 2);
+	do {
+		current = get_cpu_global_timer();
+	} while ((current - start) < wait);
+}
+
+ulong get_timer(ulong base)
+{
+	return get_time_ms() - base;
+}
+
+unsigned long long get_ticks(void)
+{
+	return get_cpu_global_timer();
+}
+
+ulong get_tbclk(void)
+{
+	return (ulong)(CONFIG_SYS_CPU_CLK >> 2);
+}

arch/arm/cpu/armv7/socfpga/Makefile

@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2012 Altera Corporation <www.altera.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+
+include $(TOPDIR)/config.mk
+
+LIB	=  $(obj)lib$(SOC).o
+
+SOBJS	:= lowlevel_init.o
+COBJS-y	:= misc.o timer.o
+COBJS-$(CONFIG_SPL_BUILD) += spl.o
+
+COBJS	:= $(COBJS-y)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+all:	 $(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

arch/arm/cpu/armv7/socfpga/config.mk

@@ -0,0 +1,16 @@
+#
+# Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed "as is" WITHOUT ANY WARRANTY of any
+# kind, whether express or implied; without even the implied warranty
+# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+ifndef CONFIG_SPL_BUILD
+ALL-y	+= $(obj)u-boot.img
+endif

arch/arm/cpu/armv7/socfpga/lowlevel_init.S

@@ -0,0 +1,77 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <config.h>
+#include <version.h>
+
+/* Save the parameter pass in by previous boot loader */
+.global save_boot_params
+save_boot_params:
+	/* save the parameter here */
+
+	/*
+	 * Setup stack for exception, which is located
+	 * at the end of on-chip RAM. We don't expect exception prior to
+	 * relocation and if that happens, we won't worry -- it will overide
+	 * global data region as the code will goto reset. After relocation,
+	 * this region won't be used by other part of program.
+	 * Hence it is safe.
+	 */
+	ldr	r0, =(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
+	ldr	r1, =IRQ_STACK_START_IN
+	str	r0, [r1]
+
+	bx	lr
+
+
+/* Set up the platform, once the cpu has been initialized */
+.globl lowlevel_init
+lowlevel_init:
+
+	/* Remap */
+#ifdef CONFIG_SPL_BUILD
+	/*
+	 * SPL : configure the remap (L3 NIC-301 GPV)
+	 * so the on-chip RAM at lower memory instead ROM.
+	 */
+	ldr	r0, =SOCFPGA_L3REGS_ADDRESS
+	mov	r1, #0x19
+	str	r1, [r0]
+#else
+	/*
+	 * U-Boot : configure the remap (L3 NIC-301 GPV)
+	 * so the SDRAM at lower memory instead on-chip RAM.
+	 */
+	ldr	r0, =SOCFPGA_L3REGS_ADDRESS
+	mov	r1, #0x2
+	str	r1, [r0]
+
+	/* Private components security */
+
+	/*
+	 * U-Boot : configure private timer, global timer and cpu
+	 * component access as non secure for kernel stage (as required
+	 * by kernel)
+	 */
+	mrc	p15,4,r0,c15,c0,0
+	add	r1, r0, #0x54
+	ldr	r2, [r1]
+	orr	r2, r2, #0xff
+	orr	r2, r2, #0xf00
+	str	r2, [r1]
+#endif	/* #ifdef CONFIG_SPL_BUILD */
+	mov	pc, lr

arch/arm/cpu/armv7/socfpga/misc.c

@@ -0,0 +1,54 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/reset_manager.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_reset_manager *reset_manager_base =
+		(void *)SOCFPGA_RSTMGR_ADDRESS;
+
+/*
+ * Write the reset manager register to cause reset
+ */
+void reset_cpu(ulong addr)
+{
+	/* request a warm reset */
+	writel(RSTMGR_CTRL_SWWARMRSTREQ_LSB, &reset_manager_base->ctrl);
+	/*
+	 * infinite loop here as watchdog will trigger and reset
+	 * the processor
+	 */
+	while (1)
+		;
+}
+
+/*
+ * Release peripherals from reset based on handoff
+ */
+void reset_deassert_peripherals_handoff(void)
+{
+	writel(0, &reset_manager_base->per_mod_reset);
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+	return 0;
+}

arch/arm/cpu/armv7/socfpga/spl.c

@@ -0,0 +1,48 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/u-boot.h>
+#include <asm/utils.h>
+#include <version.h>
+#include <image.h>
+#include <malloc.h>
+#include <asm/arch/reset_manager.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 spl_boot_device(void)
+{
+	return BOOT_DEVICE_RAM;
+}
+
+/*
+ * Board initialization after bss clearance
+ */
+void spl_board_init(void)
+{
+	/* init timer for enabling delay function */
+	timer_init();
+
+	/* de-assert reset for peripherals and bridges based on handoff */
+	reset_deassert_peripherals_handoff();
+
+	/* enable console uart printing */
+	preloader_console_init();
+}

arch/arm/cpu/armv7/socfpga/timer.c

@@ -0,0 +1,104 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/timer.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_timer *timer_base = (void *)CONFIG_SYS_TIMERBASE;
+
+/*
+ * Timer initialization
+ */
+int timer_init(void)
+{
+	writel(TIMER_LOAD_VAL, &timer_base->load_val);
+	writel(TIMER_LOAD_VAL, &timer_base->curr_val);
+	writel(readl(&timer_base->ctrl) | 0x3, &timer_base->ctrl);
+	return 0;
+}
+
+static u32 read_timer(void)
+{
+	return readl(&timer_base->curr_val);
+}
+
+/*
+ * Delay x useconds
+ */
+void __udelay(unsigned long usec)
+{
+	unsigned long now, last;
+	/*
+	 * get the tmo value based on timer clock speed
+	 * tmo = delay required / period of timer clock
+	 */
+	long tmo = usec * CONFIG_TIMER_CLOCK_KHZ / 1000;
+
+	last = read_timer();
+	while (tmo > 0) {
+		now = read_timer();
+		if (last >= now)
+			/* normal mode (non roll) */
+			tmo -= last - now;
+		else
+			/* we have overflow of the count down timer */
+			tmo -= TIMER_LOAD_VAL - last + now;
+		last = now;
+	}
+}
+
+/*
+ * Get the timer value
+ */
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+/*
+ * Timer : get the time difference
+ * Unit of tick is based on the CONFIG_SYS_HZ
+ */
+ulong get_timer_masked(void)
+{
+	/* current tick value */
+	ulong now = read_timer() / (CONFIG_TIMER_CLOCK_KHZ/CONFIG_SYS_HZ);
+	if (gd->lastinc >= now) {
+		/* normal mode (non roll) */
+		/* move stamp forward with absolute diff ticks */
+		gd->tbl += gd->lastinc - now;
+	} else {
+		/* we have overflow of the count down timer */
+		gd->tbl += TIMER_LOAD_VAL - gd->lastinc + now;
+	}
+	gd->lastinc = now;
+	return gd->tbl;
+}
+
+/*
+ * Reset the timer
+ */
+void reset_timer(void)
+{
+	/* capture current decrementer value time */
+	gd->lastinc = read_timer() / (CONFIG_TIMER_CLOCK_KHZ/CONFIG_SYS_HZ);
+	/* start "advancing" time stamp from 0 */
+	gd->tbl = 0;
+}

arch/arm/cpu/armv7/socfpga/u-boot-spl.lds

@@ -0,0 +1,60 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+MEMORY { .sdram : ORIGIN = (0), LENGTH = (0xffffffff) }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text	:
+	{
+		arch/arm/cpu/armv7/start.o	(.text)
+		*(.text*)
+	} >.sdram
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } >.sdram
+
+	. = ALIGN(4);
+	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sdram
+
+	. = ALIGN(4);
+	__image_copy_end = .;
+	_end = .;
+
+	.bss : {
+		. = ALIGN(4);
+		__bss_start = .;
+		*(.bss*)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} >.sdram
+
+	. = ALIGN(8);
+	__malloc_start = .;
+	. = . + CONFIG_SPL_MALLOC_SIZE;
+	__malloc_end = .;
+
+	. = . + CONFIG_SPL_STACK_SIZE;
+	. = ALIGN(8);
+	__stack_start = .;
+}

arch/arm/cpu/armv7/start.S

@@ -164,6 +164,7 @@ call_board_init_f:
 
 /*------------------------------------------------------------------------------*/
 
+#ifndef CONFIG_SPL_BUILD
 /*
  * void relocate_code (addr_sp, gd, addr_moni)
  *
@@ -194,7 +195,6 @@ copy_loop:
 	cmp	r0, r2			/* until source end address [r2]    */
 	blo	copy_loop
 
-#ifndef CONFIG_SPL_BUILD
 	/*
 	 * fix .rel.dyn relocations
 	 */
@@ -241,20 +241,12 @@ _rel_dyn_end_ofs:
 _dynsym_start_ofs:
 	.word __dynsym_start - _start
 
-#endif	/* #ifndef CONFIG_SPL_BUILD */
-
 clear_bss:
-#ifdef CONFIG_SPL_BUILD
-	/* No relocation for SPL */
-	ldr	r0, =__bss_start
-	ldr	r1, =__bss_end__
-#else
 	ldr	r0, _bss_start_ofs
 	ldr	r1, _bss_end_ofs
 	mov	r4, r6			/* reloc addr */
 	add	r0, r0, r4
 	add	r1, r1, r4
-#endif
 	mov	r2, #0x00000000		/* clear			    */
 
 clbss_l:cmp	r0, r1			/* clear loop... */
@@ -281,12 +273,10 @@ jump_2_ram:
  * Move vector table
  */
 #if !defined(CONFIG_TEGRA20)
-#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
 	/* Set vector address in CP15 VBAR register */
 	ldr     r0, =_start
 	add     r0, r0, r9
 	mcr     p15, 0, r0, c12, c0, 0  @Set VBAR
-#endif
 #endif /* !Tegra20 */
 
 	ldr	r0, _board_init_r_ofs
@@ -302,6 +292,7 @@ jump_2_ram:
 _board_init_r_ofs:
 	.word board_init_r - _start
 ENDPROC(relocate_code)
+#endif
 
 /*************************************************************************
  *
@@ -369,10 +360,7 @@ ENTRY(cpu_init_crit)
 	 * basic memory. Go here to bump up clock rate and handle
 	 * wake up conditions.
 	 */
-	mov	ip, lr			@ persevere link reg across call
-	bl	lowlevel_init		@ go setup pll,mux,memory
-	mov	lr, ip			@ restore link
-	mov	pc, lr			@ back to my caller
+	b	lowlevel_init		@ go setup pll,mux,memory
 ENDPROC(cpu_init_crit)
 #endif
 

arch/arm/cpu/armv7/zynq/Makefile

@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).o
+
+COBJS-y	:= timer.o
+COBJS-y	+= cpu.o
+
+COBJS	:= $(COBJS-y)
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

arch/arm/cpu/armv7/zynq/cpu.c

@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
+ * Copyright (C) 2012 Xilinx, Inc. All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+inline void lowlevel_init(void) {}
+
+void reset_cpu(ulong addr)
+{
+	while (1)
+		;
+}

arch/arm/cpu/armv7/zynq/timer.c

@@ -0,0 +1,150 @@
+/*
+ * Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
+ * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved.
+ *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+ *
+ * (C) Copyright 2004
+ * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
+ *
+ * (C) Copyright 2002-2004
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments <www.ti.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct scu_timer {
+	u32 load; /* Timer Load Register */
+	u32 counter; /* Timer Counter Register */
+	u32 control; /* Timer Control Register */
+};
+
+static struct scu_timer *timer_base =
+			      (struct scu_timer *) CONFIG_SCUTIMER_BASEADDR;
+
+#define SCUTIMER_CONTROL_PRESCALER_MASK	0x0000FF00 /* Prescaler */
+#define SCUTIMER_CONTROL_PRESCALER_SHIFT	8
+#define SCUTIMER_CONTROL_AUTO_RELOAD_MASK	0x00000002 /* Auto-reload */
+#define SCUTIMER_CONTROL_ENABLE_MASK		0x00000001 /* Timer enable */
+
+#define TIMER_LOAD_VAL 0xFFFFFFFF
+#define TIMER_PRESCALE 255
+#define TIMER_TICK_HZ  (CONFIG_CPU_FREQ_HZ / 2 / TIMER_PRESCALE)
+
+int timer_init(void)
+{
+	const u32 emask = SCUTIMER_CONTROL_AUTO_RELOAD_MASK |
+			(TIMER_PRESCALE << SCUTIMER_CONTROL_PRESCALER_SHIFT) |
+			SCUTIMER_CONTROL_ENABLE_MASK;
+
+	/* Load the timer counter register */
+	writel(0xFFFFFFFF, &timer_base->counter);
+
+	/*
+	 * Start the A9Timer device
+	 * Enable Auto reload mode, Clear prescaler control bits
+	 * Set prescaler value, Enable the decrementer
+	 */
+	clrsetbits_le32(&timer_base->control, SCUTIMER_CONTROL_PRESCALER_MASK,
+								emask);
+
+	/* Reset time */
+	gd->lastinc = readl(&timer_base->counter) /
+					(TIMER_TICK_HZ / CONFIG_SYS_HZ);
+	gd->tbl = 0;
+
+	return 0;
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+ulong get_timer_masked(void)
+{
+	ulong now;
+
+	now = readl(&timer_base->counter) / (TIMER_TICK_HZ / CONFIG_SYS_HZ);
+
+	if (gd->lastinc >= now) {
+		/* Normal mode */
+		gd->tbl += gd->lastinc - now;
+	} else {
+		/* We have an overflow ... */
+		gd->tbl += gd->lastinc + TIMER_LOAD_VAL - now;
+	}
+	gd->lastinc = now;
+
+	return gd->tbl;
+}
+
+void __udelay(unsigned long usec)
+{
+	unsigned long long tmp;
+	ulong tmo;
+
+	tmo = usec / (1000000 / CONFIG_SYS_HZ);
+	tmp = get_ticks() + tmo; /* Get current timestamp */
+
+	while (get_ticks() < tmp) { /* Loop till event */
+		 /* NOP */;
+	}
+}
+
+/* Timer without interrupts */
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	return CONFIG_SYS_HZ;
+}

arch/arm/cpu/ixp/start.S

@@ -273,6 +273,7 @@ stack_setup:
 
 	adr	r0, _start
 	cmp	r0, r6
+	moveq	r9, #0		/* no relocation. relocation offset(r9) = 0 */
 	beq	clear_bss		/* skip relocation */
 	mov	r1, r6			/* r1 <- scratch for copy_loop */
 	ldr	r3, _bss_start_ofs

arch/arm/cpu/lh7a40x/start.S

@@ -184,6 +184,7 @@ stack_setup:
 
 	adr	r0, _start
 	cmp	r0, r6
+	moveq	r9, #0		/* no relocation. relocation offset(r9) = 0 */
 	beq	clear_bss		/* skip relocation */
 	mov	r1, r6			/* r1 <- scratch for copy_loop */
 	ldr	r3, _bss_start_ofs

arch/arm/cpu/pxa/start.S

@@ -197,6 +197,7 @@ stack_setup:
 
 	adr	r0, _start
 	cmp	r0, r6
+	moveq	r9, #0		/* no relocation. relocation offset(r9) = 0 */
 	beq	clear_bss		/* skip relocation */
 	mov	r1, r6			/* r1 <- scratch for copy_loop */
 	ldr	r3, _bss_start_ofs

arch/arm/cpu/s3c44b0/start.S

@@ -156,6 +156,7 @@ stack_setup:
 
 	adr	r0, _start
 	cmp	r0, r6
+	moveq	r9, #0		/* no relocation. relocation offset(r9) = 0 */
 	beq	clear_bss		/* skip relocation */
 	mov	r1, r6			/* r1 <- scratch for copy_loop */
 	ldr	r3, _bss_start_ofs

arch/arm/cpu/sa1100/start.S

@@ -160,6 +160,7 @@ stack_setup:
 
 	adr	r0, _start
 	cmp	r0, r6
+	moveq	r9, #0		/* no relocation. relocation offset(r9) = 0 */
 	beq	clear_bss		/* skip relocation */
 	mov	r1, r6			/* r1 <- scratch for copy_loop */
 	ldr	r3, _bss_start_ofs

arch/arm/imx-common/cpu.c

@@ -30,6 +30,7 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/crm_regs.h>
+#include <ipu_pixfmt.h>
 
 #ifdef CONFIG_FSL_ESDHC
 #include <fsl_esdhc.h>
@@ -138,3 +139,11 @@ u32 get_ahb_clk(void)
 
 	return get_periph_clk() / (ahb_podf + 1);
 }
+
+#if defined(CONFIG_VIDEO_IPUV3)
+void arch_preboot_os(void)
+{
+	/* disable video before launching O/S */
+	ipuv3_fb_shutdown();
+}
+#endif

arch/arm/include/asm/arch-am33xx/spl.h

@@ -0,0 +1,33 @@
+/*
+ * (C) Copyright 2012
+ * Texas Instruments, <www.ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef	_ASM_ARCH_SPL_H_
+#define	_ASM_SPL_H_
+
+#define BOOT_DEVICE_XIP       	2
+#define BOOT_DEVICE_NAND	5
+#define BOOT_DEVICE_MMC1	8
+#define BOOT_DEVICE_MMC2	9	/* eMMC or daughter card */
+#define BOOT_DEVICE_UART	65
+#define BOOT_DEVICE_CPGMAC	70
+#define BOOT_DEVICE_MMC2_2      0xFF
+#endif

arch/arm/include/asm/arch-armv7/globaltimer.h

@@ -0,0 +1,36 @@
+/*
+ * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * (C) Copyright 2012 Renesas Solutions Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _GLOBALTIMER_H_
+#define _GLOBALTIMER_H_
+
+struct globaltimer {
+	u32 cnt_l; /* 0x00 */
+	u32 cnt_h;
+	u32 ctl;
+	u32 stat;
+	u32 cmp_l; /* 0x10 */
+	u32 cmp_h;
+	u32 inc;
+};
+
+#endif /* _GLOBALTIMER_H_ */

arch/arm/include/asm/arch-davinci/spl.h

@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2012
+ * Texas Instruments, <www.ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef	_ASM_ARCH_SPL_H_
+#define	_ASM_SPL_H_
+
+#define BOOT_DEVICE_NAND	1
+#define BOOT_DEVICE_SPI		2
+#define BOOT_DEVICE_MMC1	3
+#define BOOT_DEVICE_MMC2	4	/* dummy */
+#define BOOT_DEVICE_MMC2_2	5	/* dummy */
+
+#endif

arch/arm/include/asm/arch-kirkwood/cpu.h

@@ -155,10 +155,10 @@ struct kwgpio_registers {
 /*
  * functions
  */
-void reset_cpu(unsigned long ignored);
 unsigned char get_random_hex(void);
 unsigned int kw_sdram_bar(enum memory_bank bank);
 unsigned int kw_sdram_bs(enum memory_bank bank);
+void kw_sdram_size_adjust(enum memory_bank bank);
 int kw_config_adr_windows(void);
 void kw_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val,
 		unsigned int gpp0_oe, unsigned int gpp1_oe);

arch/arm/include/asm/arch-kirkwood/mpp.h

@@ -85,7 +85,7 @@
 #define MPP7_SPI_SCn		MPP(  7, 0x2, 0, 1, 1,   1,   1,   1    )
 #define MPP7_PTP_TRIG_GEN	MPP(  7, 0x3, 0, 1, 1,   1,   1,   1    )
 
-#define MPP8_GPIO		MPP(  8, 0x0, 1, 1, 1,    1,  1,   1    )
+#define MPP8_GPIO		MPP(  8, 0x0, 1, 1, 1,   1,   1,   1    )
 #define MPP8_TW_SDA		MPP(  8, 0x1, 1, 1, 1,   1,   1,   1    )
 #define MPP8_UART0_RTS		MPP(  8, 0x2, 0, 1, 1,   1,   1,   1    )
 #define MPP8_UART1_RTS		MPP(  8, 0x3, 0, 1, 1,   1,   1,   1    )

arch/arm/include/asm/arch-mx5/imx-regs.h

@@ -321,6 +321,8 @@
 #define BOARD_REV_1_0           0x0
 #define BOARD_REV_2_0           0x1
 
+#define BOARD_VER_OFFSET	0x8
+
 #define IMX_IIM_BASE            (IIM_BASE_ADDR)
 
 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))

arch/arm/include/asm/arch-omap3/spl.h

@@ -0,0 +1,34 @@
+/*
+ * (C) Copyright 2012
+ * Texas Instruments, <www.ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef	_ASM_ARCH_SPL_H_
+#define	_ASM_SPL_H_
+
+#define BOOT_DEVICE_NONE	0
+#define BOOT_DEVICE_XIP		1
+#define BOOT_DEVICE_NAND	2
+#define BOOT_DEVICE_ONE_NAND	3
+#define BOOT_DEVICE_MMC2	5 /*emmc*/
+#define BOOT_DEVICE_MMC1	6
+#define BOOT_DEVICE_XIPWAIT	7
+#define BOOT_DEVICE_MMC2_2      0xFF
+#endif

arch/arm/include/asm/arch-omap4/spl.h

@@ -0,0 +1,35 @@
+/*
+ * (C) Copyright 2012
+ * Texas Instruments, <www.ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef	_ASM_ARCH_SPL_H_
+#define	_ASM_SPL_H_
+
+#define BOOT_DEVICE_NONE	0
+#define BOOT_DEVICE_XIP		1
+#define BOOT_DEVICE_XIPWAIT	2
+#define BOOT_DEVICE_NAND	3
+#define BOOT_DEVICE_ONE_NAND	4
+#define BOOT_DEVICE_MMC1	5
+#define BOOT_DEVICE_MMC2	6
+#define BOOT_DEVICE_MMC2_2	0xFF
+
+#endif

arch/arm/include/asm/arch-omap4/sys_proto.h

@@ -42,7 +42,6 @@ void sr32(void *, u32, u32, u32);
 u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
 void set_pl310_ctrl_reg(u32 val);
-void omap_rev_string(void);
 void setup_clocks_for_console(void);
 void prcm_init(void);
 void bypass_dpll(u32 *const base);

arch/arm/include/asm/arch-omap5/spl.h

@@ -0,0 +1,35 @@
+/*
+ * (C) Copyright 2012
+ * Texas Instruments, <www.ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef	_ASM_ARCH_SPL_H_
+#define	_ASM_SPL_H_
+
+#define BOOT_DEVICE_NONE        0
+#define BOOT_DEVICE_XIP         1
+#define BOOT_DEVICE_XIPWAIT     2
+#define BOOT_DEVICE_NAND        3
+#define BOOT_DEVICE_ONE_NAND    4
+#define BOOT_DEVICE_MMC1        5
+#define BOOT_DEVICE_MMC2        6
+#define BOOT_DEVICE_MMC2_2	7
+
+#endif

arch/arm/include/asm/arch-omap5/sys_proto.h

@@ -42,7 +42,6 @@ void set_muxconf_regs_non_essential(void);
 void sr32(void *, u32, u32, u32);
 u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
-void omap_rev_string(void);
 void setup_clocks_for_console(void);
 void prcm_init(void);
 void bypass_dpll(u32 *const base);

arch/arm/include/asm/arch-orion5x/cpu.h

@@ -251,7 +251,6 @@ struct orion5x_ddr_addr_decode_registers {
 /*
  * functions
  */
-void reset_cpu(unsigned long ignored);
 u32 orion5x_device_id(void);
 u32 orion5x_device_rev(void);
 unsigned int orion5x_winctrl_calcsize(unsigned int sizeval);

arch/arm/include/asm/arch-rmobile/gpio.h

@@ -0,0 +1,12 @@
+#ifndef __ASM_ARCH_GPIO_H
+#define __ASM_ARCH_GPIO_H
+
+#if defined(CONFIG_SH73A0)
+#include "sh73a0-gpio.h"
+void sh73a0_pinmux_init(void);
+#elif defined(CONFIG_R8A7740)
+#include "r8a7740-gpio.h"
+void r8a7740_pinmux_init(void);
+#endif
+
+#endif /* __ASM_ARCH_GPIO_H */

arch/arm/include/asm/arch-rmobile/irqs.h

@@ -0,0 +1,18 @@
+#ifndef __ASM_MACH_IRQS_H
+#define __ASM_MACH_IRQS_H
+
+#define NR_IRQS         1024
+
+/* GIC */
+#define gic_spi(nr)		((nr) + 32)
+
+/* INTCA */
+#define evt2irq(evt)		(((evt) >> 5) - 16)
+#define irq2evt(irq)		(((irq) + 16) << 5)
+
+/* INTCS */
+#define INTCS_VECT_BASE		0x2200
+#define INTCS_VECT(n, vect)	INTC_VECT((n), INTCS_VECT_BASE + (vect))
+#define intcs_evt2irq(evt)	evt2irq(INTCS_VECT_BASE + (evt))
+
+#endif /* __ASM_MACH_IRQS_H */

arch/arm/include/asm/arch-rmobile/r8a7740-gpio.h

@@ -0,0 +1,584 @@
+/*
+ * Copyright (C) 2011  Renesas Solutions Corp.
+ * Copyright (C) 2011  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#ifndef __ASM_R8A7740_H__
+#define __ASM_R8A7740_H__
+
+/*
+ * MD_CKx pin
+ */
+#define MD_CK2	(1 << 2)
+#define MD_CK1	(1 << 1)
+#define MD_CK0	(1 << 0)
+
+/*
+ * Pin Function Controller:
+ *	GPIO_FN_xx - GPIO used to select pin function
+ *	GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
+ */
+enum {
+	/* PORT */
+	GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
+	GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
+
+	GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
+	GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
+
+	GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
+	GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
+
+	GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
+	GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
+
+	GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44,
+	GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49,
+
+	GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54,
+	GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59,
+
+	GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64,
+	GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
+
+	GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
+	GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
+
+	GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
+	GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89,
+
+	GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94,
+	GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
+
+	GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
+	GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
+
+	GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
+	GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119,
+
+	GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124,
+	GPIO_PORT125, GPIO_PORT126, GPIO_PORT127, GPIO_PORT128, GPIO_PORT129,
+
+	GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
+	GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139,
+
+	GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144,
+	GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149,
+
+	GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154,
+	GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159,
+
+	GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
+	GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169,
+
+	GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174,
+	GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178, GPIO_PORT179,
+
+	GPIO_PORT180, GPIO_PORT181, GPIO_PORT182, GPIO_PORT183, GPIO_PORT184,
+	GPIO_PORT185, GPIO_PORT186, GPIO_PORT187, GPIO_PORT188, GPIO_PORT189,
+
+	GPIO_PORT190, GPIO_PORT191, GPIO_PORT192, GPIO_PORT193, GPIO_PORT194,
+	GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199,
+
+	GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204,
+	GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209,
+
+	GPIO_PORT210, GPIO_PORT211,
+
+	/* IRQ */
+	GPIO_FN_IRQ0_PORT2,	GPIO_FN_IRQ0_PORT13,
+	GPIO_FN_IRQ1,
+	GPIO_FN_IRQ2_PORT11,	GPIO_FN_IRQ2_PORT12,
+	GPIO_FN_IRQ3_PORT10,	GPIO_FN_IRQ3_PORT14,
+	GPIO_FN_IRQ4_PORT15,	GPIO_FN_IRQ4_PORT172,
+	GPIO_FN_IRQ5_PORT0,	GPIO_FN_IRQ5_PORT1,
+	GPIO_FN_IRQ6_PORT121,	GPIO_FN_IRQ6_PORT173,
+	GPIO_FN_IRQ7_PORT120,	GPIO_FN_IRQ7_PORT209,
+	GPIO_FN_IRQ8,
+	GPIO_FN_IRQ9_PORT118,	GPIO_FN_IRQ9_PORT210,
+	GPIO_FN_IRQ10,
+	GPIO_FN_IRQ11,
+	GPIO_FN_IRQ12_PORT42,	GPIO_FN_IRQ12_PORT97,
+	GPIO_FN_IRQ13_PORT64,	GPIO_FN_IRQ13_PORT98,
+	GPIO_FN_IRQ14_PORT63,	GPIO_FN_IRQ14_PORT99,
+	GPIO_FN_IRQ15_PORT62,	GPIO_FN_IRQ15_PORT100,
+	GPIO_FN_IRQ16_PORT68,	GPIO_FN_IRQ16_PORT211,
+	GPIO_FN_IRQ17,
+	GPIO_FN_IRQ18,
+	GPIO_FN_IRQ19,
+	GPIO_FN_IRQ20,
+	GPIO_FN_IRQ21,
+	GPIO_FN_IRQ22,
+	GPIO_FN_IRQ23,
+	GPIO_FN_IRQ24,
+	GPIO_FN_IRQ25,
+	GPIO_FN_IRQ26_PORT58,	GPIO_FN_IRQ26_PORT81,
+	GPIO_FN_IRQ27_PORT57,	GPIO_FN_IRQ27_PORT168,
+	GPIO_FN_IRQ28_PORT56,	GPIO_FN_IRQ28_PORT169,
+	GPIO_FN_IRQ29_PORT50,	GPIO_FN_IRQ29_PORT170,
+	GPIO_FN_IRQ30_PORT49,	GPIO_FN_IRQ30_PORT171,
+	GPIO_FN_IRQ31_PORT41,	GPIO_FN_IRQ31_PORT167,
+
+	/* Function */
+
+	/* DBGT */
+	GPIO_FN_DBGMDT2,	GPIO_FN_DBGMDT1,	GPIO_FN_DBGMDT0,
+	GPIO_FN_DBGMD10,	GPIO_FN_DBGMD11,	GPIO_FN_DBGMD20,
+	GPIO_FN_DBGMD21,
+
+	/* FSI */
+	GPIO_FN_FSIAISLD_PORT0,		/* FSIAISLD Port 0/5 */
+	GPIO_FN_FSIAISLD_PORT5,
+	GPIO_FN_FSIASPDIF_PORT9,	/* FSIASPDIF Port 9/18 */
+	GPIO_FN_FSIASPDIF_PORT18,
+	GPIO_FN_FSIAOSLD1,	GPIO_FN_FSIAOSLD2,
+	GPIO_FN_FSIAOLR,	GPIO_FN_FSIAOBT,
+	GPIO_FN_FSIAOSLD,	GPIO_FN_FSIAOMC,
+	GPIO_FN_FSIACK,		GPIO_FN_FSIAILR,
+	GPIO_FN_FSIAIBT,
+
+	/* FMSI */
+	GPIO_FN_FMSISLD_PORT1, /* FMSISLD Port 1/6 */
+	GPIO_FN_FMSISLD_PORT6,
+	GPIO_FN_FMSIILR,	GPIO_FN_FMSIIBT,
+	GPIO_FN_FMSIOLR,	GPIO_FN_FMSIOBT,
+	GPIO_FN_FMSICK,		GPIO_FN_FMSOILR,
+	GPIO_FN_FMSOIBT,	GPIO_FN_FMSOOLR,
+	GPIO_FN_FMSOOBT,	GPIO_FN_FMSOSLD,
+	GPIO_FN_FMSOCK,
+
+	/* SCIFA0 */
+	GPIO_FN_SCIFA0_SCK,	GPIO_FN_SCIFA0_CTS,
+	GPIO_FN_SCIFA0_RTS,	GPIO_FN_SCIFA0_RXD,
+	GPIO_FN_SCIFA0_TXD,
+
+	/* SCIFA1 */
+	GPIO_FN_SCIFA1_CTS,	GPIO_FN_SCIFA1_SCK,
+	GPIO_FN_SCIFA1_RXD,	GPIO_FN_SCIFA1_TXD,
+	GPIO_FN_SCIFA1_RTS,
+
+	/* SCIFA2 */
+	GPIO_FN_SCIFA2_SCK_PORT22, /* SCIFA2_SCK Port 22/199 */
+	GPIO_FN_SCIFA2_SCK_PORT199,
+	GPIO_FN_SCIFA2_RXD,	GPIO_FN_SCIFA2_TXD,
+	GPIO_FN_SCIFA2_CTS,	GPIO_FN_SCIFA2_RTS,
+
+	/* SCIFA3 */
+	GPIO_FN_SCIFA3_RTS_PORT105, /* MSEL5CR_8_0 */
+	GPIO_FN_SCIFA3_SCK_PORT116,
+	GPIO_FN_SCIFA3_CTS_PORT117,
+	GPIO_FN_SCIFA3_RXD_PORT174,
+	GPIO_FN_SCIFA3_TXD_PORT175,
+
+	GPIO_FN_SCIFA3_RTS_PORT161, /* MSEL5CR_8_1 */
+	GPIO_FN_SCIFA3_SCK_PORT158,
+	GPIO_FN_SCIFA3_CTS_PORT162,
+	GPIO_FN_SCIFA3_RXD_PORT159,
+	GPIO_FN_SCIFA3_TXD_PORT160,
+
+	/* SCIFA4 */
+	GPIO_FN_SCIFA4_RXD_PORT12, /* MSEL5CR[12:11] = 00 */
+	GPIO_FN_SCIFA4_TXD_PORT13,
+
+	GPIO_FN_SCIFA4_RXD_PORT204, /* MSEL5CR[12:11] = 01 */
+	GPIO_FN_SCIFA4_TXD_PORT203,
+
+	GPIO_FN_SCIFA4_RXD_PORT94, /* MSEL5CR[12:11] = 10 */
+	GPIO_FN_SCIFA4_TXD_PORT93,
+
+	GPIO_FN_SCIFA4_SCK_PORT21, /* SCIFA4_SCK Port 21/205 */
+	GPIO_FN_SCIFA4_SCK_PORT205,
+
+	/* SCIFA5 */
+	GPIO_FN_SCIFA5_TXD_PORT20, /* MSEL5CR[15:14] = 00 */
+	GPIO_FN_SCIFA5_RXD_PORT10,
+
+	GPIO_FN_SCIFA5_RXD_PORT207, /* MSEL5CR[15:14] = 01 */
+	GPIO_FN_SCIFA5_TXD_PORT208,
+
+	GPIO_FN_SCIFA5_TXD_PORT91, /* MSEL5CR[15:14] = 10 */
+	GPIO_FN_SCIFA5_RXD_PORT92,
+
+	GPIO_FN_SCIFA5_SCK_PORT23, /* SCIFA5_SCK Port 23/206 */
+	GPIO_FN_SCIFA5_SCK_PORT206,
+
+	/* SCIFA6 */
+	GPIO_FN_SCIFA6_SCK,	GPIO_FN_SCIFA6_RXD,	GPIO_FN_SCIFA6_TXD,
+
+	/* SCIFA7 */
+	GPIO_FN_SCIFA7_TXD,	GPIO_FN_SCIFA7_RXD,
+
+	/* SCIFAB */
+	GPIO_FN_SCIFB_SCK_PORT190, /* MSEL5CR_17_0 */
+	GPIO_FN_SCIFB_RXD_PORT191,
+	GPIO_FN_SCIFB_TXD_PORT192,
+	GPIO_FN_SCIFB_RTS_PORT186,
+	GPIO_FN_SCIFB_CTS_PORT187,
+
+	GPIO_FN_SCIFB_SCK_PORT2, /* MSEL5CR_17_1 */
+	GPIO_FN_SCIFB_RXD_PORT3,
+	GPIO_FN_SCIFB_TXD_PORT4,
+	GPIO_FN_SCIFB_RTS_PORT172,
+	GPIO_FN_SCIFB_CTS_PORT173,
+
+	/* LCD0 */
+	GPIO_FN_LCDC0_SELECT,
+	GPIO_FN_LCD0_D0,	GPIO_FN_LCD0_D1,	GPIO_FN_LCD0_D2,
+	GPIO_FN_LCD0_D3,	GPIO_FN_LCD0_D4,	GPIO_FN_LCD0_D5,
+	GPIO_FN_LCD0_D6,	GPIO_FN_LCD0_D7,	GPIO_FN_LCD0_D8,
+	GPIO_FN_LCD0_D9,	GPIO_FN_LCD0_D10,	GPIO_FN_LCD0_D11,
+	GPIO_FN_LCD0_D12,	GPIO_FN_LCD0_D13,	GPIO_FN_LCD0_D14,
+	GPIO_FN_LCD0_D15,	GPIO_FN_LCD0_D16,	GPIO_FN_LCD0_D17,
+	GPIO_FN_LCD0_DON,	GPIO_FN_LCD0_VCPWC,	GPIO_FN_LCD0_VEPWC,
+
+	GPIO_FN_LCD0_DCK,	GPIO_FN_LCD0_VSYN, /* for RGB */
+	GPIO_FN_LCD0_HSYN,	GPIO_FN_LCD0_DISP, /* for RGB */
+
+	GPIO_FN_LCD0_WR,	GPIO_FN_LCD0_RD, /* for SYS */
+	GPIO_FN_LCD0_CS,	GPIO_FN_LCD0_RS, /* for SYS */
+
+	GPIO_FN_LCD0_D18_PORT163,	GPIO_FN_LCD0_D19_PORT162,
+	GPIO_FN_LCD0_D20_PORT161,	GPIO_FN_LCD0_D21_PORT158,
+	GPIO_FN_LCD0_D22_PORT160,	GPIO_FN_LCD0_D23_PORT159,
+	GPIO_FN_LCD0_LCLK_PORT165,	 /* MSEL5CR_6_1 */
+
+	GPIO_FN_LCD0_D18_PORT40,	GPIO_FN_LCD0_D19_PORT4,
+	GPIO_FN_LCD0_D20_PORT3,		GPIO_FN_LCD0_D21_PORT2,
+	GPIO_FN_LCD0_D22_PORT0,		GPIO_FN_LCD0_D23_PORT1,
+	GPIO_FN_LCD0_LCLK_PORT102,	/* MSEL5CR_6_0 */
+
+	/* LCD1 */
+	GPIO_FN_LCDC1_SELECT,
+	GPIO_FN_LCD1_D0,	GPIO_FN_LCD1_D1,	GPIO_FN_LCD1_D2,
+	GPIO_FN_LCD1_D3,	GPIO_FN_LCD1_D4,	GPIO_FN_LCD1_D5,
+	GPIO_FN_LCD1_D6,	GPIO_FN_LCD1_D7,	GPIO_FN_LCD1_D8,
+	GPIO_FN_LCD1_D9,	GPIO_FN_LCD1_D10,	GPIO_FN_LCD1_D11,
+	GPIO_FN_LCD1_D12,	GPIO_FN_LCD1_D13,	GPIO_FN_LCD1_D14,
+	GPIO_FN_LCD1_D15,	GPIO_FN_LCD1_D16,	GPIO_FN_LCD1_D17,
+	GPIO_FN_LCD1_D18,	GPIO_FN_LCD1_D19,	GPIO_FN_LCD1_D20,
+	GPIO_FN_LCD1_D21,	GPIO_FN_LCD1_D22,	GPIO_FN_LCD1_D23,
+	GPIO_FN_LCD1_DON,	GPIO_FN_LCD1_VCPWC,
+	GPIO_FN_LCD1_LCLK,	GPIO_FN_LCD1_VEPWC,
+
+	GPIO_FN_LCD1_DCK,	GPIO_FN_LCD1_VSYN, /* for RGB */
+	GPIO_FN_LCD1_HSYN,	GPIO_FN_LCD1_DISP, /* for RGB */
+
+	GPIO_FN_LCD1_WR,	GPIO_FN_LCD1_RD, /* for SYS */
+	GPIO_FN_LCD1_CS,	GPIO_FN_LCD1_RS, /* for SYS */
+
+	/* RSPI */
+	GPIO_FN_RSPI_SSL0_A,	GPIO_FN_RSPI_SSL1_A,
+	GPIO_FN_RSPI_SSL2_A,	GPIO_FN_RSPI_SSL3_A,
+	GPIO_FN_RSPI_MOSI_A,	GPIO_FN_RSPI_MISO_A,
+	GPIO_FN_RSPI_CK_A,
+
+	/* VIO CKO */
+	GPIO_FN_VIO_CKO1,
+	GPIO_FN_VIO_CKO2,
+	GPIO_FN_VIO_CKO_1,
+	GPIO_FN_VIO_CKO,
+
+	/* VIO0 */
+	GPIO_FN_VIO0_D0,	GPIO_FN_VIO0_D1,	GPIO_FN_VIO0_D2,
+	GPIO_FN_VIO0_D3,	GPIO_FN_VIO0_D4,	GPIO_FN_VIO0_D5,
+	GPIO_FN_VIO0_D6,	GPIO_FN_VIO0_D7,	GPIO_FN_VIO0_D8,
+	GPIO_FN_VIO0_D9,	GPIO_FN_VIO0_D10,	GPIO_FN_VIO0_D11,
+	GPIO_FN_VIO0_D12,	GPIO_FN_VIO0_VD,	GPIO_FN_VIO0_HD,
+	GPIO_FN_VIO0_CLK,	GPIO_FN_VIO0_FIELD,
+
+	GPIO_FN_VIO0_D13_PORT26, /* MSEL5CR_27_0 */
+	GPIO_FN_VIO0_D14_PORT25,
+	GPIO_FN_VIO0_D15_PORT24,
+
+	GPIO_FN_VIO0_D13_PORT22, /* MSEL5CR_27_1 */
+	GPIO_FN_VIO0_D14_PORT95,
+	GPIO_FN_VIO0_D15_PORT96,
+
+	/* VIO1 */
+	GPIO_FN_VIO1_D0,	GPIO_FN_VIO1_D1,	GPIO_FN_VIO1_D2,
+	GPIO_FN_VIO1_D3,	GPIO_FN_VIO1_D4,	GPIO_FN_VIO1_D5,
+	GPIO_FN_VIO1_D6,	GPIO_FN_VIO1_D7,	GPIO_FN_VIO1_VD,
+	GPIO_FN_VIO1_HD,	GPIO_FN_VIO1_CLK,	GPIO_FN_VIO1_FIELD,
+
+	/* TPU0 */
+	GPIO_FN_TPU0TO0,	GPIO_FN_TPU0TO1,
+	GPIO_FN_TPU0TO3,
+	GPIO_FN_TPU0TO2_PORT66, /* TPU0TO2 Port 66/202 */
+	GPIO_FN_TPU0TO2_PORT202,
+
+	/* SSP1 0 */
+	GPIO_FN_STP0_IPD0,	GPIO_FN_STP0_IPD1,	GPIO_FN_STP0_IPD2,
+	GPIO_FN_STP0_IPD3,	GPIO_FN_STP0_IPD4,	GPIO_FN_STP0_IPD5,
+	GPIO_FN_STP0_IPD6,	GPIO_FN_STP0_IPD7,	GPIO_FN_STP0_IPEN,
+	GPIO_FN_STP0_IPCLK,	GPIO_FN_STP0_IPSYNC,
+
+	/* SSP1 1 */
+	GPIO_FN_STP1_IPD1,	GPIO_FN_STP1_IPD2,	GPIO_FN_STP1_IPD3,
+	GPIO_FN_STP1_IPD4,	GPIO_FN_STP1_IPD5,	GPIO_FN_STP1_IPD6,
+	GPIO_FN_STP1_IPD7,	GPIO_FN_STP1_IPCLK,	GPIO_FN_STP1_IPSYNC,
+
+	GPIO_FN_STP1_IPD0_PORT186, /* MSEL5CR_23_0 */
+	GPIO_FN_STP1_IPEN_PORT187,
+
+	GPIO_FN_STP1_IPD0_PORT194, /* MSEL5CR_23_1 */
+	GPIO_FN_STP1_IPEN_PORT193,
+
+	/* SIM */
+	GPIO_FN_SIM_RST,	GPIO_FN_SIM_CLK,
+	GPIO_FN_SIM_D_PORT22, /* SIM_D  Port 22/199 */
+	GPIO_FN_SIM_D_PORT199,
+
+	/* SDHI0 */
+	GPIO_FN_SDHI0_D0,	GPIO_FN_SDHI0_D1,	GPIO_FN_SDHI0_D2,
+	GPIO_FN_SDHI0_D3,	GPIO_FN_SDHI0_CD,	GPIO_FN_SDHI0_WP,
+	GPIO_FN_SDHI0_CMD,	GPIO_FN_SDHI0_CLK,
+
+	/* SDHI1 */
+	GPIO_FN_SDHI1_D0,	GPIO_FN_SDHI1_D1,	GPIO_FN_SDHI1_D2,
+	GPIO_FN_SDHI1_D3,	GPIO_FN_SDHI1_CD,	GPIO_FN_SDHI1_WP,
+	GPIO_FN_SDHI1_CMD,	GPIO_FN_SDHI1_CLK,
+
+	/* SDHI2 */
+	GPIO_FN_SDHI2_D0,	GPIO_FN_SDHI2_D1,	GPIO_FN_SDHI2_D2,
+	GPIO_FN_SDHI2_D3,	GPIO_FN_SDHI2_CLK,	GPIO_FN_SDHI2_CMD,
+
+	GPIO_FN_SDHI2_CD_PORT24, /* MSEL5CR_19_0 */
+	GPIO_FN_SDHI2_WP_PORT25,
+
+	GPIO_FN_SDHI2_WP_PORT177, /* MSEL5CR_19_1 */
+	GPIO_FN_SDHI2_CD_PORT202,
+
+	/* MSIOF2 */
+	GPIO_FN_MSIOF2_TXD,	GPIO_FN_MSIOF2_RXD,	GPIO_FN_MSIOF2_TSCK,
+	GPIO_FN_MSIOF2_SS2,	GPIO_FN_MSIOF2_TSYNC,	GPIO_FN_MSIOF2_SS1,
+	GPIO_FN_MSIOF2_MCK1,	GPIO_FN_MSIOF2_MCK0,	GPIO_FN_MSIOF2_RSYNC,
+	GPIO_FN_MSIOF2_RSCK,
+
+	/* KEYSC */
+	GPIO_FN_KEYIN4,		GPIO_FN_KEYIN5,
+	GPIO_FN_KEYIN6,		GPIO_FN_KEYIN7,
+	GPIO_FN_KEYOUT0,	GPIO_FN_KEYOUT1,	GPIO_FN_KEYOUT2,
+	GPIO_FN_KEYOUT3,	GPIO_FN_KEYOUT4,	GPIO_FN_KEYOUT5,
+	GPIO_FN_KEYOUT6,	GPIO_FN_KEYOUT7,
+
+	GPIO_FN_KEYIN0_PORT43, /* MSEL4CR_18_0 */
+	GPIO_FN_KEYIN1_PORT44,
+	GPIO_FN_KEYIN2_PORT45,
+	GPIO_FN_KEYIN3_PORT46,
+
+	GPIO_FN_KEYIN0_PORT58, /* MSEL4CR_18_1 */
+	GPIO_FN_KEYIN1_PORT57,
+	GPIO_FN_KEYIN2_PORT56,
+	GPIO_FN_KEYIN3_PORT55,
+
+	/* VOU */
+	GPIO_FN_DV_D0,	GPIO_FN_DV_D1,	GPIO_FN_DV_D2,	GPIO_FN_DV_D3,
+	GPIO_FN_DV_D4,	GPIO_FN_DV_D5,	GPIO_FN_DV_D6,	GPIO_FN_DV_D7,
+	GPIO_FN_DV_D8,	GPIO_FN_DV_D9,	GPIO_FN_DV_D10,	GPIO_FN_DV_D11,
+	GPIO_FN_DV_D12,	GPIO_FN_DV_D13,	GPIO_FN_DV_D14,	GPIO_FN_DV_D15,
+	GPIO_FN_DV_CLK,
+	GPIO_FN_DV_VSYNC,
+	GPIO_FN_DV_HSYNC,
+
+	/* MEMC */
+	GPIO_FN_MEMC_AD0,	GPIO_FN_MEMC_AD1,	GPIO_FN_MEMC_AD2,
+	GPIO_FN_MEMC_AD3,	GPIO_FN_MEMC_AD4,	GPIO_FN_MEMC_AD5,
+	GPIO_FN_MEMC_AD6,	GPIO_FN_MEMC_AD7,	GPIO_FN_MEMC_AD8,
+	GPIO_FN_MEMC_AD9,	GPIO_FN_MEMC_AD10,	GPIO_FN_MEMC_AD11,
+	GPIO_FN_MEMC_AD12,	GPIO_FN_MEMC_AD13,	GPIO_FN_MEMC_AD14,
+	GPIO_FN_MEMC_AD15,	GPIO_FN_MEMC_CS0,	GPIO_FN_MEMC_INT,
+	GPIO_FN_MEMC_NWE,	GPIO_FN_MEMC_NOE,
+
+	GPIO_FN_MEMC_CS1, /* MSEL4CR_6_0 */
+	GPIO_FN_MEMC_ADV,
+	GPIO_FN_MEMC_WAIT,
+	GPIO_FN_MEMC_BUSCLK,
+
+	GPIO_FN_MEMC_A1, /* MSEL4CR_6_1 */
+	GPIO_FN_MEMC_DREQ0,
+	GPIO_FN_MEMC_DREQ1,
+	GPIO_FN_MEMC_A0,
+
+	/* MMC */
+	GPIO_FN_MMC0_D0_PORT68,		GPIO_FN_MMC0_D1_PORT69,
+	GPIO_FN_MMC0_D2_PORT70,		GPIO_FN_MMC0_D3_PORT71,
+	GPIO_FN_MMC0_D4_PORT72,		GPIO_FN_MMC0_D5_PORT73,
+	GPIO_FN_MMC0_D6_PORT74,		GPIO_FN_MMC0_D7_PORT75,
+	GPIO_FN_MMC0_CLK_PORT66,
+	GPIO_FN_MMC0_CMD_PORT67,	/* MSEL4CR_15_0 */
+
+	GPIO_FN_MMC1_D0_PORT149,	GPIO_FN_MMC1_D1_PORT148,
+	GPIO_FN_MMC1_D2_PORT147,	GPIO_FN_MMC1_D3_PORT146,
+	GPIO_FN_MMC1_D4_PORT145,	GPIO_FN_MMC1_D5_PORT144,
+	GPIO_FN_MMC1_D6_PORT143,	GPIO_FN_MMC1_D7_PORT142,
+	GPIO_FN_MMC1_CLK_PORT103,
+	GPIO_FN_MMC1_CMD_PORT104,	/* MSEL4CR_15_1 */
+
+	/* MSIOF0 */
+	GPIO_FN_MSIOF0_SS1,	GPIO_FN_MSIOF0_SS2,
+	GPIO_FN_MSIOF0_RXD,	GPIO_FN_MSIOF0_TXD,
+	GPIO_FN_MSIOF0_MCK0,	GPIO_FN_MSIOF0_MCK1,
+	GPIO_FN_MSIOF0_RSYNC,	GPIO_FN_MSIOF0_RSCK,
+	GPIO_FN_MSIOF0_TSCK,	GPIO_FN_MSIOF0_TSYNC,
+
+	/* MSIOF1 */
+	GPIO_FN_MSIOF1_RSCK,	GPIO_FN_MSIOF1_RSYNC,
+	GPIO_FN_MSIOF1_MCK0,	GPIO_FN_MSIOF1_MCK1,
+
+	GPIO_FN_MSIOF1_SS2_PORT116,	GPIO_FN_MSIOF1_SS1_PORT117,
+	GPIO_FN_MSIOF1_RXD_PORT118,	GPIO_FN_MSIOF1_TXD_PORT119,
+	GPIO_FN_MSIOF1_TSYNC_PORT120,
+	GPIO_FN_MSIOF1_TSCK_PORT121,	/* MSEL4CR_10_0 */
+
+	GPIO_FN_MSIOF1_SS1_PORT67,	GPIO_FN_MSIOF1_TSCK_PORT72,
+	GPIO_FN_MSIOF1_TSYNC_PORT73,	GPIO_FN_MSIOF1_TXD_PORT74,
+	GPIO_FN_MSIOF1_RXD_PORT75,
+	GPIO_FN_MSIOF1_SS2_PORT202,	/* MSEL4CR_10_1 */
+
+	/* GPIO */
+	GPIO_FN_GPO0,	GPIO_FN_GPI0,
+	GPIO_FN_GPO1,	GPIO_FN_GPI1,
+
+	/* USB0 */
+	GPIO_FN_USB0_OCI,	GPIO_FN_USB0_PPON,	GPIO_FN_VBUS,
+
+	/* USB1 */
+	GPIO_FN_USB1_OCI,	GPIO_FN_USB1_PPON,
+
+	/* BBIF1 */
+	GPIO_FN_BBIF1_RXD,	GPIO_FN_BBIF1_TXD,	GPIO_FN_BBIF1_TSYNC,
+	GPIO_FN_BBIF1_TSCK,	GPIO_FN_BBIF1_RSCK,	GPIO_FN_BBIF1_RSYNC,
+	GPIO_FN_BBIF1_FLOW,	GPIO_FN_BBIF1_RX_FLOW_N,
+
+	/* BBIF2 */
+	GPIO_FN_BBIF2_TXD2_PORT5, /* MSEL5CR_0_0 */
+	GPIO_FN_BBIF2_RXD2_PORT60,
+	GPIO_FN_BBIF2_TSYNC2_PORT6,
+	GPIO_FN_BBIF2_TSCK2_PORT59,
+
+	GPIO_FN_BBIF2_RXD2_PORT90, /* MSEL5CR_0_1 */
+	GPIO_FN_BBIF2_TXD2_PORT183,
+	GPIO_FN_BBIF2_TSCK2_PORT89,
+	GPIO_FN_BBIF2_TSYNC2_PORT184,
+
+	/* BSC / FLCTL / PCMCIA */
+	GPIO_FN_CS0,	GPIO_FN_CS2,	GPIO_FN_CS4,
+	GPIO_FN_CS5B,	GPIO_FN_CS6A,
+	GPIO_FN_CS5A_PORT105, /* CS5A PORT 19/105 */
+	GPIO_FN_CS5A_PORT19,
+	GPIO_FN_IOIS16, /* ? */
+
+	GPIO_FN_A0,	GPIO_FN_A1,	GPIO_FN_A2,	GPIO_FN_A3,
+	GPIO_FN_A4_FOE,		/* share with FLCTL */
+	GPIO_FN_A5_FCDE,	/* share with FLCTL */
+	GPIO_FN_A6,	GPIO_FN_A7,	GPIO_FN_A8,	GPIO_FN_A9,
+	GPIO_FN_A10,	GPIO_FN_A11,	GPIO_FN_A12,	GPIO_FN_A13,
+	GPIO_FN_A14,	GPIO_FN_A15,	GPIO_FN_A16,	GPIO_FN_A17,
+	GPIO_FN_A18,	GPIO_FN_A19,	GPIO_FN_A20,	GPIO_FN_A21,
+	GPIO_FN_A22,	GPIO_FN_A23,	GPIO_FN_A24,	GPIO_FN_A25,
+	GPIO_FN_A26,
+
+	GPIO_FN_D0_NAF0,	GPIO_FN_D1_NAF1,	/* share with FLCTL */
+	GPIO_FN_D2_NAF2,	GPIO_FN_D3_NAF3,	/* share with FLCTL */
+	GPIO_FN_D4_NAF4,	GPIO_FN_D5_NAF5,	/* share with FLCTL */
+	GPIO_FN_D6_NAF6,	GPIO_FN_D7_NAF7,	/* share with FLCTL */
+	GPIO_FN_D8_NAF8,	GPIO_FN_D9_NAF9,	/* share with FLCTL */
+	GPIO_FN_D10_NAF10,	GPIO_FN_D11_NAF11,	/* share with FLCTL */
+	GPIO_FN_D12_NAF12,	GPIO_FN_D13_NAF13,	/* share with FLCTL */
+	GPIO_FN_D14_NAF14,	GPIO_FN_D15_NAF15,	/* share with FLCTL */
+
+	GPIO_FN_D16,	GPIO_FN_D17,	GPIO_FN_D18,	GPIO_FN_D19,
+	GPIO_FN_D20,	GPIO_FN_D21,	GPIO_FN_D22,	GPIO_FN_D23,
+	GPIO_FN_D24,	GPIO_FN_D25,	GPIO_FN_D26,	GPIO_FN_D27,
+	GPIO_FN_D28,	GPIO_FN_D29,	GPIO_FN_D30,	GPIO_FN_D31,
+
+	GPIO_FN_WE0_FWE,	/* share with FLCTL */
+	GPIO_FN_WE1,
+	GPIO_FN_WE2_ICIORD,	/* share with PCMCIA */
+	GPIO_FN_WE3_ICIOWR,	/* share with PCMCIA */
+	GPIO_FN_CKO,	GPIO_FN_BS,	GPIO_FN_RDWR,
+	GPIO_FN_RD_FSC,		/* share with FLCTL */
+	GPIO_FN_WAIT_PORT177,	/* WAIT Port 90/177 */
+	GPIO_FN_WAIT_PORT90,
+
+	GPIO_FN_FCE0,	GPIO_FN_FCE1,	GPIO_FN_FRB, /* FLCTL */
+
+	/* IRDA */
+	GPIO_FN_IRDA_FIRSEL,	GPIO_FN_IRDA_IN,	GPIO_FN_IRDA_OUT,
+
+	/* ATAPI */
+	GPIO_FN_IDE_D0,		GPIO_FN_IDE_D1,		GPIO_FN_IDE_D2,
+	GPIO_FN_IDE_D3,		GPIO_FN_IDE_D4,		GPIO_FN_IDE_D5,
+	GPIO_FN_IDE_D6,		GPIO_FN_IDE_D7,		GPIO_FN_IDE_D8,
+	GPIO_FN_IDE_D9,		GPIO_FN_IDE_D10,	GPIO_FN_IDE_D11,
+	GPIO_FN_IDE_D12,	GPIO_FN_IDE_D13,	GPIO_FN_IDE_D14,
+	GPIO_FN_IDE_D15,	GPIO_FN_IDE_A0,		GPIO_FN_IDE_A1,
+	GPIO_FN_IDE_A2,		GPIO_FN_IDE_CS0,	GPIO_FN_IDE_CS1,
+	GPIO_FN_IDE_IOWR,	GPIO_FN_IDE_IORD,	GPIO_FN_IDE_IORDY,
+	GPIO_FN_IDE_INT,	GPIO_FN_IDE_RST,	GPIO_FN_IDE_DIRECTION,
+	GPIO_FN_IDE_EXBUF_ENB,	GPIO_FN_IDE_IODACK,	GPIO_FN_IDE_IODREQ,
+
+	/* RMII */
+	GPIO_FN_RMII_CRS_DV,	GPIO_FN_RMII_RX_ER,	GPIO_FN_RMII_RXD0,
+	GPIO_FN_RMII_RXD1,	GPIO_FN_RMII_TX_EN,	GPIO_FN_RMII_TXD0,
+	GPIO_FN_RMII_MDC,	GPIO_FN_RMII_TXD1,	GPIO_FN_RMII_MDIO,
+	GPIO_FN_RMII_REF50CK,	/* for RMII */
+	GPIO_FN_RMII_REF125CK,	/* for GMII */
+
+	/* GEther */
+	GPIO_FN_ET_TX_CLK,	GPIO_FN_ET_TX_EN,	GPIO_FN_ET_ETXD0,
+	GPIO_FN_ET_ETXD1,	GPIO_FN_ET_ETXD2,	GPIO_FN_ET_ETXD3,
+	GPIO_FN_ET_ETXD4,	GPIO_FN_ET_ETXD5, /* for GEther */
+	GPIO_FN_ET_ETXD6,	GPIO_FN_ET_ETXD7, /* for GEther */
+	GPIO_FN_ET_COL,		GPIO_FN_ET_TX_ER,
+	GPIO_FN_ET_RX_CLK,	GPIO_FN_ET_RX_DV,
+	GPIO_FN_ET_ERXD0,	GPIO_FN_ET_ERXD1,
+	GPIO_FN_ET_ERXD2,	GPIO_FN_ET_ERXD3,
+	GPIO_FN_ET_ERXD4,	GPIO_FN_ET_ERXD5, /* for GEther */
+	GPIO_FN_ET_ERXD6,	GPIO_FN_ET_ERXD7, /* for GEther */
+	GPIO_FN_ET_RX_ER,	GPIO_FN_ET_CRS,
+	GPIO_FN_ET_MDC,		GPIO_FN_ET_MDIO,
+	GPIO_FN_ET_LINK,	GPIO_FN_ET_PHY_INT,
+	GPIO_FN_ET_WOL,		GPIO_FN_ET_GTX_CLK,
+
+	/* DMA0 */
+	GPIO_FN_DREQ0,		GPIO_FN_DACK0,
+
+	/* DMA1 */
+	GPIO_FN_DREQ1,		GPIO_FN_DACK1,
+
+	/* SYSC */
+	GPIO_FN_RESETOUTS,
+	GPIO_FN_RESETP_PULLUP,
+	GPIO_FN_RESETP_PLAIN,
+
+	/* SDENC */
+	GPIO_FN_SDENC_CPG,
+	GPIO_FN_SDENC_DV_CLKI,
+
+	/* IRREM */
+	GPIO_FN_IROUT,
+
+	/* DEBUG */
+	GPIO_FN_EDEBGREQ_PULLDOWN,
+	GPIO_FN_EDEBGREQ_PULLUP,
+
+	GPIO_FN_TRACEAUD_FROM_VIO,
+	GPIO_FN_TRACEAUD_FROM_LCDC0,
+	GPIO_FN_TRACEAUD_FROM_MEMC,
+};
+
+#endif /* __ASM_R8A7740_H__ */

arch/arm/include/asm/arch-rmobile/r8a7740.h

@@ -0,0 +1,287 @@
+/*
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
+ */
+
+#ifndef __ASM_ARCH_R8A7740_H
+#define __ASM_ARCH_R8A7740_H
+
+/*
+ * R8A7740 I/O Addresses
+ */
+
+#define MERAM_BASE	0xE5580000
+#define DDRP_BASE	0xC12A0000
+#define HPB_BASE	0xE6000000
+#define RWDT0_BASE	0xE6020000
+#define RWDT1_BASE	0xE6030000
+#define GPIO_BASE	0xE6050000
+#define CMT1_BASE	0xE6138000
+#define CPG_BASE	0xE6150000
+#define SYSC_BASE	0xE6180000
+#define SDHI0_BASE	0xE6850000
+#define SDHI1_BASE	0xE6860000
+#define MMCIF_BASE	0xE6BD0000
+#define SCIF5_BASE	0xE6CB0000
+#define SCIF6_BASE	0xE6CC0000
+#define DBSC_BASE	0xFE400000
+#define BSC_BASE	0xFEC10000
+#define I2C0_BASE	0xFFF20000
+#define I2C1_BASE	0xE6C20000
+#define TMU_BASE	0xFFF80000
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+
+/* RWDT */
+struct r8a7740_rwdt {
+	u16 rwtcnt0;	/* 0x00 */
+	u16 dummy0;		/* 0x02 */
+	u16 rwtcsra0;	/* 0x04 */
+	u16 dummy1;		/* 0x06 */
+	u16 rwtcsrb0;	/* 0x08 */
+	u16 dummy2;		/* 0x0A */
+};
+
+/* HPB Semaphore Control Registers */
+struct r8a7740_hpb {
+	u32 hpbctrl0;
+	u32 hpbctrl1;
+	u32 hpbctrl2;
+	u32 cccr;
+	u32 dummy0; /* 0x20 */
+	u32 hpbctrl4;
+	u32 hpbctrl5;
+};
+
+/* CPG */
+struct r8a7740_cpg {
+	u32 frqcra;
+	u32 frqcrb;
+	u32 vclkcr1;
+	u32 vclkcr2;
+	u32 fmsickcr;
+	u32 fmsockcr;
+	u32 fsiackcr;
+	u32 dummy0; /* 0x1c */
+	u32 rtstbcr;
+	u32 systbcr;
+	u32 pllc01cr;
+	u32 pllc2cr;
+	u32 mstpsr0;
+	u32 dummy1; /* 0x34 */
+	u32 mstpsr1;
+	u32 mstpsr5;
+	u32 mstpsr2;
+	u32 dummy2; /* 0x44 */
+	u32 mstpsr3;
+	u32 mstpsr4;
+	u32 dummy3; /* 0x50 */
+	u32 astat;
+	u32 dummy4[4]; /* 0x58 .. 0x64 */
+	u32 ztrckcr;
+	u32 dummy5[5]; /* 0x6c .. 0x7c */
+	u32 subckcr;
+	u32 spuckcr;
+	u32 vouckcr;
+	u32 usbckcr;
+	u32 dummy6[3]; /* 0x90 .. 0x98 */
+	u32 stprckcr;
+	u32 srcr0;
+	u32 dummy7; /* 0xa4 */
+	u32 srcr1;
+	u32 dummy8; /* 0xac */
+	u32 srcr2;
+	u32 dummy9; /* 0xb4 */
+	u32 srcr3;
+	u32 srcr4;
+	u32 dummy10; /* 0xc0 */
+	u32 srcr5;
+	u32 pllc01stpcr;
+	u32 dummy11[5]; /* 0xcc .. 0xdc */
+	u32 frqcrc;
+	u32 frqcrd;
+	u32 dummy12[10]; /* 0xe8 .. 0x10c */
+	u32 rmstpcr0;
+	u32 rmstpcr1;
+	u32 rmstpcr2;
+	u32 rmstpcr3;
+	u32 rmstpcr4;
+	u32 rmstpcr5;
+	u32 dummy13[2]; /* 0x128 .. 0x12c */
+	u32 smstpcr0;
+	u32 smstpcr1;
+	u32 smstpcr2;
+	u32 smstpcr3;
+	u32 smstpcr4;
+	u32 smstpcr5;
+};
+
+/* BSC */
+struct r8a7740_bsc {
+	u32 cmncr;
+	u32 cs0bcr;
+	u32 cs2bcr;
+	u32 dummy0; /* 0x0c */
+	u32 cs4bcr;
+	u32 cs5abcr;
+	u32 cs5bbcr;
+	u32 cs6abcr;
+	u32 dummy1; /* 0x20 */
+	u32 cs0wcr;
+	u32 cs2wcr;
+	u32 dummy2; /* 0x2c */
+	u32 cs4wcr;
+	u32 cs5awcr;
+	u32 cs5bwcr;
+	u32 cs6awcr;
+	u32 dummy3[5]; /* 0x40 .. 0x50 */
+	u32 rbwtcnt;
+	u32 busycr;
+	u32 dummy4[5]; /* 0x5c .. 0x6c */
+	u32 bromtimcr;
+	u32 dummy5[7]; /* 0x74 .. 0x8c */
+	u32 bptcr00;
+	u32 bptcr01;
+	u32 bptcr02;
+	u32 bptcr03;
+	u32 bptcr04;
+	u32 bptcr05;
+	u32 bptcr06;
+	u32 bptcr07;
+	u32 bptcr08;
+	u32 bptcr09;
+	u32 bptcr10;
+	u32 bptcr11;
+	u32 bptcr12;
+	u32 bptcr13;
+	u32 bptcr14;
+	u32 bptcr15;
+	u32 bptcr16;
+	u32 bptcr17;
+	u32 bptcr18;
+	u32 bptcr19;
+	u32 bptcr20;
+	u32 bptcr21;
+	u32 bptcr22;
+	u32 bptcr23;
+	u32 bptcr24;
+	u32 bptcr25;
+	u32 bptcr26;
+	u32 bptcr27;
+	u32 bptcr28;
+	u32 bptcr29;
+	u32 bptcr30;
+	u32 bptcr31;
+	u32 bswcr;
+	u32 dummy6[68]; /* 0x114 .. 0x220 */
+	u32 cs0wcr2;
+	u32 cs2wcr2;
+	u32 dummy7; /* 0x22c */
+	u32 cs4wcr2;
+};
+
+#define CS0WCR2 0xFEC10224
+#define CS2WCR2 0xFEC10228
+#define CS4WCR2 0xFEC10230
+
+/* DDRP */
+struct r8a7740_ddrp {
+	u32 funcctrl;
+	u32 dllctrl;
+	u32 zqcalctrl;
+	u32 zqodtctrl;
+	u32 rdctrl;
+	u32 rdtmg;
+	u32 fifoinit;
+	u32 outctrl;
+	u32 dummy0[50]; /* 0x20 .. 0xe4 */
+	u32 dqcalofs1;
+	u32 dqcalofs2;
+	u32 dummy1[2]; /* 0xf0 .. 0xf4 */
+	u32 dqcalexp;
+};
+
+#define DDRPNCNT 0xE605803C
+#define DDRVREFCNT 0xE61500EC
+
+/* DBSC */
+struct r8a7740_dbsc {
+	u32 dummy0;
+	u32 dbsvcr;
+	u32 dbstate0;
+	u32 dbstate1;
+	u32 dbacen;
+	u32 dbrfen;
+	u32 dbcmd;
+	u32 dbwait;
+	u32 dbkind;
+	u32 dbconf0;
+	u32 dummy1[2]; /* 0x28 .. 0x2c */
+	u32 dbphytype;
+	u32 dummy2[3]; /* 0x34 .. 0x3c */
+	u32 dbtr0;
+	u32 dbtr1;
+	u32 dbtr2;
+	u32 dummy3; /* 0x4c */
+	u32 dbtr3;
+	u32 dbtr4;
+	u32 dbtr5;
+	u32 dbtr6;
+	u32 dbtr7;
+	u32 dbtr8;
+	u32 dbtr9;
+	u32 dbtr10;
+	u32 dbtr11;
+	u32 dbtr12;
+	u32 dbtr13;
+	u32 dbtr14;
+	u32 dbtr15;
+	u32 dbtr16;
+	u32 dbtr17;
+	u32 dbtr18;
+	u32 dbtr19;
+	u32 dummy4[7]; /* 0x94 .. 0xac */
+	u32 dbbl;
+	u32 dummy5[3]; /* 0xb4 .. 0xbc */
+	u32 dbadj0;
+	u32 dbadj1;
+	u32 dbadj2;
+	u32 dummy6[5]; /* 0xcc .. 0xdc */
+	u32 dbrfcnf0;
+	u32 dbrfcnf1;
+	u32 dbrfcnf2;
+	u32 dbrfcnf3;
+	u32 dummy7; /* 0xf0 */
+	u32 dbcalcnf;
+	u32 dbcaltr;
+	u32 dummy8; /* 0xfc */;
+	u32 dbrnk0;
+	u32 dummy9[31]; /* 0x104 .. 0x17C */
+	u32 dbpdncnf;
+	u32 dummy10[7]; /* 0x184 .. 0x19C */
+	u32 dbmrrdr;
+	u32 dummy11[39]; /* 0x1A4 .. 0x23C */
+	u32 dbdfistat;
+	u32 dbdficnt;
+	u32 dummy12[46]; /* 0x248 .. 0x2FC */
+	u32 dbbs0cnt0;
+	u32 dbbs0cnt1;
+};
+
+#endif
+
+#endif /* __ASM_ARCH_R8A7740_H */

arch/arm/include/asm/arch-rmobile/rmobile.h

@@ -0,0 +1,14 @@
+#ifndef __ASM_ARCH_RMOBILE_H
+#define __ASM_ARCH_RMOBILE_H
+
+#if defined(CONFIG_RMOBILE)
+#if defined(CONFIG_SH73A0)
+#include <asm/arch/sh73a0.h>
+#elif defined(CONFIG_R8A7740)
+#include <asm/arch/r8a7740.h>
+#else
+#error "SOC Name not defined"
+#endif
+#endif /* CONFIG_RMOBILE */
+
+#endif /* __ASM_ARCH_RMOBILE_H */

arch/arm/include/asm/arch-rmobile/sh73a0-gpio.h

@@ -0,0 +1,553 @@
+#ifndef __ASM_SH73A0_H__
+#define __ASM_SH73A0_H__
+
+/* Pin Function Controller:
+ * GPIO_FN_xx - GPIO used to select pin function and MSEL switch
+ * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
+ */
+enum {
+	/* Hardware manual Table 25-1 (GPIO) */
+	GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
+	GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
+
+	GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
+	GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
+
+	GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
+	GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
+
+	GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
+	GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
+
+	GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44,
+	GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49,
+
+	GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54,
+	GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59,
+
+	GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64,
+	GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
+
+	GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
+	GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
+
+	GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
+	GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89,
+
+	GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94,
+	GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
+
+	GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
+	GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
+
+	GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
+	GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118,
+
+	GPIO_PORT128, GPIO_PORT129,
+
+	GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
+	GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139,
+
+	GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144,
+	GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149,
+
+	GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154,
+	GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159,
+
+	GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
+
+	GPIO_PORT192, GPIO_PORT193, GPIO_PORT194,
+	GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199,
+
+	GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204,
+	GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209,
+
+	GPIO_PORT210, GPIO_PORT211, GPIO_PORT212, GPIO_PORT213, GPIO_PORT214,
+	GPIO_PORT215, GPIO_PORT216, GPIO_PORT217, GPIO_PORT218, GPIO_PORT219,
+
+	GPIO_PORT220, GPIO_PORT221, GPIO_PORT222, GPIO_PORT223, GPIO_PORT224,
+	GPIO_PORT225, GPIO_PORT226, GPIO_PORT227, GPIO_PORT228, GPIO_PORT229,
+
+	GPIO_PORT230, GPIO_PORT231, GPIO_PORT232, GPIO_PORT233, GPIO_PORT234,
+	GPIO_PORT235, GPIO_PORT236, GPIO_PORT237, GPIO_PORT238, GPIO_PORT239,
+
+	GPIO_PORT240, GPIO_PORT241, GPIO_PORT242, GPIO_PORT243, GPIO_PORT244,
+	GPIO_PORT245, GPIO_PORT246, GPIO_PORT247, GPIO_PORT248, GPIO_PORT249,
+
+	GPIO_PORT250, GPIO_PORT251, GPIO_PORT252, GPIO_PORT253, GPIO_PORT254,
+	GPIO_PORT255, GPIO_PORT256, GPIO_PORT257, GPIO_PORT258, GPIO_PORT259,
+
+	GPIO_PORT260, GPIO_PORT261, GPIO_PORT262, GPIO_PORT263, GPIO_PORT264,
+	GPIO_PORT265, GPIO_PORT266, GPIO_PORT267, GPIO_PORT268, GPIO_PORT269,
+
+	GPIO_PORT270, GPIO_PORT271, GPIO_PORT272, GPIO_PORT273, GPIO_PORT274,
+	GPIO_PORT275, GPIO_PORT276, GPIO_PORT277, GPIO_PORT278, GPIO_PORT279,
+
+	GPIO_PORT280, GPIO_PORT281, GPIO_PORT282,
+
+	GPIO_PORT288, GPIO_PORT289,
+
+	GPIO_PORT290, GPIO_PORT291, GPIO_PORT292, GPIO_PORT293, GPIO_PORT294,
+	GPIO_PORT295, GPIO_PORT296, GPIO_PORT297, GPIO_PORT298, GPIO_PORT299,
+
+	GPIO_PORT300, GPIO_PORT301, GPIO_PORT302, GPIO_PORT303, GPIO_PORT304,
+	GPIO_PORT305, GPIO_PORT306, GPIO_PORT307, GPIO_PORT308, GPIO_PORT309,
+
+	/* Table 25-1 (Function 0-7) */
+	GPIO_FN_VBUS_0,
+	GPIO_FN_GPI0,
+	GPIO_FN_GPI1,
+	GPIO_FN_GPI2,
+	GPIO_FN_GPI3,
+	GPIO_FN_GPI4,
+	GPIO_FN_GPI5,
+	GPIO_FN_GPI6,
+	GPIO_FN_GPI7,
+	GPIO_FN_SCIFA7_RXD,
+	GPIO_FN_SCIFA7_CTS_,
+	GPIO_FN_GPO7, GPIO_FN_MFG0_OUT2,
+	GPIO_FN_GPO6, GPIO_FN_MFG1_OUT2,
+	GPIO_FN_GPO5, GPIO_FN_SCIFA0_SCK, GPIO_FN_FSICOSLDT3, \
+	GPIO_FN_PORT16_VIO_CKOR,
+	GPIO_FN_SCIFA0_TXD,
+	GPIO_FN_SCIFA7_TXD,
+	GPIO_FN_SCIFA7_RTS_, GPIO_FN_PORT19_VIO_CKO2,
+	GPIO_FN_GPO0,
+	GPIO_FN_GPO1,
+	GPIO_FN_GPO2, GPIO_FN_STATUS0,
+	GPIO_FN_GPO3, GPIO_FN_STATUS1,
+	GPIO_FN_GPO4, GPIO_FN_STATUS2,
+	GPIO_FN_VINT,
+	GPIO_FN_TCKON,
+	GPIO_FN_XDVFS1, GPIO_FN_PORT27_I2C_SCL2, GPIO_FN_PORT27_I2C_SCL3, \
+	GPIO_FN_MFG0_OUT1, GPIO_FN_PORT27_IROUT,
+	GPIO_FN_XDVFS2, GPIO_FN_PORT28_I2C_SDA2, GPIO_FN_PORT28_I2C_SDA3, \
+	GPIO_FN_PORT28_TPU1TO1,
+	GPIO_FN_SIM_RST, GPIO_FN_PORT29_TPU1TO1,
+	GPIO_FN_SIM_CLK, GPIO_FN_PORT30_VIO_CKOR,
+	GPIO_FN_SIM_D, GPIO_FN_PORT31_IROUT,
+	GPIO_FN_SCIFA4_TXD,
+	GPIO_FN_SCIFA4_RXD, GPIO_FN_XWUP,
+	GPIO_FN_SCIFA4_RTS_,
+	GPIO_FN_SCIFA4_CTS_,
+	GPIO_FN_FSIBOBT, GPIO_FN_FSIBIBT,
+	GPIO_FN_FSIBOLR, GPIO_FN_FSIBILR,
+	GPIO_FN_FSIBOSLD,
+	GPIO_FN_FSIBISLD,
+	GPIO_FN_VACK,
+	GPIO_FN_XTAL1L,
+	GPIO_FN_SCIFA0_RTS_, GPIO_FN_FSICOSLDT2,
+	GPIO_FN_SCIFA0_RXD,
+	GPIO_FN_SCIFA0_CTS_, GPIO_FN_FSICOSLDT1,
+	GPIO_FN_FSICOBT, GPIO_FN_FSICIBT, GPIO_FN_FSIDOBT, GPIO_FN_FSIDIBT,
+	GPIO_FN_FSICOLR, GPIO_FN_FSICILR, GPIO_FN_FSIDOLR, GPIO_FN_FSIDILR,
+	GPIO_FN_FSICOSLD, GPIO_FN_PORT47_FSICSPDIF,
+	GPIO_FN_FSICISLD, GPIO_FN_FSIDISLD,
+	GPIO_FN_FSIACK, GPIO_FN_PORT49_IRDA_OUT, GPIO_FN_PORT49_IROUT, \
+	GPIO_FN_FSIAOMC,
+	GPIO_FN_FSIAOLR, GPIO_FN_BBIF2_TSYNC2, GPIO_FN_TPU2TO2, GPIO_FN_FSIAILR,
+
+	GPIO_FN_FSIAOBT, GPIO_FN_BBIF2_TSCK2, GPIO_FN_TPU2TO3, GPIO_FN_FSIAIBT,
+	GPIO_FN_FSIAOSLD, GPIO_FN_BBIF2_TXD2,
+	GPIO_FN_FSIASPDIF, GPIO_FN_PORT53_IRDA_IN, GPIO_FN_TPU3TO3, \
+	GPIO_FN_FSIBSPDIF, GPIO_FN_PORT53_FSICSPDIF,
+	GPIO_FN_FSIBCK, GPIO_FN_PORT54_IRDA_FIRSEL, GPIO_FN_TPU3TO2, \
+	GPIO_FN_FSIBOMC, GPIO_FN_FSICCK, GPIO_FN_FSICOMC,
+	GPIO_FN_FSIAISLD, GPIO_FN_TPU0TO0,
+	GPIO_FN_A0, GPIO_FN_BS_,
+	GPIO_FN_A12, GPIO_FN_PORT58_KEYOUT7, GPIO_FN_TPU4TO2,
+	GPIO_FN_A13, GPIO_FN_PORT59_KEYOUT6, GPIO_FN_TPU0TO1,
+	GPIO_FN_A14, GPIO_FN_KEYOUT5,
+	GPIO_FN_A15, GPIO_FN_KEYOUT4,
+	GPIO_FN_A16, GPIO_FN_KEYOUT3, GPIO_FN_MSIOF0_SS1,
+	GPIO_FN_A17, GPIO_FN_KEYOUT2, GPIO_FN_MSIOF0_TSYNC,
+	GPIO_FN_A18, GPIO_FN_KEYOUT1, GPIO_FN_MSIOF0_TSCK,
+	GPIO_FN_A19, GPIO_FN_KEYOUT0, GPIO_FN_MSIOF0_TXD,
+	GPIO_FN_A20, GPIO_FN_KEYIN0, GPIO_FN_MSIOF0_RSCK,
+	GPIO_FN_A21, GPIO_FN_KEYIN1, GPIO_FN_MSIOF0_RSYNC,
+	GPIO_FN_A22, GPIO_FN_KEYIN2, GPIO_FN_MSIOF0_MCK0,
+	GPIO_FN_A23, GPIO_FN_KEYIN3, GPIO_FN_MSIOF0_MCK1,
+	GPIO_FN_A24, GPIO_FN_KEYIN4, GPIO_FN_MSIOF0_RXD,
+	GPIO_FN_A25, GPIO_FN_KEYIN5, GPIO_FN_MSIOF0_SS2,
+	GPIO_FN_A26, GPIO_FN_KEYIN6,
+	GPIO_FN_KEYIN7,
+	GPIO_FN_D0_NAF0,
+	GPIO_FN_D1_NAF1,
+	GPIO_FN_D2_NAF2,
+	GPIO_FN_D3_NAF3,
+	GPIO_FN_D4_NAF4,
+	GPIO_FN_D5_NAF5,
+	GPIO_FN_D6_NAF6,
+	GPIO_FN_D7_NAF7,
+	GPIO_FN_D8_NAF8,
+	GPIO_FN_D9_NAF9,
+	GPIO_FN_D10_NAF10,
+	GPIO_FN_D11_NAF11,
+	GPIO_FN_D12_NAF12,
+	GPIO_FN_D13_NAF13,
+	GPIO_FN_D14_NAF14,
+	GPIO_FN_D15_NAF15,
+	GPIO_FN_CS4_,
+	GPIO_FN_CS5A_, GPIO_FN_PORT91_RDWR,
+	GPIO_FN_CS5B_, GPIO_FN_FCE1_,
+	GPIO_FN_CS6B_, GPIO_FN_DACK0,
+	GPIO_FN_FCE0_, GPIO_FN_CS6A_,
+	GPIO_FN_WAIT_, GPIO_FN_DREQ0,
+	GPIO_FN_RD__FSC,
+	GPIO_FN_WE0__FWE, GPIO_FN_RDWR_FWE,
+	GPIO_FN_WE1_,
+	GPIO_FN_FRB,
+	GPIO_FN_CKO,
+	GPIO_FN_NBRSTOUT_,
+	GPIO_FN_NBRST_,
+	GPIO_FN_BBIF2_TXD,
+	GPIO_FN_BBIF2_RXD,
+	GPIO_FN_BBIF2_SYNC,
+	GPIO_FN_BBIF2_SCK,
+	GPIO_FN_SCIFA3_CTS_, GPIO_FN_MFG3_IN2,
+	GPIO_FN_SCIFA3_RXD, GPIO_FN_MFG3_IN1,
+	GPIO_FN_BBIF1_SS2, GPIO_FN_SCIFA3_RTS_, GPIO_FN_MFG3_OUT1,
+	GPIO_FN_SCIFA3_TXD,
+	GPIO_FN_HSI_RX_DATA, GPIO_FN_BBIF1_RXD,
+	GPIO_FN_HSI_TX_WAKE, GPIO_FN_BBIF1_TSCK,
+	GPIO_FN_HSI_TX_DATA, GPIO_FN_BBIF1_TSYNC,
+	GPIO_FN_HSI_TX_READY, GPIO_FN_BBIF1_TXD,
+	GPIO_FN_HSI_RX_READY, GPIO_FN_BBIF1_RSCK, GPIO_FN_PORT115_I2C_SCL2, \
+	GPIO_FN_PORT115_I2C_SCL3,
+	GPIO_FN_HSI_RX_WAKE, GPIO_FN_BBIF1_RSYNC, GPIO_FN_PORT116_I2C_SDA2, \
+	GPIO_FN_PORT116_I2C_SDA3,
+	GPIO_FN_HSI_RX_FLAG, GPIO_FN_BBIF1_SS1, GPIO_FN_BBIF1_FLOW,
+	GPIO_FN_HSI_TX_FLAG,
+	GPIO_FN_VIO_VD, GPIO_FN_PORT128_LCD2VSYN, GPIO_FN_VIO2_VD, \
+	GPIO_FN_LCD2D0,
+
+	GPIO_FN_VIO_HD, GPIO_FN_PORT129_LCD2HSYN, GPIO_FN_PORT129_LCD2CS_, \
+	GPIO_FN_VIO2_HD, GPIO_FN_LCD2D1,
+	GPIO_FN_VIO_D0, GPIO_FN_PORT130_MSIOF2_RXD, GPIO_FN_LCD2D10,
+	GPIO_FN_VIO_D1, GPIO_FN_PORT131_KEYOUT6, GPIO_FN_PORT131_MSIOF2_SS1, \
+	GPIO_FN_PORT131_KEYOUT11, GPIO_FN_LCD2D11,
+	GPIO_FN_VIO_D2, GPIO_FN_PORT132_KEYOUT7, GPIO_FN_PORT132_MSIOF2_SS2, \
+	GPIO_FN_PORT132_KEYOUT10, GPIO_FN_LCD2D12,
+	GPIO_FN_VIO_D3, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_LCD2D13,
+	GPIO_FN_VIO_D4, GPIO_FN_MSIOF2_TXD, GPIO_FN_LCD2D14,
+	GPIO_FN_VIO_D5, GPIO_FN_MSIOF2_TSCK, GPIO_FN_LCD2D15,
+	GPIO_FN_VIO_D6, GPIO_FN_PORT136_KEYOUT8, GPIO_FN_LCD2D16,
+	GPIO_FN_VIO_D7, GPIO_FN_PORT137_KEYOUT9, GPIO_FN_LCD2D17,
+	GPIO_FN_VIO_D8, GPIO_FN_PORT138_KEYOUT8, GPIO_FN_VIO2_D0, \
+	GPIO_FN_LCD2D6,
+	GPIO_FN_VIO_D9, GPIO_FN_PORT139_KEYOUT9, GPIO_FN_VIO2_D1, \
+	GPIO_FN_LCD2D7,
+	GPIO_FN_VIO_D10, GPIO_FN_TPU0TO2, GPIO_FN_VIO2_D2, GPIO_FN_LCD2D8,
+	GPIO_FN_VIO_D11, GPIO_FN_TPU0TO3, GPIO_FN_VIO2_D3, GPIO_FN_LCD2D9,
+	GPIO_FN_VIO_D12, GPIO_FN_PORT142_KEYOUT10, GPIO_FN_VIO2_D4, \
+	GPIO_FN_LCD2D2,
+	GPIO_FN_VIO_D13, GPIO_FN_PORT143_KEYOUT11, GPIO_FN_PORT143_KEYOUT6, \
+	GPIO_FN_VIO2_D5, GPIO_FN_LCD2D3,
+	GPIO_FN_VIO_D14, GPIO_FN_PORT144_KEYOUT7, GPIO_FN_VIO2_D6, \
+	GPIO_FN_LCD2D4,
+	GPIO_FN_VIO_D15, GPIO_FN_TPU1TO3, GPIO_FN_PORT145_LCD2DISP, \
+	GPIO_FN_PORT145_LCD2RS, GPIO_FN_VIO2_D7, GPIO_FN_LCD2D5,
+	GPIO_FN_VIO_CLK, GPIO_FN_LCD2DCK, GPIO_FN_PORT146_LCD2WR_, \
+	GPIO_FN_VIO2_CLK, GPIO_FN_LCD2D18,
+	GPIO_FN_VIO_FIELD, GPIO_FN_LCD2RD_, GPIO_FN_VIO2_FIELD, GPIO_FN_LCD2D19,
+	GPIO_FN_VIO_CKO,
+	GPIO_FN_A27, GPIO_FN_PORT149_RDWR, GPIO_FN_MFG0_IN1, \
+	GPIO_FN_PORT149_KEYOUT9,
+	GPIO_FN_MFG0_IN2,
+	GPIO_FN_TS_SPSYNC3, GPIO_FN_MSIOF2_RSCK,
+	GPIO_FN_TS_SDAT3, GPIO_FN_MSIOF2_RSYNC,
+	GPIO_FN_TPU1TO2, GPIO_FN_TS_SDEN3, GPIO_FN_PORT153_MSIOF2_SS1,
+	GPIO_FN_SCIFA2_TXD1, GPIO_FN_MSIOF2_MCK0,
+	GPIO_FN_SCIFA2_RXD1, GPIO_FN_MSIOF2_MCK1,
+	GPIO_FN_SCIFA2_RTS1_, GPIO_FN_PORT156_MSIOF2_SS2,
+	GPIO_FN_SCIFA2_CTS1_, GPIO_FN_PORT157_MSIOF2_RXD,
+	GPIO_FN_DINT_, GPIO_FN_SCIFA2_SCK1, GPIO_FN_TS_SCK3,
+	GPIO_FN_PORT159_SCIFB_SCK, GPIO_FN_PORT159_SCIFA5_SCK, GPIO_FN_NMI,
+	GPIO_FN_PORT160_SCIFB_TXD, GPIO_FN_PORT160_SCIFA5_TXD,
+	GPIO_FN_PORT161_SCIFB_CTS_, GPIO_FN_PORT161_SCIFA5_CTS_,
+	GPIO_FN_PORT162_SCIFB_RXD, GPIO_FN_PORT162_SCIFA5_RXD,
+	GPIO_FN_PORT163_SCIFB_RTS_, GPIO_FN_PORT163_SCIFA5_RTS_, \
+	GPIO_FN_TPU3TO0,
+	GPIO_FN_LCDD0,
+	GPIO_FN_LCDD1, GPIO_FN_PORT193_SCIFA5_CTS_, GPIO_FN_BBIF2_TSYNC1,
+	GPIO_FN_LCDD2, GPIO_FN_PORT194_SCIFA5_RTS_, GPIO_FN_BBIF2_TSCK1,
+	GPIO_FN_LCDD3, GPIO_FN_PORT195_SCIFA5_RXD, GPIO_FN_BBIF2_TXD1,
+	GPIO_FN_LCDD4, GPIO_FN_PORT196_SCIFA5_TXD,
+	GPIO_FN_LCDD5, GPIO_FN_PORT197_SCIFA5_SCK, GPIO_FN_MFG2_OUT2, \
+	GPIO_FN_TPU2TO1,
+	GPIO_FN_LCDD6,
+	GPIO_FN_LCDD7, GPIO_FN_TPU4TO1, GPIO_FN_MFG4_OUT2,
+	GPIO_FN_LCDD8, GPIO_FN_D16,
+	GPIO_FN_LCDD9, GPIO_FN_D17,
+	GPIO_FN_LCDD10, GPIO_FN_D18,
+	GPIO_FN_LCDD11, GPIO_FN_D19,
+	GPIO_FN_LCDD12, GPIO_FN_D20,
+	GPIO_FN_LCDD13, GPIO_FN_D21,
+	GPIO_FN_LCDD14, GPIO_FN_D22,
+	GPIO_FN_LCDD15, GPIO_FN_PORT207_MSIOF0L_SS1, GPIO_FN_D23,
+	GPIO_FN_LCDD16, GPIO_FN_PORT208_MSIOF0L_SS2, GPIO_FN_D24,
+	GPIO_FN_LCDD17, GPIO_FN_D25,
+	GPIO_FN_LCDD18, GPIO_FN_DREQ2, GPIO_FN_PORT210_MSIOF0L_SS1, GPIO_FN_D26,
+	GPIO_FN_LCDD19, GPIO_FN_PORT211_MSIOF0L_SS2, GPIO_FN_D27,
+	GPIO_FN_LCDD20, GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0, GPIO_FN_D28,
+	GPIO_FN_LCDD21, GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1, GPIO_FN_D29,
+	GPIO_FN_LCDD22, GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_RSCK, GPIO_FN_D30,
+	GPIO_FN_LCDD23, GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_RSYNC, GPIO_FN_D31,
+	GPIO_FN_LCDDCK, GPIO_FN_LCDWR_,
+	GPIO_FN_LCDRD_, GPIO_FN_DACK2, GPIO_FN_PORT217_LCD2RS, \
+	GPIO_FN_MSIOF0L_TSYNC, GPIO_FN_VIO2_FIELD3, GPIO_FN_PORT217_LCD2DISP,
+	GPIO_FN_LCDHSYN, GPIO_FN_LCDCS_, GPIO_FN_LCDCS2_, GPIO_FN_DACK3, \
+	GPIO_FN_PORT218_VIO_CKOR,
+	GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_PORT219_LCD2WR_, \
+	GPIO_FN_DREQ3, GPIO_FN_MSIOF0L_TSCK, GPIO_FN_VIO2_CLK3, \
+	GPIO_FN_LCD2DCK_2,
+	GPIO_FN_LCDVSYN, GPIO_FN_LCDVSYN2,
+	GPIO_FN_LCDLCLK, GPIO_FN_DREQ1, GPIO_FN_PORT221_LCD2CS_, \
+	GPIO_FN_PWEN, GPIO_FN_MSIOF0L_RXD, GPIO_FN_VIO2_HD3, \
+	GPIO_FN_PORT221_LCD2HSYN,
+	GPIO_FN_LCDDON, GPIO_FN_LCDDON2, GPIO_FN_DACK1, GPIO_FN_OVCN, \
+	GPIO_FN_MSIOF0L_TXD, GPIO_FN_VIO2_VD3, GPIO_FN_PORT222_LCD2VSYN,
+
+	GPIO_FN_SCIFA1_TXD, GPIO_FN_OVCN2,
+	GPIO_FN_EXTLP, GPIO_FN_SCIFA1_SCK, GPIO_FN_PORT226_VIO_CKO2,
+	GPIO_FN_SCIFA1_RTS_, GPIO_FN_IDIN,
+	GPIO_FN_SCIFA1_RXD,
+	GPIO_FN_SCIFA1_CTS_, GPIO_FN_MFG1_IN1,
+	GPIO_FN_MSIOF1_TXD, GPIO_FN_SCIFA2_TXD2,
+	GPIO_FN_MSIOF1_TSYNC, GPIO_FN_SCIFA2_CTS2_,
+	GPIO_FN_MSIOF1_TSCK, GPIO_FN_SCIFA2_SCK2,
+	GPIO_FN_MSIOF1_RXD, GPIO_FN_SCIFA2_RXD2,
+	GPIO_FN_MSIOF1_RSCK, GPIO_FN_SCIFA2_RTS2_, GPIO_FN_VIO2_CLK2, \
+	GPIO_FN_LCD2D20,
+	GPIO_FN_MSIOF1_RSYNC, GPIO_FN_MFG1_IN2, GPIO_FN_VIO2_VD2, \
+	GPIO_FN_LCD2D21,
+	GPIO_FN_MSIOF1_MCK0, GPIO_FN_PORT236_I2C_SDA2,
+	GPIO_FN_MSIOF1_MCK1, GPIO_FN_PORT237_I2C_SCL2,
+	GPIO_FN_MSIOF1_SS1, GPIO_FN_VIO2_FIELD2, GPIO_FN_LCD2D22,
+	GPIO_FN_MSIOF1_SS2, GPIO_FN_VIO2_HD2, GPIO_FN_LCD2D23,
+	GPIO_FN_SCIFA6_TXD,
+	GPIO_FN_PORT241_IRDA_OUT, GPIO_FN_PORT241_IROUT, GPIO_FN_MFG4_OUT1, \
+	GPIO_FN_TPU4TO0,
+	GPIO_FN_PORT242_IRDA_IN, GPIO_FN_MFG4_IN2,
+	GPIO_FN_PORT243_IRDA_FIRSEL, GPIO_FN_PORT243_VIO_CKO2,
+	GPIO_FN_PORT244_SCIFA5_CTS_, GPIO_FN_MFG2_IN1, \
+	GPIO_FN_PORT244_SCIFB_CTS_, GPIO_FN_MSIOF2R_RXD,
+	GPIO_FN_PORT245_SCIFA5_RTS_, GPIO_FN_MFG2_IN2, \
+	GPIO_FN_PORT245_SCIFB_RTS_, GPIO_FN_MSIOF2R_TXD,
+	GPIO_FN_PORT246_SCIFA5_RXD, GPIO_FN_MFG1_OUT1, \
+	GPIO_FN_PORT246_SCIFB_RXD, GPIO_FN_TPU1TO0,
+	GPIO_FN_PORT247_SCIFA5_TXD, GPIO_FN_MFG3_OUT2, \
+	GPIO_FN_PORT247_SCIFB_TXD, GPIO_FN_TPU3TO1,
+	GPIO_FN_PORT248_SCIFA5_SCK, GPIO_FN_MFG2_OUT1, \
+	GPIO_FN_PORT248_SCIFB_SCK, GPIO_FN_TPU2TO0, \
+	GPIO_FN_PORT248_I2C_SCL3, GPIO_FN_MSIOF2R_TSCK,
+	GPIO_FN_PORT249_IROUT, GPIO_FN_MFG4_IN1, \
+	GPIO_FN_PORT249_I2C_SDA3, GPIO_FN_MSIOF2R_TSYNC,
+	GPIO_FN_SDHICLK0,
+	GPIO_FN_SDHICD0,
+	GPIO_FN_SDHID0_0,
+	GPIO_FN_SDHID0_1,
+	GPIO_FN_SDHID0_2,
+	GPIO_FN_SDHID0_3,
+	GPIO_FN_SDHICMD0,
+	GPIO_FN_SDHIWP0,
+	GPIO_FN_SDHICLK1,
+	GPIO_FN_SDHID1_0, GPIO_FN_TS_SPSYNC2,
+	GPIO_FN_SDHID1_1, GPIO_FN_TS_SDAT2,
+	GPIO_FN_SDHID1_2, GPIO_FN_TS_SDEN2,
+	GPIO_FN_SDHID1_3, GPIO_FN_TS_SCK2,
+	GPIO_FN_SDHICMD1,
+	GPIO_FN_SDHICLK2,
+	GPIO_FN_SDHID2_0, GPIO_FN_TS_SPSYNC4,
+	GPIO_FN_SDHID2_1, GPIO_FN_TS_SDAT4,
+	GPIO_FN_SDHID2_2, GPIO_FN_TS_SDEN4,
+	GPIO_FN_SDHID2_3, GPIO_FN_TS_SCK4,
+	GPIO_FN_SDHICMD2,
+	GPIO_FN_MMCCLK0,
+	GPIO_FN_MMCD0_0,
+	GPIO_FN_MMCD0_1,
+	GPIO_FN_MMCD0_2,
+	GPIO_FN_MMCD0_3,
+	GPIO_FN_MMCD0_4, GPIO_FN_TS_SPSYNC5,
+	GPIO_FN_MMCD0_5, GPIO_FN_TS_SDAT5,
+	GPIO_FN_MMCD0_6, GPIO_FN_TS_SDEN5,
+	GPIO_FN_MMCD0_7, GPIO_FN_TS_SCK5,
+	GPIO_FN_MMCCMD0,
+	GPIO_FN_RESETOUTS_, GPIO_FN_EXTAL2OUT,
+	GPIO_FN_MCP_WAIT__MCP_FRB,
+	GPIO_FN_MCP_CKO, GPIO_FN_MMCCLK1,
+	GPIO_FN_MCP_D15_MCP_NAF15,
+	GPIO_FN_MCP_D14_MCP_NAF14,
+	GPIO_FN_MCP_D13_MCP_NAF13,
+	GPIO_FN_MCP_D12_MCP_NAF12,
+	GPIO_FN_MCP_D11_MCP_NAF11,
+	GPIO_FN_MCP_D10_MCP_NAF10,
+	GPIO_FN_MCP_D9_MCP_NAF9,
+	GPIO_FN_MCP_D8_MCP_NAF8, GPIO_FN_MMCCMD1,
+	GPIO_FN_MCP_D7_MCP_NAF7, GPIO_FN_MMCD1_7,
+
+	GPIO_FN_MCP_D6_MCP_NAF6, GPIO_FN_MMCD1_6,
+	GPIO_FN_MCP_D5_MCP_NAF5, GPIO_FN_MMCD1_5,
+	GPIO_FN_MCP_D4_MCP_NAF4, GPIO_FN_MMCD1_4,
+	GPIO_FN_MCP_D3_MCP_NAF3, GPIO_FN_MMCD1_3,
+	GPIO_FN_MCP_D2_MCP_NAF2, GPIO_FN_MMCD1_2,
+	GPIO_FN_MCP_D1_MCP_NAF1, GPIO_FN_MMCD1_1,
+	GPIO_FN_MCP_D0_MCP_NAF0, GPIO_FN_MMCD1_0,
+	GPIO_FN_MCP_NBRSTOUT_,
+	GPIO_FN_MCP_WE0__MCP_FWE, GPIO_FN_MCP_RDWR_MCP_FWE,
+
+	/* MSEL2 special case */
+	GPIO_FN_TSIF2_TS_XX1,
+	GPIO_FN_TSIF2_TS_XX2,
+	GPIO_FN_TSIF2_TS_XX3,
+	GPIO_FN_TSIF2_TS_XX4,
+	GPIO_FN_TSIF2_TS_XX5,
+	GPIO_FN_TSIF1_TS_XX1,
+	GPIO_FN_TSIF1_TS_XX2,
+	GPIO_FN_TSIF1_TS_XX3,
+	GPIO_FN_TSIF1_TS_XX4,
+	GPIO_FN_TSIF1_TS_XX5,
+	GPIO_FN_TSIF0_TS_XX1,
+	GPIO_FN_TSIF0_TS_XX2,
+	GPIO_FN_TSIF0_TS_XX3,
+	GPIO_FN_TSIF0_TS_XX4,
+	GPIO_FN_TSIF0_TS_XX5,
+	GPIO_FN_MST1_TS_XX1,
+	GPIO_FN_MST1_TS_XX2,
+	GPIO_FN_MST1_TS_XX3,
+	GPIO_FN_MST1_TS_XX4,
+	GPIO_FN_MST1_TS_XX5,
+	GPIO_FN_MST0_TS_XX1,
+	GPIO_FN_MST0_TS_XX2,
+	GPIO_FN_MST0_TS_XX3,
+	GPIO_FN_MST0_TS_XX4,
+	GPIO_FN_MST0_TS_XX5,
+
+	/* MSEL3 special cases */
+	GPIO_FN_SDHI0_VCCQ_MC0_ON,
+	GPIO_FN_SDHI0_VCCQ_MC0_OFF,
+	GPIO_FN_DEBUG_MON_VIO,
+	GPIO_FN_DEBUG_MON_LCDD,
+	GPIO_FN_LCDC_LCDC0,
+	GPIO_FN_LCDC_LCDC1,
+
+	/* MSEL4 special cases */
+	GPIO_FN_IRQ9_MEM_INT,
+	GPIO_FN_IRQ9_MCP_INT,
+	GPIO_FN_A11,
+	GPIO_FN_KEYOUT8,
+	GPIO_FN_TPU4TO3,
+	GPIO_FN_RESETA_N_PU_ON,
+	GPIO_FN_RESETA_N_PU_OFF,
+	GPIO_FN_EDBGREQ_PD,
+	GPIO_FN_EDBGREQ_PU,
+
+	/* Functions with pull-ups */
+	GPIO_FN_KEYIN0_PU,
+	GPIO_FN_KEYIN1_PU,
+	GPIO_FN_KEYIN2_PU,
+	GPIO_FN_KEYIN3_PU,
+	GPIO_FN_KEYIN4_PU,
+	GPIO_FN_KEYIN5_PU,
+	GPIO_FN_KEYIN6_PU,
+	GPIO_FN_KEYIN7_PU,
+	GPIO_FN_SDHICD0_PU,
+	GPIO_FN_SDHID0_0_PU,
+	GPIO_FN_SDHID0_1_PU,
+	GPIO_FN_SDHID0_2_PU,
+	GPIO_FN_SDHID0_3_PU,
+	GPIO_FN_SDHICMD0_PU,
+	GPIO_FN_SDHIWP0_PU,
+	GPIO_FN_SDHID1_0_PU,
+	GPIO_FN_SDHID1_1_PU,
+	GPIO_FN_SDHID1_2_PU,
+	GPIO_FN_SDHID1_3_PU,
+	GPIO_FN_SDHICMD1_PU,
+	GPIO_FN_SDHID2_0_PU,
+	GPIO_FN_SDHID2_1_PU,
+	GPIO_FN_SDHID2_2_PU,
+	GPIO_FN_SDHID2_3_PU,
+	GPIO_FN_SDHICMD2_PU,
+	GPIO_FN_MMCCMD0_PU,
+	GPIO_FN_MMCCMD1_PU,
+	GPIO_FN_MMCD0_0_PU,
+	GPIO_FN_MMCD0_1_PU,
+	GPIO_FN_MMCD0_2_PU,
+	GPIO_FN_MMCD0_3_PU,
+	GPIO_FN_MMCD0_4_PU,
+	GPIO_FN_MMCD0_5_PU,
+	GPIO_FN_MMCD0_6_PU,
+	GPIO_FN_MMCD0_7_PU,
+	GPIO_FN_FSIACK_PU,
+	GPIO_FN_FSIAILR_PU,
+	GPIO_FN_FSIAIBT_PU,
+	GPIO_FN_FSIAISLD_PU,
+
+	/* end of GPIO */
+	GPIO_NR,
+};
+
+/* DMA slave IDs */
+enum {
+	SHDMA_SLAVE_INVALID,
+	SHDMA_SLAVE_SCIF0_TX,
+	SHDMA_SLAVE_SCIF0_RX,
+	SHDMA_SLAVE_SCIF1_TX,
+	SHDMA_SLAVE_SCIF1_RX,
+	SHDMA_SLAVE_SCIF2_TX,
+	SHDMA_SLAVE_SCIF2_RX,
+	SHDMA_SLAVE_SCIF3_TX,
+	SHDMA_SLAVE_SCIF3_RX,
+	SHDMA_SLAVE_SCIF4_TX,
+	SHDMA_SLAVE_SCIF4_RX,
+	SHDMA_SLAVE_SCIF5_TX,
+	SHDMA_SLAVE_SCIF5_RX,
+	SHDMA_SLAVE_SCIF6_TX,
+	SHDMA_SLAVE_SCIF6_RX,
+	SHDMA_SLAVE_SCIF7_TX,
+	SHDMA_SLAVE_SCIF7_RX,
+	SHDMA_SLAVE_SCIF8_TX,
+	SHDMA_SLAVE_SCIF8_RX,
+	SHDMA_SLAVE_SDHI0_TX,
+	SHDMA_SLAVE_SDHI0_RX,
+	SHDMA_SLAVE_SDHI1_TX,
+	SHDMA_SLAVE_SDHI1_RX,
+	SHDMA_SLAVE_SDHI2_TX,
+	SHDMA_SLAVE_SDHI2_RX,
+	SHDMA_SLAVE_MMCIF_TX,
+	SHDMA_SLAVE_MMCIF_RX,
+};
+
+/*
+ *		SH73A0 IRQ LOCATION TABLE
+ *
+ * 416	-----------------------------------------
+ *		IRQ0-IRQ15
+ * 431	-----------------------------------------
+ * ...
+ * 448	-----------------------------------------
+ *		sh73a0-intcs
+ *		sh73a0-intca-irq-pins
+ * 680	-----------------------------------------
+ * ...
+ * 700	-----------------------------------------
+ *		sh73a0-pint0
+ * 731	-----------------------------------------
+ * 732	-----------------------------------------
+ *		sh73a0-pint1
+ * 739	-----------------------------------------
+ * ...
+ * 800	-----------------------------------------
+ *		IRQ16-IRQ31
+ * 815	-----------------------------------------
+ * ...
+ * 928	-----------------------------------------
+ *		sh73a0-intca-irq-pins
+ * 943	-----------------------------------------
+ */
+
+/* PINT interrupts are located at Linux IRQ 700 and up */
+#define SH73A0_PINT0_IRQ(irq) ((irq) + 700)
+#define SH73A0_PINT1_IRQ(irq) ((irq) + 732)
+
+#endif /* __ASM_SH73A0_H__ */

arch/arm/include/asm/arch-rmobile/sh73a0.h

@@ -0,0 +1,289 @@
+#ifndef __ASM_ARCH_RMOBILE_SH73A0_H
+#define __ASM_ARCH_RMOBILE_SH73A0_H
+
+/* Global Timer */
+#define GLOBAL_TIMER_BASE_ADDR	(0xF0000200)
+#define MERAM_BASE	(0xE5580000)
+
+/* GIC */
+#define GIC_BASE	(0xF0000100)
+#define ICCICR	GIC_BASE
+
+/* Secure control register */
+#define LIFEC_SEC_SRC	(0xE6110008)
+
+/* RWDT */
+#define	RWDT_BASE   (0xE6020000)
+
+/* HPB Semaphore Control Registers */
+#define HPB_BASE	(0xE6001010)
+
+/* Bus Semaphore Control Registers */
+#define HPBSCR_BASE (0xE6001600)
+
+/* SBSC1 */
+#define SBSC1_BASE	(0xFE400000)
+#define	SDMRA1A		(SBSC1_BASE + 0x100000)
+#define	SDMRA2A		(SBSC1_BASE + 0x1C0000)
+#define	SDMRA3A		(SBSC1_BASE + 0x104000)
+
+/* SBSC2 */
+#define SBSC2_BASE	(0xFB400000)
+#define	SDMRA1B		(SBSC2_BASE + 0x100000)
+#define	SDMRA2B		(SBSC2_BASE + 0x1C0000)
+#define	SDMRA3B		(SBSC2_BASE + 0x104000)
+
+/* CPG */
+#define CPG_BASE   (0xE6150000)
+#define	CPG_SRCR_BASE	(CPG_BASE + 0x80A0)
+#define WUPCR	(CPG_BASE + 0x1010)
+#define SRESCR	(CPG_BASE + 0x1018)
+#define PCLKCR	(CPG_BASE + 0x1020)
+
+/* SYSC */
+#define SYSC_BASE   (0xE6180000)
+#define RESCNT2	(SYSC_BASE + 0x8020)
+
+/* BSC */
+#define BSC_BASE (0xFEC10000)
+
+/* SCIF */
+#define SCIF0_BASE	(0xE6C40000)
+#define SCIF1_BASE	(0xE6C50000)
+#define SCIF2_BASE	(0xE6C60000)
+#define SCIF3_BASE	(0xE6C70000)
+#define SCIF4_BASE	(0xE6C80000)
+#define SCIF5_BASE	(0xE6CB0000)
+#define SCIF6_BASE	(0xE6CC0000)
+#define SCIF7_BASE	(0xE6CD0000)
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+
+/* RWDT */
+struct sh73a0_rwdt {
+	u16 rwtcnt0;	/* 0x00 */
+	u16 dummy0;	/* 0x02 */
+	u16 rwtcsra0;	/* 0x04 */
+	u16 dummy1;	/* 0x06 */
+	u16 rwtcsrb0;	/* 0x08 */
+};
+
+/* HPB Semaphore Control Registers */
+struct sh73a0_hpb {
+	u32 hpbctrl0;
+	u32 hpbctrl1;
+	u32 hpbctrl2;
+	u32 cccr;
+	u32 dummy0; /* 0x20 */
+	u32 hpbctrl4;
+	u32 hpbctrl5;
+	u32 dummy1; /* 0x2C */
+	u32 hpbctrl6;
+};
+
+/* Bus Semaphore Control Registers */
+struct sh73a0_hpb_bscr {
+	u32 mpsrc; /* 0x00 */
+	u32 mpacctl; /* 0x04 */
+	u32 dummy0[6];
+	u32 smgpiosrc; /* 0x20 */
+	u32 smgpioerr;
+	u32 smgpiotime;
+	u32 smgpiocnt;
+	u32 dummy1[4]; /* 0x30 .. 0x3C */
+	u32 smcmt2src;
+	u32 smcmt2err;
+	u32 smcmt2time;
+	u32 smcmt2cnt;
+	u32 smcpgsrc;
+	u32 smcpgerr;
+	u32 smcpgtime;
+	u32 smcpgcnt;
+	u32 dummy2[4]; /* 0x60 - 0x6C */
+	u32 smsyscsrc;
+	u32 smsyscerr;
+	u32 smsysctime;
+	u32 smsysccnt;
+};
+
+/* SBSC */
+struct sh73a0_sbsc {
+	u32 dummy0[2]; /* 0x00, 0x04 */
+	u32 sdcr0;
+	u32 sdcr1;
+	u32 sdpcr;
+	u32 dummy1; /* 0x14 */
+	u32 sdcr0s;
+	u32 sdcr1s;
+	u32 rtcsr;
+	u32 dummy2; /* 0x24 */
+	u32 rtcor;
+	u32 rtcorh;
+	u32 rtcors;
+	u32 rtcorsh;
+	u32 dummy3[2]; /* 0x38, 0x3C */
+	u32 sdwcrc0;
+	u32 sdwcrc1;
+	u32 sdwcr00;
+	u32 sdwcr01;
+	u32 sdwcr10;
+	u32 sdwcr11;
+	u32 sdpdcr0;
+	u32 dummy4; /* 0x5C */
+	u32 sdwcr2;
+	u32 sdwcrc2;
+	u32 zqccr;
+	u32 dummy5[6]; /* 0x6C .. 0x80 */
+	u32 sdmracr0;
+	u32 dummy6; /* 0x88 */
+	u32 sdmrtmpcr;
+	u32 dummy7; /* 0x90 */
+	u32 sdmrtmpmsk;
+	u32 dummy8; /* 0x98 */
+	u32 sdgencnt;
+	u32 dphycnt0;
+	u32 dphycnt1;
+	u32 dphycnt2;
+	u32 dummy9[2]; /* 0xAC .. 0xB0 */
+	u32 sddrvcr0;
+	u32 dummy10[14]; /* 0xB8 .. 0xEC */
+	u32 dptdivcr0;
+	u32 dptdivcr1;
+	u32 dptdivcr2;
+	u32 dummy11; /* 0xFC */
+	u32 sdptcr0;
+	u32 sdptcr1;
+	u32 sdptcr2;
+	u32 sdptcr3; /* 0x10C */
+	u32 dummy12[145]; /* 0x110 .. 0x350 */
+	u32 dllcnt0; /* 0x354 */
+	u32 sbscmon0;
+};
+
+/* CPG */
+struct sh73a0_sbsc_cpg {
+	u32 frqcra; /* 0x00 */
+	u32 frqcrb;
+	u32 vclkcr1;
+	u32 vclkcr2;
+	u32 zbckcr;
+	u32 flckcr;
+	u32 fsiackcr;
+	u32 vclkcr3;
+	u32 rtstbcr;
+	u32 systbcr;
+	u32 pll1cr;
+	u32 pll2cr;
+	u32 mstpsr0;
+	u32 dummy0; /* 0x34 */
+	u32 mstpsr1;
+	u32 mstpsr5;
+	u32 mstpsr2;
+	u32 dummy1; /* 0x44 */
+	u32 mstpsr3;
+	u32 mstpsr4;
+	u32 dummy2; /* 0x50 */
+	u32 astat;
+	u32 dvfscr0;
+	u32 dvfscr1;
+	u32 dsitckcr;
+	u32 dsi0pckcr;
+	u32 dsi1pckcr;
+	u32 dsi0phycr;
+	u32 dsi1phycr;
+	u32 sd0ckcr;
+	u32 sd1ckcr;
+	u32 sd2ckcr;
+	u32 subckcr;
+	u32 spuackcr;
+	u32 msuckcr;
+	u32 hsickcr;
+	u32 fsibckcr;
+	u32 spuvckcr;
+	u32 mfck1cr;
+	u32 mfck2cr;
+	u32 dummy3[8]; /* 0xA0 .. 0xBC */
+	u32 ckscr;
+	u32 dummy4; /* 0xC4 */
+	u32 pll1stpcr;
+	u32 mpmode;
+	u32 pllecr;
+	u32 dummy5; /* 0xD4 */
+	u32 pll0cr;
+	u32 pll3cr;
+	u32 dummy6; /* 0xE0 */
+	u32 frqcrd;
+	u32 dummyi7; /* 0xE8 */
+	u32 vrefcr;
+	u32 pll0stpcr;
+	u32 dummy8; /* 0xF4 */
+	u32 pll2stpcr;
+	u32 pll3stpcr;
+	u32 dummy9[4]; /* 0x100 .. 0x10c */
+	u32 rmstpcr0;
+	u32 rmstpcr1;
+	u32 rmstpcr2;
+	u32 rmstpcr3;
+	u32 rmstpcr4;
+	u32 rmstpcr5;
+	u32 dummy10[2]; /* 0x128 .. 0x12c */
+	u32 smstpcr0;
+	u32 smstpcr1;
+	u32 smstpcr2;
+	u32 smstpcr3;
+	u32 smstpcr4;
+	u32 smstpcr5;
+	u32 dummy11[2]; /* 0x148 .. 0x14c */
+	u32 cpgxxcs4;
+	u32 dummy12[7]; /* 0x154 .. 0x16c */
+	u32 dvfscr2;
+	u32 dvfscr3;
+	u32 dvfscr4;
+	u32 dvfscr5; /* 0x17C */
+};
+
+/* CPG SRCR part OK */
+struct sh73a0_sbsc_cpg_srcr {
+	u32 srcr0;
+	u32 dummy0; /* 0xA4 */
+	u32 srcr1;
+	u32 dummy1; /* 0xAC */
+	u32 srcr2;
+	u32 dummy2; /* 0xB4 */
+	u32 srcr3;
+	u32 srcr4;
+	u32 dummy3; /* 0xC0 */
+	u32 srcr5;
+};
+
+/* BSC */
+struct sh73a0_bsc {
+	u32 cmncr;
+	u32 cs0bcr;
+	u32 cs2bcr;
+	u32 dummy0; /* 0x0C */
+	u32 cs4bcr;
+	u32 cs5abcr;
+	u32 cs5bbcr;
+	u32 cs6abcr;
+	u32 cs6bbcr;
+	u32 cs0wcr;
+	u32 cs2wcr;
+	u32 dummy1; /* 0x2C */
+	u32 cs4wcr;
+	u32 cs5awcr;
+	u32 cs5bwcr;
+	u32 cs6awcr;
+	u32 cs6bwcr;
+	u32 rbwtcnt;
+	u32 busycr;
+	u32 dummy2; /* 0x5c */
+	u32 cs7abcr;
+	u32 cs7awcr;
+	u32 dummy3[2]; /* 0x68, 0x6C */
+	u32 bromtimcr;
+};
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASM_ARCH_RMOBILE_SH73A0_H */

arch/arm/include/asm/arch-rmobile/sys_proto.h

@@ -0,0 +1,29 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+struct rmobile_sysinfo {
+	char *board_string;
+};
+extern const struct rmobile_sysinfo sysinfo;
+
+#endif

arch/arm/include/asm/arch-s3c24x0/gpio.h

@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) 2012.
+ *
+ * Gabriel Huau <contact@huau-gabriel.fr>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _S3C24X0_GPIO_H_
+#define _S3C24X0_GPIO_H_
+
+enum s3c2440_gpio {
+	GPA0,
+	GPA1,
+	GPA2,
+	GPA3,
+	GPA4,
+	GPA5,
+	GPA6,
+	GPA7,
+	GPA8,
+	GPA9,
+	GPA10,
+	GPA11,
+	GPA12,
+	GPA13,
+	GPA14,
+	GPA15,
+	GPA16,
+	GPA17,
+	GPA18,
+	GPA19,
+	GPA20,
+	GPA21,
+	GPA22,
+	GPA23,
+	GPA24,
+
+	GPB0 = 32,
+	GPB1,
+	GPB2,
+	GPB3,
+	GPB4,
+	GPB5,
+	GPB6,
+	GPB7,
+	GPB8,
+	GPB9,
+	GPB10,
+
+	GPC0 = 64,
+	GPC1,
+	GPC2,
+	GPC3,
+	GPC4,
+	GPC5,
+	GPC6,
+	GPC7,
+	GPC8,
+	GPC9,
+	GPC10,
+	GPC11,
+	GPC12,
+	GPC13,
+	GPC14,
+	GPC15,
+
+	GPD0 = 96,
+	GPD1,
+	GPD2,
+	GPD3,
+	GPD4,
+	GPD5,
+	GPD6,
+	GPD7,
+	GPD8,
+	GPD9,
+	GPD10,
+	GPD11,
+	GPD12,
+	GPD13,
+	GPD14,
+	GPD15,
+
+	GPE0 = 128,
+	GPE1,
+	GPE2,
+	GPE3,
+	GPE4,
+	GPE5,
+	GPE6,
+	GPE7,
+	GPE8,
+	GPE9,
+	GPE10,
+	GPE11,
+	GPE12,
+	GPE13,
+	GPE14,
+	GPE15,
+
+	GPF0 = 160,
+	GPF1,
+	GPF2,
+	GPF3,
+	GPF4,
+	GPF5,
+	GPF6,
+	GPF7,
+
+	GPG0 = 192,
+	GPG1,
+	GPG2,
+	GPG3,
+	GPG4,
+	GPG5,
+	GPG6,
+	GPG7,
+	GPG8,
+	GPG9,
+	GPG10,
+	GPG11,
+	GPG12,
+	GPG13,
+	GPG14,
+	GPG15,
+
+	GPH0 = 224,
+	GPH1,
+	GPH2,
+	GPH3,
+	GPH4,
+	GPH5,
+	GPH6,
+	GPH7,
+	GPH8,
+	GPH9,
+	GPH10,
+
+	GPJ0 = 256,
+	GPJ1,
+	GPJ2,
+	GPJ3,
+	GPJ4,
+	GPJ5,
+	GPJ6,
+	GPJ7,
+	GPJ8,
+	GPJ9,
+	GPJ10,
+	GPJ11,
+	GPJ12,
+};
+
+#endif

arch/arm/include/asm/arch-s3c24x0/iomux.h

@@ -0,0 +1,200 @@
+/*
+ * Copyright (c) 2012
+ *
+ * Gabriel Huau <contact@huau-gabriel.fr>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _S3C24X0_IOMUX_H_
+#define _S3C24X0_IOMUX_H_
+
+enum s3c2440_iomux_func {
+	/* PORT A */
+	IOMUXA_ADDR0	= 1,
+	IOMUXA_ADDR16	= (1 << 1),
+	IOMUXA_ADDR17	= (1 << 2),
+	IOMUXA_ADDR18	= (1 << 3),
+	IOMUXA_ADDR19	= (1 << 4),
+	IOMUXA_ADDR20	= (1 << 5),
+	IOMUXA_ADDR21	= (1 << 6),
+	IOMUXA_ADDR22	= (1 << 7),
+	IOMUXA_ADDR23	= (1 << 8),
+	IOMUXA_ADDR24	= (1 << 9),
+	IOMUXA_ADDR25	= (1 << 10),
+	IOMUXA_ADDR26	= (1 << 11),
+	IOMUXA_nGCS1	= (1 << 12),
+	IOMUXA_nGCS2	= (1 << 13),
+	IOMUXA_nGCS3	= (1 << 14),
+	IOMUXA_nGCS4	= (1 << 15),
+	IOMUXA_nGCS5	= (1 << 16),
+	IOMUXA_CLE	= (1 << 17),
+	IOMUXA_ALE	= (1 << 18),
+	IOMUXA_nFWE	= (1 << 19),
+	IOMUXA_nFRE	= (1 << 20),
+	IOMUXA_nRSTOUT	= (1 << 21),
+	IOMUXA_nFCE		= (1 << 22),
+
+	/* PORT B */
+	IOMUXB_nXDREQ0	= (2 << 20),
+	IOMUXB_nXDACK0	= (2 << 18),
+	IOMUXB_nXDREQ1	= (2 << 16),
+	IOMUXB_nXDACK1	= (2 << 14),
+	IOMUXB_nXBREQ	= (2 << 12),
+	IOMUXB_nXBACK	= (2 << 10),
+	IOMUXB_TCLK0	= (2 << 8),
+	IOMUXB_TOUT3	= (2 << 6),
+	IOMUXB_TOUT2	= (2 << 4),
+	IOMUXB_TOUT1	= (2 << 2),
+	IOMUXB_TOUT0	= 2,
+
+	/* PORT C */
+	IOMUXC_VS7	= (2 << 30),
+	IOMUXC_VS6	= (2 << 28),
+	IOMUXC_VS5	= (2 << 26),
+	IOMUXC_VS4	= (2 << 24),
+	IOMUXC_VS3	= (2 << 22),
+	IOMUXC_VS2	= (2 << 20),
+	IOMUXC_VS1	= (2 << 18),
+	IOMUXC_VS0	= (2 << 16),
+	IOMUXC_LCD_LPCREVB	= (2 << 14),
+	IOMUXC_LCD_LPCREV	= (2 << 12),
+	IOMUXC_LCD_LPCOE	= (2 << 10),
+	IOMUXC_VM		= (2 << 8),
+	IOMUXC_VFRAME	= (2 << 6),
+	IOMUXC_VLINE	= (2 << 4),
+	IOMUXC_VCLK		= (2 << 2),
+	IOMUXC_LEND		= 2,
+	IOMUXC_I2SSDI	= (3 << 8),
+
+	/* PORT D */
+	IOMUXD_VS23	= (2 << 30),
+	IOMUXD_VS22	= (2 << 28),
+	IOMUXD_VS21	= (2 << 26),
+	IOMUXD_VS20	= (2 << 24),
+	IOMUXD_VS19	= (2 << 22),
+	IOMUXD_VS18	= (2 << 20),
+	IOMUXD_VS17	= (2 << 18),
+	IOMUXD_VS16	= (2 << 16),
+	IOMUXD_VS15	= (2 << 14),
+	IOMUXD_VS14	= (2 << 12),
+	IOMUXD_VS13	= (2 << 10),
+	IOMUXD_VS12	= (2 << 8),
+	IOMUXD_VS11	= (2 << 6),
+	IOMUXD_VS10	= (2 << 4),
+	IOMUXD_VS9	= (2 << 2),
+	IOMUXD_VS8	= 2,
+	IOMUXD_nSS0	= (3 << 30),
+	IOMUXD_nSS1	= (3 << 28),
+	IOMUXD_SPICLK1	= (3 << 20),
+	IOMUXD_SPIMOSI1	= (3 << 18),
+	IOMUXD_SPIMISO1	= (3 << 16),
+
+	/* PORT E */
+	IOMUXE_IICSDA	= (2 << 30),
+	IOMUXE_IICSCL	= (2 << 28),
+	IOMUXE_SPICLK0	= (2 << 26),
+	IOMUXE_SPIMOSI0	= (2 << 24),
+	IOMUXE_SPIMISO0	= (2 << 22),
+	IOMUXE_SDDAT3	= (2 << 20),
+	IOMUXE_SDDAT2	= (2 << 18),
+	IOMUXE_SDDAT1	= (2 << 16),
+	IOMUXE_SDDAT0	= (2 << 14),
+	IOMUXE_SDCMD	= (2 << 12),
+	IOMUXE_SDCLK	= (2 << 10),
+	IOMUXE_I2SDO	= (2 << 8),
+	IOMUXE_I2SDI	= (2 << 6),
+	IOMUXE_CDCLK	= (2 << 4),
+	IOMUXE_I2SSCLK	= (2 << 2),
+	IOMUXE_I2SLRCK	= 2,
+	IOMUXE_AC_SDATA_OUT	= (3 << 8),
+	IOMUXE_AC_SDATA_IN	= (3 << 6),
+	IOMUXE_AC_nRESET	= (3 << 4),
+	IOMUXE_AC_BIT_CLK	= (3 << 2),
+	IOMUXE_AC_SYNC		= 3,
+
+	/* PORT F */
+	IOMUXF_EINT7	= (2 << 14),
+	IOMUXF_EINT6	= (2 << 12),
+	IOMUXF_EINT5	= (2 << 10),
+	IOMUXF_EINT4	= (2 << 8),
+	IOMUXF_EINT3	= (2 << 6),
+	IOMUXF_EINT2	= (2 << 4),
+	IOMUXF_EINT1	= (2 << 2),
+	IOMUXF_EINT0	= 2,
+
+	/* PORT G */
+	IOMUXG_EINT23	= (2 << 30),
+	IOMUXG_EINT22	= (2 << 28),
+	IOMUXG_EINT21	= (2 << 26),
+	IOMUXG_EINT20	= (2 << 24),
+	IOMUXG_EINT19	= (2 << 22),
+	IOMUXG_EINT18	= (2 << 20),
+	IOMUXG_EINT17	= (2 << 18),
+	IOMUXG_EINT16	= (2 << 16),
+	IOMUXG_EINT15	= (2 << 14),
+	IOMUXG_EINT14	= (2 << 12),
+	IOMUXG_EINT13	= (2 << 10),
+	IOMUXG_EINT12	= (2 << 8),
+	IOMUXG_EINT11	= (2 << 6),
+	IOMUXG_EINT10	= (2 << 4),
+	IOMUXG_EINT9	= (2 << 2),
+	IOMUXG_EINT8	= 2,
+	IOMUXG_TCLK1	= (3 << 22),
+	IOMUXG_nCTS1	= (3 << 20),
+	IOMUXG_nRTS1	= (3 << 18),
+	IOMUXG_SPICLK1	= (3 << 14),
+	IOMUXG_SPIMOSI1	= (3 << 12),
+	IOMUXG_SPIMISO1	= (3 << 10),
+	IOMUXG_LCD_PWRDN	= (3 << 8),
+	IOMUXG_nSS1			= (3 << 6),
+	IOMUXG_nSS0			= (3 << 4),
+
+	/* PORT H */
+	IOMUXH_CLKOUT1	= (2 << 20),
+	IOMUXH_CLKOUT0	= (2 << 18),
+	IOMUXH_UEXTCLK	= (2 << 16),
+	IOMUXH_RXD2		= (2 << 14),
+	IOMUXH_TXD2		= (2 << 12),
+	IOMUXH_RXD1		= (2 << 10),
+	IOMUXH_TXD1		= (2 << 8),
+	IOMUXH_RXD0		= (2 << 6),
+	IOMUXH_TXD0		= (2 << 4),
+	IOMUXH_nRTS0	= (2 << 2),
+	IOMUXH_nCTS0	= 2,
+	IOMUXH_nCTS1	= (3 << 14),
+	IOMUXH_nRTS1	= (3 << 12),
+
+	/* PORT J */
+	IOMUXJ_CAMRESET		= (2 << 24),
+	IOMUXJ_CAMCLKOUT	= (2 << 22),
+	IOMUXJ_CAMHREF		= (2 << 20),
+	IOMUXJ_CAMVSYNC		= (2 << 18),
+	IOMUXJ_CAMPCLK		= (2 << 16),
+	IOMUXJ_CAMDATA7		= (2 << 14),
+	IOMUXJ_CAMDATA6		= (2 << 12),
+	IOMUXJ_CAMDATA5		= (2 << 10),
+	IOMUXJ_CAMDATA4		= (2 << 8),
+	IOMUXJ_CAMDATA3		= (2 << 6),
+	IOMUXJ_CAMDATA2		= (2 << 4),
+	IOMUXJ_CAMDATA1		= (2 << 2),
+	IOMUXJ_CAMDATA0		= 2
+};
+
+#endif

arch/arm/include/asm/arch-socfpga/reset_manager.h

@@ -0,0 +1,37 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef	_RESET_MANAGER_H_
+#define	_RESET_MANAGER_H_
+
+void reset_cpu(ulong addr);
+void reset_deassert_peripherals_handoff(void);
+
+struct socfpga_reset_manager {
+	u32	padding1;
+	u32	ctrl;
+	u32	padding2;
+	u32	padding3;
+	u32	mpu_mod_reset;
+	u32	per_mod_reset;
+	u32	per2_mod_reset;
+	u32	brg_mod_reset;
+};
+
+#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
+
+#endif /* _RESET_MANAGER_H_ */

arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h

@@ -0,0 +1,27 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SOCFPGA_BASE_ADDRS_H_
+#define _SOCFPGA_BASE_ADDRS_H_
+
+#define SOCFPGA_L3REGS_ADDRESS 0xff800000
+#define SOCFPGA_UART0_ADDRESS 0xffc02000
+#define SOCFPGA_UART1_ADDRESS 0xffc03000
+#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000
+#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
+
+#endif /* _SOCFPGA_BASE_ADDRS_H_ */

arch/arm/include/asm/arch-socfpga/spl.h

@@ -0,0 +1,26 @@
+/*
+ *  Copyright (C) 2012 Pavel Machek <pavel@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SOCFPGA_SPL_H_
+#define _SOCFPGA_SPL_H_
+
+/* Symbols from linker script */
+extern char __malloc_start, __malloc_end, __stack_start;
+
+#define BOOT_DEVICE_RAM 1
+
+#endif

arch/arm/include/asm/arch-socfpga/timer.h

@@ -0,0 +1,29 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SOCFPGA_TIMER_H_
+#define _SOCFPGA_TIMER_H_
+
+struct socfpga_timer {
+	u32	load_val;
+	u32	curr_val;
+	u32	ctrl;
+	u32	eoi;
+	u32	int_stat;
+};
+
+#endif

arch/arm/include/asm/mach-types.h

@@ -1105,6 +1105,8 @@ extern unsigned int __machine_arch_type;
 #define MACH_TYPE_UBISYS_P9D_EVP       3493
 #define MACH_TYPE_ATDGP318             3494
 #define MACH_TYPE_OMAP5_SEVM           3777
+#define MACH_TYPE_ARMADILLO_800EVA     3863
+#define MACH_TYPE_KZM9G                4140
 
 #ifdef CONFIG_ARCH_EBSA110
 # ifdef machine_arch_type
@@ -14222,6 +14224,30 @@ extern unsigned int __machine_arch_type;
 # define machine_is_omap5_sevm()      (0)
 #endif
 
+#ifdef CONFIG_MACH_ARMADILLO800EVA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type __machine_arch_type
+# else
+#  define machine_arch_type MACH_TYPE_ARMADILLO800EVA
+# endif
+# define machine_is_armadillo800eva()	(machine_arch_type == MACH_TYPE_ARMADILLO800EVA)
+#else
+# define machine_is_armadillo800eva()	(0)
+#endif
+
+#ifdef CONFIG_MACH_KZM9G
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type __machine_arch_type
+# else
+#  define machine_arch_type MACH_TYPE_KZM9G
+# endif
+# define machine_is_kzm9g()	(machine_arch_type == MACH_TYPE_KZM9G)
+#else
+# define machine_is_kzm9g()	(0)
+#endif
+
 /*
  * These have not yet been registered
  */

arch/arm/include/asm/omap_common.h

@@ -34,83 +34,6 @@
 #define OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL	2
 #define OMAP_INIT_CONTEXT_UBOOT_AFTER_CH	3
 
-void preloader_console_init(void);
-
-/* Boot device */
-#ifdef CONFIG_OMAP54XX
-#define BOOT_DEVICE_NONE        0
-#define BOOT_DEVICE_XIP         1
-#define BOOT_DEVICE_XIPWAIT     2
-#define BOOT_DEVICE_NAND        3
-#define BOOT_DEVICE_ONE_NAND    4
-#define BOOT_DEVICE_MMC1        5
-#define BOOT_DEVICE_MMC2        6
-#define BOOT_DEVICE_MMC2_2	7
-#elif defined(CONFIG_OMAP44XX) /* OMAP4 */
-#define BOOT_DEVICE_NONE	0
-#define BOOT_DEVICE_XIP		1
-#define BOOT_DEVICE_XIPWAIT	2
-#define BOOT_DEVICE_NAND	3
-#define BOOT_DEVICE_ONE_NAND	4
-#define BOOT_DEVICE_MMC1	5
-#define BOOT_DEVICE_MMC2	6
-#define BOOT_DEVICE_MMC2_2	0xFF
-#elif defined(CONFIG_OMAP34XX)	/* OMAP3 */
-#define BOOT_DEVICE_NONE	0
-#define BOOT_DEVICE_XIP		1
-#define BOOT_DEVICE_NAND	2
-#define BOOT_DEVICE_ONE_NAND	3
-#define BOOT_DEVICE_MMC2	5 /*emmc*/
-#define BOOT_DEVICE_MMC1	6
-#define BOOT_DEVICE_XIPWAIT	7
-#define BOOT_DEVICE_MMC2_2      0xFF
-#elif defined(CONFIG_AM33XX)	/* AM33XX */
-#define BOOT_DEVICE_NAND	5
-#define BOOT_DEVICE_MMC1	8
-#define BOOT_DEVICE_MMC2	9 /* eMMC or daughter card */
-#define BOOT_DEVICE_UART	65
-#define BOOT_DEVICE_MMC2_2      0xFF
-#endif
-
-/* Boot type */
-#define	MMCSD_MODE_UNDEFINED	0
-#define MMCSD_MODE_RAW		1
-#define MMCSD_MODE_FAT		2
-#define NAND_MODE_HW_ECC	3
-
-struct spl_image_info {
-	const char *name;
-	u8 os;
-	u32 load_addr;
-	u32 entry_point;
-	u32 size;
-};
-
-extern struct spl_image_info spl_image;
-
-extern u32* boot_params_ptr;
-u32 omap_boot_device(void);
-u32 omap_boot_mode(void);
-
-/* SPL common function s*/
-void spl_parse_image_header(const struct image_header *header);
-void omap_rev_string(void);
-void spl_board_prepare_for_linux(void);
-int spl_start_uboot(void);
-
-/* NAND SPL functions */
-void spl_nand_load_image(void);
-
-/* MMC SPL functions */
-void spl_mmc_load_image(void);
-
-/* YMODEM SPL functions */
-void spl_ymodem_load_image(void);
-
-#ifdef CONFIG_SPL_BOARD_INIT
-void spl_board_init(void);
-#endif
-
 static inline u32 omap_revision(void)
 {
 	extern u32 *const omap_si_rev;

arch/arm/include/asm/spl.h

@@ -1,5 +1,6 @@
 /*
- * Copyright 2011 Freescale Semiconductor, Inc.
+ * (C) Copyright 2012
+ * Texas Instruments, <www.ti.com>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -19,30 +20,15 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
+#ifndef	_ASM_SPL_H_
+#define	_ASM_SPL_H_
 
-/*
- * P3060 QDS board configuration file
- */
-#define CONFIG_P3060QDS
-#define CONFIG_PHYS_64BIT
-#define CONFIG_PPC_P3060
-#define CONFIG_FSL_QIXIS
+/* Platform-specific defines */
+#include <asm/arch/spl.h>
 
-#define CONFIG_NAND_FSL_ELBC
+/* Linker symbols. */
+extern char __bss_start[], __bss_end__[];
 
-#define CONFIG_ICS307_REFCLK_HZ	25000000  /* ICS307 ref clk freq */
+extern gd_t gdata;
 
-#define CONFIG_SPI_FLASH_ATMEL
-#define CONFIG_SPI_FLASH_EON
-#define CONFIG_SPI_FLASH_SST
-
-#include "corenet_ds.h"
-
-#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
-#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
-#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
-#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
-
-/* There is a PCA9547 8-channel I2C-bus multiplexer on P3060QDS board */
-#define CONFIG_I2C_MUX
-#define CONFIG_I2C_MULTI_BUS
+#endif

arch/arm/lib/Makefile

@@ -44,6 +44,8 @@ COBJS-y	+= interrupts.o
 COBJS-y	+= reset.o
 SOBJS-$(CONFIG_USE_ARCH_MEMSET) += memset.o
 SOBJS-$(CONFIG_USE_ARCH_MEMCPY) += memcpy.o
+else
+COBJS-$(CONFIG_SPL_FRAMEWORK) += spl.o
 endif
 
 COBJS-y	+= cache.o

arch/arm/lib/bootm.c

@@ -69,8 +69,8 @@ void arch_lmb_reserve(struct lmb *lmb)
 	sp = get_sp();
 	debug("## Current stack ends at 0x%08lx ", sp);
 
-	/* adjust sp by 1K to be safe */
-	sp -= 1024;
+	/* adjust sp by 4K to be safe */
+	sp -= 4096;
 	lmb_reserve(lmb, sp,
 		    gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size - sp);
 }
@@ -258,6 +258,9 @@ static int create_fdt(bootm_headers_t *images)
 	fixup_memory_node(*of_flat_tree);
 	fdt_fixup_ethernet(*of_flat_tree);
 	fdt_initrd(*of_flat_tree, *initrd_start, *initrd_end, 1);
+#ifdef CONFIG_OF_BOARD_SETUP
+	ft_board_setup(*of_flat_tree, gd->bd);
+#endif
 
 	return 0;
 }

arch/arm/lib/spl.c

@@ -0,0 +1,72 @@
+/*
+ * (C) Copyright 2010-2012
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ * Tom Rini <trini@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <config.h>
+#include <spl.h>
+#include <image.h>
+#include <linux/compiler.h>
+
+/* Pointer to as well as the global data structure for SPL */
+DECLARE_GLOBAL_DATA_PTR;
+gd_t gdata __attribute__ ((section(".data")));
+
+/*
+ * In the context of SPL, board_init_f must ensure that any clocks/etc for
+ * DDR are enabled, ensure that the stack pointer is valid, clear the BSS
+ * and call board_init_f.  We provide this version by default but mark it
+ * as __weak to allow for platforms to do this in their own way if needed.
+ */
+void __weak board_init_f(ulong dummy)
+{
+	/* Set the stack pointer. */
+	asm volatile("mov sp, %0\n" : : "r"(CONFIG_SPL_STACK));
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end__ - __bss_start);
+
+	/* Set global data pointer. */
+	gd = &gdata;
+
+	board_init_r(NULL, 0);
+}
+
+/*
+ * This function jumps to an image with argument. Normally an FDT or ATAGS
+ * image.
+ * arg: Pointer to paramter image in RAM
+ */
+#ifdef CONFIG_SPL_OS_BOOT
+void __noreturn jump_to_image_linux(void *arg)
+{
+	debug("Entering kernel arg pointer: 0x%p\n", arg);
+	typedef void (*image_entry_arg_t)(int, int, void *)
+		__attribute__ ((noreturn));
+	image_entry_arg_t image_entry =
+		(image_entry_arg_t) spl_image.entry_point;
+	cleanup_before_linux();
+	image_entry(0, CONFIG_MACH_TYPE, arg);
+}
+#endif

arch/avr32/lib/board.c

@@ -250,7 +250,6 @@ void board_init_f(ulong board_type)
 
 void board_init_r(gd_t *new_gd, ulong dest_addr)
 {
-	extern void malloc_bin_reloc (void);
 #ifndef CONFIG_ENV_IS_NOWHERE
 	extern char * env_name_spec;
 #endif

arch/m68k/lib/board.c

@@ -389,7 +389,6 @@ void board_init_r (gd_t *id, ulong dest_addr)
 {
 	char *s;
 	bd_t *bd;
-	extern void malloc_bin_reloc (void);
 
 #ifndef CONFIG_ENV_IS_NOWHERE
 	extern char * env_name_spec;

arch/mips/lib/board.c

@@ -248,7 +248,6 @@ void board_init_r(gd_t *id, ulong dest_addr)
 #ifndef CONFIG_SYS_NO_FLASH
 	ulong size;
 #endif
-	extern void malloc_bin_reloc(void);
 #ifndef CONFIG_ENV_IS_NOWHERE
 	extern char *env_name_spec;
 #endif

arch/nds32/lib/board.c

@@ -306,8 +306,6 @@ void board_init_r(gd_t *id, ulong dest_addr)
 	bd_t *bd;
 	ulong malloc_start;
 
-	extern void malloc_bin_reloc(void);
-
 	gd = id;
 	bd = gd->bd;
 

arch/openrisc/include/asm/bitops.h

@@ -25,4 +25,8 @@
 #define PLATFORM_FFS
 #include <asm/bitops/ffs.h>
 
+#define hweight32(x) generic_hweight32(x)
+#define hweight16(x) generic_hweight16(x)
+#define hweight8(x) generic_hweight8(x)
+
 #endif /* __ASM_GENERIC_BITOPS_H */

arch/openrisc/lib/timer.c

@@ -86,6 +86,16 @@ void set_timer(ulong t)
 	timestamp = t;
 }
 
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+ulong get_tbclk(void)
+{
+	return CONFIG_SYS_HZ;
+}
+
 void __udelay(ulong usec)
 {
 	ulong elapsed = 0;

arch/powerpc/cpu/mpc85xx/Makefile

@@ -55,8 +55,6 @@ COBJS-$(CONFIG_P1011)	+= ddr-gen3.o
 COBJS-$(CONFIG_P1012)	+= ddr-gen3.o
 COBJS-$(CONFIG_P1013)	+= ddr-gen3.o
 COBJS-$(CONFIG_P1014)	+= ddr-gen3.o
-COBJS-$(CONFIG_P1015)	+= ddr-gen3.o
-COBJS-$(CONFIG_P1016)	+= ddr-gen3.o
 COBJS-$(CONFIG_P1020)	+= ddr-gen3.o
 COBJS-$(CONFIG_P1021)	+= ddr-gen3.o
 COBJS-$(CONFIG_P1022)	+= ddr-gen3.o
@@ -64,10 +62,8 @@ COBJS-$(CONFIG_P1024)	+= ddr-gen3.o
 COBJS-$(CONFIG_P1025)	+= ddr-gen3.o
 COBJS-$(CONFIG_P2010)	+= ddr-gen3.o
 COBJS-$(CONFIG_P2020)	+= ddr-gen3.o
-COBJS-$(CONFIG_PPC_P2040)	+= ddr-gen3.o
 COBJS-$(CONFIG_PPC_P2041)	+= ddr-gen3.o
 COBJS-$(CONFIG_PPC_P3041)	+= ddr-gen3.o
-COBJS-$(CONFIG_PPC_P3060)	+= ddr-gen3.o
 COBJS-$(CONFIG_PPC_P4080)	+= ddr-gen3.o
 COBJS-$(CONFIG_PPC_P5020)	+= ddr-gen3.o
 COBJS-$(CONFIG_BSC9131)		+= ddr-gen3.o
@@ -80,10 +76,8 @@ COBJS-$(CONFIG_PCI)	+= pci.o
 COBJS-$(CONFIG_SYS_DPAA_QBMAN) += portals.o
 
 # various SoC specific assignments
-COBJS-$(CONFIG_PPC_P2040) += p2041_ids.o
 COBJS-$(CONFIG_PPC_P2041) += p2041_ids.o
 COBJS-$(CONFIG_PPC_P3041) += p3041_ids.o
-COBJS-$(CONFIG_PPC_P3060) += p3060_ids.o
 COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o
 COBJS-$(CONFIG_PPC_P5020) += p5020_ids.o
 
@@ -103,8 +97,6 @@ COBJS-$(CONFIG_P1011)	+= p1021_serdes.o
 COBJS-$(CONFIG_P1012)	+= p1021_serdes.o
 COBJS-$(CONFIG_P1013)	+= p1022_serdes.o
 COBJS-$(CONFIG_P1014)	+= p1010_serdes.o
-COBJS-$(CONFIG_P1015)	+= p1021_serdes.o
-COBJS-$(CONFIG_P1016)	+= p1021_serdes.o
 COBJS-$(CONFIG_P1017)	+= p1023_serdes.o
 COBJS-$(CONFIG_P1020)	+= p1021_serdes.o
 COBJS-$(CONFIG_P1021)	+= p1021_serdes.o
@@ -114,10 +106,8 @@ COBJS-$(CONFIG_P1024)	+= p1021_serdes.o
 COBJS-$(CONFIG_P1025)	+= p1021_serdes.o
 COBJS-$(CONFIG_P2010)	+= p2020_serdes.o
 COBJS-$(CONFIG_P2020)	+= p2020_serdes.o
-COBJS-$(CONFIG_PPC_P2040) += p2041_serdes.o
 COBJS-$(CONFIG_PPC_P2041) += p2041_serdes.o
 COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o
-COBJS-$(CONFIG_PPC_P3060) += p3060_serdes.o
 COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o
 COBJS-$(CONFIG_PPC_P5020) += p5020_serdes.o
 

arch/powerpc/cpu/mpc85xx/cmd_errata.c

@@ -27,6 +27,9 @@
 
 static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
+#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
+	extern int enable_cpu_a011_workaround;
+#endif
 	__maybe_unused u32 svr = get_svr();
 
 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
@@ -56,8 +59,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	/*
 	 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
 	 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
+	 * The SVR has been checked by cpu_init_r().
 	 */
-	if (SVR_SOC_VER(svr) != SVR_P4080 || SVR_MAJ(svr) < 3)
+	if (enable_cpu_a011_workaround)
 		puts("Work-around for Erratum CPU-A011 enabled\n");
 #endif
 #if defined(CONFIG_SYS_FSL_ERRATUM_CPU_A003999)
@@ -119,6 +123,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
 	if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
 		puts("Work-around for Erratum NMG ETSEC129 enabled\n");
+#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A004510
+	puts("Work-around for Erratum A004510 enabled\n");
 #endif
 	return 0;
 }

arch/powerpc/cpu/mpc85xx/cpu.c

@@ -117,6 +117,9 @@ int checkcpu (void)
 	case PVR_VER_E5500:
 		puts("E5500");
 		break;
+	case PVR_VER_E6500:
+		puts("E6500");
+		break;
 	default:
 		puts("Unknown");
 		break;
@@ -427,10 +430,20 @@ static void dump_spd_ddr_reg(void)
 		case 0:
 			ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
 			break;
-#ifdef CONFIG_SYS_MPC85xx_DDR2_ADDR
+#if defined(CONFIG_SYS_MPC85xx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
 		case 1:
 			ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR;
 			break;
+#endif
+#if defined(CONFIG_SYS_MPC85xx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
+		case 2:
+			ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR3_ADDR;
+			break;
+#endif
+#if defined(CONFIG_SYS_MPC85xx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
+		case 3:
+			ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR4_ADDR;
+			break;
 #endif
 		default:
 			printf("%s unexpected controller number = %u\n",

arch/powerpc/cpu/mpc85xx/cpu_init.c

@@ -38,6 +38,7 @@
 #include <asm/fsl_law.h>
 #include <asm/fsl_serdes.h>
 #include <asm/fsl_srio.h>
+#include <hwconfig.h>
 #include <linux/compiler.h>
 #include "mp.h"
 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
@@ -311,11 +312,41 @@ int cpu_init_r(void)
 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
 	defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
 	/*
+	 * CPU22 and NMG_CPU_A011 share the same workaround.
 	 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
 	 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
-	 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
+	 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both
+	 * fixed in 2.0. NMG_CPU_A011 is activated by default and can
+	 * be disabled by hwconfig with syntax:
+	 *
+	 * fsl_cpu_a011:disable
 	 */
-	if (SVR_SOC_VER(svr) != SVR_P4080 || SVR_MAJ(svr) < 3) {
+	extern int enable_cpu_a011_workaround;
+#ifdef CONFIG_SYS_P4080_ERRATUM_CPU22
+	enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3);
+#else
+	char buffer[HWCONFIG_BUFFER_SIZE];
+	char *buf = NULL;
+	int n, res;
+
+	n = getenv_f("hwconfig", buffer, sizeof(buffer));
+	if (n > 0)
+		buf = buffer;
+
+	res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf);
+	if (res > 0)
+		enable_cpu_a011_workaround = 0;
+	else {
+		if (n >= HWCONFIG_BUFFER_SIZE) {
+			printf("fsl_cpu_a011 was not found. hwconfig variable "
+				"may be too long\n");
+		}
+		enable_cpu_a011_workaround =
+			(SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) ||
+			(SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2);
+	}
+#endif
+	if (enable_cpu_a011_workaround) {
 		flush_dcache();
 		mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
 		sync();
@@ -447,11 +478,18 @@ skip_l2:
 
 #ifdef CONFIG_SYS_SRIO
 	srio_init();
-#ifdef CONFIG_SRIOBOOT_MASTER
-	srio_boot_master();
-#ifdef CONFIG_SRIOBOOT_SLAVE_HOLDOFF
-	srio_boot_master_release_slave();
-#endif
+#ifdef CONFIG_FSL_CORENET
+	char *s = getenv("bootmaster");
+	if (s) {
+		if (!strcmp(s, "SRIO1")) {
+			srio_boot_master(1);
+			srio_boot_master_release_slave(1);
+		}
+		if (!strcmp(s, "SRIO2")) {
+			srio_boot_master(2);
+			srio_boot_master_release_slave(2);
+		}
+	}
 #endif
 #endif