Prepare v2013.01.01

Signed-off-by: Tom Rini <trini@ti.com>

Makefile

@@ -23,8 +23,8 @@
 
 VERSION = 2013
 PATCHLEVEL = 01
-SUBLEVEL =
-EXTRAVERSION = -rc3
+SUBLEVEL = 01
+EXTRAVERSION =
 ifneq "$(SUBLEVEL)" ""
 U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
 else
@@ -869,7 +869,7 @@ clobber:	tidy
 	@rm -f $(obj)nand_spl/{u-boot-nand_spl.lds,u-boot-spl,u-boot-spl.map}
 	@rm -f $(obj)spl/{u-boot-spl,u-boot-spl.bin,u-boot-spl.map}
 	@rm -f $(obj)spl/{u-boot-spl.lds,u-boot.lst}
-	@rm -f $(obj)MLO
+	@rm -f $(obj)MLO MLO.byteswap
 	@rm -f $(obj)SPL
 	@rm -f $(obj)tools/xway-swap-bytes
 	@rm -f $(obj)arch/powerpc/cpu/mpc824x/bedbug_603e.c

README

@@ -616,6 +616,14 @@ The following options need to be configured:
 		boot loader that has already initialized the UART.  Define this
 		variable to flush the UART at init time.
 
+		CONFIG_SYS_NS16550_BROKEN_TEMT
+
+		16550 UART set the Transmitter Empty (TEMT) Bit when all output
+		has finished and the transmitter is totally empty. U-Boot waits
+		for this bit to be set to initialize the serial console. On some
+		broken platforms this bit is not set in SPL making U-Boot to
+		hang while waiting for TEMT. Define this option to avoid it.
+
 
 - Console Interface:
 		Depending on board, define exactly one serial port
@@ -849,6 +857,7 @@ The following options need to be configured:
 		CONFIG_CMD_LOADS	  loads
 		CONFIG_CMD_MD5SUM	  print md5 message digest
 					  (requires CONFIG_CMD_MEMORY and CONFIG_MD5)
+		CONFIG_CMD_MEMINFO	* Display detailed memory information
 		CONFIG_CMD_MEMORY	  md, mm, nm, mw, cp, cmp, crc, base,
 					  loop, loopw, mtest
 		CONFIG_CMD_MISC		  Misc functions like sleep etc
@@ -2378,6 +2387,15 @@ CBFS (Coreboot Filesystem) support
 		run-time determined information about the hardware to the
 		environment.  These will be named board_name, board_rev.
 
+		CONFIG_DELAY_ENVIRONMENT
+
+		Normally the environment is loaded when the board is
+		intialised so that it is available to U-Boot. This inhibits
+		that so that the environment is not available until
+		explicitly loaded later by U-Boot code. With CONFIG_OF_CONTROL
+		this is instead controlled by the value of
+		/config/load-environment.
+
 - DataFlash Support:
 		CONFIG_HAS_DATAFLASH
 
@@ -2696,10 +2714,13 @@ FIT uImage format:
 		CONFIG_FB_ADDR
 
 		Define CONFIG_FB_ADDR if you want to use specific
-		address for frame buffer.
-		Then system will reserve the frame buffer address to
-		defined address instead of lcd_setmem (this function
-		grabs the memory for frame buffer by panel's size).
+		address for frame buffer.  This is typically the case
+		when using a graphics controller has separate video
+		memory.  U-Boot will then place the frame buffer at
+		the given address instead of dynamically reserving it
+		in system RAM by calling lcd_setmem(), which grabs
+		the memory for the frame buffer depending on the
+		configured panel size.
 
 		Please see board_init_f function.
 
@@ -3453,6 +3474,16 @@ use the "saveenv" command to store a valid environment.
 		space for already greatly restricted images, including but not
 		limited to NAND_SPL configurations.
 
+- CONFIG_DISPLAY_BOARDINFO
+		Display information about the board that U-Boot is running on
+		when U-Boot starts up. The board function checkboard() is called
+		to do this.
+
+- CONFIG_DISPLAY_BOARDINFO_LATE
+		Similar to the previous option, but display this information
+		later, once stdio is running and output goes to the LCD, if
+		present.
+
 Low Level (hardware related) configuration options:
 ---------------------------------------------------
 

arch/arm/cpu/arm1136/mx31/timer.c

@@ -161,42 +161,3 @@ ulong get_tbclk(void)
 {
 	return MXC_CLK32;
 }
-
-void reset_cpu(ulong addr)
-{
-	struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE;
-	wdog->wcr = WDOG_ENABLE;
-	while (1)
-		;
-}
-
-#ifdef CONFIG_HW_WATCHDOG
-void mxc_hw_watchdog_enable(void)
-{
-	struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE;
-	u16 secs;
-
-	/*
-	 * The timer watchdog can be set between
-	 * 0.5 and 128 Seconds. If not defined
-	 * in configuration file, sets 64 Seconds
-	 */
-#ifdef CONFIG_SYS_WD_TIMER_SECS
-	secs = (CONFIG_SYS_WD_TIMER_SECS << 1) & 0xFF;
-	if (!secs) secs = 1;
-#else
-	secs = 64;
-#endif
-	setbits_le16(&wdog->wcr, (secs << WDOG_WT_SHIFT) | WDOG_ENABLE
-							 | WDOG_WDZST);
-}
-
-
-void mxc_hw_watchdog_reset(void)
-{
-	struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE;
-
-	writew(0x5555, &wdog->wsr);
-	writew(0xAAAA, &wdog->wsr);
-}
-#endif

arch/arm/cpu/arm1136/mx35/generic.c

@@ -488,12 +488,6 @@ int get_clocks(void)
 	return 0;
 }
 
-void reset_cpu(ulong addr)
-{
-	struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
-	writew(4, &wdog->wcr);
-}
-
 #define RCSR_MEM_CTL_WEIM	0
 #define RCSR_MEM_CTL_NAND	1
 #define RCSR_MEM_CTL_ATA	2

arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c

@@ -193,6 +193,19 @@ void at91_spi1_hw_init(unsigned long cs_mask)
 }
 #endif
 
+#if defined(CONFIG_USB_OHCI_NEW) || defined(CONFIG_USB_EHCI)
+void at91_uhp_hw_init(void)
+{
+	/* Enable VBus on UHP ports */
+	at91_set_pio_output(AT91_PIO_PORTD, 18, 0); /* port A */
+	at91_set_pio_output(AT91_PIO_PORTD, 19, 0); /* port B */
+#if defined(CONFIG_USB_OHCI_NEW)
+	/* port C is OHCI only */
+	at91_set_pio_output(AT91_PIO_PORTD, 20, 0); /* port C */
+#endif
+}
+#endif
+
 #ifdef CONFIG_MACB
 void at91_macb_hw_init(void)
 {

arch/arm/cpu/arm926ejs/kirkwood/mpp.c

@@ -31,7 +31,7 @@ static u32 kirkwood_variant(void)
 #define MPP_CTRL(i)	(KW_MPP_BASE + (i* 4))
 #define MPP_NR_REGS	(1 + MPP_MAX/8)
 
-void kirkwood_mpp_conf(u32 *mpp_list, u32 *mpp_save)
+void kirkwood_mpp_conf(const u32 *mpp_list, u32 *mpp_save)
 {
 	u32 mpp_ctrl[MPP_NR_REGS];
 	unsigned int variant_mask;

arch/arm/cpu/armv7/exynos/clock.c

@@ -112,6 +112,36 @@ static unsigned long exynos4_get_pll_clk(int pllreg)
 	return exynos_get_pll_clk(pllreg, r, k);
 }
 
+/* exynos4x12: return pll clock frequency */
+static unsigned long exynos4x12_get_pll_clk(int pllreg)
+{
+	struct exynos4x12_clock *clk =
+		(struct exynos4x12_clock *)samsung_get_base_clock();
+	unsigned long r, k = 0;
+
+	switch (pllreg) {
+	case APLL:
+		r = readl(&clk->apll_con0);
+		break;
+	case MPLL:
+		r = readl(&clk->mpll_con0);
+		break;
+	case EPLL:
+		r = readl(&clk->epll_con0);
+		k = readl(&clk->epll_con1);
+		break;
+	case VPLL:
+		r = readl(&clk->vpll_con0);
+		k = readl(&clk->vpll_con1);
+		break;
+	default:
+		printf("Unsupported PLL (%d)\n", pllreg);
+		return 0;
+	}
+
+	return exynos_get_pll_clk(pllreg, r, k);
+}
+
 /* exynos5: return pll clock frequency */
 static unsigned long exynos5_get_pll_clk(int pllreg)
 {
@@ -193,6 +223,28 @@ static unsigned long exynos4_get_arm_clk(void)
 	return armclk;
 }
 
+/* exynos4x12: return ARM clock frequency */
+static unsigned long exynos4x12_get_arm_clk(void)
+{
+	struct exynos4x12_clock *clk =
+		(struct exynos4x12_clock *)samsung_get_base_clock();
+	unsigned long div;
+	unsigned long armclk;
+	unsigned int core_ratio;
+	unsigned int core2_ratio;
+
+	div = readl(&clk->div_cpu0);
+
+	/* CORE_RATIO: [2:0], CORE2_RATIO: [30:28] */
+	core_ratio = (div >> 0) & 0x7;
+	core2_ratio = (div >> 28) & 0x7;
+
+	armclk = get_pll_clk(APLL) / (core_ratio + 1);
+	armclk /= (core2_ratio + 1);
+
+	return armclk;
+}
+
 /* exynos5: return ARM clock frequency */
 static unsigned long exynos5_get_arm_clk(void)
 {
@@ -258,6 +310,20 @@ static unsigned long exynos4_get_pwm_clk(void)
 	return pclk;
 }
 
+/* exynos4x12: return pwm clock frequency */
+static unsigned long exynos4x12_get_pwm_clk(void)
+{
+	unsigned long pclk, sclk;
+	unsigned int ratio;
+
+	sclk = get_pll_clk(MPLL);
+	ratio = 8;
+
+	pclk = sclk / (ratio + 1);
+
+	return pclk;
+}
+
 /* exynos5: return pwm clock frequency */
 static unsigned long exynos5_get_pwm_clk(void)
 {
@@ -326,6 +392,51 @@ static unsigned long exynos4_get_uart_clk(int dev_index)
 	return uclk;
 }
 
+/* exynos4x12: return uart clock frequency */
+static unsigned long exynos4x12_get_uart_clk(int dev_index)
+{
+	struct exynos4x12_clock *clk =
+		(struct exynos4x12_clock *)samsung_get_base_clock();
+	unsigned long uclk, sclk;
+	unsigned int sel;
+	unsigned int ratio;
+
+	/*
+	 * CLK_SRC_PERIL0
+	 * UART0_SEL [3:0]
+	 * UART1_SEL [7:4]
+	 * UART2_SEL [8:11]
+	 * UART3_SEL [12:15]
+	 * UART4_SEL [16:19]
+	 */
+	sel = readl(&clk->src_peril0);
+	sel = (sel >> (dev_index << 2)) & 0xf;
+
+	if (sel == 0x6)
+		sclk = get_pll_clk(MPLL);
+	else if (sel == 0x7)
+		sclk = get_pll_clk(EPLL);
+	else if (sel == 0x8)
+		sclk = get_pll_clk(VPLL);
+	else
+		return 0;
+
+	/*
+	 * CLK_DIV_PERIL0
+	 * UART0_RATIO [3:0]
+	 * UART1_RATIO [7:4]
+	 * UART2_RATIO [8:11]
+	 * UART3_RATIO [12:15]
+	 * UART4_RATIO [16:19]
+	 */
+	ratio = readl(&clk->div_peril0);
+	ratio = (ratio >> (dev_index << 2)) & 0xf;
+
+	uclk = sclk / (ratio + 1);
+
+	return uclk;
+}
+
 /* exynos5: return uart clock frequency */
 static unsigned long exynos5_get_uart_clk(int dev_index)
 {
@@ -373,6 +484,100 @@ static unsigned long exynos5_get_uart_clk(int dev_index)
 	return uclk;
 }
 
+static unsigned long exynos4_get_mmc_clk(int dev_index)
+{
+	struct exynos4_clock *clk =
+		(struct exynos4_clock *)samsung_get_base_clock();
+	unsigned long uclk, sclk;
+	unsigned int sel, ratio, pre_ratio;
+	int shift;
+
+	sel = readl(&clk->src_fsys);
+	sel = (sel >> (dev_index << 2)) & 0xf;
+
+	if (sel == 0x6)
+		sclk = get_pll_clk(MPLL);
+	else if (sel == 0x7)
+		sclk = get_pll_clk(EPLL);
+	else if (sel == 0x8)
+		sclk = get_pll_clk(VPLL);
+	else
+		return 0;
+
+	switch (dev_index) {
+	case 0:
+	case 1:
+		ratio = readl(&clk->div_fsys1);
+		pre_ratio = readl(&clk->div_fsys1);
+		break;
+	case 2:
+	case 3:
+		ratio = readl(&clk->div_fsys2);
+		pre_ratio = readl(&clk->div_fsys2);
+		break;
+	case 4:
+		ratio = readl(&clk->div_fsys3);
+		pre_ratio = readl(&clk->div_fsys3);
+		break;
+	default:
+		return 0;
+	}
+
+	if (dev_index == 1 || dev_index == 3)
+		shift = 16;
+
+	ratio = (ratio >> shift) & 0xf;
+	pre_ratio = (pre_ratio >> (shift + 8)) & 0xff;
+	uclk = (sclk / (ratio + 1)) / (pre_ratio + 1);
+
+	return uclk;
+}
+
+static unsigned long exynos5_get_mmc_clk(int dev_index)
+{
+	struct exynos5_clock *clk =
+		(struct exynos5_clock *)samsung_get_base_clock();
+	unsigned long uclk, sclk;
+	unsigned int sel, ratio, pre_ratio;
+	int shift;
+
+	sel = readl(&clk->src_fsys);
+	sel = (sel >> (dev_index << 2)) & 0xf;
+
+	if (sel == 0x6)
+		sclk = get_pll_clk(MPLL);
+	else if (sel == 0x7)
+		sclk = get_pll_clk(EPLL);
+	else if (sel == 0x8)
+		sclk = get_pll_clk(VPLL);
+	else
+		return 0;
+
+	switch (dev_index) {
+	case 0:
+	case 1:
+		ratio = readl(&clk->div_fsys1);
+		pre_ratio = readl(&clk->div_fsys1);
+		break;
+	case 2:
+	case 3:
+		ratio = readl(&clk->div_fsys2);
+		pre_ratio = readl(&clk->div_fsys2);
+		break;
+	default:
+		return 0;
+	}
+
+	if (dev_index == 1 || dev_index == 3)
+		shift = 16;
+
+	ratio = (ratio >> shift) & 0xf;
+	pre_ratio = (pre_ratio >> (shift + 8)) & 0xff;
+	uclk = (sclk / (ratio + 1)) / (pre_ratio + 1);
+
+	return uclk;
+}
+
 /* exynos4: set the mmc clock */
 static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
 {
@@ -381,6 +586,38 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
 	unsigned int addr;
 	unsigned int val;
 
+	/*
+	 * CLK_DIV_FSYS1
+	 * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
+	 * CLK_DIV_FSYS2
+	 * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
+	 * CLK_DIV_FSYS3
+	 * MMC4_PRE_RATIO [15:8]
+	 */
+	if (dev_index < 2) {
+		addr = (unsigned int)&clk->div_fsys1;
+	}  else if (dev_index == 4) {
+		addr = (unsigned int)&clk->div_fsys3;
+		dev_index -= 4;
+	} else {
+		addr = (unsigned int)&clk->div_fsys2;
+		dev_index -= 2;
+	}
+
+	val = readl(addr);
+	val &= ~(0xff << ((dev_index << 4) + 8));
+	val |= (div & 0xff) << ((dev_index << 4) + 8);
+	writel(val, addr);
+}
+
+/* exynos4x12: set the mmc clock */
+static void exynos4x12_set_mmc_clk(int dev_index, unsigned int div)
+{
+	struct exynos4x12_clock *clk =
+		(struct exynos4x12_clock *)samsung_get_base_clock();
+	unsigned int addr;
+	unsigned int val;
+
 	/*
 	 * CLK_DIV_FSYS1
 	 * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
@@ -603,7 +840,7 @@ void exynos5_set_lcd_clk(void)
 	 */
 	cfg = readl(&clk->src_disp1_0);
 	cfg &= ~(0xf);
-	cfg |= 0x8;
+	cfg |= 0x6;
 	writel(cfg, &clk->src_disp1_0);
 
 	/*
@@ -940,16 +1177,22 @@ unsigned long get_pll_clk(int pllreg)
 {
 	if (cpu_is_exynos5())
 		return exynos5_get_pll_clk(pllreg);
-	else
+	else {
+		if (proid_is_exynos4412())
+			return exynos4x12_get_pll_clk(pllreg);
 		return exynos4_get_pll_clk(pllreg);
+	}
 }
 
 unsigned long get_arm_clk(void)
 {
 	if (cpu_is_exynos5())
 		return exynos5_get_arm_clk();
-	else
+	else {
+		if (proid_is_exynos4412())
+			return exynos4x12_get_arm_clk();
 		return exynos4_get_arm_clk();
+	}
 }
 
 unsigned long get_i2c_clk(void)
@@ -968,24 +1211,41 @@ unsigned long get_pwm_clk(void)
 {
 	if (cpu_is_exynos5())
 		return exynos5_get_pwm_clk();
-	else
+	else {
+		if (proid_is_exynos4412())
+			return exynos4x12_get_pwm_clk();
 		return exynos4_get_pwm_clk();
+	}
 }
 
 unsigned long get_uart_clk(int dev_index)
 {
 	if (cpu_is_exynos5())
 		return exynos5_get_uart_clk(dev_index);
-	else
+	else {
+		if (proid_is_exynos4412())
+			return exynos4x12_get_uart_clk(dev_index);
 		return exynos4_get_uart_clk(dev_index);
+	}
+}
+
+unsigned long get_mmc_clk(int dev_index)
+{
+	if (cpu_is_exynos5())
+		return exynos5_get_mmc_clk(dev_index);
+	else
+		return exynos4_get_mmc_clk(dev_index);
 }
 
 void set_mmc_clk(int dev_index, unsigned int div)
 {
 	if (cpu_is_exynos5())
 		exynos5_set_mmc_clk(dev_index, div);
-	else
+	else {
+		if (proid_is_exynos4412())
+			exynos4x12_set_mmc_clk(dev_index, div);
 		exynos4_set_mmc_clk(dev_index, div);
+	}
 }
 
 unsigned long get_lcd_clk(void)

arch/arm/cpu/armv7/exynos/pinmux.c

@@ -22,6 +22,7 @@
  */
 
 #include <common.h>
+#include <fdtdec.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch/sromc.h>
@@ -370,6 +371,43 @@ static void exynos4_i2c_config(int peripheral, int flags)
 	}
 }
 
+static int exynos4_mmc_config(int peripheral, int flags)
+{
+	struct exynos4_gpio_part2 *gpio2 =
+		(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
+	struct s5p_gpio_bank *bank, *bank_ext;
+	int i;
+
+	switch (peripheral) {
+	case PERIPH_ID_SDMMC0:
+		bank = &gpio2->k0;
+		bank_ext = &gpio2->k1;
+		break;
+	case PERIPH_ID_SDMMC2:
+		bank = &gpio2->k2;
+		bank_ext = &gpio2->k3;
+		break;
+	default:
+		return -1;
+	}
+	for (i = 0; i < 7; i++) {
+		if (i == 2)
+			continue;
+		s5p_gpio_cfg_pin(bank, i,  GPIO_FUNC(0x2));
+		s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
+		s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+	}
+	if (flags & PINMUX_FLAG_8BIT_MODE) {
+		for (i = 3; i < 7; i++) {
+			s5p_gpio_cfg_pin(bank_ext, i,  GPIO_FUNC(0x3));
+			s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_NONE);
+			s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
+		}
+	}
+
+	return 0;
+}
+
 static int exynos4_pinmux_config(int peripheral, int flags)
 {
 	switch (peripheral) {
@@ -383,6 +421,14 @@ static int exynos4_pinmux_config(int peripheral, int flags)
 	case PERIPH_ID_I2C7:
 		exynos4_i2c_config(peripheral, flags);
 		break;
+	case PERIPH_ID_SDMMC0:
+	case PERIPH_ID_SDMMC2:
+		return exynos4_mmc_config(peripheral, flags);
+	case PERIPH_ID_SDMMC1:
+	case PERIPH_ID_SDMMC3:
+	case PERIPH_ID_SDMMC4:
+		printf("SDMMC device %d not implemented\n", peripheral);
+		return -1;
 	default:
 		debug("%s: invalid peripheral %d", __func__, peripheral);
 		return -1;
@@ -402,3 +448,31 @@ int exynos_pinmux_config(int peripheral, int flags)
 		return -1;
 	}
 }
+
+#ifdef CONFIG_OF_CONTROL
+static int exynos5_pinmux_decode_periph_id(const void *blob, int node)
+{
+	int err;
+	u32 cell[3];
+
+	err = fdtdec_get_int_array(blob, node, "interrupts", cell,
+					ARRAY_SIZE(cell));
+	if (err)
+		return PERIPH_ID_NONE;
+
+	/* check for invalid peripheral id */
+	if ((PERIPH_ID_SDMMC4 > cell[1]) || (cell[1] < PERIPH_ID_UART0))
+		return cell[1];
+
+	debug(" invalid peripheral id\n");
+	return PERIPH_ID_NONE;
+}
+
+int pinmux_decode_periph_id(const void *blob, int node)
+{
+	if (cpu_is_exynos5())
+		return  exynos5_pinmux_decode_periph_id(blob, node);
+	else
+		return PERIPH_ID_NONE;
+}
+#endif

arch/arm/cpu/armv7/mx6/lowlevel_init.S

@@ -20,6 +20,16 @@
 
 #include <linux/linkage.h>
 
+.macro init_arm_errata
+	/* ARM erratum ID #743622 */
+	mrc	p15, 0, r10, c15, c0, 1		/* read diagnostic register */
+	orr	r10, r10, #1 << 6		/* set bit #6 */
+	/* ARM erratum ID #751472 */
+	orr	r10, r10, #1 << 11		/* set bit #11 */
+	mcr	p15, 0, r10, c15, c0, 1		/* write diagnostic register */
+.endm
+
 ENTRY(lowlevel_init)
+	init_arm_errata
 	mov pc, lr
 ENDPROC(lowlevel_init)

arch/arm/cpu/pxa/start.S

@@ -183,7 +183,9 @@ relocate_code:
 
 /* Disable the Dcache RAM lock for stack now */
 #ifdef	CONFIG_CPU_PXA25X
+	mov	r12, lr
 	bl	cpu_init_crit
+	mov	lr, r12
 #endif
 
 	adr	r0, _start

arch/arm/dts/exynos5250.dtsi

@@ -0,0 +1,154 @@
+/*
+ * SAMSUNG EXYNOS5250 SoC device tree source
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
+ * EXYNOS5250 based board files can include this file and provide
+ * values for board specfic bindings.
+ *
+ * Note: This file does not include device nodes for all the controllers in
+ * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
+ * additional nodes can be added to this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/include/ "skeleton.dtsi"
+
+/ {
+	compatible = "samsung,exynos5250";
+
+	sromc@12250000 {
+		compatible = "samsung,exynos-sromc";
+		reg = <0x12250000 0x20>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	i2c@12c60000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x12C60000 0x100>;
+		interrupts = <0 56 0>;
+	};
+
+	i2c@12c70000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x12C70000 0x100>;
+		interrupts = <0 57 0>;
+	};
+
+	i2c@12c80000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x12C80000 0x100>;
+		interrupts = <0 58 0>;
+	};
+
+	i2c@12c90000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x12C90000 0x100>;
+		interrupts = <0 59 0>;
+	};
+
+	i2c@12ca0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x12CA0000 0x100>;
+		interrupts = <0 60 0>;
+	};
+
+	i2c@12cb0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x12CB0000 0x100>;
+		interrupts = <0 61 0>;
+	};
+
+	i2c@12cc0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x12CC0000 0x100>;
+		interrupts = <0 62 0>;
+	};
+
+	i2c@12cd0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x12CD0000 0x100>;
+		interrupts = <0 63 0>;
+	};
+
+	sound@12d60000 {
+		compatible = "samsung,exynos-sound";
+		reg = <0x12d60000 0x20>;
+	};
+
+	spi@12d20000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos-spi";
+		reg = <0x12d20000 0x30>;
+		interrupts = <0 68 0>;
+	};
+
+	spi@12d30000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos-spi";
+		reg = <0x12d30000 0x30>;
+		interrupts = <0 69 0>;
+	};
+
+	spi@12d40000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos-spi";
+		reg = <0x12d40000 0x30>;
+		clock-frequency = <50000000>;
+		interrupts = <0 70 0>;
+        };
+
+	spi@131a0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos-spi";
+		reg = <0x131a0000 0x30>;
+		interrupts = <0 129 0>;
+	};
+
+	spi@131b0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos-spi";
+		reg = <0x131b0000 0x30>;
+		interrupts = <0 130 0>;
+	};
+
+	ehci@12110000 {
+		compatible = "samsung,exynos-ehci";
+		reg = <0x12110000 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		phy {
+			compatible = "samsung,exynos-usb-phy";
+			reg = <0x12130000 0x100>;
+		};
+	};
+
+};

arch/arm/imx-common/cpu.c

@@ -175,11 +175,6 @@ int cpu_mmc_init(bd_t *bis)
 }
 #endif
 
-void reset_cpu(ulong addr)
-{
-	__raw_writew(4, WDOG1_BASE_ADDR);
-}
-
 u32 get_ahb_clk(void)
 {
 	struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

arch/arm/include/asm/arch-at91/at91sam9x5.h

@@ -154,6 +154,8 @@
 #define ATMEL_PIO_PORTS         4
 #define CPU_HAS_PIO3
 #define PIO_SCDR_DIV            (0x3fff <<  0)  /* Slow Clock Divider Mask */
+#define ATMEL_PMC_UHP		AT91SAM926x_PMC_UHP
+#define ATMEL_ID_UHP		ATMEL_ID_UHPHS
 
 /*
  * at91sam9x5 specific prototypes

arch/arm/include/asm/arch-exynos/clk.h

@@ -34,6 +34,7 @@ unsigned long get_arm_clk(void);
 unsigned long get_i2c_clk(void);
 unsigned long get_pwm_clk(void);
 unsigned long get_uart_clk(int dev_index);
+unsigned long get_mmc_clk(int dev_index);
 void set_mmc_clk(int dev_index, unsigned int div);
 unsigned long get_lcd_clk(void);
 void set_lcd_clk(void);

arch/arm/include/asm/arch-exynos/clock.h

@@ -251,6 +251,282 @@ struct exynos4_clock {
 	unsigned int	div_iem_l1;
 };
 
+struct exynos4x12_clock {
+	unsigned char	res1[0x4200];
+	unsigned int	src_leftbus;
+	unsigned char	res2[0x1fc];
+	unsigned int	mux_stat_leftbus;
+	unsigned char	res3[0xfc];
+	unsigned int	div_leftbus;
+	unsigned char	res4[0xfc];
+	unsigned int	div_stat_leftbus;
+	unsigned char	res5[0x1fc];
+	unsigned int	gate_ip_leftbus;
+	unsigned char	res6[0x12c];
+	unsigned int	gate_ip_image;
+	unsigned char	res7[0xcc];
+	unsigned int	clkout_leftbus;
+	unsigned int	clkout_leftbus_div_stat;
+	unsigned char	res8[0x37f8];
+	unsigned int	src_rightbus;
+	unsigned char	res9[0x1fc];
+	unsigned int	mux_stat_rightbus;
+	unsigned char	res10[0xfc];
+	unsigned int	div_rightbus;
+	unsigned char	res11[0xfc];
+	unsigned int	div_stat_rightbus;
+	unsigned char	res12[0x1fc];
+	unsigned int	gate_ip_rightbus;
+	unsigned char	res13[0x15c];
+	unsigned int	gate_ip_perir;
+	unsigned char	res14[0x9c];
+	unsigned int	clkout_rightbus;
+	unsigned int	clkout_rightbus_div_stat;
+	unsigned char	res15[0x3608];
+	unsigned int	epll_lock;
+	unsigned char	res16[0xc];
+	unsigned int	vpll_lock;
+	unsigned char	res17[0xec];
+	unsigned int	epll_con0;
+	unsigned int	epll_con1;
+	unsigned int	epll_con2;
+	unsigned char	res18[0x4];
+	unsigned int	vpll_con0;
+	unsigned int	vpll_con1;
+	unsigned int	vpll_con2;
+	unsigned char	res19[0xe4];
+	unsigned int	src_top0;
+	unsigned int	src_top1;
+	unsigned char	res20[0x8];
+	unsigned int	src_cam;
+	unsigned int	src_tv;
+	unsigned int	src_mfc;
+	unsigned int	src_g3d;
+	unsigned char	res21[0x4];
+	unsigned int	src_lcd;
+	unsigned int	src_isp;
+	unsigned int	src_maudio;
+	unsigned int	src_fsys;
+	unsigned char	res22[0xc];
+	unsigned int	src_peril0;
+	unsigned int	src_peril1;
+	unsigned int	src_cam1;
+	unsigned char	res23[0xb4];
+	unsigned int	src_mask_top;
+	unsigned char	res24[0xc];
+	unsigned int	src_mask_cam;
+	unsigned int	src_mask_tv;
+	unsigned char	res25[0xc];
+	unsigned int	src_mask_lcd;
+	unsigned int	src_mask_isp;
+	unsigned int	src_mask_maudio;
+	unsigned int	src_mask_fsys;
+	unsigned char	res26[0xc];
+	unsigned int	src_mask_peril0;
+	unsigned int	src_mask_peril1;
+	unsigned char	res27[0xb8];
+	unsigned int	mux_stat_top0;
+	unsigned int	mux_stat_top1;
+	unsigned char	res28[0x10];
+	unsigned int	mux_stat_mfc;
+	unsigned int	mux_stat_g3d;
+	unsigned char	res29[0x28];
+	unsigned int	mux_stat_cam1;
+	unsigned char	res30[0xb4];
+	unsigned int	div_top;
+	unsigned char	res31[0xc];
+	unsigned int	div_cam;
+	unsigned int	div_tv;
+	unsigned int	div_mfc;
+	unsigned int	div_g3d;
+	unsigned char	res32[0x4];
+	unsigned int	div_lcd;
+	unsigned int	div_isp;
+	unsigned int	div_maudio;
+	unsigned int	div_fsys0;
+	unsigned int	div_fsys1;
+	unsigned int	div_fsys2;
+	unsigned int	div_fsys3;
+	unsigned int	div_peril0;
+	unsigned int	div_peril1;
+	unsigned int	div_peril2;
+	unsigned int	div_peril3;
+	unsigned int	div_peril4;
+	unsigned int	div_peril5;
+	unsigned int	div_cam1;
+	unsigned char	res33[0x14];
+	unsigned int	div2_ratio;
+	unsigned char	res34[0x8c];
+	unsigned int	div_stat_top;
+	unsigned char	res35[0xc];
+	unsigned int	div_stat_cam;
+	unsigned int	div_stat_tv;
+	unsigned int	div_stat_mfc;
+	unsigned int	div_stat_g3d;
+	unsigned char	res36[0x4];
+	unsigned int	div_stat_lcd;
+	unsigned int	div_stat_isp;
+	unsigned int	div_stat_maudio;
+	unsigned int	div_stat_fsys0;
+	unsigned int	div_stat_fsys1;
+	unsigned int	div_stat_fsys2;
+	unsigned int	div_stat_fsys3;
+	unsigned int	div_stat_peril0;
+	unsigned int	div_stat_peril1;
+	unsigned int	div_stat_peril2;
+	unsigned int	div_stat_peril3;
+	unsigned int	div_stat_peril4;
+	unsigned int	div_stat_peril5;
+	unsigned int	div_stat_cam1;
+	unsigned char	res37[0x14];
+	unsigned int	div2_stat;
+	unsigned char	res38[0x29c];
+	unsigned int	gate_ip_cam;
+	unsigned int	gate_ip_tv;
+	unsigned int	gate_ip_mfc;
+	unsigned int	gate_ip_g3d;
+	unsigned char	res39[0x4];
+	unsigned int	gate_ip_lcd;
+	unsigned int	gate_ip_isp;
+	unsigned char	res40[0x4];
+	unsigned int	gate_ip_fsys;
+	unsigned char	res41[0x8];
+	unsigned int	gate_ip_gps;
+	unsigned int	gate_ip_peril;
+	unsigned char	res42[0xc];
+	unsigned char	res43[0x4];
+	unsigned char	res44[0xc];
+	unsigned int	gate_block;
+	unsigned char	res45[0x8c];
+	unsigned int	clkout_cmu_top;
+	unsigned int	clkout_cmu_top_div_stat;
+	unsigned char	res46[0x3600];
+	unsigned int	mpll_lock;
+	unsigned char	res47[0xfc];
+	unsigned int	mpll_con0;
+	unsigned int	mpll_con1;
+	unsigned char	res48[0xf0];
+	unsigned int	src_dmc;
+	unsigned char	res49[0xfc];
+	unsigned int	src_mask_dmc;
+	unsigned char	res50[0xfc];
+	unsigned int	mux_stat_dmc;
+	unsigned char	res51[0xfc];
+	unsigned int	div_dmc0;
+	unsigned int	div_dmc1;
+	unsigned char	res52[0xf8];
+	unsigned int	div_stat_dmc0;
+	unsigned int	div_stat_dmc1;
+	unsigned char	res53[0xf8];
+	unsigned int	gate_bus_dmc0;
+	unsigned int	gate_bus_dmc1;
+	unsigned char	res54[0x1f8];
+	unsigned int	gate_ip_dmc0;
+	unsigned int	gate_ip_dmc1;
+	unsigned char	res55[0xf8];
+	unsigned int	clkout_cmu_dmc;
+	unsigned int	clkout_cmu_dmc_div_stat;
+	unsigned char	res56[0x5f8];
+	unsigned int	dcgidx_map0;
+	unsigned int	dcgidx_map1;
+	unsigned int	dcgidx_map2;
+	unsigned char	res57[0x14];
+	unsigned int	dcgperf_map0;
+	unsigned int	dcgperf_map1;
+	unsigned char	res58[0x18];
+	unsigned int	dvcidx_map;
+	unsigned char	res59[0x1c];
+	unsigned int	freq_cpu;
+	unsigned int	freq_dpm;
+	unsigned char	res60[0x18];
+	unsigned int	dvsemclk_en;
+	unsigned int	maxperf;
+	unsigned char	res61[0x8];
+	unsigned int	dmc_freq_ctrl;
+	unsigned int	dmc_pause_ctrl;
+	unsigned int	dddrphy_lock_ctrl;
+	unsigned int	c2c_state;
+	unsigned char	res62[0x2f60];
+	unsigned int	apll_lock;
+	unsigned char	res63[0x8];
+	unsigned char	res64[0xf4];
+	unsigned int	apll_con0;
+	unsigned int	apll_con1;
+	unsigned char	res65[0xf8];
+	unsigned int	src_cpu;
+	unsigned char	res66[0x1fc];
+	unsigned int	mux_stat_cpu;
+	unsigned char	res67[0xfc];
+	unsigned int	div_cpu0;
+	unsigned int	div_cpu1;
+	unsigned char	res68[0xf8];
+	unsigned int	div_stat_cpu0;
+	unsigned int	div_stat_cpu1;
+	unsigned char	res69[0x2f8];
+	unsigned int	clk_gate_ip_cpu;
+	unsigned char	res70[0xfc];
+	unsigned int	clkout_cmu_cpu;
+	unsigned int	clkout_cmu_cpu_div_stat;
+	unsigned char	res71[0x5f8];
+	unsigned int	armclk_stopctrl;
+	unsigned int	atclk_stopctrl;
+	unsigned char	res72[0x10];
+	unsigned char	res73[0x8];
+	unsigned int	pwr_ctrl;
+	unsigned int	pwr_ctrl2;
+	unsigned char	res74[0xd8];
+	unsigned int	apll_con0_l8;
+	unsigned int	apll_con0_l7;
+	unsigned int	apll_con0_l6;
+	unsigned int	apll_con0_l5;
+	unsigned int	apll_con0_l4;
+	unsigned int	apll_con0_l3;
+	unsigned int	apll_con0_l2;
+	unsigned int	apll_con0_l1;
+	unsigned int	iem_control;
+	unsigned char	res75[0xdc];
+	unsigned int	apll_con1_l8;
+	unsigned int	apll_con1_l7;
+	unsigned int	apll_con1_l6;
+	unsigned int	apll_con1_l5;
+	unsigned int	apll_con1_l4;
+	unsigned int	apll_con1_l3;
+	unsigned int	apll_con1_l2;
+	unsigned int	apll_con1_l1;
+	unsigned char	res76[0xe0];
+	unsigned int	div_iem_l8;
+	unsigned int	div_iem_l7;
+	unsigned int	div_iem_l6;
+	unsigned int	div_iem_l5;
+	unsigned int	div_iem_l4;
+	unsigned int	div_iem_l3;
+	unsigned int	div_iem_l2;
+	unsigned int	div_iem_l1;
+	unsigned char	res77[0xe0];
+	unsigned int	l2_status;
+	unsigned char	res78[0xc];
+	unsigned int	cpu_status;
+	unsigned char	res79[0xc];
+	unsigned int	ptm_status;
+	unsigned char	res80[0x2edc];
+	unsigned int	div_isp0;
+	unsigned int	div_isp1;
+	unsigned char	res81[0xf8];
+	unsigned int	div_stat_isp0;
+	unsigned int	div_stat_isp1;
+	unsigned char	res82[0x3f8];
+	unsigned int	gate_ip_isp0;
+	unsigned int	gate_ip_isp1;
+	unsigned char	res83[0x1f8];
+	unsigned int	clkout_cmu_isp;
+	unsigned int	clkout_cmu_ispd_div_stat;
+	unsigned char	res84[0xf8];
+	unsigned int	cmu_isp_spar0;
+	unsigned int	cmu_isp_spar1;
+	unsigned int	cmu_isp_spar2;
+	unsigned int	cmu_isp_spar3;
+};
+
 struct exynos5_clock {
 	unsigned int	apll_lock;
 	unsigned char	res1[0xfc];

arch/arm/include/asm/arch-exynos/cpu.h

@@ -27,7 +27,7 @@
 #define EXYNOS_CPU_NAME			"Exynos"
 #define EXYNOS4_ADDR_BASE		0x10000000
 
-/* EXYNOS4 */
+/* EXYNOS4 Common*/
 #define EXYNOS4_I2C_SPACING		0x10000
 
 #define EXYNOS4_GPIO_PART3_BASE		0x03860000
@@ -63,7 +63,40 @@
 #define EXYNOS4_DP_BASE			DEVICE_NOT_AVAILABLE
 #define EXYNOS4_SPI_ISP_BASE		DEVICE_NOT_AVAILABLE
 
-/* EXYNOS5 */
+/* EXYNOS4X12 */
+#define EXYNOS4X12_GPIO_PART3_BASE	0x03860000
+#define EXYNOS4X12_PRO_ID		0x10000000
+#define EXYNOS4X12_SYSREG_BASE		0x10010000
+#define EXYNOS4X12_POWER_BASE		0x10020000
+#define EXYNOS4X12_SWRESET		0x10020400
+#define EXYNOS4X12_USBPHY_CONTROL	0x10020704
+#define EXYNOS4X12_CLOCK_BASE		0x10030000
+#define EXYNOS4X12_SYSTIMER_BASE	0x10050000
+#define EXYNOS4X12_WATCHDOG_BASE	0x10060000
+#define EXYNOS4X12_DMC0_BASE		0x10600000
+#define EXYNOS4X12_DMC1_BASE		0x10610000
+#define EXYNOS4X12_GPIO_PART4_BASE	0x106E0000
+#define EXYNOS4X12_GPIO_PART2_BASE	0x11000000
+#define EXYNOS4X12_GPIO_PART1_BASE	0x11400000
+#define EXYNOS4X12_FIMD_BASE		0x11C00000
+#define EXYNOS4X12_MIPI_DSIM_BASE	0x11C80000
+#define EXYNOS4X12_USBOTG_BASE		0x12480000
+#define EXYNOS4X12_MMC_BASE		0x12510000
+#define EXYNOS4X12_SROMC_BASE		0x12570000
+#define EXYNOS4X12_USB_HOST_EHCI_BASE	0x12580000
+#define EXYNOS4X12_USBPHY_BASE		0x125B0000
+#define EXYNOS4X12_UART_BASE		0x13800000
+#define EXYNOS4X12_I2C_BASE		0x13860000
+#define EXYNOS4X12_PWMTIMER_BASE	0x139D0000
+
+#define EXYNOS4X12_ADC_BASE		DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_DP_BASE		DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_MODEM_BASE		DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_I2S_BASE            DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_SPI_BASE            DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_SPI_ISP_BASE                DEVICE_NOT_AVAILABLE
+
+/* EXYNOS5 Common*/
 #define EXYNOS5_I2C_SPACING		0x10000
 
 #define EXYNOS5_GPIO_PART4_BASE		0x03860000
@@ -154,17 +187,20 @@ static inline int proid_is_##type(void)			\
 }
 
 IS_EXYNOS_TYPE(exynos4210, 0x4210)
+IS_EXYNOS_TYPE(exynos4412, 0x4412)
 IS_EXYNOS_TYPE(exynos5250, 0x5250)
 
 #define SAMSUNG_BASE(device, base)				\
 static inline unsigned int samsung_get_base_##device(void)	\
 {								\
-	if (cpu_is_exynos4())					\
+	if (cpu_is_exynos4()) {					\
+		if (proid_is_exynos4412())			\
+			return EXYNOS4X12_##base;		\
 		return EXYNOS4_##base;				\
-	else if (cpu_is_exynos5())				\
+	} else if (cpu_is_exynos5()) {				\
 		return EXYNOS5_##base;				\
-	else							\
-		return 0;					\
+	}							\
+	return 0;						\
 }
 
 SAMSUNG_BASE(adc, ADC_BASE)

arch/arm/include/asm/arch-exynos/dp_info.h

@@ -211,4 +211,6 @@ unsigned int exynos_init_dp(void)
 }
 #endif
 
+void exynos_set_dp_platform_data(struct exynos_dp_platform_data *pd);
+
 #endif /* _DP_INFO_H */

arch/arm/include/asm/arch-exynos/gpio.h

@@ -79,6 +79,67 @@ struct exynos4_gpio_part3 {
 	struct s5p_gpio_bank z;
 };
 
+struct exynos4x12_gpio_part1 {
+	struct s5p_gpio_bank a0;
+	struct s5p_gpio_bank a1;
+	struct s5p_gpio_bank b;
+	struct s5p_gpio_bank c0;
+	struct s5p_gpio_bank c1;
+	struct s5p_gpio_bank d0;
+	struct s5p_gpio_bank d1;
+	struct s5p_gpio_bank res1[0x5];
+	struct s5p_gpio_bank f0;
+	struct s5p_gpio_bank f1;
+	struct s5p_gpio_bank f2;
+	struct s5p_gpio_bank f3;
+	struct s5p_gpio_bank res2[0x2];
+	struct s5p_gpio_bank j0;
+	struct s5p_gpio_bank j1;
+};
+
+struct exynos4x12_gpio_part2 {
+	struct s5p_gpio_bank res1[0x2];
+	struct s5p_gpio_bank k0;
+	struct s5p_gpio_bank k1;
+	struct s5p_gpio_bank k2;
+	struct s5p_gpio_bank k3;
+	struct s5p_gpio_bank l0;
+	struct s5p_gpio_bank l1;
+	struct s5p_gpio_bank l2;
+	struct s5p_gpio_bank y0;
+	struct s5p_gpio_bank y1;
+	struct s5p_gpio_bank y2;
+	struct s5p_gpio_bank y3;
+	struct s5p_gpio_bank y4;
+	struct s5p_gpio_bank y5;
+	struct s5p_gpio_bank y6;
+	struct s5p_gpio_bank res2[0x3];
+	struct s5p_gpio_bank m0;
+	struct s5p_gpio_bank m1;
+	struct s5p_gpio_bank m2;
+	struct s5p_gpio_bank m3;
+	struct s5p_gpio_bank m4;
+	struct s5p_gpio_bank res3[0x48];
+	struct s5p_gpio_bank x0;
+	struct s5p_gpio_bank x1;
+	struct s5p_gpio_bank x2;
+	struct s5p_gpio_bank x3;
+};
+
+struct exynos4x12_gpio_part3 {
+	struct s5p_gpio_bank z;
+};
+
+struct exynos4x12_gpio_part4 {
+	struct s5p_gpio_bank v0;
+	struct s5p_gpio_bank v1;
+	struct s5p_gpio_bank res1[0x1];
+	struct s5p_gpio_bank v2;
+	struct s5p_gpio_bank v3;
+	struct s5p_gpio_bank res2[0x1];
+	struct s5p_gpio_bank v4;
+};
+
 struct exynos5_gpio_part1 {
 	struct s5p_gpio_bank a0;
 	struct s5p_gpio_bank a1;
@@ -163,6 +224,30 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
 	    - EXYNOS4_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
 	  * GPIO_PER_BANK) + pin) + EXYNOS4_GPIO_PART1_MAX)
 
+#define exynos4x12_gpio_part1_get_nr(bank, pin) \
+	((((((unsigned int) &(((struct exynos4x12_gpio_part1 *) \
+			       EXYNOS4X12_GPIO_PART1_BASE)->bank)) \
+	    - EXYNOS4X12_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \
+	  * GPIO_PER_BANK) + pin)
+
+#define EXYNOS4X12_GPIO_PART1_MAX ((sizeof(struct exynos4x12_gpio_part1) \
+			    / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
+
+#define exynos4x12_gpio_part2_get_nr(bank, pin) \
+	(((((((unsigned int) &(((struct exynos4x12_gpio_part2 *) \
+				EXYNOS4X12_GPIO_PART2_BASE)->bank)) \
+	    - EXYNOS4X12_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
+	  * GPIO_PER_BANK) + pin) + EXYNOS4X12_GPIO_PART1_MAX)
+
+#define EXYNOS4X12_GPIO_PART2_MAX ((sizeof(struct exynos4x12_gpio_part2) \
+			    / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
+
+#define exynos4x12_gpio_part3_get_nr(bank, pin) \
+	(((((((unsigned int) &(((struct exynos4x12_gpio_part3 *) \
+				EXYNOS4X12_GPIO_PART3_BASE)->bank)) \
+	    - EXYNOS4X12_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \
+	  * GPIO_PER_BANK) + pin) + EXYNOS4X12_GPIO_PART2_MAX)
+
 #define exynos5_gpio_part1_get_nr(bank, pin) \
 	((((((unsigned int) &(((struct exynos5_gpio_part1 *) \
 			       EXYNOS5_GPIO_PART1_BASE)->bank)) \

arch/arm/include/asm/arch-exynos/mipi_dsim.h

@@ -358,7 +358,14 @@ struct mipi_dsim_lcd_driver {
 	void	(*mipi_display_on)(struct mipi_dsim_device *dsim_dev);
 };
 
+#ifdef CONFIG_EXYNOS_MIPI_DSIM
 int exynos_mipi_dsi_init(void);
+#else
+static inline int exynos_mipi_dsi_init(void)
+{
+	return 0;
+}
+#endif
 
 /*
  * register mipi_dsim_lcd_driver object defined by lcd panel driver

arch/arm/include/asm/arch-exynos/periph.h

@@ -25,12 +25,17 @@
 #define __ASM_ARM_ARCH_PERIPH_H
 
 /*
- * Peripherals requiring clock/pinmux configuration. List will
+ * Peripherals required for pinmux configuration. List will
  * grow with support for more devices getting added.
+ * Numbering based on interrupt table.
  *
  */
 enum periph_id {
-	PERIPH_ID_I2C0,
+	PERIPH_ID_UART0 = 51,
+	PERIPH_ID_UART1,
+	PERIPH_ID_UART2,
+	PERIPH_ID_UART3,
+	PERIPH_ID_I2C0 = 56,
 	PERIPH_ID_I2C1,
 	PERIPH_ID_I2C2,
 	PERIPH_ID_I2C3,
@@ -38,22 +43,24 @@ enum periph_id {
 	PERIPH_ID_I2C5,
 	PERIPH_ID_I2C6,
 	PERIPH_ID_I2C7,
-	PERIPH_ID_I2S1,
-	PERIPH_ID_SDMMC0,
+	PERIPH_ID_SPI0 = 68,
+	PERIPH_ID_SPI1,
+	PERIPH_ID_SPI2,
+	PERIPH_ID_SDMMC0 = 75,
 	PERIPH_ID_SDMMC1,
 	PERIPH_ID_SDMMC2,
 	PERIPH_ID_SDMMC3,
-	PERIPH_ID_SDMMC4,
-	PERIPH_ID_SROMC,
-	PERIPH_ID_SPI0,
-	PERIPH_ID_SPI1,
-	PERIPH_ID_SPI2,
+	PERIPH_ID_I2S1 = 99,
+
+	/* Since following peripherals do
+	 * not have shared peripheral interrupts (SPIs)
+	 * they are numbered arbitiraly after the maximum
+	 * SPIs Exynos has (128)
+	 */
+	PERIPH_ID_SROMC = 128,
 	PERIPH_ID_SPI3,
 	PERIPH_ID_SPI4,
-	PERIPH_ID_UART0,
-	PERIPH_ID_UART1,
-	PERIPH_ID_UART2,
-	PERIPH_ID_UART3,
+	PERIPH_ID_SDMMC4,
 
 	PERIPH_ID_COUNT,
 	PERIPH_ID_NONE = -1,

arch/arm/include/asm/arch-exynos/pinmux.h

@@ -55,4 +55,12 @@ enum {
  */
 int exynos_pinmux_config(int peripheral, int flags);
 
+/**
+ * Decode the peripheral id using the interrpt numbers.
+ *
+ * @param blob  Device tree blob
+ * @param node  FDT I2C node to find
+ * @return peripheral id if ok, PERIPH_ID_NONE on error
+ */
+int pinmux_decode_periph_id(const void *blob, int node);
 #endif

arch/arm/include/asm/arch-exynos/sromc.h

@@ -48,4 +48,22 @@ struct s5p_sromc {
 /* Configure the Band Width and Bank Control Regs for required SROMC Bank */
 void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf);
 
+enum {
+	FDT_SROM_PMC,
+	FDT_SROM_TACP,
+	FDT_SROM_TAH,
+	FDT_SROM_TCOH,
+	FDT_SROM_TACC,
+	FDT_SROM_TCOS,
+	FDT_SROM_TACS,
+
+	FDT_SROM_TIMING_COUNT,
+};
+
+struct fdt_sromc {
+	u8 bank;	/* srom bank number */
+	u8 width;	/* bus width in bytes */
+	unsigned int timing[FDT_SROM_TIMING_COUNT]; /* timing parameters */
+};
+
 #endif /* __ASM_ARCH_SROMC_H_ */

arch/arm/include/asm/arch-kirkwood/cpu.h

@@ -33,7 +33,7 @@
 			| (attr << 8) | (kw_winctrl_calcsize(size) << 16))
 
 #define KWGBE_PORT_SERIAL_CONTROL1_REG(_x)	\
-		((_x ? KW_EGIGA0_BASE : KW_EGIGA1_BASE) + 0x44c)
+		((_x ? KW_EGIGA1_BASE : KW_EGIGA0_BASE) + 0x44c)
 
 #define KW_REG_PCIE_DEVID		(KW_REG_PCIE_BASE + 0x00)
 #define KW_REG_PCIE_REVID		(KW_REG_PCIE_BASE + 0x08)

arch/arm/include/asm/arch-kirkwood/mpp.h

@@ -312,6 +312,6 @@
 
 #define MPP_MAX			49
 
-void kirkwood_mpp_conf(u32 *mpp_list, u32 *mpp_save);
+void kirkwood_mpp_conf(const u32 *mpp_list, u32 *mpp_save);
 
 #endif

arch/arm/include/asm/arch-mx31/clock.h

@@ -58,7 +58,5 @@ extern void mx31_set_gpr(enum iomux_gp_func gp, char en);
 void mx31_uart1_hw_init(void);
 void mx31_uart2_hw_init(void);
 void mx31_spi2_hw_init(void);
-void mxc_hw_watchdog_enable(void);
-void mxc_hw_watchdog_reset(void);
 
 #endif /* __ASM_ARCH_CLOCK_H */

arch/arm/include/asm/arch-mx31/imx-regs.h

@@ -68,17 +68,6 @@ struct cspi_regs {
 	u32 test;
 };
 
-/* Watchdog Timer (WDOG) registers */
-#define WDOG_ENABLE	(1 << 2)
-#define WDOG_WT_SHIFT	8
-#define WDOG_WDZST	(1 << 0)
-
-struct wdog_regs {
-	u16 wcr;	/* Control */
-	u16 wsr;	/* Service */
-	u16 wrsr;	/* Reset Status */
-};
-
 /* IIM Control Registers */
 struct iim_regs {
 	u32 iim_stat;
@@ -687,7 +676,7 @@ struct esdc_regs {
 
 #define ARM_PPMRR		0x40000015
 
-#define WDOG_BASE		0x53FDC000
+#define WDOG1_BASE_ADDR		0x53FDC000
 
 /*
  * GPIO

arch/arm/include/asm/arch-mx35/imx-regs.h

@@ -80,7 +80,7 @@
 #define GPIO2_BASE_ADDR		0x53FD0000
 #define SDMA_BASE_ADDR		0x53FD4000
 #define RTC_BASE_ADDR		0x53FD8000
-#define WDOG_BASE_ADDR		0x53FDC000
+#define WDOG1_BASE_ADDR		0x53FDC000
 #define PWM_BASE_ADDR		0x53FE0000
 #define RTIC_BASE_ADDR		0x53FEC000
 #define IIM_BASE_ADDR		0x53FF0000
@@ -292,15 +292,6 @@ struct cspi_regs {
 	u32 test;
 };
 
-/* Watchdog Timer (WDOG) registers */
-struct wdog_regs {
-	u16 wcr;	/* Control */
-	u16 wsr;	/* Service */
-	u16 wrsr;	/* Reset Status */
-	u16 wicr;	/* Interrupt Control */
-	u16 wmcr;	/* Misc Control */
-};
-
 struct esdc_regs {
 	u32	esdctl0;
 	u32	esdcfg0;

arch/arm/include/asm/arch-mx5/imx-regs.h

@@ -218,16 +218,6 @@
  */
 #define WBED		1
 
-/*
- * WEIM WCR
- */
-#define BCM		1
-#define GBCD(x)		(((x) & 0x3) << 1)
-#define INTEN		(1 << 4)
-#define INTPOL		(1 << 5)
-#define WDOG_EN		(1 << 8)
-#define WDOG_LIMIT(x)	(((x) & 0x3) << 9)
-
 #define CS0_128					0
 #define CS0_64M_CS1_64M				1
 #define CS0_64M_CS1_32M_CS2_32M			2

arch/arm/include/asm/global_data.h

@@ -73,6 +73,7 @@ typedef	struct	global_data {
 	unsigned long	reloc_off;
 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
 	unsigned long	tlb_addr;
+	unsigned long	tlb_size;
 #endif
 	const void	*fdt_blob;	/* Our device tree, NULL if none */
 	void		**jt;		/* jump table */

arch/arm/lib/Makefile

@@ -42,14 +42,15 @@ ifndef CONFIG_SPL_BUILD
 COBJS-y	+= board.o
 COBJS-y	+= bootm.o
 COBJS-$(CONFIG_SYS_L2_PL310) += cache-pl310.o
-COBJS-y	+= interrupts.o
-COBJS-y	+= reset.o
 SOBJS-$(CONFIG_USE_ARCH_MEMSET) += memset.o
 SOBJS-$(CONFIG_USE_ARCH_MEMCPY) += memcpy.o
 else
 COBJS-$(CONFIG_SPL_FRAMEWORK) += spl.o
 endif
 
+COBJS-y	+= interrupts.o
+COBJS-y	+= reset.o
+
 COBJS-y	+= cache.o
 COBJS-y	+= cache-cp15.o
 

arch/arm/lib/board.c

@@ -40,6 +40,7 @@
 
 #include <common.h>
 #include <command.h>
+#include <environment.h>
 #include <malloc.h>
 #include <stdio_dev.h>
 #include <version.h>
@@ -231,14 +232,22 @@ int __power_init_board(void)
 int power_init_board(void)
 	__attribute__((weak, alias("__power_init_board")));
 
+	/* Record the board_init_f() bootstage (after arch_cpu_init()) */
+static int mark_bootstage(void)
+{
+	bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f");
+
+	return 0;
+}
+
 init_fnc_t *init_sequence[] = {
 	arch_cpu_init,		/* basic arch cpu dependent setup */
-
-#if defined(CONFIG_BOARD_EARLY_INIT_F)
-	board_early_init_f,
-#endif
+	mark_bootstage,
 #ifdef CONFIG_OF_CONTROL
 	fdtdec_check_fdt,
+#endif
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+	board_early_init_f,
 #endif
 	timer_init,		/* initialize timer */
 #ifdef CONFIG_BOARD_POSTCLK_INIT
@@ -277,8 +286,6 @@ void board_init_f(ulong bootflag)
 	void *new_fdt = NULL;
 	size_t fdt_size = 0;
 
-	bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f");
-
 	memset((void *)gd, 0, sizeof(gd_t));
 
 	gd->mon_len = _bss_end_ofs;
@@ -348,13 +355,14 @@ void board_init_f(ulong bootflag)
 
 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
 	/* reserve TLB table */
-	addr -= (4096 * 4);
+	gd->tlb_size = 4096 * 4;
+	addr -= gd->tlb_size;
 
 	/* round down to next 64 kB limit */
 	addr &= ~(0x10000 - 1);
 
 	gd->tlb_addr = addr;
-	debug("TLB table at: %08lx\n", addr);
+	debug("TLB table from %08lx to %08lx\n", addr, addr + gd->tlb_size);
 #endif
 
 	/* round down to next 4 kB limit */
@@ -467,7 +475,38 @@ static char *failed = "*** failed ***\n";
 #endif
 
 /*
- ************************************************************************
+ * Tell if it's OK to load the environment early in boot.
+ *
+ * If CONFIG_OF_CONFIG is defined, we'll check with the FDT to see
+ * if this is OK (defaulting to saying it's not OK).
+ *
+ * NOTE: Loading the environment early can be a bad idea if security is
+ *       important, since no verification is done on the environment.
+ *
+ * @return 0 if environment should not be loaded, !=0 if it is ok to load
+ */
+static int should_load_env(void)
+{
+#ifdef CONFIG_OF_CONTROL
+	return fdtdec_get_config_int(gd->fdt_blob, "load-environment", 1);
+#elif defined CONFIG_DELAY_ENVIRONMENT
+	return 0;
+#else
+	return 1;
+#endif
+}
+
+#if defined(CONFIG_DISPLAY_BOARDINFO_LATE) && defined(CONFIG_OF_CONTROL)
+static void display_fdt_model(const void *blob)
+{
+	const char *model;
+
+	model = (char *)fdt_getprop(blob, 0, "model", NULL);
+	printf("Model: %s\n", model ? model : "<unknown>");
+}
+#endif
+
+/************************************************************************
  *
  * This is the next part if the initialization sequence: we are now
  * running from RAM and have a "normal" C environment, i. e. global
@@ -560,8 +599,8 @@ void board_init_r(gd_t *id, ulong dest_addr)
 #endif
 
 #ifdef CONFIG_GENERIC_MMC
-       puts("MMC:   ");
-       mmc_initialize(gd->bd);
+	puts("MMC:   ");
+	mmc_initialize(gd->bd);
 #endif
 
 #ifdef CONFIG_HAS_DATAFLASH
@@ -570,7 +609,10 @@ void board_init_r(gd_t *id, ulong dest_addr)
 #endif
 
 	/* initialize environment */
-	env_relocate();
+	if (should_load_env())
+		env_relocate();
+	else
+		set_default_env(NULL);
 
 #if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
 	arm_pci_init();
@@ -587,6 +629,15 @@ void board_init_r(gd_t *id, ulong dest_addr)
 
 	console_init_r();	/* fully init console as a device */
 
+#ifdef CONFIG_DISPLAY_BOARDINFO_LATE
+# ifdef CONFIG_OF_CONTROL
+	/* Put this here so it appears on the LCD, now it is ready */
+	display_fdt_model(gd->fdt_blob);
+# else
+	checkboard();
+# endif
+#endif
+
 #if defined(CONFIG_ARCH_MISC_INIT)
 	/* miscellaneous arch dependent initialisations */
 	arch_misc_init();

arch/arm/lib/cache-cp15.c

@@ -153,8 +153,11 @@ static void cache_disable(uint32_t cache_bit)
 			return;
 		/* if disabling data cache, disable mmu too */
 		cache_bit |= CR_M;
-		flush_dcache_all();
 	}
+	reg = get_cr();
+	cp_delay();
+	if (cache_bit == (CR_C | CR_M))
+		flush_dcache_all();
 	set_cr(reg & ~cache_bit);
 }
 #endif

arch/m68k/lib/board.c

@@ -402,14 +402,14 @@ void board_init_r (gd_t *id, ulong dest_addr)
 
 	gd->flags |= GD_FLG_RELOC;	/* tell others: relocation done */
 
-	serial_initialize();
-
 	debug ("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
 
 	WATCHDOG_RESET ();
 
 	gd->reloc_off =  dest_addr - CONFIG_SYS_MONITOR_BASE;
 
+	serial_initialize();
+
 	monitor_flash_len = (ulong)&__init_end - dest_addr;
 
 #if defined(CONFIG_NEEDS_MANUAL_RELOC)

board/LaCie/net2big_v2/net2big_v2.c

@@ -39,7 +39,7 @@ int board_early_init_f(void)
 			NET2BIG_V2_OE_LOW, NET2BIG_V2_OE_HIGH);
 
 	/* Multi-Purpose Pins Functionality configuration */
-	u32 kwmpp_config[] = {
+	static const u32 kwmpp_config[] = {
 		MPP0_SPI_SCn,
 		MPP1_SPI_MOSI,
 		MPP2_SPI_SCK,

board/LaCie/netspace_v2/netspace_v2.c

@@ -39,7 +39,7 @@ int board_early_init_f(void)
 			NETSPACE_V2_OE_LOW, NETSPACE_V2_OE_HIGH);
 
 	/* Multi-Purpose Pins Functionality configuration */
-	u32 kwmpp_config[] = {
+	static const u32 kwmpp_config[] = {
 		MPP0_SPI_SCn,
 		MPP1_SPI_MOSI,
 		MPP2_SPI_SCK,

board/LaCie/wireless_space/Makefile

@@ -0,0 +1,46 @@
+#
+# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+#
+# Based on Kirkwood support:
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+# GNU General Public License for more details.
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o ../common/common.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/LaCie/wireless_space/kwbimage.cfg

@@ -0,0 +1,82 @@
+#
+# Copyright (C) 2012 Albert ARIBAUD <albert.u.boot@aribaud.net>
+#
+# Based on netspace_v2 kwbimage.cfg:
+# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+#
+# Based on Kirkwood support:
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	nand	# Boot from NAND flash
+NAND_PAGE_SIZE 800
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Values taken from image original LaCie U-Boot header dump!
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1B1B1B9B
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000c30	# DDR Configuration register
+
+DATA 0xFFD01404 0x37743000	# DDR Controller Control Low
+
+DATA 0xFFD01408 0x11012228	# DDR Timing (Low) (active cycles value +1)
+
+DATA 0xFFD0140C 0x00000A19	#  DDR Timing (High)
+
+DATA 0xFFD01410 0x0000CCCC	#  DDR Address Control
+
+DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
+
+DATA 0xFFD01418 0x00000000	#  DDR Operation
+
+DATA 0xFFD0141C 0x00000662	#  DDR Mode
+
+DATA 0xFFD01420 0x00000004	#  DDR Extended Mode
+
+DATA 0xFFD01424 0x0000F07F	#  DDR Controller Control High
+
+DATA 0xFFD01428 0x00096630	# DDR2 ODT Read Timing (default values)
+
+DATA 0xFFD0147C 0x00009663	# DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01504 0x0FFFFFF1	# CS[0]n Size
+DATA 0xFFD01508 0x00000000	# CS[1]n Base address to 0x0
+DATA 0xFFD0150C 0x00000000	# CS[1]n Size, window disabled
+DATA 0xFFD01514 0x00000000	# CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000	# CS[3]n Size, window disabled
+DATA 0xFFD01494 0x00120012	#  DDR ODT Control (Low)
+DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
+DATA 0xFFD0149C 0x0000E40F	# CPU ODT Control
+DATA 0xFFD01480 0x00000001	# DDR Initialization Control
+DATA 0xFFD20134 0x66666666
+DATA 0xFFD20138 0x66666666
+DATA 0xFFD10000 0x01112222
+DATA 0xFFD1000C 0x00000000
+DATA 0xFFD10104 0x00000000
+DATA 0xFFD10100 0x40000000
+# End of Header extension
+DATA 0x0 0x0

board/LaCie/wireless_space/wireless_space.c

@@ -0,0 +1,176 @@
+/*
+ * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+ *
+ * Based on Kirkwood support:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/kirkwood.h>
+#include <asm/arch/mpp.h>
+#include <asm/arch/gpio.h>
+
+#include "../common/common.h"
+#include "netdev.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* GPIO configuration: start FAN at low speed, USB and HDD */
+
+#define WIRELESS_SPACE_OE_LOW		0xFF006808
+#define WIRELESS_SPACE_OE_HIGH		0x0000F989
+#define WIRELESS_SPACE_OE_VAL_LOW	0x00010080
+#define WIRELESS_SPACE_OE_VAL_HIGH	0x00000240
+
+#define WIRELESS_SPACE_REAR_BUTTON	13
+#define WIRELESS_SPACE_FRONT_BUTTON	43
+
+const u32 kwmpp_config[] = {
+	MPP0_NF_IO2,
+	MPP1_NF_IO3,
+	MPP2_NF_IO4,
+	MPP3_NF_IO5,
+	MPP4_NF_IO6,
+	MPP5_NF_IO7,
+	MPP6_SYSRST_OUTn,
+	MPP7_GPO,		/* Fan speed (bit 1) */
+	MPP8_TW_SDA,
+	MPP9_TW_SCK,
+	MPP10_UART0_TXD,
+	MPP11_UART0_RXD,
+	MPP13_GPIO,		/* Red led */
+	MPP14_GPIO,		/* USB fuse */
+	MPP15_SATA0_ACTn,
+	MPP16_GPIO,		/* SATA 0 power */
+	MPP17_GPIO,		/* SATA 1 power */
+	MPP18_NF_IO0,
+	MPP19_NF_IO1,
+	MPP20_GE1_0,		/* Gigabit Ethernet 1 */
+	MPP21_GE1_1,
+	MPP22_GE1_2,
+	MPP23_GE1_3,
+	MPP24_GE1_4,
+	MPP25_GE1_5,
+	MPP26_GE1_6,
+	MPP27_GE1_7,
+	MPP28_GE1_8,
+	MPP29_GE1_9,
+	MPP30_GE1_10,
+	MPP31_GE1_11,
+	MPP32_GE1_12,
+	MPP33_GE1_13,
+	MPP34_GE1_14,
+	MPP35_GE1_15,
+	MPP36_GPIO,		/* Fan speed (bit 2) */
+	MPP37_GPIO,		/* Fan speed (bit 0) */
+	MPP38_GPIO,		/* Fan power */
+	MPP39_GPIO,		/* Fan rotation fail */
+	MPP40_GPIO,		/* Ethernet switch link */
+	MPP41_GPIO,		/* USB enable host vbus */
+	MPP42_GPIO,		/* LED clock control */
+	MPP43_GPIO,		/* WPS button (0=Pushed, 1=Released) */
+	MPP44_GPIO,		/* Red LED on/off */
+	MPP45_GPIO,		/* Red LED timer blink (on=off=100ms) */
+	MPP46_GPIO,		/* Green LED on/off */
+	MPP47_GPIO,		/* LED (blue, green) SATA activity blink */
+	MPP48_GPIO,		/* Blue LED on/off */
+	0
+};
+
+struct mv88e61xx_config swcfg = {
+	.name = "egiga0",
+	.vlancfg = MV88E61XX_VLANCFG_ROUTER,
+	.rgmii_delay = MV88E61XX_RGMII_DELAY_EN,
+	.led_init = MV88E61XX_LED_INIT_EN,
+	.mdip = MV88E61XX_MDIP_NOCHANGE,
+	.portstate = MV88E61XX_PORTSTT_FORWARDING,
+	.cpuport = 0x20,
+	.ports_enabled = 0x3F,
+};
+
+int board_early_init_f(void)
+{
+	/* Gpio configuration */
+	kw_config_gpio(WIRELESS_SPACE_OE_VAL_LOW, WIRELESS_SPACE_OE_VAL_HIGH,
+			WIRELESS_SPACE_OE_LOW, WIRELESS_SPACE_OE_HIGH);
+
+	/* Multi-Purpose Pins Functionality configuration */
+	kirkwood_mpp_conf(kwmpp_config, NULL);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Machine number */
+	gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
+
+	/* Boot parameters address */
+	gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+
+	return 0;
+}
+
+#if defined(CONFIG_MISC_INIT_R)
+int misc_init_r(void)
+{
+#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
+	if (!getenv("ethaddr")) {
+		uchar mac[6];
+		if (lacie_read_mac_address(mac) == 0)
+			eth_setenv_enetaddr("ethaddr", mac);
+	}
+#endif
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
+/* Configure and initialize PHY */
+void reset_phy(void)
+{
+	/* configure switch on egiga0 */
+	mv88e61xx_switch_initialize(&swcfg);
+}
+#endif
+
+#if defined(CONFIG_KIRKWOOD_GPIO) && defined(CONFIG_WIRELESS_SPACE_CMD)
+/* Return GPIO button status */
+static int
+do_ws(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	if (strcmp(argv[1], "button") == 0) {
+		if (strcmp(argv[2], "rear") == 0)
+			/* invert GPIO result for intuitive while/until use */
+			return !kw_gpio_get_value(WIRELESS_SPACE_REAR_BUTTON);
+		else if (strcmp(argv[2], "front") == 0)
+			return kw_gpio_get_value(WIRELESS_SPACE_FRONT_BUTTON);
+		else
+			return -1;
+	} else {
+		return -1;
+	}
+}
+
+U_BOOT_CMD(ws, 3, 0, do_ws,
+	   "Return GPIO button status 0=off 1=on",
+	   "- ws button rear|front: test buttons' states\n"
+);
+#endif

board/Marvell/dreamplug/dreamplug.c

@@ -46,7 +46,7 @@ int board_early_init_f(void)
 			DREAMPLUG_OE_LOW, DREAMPLUG_OE_HIGH);
 
 	/* Multi-Purpose Pins Functionality configuration */
-	u32 kwmpp_config[] = {
+	static const u32 kwmpp_config[] = {
 		MPP0_SPI_SCn,		/* SPI Flash */
 		MPP1_SPI_MOSI,
 		MPP2_SPI_SCK,

board/Marvell/guruplug/guruplug.c

@@ -43,7 +43,7 @@ int board_early_init_f(void)
 			GURUPLUG_OE_LOW, GURUPLUG_OE_HIGH);
 
 	/* Multi-Purpose Pins Functionality configuration */
-	u32 kwmpp_config[] = {
+	static const u32 kwmpp_config[] = {
 		MPP0_NF_IO2,
 		MPP1_NF_IO3,
 		MPP2_NF_IO4,

board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c

@@ -45,7 +45,7 @@ int board_early_init_f(void)
 			MV88F6281GTW_GE_OE_LOW, MV88F6281GTW_GE_OE_HIGH);
 
 	/* Multi-Purpose Pins Functionality configuration */
-	u32 kwmpp_config[] = {
+	static const u32 kwmpp_config[] = {
 		MPP0_SPI_SCn,
 		MPP1_SPI_MOSI,
 		MPP2_SPI_SCK,

board/Marvell/openrd/openrd.c

@@ -48,7 +48,7 @@ int board_early_init_f(void)
 			OPENRD_OE_LOW, OPENRD_OE_HIGH);
 
 	/* Multi-Purpose Pins Functionality configuration */
-	u32 kwmpp_config[] = {
+	static const u32 kwmpp_config[] = {
 		MPP0_NF_IO2,
 		MPP1_NF_IO3,
 		MPP2_NF_IO4,

board/Marvell/rd6281a/rd6281a.c

@@ -44,7 +44,7 @@ int board_early_init_f(void)
 			RD6281A_OE_LOW, RD6281A_OE_HIGH);
 
 	/* Multi-Purpose Pins Functionality configuration */
-	u32 kwmpp_config[] = {
+	static const u32 kwmpp_config[] = {
 		MPP0_NF_IO2,
 		MPP1_NF_IO3,
 		MPP2_NF_IO4,

board/Marvell/sheevaplug/sheevaplug.c

@@ -43,7 +43,7 @@ int board_early_init_f(void)
 			SHEEVAPLUG_OE_LOW, SHEEVAPLUG_OE_HIGH);
 
 	/* Multi-Purpose Pins Functionality configuration */
-	u32 kwmpp_config[] = {
+	static const u32 kwmpp_config[] = {
 		MPP0_NF_IO2,
 		MPP1_NF_IO3,
 		MPP2_NF_IO4,

board/Seagate/dockstar/dockstar.c

@@ -47,7 +47,7 @@ int board_early_init_f(void)
 			DOCKSTAR_OE_LOW, DOCKSTAR_OE_HIGH);
 
 	/* Multi-Purpose Pins Functionality configuration */
-	u32 kwmpp_config[] = {
+	static const u32 kwmpp_config[] = {
 		MPP0_NF_IO2,
 		MPP1_NF_IO3,
 		MPP2_NF_IO4,

board/atmel/at91sam9x5ek/at91sam9x5ek.c

@@ -295,6 +295,9 @@ int board_init(void)
 	at91_macb_hw_init();
 #endif
 
+#if defined(CONFIG_USB_OHCI_NEW) || defined(CONFIG_USB_EHCI)
+	at91_uhp_hw_init();
+#endif
 #ifdef CONFIG_LCD
 	at91sam9x5ek_lcd_hw_init();
 #endif

board/buffalo/lsxl/lsxl.c

@@ -49,9 +49,8 @@
  * you can do this only with a working network connection. Therefore, a random
  * ethernet address is generated if none is set and a DHCP request is sent.
  * After a successful DHCP response is received, the network settings are
- * configured and the ncip parameter is set to the serverip. Eg. for a working
- * resuce mode, you should set 'next-server' to the host where the netconsole
- * client is started.
+ * configured and the ncip is unset. Therefore, all netconsole packets are
+ * broadcasted.
  * Additionally, the bootsource is set to 'rescue'.
  */
 
@@ -76,7 +75,7 @@ int board_early_init_f(void)
 	 * Multi-Purpose Pins Functionality configuration
 	 * These strappings are taken from the original vendor uboot port.
 	 */
-	u32 kwmpp_config[] = {
+	static const u32 kwmpp_config[] = {
 		MPP0_SPI_SCn,
 		MPP1_SPI_MOSI,
 		MPP2_SPI_SCK,

board/cloudengines/pogo_e02/pogo_e02.c

@@ -45,7 +45,7 @@ int board_early_init_f(void)
 			POGO_E02_OE_LOW, POGO_E02_OE_HIGH);
 
 	/* Multi-Purpose Pins Functionality configuration */
-	u32 kwmpp_config[] = {
+	static const u32 kwmpp_config[] = {
 		MPP0_NF_IO2,
 		MPP1_NF_IO3,
 		MPP2_NF_IO4,

board/d-link/dns325/dns325.c

@@ -44,7 +44,7 @@ int board_early_init_f(void)
 			DNS325_OE_LOW, DNS325_OE_HIGH);
 
 	/* Multi-Purpose Pins Functionality configuration */
-	u32 kwmpp_config[] = {
+	static const u32 kwmpp_config[] = {
 		MPP0_NF_IO2,
 		MPP1_NF_IO3,
 		MPP2_NF_IO4,

board/davedenx/qong/qong.c

@@ -37,13 +37,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifdef CONFIG_HW_WATCHDOG
-void hw_watchdog_reset(void)
-{
-	mxc_hw_watchdog_reset();
-}
-#endif
-
 int dram_init(void)
 {
 	/* dram_init must store complete ramsize in gd->ram_size */
@@ -188,7 +181,7 @@ int board_late_init(void)
 	pmic_reg_write(p, REG_INT_STATUS1, RTCRSTI);
 
 #ifdef CONFIG_HW_WATCHDOG
-	mxc_hw_watchdog_enable();
+	hw_watchdog_init();
 #endif
 
 	return 0;

board/freescale/mx31pdk/mx31pdk.c

@@ -36,13 +36,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifdef CONFIG_HW_WATCHDOG
-void hw_watchdog_reset(void)
-{
-	mxc_hw_watchdog_reset();
-}
-#endif
-
 int dram_init(void)
 {
 	/* dram_init must store complete ramsize in gd->ram_size */
@@ -98,7 +91,7 @@ int board_late_init(void)
 	pmic_reg_write(p, REG_POWER_CTL0, val | COINCHEN);
 	pmic_reg_write(p, REG_INT_STATUS1, RTCRSTI);
 #ifdef CONFIG_HW_WATCHDOG
-	mxc_hw_watchdog_enable();
+	hw_watchdog_init();
 #endif
 	return 0;
 }

board/freescale/mx51evk/mx51evk.c

@@ -489,8 +489,6 @@ int board_init(void)
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 
-	lcd_enable();
-
 	return 0;
 }
 

board/freescale/mx51evk/mx51evk_video.c

@@ -48,6 +48,22 @@ static struct fb_videomode const claa_wvga = {
 	.vmode		= FB_VMODE_NONINTERLACED
 };
 
+static struct fb_videomode const dvi = {
+	.name		= "DVI panel",
+	.refresh	= 60,
+	.xres		= 1024,
+	.yres		= 768,
+	.pixclock	= 15385,
+	.left_margin	= 220,
+	.right_margin	= 40,
+	.upper_margin	= 21,
+	.lower_margin	= 7,
+	.hsync_len	= 60,
+	.vsync_len	= 10,
+	.sync		= 0,
+	.vmode		= FB_VMODE_NONINTERLACED
+};
+
 void setup_iomux_lcd(void)
 {
 	/* DI2_PIN15 */
@@ -73,9 +89,26 @@ void setup_iomux_lcd(void)
 	gpio_direction_output(MX51EVK_LCD_BACKLIGHT, 1);
 }
 
-void lcd_enable(void)
+int board_video_skip(void)
 {
-	int ret = ipuv3_fb_init(&claa_wvga, 1, IPU_PIX_FMT_RGB565);
+	int ret;
+	char const *e = getenv("panel");
+
+	if (e) {
+		if (strcmp(e, "claa") == 0) {
+			ret = ipuv3_fb_init(&claa_wvga, 1, IPU_PIX_FMT_RGB565);
+			if (ret)
+				printf("claa cannot be configured: %d\n", ret);
+			return ret;
+		}
+	}
+
+	/*
+	 * 'panel' env variable not found or has different value than 'claa'
+	 *  Defaulting to dvi output.
+	 */
+	ret = ipuv3_fb_init(&dvi, 0, IPU_PIX_FMT_RGB24);
 	if (ret)
-		printf("LCD cannot be configured: %d\n", ret);
+		printf("dvi cannot be configured: %d\n", ret);
+	return ret;
 }

board/freescale/mx53loco/mx53loco.c

@@ -503,8 +503,6 @@ int board_init(void)
 	mxc_set_sata_internal_clock();
 	setup_iomux_i2c();
 
-	lcd_enable();
-
 	return 0;
 }
 

board/freescale/mx53loco/mx53loco_video.c

@@ -46,6 +46,21 @@ static struct fb_videomode const claa_wvga = {
 	.vmode		= FB_VMODE_NONINTERLACED
 };
 
+static struct fb_videomode const seiko_wvga = {
+	.name		= "Seiko-43WVF1G",
+	.refresh	= 60,
+	.xres		= 800,
+	.yres		= 480,
+	.pixclock	= 29851, /* picosecond (33.5 MHz) */
+	.left_margin	= 89,
+	.right_margin	= 164,
+	.upper_margin	= 23,
+	.lower_margin	= 10,
+	.hsync_len	= 10,
+	.vsync_len	= 10,
+	.sync		= 0,
+};
+
 void setup_iomux_lcd(void)
 {
 	mxc_request_iomux(MX53_PIN_DI0_DISP_CLK, IOMUX_CONFIG_ALT0);
@@ -86,9 +101,26 @@ void setup_iomux_lcd(void)
 	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_1), 1);
 }
 
-void lcd_enable(void)
+int board_video_skip(void)
 {
-	int ret = ipuv3_fb_init(&claa_wvga, 0, IPU_PIX_FMT_RGB565);
+	int ret;
+	char const *e = getenv("panel");
+
+	if (e) {
+		if (strcmp(e, "seiko") == 0) {
+			ret = ipuv3_fb_init(&seiko_wvga, 0, IPU_PIX_FMT_RGB24);
+			if (ret)
+				printf("Seiko cannot be configured: %d\n", ret);
+			return ret;
+		}
+	}
+
+	/*
+	 * 'panel' env variable not found or has different value than 'seiko'
+	 *  Defaulting to claa lcd.
+	 */
+	ret = ipuv3_fb_init(&claa_wvga, 0, IPU_PIX_FMT_RGB565);
 	if (ret)
-		printf("LCD cannot be configured: %d\n", ret);
+		printf("CLAA cannot be configured: %d\n", ret);
+	return ret;
 }

board/hale/tt01/tt01.c

@@ -179,7 +179,7 @@ int board_init(void)
 int board_late_init(void)
 {
 #ifdef CONFIG_HW_WATCHDOG
-	mxc_hw_watchdog_enable();
+	hw_watchdog_init();
 #endif
 
 	return 0;

board/iomega/iconnect/iconnect.c

@@ -41,7 +41,7 @@ int board_early_init_f(void)
 			ICONNECT_OE_LOW, ICONNECT_OE_HIGH);
 
 	/* Multi-Purpose Pins Functionality configuration */
-	u32 kwmpp_config[] = {
+	static const u32 kwmpp_config[] = {
 		MPP0_NF_IO2,
 		MPP1_NF_IO3,
 		MPP2_NF_IO4,

board/karo/tk71/tk71.c

@@ -47,7 +47,7 @@ int board_early_init_f(void)
 			TK71_OE_LOW, TK71_OE_HIGH);
 
 	/* Multi-Purpose Pins Functionality configuration */
-	u32 kwmpp_config[] = {
+	static const u32 kwmpp_config[] = {
 		MPP0_NF_IO2,
 		MPP1_NF_IO3,
 		MPP2_NF_IO4,

board/keymile/common/common.c

@@ -121,7 +121,7 @@ int i2c_make_abort(void)
 {
 
 #if defined(CONFIG_HARD_I2C) && !defined(MACH_TYPE_KM_KIRKWOOD)
-	immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
+	immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 	i2c8260_t *i2c	= (i2c8260_t *)&immap->im_i2c;
 
 	/*

board/keymile/km_arm/km_arm.c

@@ -54,7 +54,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define MASK_RBI_DEFECT_16	0x01
 
 /* Multi-Purpose Pins Functionality configuration */
-u32 kwmpp_config[] = {
+static const u32 kwmpp_config[] = {
 	MPP0_NF_IO2,
 	MPP1_NF_IO3,
 	MPP2_NF_IO4,
@@ -193,15 +193,6 @@ void set_bootcount_addr(void)
 
 int misc_init_r(void)
 {
-	char *str;
-	int mach_type;
-
-	str = getenv("mach_type");
-	if (str != NULL) {
-		mach_type = simple_strtoul(str, NULL, 10);
-		printf("Overwriting MACH_TYPE with %d!!!\n", mach_type);
-		gd->bd->bi_arch_number = mach_type;
-	}
 #if defined(CONFIG_KM_MGCOGE3UN)
 	char *wait_for_ne;
 	wait_for_ne = getenv("waitforne");
@@ -258,11 +249,6 @@ int board_early_init_f(void)
 
 int board_init(void)
 {
-	/*
-	 * arch number of board
-	 */
-	gd->bd->bi_arch_number = MACH_TYPE_KM_KIRKWOOD;
-
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
 

board/keymile/km_arm/kwbimage-memphis.cfg

@@ -55,9 +55,9 @@ DATA 0xFFD10008 0x00001100	# MPP Control 2 Register
 DATA 0xFFD100E0 0x1B1B1B1B	# IO Configuration 0 Register
 DATA 0xFFD20134 0x66666666	# L2 RAM Timing 0 Register
 DATA 0xFFD20138 0x66666666	# L2 RAM Timing 1 Register
-DATA 0xFFD20154 0x00000200	# CPU RAM Management Control3 Register
-DATA 0xFFD2014C 0x00001C00	# CPU RAM Management Control1 Register
-DATA 0xFFD20148 0x00000001	# CPU RAM Management Control0 Register
+
+# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched!
+# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage
 
 #Dram initalization
 DATA 0xFFD01400 0x430004E0	# SDRAM Configuration Register

board/keymile/km_arm/kwbimage.cfg

@@ -52,9 +52,9 @@ DATA 0xFFD10008 0x00001100	# MPP Control 2 Register
 DATA 0xFFD100E0 0x1B1B1B1B	# IO Configuration 0 Register
 DATA 0xFFD20134 0x66666666	# L2 RAM Timing 0 Register
 DATA 0xFFD20138 0x66666666	# L2 RAM Timing 1 Register
-DATA 0xFFD20154 0x00000200	# CPU RAM Management Control3 Register
-DATA 0xFFD2014C 0x00001C00	# CPU RAM Management Control1 Register
-DATA 0xFFD20148 0x00000001	# CPU RAM Management Control0 Register
+
+# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched!
+# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage
 
 #Dram initalization
 DATA 0xFFD01400 0x43000400	# SDRAM Configuration Register

board/keymile/km_arm/kwbimage_128M16_1.cfg

@@ -98,29 +98,8 @@ DATA 0xFFD20138 0x66666666	# L2 RAM Timing 1 Register
 # bit 19-18: 1, ECC RAM WTC RAM0
 # bit 31-20: ???,Reserve
 
-DATA 0xFFD20154 0x00000200	# CPU RAM Management Control3 Register
-# bit 23-0:  0x000200, Addr Config tuning
-# bit 31-24: 0,        Reserved
-
-# ??? Missing register # CPU RAM Management Control2 Register
-
-DATA 0xFFD2014C 0x00001C00	# CPU RAM Management Control1 Register
-# bit 15-0:  0x1C00, Opmux Tuning
-# bit 31-16: 0,      Pc Dp Tuning
-
-DATA 0xFFD20148 0x00000001	# CPU RAM Management Control0 Register
-# bit 1-0:   1, addr clk tune
-# bit 3-2:   0, reserved
-# bit 5-4:   0, dtcmp clk tune
-# bit 7-6:   0, reserved
-# bit 9-8:   0, macdrv clk tune
-# bit 11-10: 0, opmuxgm2 clk tune
-# bit 15-14: 0, rf clk tune
-# bit 17-16: 0, rfbypass clk tune
-# bit 19-18: 0, pc dp clk tune
-# bit 23-20: 0, icache clk tune
-# bit 27:24: 0, dcache clk tune
-# bit 31:28: 0, regfile tunin
+# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched!
+# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage
 
 # SDRAM initalization
 DATA 0xFFD01400 0x430004E0	# SDRAM Configuration Register

board/keymile/km_arm/kwbimage_256M8_1.cfg

@@ -100,29 +100,8 @@ DATA 0xFFD20138 0x66666666	# L2 RAM Timing 1 Register
 # bit 19-18: 1, ECC RAM WTC RAM0
 # bit 31-20: ?,Reserved
 
-DATA 0xFFD20154 0x00000200	# CPU RAM Management Control3 Register
-# bit 23-0:  0x000200, Addr Config tuning
-# bit 31-24: 0,        Reserved
-
-# ??? Missing register # CPU RAM Management Control2 Register
-
-DATA 0xFFD2014C 0x00001C00	# CPU RAM Management Control1 Register
-# bit 15-0:  0x1C00, Opmux Tuning
-# bit 31-16: 0,      Pc Dp Tuning
-
-DATA 0xFFD20148 0x00000001	# CPU RAM Management Control0 Register
-# bit 1-0:   1, addr clk tune
-# bit 3-2:   0, reserved
-# bit 5-4:   0, dtcmp clk tune
-# bit 7-6:   0, reserved
-# bit 9-8:   0, macdrv clk tune
-# bit 11-10: 0, opmuxgm2 clk tune
-# bit 15-14: 0, rf clk tune
-# bit 17-16: 0, rfbypass clk tune
-# bit 19-18: 0, pc dp clk tune
-# bit 23-20: 0, icache clk tune
-# bit 27:24: 0, dcache clk tune
-# bit 31:28: 0, regfile tunin
+# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched!
+# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage
 
 # SDRAM initalization
 DATA 0xFFD01400 0x430004E0	# SDRAM Configuration Register

board/raidsonic/ib62x0/ib62x0.c

@@ -45,7 +45,7 @@ int board_early_init_f(void)
 	/* Set SATA activity LEDs to default off */
 	writel(MVSATAHC_LED_POLARITY_CTRL, MVSATAHC_LED_CONF_REG);
 	/* Multi-Purpose Pins Functionality configuration */
-	u32 kwmpp_config[] = {
+	static const u32 kwmpp_config[] = {
 		MPP0_NF_IO2,
 		MPP1_NF_IO3,
 		MPP2_NF_IO4,

board/samsung/dts/exynos5250-smdk5250.dts

@@ -0,0 +1,69 @@
+/*
+ * SAMSUNG SMDK5250 board device tree source
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+/include/ ARCH_CPU_DTS
+
+/ {
+	model = "SAMSUNG SMDK5250 board based on EXYNOS5250";
+	compatible = "samsung,smdk5250", "samsung,exynos5250";
+
+	aliases {
+		i2c0 = "/i2c@12c60000";
+		i2c1 = "/i2c@12c70000";
+		i2c2 = "/i2c@12c80000";
+		i2c3 = "/i2c@12c90000";
+		i2c4 = "/i2c@12ca0000";
+		i2c5 = "/i2c@12cb0000";
+		i2c6 = "/i2c@12cc0000";
+		i2c7 = "/i2c@12cd0000";
+		spi0 = "/spi@12d20000";
+		spi1 = "/spi@12d30000";
+		spi2 = "/spi@12d40000";
+		spi3 = "/spi@131a0000";
+		spi4 = "/spi@131b0000";
+	};
+
+	sromc@12250000 {
+		bank = <1>;
+		srom-timing = <1 9 12 1 6 1 1>;
+		width = <2>;
+		lan@5000000 {
+			compatible = "smsc,lan9215", "smsc,lan";
+			reg = <0x5000000 0x100>;
+			phy-mode = "mii";
+		};
+	};
+
+	sound@12d60000 {
+		samsung,i2s-epll-clock-frequency = <192000000>;
+		samsung,i2s-sampling-rate = <48000>;
+		samsung,i2s-bits-per-sample = <16>;
+		samsung,i2s-channels = <2>;
+		samsung,i2s-lr-clk-framesize = <256>;
+		samsung,i2s-bit-clk-framesize = <32>;
+		samsung,codec-type = "wm8994";
+	};
+
+	i2c@12c70000 {
+		soundcodec@1a {
+			reg = <0x1a>;
+			compatible = "wolfson,wm8994-codec";
+		};
+	};
+
+	i2c@12c60000 {
+		pmic@9 {
+			reg = <0x9>;
+			compatible = "maxim,max77686_pmic";
+		};
+	};
+};

board/samsung/smdk5250/smdk5250.c

@@ -21,43 +21,35 @@
  */
 
 #include <common.h>
+#include <fdtdec.h>
 #include <asm/io.h>
 #include <i2c.h>
+#include <lcd.h>
 #include <netdev.h>
 #include <spi.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/mmc.h>
 #include <asm/arch/pinmux.h>
+#include <asm/arch/power.h>
 #include <asm/arch/sromc.h>
+#include <asm/arch/dp_info.h>
 #include <power/pmic.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifdef CONFIG_SMC911X
-static int smc9115_pre_init(void)
+#ifdef CONFIG_USB_EHCI_EXYNOS
+int board_usb_vbus_init(void)
 {
-	u32 smc_bw_conf, smc_bc_conf;
-	int err;
+	struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
+						samsung_get_base_gpio_part1();
 
-	/* Ethernet needs data bus width of 16 bits */
-	smc_bw_conf = SROMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK)
-			| SROMC_BYTE_ENABLE(CONFIG_ENV_SROM_BANK);
+	/* Enable VBUS power switch */
+	s5p_gpio_direction_output(&gpio1->x2, 6, 1);
 
-	smc_bc_conf = SROMC_BC_TACS(0x01) | SROMC_BC_TCOS(0x01)
-			| SROMC_BC_TACC(0x06) | SROMC_BC_TCOH(0x01)
-			| SROMC_BC_TAH(0x0C)  | SROMC_BC_TACP(0x09)
-			| SROMC_BC_PMC(0x01);
+	/* VBUS turn ON time */
+	mdelay(3);
 
-	/* Select and configure the SROMC bank */
-	err = exynos_pinmux_config(PERIPH_ID_SROMC,
-				CONFIG_ENV_SROM_BANK | PINMUX_FLAG_16BIT);
-	if (err) {
-		debug("SROMC not configured\n");
-		return err;
-	}
-
-	s5p_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf);
 	return 0;
 }
 #endif
@@ -67,6 +59,9 @@ int board_init(void)
 	gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
 #ifdef CONFIG_EXYNOS_SPI
 	spi_init();
+#endif
+#ifdef CONFIG_USB_EHCI_EXYNOS
+	board_usb_vbus_init();
 #endif
 	return 0;
 }
@@ -122,12 +117,94 @@ void dram_init_banksize(void)
 							PHYS_SDRAM_8_SIZE);
 }
 
+#ifdef CONFIG_OF_CONTROL
+static int decode_sromc(const void *blob, struct fdt_sromc *config)
+{
+	int err;
+	int node;
+
+	node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC);
+	if (node < 0) {
+		debug("Could not find SROMC node\n");
+		return node;
+	}
+
+	config->bank = fdtdec_get_int(blob, node, "bank", 0);
+	config->width = fdtdec_get_int(blob, node, "width", 2);
+
+	err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing,
+			FDT_SROM_TIMING_COUNT);
+	if (err < 0) {
+		debug("Could not decode SROMC configuration\n");
+		return -FDT_ERR_NOTFOUND;
+	}
+
+	return 0;
+}
+#endif
+
 int board_eth_init(bd_t *bis)
 {
 #ifdef CONFIG_SMC911X
-	if (smc9115_pre_init())
+	u32 smc_bw_conf, smc_bc_conf;
+	struct fdt_sromc config;
+	fdt_addr_t base_addr;
+	int node;
+
+#ifdef CONFIG_OF_CONTROL
+	node = decode_sromc(gd->fdt_blob, &config);
+	if (node < 0) {
+		debug("%s: Could not find sromc configuration\n", __func__);
+		return 0;
+	}
+	node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215);
+	if (node < 0) {
+		debug("%s: Could not find lan9215 configuration\n", __func__);
+		return 0;
+	}
+
+	/* We now have a node, so any problems from now on are errors */
+	base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg");
+	if (base_addr == FDT_ADDR_T_NONE) {
+		debug("%s: Could not find lan9215 address\n", __func__);
 		return -1;
-	return smc911x_initialize(0, CONFIG_SMC911X_BASE);
+	}
+#else
+	/* Non-FDT configuration - bank number and timing parameters*/
+	config.bank = CONFIG_ENV_SROM_BANK;
+	config.width = 2;
+
+	config.timing[FDT_SROM_TACS] = 0x01;
+	config.timing[FDT_SROM_TCOS] = 0x01;
+	config.timing[FDT_SROM_TACC] = 0x06;
+	config.timing[FDT_SROM_TCOH] = 0x01;
+	config.timing[FDT_SROM_TAH] = 0x0C;
+	config.timing[FDT_SROM_TACP] = 0x09;
+	config.timing[FDT_SROM_PMC] = 0x01;
+	base_addr = CONFIG_SMC911X_BASE;
+#endif
+
+	/* Ethernet needs data bus width of 16 bits */
+	if (config.width != 2) {
+		debug("%s: Unsupported bus width %d\n", __func__,
+			config.width);
+		return -1;
+	}
+	smc_bw_conf = SROMC_DATA16_WIDTH(config.bank)
+			| SROMC_BYTE_ENABLE(config.bank);
+
+	smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS])   |\
+			SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) |\
+			SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) |\
+			SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) |\
+			SROMC_BC_TAH(config.timing[FDT_SROM_TAH])   |\
+			SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) |\
+			SROMC_BC_PMC(config.timing[FDT_SROM_PMC]);
+
+	/* Select and configure the SROMC bank */
+	exynos_pinmux_config(PERIPH_ID_SROMC, config.bank);
+	s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf);
+	return smc911x_initialize(0, base_addr);
 #endif
 	return 0;
 }
@@ -188,24 +265,6 @@ static int board_uart_init(void)
 	return 0;
 }
 
-#ifdef CONFIG_SYS_I2C_INIT_BOARD
-static int board_i2c_init(void)
-{
-	int i, err;
-
-	for (i = 0; i < CONFIG_MAX_I2C_NUM; i++) {
-		err = exynos_pinmux_config((PERIPH_ID_I2C0 + i),
-						PINMUX_FLAG_NONE);
-		if (err) {
-			debug("I2C%d not configured\n", (PERIPH_ID_I2C0 + i));
-			return err;
-		}
-	}
-	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-	return 0;
-}
-#endif
-
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 int board_early_init_f(void)
 {
@@ -216,8 +275,104 @@ int board_early_init_f(void)
 		return err;
 	}
 #ifdef CONFIG_SYS_I2C_INIT_BOARD
-	err = board_i2c_init();
+	board_i2c_init(gd->fdt_blob);
 #endif
 	return err;
 }
 #endif
+
+#ifdef CONFIG_LCD
+void cfg_lcd_gpio(void)
+{
+	struct exynos5_gpio_part1 *gpio1 =
+		(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
+
+	/* For Backlight */
+	s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
+	s5p_gpio_set_value(&gpio1->b2, 0, 1);
+
+	/* LCD power on */
+	s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
+	s5p_gpio_set_value(&gpio1->x1, 5, 1);
+
+	/* Set Hotplug detect for DP */
+	s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
+}
+
+vidinfo_t panel_info = {
+	.vl_freq	= 60,
+	.vl_col		= 2560,
+	.vl_row		= 1600,
+	.vl_width	= 2560,
+	.vl_height	= 1600,
+	.vl_clkp	= CONFIG_SYS_LOW,
+	.vl_hsp		= CONFIG_SYS_LOW,
+	.vl_vsp		= CONFIG_SYS_LOW,
+	.vl_dp		= CONFIG_SYS_LOW,
+	.vl_bpix	= 4,	/* LCD_BPP = 2^4, for output conosle on LCD */
+
+	/* wDP panel timing infomation */
+	.vl_hspw	= 32,
+	.vl_hbpd	= 80,
+	.vl_hfpd	= 48,
+
+	.vl_vspw	= 6,
+	.vl_vbpd	= 37,
+	.vl_vfpd	= 3,
+	.vl_cmd_allow_len = 0xf,
+
+	.win_id		= 3,
+	.cfg_gpio	= cfg_lcd_gpio,
+	.backlight_on	= NULL,
+	.lcd_power_on	= NULL,
+	.reset_lcd	= NULL,
+	.dual_lcd_enabled = 0,
+
+	.init_delay	= 0,
+	.power_on_delay = 0,
+	.reset_delay	= 0,
+	.interface_mode = FIMD_RGB_INTERFACE,
+	.dp_enabled	= 1,
+};
+
+static struct edp_device_info edp_info = {
+	.disp_info = {
+		.h_res = 2560,
+		.h_sync_width = 32,
+		.h_back_porch = 80,
+		.h_front_porch = 48,
+		.v_res = 1600,
+		.v_sync_width  = 6,
+		.v_back_porch = 37,
+		.v_front_porch = 3,
+		.v_sync_rate = 60,
+	},
+	.lt_info = {
+		.lt_status = DP_LT_NONE,
+	},
+	.video_info = {
+		.master_mode = 0,
+		.bist_mode = DP_DISABLE,
+		.bist_pattern = NO_PATTERN,
+		.h_sync_polarity = 0,
+		.v_sync_polarity = 0,
+		.interlaced = 0,
+		.color_space = COLOR_RGB,
+		.dynamic_range = VESA,
+		.ycbcr_coeff = COLOR_YCBCR601,
+		.color_depth = COLOR_8,
+	},
+};
+
+static struct exynos_dp_platform_data dp_platform_data = {
+	.phy_enable	= set_dp_phy_ctrl,
+	.edp_dev_info	= &edp_info,
+};
+
+void init_panel_info(vidinfo_t *vid)
+{
+	vid->rgb_mode   = MODE_RGB_P,
+
+	exynos_set_dp_platform_data(&dp_platform_data);
+}
+#endif

board/samsung/trats/trats.c

@@ -67,7 +67,7 @@ struct s3c_plat_otg_data s5pc210_otg_data;
 
 int board_init(void)
 {
-	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+	gd->bd->bi_boot_params = CONFIG_SYS_SPL_ARGS_ADDR;
 
 	check_hw_revision();
 	printf("HW Revision:\t0x%x\n", board_rev);

boards.cfg

@@ -99,6 +99,7 @@ at91sam9m10g45ek_nandflash   arm         arm926ejs   at91sam9m10g45ek    atmel
 at91sam9rlek_dataflash       arm         arm926ejs   at91sam9rlek        atmel          at91        at91sam9rlek:AT91SAM9RL,SYS_USE_DATAFLASH
 at91sam9rlek_nandflash       arm         arm926ejs   at91sam9rlek        atmel          at91        at91sam9rlek:AT91SAM9RL,SYS_USE_NANDFLASH
 at91sam9x5ek_nandflash       arm         arm926ejs   at91sam9x5ek        atmel          at91        at91sam9x5ek:AT91SAM9X5,SYS_USE_NANDFLASH
+at91sam9x5ek_dataflash       arm         arm926ejs   at91sam9x5ek        atmel          at91        at91sam9x5ek:AT91SAM9X5,SYS_USE_DATAFLASH
 at91sam9x5ek_spiflash        arm         arm926ejs   at91sam9x5ek        atmel          at91        at91sam9x5ek:AT91SAM9X5,SYS_USE_SPIFLASH
 at91sam9x5ek_mmc             arm         arm926ejs   at91sam9x5ek        atmel          at91        at91sam9x5ek:AT91SAM9X5,SYS_USE_MMC
 at91sam9xeek_dataflash_cs0   arm         arm926ejs   at91sam9260ek       atmel          at91        at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS0
@@ -171,6 +172,7 @@ netspace_lite_v2             arm         arm926ejs   netspace_v2         LaCie
 netspace_max_v2              arm         arm926ejs   netspace_v2         LaCie          kirkwood	lacie_kw:NETSPACE_MAX_V2
 netspace_mini_v2             arm         arm926ejs   netspace_v2         LaCie          kirkwood	lacie_kw:NETSPACE_MINI_V2
 netspace_v2                  arm         arm926ejs   netspace_v2         LaCie          kirkwood	lacie_kw:NETSPACE_V2
+wireless_space               arm         arm926ejs   wireless_space      LaCie          kirkwood
 dreamplug                    arm         arm926ejs   -                   Marvell        kirkwood
 guruplug                     arm         arm926ejs   -                   Marvell        kirkwood
 mv88f6281gtw_ge              arm         arm926ejs   -                   Marvell        kirkwood

common/cmd_mem.c

@@ -33,6 +33,9 @@
 #include <dataflash.h>
 #endif
 #include <watchdog.h>
+#include <linux/compiler.h>
+
+DECLARE_GLOBAL_DATA_PTR;
 
 static int mod_mem(cmd_tbl_t *, int, int, int, char * const []);
 
@@ -1203,6 +1206,22 @@ U_BOOT_CMD(
 
 #endif
 
+#ifdef CONFIG_CMD_MEMINFO
+__weak void board_show_dram(ulong size)
+{
+	puts("DRAM:  ");
+	print_size(size, "\n");
+}
+
+static int do_mem_info(cmd_tbl_t *cmdtp, int flag, int argc,
+		       char * const argv[])
+{
+	board_show_dram(gd->ram_size);
+
+	return 0;
+}
+#endif
+
 U_BOOT_CMD(
 	base,	2,	1,	do_mem_base,
 	"print or set address offset",
@@ -1243,3 +1262,11 @@ U_BOOT_CMD(
 	"[.b, .w, .l] address value delay(ms)"
 );
 #endif /* CONFIG_MX_CYCLIC */
+
+#ifdef CONFIG_CMD_MEMINFO
+U_BOOT_CMD(
+	meminfo,	3,	1,	do_mem_info,
+	"display memory information",
+	""
+);
+#endif

common/cmd_sound.c

@@ -33,7 +33,7 @@ static int do_init(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
 {
 	int ret;
 
-	ret = sound_init();
+	ret = sound_init(gd->fdt_blob);
 	if (ret) {
 		printf("Initialise Audio driver failed\n");
 		return CMD_RET_FAILURE;

common/lcd.c

@@ -888,7 +888,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 	}
 
 	/* We support displaying 8bpp BMPs on 16bpp LCDs */
-	if (bpix != bmp_bpix && (bmp_bpix != 8 || bpix != 16 || bpix != 32)) {
+	if (bpix != bmp_bpix && !(bmp_bpix == 8 && bpix == 16)) {
 		printf ("Error: %d bit/pixel mode, but BMP has %d bit/pixel\n",
 			bpix,
 			le16_to_cpu(bmp->header.bit_count));

doc/README.watchdog

@@ -0,0 +1,29 @@
+Watchdog driver general info
+
+CONFIG_HW_WATCHDOG
+	This enables hw_watchdog_reset to be called during various loops,
+	including waiting for a character on a serial port. But it
+	does not also call hw_watchdog_init. Boards which want this
+	enabled must call this function in their board file. This split
+	is useful because some rom's enable the watchdog when downloading
+	new code, so it must be serviced, but the board would rather it
+	was off. And, it cannot always be turned off once on.
+
+CONFIG_WATCHDOG_TIMEOUT_MSECS
+	Can be used to change the timeout for i.mx31/35/5x/6x.
+	If not given, will default to maximum timeout. This would
+	be 128000 msec for i.mx31/35/5x/6x.
+
+CONFIG_AT91SAM9_WATCHDOG
+	Available for AT91SAM9 to service the watchdog.
+
+CONFIG_FTWDT010_WATCHDOG
+	Available for FTWDT010 to service the watchdog.
+
+CONFIG_FTWDT010_HW_TIMEOUT
+	Can be used to change the timeout for FTWDT010.
+
+CONFIG_IMX_WATCHDOG
+	Available for i.mx31/35/5x/6x to service the watchdog. This is not
+	automatically set because some boards (vision2) still need to define
+	their own hw_watchdog_reset routine.

doc/device-tree-bindings/exynos/isp-spi.txt

@@ -0,0 +1,22 @@
+Exynos ISP SPI Subsystem
+
+The device node for ISP SPI subsytem.
+Since Peripheral id in EXYNOS is decoded based on Interrupts, currently
+ISP SPI have no individual interrupts hence we add ad dummy interrupt node
+which will have a value beyond the maximum number of interrupts exynos5 can
+support.
+
+Required properties :
+ - compatible : Should be "samsung,exynos-spi" for spi.
+ - reg : Base adrress of the the subsystem.
+ - interrupts : A value which is beyond the maximum number of interrupts
+exynos5 can support.
+
+Example:
+spi@131a0000 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	compatible = "samsung,exynos-spi";
+	reg = <0x131a0000 0x30>;
+	interrupts = <0 129 0>;
+};

doc/device-tree-bindings/exynos/sound.txt

@@ -0,0 +1,27 @@
+Exynos Sound Subsystem
+
+The device node for sound subsytem which contains codec and i2s block
+that is a part of Exynos5250
+
+Required properties :
+ - compatible : Should be "samsung,exynos-sound" for sound
+ - samsung,i2s-epll-clock-frequency : epll clock output frequency in Hz
+ - samsung,i2s-sampling-rate : sampling rate, default is 48000
+ - samsung,i2s-bits-per-sample : sample width, defalut is 16 bit
+ - samsung,i2s-channels : nummber of channels, default is 2
+ - samsung,i2s-lr-clk-framesize : lr clock frame size
+ - samsung,i2s-bit-clk-framesize : bit clock frame size
+ - samsung,codec-type : sound codec type
+
+Example:
+
+sound@12d60000 {
+	compatible = "samsung,exynos-sound"
+	samsung,i2s-epll-clock-frequency = <192000000>;
+	samsung,i2s-sampling-rate = <48000>;
+	samsung,i2s-bits-per-sample = <16>;
+	samsung,i2s-channels = <2>;
+	samsung,i2s-lr-clk-framesize = <256>;
+	samsung,i2s-bit-clk-framesize = <32>;
+	samsung,codec-type = "wm8994";
+};

drivers/i2c/s3c24x0_i2c.c

@@ -27,9 +27,11 @@
  */
 
 #include <common.h>
+#include <fdtdec.h>
 #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
 #include <asm/arch/clk.h>
 #include <asm/arch/cpu.h>
+#include <asm/arch/pinmux.h>
 #else
 #include <asm/arch/s3c24x0_cpu.h>
 #endif
@@ -60,7 +62,16 @@
 #define I2C_TIMEOUT 1		/* 1 second */
 
 
-static unsigned int g_current_bus;	/* Stores Current I2C Bus */
+/*
+ * For SPL boot some boards need i2c before SDRAM is initialised so force
+ * variables to live in SRAM
+ */
+static unsigned int g_current_bus __attribute__((section(".data")));
+#ifdef CONFIG_OF_CONTROL
+static int i2c_busses __attribute__((section(".data")));
+static struct s3c24x0_i2c_bus i2c_bus[CONFIG_MAX_I2C_NUM]
+			__attribute__((section(".data")));
+#endif
 
 #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
 static int GetI2CSDA(void)
@@ -512,4 +523,76 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
 		(i2c, I2C_WRITE, chip << 1, &xaddr[4 - alen], alen, buffer,
 		 len) != 0);
 }
+
+#ifdef CONFIG_OF_CONTROL
+void board_i2c_init(const void *blob)
+{
+	int node_list[CONFIG_MAX_I2C_NUM];
+	int count, i;
+
+	count = fdtdec_find_aliases_for_id(blob, "i2c",
+		COMPAT_SAMSUNG_S3C2440_I2C, node_list,
+		CONFIG_MAX_I2C_NUM);
+
+	for (i = 0; i < count; i++) {
+		struct s3c24x0_i2c_bus *bus;
+		int node = node_list[i];
+
+		if (node <= 0)
+			continue;
+		bus = &i2c_bus[i];
+		bus->regs = (struct s3c24x0_i2c *)
+			fdtdec_get_addr(blob, node, "reg");
+		bus->id = pinmux_decode_periph_id(blob, node);
+		bus->node = node;
+		bus->bus_num = i2c_busses++;
+		exynos_pinmux_config(bus->id, 0);
+	}
+}
+
+static struct s3c24x0_i2c_bus *get_bus(unsigned int bus_idx)
+{
+	if (bus_idx < i2c_busses)
+		return &i2c_bus[bus_idx];
+
+	debug("Undefined bus: %d\n", bus_idx);
+	return NULL;
+}
+
+int i2c_get_bus_num_fdt(int node)
+{
+	int i;
+
+	for (i = 0; i < i2c_busses; i++) {
+		if (node == i2c_bus[i].node)
+			return i;
+	}
+
+	debug("%s: Can't find any matched I2C bus\n", __func__);
+	return -1;
+}
+
+int i2c_reset_port_fdt(const void *blob, int node)
+{
+	struct s3c24x0_i2c_bus *i2c;
+	int bus;
+
+	bus = i2c_get_bus_num_fdt(node);
+	if (bus < 0) {
+		debug("could not get bus for node %d\n", node);
+		return -1;
+	}
+
+	i2c = get_bus(bus);
+	if (!i2c) {
+		debug("get_bus() failed for node node %d\n", node);
+		return -1;
+	}
+
+	i2c_ch_init(i2c->regs, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+	return 0;
+}
+#endif
+
 #endif /* CONFIG_HARD_I2C */

drivers/i2c/s3c24x0_i2c.h

@@ -30,4 +30,11 @@ struct s3c24x0_i2c {
 	u32	iicds;
 	u32	iiclc;
 };
+
+struct s3c24x0_i2c_bus {
+	int node;	/* device tree node */
+	int bus_num;	/* i2c bus number */
+	struct s3c24x0_i2c *regs;
+	int id;
+};
 #endif /* _S3C24X0_I2C_H */

drivers/net/phy/mv88e61xx.c

@@ -26,6 +26,14 @@
 #include <netdev.h>
 #include "mv88e61xx.h"
 
+/*
+ * Uncomment either of the following line for local debug control;
+ * otherwise global debug control will apply.
+ */
+
+/* #undef DEBUG */
+/* #define DEBUG */
+
 #ifdef CONFIG_MV88E61XX_MULTICHIP_ADRMODE
 /* Chip Address mode
  * The Switch support two modes of operation
@@ -52,7 +60,8 @@ static int mv88e61xx_busychk_multic(char *name, u32 devaddr)
 	return 0;
 }
 
-static void mv88e61xx_wr_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 data)
+static void mv88e61xx_switch_write(char *name, u32 phy_adr,
+	u32 reg_ofs, u16 data)
 {
 	u16 mii_dev_addr;
 
@@ -70,7 +79,8 @@ static void mv88e61xx_wr_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 data)
 									 15));
 }
 
-static void mv88e61xx_rd_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 * data)
+static void mv88e61xx_switch_read(char *name, u32 phy_adr,
+	u32 reg_ofs, u16 *data)
 {
 	u16 mii_dev_addr;
 
@@ -90,110 +100,51 @@ static void mv88e61xx_rd_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 * data)
 }
 #endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */
 
-static void mv88e61xx_port_vlan_config(struct mv88e61xx_config *swconfig,
-				       u32 max_prtnum, u32 ports_ofs)
+/*
+ * Convenience macros for switch device/port reads/writes
+ * These macros output valid 'mv88e61xx' U_BOOT_CMDs
+ */
+
+#ifndef DEBUG
+#define WR_SWITCH_REG wr_switch_reg
+#define RD_SWITCH_REG rd_switch_reg
+#define WR_SWITCH_PORT_REG(n, p, r, d) \
+	WR_SWITCH_REG(n, (MV88E61XX_PRT_OFST+p), r, d)
+#define RD_SWITCH_PORT_REG(n, p, r, d) \
+	RD_SWITCH_REG(n, (MV88E61XX_PRT_OFST+p), r, d)
+#else
+static void WR_SWITCH_REG(char *name, u32 dev_adr, u32 reg_ofs, u16 data)
 {
-	u32 prt;
-	u16 reg;
-	char *name = swconfig->name;
-	u32 cpu_port = swconfig->cpuport;
-	u32 port_mask = swconfig->ports_enabled;
-	enum mv88e61xx_cfg_vlan vlancfg = swconfig->vlancfg;
-
-	/* be sure all ports are disabled */
-	for (prt = 0; prt < max_prtnum; prt++) {
-		RD_PHY(name, ports_ofs + prt, MV88E61XX_PRT_CTRL_REG, &reg);
-		reg &= ~0x3;
-		WR_PHY(name, ports_ofs + prt, MV88E61XX_PRT_CTRL_REG, reg);
-
-		if (!(cpu_port & (1 << prt)))
-			continue;
-		/* Set CPU port VID to 0x1 */
-		RD_PHY(name, (ports_ofs + prt), MV88E61XX_PRT_VID_REG, &reg);
-		reg &= ~0xfff;
-		reg |= 0x1;
-		WR_PHY(name, (ports_ofs + prt), MV88E61XX_PRT_VID_REG, reg);
-	}
-
-	/* Setting  Port default priority for all ports to zero */
-	for (prt = 0; prt < max_prtnum; prt++) {
-		RD_PHY(name, ports_ofs + prt, MV88E61XX_PRT_VID_REG, &reg);
-		reg &= ~0xc000;
-		WR_PHY(name, ports_ofs + prt, MV88E61XX_PRT_VID_REG, reg);
-	}
-	/* Setting VID and VID map for all ports except CPU port */
-	for (prt = 0; prt < max_prtnum; prt++) {
-		/* only for enabled ports */
-		if ((1 << prt) & port_mask) {
-			/* skip CPU port */
-			if ((1 << prt) & cpu_port) {
-				/*
-				 * Set Vlan map table for cpu_port to see
-				 * all ports
-				 */
-				RD_PHY(name, (ports_ofs + prt),
-				       MV88E61XX_PRT_VMAP_REG, &reg);
-				reg &= ~((1 << max_prtnum) - 1);
-				reg |= port_mask & ~(1 << prt);
-				WR_PHY(name, (ports_ofs + prt),
-				       MV88E61XX_PRT_VMAP_REG, reg);
-			} else {
-
-				/*
-				 *  set Ports VLAN Mapping.
-				 *      port prt <--> cpu_port VLAN #prt+1.
-				 */
-				RD_PHY(name, ports_ofs + prt,
-				       MV88E61XX_PRT_VID_REG, &reg);
-				reg &= ~0x0fff;
-				reg |= (prt + 1);
-				WR_PHY(name, ports_ofs + prt,
-				       MV88E61XX_PRT_VID_REG, reg);
-
-				RD_PHY(name, ports_ofs + prt,
-				       MV88E61XX_PRT_VMAP_REG, &reg);
-				if (vlancfg == MV88E61XX_VLANCFG_DEFAULT) {
-					/*
-					 * all any port can send frames to all other ports
-					 * ref: sec 3.2.1.1 of datasheet
-					 */
-					reg |= 0x03f;
-					reg &= ~(1 << prt);
-				} else if (vlancfg == MV88E61XX_VLANCFG_ROUTER) {
-					/*
-					 * all other ports can send frames to CPU port only
-					 * ref: sec 3.2.1.2 of datasheet
-					 */
-					reg &= ~((1 << max_prtnum) - 1);
-					reg |= cpu_port;
-				}
-				WR_PHY(name, ports_ofs + prt,
-				       MV88E61XX_PRT_VMAP_REG, reg);
-			}
-		}
-	}
-
-	/*
-	 * enable only appropriate ports to forwarding mode
-	 * and disable the others
-	 */
-	for (prt = 0; prt < max_prtnum; prt++) {
-		if ((1 << prt) & port_mask) {
-			RD_PHY(name, ports_ofs + prt,
-			       MV88E61XX_PRT_CTRL_REG, &reg);
-			reg |= 0x3;
-			WR_PHY(name, ports_ofs + prt,
-			       MV88E61XX_PRT_CTRL_REG, reg);
-		} else {
-			/* Disable port */
-			RD_PHY(name, ports_ofs + prt,
-			       MV88E61XX_PRT_CTRL_REG, &reg);
-			reg &= ~0x3;
-			WR_PHY(name, ports_ofs + prt,
-			       MV88E61XX_PRT_CTRL_REG, reg);
-		}
-	}
+	printf("mv88e61xx %s dev %02x reg %02x write %04x\n",
+		name, dev_adr, reg_ofs, data);
+	wr_switch_reg(name, dev_adr, reg_ofs, data);
 }
+static void RD_SWITCH_REG(char *name, u32 dev_adr, u32 reg_ofs, u16 *data)
+{
+	rd_switch_reg(name, dev_adr, reg_ofs, data);
+	printf("mv88e61xx %s dev %02x reg %02x read %04x\n",
+		name, dev_adr, reg_ofs, *data);
+}
+static void WR_SWITCH_PORT_REG(char *name, u32 prt_adr, u32 reg_ofs,
+	u16 data)
+{
+	printf("mv88e61xx %s port %02x reg %02x write %04x\n",
+		name, prt_adr, reg_ofs, data);
+	wr_switch_reg(name, (MV88E61XX_PRT_OFST+prt_adr), reg_ofs, data);
+}
+static void RD_SWITCH_PORT_REG(char *name, u32 prt_adr, u32 reg_ofs,
+	u16 *data)
+{
+	rd_switch_reg(name, (MV88E61XX_PRT_OFST+prt_adr), reg_ofs, data);
+	printf("mv88e61xx %s port %02x reg %02x read %04x\n",
+		name, prt_adr, reg_ofs, *data);
+}
+#endif
+
+/*
+ * Local functions to read/write registers on the switch PHYs.
+ * NOTE! This goes through switch, not direct miiphy, writes and reads!
+ */
 
 /*
  * Make sure SMIBusy bit cleared before another
@@ -204,7 +155,7 @@ static int mv88e61xx_busychk(char *name)
 	u16 reg = 0;
 	u32 timeout = MV88E61XX_PHY_TIMEOUT;
 	do {
-		RD_PHY(name, MV88E61XX_GLB2REG_DEVADR,
+		rd_switch_reg(name, MV88E61XX_GLB2REG_DEVADR,
 		       MV88E61XX_PHY_CMD, &reg);
 		if (timeout-- == 0) {
 			printf("SMI busy timeout\n");
@@ -214,34 +165,110 @@ static int mv88e61xx_busychk(char *name)
 	return 0;
 }
 
+static inline int mv88e61xx_switch_miiphy_write(char *name, u32 phy,
+	u32 reg, u16 data)
+{
+	/* write switch data reg then cmd reg then check completion */
+	wr_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA,
+		data);
+	wr_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_CMD,
+		(MV88E61XX_PHY_WRITE_CMD | (phy << 5)  | reg));
+	return mv88e61xx_busychk(name);
+}
+
+static inline int mv88e61xx_switch_miiphy_read(char *name, u32 phy,
+	u32 reg, u16 *data)
+{
+	/* write switch cmd reg, check for completion */
+	wr_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_CMD,
+		(MV88E61XX_PHY_READ_CMD | (phy << 5)  | reg));
+	if (mv88e61xx_busychk(name))
+		return -1;
+	/* read switch data reg and return success */
+	rd_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, data);
+	return 0;
+}
+
+/*
+ * Convenience macros for switch PHY reads/writes
+ */
+
+#ifndef DEBUG
+#define WR_SWITCH_PHY_REG mv88e61xx_switch_miiphy_write
+#define RD_SWITCH_PHY_REG mv88e61xx_switch_miiphy_read
+#else
+static inline int WR_SWITCH_PHY_REG(char *name, u32 phy_adr,
+	u32 reg_ofs, u16 data)
+{
+	int r = mv88e61xx_switch_miiphy_write(name, phy_adr, reg_ofs, data);
+	if (r)
+		printf("** ERROR writing mv88e61xx %s phy %02x reg %02x\n",
+			name, phy_adr, reg_ofs);
+	else
+		printf("mv88e61xx %s phy %02x reg %02x write %04x\n",
+			name, phy_adr, reg_ofs, data);
+	return r;
+}
+static inline int RD_SWITCH_PHY_REG(char *name, u32 phy_adr,
+	u32 reg_ofs, u16 *data)
+{
+	int r = mv88e61xx_switch_miiphy_read(name, phy_adr, reg_ofs, data);
+	if (r)
+		printf("** ERROR reading mv88e61xx %s phy %02x reg %02x\n",
+			name, phy_adr, reg_ofs);
+	else
+		printf("mv88e61xx %s phy %02x reg %02x read %04x\n",
+			name, phy_adr, reg_ofs, *data);
+	return r;
+}
+#endif
+
+static void mv88e61xx_port_vlan_config(struct mv88e61xx_config *swconfig)
+{
+	u32 prt;
+	u16 reg;
+	char *name = swconfig->name;
+	u32 port_mask = swconfig->ports_enabled;
+
+	/* apply internal vlan config */
+	for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) {
+		/* only for enabled ports */
+		if ((1 << prt) & port_mask) {
+			/* take vlan map from swconfig */
+			u8 vlanmap = swconfig->vlancfg[prt];
+			/* remove disabled ports from vlan map */
+			vlanmap &= swconfig->ports_enabled;
+			/* apply vlan map to port */
+			RD_SWITCH_PORT_REG(name, prt,
+				MV88E61XX_PRT_VMAP_REG, &reg);
+			reg &= ~((1 << MV88E61XX_MAX_PORTS_NUM) - 1);
+			reg |= vlanmap;
+			WR_SWITCH_PORT_REG(name, prt,
+				MV88E61XX_PRT_VMAP_REG, reg);
+		}
+	}
+}
+
 /*
  * Power up the specified port and reset PHY
  */
-static int mv88361xx_powerup(struct mv88e61xx_config *swconfig, u32 prt)
+static int mv88361xx_powerup(struct mv88e61xx_config *swconfig, u32 phy)
 {
 	char *name = swconfig->name;
 
-	/* Write Copper Specific control reg1 (0x14) for-
+	/* Write Copper Specific control reg1 (0x10) for-
 	 * Enable Phy power up
 	 * Energy Detect on (sense&Xmit NLP Periodically
 	 * reset other settings default
 	 */
-	WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, 0x3360);
-	WR_PHY(name, MV88E61XX_GLB2REG_DEVADR,
-	       MV88E61XX_PHY_CMD, (0x9410 | (prt << 5)));
-
-	if (mv88e61xx_busychk(name))
+	if (WR_SWITCH_PHY_REG(name, phy, 0x10, 0x3360))
 		return -1;
 
 	/* Write PHY ctrl reg (0x0) to apply
 	 * Phy reset (set bit 15 low)
 	 * reset other default values
 	 */
-	WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, 0x1140);
-	WR_PHY(name, MV88E61XX_GLB2REG_DEVADR,
-	       MV88E61XX_PHY_CMD, (0x9400 | (prt << 5)));
-
-	if (mv88e61xx_busychk(name))
+	if (WR_SWITCH_PHY_REG(name, phy, 0x00, 0x9140))
 		return -1;
 
 	return 0;
@@ -256,48 +283,26 @@ static int mv88361xx_powerup(struct mv88e61xx_config *swconfig, u32 prt)
  * to setup PHY LEDs default configuration to detect 10/100/1000Mb/s
  * Link status
  */
-static int mv88361xx_led_init(struct mv88e61xx_config *swconfig, u32 prt)
+static int mv88361xx_led_init(struct mv88e61xx_config *swconfig, u32 phy)
 {
 	char *name = swconfig->name;
-	u16 reg;
 
 	if (swconfig->led_init != MV88E61XX_LED_INIT_EN)
 		return 0;
 
 	/* set page address to 3 */
-	reg = 3;
-	WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, reg);
-	WR_PHY(name, MV88E61XX_GLB2REG_DEVADR,
-	       MV88E61XX_PHY_CMD, (1 << MV88E61XX_BUSY_OFST |
-				   1 << MV88E61XX_MODE_OFST |
-				   1 << MV88E61XX_OP_OFST |
-				   prt << MV88E61XX_ADDR_OFST | 22));
-
-	if (mv88e61xx_busychk(name))
+	if (WR_SWITCH_PHY_REG(name, phy, 0x16, 0x0003))
 		return -1;
 
-	/* set LED Func Ctrl reg */
-	reg = 1;	/* LED[0] On-Link, Blink-Activity, Off-NoLink */
-	WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, reg);
-	WR_PHY(name, MV88E61XX_GLB2REG_DEVADR,
-	       MV88E61XX_PHY_CMD, (1 << MV88E61XX_BUSY_OFST |
-				   1 << MV88E61XX_MODE_OFST |
-				   1 << MV88E61XX_OP_OFST |
-				   prt << MV88E61XX_ADDR_OFST | 16));
-
-	if (mv88e61xx_busychk(name))
+	/*
+	 * set LED Func Ctrl reg
+	 * value 0x0001 = LED[0] On-Link, Blink-Activity, Off-NoLink
+	 */
+	if (WR_SWITCH_PHY_REG(name, phy, 0x10, 0x0001))
 		return -1;
 
 	/* set page address to 0 */
-	reg = 0;
-	WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, reg);
-	WR_PHY(name, MV88E61XX_GLB2REG_DEVADR,
-	       MV88E61XX_PHY_CMD, (1 << MV88E61XX_BUSY_OFST |
-				   1 << MV88E61XX_MODE_OFST |
-				   1 << MV88E61XX_OP_OFST |
-				   prt << MV88E61XX_ADDR_OFST | 22));
-
-	if (mv88e61xx_busychk(name))
+	if (WR_SWITCH_PHY_REG(name, phy, 0x16, 0x0000))
 		return -1;
 
 	return 0;
@@ -312,23 +317,15 @@ static int mv88361xx_led_init(struct mv88e61xx_config *swconfig, u32 prt)
  * This is optional settings may be needed on some boards
  * for PHY<->magnetics h/w tuning
  */
-static int mv88361xx_reverse_mdipn(struct mv88e61xx_config *swconfig, u32 prt)
+static int mv88361xx_reverse_mdipn(struct mv88e61xx_config *swconfig, u32 phy)
 {
 	char *name = swconfig->name;
-	u16 reg;
 
 	if (swconfig->mdip != MV88E61XX_MDIP_REVERSE)
 		return 0;
 
-	reg = 0x0f;		/*Reverse MDIP/N[3:0] bits */
-	WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, reg);
-	WR_PHY(name, MV88E61XX_GLB2REG_DEVADR,
-	       MV88E61XX_PHY_CMD, (1 << MV88E61XX_BUSY_OFST |
-				   1 << MV88E61XX_MODE_OFST |
-				   1 << MV88E61XX_OP_OFST |
-				   prt << MV88E61XX_ADDR_OFST | 20));
-
-	if (mv88e61xx_busychk(name))
+	/*Reverse MDIP/N[3:0] bits */
+	if (WR_SWITCH_PHY_REG(name, phy, 0x14, 0x000f))
 		return -1;
 
 	return 0;
@@ -343,6 +340,7 @@ int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig)
 	u16 reg;
 	char *idstr;
 	char *name = swconfig->name;
+	int time;
 
 	if (miiphy_set_current_dev(name)) {
 		printf("%s failed\n", __FUNCTION__);
@@ -354,7 +352,7 @@ int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig)
 		printf("Invalid cpu port config, using default port5\n");
 	}
 
-	RD_PHY(name, MV88E61XX_PRT_OFST, MII_PHYSID2, &reg);
+	RD_SWITCH_PORT_REG(name, 0, MII_PHYSID2, &reg);
 	switch (reg &= 0xfff0) {
 	case 0x1610:
 		idstr = "88E6161";
@@ -373,46 +371,183 @@ int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig)
 		break;
 	}
 
-	/* Port based VLANs configuration */
-	if ((swconfig->vlancfg == MV88E61XX_VLANCFG_DEFAULT)
-	    || (swconfig->vlancfg == MV88E61XX_VLANCFG_ROUTER))
-		mv88e61xx_port_vlan_config(swconfig, MV88E61XX_MAX_PORTS_NUM,
-					   MV88E61XX_PRT_OFST);
-	else {
-		printf("Unsupported mode %s failed\n", __FUNCTION__);
-		return -1;
+	/* be sure all ports are disabled */
+	for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) {
+		RD_SWITCH_PORT_REG(name, prt, MV88E61XX_PRT_CTRL_REG, &reg);
+		reg &= ~0x3;
+		WR_SWITCH_PORT_REG(name, prt, MV88E61XX_PRT_CTRL_REG, reg);
 	}
 
+	/* wait 2 ms for queues to drain */
+	udelay(2000);
+
+	/* reset switch */
+	RD_SWITCH_REG(name, MV88E61XX_GLBREG_DEVADR, MV88E61XX_SGCR, &reg);
+	reg |= 0x8000;
+	WR_SWITCH_REG(name, MV88E61XX_GLBREG_DEVADR, MV88E61XX_SGCR, reg);
+
+	/* wait up to 1 second for switch reset complete */
+	for (time = 1000; time; time--) {
+		RD_SWITCH_REG(name, MV88E61XX_GLBREG_DEVADR, MV88E61XX_SGSR,
+			&reg);
+		if ((reg & 0xc800) == 0xc800)
+			break;
+		udelay(1000);
+	}
+	if (!time)
+		return -1;
+
+	/* Port based VLANs configuration */
+	mv88e61xx_port_vlan_config(swconfig);
+
 	if (swconfig->rgmii_delay == MV88E61XX_RGMII_DELAY_EN) {
 		/*
 		 * Enable RGMII delay on Tx and Rx for CPU port
 		 * Ref: sec 9.5 of chip datasheet-02
 		 */
-		WR_PHY(name, MV88E61XX_PRT_OFST + 5,
-		       MV88E61XX_RGMII_TIMECTRL_REG, 0x18);
-		WR_PHY(name, MV88E61XX_PRT_OFST + 4,
-		       MV88E61XX_RGMII_TIMECTRL_REG, 0xc1e7);
+		/*Force port link down */
+		WR_SWITCH_PORT_REG(name, 5, MV88E61XX_PCS_CTRL_REG, 0x10);
+		/* configure port RGMII delay */
+		WR_SWITCH_PORT_REG(name, 4,
+			MV88E61XX_RGMII_TIMECTRL_REG, 0x81e7);
+		RD_SWITCH_PORT_REG(name, 5,
+			MV88E61XX_RGMII_TIMECTRL_REG, &reg);
+		WR_SWITCH_PORT_REG(name, 5,
+			MV88E61XX_RGMII_TIMECTRL_REG, reg | 0x18);
+		WR_SWITCH_PORT_REG(name, 4,
+			MV88E61XX_RGMII_TIMECTRL_REG, 0xc1e7);
+		/* Force port to RGMII FDX 1000Base then up */
+		WR_SWITCH_PORT_REG(name, 5, MV88E61XX_PCS_CTRL_REG, 0x1e);
+		WR_SWITCH_PORT_REG(name, 5, MV88E61XX_PCS_CTRL_REG, 0x3e);
 	}
 
 	for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) {
-		if (!((1 << prt) & swconfig->cpuport)) {
 
-			if (mv88361xx_led_init(swconfig, prt))
+		/* configure port's PHY */
+		if (!((1 << prt) & swconfig->cpuport)) {
+			/* port 4 has phy 6, not 4 */
+			int phy = (prt == 4) ? 6 : prt;
+			if (mv88361xx_powerup(swconfig, phy))
 				return -1;
-			if (mv88361xx_reverse_mdipn(swconfig, prt))
+			if (mv88361xx_reverse_mdipn(swconfig, phy))
 				return -1;
-			if (mv88361xx_powerup(swconfig, prt))
+			if (mv88361xx_led_init(swconfig, phy))
 				return -1;
 		}
 
+		/* set port VID to port+1 except for cpu port */
+		if (!((1 << prt) & swconfig->cpuport)) {
+			RD_SWITCH_PORT_REG(name, prt,
+				MV88E61XX_PRT_VID_REG, &reg);
+			WR_SWITCH_PORT_REG(name, prt,
+				MV88E61XX_PRT_VID_REG,
+				(reg & ~1023) | (prt+1));
+		}
+
 		/*Program port state */
-		RD_PHY(name, MV88E61XX_PRT_OFST + prt,
-		       MV88E61XX_PRT_CTRL_REG, &reg);
-		WR_PHY(name, MV88E61XX_PRT_OFST + prt,
-		       MV88E61XX_PRT_CTRL_REG,
-		       reg | (swconfig->portstate & 0x03));
+		RD_SWITCH_PORT_REG(name, prt,
+			MV88E61XX_PRT_CTRL_REG, &reg);
+		WR_SWITCH_PORT_REG(name, prt,
+			MV88E61XX_PRT_CTRL_REG,
+			reg | (swconfig->portstate & 0x03));
+
 	}
 
 	printf("%s Initialized on %s\n", idstr, name);
 	return 0;
 }
+
+#ifdef CONFIG_MV88E61XX_CMD
+static int
+do_switch(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	char *name, *endp;
+	int write = 0;
+	enum { dev, prt, phy } target = dev;
+	u32 addrlo, addrhi, addr;
+	u32 reglo, reghi, reg;
+	u16 data, rdata;
+
+	if (argc < 7)
+		return -1;
+
+	name = argv[1];
+
+	if (strcmp(argv[2], "phy") == 0)
+		target = phy;
+	else if (strcmp(argv[2], "port") == 0)
+		target = prt;
+	else if (strcmp(argv[2], "dev") != 0)
+		return 1;
+
+	addrlo = simple_strtoul(argv[3], &endp, 16);
+
+	if (!*endp) {
+		addrhi = addrlo;
+	} else {
+		while (*endp < '0' || *endp > '9')
+			endp++;
+		addrhi = simple_strtoul(endp, NULL, 16);
+	}
+
+	reglo = simple_strtoul(argv[5], &endp, 16);
+	if (!*endp) {
+		reghi = reglo;
+	} else {
+		while (*endp < '0' || *endp > '9')
+			endp++;
+		reghi = simple_strtoul(endp, NULL, 16);
+	}
+
+	if (strcmp(argv[6], "write") == 0)
+		write = 1;
+	else if (strcmp(argv[6], "read") != 0)
+		return 1;
+
+	data = simple_strtoul(argv[7], NULL, 16);
+
+	for (addr = addrlo; addr <= addrhi; addr++) {
+		for (reg = reglo; reg <= reghi; reg++) {
+			if (write) {
+				if (target == phy)
+					mv88e61xx_switch_miiphy_write(
+						name, addr, reg, data);
+				else if (target == prt)
+					wr_switch_reg(name,
+						addr+MV88E61XX_PRT_OFST,
+						reg, data);
+				else
+					wr_switch_reg(name, addr, reg, data);
+			} else {
+				if (target == phy)
+					mv88e61xx_switch_miiphy_read(
+						name, addr, reg, &rdata);
+				else if (target == prt)
+					rd_switch_reg(name,
+						addr+MV88E61XX_PRT_OFST,
+						reg, &rdata);
+				else
+					rd_switch_reg(name, addr, reg, &rdata);
+				printf("%s %s %s %02x %s %02x %s %04x\n",
+					argv[0], argv[1], argv[2], addr,
+					argv[4], reg, argv[6], rdata);
+				if (write && argc == 7 && rdata != data)
+					return 1;
+			}
+		}
+	}
+	return 0;
+}
+
+U_BOOT_CMD(mv88e61xx, 8, 0, do_switch,
+	"Read or write mv88e61xx switch registers",
+	"<ethdevice> dev|port|phy <addr> reg <reg> write <data>\n"
+	"<ethdevice> dev|port|phy <addr> reg <reg> read [<data>]\n"
+	"    - read/write switch device, port or phy at (addr,reg)\n"
+	"      addr=0..0x1C for dev, 0..5 for port or phy.\n"
+	"      reg=0..0x1F.\n"
+	"      data=0..0xFFFF (tested if present against actual read).\n"
+	"      All numeric parameters are assumed to be hex.\n"
+	"      <addr> and <<reg> arguments can be ranges (x..y)"
+);
+#endif /* CONFIG_MV88E61XX_CMD */

drivers/net/phy/mv88e61xx.h

@@ -28,35 +28,50 @@
 #include <miiphy.h>
 
 #define MV88E61XX_CPU_PORT		0x5
-#define MV88E61XX_MAX_PORTS_NUM		0x6
 
 #define MV88E61XX_PHY_TIMEOUT		100000
 
-#define MV88E61XX_PRT_STS_REG		0x1
+/* port dev-addr (= port + 0x10) */
+#define MV88E61XX_PRT_OFST		0x10
+/* port registers */
+#define MV88E61XX_PCS_CTRL_REG		0x1
 #define MV88E61XX_PRT_CTRL_REG		0x4
 #define MV88E61XX_PRT_VMAP_REG		0x6
 #define MV88E61XX_PRT_VID_REG		0x7
+#define MV88E61XX_RGMII_TIMECTRL_REG	0x1A
 
-#define MV88E61XX_PRT_OFST		0x10
+/* global registers dev-addr */
+#define MV88E61XX_GLBREG_DEVADR	0x1B
+/* global registers */
+#define MV88E61XX_SGSR			0x00
+#define MV88E61XX_SGCR			0x04
+
+/* global 2 registers dev-addr */
+#define MV88E61XX_GLB2REG_DEVADR	0x1C
+/* global 2 registers */
 #define MV88E61XX_PHY_CMD		0x18
 #define MV88E61XX_PHY_DATA		0x19
-#define MV88E61XX_RGMII_TIMECTRL_REG	0x1A
-#define MV88E61XX_GLB2REG_DEVADR	0x1C
+/* global 2 phy commands */
+#define MV88E61XX_PHY_WRITE_CMD		0x9400
+#define MV88E61XX_PHY_READ_CMD		0x9800
 
 #define MV88E61XX_BUSY_OFST		15
 #define MV88E61XX_MODE_OFST		12
-#define MV88E61XX_OP_OFST			10
+#define MV88E61XX_OP_OFST		10
 #define MV88E61XX_ADDR_OFST		5
 
 #ifdef CONFIG_MV88E61XX_MULTICHIP_ADRMODE
 static int mv88e61xx_busychk_multic(char *name, u32 devaddr);
-static void mv88e61xx_wr_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 data);
-static void mv88e61xx_rd_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 * data);
-#define WR_PHY mv88e61xx_wr_phy
-#define RD_PHY mv88e61xx_rd_phy
+static void mv88e61xx_switch_write(char *name, u32 phy_adr,
+	u32 reg_ofs, u16 data);
+static void mv88e61xx_switch_read(char *name, u32 phy_adr,
+	u32 reg_ofs, u16 *data);
+#define wr_switch_reg mv88e61xx_switch_write
+#define rd_switch_reg mv88e61xx_switch_read
 #else
-#define WR_PHY miiphy_write
-#define RD_PHY miiphy_read
+/* switch appears a s simple PHY and can thus use miiphy */
+#define wr_switch_reg miiphy_write
+#define rd_switch_reg miiphy_read
 #endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */
 
 #endif /* _MV88E61XX_H */

drivers/power/pmic/pmic_max77686.c

@@ -22,10 +22,14 @@
  */
 
 #include <common.h>
+#include <fdtdec.h>
+#include <i2c.h>
 #include <power/pmic.h>
 #include <power/max77686_pmic.h>
 #include <errno.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int pmic_init(unsigned char bus)
 {
 	static const char name[] = "MAX77686_PMIC";
@@ -36,13 +40,40 @@ int pmic_init(unsigned char bus)
 		return -ENOMEM;
 	}
 
-	puts("Board PMIC init\n");
+#ifdef CONFIG_OF_CONTROL
+	const void *blob = gd->fdt_blob;
+	int node, parent;
+
+	node = fdtdec_next_compatible(blob, 0, COMPAT_MAXIM_MAX77686_PMIC);
+	if (node < 0) {
+		debug("PMIC: No node for PMIC Chip in device tree\n");
+		debug("node = %d\n", node);
+		return -1;
+	}
+
+	parent = fdt_parent_offset(blob, node);
+	if (parent < 0) {
+		debug("%s: Cannot find node parent\n", __func__);
+		return -1;
+	}
+
+	p->bus = i2c_get_bus_num_fdt(parent);
+	if (p->bus < 0) {
+		debug("%s: Cannot find I2C bus\n", __func__);
+		return -1;
+	}
+	p->hw.i2c.addr = fdtdec_get_int(blob, node, "reg", 9);
+#else
+	p->bus = bus;
+	p->hw.i2c.addr = MAX77686_I2C_ADDR;
+#endif
+
 	p->name = name;
 	p->interface = PMIC_I2C;
 	p->number_of_regs = PMIC_NUM_OF_REGS;
-	p->hw.i2c.addr = MAX77686_I2C_ADDR;
 	p->hw.i2c.tx_num = 1;
-	p->bus = bus;
+
+	puts("Board PMIC init\n");
 
 	return 0;
 }

drivers/power/twl4030.c

@@ -71,7 +71,7 @@ void twl4030_pmrecv_vsel_cfg(u8 vsel_reg, u8 vsel_val,
 	ret = twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, vsel_val,
 				vsel_reg);
 	if (ret != 0) {
-		printf("Could could not write vsel to reg %02x (%d)\n",
+		printf("Could not write vsel to reg %02x (%d)\n",
 			vsel_reg, ret);
 		return;
 	}
@@ -80,7 +80,7 @@ void twl4030_pmrecv_vsel_cfg(u8 vsel_reg, u8 vsel_val,
 	ret = twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, dev_grp_sel,
 				dev_grp);
 	if (ret != 0)
-		printf("Could could not write grp_sel to reg %02x (%d)\n",
+		printf("Could not write grp_sel to reg %02x (%d)\n",
 			dev_grp, ret);
 }
 

drivers/serial/ns16550.c

@@ -36,8 +36,10 @@
 
 void NS16550_init(NS16550_t com_port, int baud_divisor)
 {
+#if (!defined(CONFIG_SYS_NS16550_BROKEN_TEMT))
 	while (!(serial_in(&com_port->lsr) & UART_LSR_TEMT))
 		;
+#endif
 
 	serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier);
 #if (defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)) || \

drivers/sound/sound.c

@@ -24,27 +24,82 @@
 #include <malloc.h>
 #include <common.h>
 #include <asm/io.h>
+#include <libfdt.h>
+#include <fdtdec.h>
 #include <i2c.h>
 #include <i2s.h>
 #include <sound.h>
-#include "wm8994.h"
 #include <asm/arch/sound.h>
+#include "wm8994.h"
 
 /* defines */
 #define SOUND_400_HZ 400
 #define SOUND_BITS_IN_BYTE 8
 
 static struct i2stx_info g_i2stx_pri;
-static struct sound_codec_info g_codec_info;
 
 /*
- * get_sound_fdt_values gets fdt values for i2s parameters
+ * get_sound_i2s_values gets values for i2s parameters
  *
  * @param i2stx_info	i2s transmitter transfer param structure
- * @param blob		FDT blob
+ * @param blob		FDT blob if enabled else NULL
  */
-static void get_sound_i2s_values(struct i2stx_info *i2s)
+static int get_sound_i2s_values(struct i2stx_info *i2s, const void *blob)
 {
+#ifdef CONFIG_OF_CONTROL
+	int node;
+	int error = 0;
+	int base;
+
+	node = fdtdec_next_compatible(blob, 0,
+					COMPAT_SAMSUNG_EXYNOS5_SOUND);
+	if (node <= 0) {
+		debug("EXYNOS_SOUND: No node for sound in device tree\n");
+		return -1;
+	}
+
+	/*
+	 * Get the pre-defined sound specific values from FDT.
+	 * All of these are expected to be correct otherwise
+	 * wrong register values in i2s setup parameters
+	 * may result in no sound play.
+	 */
+	base = fdtdec_get_addr(blob, node, "reg");
+	if (base == FDT_ADDR_T_NONE) {
+		debug("%s: Missing  i2s base\n", __func__);
+		return -1;
+	}
+	i2s->base_address = base;
+
+	i2s->audio_pll_clk = fdtdec_get_int(blob,
+				node, "samsung,i2s-epll-clock-frequency", -1);
+	error |= i2s->audio_pll_clk;
+	debug("audio_pll_clk = %d\n", i2s->audio_pll_clk);
+	i2s->samplingrate = fdtdec_get_int(blob,
+				node, "samsung,i2s-sampling-rate", -1);
+	error |= i2s->samplingrate;
+	debug("samplingrate = %d\n", i2s->samplingrate);
+	i2s->bitspersample = fdtdec_get_int(blob,
+				node, "samsung,i2s-bits-per-sample", -1);
+	error |= i2s->bitspersample;
+	debug("bitspersample = %d\n", i2s->bitspersample);
+	i2s->channels = fdtdec_get_int(blob,
+			node, "samsung,i2s-channels", -1);
+	error |= i2s->channels;
+	debug("channels = %d\n", i2s->channels);
+	i2s->rfs = fdtdec_get_int(blob,
+				node, "samsung,i2s-lr-clk-framesize", -1);
+	error |= i2s->rfs;
+	debug("rfs = %d\n", i2s->rfs);
+	i2s->bfs = fdtdec_get_int(blob,
+				node, "samsung,i2s-bit-clk-framesize", -1);
+	error |= i2s->bfs;
+	debug("bfs = %d\n", i2s->bfs);
+	if (error == -1) {
+		debug("fail to get sound i2s node properties\n");
+		return -1;
+	}
+#else
 	i2s->base_address = samsung_get_base_i2s();
 	i2s->audio_pll_clk = I2S_PLL_CLK;
 	i2s->samplingrate = I2S_SAMPLING_RATE;
@@ -52,83 +107,76 @@ static void get_sound_i2s_values(struct i2stx_info *i2s)
 	i2s->channels = I2S_CHANNELS;
 	i2s->rfs = I2S_RFS;
 	i2s->bfs = I2S_BFS;
-}
-
-/*
- * Gets fdt values for wm8994 config parameters
- *
- * @param pcodec_info	codec information structure
- * @param blob		FDT blob
- * @return		int value, 0 for success
- */
-static int get_sound_wm8994_values(struct sound_codec_info *pcodec_info)
-{
-	int error = 0;
-
-	switch (AUDIO_COMPAT) {
-	case AUDIO_COMPAT_SPI:
-		debug("%s: Support not added for SPI interface\n", __func__);
-		return -1;
-		break;
-	case AUDIO_COMPAT_I2C:
-		pcodec_info->i2c_bus = AUDIO_I2C_BUS;
-		pcodec_info->i2c_dev_addr = AUDIO_I2C_REG;
-		debug("i2c dev addr = %d\n", pcodec_info->i2c_dev_addr);
-		break;
-	default:
-		debug("%s: Unknown compat id %d\n", __func__, AUDIO_COMPAT);
-		return -1;
-	}
-
-	if (error == -1) {
-		debug("fail to get wm8994 codec node properties\n");
-		return -1;
-	}
-
+#endif
 	return 0;
 }
 
 /*
- * Gets fdt values for codec config parameters
+ * Init codec
  *
- * @param pcodec_info	codec information structure
- * @param blob		FDT blob
- * @return		int value, 0 for success
+ * @param blob          FDT blob
+ * @param pi2s_tx	i2s parameters required by codec
+ * @return              int value, 0 for success
  */
-static int get_sound_codec_values(struct sound_codec_info *pcodec_info)
+static int codec_init(const void *blob, struct i2stx_info *pi2s_tx)
 {
-	int error = 0;
+	int ret;
 	const char *codectype;
+#ifdef CONFIG_OF_CONTROL
+	int node;
 
-	codectype =  AUDIO_CODEC;
-
-	if (!strcmp(codectype, "wm8994")) {
-		pcodec_info->codec_type = CODEC_WM_8994;
-		error = get_sound_wm8994_values(pcodec_info);
-	} else {
-		error = -1;
+	/* Get the node from FDT for sound */
+	node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SOUND);
+	if (node <= 0) {
+		debug("EXYNOS_SOUND: No node for sound in device tree\n");
+		debug("node = %d\n", node);
+		return -1;
 	}
 
-	if (error == -1) {
-		debug("fail to get sound codec node properties\n");
+	/*
+	 * Get the pre-defined sound codec specific values from FDT.
+	 * All of these are expected to be correct otherwise sound
+	 * can not be played
+	 */
+	codectype = fdt_getprop(blob, node, "samsung,codec-type", NULL);
+	debug("device = %s\n", codectype);
+#else
+	codectype =  AUDIO_CODEC;
+#endif
+	if (!strcmp(codectype, "wm8994")) {
+		/* Check the codec type and initialise the same */
+		ret = wm8994_init(blob, WM8994_AIF2,
+			pi2s_tx->samplingrate,
+			(pi2s_tx->samplingrate * (pi2s_tx->rfs)),
+			pi2s_tx->bitspersample, pi2s_tx->channels);
+	} else {
+		debug("%s: Unknown code type %s\n", __func__,
+		      codectype);
+		return -1;
+	}
+	if (ret) {
+		debug("%s: Codec init failed\n", __func__);
 		return -1;
 	}
 
 	return 0;
 }
 
-int sound_init(void)
+int sound_init(const void *blob)
 {
 	int ret;
 	struct i2stx_info *pi2s_tx = &g_i2stx_pri;
-	struct sound_codec_info *pcodec_info = &g_codec_info;
 
 	/* Get the I2S Values */
-	get_sound_i2s_values(pi2s_tx);
-
-	/* Get the codec Values */
-	if (get_sound_codec_values(pcodec_info) < 0)
+	if (get_sound_i2s_values(pi2s_tx, blob) < 0) {
+		debug(" FDT I2S values failed\n");
 		return -1;
+	}
+
+	if (codec_init(blob, pi2s_tx) < 0) {
+		debug(" Codec init failed\n");
+		return -1;
+	}
 
 	ret = i2s_tx_init(pi2s_tx);
 	if (ret) {
@@ -137,21 +185,6 @@ int sound_init(void)
 		return ret;
 	}
 
-	/* Check the codec type and initialise the same */
-	if (pcodec_info->codec_type == CODEC_WM_8994) {
-		ret = wm8994_init(pcodec_info, WM8994_AIF2,
-			pi2s_tx->samplingrate,
-			(pi2s_tx->samplingrate * (pi2s_tx->rfs)),
-			pi2s_tx->bitspersample, pi2s_tx->channels);
-	} else {
-		debug("%s: Unknown code type %d\n", __func__,
-		      pcodec_info->codec_type);
-		return -1;
-	}
-	if (ret) {
-		debug("%s: Codec init failed\n", __func__);
-		return -1;
-	}
 
 	return ret;
 }

drivers/sound/wm8994.c

@@ -26,9 +26,11 @@
 #include <asm/io.h>
 #include <common.h>
 #include <div64.h>
+#include <fdtdec.h>
 #include <i2c.h>
 #include <i2s.h>
 #include <sound.h>
+#include <asm/arch/sound.h>
 #include "wm8994.h"
 #include "wm8994_registers.h"
 
@@ -77,6 +79,7 @@ static int bclk_divs[] = {
 
 static struct wm8994_priv g_wm8994_info;
 static unsigned char g_wm8994_i2c_dev_addr;
+static struct sound_codec_info g_codec_info;
 
 /*
  * Initialise I2C for wm 8994
@@ -747,13 +750,80 @@ err:
 	return -1;
 }
 
+/*
+ * Gets fdt values for wm8994 config parameters
+ *
+ * @param pcodec_info	codec information structure
+ * @param blob		FDT blob
+ * @return		int value, 0 for success
+ */
+static int get_codec_values(struct sound_codec_info *pcodec_info,
+			const void *blob)
+{
+	int error = 0;
+#ifdef CONFIG_OF_CONTROL
+	enum fdt_compat_id compat;
+	int node;
+	int parent;
+
+	/* Get the node from FDT for codec */
+	node = fdtdec_next_compatible(blob, 0, COMPAT_WOLFSON_WM8994_CODEC);
+	if (node <= 0) {
+		debug("EXYNOS_SOUND: No node for codec in device tree\n");
+		debug("node = %d\n", node);
+		return -1;
+	}
+
+	parent = fdt_parent_offset(blob, node);
+	if (parent < 0) {
+		debug("%s: Cannot find node parent\n", __func__);
+		return -1;
+	}
+
+	compat = fdtdec_lookup(blob, parent);
+	switch (compat) {
+	case COMPAT_SAMSUNG_S3C2440_I2C:
+		pcodec_info->i2c_bus = i2c_get_bus_num_fdt(parent);
+		error |= pcodec_info->i2c_bus;
+		debug("i2c bus = %d\n", pcodec_info->i2c_bus);
+		pcodec_info->i2c_dev_addr = fdtdec_get_int(blob, node,
+							"reg", 0);
+		error |= pcodec_info->i2c_dev_addr;
+		debug("i2c dev addr = %d\n", pcodec_info->i2c_dev_addr);
+		break;
+	default:
+		debug("%s: Unknown compat id %d\n", __func__, compat);
+		return -1;
+	}
+#else
+	pcodec_info->i2c_bus = AUDIO_I2C_BUS;
+	pcodec_info->i2c_dev_addr = AUDIO_I2C_REG;
+	debug("i2c dev addr = %d\n", pcodec_info->i2c_dev_addr);
+#endif
+
+	pcodec_info->codec_type = CODEC_WM_8994;
+
+	if (error == -1) {
+		debug("fail to get wm8994 codec node properties\n");
+		return -1;
+	}
+
+	return 0;
+}
+
 /*wm8994 Device Initialisation */
-int wm8994_init(struct sound_codec_info *pcodec_info,
-			enum en_audio_interface aif_id,
+int wm8994_init(const void *blob, enum en_audio_interface aif_id,
 			int sampling_rate, int mclk_freq,
 			int bits_per_sample, unsigned int channels)
 {
 	int ret = 0;
+	struct sound_codec_info *pcodec_info = &g_codec_info;
+
+	/* Get the codec Values */
+	if (get_codec_values(pcodec_info, blob) < 0) {
+		debug("FDT Codec values failed\n");
+		return -1;
+	}
 
 	/* shift the device address by 1 for 7 bit addressing */
 	g_wm8994_i2c_dev_addr = pcodec_info->i2c_dev_addr;

drivers/sound/wm8994.h

@@ -69,8 +69,7 @@ enum wm8994_type {
 /*
  * intialise wm8994 sound codec device for the given configuration
  *
- * @param pcodec_info		pointer value of the sound codec info structure
- *				parsed from device tree
+ * @param blob			FDT node for codec values
  * @param aif_id		enum value of codec interface port in which
  *				soc i2s is connected
  * @param sampling_rate		Sampling rate ranges between from 8khz to 96khz
@@ -80,8 +79,7 @@ enum wm8994_type {
  *
  * @returns -1 for error  and 0  Success.
  */
-int wm8994_init(struct sound_codec_info *pcodec_info,
-			enum en_audio_interface aif_id,
+int wm8994_init(const void *blob, enum en_audio_interface aif_id,
 			int sampling_rate, int mclk_freq,
 			int bits_per_sample, unsigned int channels);
 #endif /*__WM8994_H__ */

drivers/spi/atmel_spi.c

@@ -92,7 +92,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 	as->slave.cs = cs;
 	as->regs = regs;
 	as->mr = ATMEL_SPI_MR_MSTR | ATMEL_SPI_MR_MODFDIS
-#if defined(CONFIG_AT91SAM9X5)
+#if defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9M10G45)
 			| ATMEL_SPI_MR_WDRBT
 #endif
 			| ATMEL_SPI_MR_PCS(~(1 << cs) & 0xf);

drivers/spi/exynos_spi.c

@@ -20,6 +20,7 @@
 #include <common.h>
 #include <malloc.h>
 #include <spi.h>
+#include <fdtdec.h>
 #include <asm/arch/clk.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/cpu.h>
@@ -28,16 +29,20 @@
 #include <asm/arch-exynos/spi.h>
 #include <asm/io.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* Information about each SPI controller */
 struct spi_bus {
 	enum periph_id periph_id;
 	s32 frequency;		/* Default clock frequency, -1 for none */
 	struct exynos_spi *regs;
 	int inited;		/* 1 if this bus is ready for use */
+	int node;
 };
 
 /* A list of spi buses that we know about */
 static struct spi_bus spi_bus[EXYNOS5_SPI_NUM_CONTROLLERS];
+static unsigned int bus_count;
 
 struct exynos_spi_slave {
 	struct spi_slave slave;
@@ -50,7 +55,7 @@ struct exynos_spi_slave {
 
 static struct spi_bus *spi_get_bus(unsigned dev_index)
 {
-	if (dev_index < EXYNOS5_SPI_NUM_CONTROLLERS)
+	if (dev_index < bus_count)
 		return &spi_bus[dev_index];
 	debug("%s: invalid bus %d", __func__, dev_index);
 
@@ -347,21 +352,100 @@ static inline struct exynos_spi *get_spi_base(int dev_index)
 					(dev_index - 3);
 }
 
+/*
+ * Read the SPI config from the device tree node.
+ *
+ * @param blob  FDT blob to read from
+ * @param node  Node offset to read from
+ * @param bus   SPI bus structure to fill with information
+ * @return 0 if ok, or -FDT_ERR_NOTFOUND if something was missing
+ */
+static int spi_get_config(const void *blob, int node, struct spi_bus *bus)
+{
+	bus->node = node;
+	bus->regs = (struct exynos_spi *)fdtdec_get_addr(blob, node, "reg");
+	bus->periph_id = pinmux_decode_periph_id(blob, node);
+
+	if (bus->periph_id == PERIPH_ID_NONE) {
+		debug("%s: Invalid peripheral ID %d\n", __func__,
+			bus->periph_id);
+		return -FDT_ERR_NOTFOUND;
+	}
+
+	/* Use 500KHz as a suitable default */
+	bus->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
+					500000);
+
+	return 0;
+}
+
+/*
+ * Process a list of nodes, adding them to our list of SPI ports.
+ *
+ * @param blob          fdt blob
+ * @param node_list     list of nodes to process (any <=0 are ignored)
+ * @param count         number of nodes to process
+ * @param is_dvc        1 if these are DVC ports, 0 if standard I2C
+ * @return 0 if ok, -1 on error
+ */
+static int process_nodes(const void *blob, int node_list[], int count)
+{
+	int i;
+
+	/* build the i2c_controllers[] for each controller */
+	for (i = 0; i < count; i++) {
+		int node = node_list[i];
+		struct spi_bus *bus;
+
+		if (node <= 0)
+			continue;
+
+		bus = &spi_bus[i];
+		if (spi_get_config(blob, node, bus)) {
+			printf("exynos spi_init: failed to decode bus %d\n",
+				i);
+			return -1;
+		}
+
+		debug("spi: controller bus %d at %p, periph_id %d\n",
+		      i, bus->regs, bus->periph_id);
+		bus->inited = 1;
+		bus_count++;
+	}
+
+	return 0;
+}
+
 /* Sadly there is no error return from this function */
 void spi_init(void)
 {
-	int i;
+	int count;
+
+#ifdef CONFIG_OF_CONTROL
+	int node_list[EXYNOS5_SPI_NUM_CONTROLLERS];
+	const void *blob = gd->fdt_blob;
+
+	count = fdtdec_find_aliases_for_id(blob, "spi",
+			COMPAT_SAMSUNG_EXYNOS_SPI, node_list,
+			EXYNOS5_SPI_NUM_CONTROLLERS);
+	if (process_nodes(blob, node_list, count))
+		return;
+
+#else
 	struct spi_bus *bus;
 
-	for (i = 0; i < EXYNOS5_SPI_NUM_CONTROLLERS; i++) {
-		bus = &spi_bus[i];
-		bus->regs = get_spi_base(i);
-		bus->periph_id = PERIPH_ID_SPI0 + i;
+	for (count = 0; count < EXYNOS5_SPI_NUM_CONTROLLERS; count++) {
+		bus = &spi_bus[count];
+		bus->regs = get_spi_base(count);
+		bus->periph_id = PERIPH_ID_SPI0 + count;
 
 		/* Although Exynos5 supports upto 50Mhz speed,
 		 * we are setting it to 10Mhz for safe side
 		 */
 		bus->frequency = 10000000;
 		bus->inited = 1;
+		bus->node = 0;
+		bus_count = EXYNOS5_SPI_NUM_CONTROLLERS;
 	}
+#endif
 }

drivers/spi/kirkwood_spi.c

@@ -41,7 +41,10 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 {
 	struct spi_slave *slave;
 	u32 data;
-	u32 kwspi_mpp_config[] = { 0, 0 };
+	static const u32 kwspi_mpp_config[2][2] = {
+		{ MPP0_SPI_SCn, 0 }, /* if cs == 0 */
+		{ MPP7_SPI_SCn, 0 } /* if cs != 0 */
+	};
 
 	if (!spi_cs_is_valid(bus, cs))
 		return NULL;
@@ -68,12 +71,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 	writel(KWSPI_IRQMASK, &spireg->irq_mask);
 
 	/* program mpp registers to select  SPI_CSn */
-	if (cs) {
-		kwspi_mpp_config[0] = MPP7_SPI_SCn;
-	} else {
-		kwspi_mpp_config[0] = MPP0_SPI_SCn;
-	}
-	kirkwood_mpp_conf(kwspi_mpp_config, cs_spi_mpp_back);
+	kirkwood_mpp_conf(kwspi_mpp_config[cs ? 1 : 0], cs_spi_mpp_back);
 
 	return slave;
 }

drivers/usb/host/ehci-exynos.c

@@ -21,13 +21,71 @@
  */
 
 #include <common.h>
+#include <fdtdec.h>
+#include <libfdt.h>
+#include <malloc.h>
 #include <usb.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/ehci.h>
 #include <asm/arch/system.h>
 #include <asm/arch/power.h>
+#include <asm-generic/errno.h>
+#include <linux/compat.h>
 #include "ehci.h"
 
+/* Declare global data pointer */
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+ * Contains pointers to register base addresses
+ * for the usb controller.
+ */
+struct exynos_ehci {
+	struct exynos_usb_phy *usb;
+	unsigned int *hcd;
+};
+
+static int exynos_usb_parse_dt(const void *blob, struct exynos_ehci *exynos)
+{
+	unsigned int node;
+	int depth;
+
+	node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS_EHCI);
+	if (node <= 0) {
+		debug("EHCI: Can't get device node for ehci\n");
+		return -ENODEV;
+	}
+
+	/*
+	 * Get the base address for EHCI controller from the device node
+	 */
+	exynos->hcd = (unsigned int *)fdtdec_get_addr(blob, node, "reg");
+	if (exynos->hcd == NULL) {
+		debug("Can't get the EHCI register address\n");
+		return -ENXIO;
+	}
+
+	depth = 0;
+	node = fdtdec_next_compatible_subnode(blob, node,
+					COMPAT_SAMSUNG_EXYNOS_USB_PHY, &depth);
+	if (node <= 0) {
+		debug("EHCI: Can't get device node for usb-phy controller\n");
+		return -ENODEV;
+	}
+
+	/*
+	 * Get the base address for usbphy from the device node
+	 */
+	exynos->usb = (struct exynos_usb_phy *)fdtdec_get_addr(blob, node,
+								"reg");
+	if (exynos->usb == NULL) {
+		debug("Can't get the usbphy register address\n");
+		return -ENXIO;
+	}
+
+	return 0;
+}
+
 /* Setup the EHCI host controller. */
 static void setup_usb_phy(struct exynos_usb_phy *usb)
 {
@@ -86,12 +144,20 @@ static void reset_usb_phy(struct exynos_usb_phy *usb)
  */
 int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 {
-	struct exynos_usb_phy *usb;
+	struct exynos_ehci *exynos = NULL;
 
-	usb = (struct exynos_usb_phy *)samsung_get_base_usb_phy();
-	setup_usb_phy(usb);
+	exynos = (struct exynos_ehci *)
+			kzalloc(sizeof(struct exynos_ehci), GFP_KERNEL);
+	if (!exynos) {
+		debug("failed to allocate exynos ehci context\n");
+		return -ENOMEM;
+	}
 
-	*hccr = (struct ehci_hccr *)samsung_get_base_usb_ehci();
+	exynos_usb_parse_dt(gd->fdt_blob, exynos);
+
+	setup_usb_phy(exynos->usb);
+
+	*hccr = (struct ehci_hccr *)(exynos->hcd);
 	*hcor = (struct ehci_hcor *)((uint32_t) *hccr
 				+ HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
 
@@ -99,6 +165,8 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 		(uint32_t)*hccr, (uint32_t)*hcor,
 		(uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
 
+	kfree(exynos);
+
 	return 0;
 }
 
@@ -108,10 +176,20 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
  */
 int ehci_hcd_stop(int index)
 {
-	struct exynos_usb_phy *usb;
+	struct exynos_ehci *exynos = NULL;
 
-	usb = (struct exynos_usb_phy *)samsung_get_base_usb_phy();
-	reset_usb_phy(usb);
+	exynos = (struct exynos_ehci *)
+			kzalloc(sizeof(struct exynos_ehci), GFP_KERNEL);
+	if (!exynos) {
+		debug("failed to allocate exynos ehci context\n");
+		return -ENOMEM;
+	}
+
+	exynos_usb_parse_dt(gd->fdt_blob, exynos);
+
+	reset_usb_phy(exynos->usb);
+
+	kfree(exynos);
 
 	return 0;
 }

drivers/usb/host/ohci-at91.c

@@ -41,7 +41,8 @@ int usb_cpu_init(void)
 	writel(get_pllb_init(), &pmc->pllbr);
 	while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB)
 		;
-#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
+#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) || \
+	defined(CONFIG_AT91SAM9X5)
 	/* Enable UPLL */
 	writel(readl(&pmc->uckr) | AT91_PMC_UPLLEN | AT91_PMC_BIASEN,
 		&pmc->uckr);
@@ -81,7 +82,8 @@ int usb_cpu_stop(void)
 	writel(0, &pmc->pllbr);
 	while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != 0)
 		;
-#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
+#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) || \
+	defined(CONFIG_AT91SAM9X5)
 	/* Disable UPLL */
 	writel(readl(&pmc->uckr) & (~AT91_PMC_UPLLEN), &pmc->uckr);
 	while ((readl(&pmc->sr) & AT91_PMC_LOCKU) == AT91_PMC_LOCKU)

drivers/video/exynos_dp.c

@@ -857,7 +857,6 @@ unsigned int exynos_init_dp(void)
 {
 	unsigned int ret;
 	struct edp_device_info *edp_info;
-	struct edp_disp_info disp_info;
 
 	edp_info = kzalloc(sizeof(struct edp_device_info), GFP_KERNEL);
 	if (!edp_info) {
@@ -870,7 +869,6 @@ unsigned int exynos_init_dp(void)
 		debug("failed to get edp_info data.\n");
 		return -EFAULT;
 	}
-	disp_info = edp_info->disp_info;
 
 	exynos_dp_disp_info(&edp_info->disp_info);
 

drivers/video/exynos_fb.c

@@ -63,8 +63,12 @@ static void exynos_lcd_init_mem(void *lcdbase, vidinfo_t *vid)
 static void exynos_lcd_init(vidinfo_t *vid)
 {
 	exynos_fimd_lcd_init(vid);
+
+	/* Enable flushing after LCD writes if requested */
+	lcd_set_flush_dcache(1);
 }
 
+#ifdef CONFIG_CMD_BMP
 static void draw_logo(void)
 {
 	int x, y;
@@ -87,6 +91,7 @@ static void draw_logo(void)
 	addr = panel_info.logo_addr;
 	bmp_display(addr, x, y);
 }
+#endif
 
 static void lcd_panel_on(vidinfo_t *vid)
 {
@@ -145,7 +150,9 @@ void lcd_enable(void)
 	if (panel_info.logo_on) {
 		memset(lcd_base, 0, panel_width * panel_height *
 				(NBITS(panel_info.vl_bpix) >> 3));
+#ifdef CONFIG_CMD_BMP
 		draw_logo();
+#endif
 	}
 
 	lcd_panel_on(&panel_info);

drivers/video/exynos_fimd.c

@@ -88,14 +88,18 @@ static void exynos_fimd_set_par(unsigned int win_id)
 	/* DATAPATH is DMA */
 	cfg |= EXYNOS_WINCON_DATAPATH_DMA;
 
-	/* bpp is 32 */
-	cfg |= EXYNOS_WINCON_WSWP_ENABLE;
+	if (pvid->logo_on) /* To get proprietary LOGO */
+		cfg |= EXYNOS_WINCON_WSWP_ENABLE;
+	else /* To get output console on LCD */
+		cfg |= EXYNOS_WINCON_HAWSWP_ENABLE;
 
 	/* dma burst is 16 */
 	cfg |= EXYNOS_WINCON_BURSTLEN_16WORD;
 
-	/* pixel format is unpacked RGB888 */
-	cfg |= EXYNOS_WINCON_BPPMODE_24BPP_888;
+	if (pvid->logo_on) /* To get proprietary LOGO */
+		cfg |= EXYNOS_WINCON_BPPMODE_24BPP_888;
+	else /* To get output console on LCD */
+		cfg |= EXYNOS_WINCON_BPPMODE_16BPP_565;
 
 	writel(cfg, (unsigned int)&fimd_ctrl->wincon0 +
 			EXYNOS_WINCON(win_id));

drivers/watchdog/Makefile

@@ -27,6 +27,9 @@ LIB	:= $(obj)libwatchdog.o
 
 COBJS-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o
 COBJS-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o
+ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6))
+COBJS-y += imx_watchdog.o
+endif
 COBJS-$(CONFIG_TNETV107X_WATCHDOG) += tnetv107x_wdt.o
 COBJS-$(CONFIG_S5P)               += s5p_wdt.o
 

drivers/watchdog/imx_watchdog.c

@@ -0,0 +1,66 @@
+/*
+ * watchdog.c - driver for i.mx on-chip watchdog
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <watchdog.h>
+#include <asm/arch/imx-regs.h>
+
+struct watchdog_regs {
+	u16	wcr;	/* Control */
+	u16	wsr;	/* Service */
+	u16	wrsr;	/* Reset Status */
+};
+
+#define WCR_WDZST	0x01
+#define WCR_WDBG	0x02
+#define WCR_WDE		0x04	/* WDOG enable */
+#define WCR_WDT		0x08
+#define WCR_WDW		0x80
+#define SET_WCR_WT(x)	(x << 8)
+
+#ifdef CONFIG_IMX_WATCHDOG
+void hw_watchdog_reset(void)
+{
+	struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
+
+	writew(0x5555, &wdog->wsr);
+	writew(0xaaaa, &wdog->wsr);
+}
+
+void hw_watchdog_init(void)
+{
+	struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
+	u16 timeout;
+
+	/*
+	 * The timer watchdog can be set between
+	 * 0.5 and 128 Seconds. If not defined
+	 * in configuration file, sets 128 Seconds
+	 */
+#ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS
+#define CONFIG_WATCHDOG_TIMEOUT_MSECS 128000
+#endif
+	timeout = (CONFIG_WATCHDOG_TIMEOUT_MSECS / 500) - 1;
+	writew(WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_WDT |
+		WCR_WDW | SET_WCR_WT(timeout), &wdog->wcr);
+	hw_watchdog_reset();
+}
+#endif
+
+void reset_cpu(ulong addr)
+{
+	struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
+
+	writew(WCR_WDE, &wdog->wcr);
+	writew(0x5555, &wdog->wsr);
+	writew(0xaaaa, &wdog->wsr);	/* load minimum 1/2 second timeout */
+	while (1) {
+		/*
+		 * spin for .5 seconds before reset
+		 */
+	}
+}

fs/fat/fat.c

@@ -569,9 +569,9 @@ static __u8 mkcksum(const char name[8], const char ext[3])
 
 	__u8 ret = 0;
 
-	for (i = 0; i < sizeof(name); i++)
+	for (i = 0; i < 8; i++)
 		ret = (((ret & 1) << 7) | ((ret & 0xfe) >> 1)) + name[i];
-	for (i = 0; i < sizeof(ext); i++)
+	for (i = 0; i < 3; i++)
 		ret = (((ret & 1) << 7) | ((ret & 0xfe) >> 1)) + ext[i];
 
 	return ret;

include/common.h

@@ -311,6 +311,15 @@ int mac_read_from_eeprom(void);
 extern u8 _binary_dt_dtb_start[];	/* embedded device tree blob */
 int set_cpu_clk_info(void);
 
+/**
+ * Show the DRAM size in a board-specific way
+ *
+ * This is used by boards to display DRAM information in their own way.
+ *
+ * @param size	Size of DRAM (which should be displayed along with other info)
+ */
+void board_show_dram(ulong size);
+
 /* common/flash.c */
 void flash_perror (int);
 

include/config_cmd_all.h

@@ -56,6 +56,7 @@
 #define CONFIG_CMD_LICENSE	/* console license display	*/
 #define CONFIG_CMD_LOADB	/* loadb			*/
 #define CONFIG_CMD_LOADS	/* loads			*/
+#define CONFIG_CMD_MEMINFO	/* meminfo			*/
 #define CONFIG_CMD_MEMORY	/* md mm nm mw cp cmp crc base loop mtest */
 #define CONFIG_CMD_MFSL		/* FSL support for Microblaze	*/
 #define CONFIG_CMD_MII		/* MII support			*/

include/configs/at91sam9x5ek.h

@@ -90,6 +90,14 @@
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_SF
 #define CONFIG_CMD_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_USB
+
+/*
+ * define CONFIG_USB_EHCI to enable USB Hi-Speed (aka 2.0)
+ * NB: in this case, USB 1.1 devices won't be recognized.
+ */
+
 
 /* SDRAM */
 #define CONFIG_NR_DRAM_BANKS		1
@@ -142,9 +150,12 @@
 /* MMC */
 #ifdef CONFIG_CMD_MMC
 #define CONFIG_MMC
-#define CONFIG_CMD_FAT
 #define CONFIG_GENERIC_MMC
 #define CONFIG_GENERIC_ATMEL_MCI
+#endif
+
+/* FAT */
+#ifdef CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 #endif
 
@@ -154,6 +165,22 @@
 #define CONFIG_NET_RETRY_COUNT		20
 #define CONFIG_MACB_SEARCH_PHY
 
+/* USB */
+#ifdef CONFIG_CMD_USB
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_ATMEL
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	2
+#else
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		ATMEL_BASE_OHCI
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9x5"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	3
+#endif
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_STORAGE
+#endif
+
 #define CONFIG_SYS_LOAD_ADDR		0x22000000	/* load address */
 
 #define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
@@ -178,6 +205,16 @@
 #define CONFIG_BOOTCOMMAND	"sf probe 0; " \
 				"sf read 0x22000000 0x100000 0x300000; " \
 				"bootm 0x22000000"
+#elif defined(CONFIG_SYS_USE_DATAFLASH)
+/* bootstrap + u-boot + env + linux in data flash */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET	0x4200
+#define CONFIG_ENV_SIZE		0x4200
+#define CONFIG_ENV_SECT_SIZE	0x210
+#define CONFIG_ENV_SPI_MAX_HZ	30000000
+#define CONFIG_BOOTCOMMAND	"sf probe 0; " \
+				"sf read 0x22000000 0x84000 0x294000; " \
+				"bootm 0x22000000"
 #else /* CONFIG_SYS_USE_MMC */
 /* bootstrap + u-boot + env + linux in mmc */
 #define CONFIG_ENV_IS_IN_MMC

include/configs/exynos5250-dt.h

@@ -0,0 +1,321 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Configuration settings for the SAMSUNG EXYNOS5250 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_SAMSUNG			/* in a SAMSUNG core */
+#define CONFIG_S5P			/* S5P Family */
+#define CONFIG_EXYNOS5			/* which is in a Exynos5 Family */
+#define CONFIG_SMDK5250			/* which is in a SMDK5250 */
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Enable fdt support for Exynos5250 */
+#define CONFIG_ARCH_DEVICE_TREE		exynos5250
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
+/* Keep L2 Cache Disabled */
+#define CONFIG_SYS_DCACHE_OFF
+
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CONFIG_SYS_TEXT_BASE		0x43E00000
+
+/* input clock of PLL: SMDK5250 has 24MHz input clock */
+#define CONFIG_SYS_CLK_FREQ		24000000
+
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMDLINE_EDITING
+
+/* MACH_TYPE_SMDK5250 macro will be removed once added to mach-types */
+#define MACH_TYPE_SMDK5250		3774
+#define CONFIG_MACH_TYPE		MACH_TYPE_SMDK5250
+
+/* Power Down Modes */
+#define S5P_CHECK_SLEEP			0x00000BAD
+#define S5P_CHECK_DIDLE			0xBAD00000
+#define S5P_CHECK_LPA			0xABAD0000
+
+/* Offset for inform registers */
+#define INFORM0_OFFSET			0x800
+#define INFORM1_OFFSET			0x804
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (4 << 20))
+
+/* select serial console configuration */
+#define CONFIG_SERIAL3			/* use SERIAL 3 */
+#define CONFIG_BAUDRATE			115200
+#define EXYNOS5_DEFAULT_UART_OFFSET	0x010000
+
+/* Console configuration */
+#define CONFIG_CONSOLE_MUX
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define EXYNOS_DEVICE_SETTINGS \
+		"stdin=serial\0" \
+		"stdout=serial,lcd\0" \
+		"stderr=serial,lcd\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	EXYNOS_DEVICE_SETTINGS
+
+#define TZPC_BASE_OFFSET		0x10000
+
+/* SD/MMC configuration */
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_SDHCI
+#define CONFIG_S5P_SDHCI
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* PWM */
+#define CONFIG_PWM
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Command definition*/
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_NET
+
+#define CONFIG_BOOTDELAY		3
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+/* USB */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_EXYNOS
+#define CONFIG_USB_STORAGE
+
+/* MMC SPL */
+#define CONFIG_SPL
+#define COPY_BL2_FNPTR_ADDR	0x02020030
+
+/* specific .lds file */
+#define CONFIG_SPL_LDSCRIPT	"board/samsung/smdk5250/smdk5250-uboot-spl.lds"
+#define CONFIG_SPL_TEXT_BASE	0x02023400
+#define CONFIG_SPL_MAX_SIZE	(14 * 1024)
+
+#define CONFIG_BOOTCOMMAND	"mmc read 40007000 451 2000; bootm 40007000"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser	*/
+#define CONFIG_SYS_PROMPT		"SMDK5250 # "
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE		384	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC1,115200n8\0"
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5E00000)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x3E00000)
+
+#define CONFIG_SYS_HZ			1000
+
+#define CONFIG_RD_LVL
+
+#define CONFIG_NR_DRAM_BANKS	8
+#define SDRAM_BANK_SIZE		(256UL << 20UL)	/* 256 MB */
+#define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_1_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_2		(CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
+#define PHYS_SDRAM_2_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_3		(CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_3_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_4		(CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_4_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_5		(CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_5_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_6		(CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_6_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_7		(CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_7_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_8		(CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_8_SIZE	SDRAM_BANK_SIZE
+
+#define CONFIG_SYS_MONITOR_BASE	0x00000000
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+#undef CONFIG_CMD_IMLS
+#define CONFIG_IDENT_STRING		" for SMDK5250"
+
+#define CONFIG_SYS_MMC_ENV_DEV		0
+
+#define CONFIG_SECURE_BL1_ONLY
+
+/* Secure FW size configuration */
+#ifdef	CONFIG_SECURE_BL1_ONLY
+#define	CONFIG_SEC_FW_SIZE		(8 << 10)	/* 8KB */
+#else
+#define	CONFIG_SEC_FW_SIZE		0
+#endif
+
+/* Configuration of BL1, BL2, ENV Blocks on mmc */
+#define CONFIG_RES_BLOCK_SIZE	(512)
+#define CONFIG_BL1_SIZE		(16 << 10) /*16 K reserved for BL1*/
+#define	CONFIG_BL2_SIZE		(512UL << 10UL)	/* 512 KB */
+#define CONFIG_ENV_SIZE		(16 << 10)	/* 16 KB */
+
+#define CONFIG_BL1_OFFSET	(CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
+#define CONFIG_BL2_OFFSET	(CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
+#define CONFIG_ENV_OFFSET	(CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE)
+
+/* U-boot copy size from boot Media to DRAM.*/
+#define BL2_START_OFFSET	(CONFIG_BL2_OFFSET/512)
+#define BL2_SIZE_BLOC_COUNT	(CONFIG_BL2_SIZE/512)
+
+#define OM_STAT				(0x1f << 1)
+#define EXYNOS_COPY_SPI_FNPTR_ADDR	0x02020058
+#define SPI_FLASH_UBOOT_POS		(CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
+
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_IRAM_STACK	0x02050000
+
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_LOAD_ADDR - 0x1000000)
+
+/* I2C */
+#define CONFIG_SYS_I2C_INIT_BOARD
+#define CONFIG_HARD_I2C
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C_SPEED	100000		/* 100 Kbps */
+#define CONFIG_DRIVER_S3C24X0_I2C
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_MAX_I2C_NUM	8
+#define CONFIG_SYS_I2C_SLAVE    0x0
+#define CONFIG_I2C_EDID
+
+/* PMIC */
+#define CONFIG_PMIC
+#define CONFIG_PMIC_I2C
+#define CONFIG_PMIC_MAX77686
+
+/* SPI */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_SPI_FLASH
+
+#ifdef CONFIG_SPI_FLASH
+#define CONFIG_EXYNOS_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
+#define CONFIG_SF_DEFAULT_SPEED		50000000
+#define EXYNOS5_SPI_NUM_CONTROLLERS	5
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_MODE	SPI_MODE_0
+#define CONFIG_ENV_SECT_SIZE	CONFIG_ENV_SIZE
+#define CONFIG_ENV_SPI_BUS	1
+#define CONFIG_ENV_SPI_MAX_HZ	50000000
+#endif
+
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_MAX77686
+
+/* SPI */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_SPI_FLASH
+
+#ifdef CONFIG_SPI_FLASH
+#define CONFIG_EXYNOS_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
+#define CONFIG_SF_DEFAULT_SPEED		50000000
+#define EXYNOS5_SPI_NUM_CONTROLLERS	5
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_MODE	SPI_MODE_0
+#define CONFIG_ENV_SECT_SIZE	CONFIG_ENV_SIZE
+#define CONFIG_ENV_SPI_BUS	1
+#define CONFIG_ENV_SPI_MAX_HZ	50000000
+#endif
+
+/* Ethernet Controllor Driver */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_BASE		0x5000000
+#define CONFIG_SMC911X_16_BIT
+#define CONFIG_ENV_SROM_BANK		1
+#endif /*CONFIG_CMD_NET*/
+
+/* Enable PXE Support */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_CMD_PXE
+#define CONFIG_MENU
+#endif
+
+/* Sound */
+#define CONFIG_CMD_SOUND
+#ifdef CONFIG_CMD_SOUND
+#define CONFIG_SOUND
+#define CONFIG_I2S
+#define CONFIG_SOUND_WM8994
+#endif
+
+/* Enable devicetree support */
+#define CONFIG_OF_LIBFDT
+
+/* SHA hashing */
+#define CONFIG_CMD_HASH
+#define CONFIG_HASH_VERIFY
+#define CONFIG_SHA1
+#define CONFIG_SHA256
+
+/* Display */
+#define CONFIG_LCD
+#ifdef CONFIG_LCD
+#define CONFIG_EXYNOS_FB
+#define CONFIG_EXYNOS_DP
+#define LCD_XRES			2560
+#define LCD_YRES			1600
+#define LCD_BPP			LCD_COLOR16
+#endif
+
+#endif	/* __CONFIG_H */