Compare commits

...

613 Commits

Author SHA1 Message Date
Tom Rini
d6c1ffc7d2 Prepare v2014.10-rc2
Signed-off-by: Tom Rini <trini@ti.com>
2014-09-02 16:58:29 -04:00
Tom Rini
48f892dc73 Merge git://git.denx.de/u-boot-usb 2014-09-02 16:37:57 -04:00
Tom Rini
2c19478e01 Merge branch 'master' of git://git.denx.de/u-boot-arc 2014-09-02 16:37:17 -04:00
Bo Shen
06fa91cd67 USB: gadget: s3c: get rid of debug compile warning
When enable debug option to compile, it will give the following
warning, this patch is used to get rid of it.
--->8---
warning: 'flags' is used uninitialized in this function [-Wuninitialized]
---8<---

Signed-off-by: Bo Shen <voice.shen@atmel.com>
2014-09-02 14:32:15 +02:00
Bo Shen
f9abd4b415 USB: gadget: atmel: get rid of debug compile warning
When enable debug option to compile, it will give the following
warning, this patch is used to get rid of it.
--->8---
warning: 'flags' is used uninitialized in this function [-Wuninitialized]
---8<---

Signed-off-by: Bo Shen <voice.shen@atmel.com>
2014-09-02 14:32:15 +02:00
Stephen Warren
842ef9a98e usb: ci_udc: implement dfu_usb_get_reset
This allows the USB code to determine whether a USB bus reset was issued,
which in turn allows the code to differentiate between a detach (return
to shell prompt) and a board reset/reboot request.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-09-02 14:29:28 +02:00
Lukasz Majewski
f2ec4e34aa udc: dfu: s3c_udc: Provide function to check if USB reset was asserted
New dfu_usb_get_reset() method is necessary to distinct two different
use cases of dfu-util program.
This method checks if the USB bus reset has been really performed after
DFU DETACH.

Without this function the previous DFU behavior is preserved.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
2014-09-02 14:29:28 +02:00
Lukasz Majewski
1cc03c5c53 dfu: Provide means to find difference between dfu-util -e and -R
This commit provides distinction between DFU device detach and reset.
The -R behavior is preserved with proper handling of the dfu-util's -e
switch, which detach the DFU device.

By running dfu-util -e; one can force device to finish the execution of
dfu command on target and execute some other scripted commands.

Moreover, some naming has been changed - the dfu_reset() method now is known
as dfu_detach(). New name better reflects the purpose of the code.

It was also necessary to increase the number of usb_gadget_handle_interrupts()
calls since we also must wait for detection of the USB reset event.

Example usage:
1. -e (detach) switch
 dfu-util -a0 -D file1.bin;dfu-util -a3 -D uImage;dfu-util -e

 access to u-boot prompt.

2. -R (reset) switch
 dfu-util -a0 -D file1.bin;dfu-util -R -a3 -D uImage

 target board reset

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
2014-09-02 14:29:28 +02:00
Tom Rini
141e1faec2 Merge git://git.denx.de/u-boot-dm 2014-09-02 08:22:26 -04:00
Vasili Galka
3400655e0f mpc5xxx: Add stub implementation of cache functions
Some drivers (e.g. net/e1000) reference these functions. So, this
fixes the build of MVBC_P board.

I'm not familiar with the MPC5xxx platform, maybe a full
implementation shall be implemented instead of this stub in the
future.

Signed-off-by: Vasili Galka <vvv444@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>, Marek Vasut <marex@denx.de>
Acked-by: Wolfgang Denk <wd@denx.de>
2014-09-02 08:19:58 -04:00
Simon Glass
4bc9a19324 dm: sandbox: dts: Add a GPIO bank
Add a bank of GPIOs for sandbox which can be used for testing this
functionality.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-08-31 23:21:42 -06:00
Simon Glass
9165e8428d dm: gpio: Allow gpio command to adjust GPIOs that are busy
The gpio command mostly relies on gpio_request() and gpio_free() being
nops, in that you can request a GPIO twice. With driver model this is
now implemented correctly, so it fails.

Change the command to deal with a failure to claim the GPIO.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-08-31 23:21:19 -06:00
Simon Glass
89e6405425 dm: gpio: Enhance gpio command to show only active GPIOs
The GPIO list is very long in many cases and most of them are not used.
By default, show only the GPIOs that are in use, and provide a flag to show
all of them. This makes the 'gpio status' command much more pleasant.

In order to do this, driver model now exposes a method for obtaining the
'function' of a GPIO, which describes whether it is an input or output, for
example. Implementation of this method is optional.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-08-31 23:21:06 -06:00
Masahiro Yamada
a1263632bb mx6: tqma6: get board support back to Kconfig build system
The QS Systems TQMa6 board support was added by commit cb07d74e
and lost by commit e82abaeb.

Commit e82abaeb merged the IMX branch based on pre-Kconfig
and the mainline based on post-Kconfig, simply deleting
the boards.cfg file.  As a result, some boards added just before
the merge were lost.

This commit adds Kconfig, defconfig, MAINTAINERS for TQMa6 board
to work on the Kconfig infrastructure.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Markus Niebel <Markus.Niebel@tq-group.com>
Cc: Stefano Babic <sbabic@denx.de>
2014-08-31 12:01:04 -04:00
Tom Rini
0a64bc20f7 Merge branch 'master' of git://git.denx.de/u-boot-nios 2014-08-31 07:45:55 -04:00
Masahiro Yamada
16e16fdde2 nomadik: kconfig: move board select menu and common settings
Becuase the board select menu in arch/arm/Kconfig is too big,
move the Nomadik board select menu to nomadik/Kconfig.

Move also common settings (CONFIG_SYS_CPU="arm926ejs" and
CONFIG_SYS_SOC="nomadik").

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-30 21:22:00 -04:00
Masahiro Yamada
ef2b694c73 highbank: kconfig: move common settings
Move Highbank-specific settings to highbank/Kconfig.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Rob Herring <robh@kernel.org>
2014-08-30 21:22:00 -04:00
Masahiro Yamada
22f2be7a12 orion5x: kconfig: move board select menu and common settings
Becuase the board select menu in arch/arm/Kconfig is too big,
move the Orion5x board select menu to orion5x/Kconfig.

Move also common settings (CONFIG_SYS_CPU="arm926ejs" and
CONFIG_SYS_SOC="orion5x").

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
2014-08-30 21:21:59 -04:00
Masahiro Yamada
c338f09e96 keystone: kconfig: move board select menu and common settings
Becuase the board select menu in arch/arm/Kconfig is too big,
move the Keystone board select menu to keystone/Kconfig.

Move also common settings (CONFIG_SYS_CPU="armv7" and
CONFIG_SYS_SOC="keystone").

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Tom Rini <trini@ti.com>
Cc: Vitaly Andrianov <vitalya@ti.com>
2014-08-30 21:21:59 -04:00
Masahiro Yamada
6c5431ac81 omap5: kconfig: move board select menu and common settings
Becuase the board select menu in arch/arm/Kconfig is too big,
move the OMAP5 board select menu to omap5/Kconfig.

Move also common settings (CONFIG_SYS_CPU="armv7" and
CONFIG_SYS_SOC="omap5").

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Tom Rini <trini@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
2014-08-30 21:21:59 -04:00
Masahiro Yamada
d08215a5f1 omap4: kconfig: move board select menu and common settings
Becuase the board select menu in arch/arm/Kconfig is too big,
move the OMAP4 board select menu to omap4/Kconfig.

Move also common settings (CONFIG_SYS_CPU="armv7" and
CONFIG_SYS_SOC="omap4").

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Tom Rini <trini@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
2014-08-30 21:21:59 -04:00
Masahiro Yamada
3cfbcb58d3 omap3: kconfig: move board select menu and common settings
Becuase the board select menu in arch/arm/Kconfig is too big,
move the OMAP3 board select menu to omap3/Kconfig.

Move also common settings (CONFIG_SYS_CPU="armv7" and
CONFIG_SYS_SOC="omap3

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Tom Rini <trini@ti.com>
2014-08-30 21:21:59 -04:00
Masahiro Yamada
3491ba6311 davinci: kconfig: move board select menu and common settings
Becuase the board select menu in arch/arm/Kconfig is too big,
move the Davinci board select menu to davinci/Kconfig.

Move also common settings (CONFIG_SYS_CPU="arm926ejs" and
CONFIG_SYS_SOC="davinci").

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Tom Rini <trini@ti.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
2014-08-30 21:21:59 -04:00
Masahiro Yamada
72df68cc6b exynos: kconfig: move board select menu and common settings
Becuase the board select menu in arch/arm/Kconfig is too big,
move the Exynos board select menu to exynos/Kconfig.

Consolidate also common settings (CONFIG_SYS_CPU="armv7" and
CONFIG_SYS_SOC="exynos").

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
2014-08-30 21:21:59 -04:00
Masahiro Yamada
47539e2317 kirkwood: kconfig: refactor Kconfig and defconfig
Becuase the board select menu in arch/arm/Kconfig is too big,
move the KirkWood board select menu to kirkwood/Kconfig.

Consolidate also common settings (CONFIG_SYS_CPU="arm926ejs" and
CONFIG_SYS_SOC="kirkwood").

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Prafulla Wadasdkar <prafulla@marvell.com>
Cc: Luka Perkov <luka@openwrt.org>
2014-08-30 21:21:21 -04:00
Masahiro Yamada
ad17a81c06 versatile: kconfig: move common settings
Move Versatile-specific settings to versatile/Kconfig.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-30 21:19:32 -04:00
Masahiro Yamada
f40b989863 rmobile: kconfig: move board select menu and common settings
Becuase the board select menu in arch/arm/Kconfig is too big,
move the Rmobile board select menu to rmobile/Kconfig.

Consolidate also common settings (CONFIG_SYS_CPU="armv7" and
CONFIG_SYS_SOC="rmobile").

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-08-30 21:19:32 -04:00
Masahiro Yamada
ddd960e6c4 tegra: kconfig: move board select menu and common settings
Becuase the board select menu in arch/arm/Kconfig is too big,
move the Tegra board select menu to tegra/Kconfig.

Insert the Tegra SoC select menu between the arch select and the
board select.

 Architecture select
 |-- Tegra Platform (Tegra)
     |- Tegra SoC select (Tegra20 / 30 / 114 / 124)
        |- Board select

Consolidate also common settings (CONFIG_SYS_CPU="armv7" and
CONFIG_SYS_SOC="tegra*") and always "select" CONFIG_SPL as follows:

  config TEGRA
          bool
          select SPL

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Cc: Tom Warren <twarren@nvidia.com>
2014-08-30 21:19:32 -04:00
Masahiro Yamada
44dcb4036b zynq: kconfig: move board select menu and common settings
Becuase the board select menu in arch/arm/Kconfig is too big,
move the Zynq board select menu to zynq/Kconfig.

Consolidate also common settings (CONFIG_SYS_CPU="armv7" and
CONFIG_SYS_SOC="zynq").

Refactor board/xilinx/zynq/MAINTAINERS too.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Tested-by: Michal Simek <michal.simek@xilinx.com>
2014-08-30 21:19:32 -04:00
Benoît Thébaudeau
eeadd3fe0f arm: Add missing .vectors section to linker scripts
Commit 41623c9 'arm: move exception handling out of start.S files' missed some
linker scripts. Hence, some boards no longer had exception handling linked since
this commit. Restore the original behavior by adding the .vectors section to
these linker scripts.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
2014-08-30 07:46:41 -04:00
Holger Brunck
58c90c88ad arm/km: disable subpage write for km_kirkwood_pci and kmsuv31 target
Newer FLASH types used on these boards don't allow writing of subpages.
So disable subpage write in the NAND driver. Additionally we need to
tell the UBI layer in the kernel that he also should only write 2048
bytes. This is done with an additional command line parameter for the
kernel commandline.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
2014-08-30 07:46:41 -04:00
Holger Brunck
292221e183 arm/kirkwood/nand: allow forced disabling for subpage writes
Make it configurable to disable subpage writes like the DaVinci NAND
driver already does.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
cc: Scott Wood <scottwood@freescale.com>
2014-08-30 07:46:41 -04:00
Tom Rini
6717252837 vexpress_aemv8a.h: Enable CONFIG_CMD_BOOTI and CONFIG_CMD_UNZIP
Add support for booting Images and for unzipping Image.gz files.

Signed-off-by: Tom Rini <trini@ti.com>
2014-08-30 07:46:41 -04:00
Tom Rini
5bcae13ee4 vexpress_aemv8a.h: Clean up the config
- Drop DEBUG
- Drop defines we can use the default of.
- Provide a larger malloc pool.
- Correct default locations for kernel / initrd / device tree

Signed-off-by: Tom Rini <trini@ti.com>
2014-08-30 07:46:41 -04:00
Tom Rini
d2b2ffe310 cmd_bootm.c: Add 'booti' for ARM64 Linux kernel Images
The default format for arm64 Linux kernels is the "Image" format,
described in Documentation/arm64/booting.txt.  This, along with an
optional gzip compression on top is all that is generated by default.
The Image format has a magic number within the header for verification,
a text_offset where the Image must be run from, an image_size that
includes the BSS and reserved fields.

This does not support automatic detection of a gzip compressed image.

Signed-off-by: Tom Rini <trini@ti.com>
2014-08-30 07:46:41 -04:00
Tom Rini
3f1b6bebe0 arm64: Correct passing of Linux kernel args
The Documentation/arm64/booting.txt document says that pass in x1/x2/x3
as 0 as they are reserved for future use.

Signed-off-by: Tom Rini <trini@ti.com>
2014-08-30 07:46:40 -04:00
Steve Rae
9dec5270be arm: convert Cygnus and NSP boards to Kconfig
Convert the bcm958300k and the bcm958622hr boards from "boards.cfg" to Kconfig.

Signed-off-by: Steve Rae <srae@broadcom.com>
2014-08-30 07:46:40 -04:00
Scott Branden
da1f5ac295 arm: add Cygnus and NSP boards
The bcm_ep board configuration is used by a number of boards
including Cygnus and NSP.
Add builds for the bcm958300k and the bcm958622hr boards.

Signed-off-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Steve Rae <srae@broadcom.com>
2014-08-30 07:46:40 -04:00
Scott Branden
562f01a2ba arm: bcmnsp: Add bcmnsp u-architecture
Base support for the Broadcom NSP SoC.
Based on iproc-common and the SoC specific reset function.

Signed-off-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Steve Rae <srae@broadcom.com>
2014-08-30 07:46:40 -04:00
Scott Branden
7986688075 arm: bcmcygnus: Add bcmcygnus u-architecture
Base support for the Broadcom Cygnus SoC.
Based on iproc-common and the SoC specific reset function.

Signed-off-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Steve Rae <srae@broadcom.com>
2014-08-30 07:46:40 -04:00
Scott Branden
c4b4500910 arm: iproc: Initial commit of iproc architecture code
The iproc architecture code is present in several Broadcom
chip architectures, including Cygnus and NSP.

Signed-off-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Steve Rae <srae@broadcom.com>
2014-08-30 07:46:40 -04:00
Stefan Agner
b0e31c7b66 arm: vf610: add NFC clock support
Add NFC (NAND Flash Controller) clock support and enable them
at board initialization time.

Signed-off-by: Stefan Agner <stefan@agner.ch>
2014-08-30 07:46:40 -04:00
Stefan Agner
baa3134440 arm: vf610: add NFC pin mux
Add pin mux for NAND Flash Controller (NFC). NAND can be connected
using 8 or 16 data lines, this patch adds pin mux entries for all
16 data lines.

Signed-off-by: Stefan Agner <stefan@agner.ch>
2014-08-30 07:46:39 -04:00
Masahiro Yamada
aee63751d9 MAINTAINERS: change the status of vexpress board to Orphan
The email address of Matt Waddel is no longer working.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Alexei Fedorov <alexie.fedorov@arm.com>
2014-08-30 07:46:39 -04:00
Marek Vasut
221a49d5bd ARM: Fix overflow in MMU setup
The patch fixes a corner case where adding size to DRAM start resulted
in a value (1 << 32), which in turn overflew the u32 computation, which
resulted in 0 and it therefore prevented correct setup of the MMU tables.

The addition of DRAM bank start and it's size can end up right at the end
of the address space in the special case of a machine with enough memory.
To prevent this overflow, shift the start and size separately and add them
only after they were shifted.

Hopefully, we only have systems in tree which have DRAM size aligned to
1MiB boundary. If not, this patch would break such systems. On the other
hand, such system would be broken by design anyway.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
2014-08-30 07:46:39 -04:00
Steve Rae
a9a274c1eb arm: bcm281xx: add board with Ethernet capability
Add board which has Broadcom StarFighter2 Ethernet capability.

Signed-off-by: Steve Rae <srae@broadcom.com>
2014-08-30 07:46:39 -04:00
Jiandong Zheng
799e125cca arm: bcm281xx: net: Add Ethernet Driver
The Broadcom StarFighter2 Ethernet driver is used in multiple Broadcom
SoC(s) and:
- supports multiple MAC blocks,
- provides support for the Broadcom GMAC.
This driver requires MII and PHYLIB.

Signed-off-by: Jiandong Zheng <jdzheng@broadcom.com>
Signed-off-by: Steve Rae <srae@broadcom.com>
2014-08-30 07:46:39 -04:00
Jiandong Zheng
2d66a0fd58 arm: bcm281xx: Add Ethernet Clock support
Enable Ethernet clock when Broadcom StarFighter2 Ethernet block
(CONFIG_BCM_SF2_ETH) is enabled.

Signed-off-by: Jiandong Zheng <jdzheng@broadcom.com>
Signed-off-by: Steve Rae <srae@broadcom.com>
2014-08-30 07:46:39 -04:00
Andre Przywara
fafbc6c000 ARM: enable ARMv7 virt support for the Arndale board
To enable hypervisors utilizing the ARMv7 virtualization extension
on the Arndale board, add the simple SMP pen address writer function
and add the required configuration variables to switch all cores to
HYP mode before launching the OS.
This allows booting KVM and Xen directly from u-boot.

Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2014-08-30 07:46:38 -04:00
Sergey Kostanbaev
0bf62d7bc4 arm: ep9315: Add .vectors section to lds and remove obsolete lds
However ep9315 don't use
interrupt vectors during startup, but _startup symbol is used inside uboot to
calculate actual monitor size.

Signed-off-by: Sergey Kostanbaev <sergey.kostanbaev@gmail.com>
Cc: albert.u.boot@aribaud.net
2014-08-30 07:46:38 -04:00
Pavel Machek
7860649716 socfpga: cleanup socfpga_dw_mmc
Cleanups as suggested by wd on mailing list.

Signed-off-by: Pavel Machek <pavel@denx.de>
Acked-by: Chin Liang See <clsee@altera.com>
2014-08-30 07:46:38 -04:00
Pavel Machek
99b97106f3 socfpga: initialize designware ethernet
Enable initialization fo designware ethernet controller. With this
patch, ethernet works in my configuration, provided I set ethernet
address in the environment.

Signed-off-by: Pavel Machek <pavel@denx.de>
2014-08-30 07:46:38 -04:00
Thomas Chou
857b9cb69f nios2: rebase nios2-generic board to 3c120 reference design
Though nios2-generic board meant to be a template, it is helpful
to be able to test on a real hardware. As the nios2 linux is
developed and tested on a 3c120 FPGA based Golden Hardware Reference
Design, it makes sense to rebase nios2-generic on this FPGA design.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
2014-08-30 17:48:43 +08:00
Thomas Chou
c69d2e5761 nios2: link to CONFIG_SYS_MONITOR_BASE and remove text_base hook
This patch changes the link script to base at CONFIG_SYS_MONITOR_BASE.
Then we can remove the text_base hook in nios2-generic board.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
2014-08-30 17:48:43 +08:00
Thomas Chou
3a55a56662 serial: move nios2-yanu.h into opencores_yanu driver
The nios2-yanu.h contains hardware registers and bits of
opencores yanu. As there is no other user of this header
, it should be moved into the driver.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
CC: Renato Andreola <renato.andreola@imagos.it>
2014-08-30 17:48:43 +08:00
Thomas Chou
57cfeb5140 nios2: move nios2.h to arch asm directory
The nios2.h is nios2 cpu specific, and should go arch asm
directory.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
2014-08-30 17:48:43 +08:00
Thomas Chou
8645071006 nios2: divide nios2-io.h into each specific drivers and remove it
The nios2-io.h defines hardware registers and bits of several FPGA
IP cores. It could be divided in to the specific drivers, including
altera timer, altera sysid, altera uart and altera jtag uart. The
altera pio and altera spi drivers use their own hardware definitions.
The removal of nios2-io.h will help modularity and maintenance.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
2014-08-30 17:48:43 +08:00
Thomas Chou
ef3cc8112c nios2: remove epled driver
The epled driver was replaced by altera_pio and gpio_led.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
2014-08-30 17:48:43 +08:00
Chin Liang See
3ab019e1dc socfpga: Fix SOCFPGA build error for Altera dev kit
To fix the build error when build for Altera dev kit, not
virtual target. At same time, set the build for Altera dev
kit as default instead virtual target. With that, U-Boot
is booting well and SPL still lack of few drivers.

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
2014-08-29 15:50:54 -04:00
Pavel Machek
51fb455f82 socfpga: fix clock manager register definition
Structure defining clock manager hardware was wrong, leading to
wrong registers being accessed and hang in MMC init.

This fixes structure to match hardware.

Signed-off-by: Pavel Machek <pavel@denx.de>
2014-08-29 15:50:50 -04:00
Christian Riesch
db993fc8ec arm: include config.h in arch/arm/lib/vectors.S
config.h is required for CONFIG_SYS_DV_NOR_BOOT_CFG.

Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Reported-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
2014-08-29 15:50:43 -04:00
Jeroen Hofstee
8863aa5c98 ARM:asm:io.h use static inline
When compiling u-boot with W=1 the extern inline void for
read* is likely causing the most noise. gcc / clang will
warn there is never a actual declaration for these functions.
Instead of declaring these extern make them static inline so
it is actually declared.

cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-08-29 15:50:43 -04:00
Tom Rini
6defdc0b55 Merge branch 'master' of git://git.denx.de/u-boot-ti 2014-08-29 13:47:42 -04:00
Tom Rini
8f005b3918 Merge git://git.denx.de/u-boot-usb 2014-08-29 11:15:18 -04:00
Tom Rini
7f14fb20f8 Merge branch 'zynq' of git://www.denx.de/git/u-boot-microblaze 2014-08-29 11:07:35 -04:00
Tom Rini
5ddc329341 Merge branch 'master' of git://git.denx.de/u-boot-tegra 2014-08-29 11:07:10 -04:00
Tom Rini
5a1095a830 Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2014-08-29 11:06:51 -04:00
Tom Rini
6af857c50d Merge branch 'master' of http://git.denx.de/u-boot-sunxi 2014-08-29 11:06:26 -04:00
Stephen Warren
74c0d756de usb: hub: don't check CONNECTION in hub_port_reset()
One specific USB 3.0 device behaves strangely when reset by
usb_new_device()'s call to hub_port_reset(). For some reason, the device
appears to briefly drop off the bus when this second bus reset is
executed, yet if we retry this loop, it'll eventually come back after
another two resets.

If USB bus reset is executed over and over within usb_new_device()'s call
to hub_port_reset(), I see the following sequence of results, which
repeats as long as you want:

1) STAT_C_CONNECTION = 1 STAT_CONNECTION = 0  USB_PORT_STAT_ENABLE 0
2) STAT_C_CONNECTION = 1 STAT_CONNECTION = 1  USB_PORT_STAT_ENABLE 0
3) STAT_C_CONNECTION = 1 STAT_CONNECTION = 1  USB_PORT_STAT_ENABLE 1

The device in question is a SanDisk Ultra USB 3.0 16GB memory stick with
USB VID/PID 0x0781/0x5581.

In order to allow this device to work with U-Boot, ignore the
{C_,}CONNECTION bits in the status/change registers, and only use the
ENABLE bit to determine if the reset was successful.

To be honest, extensive investigation has failed to determine why this
problem occurs. I'd love to know! I don't know if it's caused by:
* A HW bug in the device
* A HW bug in the Tegra USB controller
* A SW bug in the U-Boot Tegra USB driver
* A SW bug in the U-Boot USB core

This issue only occurs when the device's USB3 pins are attached to the
host; if only the USB2 pins are connected the issue does not occur. The
USB3 controller on Tegra is in reset, so is not actively communicating
with the device at all - a USB3 analyzer confirms this. Slightly
unplugging the device (so the USB3 pins don't contact) or using a USB2
cable or hub as an intermediary avoids the problem. For some reason,
the Linux kernel (either on the same Tegra board, or on an x86 host)
has no issue with the device, and I observe no disconnections during
reset.

This change won't affect any USB device that already works, since such
devices could not currently be triggering the error return this patch
removes, or they wouldn't be working currently.

However, this patch is quite reliable in practice, hence I hope it's
acceptable to solve the problem.

The only potential fallout I can see from this patch is:

* A broken device that triggers C_CONNECTION/!CONNECTION now causes the
  loop in hub_port_reset() to run multiple times. If it never succeeds,
  this will cause "usb start" to take roughly 1s extra to execute.

* If the user unplugs a device while hub_port_reset() is executing, and
  very quickly swaps in a new device, hub_port_reset() might succeed on
  the new device. This would mean that any information cached about the
  original device (from the descriptor read in usb_new_device(), which
  simply caches the max packet size) might be invalid, which would cause
  problems talking to the new device. However, without this change, the
  new device wouldn't work anyway, so this is probably not much of a
  loss.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-08-29 11:27:43 +02:00
Marek Vasut
97b9eb9e6a usb: Handle -ENODEV from usb_lowlevel_init()
As we support both Host and Device mode operation, an OTG controller
can return -ENODEV on a port which it found to be in Device mode during
Host mode scan for devices. In case -ENODEV is returned, print that the
port is not available and continue instead of screaming a bloody error
message.

Signed-off-by: Marek Vasut <marex@denx.de>
2014-08-29 11:27:42 +02:00
Masahiro Yamada
d1b60d3407 README.kconfig: document backward compatibility "make *_config"
Commit 3ff291f371
(kconfig: convert Kconfig helper script into a shell script)
restored "<board>_config" target for backward compatibility.
It should be documented.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2014-08-28 17:18:49 -04:00
Masahiro Yamada
2134342e57 tools/genboardscfg.py: change shebang into /usr/bin/env python2
This tool only works on python 2 (python 2.6 or lator).

Change the shebang to make sure the script is run by python 2
and clearly say the supported version in the comment block.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-28 17:18:49 -04:00
Stefan Roese
5a834c1f9e net: cpsw: am335x: Drop constant link checking from rx/tx path's
We noticed on the DXR2 platform (AM335x with a SMSC LAN9303 switch connected
to the CPSW MAC) that the network performance in U-Boot is quite poor. Only
when the transfer is started without a cable connected, and the cable is
plugged after the first timeout "T" occured, an increased in performance
can be seen. Debugging has revealed, that the cpsw driver has constant
link checking builtin into the rx and tx functions. This results in the
bad performance and seems to be unnecessary. The link has already been
checked in the init function, before the transfer is started. This usually
is sufficient.

BTW: I have seen no other network driver in U-Boot so far, that constantly
checks for link in the rx / tx functions.

The performance numbers on the DXR2 board are:

0.56 MiB/s	cpsw_check_link() in rx and tx path
0.87 MiB/s	cpsw_check_link() only in tx path
1.0  MiB/s	cpsw_check_link() only in rx path
2.7  MiB/s	no cpsw_check_link() in rx and tx path

So with this patch the network performance on DXR2 increases from 0.56
to 2.7 MiB/s (nearly 5 times as fast).

Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Samuel Egli <samuel.egli@siemens.com>
Tested-by: Heiko Schocher <hs@denx.de>
Cc: Vladimir Koutny <vladimir.koutny@streamunlimited.com>
Cc: Mugunthan V N <mugunthanvnm@ti.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Tom Rini <trini@ti.com>
2014-08-28 17:18:49 -04:00
Masahiro Yamada
9a65cb7ffe tools/genboardscfg.py: improve performance
I guess some developers are already getting sick of this tool
because it generally takes a few minites to generate the boards.cfg
on a reasonable computer.

The idea popped up on my mind was to skip Makefiles and
to run script/kconfig/conf directly.
This tool should become about 4 times faster.
You might still not be satisfied, but better than doing nothing.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-08-28 17:18:49 -04:00
Masahiro Yamada
d1bf4afda6 tools/genboardscfg.py: check if the boards.cfg is up to date
It looks silly to regenerate the boards.cfg even when it is
already up to date.

The tool should exit with doing nothing if the boards.cfg is newer
than any of defconfig, Kconfig and MAINTAINERS files.

Specify -f (--force) option to get the boards.cfg regenerated
regardless its time stamp.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-08-28 17:18:49 -04:00
Masahiro Yamada
79d45d32bc tools/genboardscfg.py: fix minor problems on termination
This tool deletes the incomplete boards.cfg
if it encounters an error or is is terminated by the user.

I notice some problems even though they rarely happen.

[1] The boards.cfg is removed if the program is terminated
during __gen_boards_cfg() function but before boards.cfg
is actually touched.  In this case, the previous boards.cfg
should be kept as it is.

[2] If an error occurs while deleting the incomplete boards.cfg,
the program throws another exception.  This hides the privious
exception and we will not be able to know the real cause.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-08-28 17:18:49 -04:00
Masahiro Yamada
d6538d22de tools/genboardscfg.py: wait for unfinished subprocesses before error-out
When an error occurs or the program is terminated by the user
on the way, the destructer __del__ of class Slot is invoked and
the work directories are removed.

We have to make sure there are no subprocesses (in this case,
"make O=<work_dir> ...") using the work directories before
removing them.  Otherwise the subprocess spits a bunch of error
messages possibly causing more problems.  Perhaps some users
may get upset to see too many error messages.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-08-28 17:18:48 -04:00
Masahiro Yamada
13246f4861 tools/genboardscfg.py: be tolerant of insane Kconfig
The tools/genboardscfg.py expects all the Kconfig and defconfig are
written correctly.  Imagine someone accidentally has broken a board.
Error-out just for one broken board is annoying for the other
developers.  Let the tool skip insane boards and continue processing.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-08-28 17:18:48 -04:00
Masahiro Yamada
b8828e8ff3 tools/genboardscfg.py: be tolerant of missing MAINTAINERS
tools/genboardscfg.py expects all the boards have MAINTAINERS.
If someone adds a new board but misses to add its MAINTAINERS file,
tools/genboardscfg.py fails to generate the boards.cfg file.
It is annoying for the other developers.

This commit allows tools/genboardscfg.py to display warning messages
and continue processing even if some MAINTAINERS files are missing
or have broken formats.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-08-28 17:18:48 -04:00
Masahiro Yamada
04b43f3273 tools/genboardscfg.py: ignore defconfigs starting with a dot
Kconfig in U-Boot creates a temporary file configs/.tmp_defconfig
during processing "make <board>_defconfig".  The temporary file
might be left over for some reasons.

Just in case, tools/genboardscfg.py should make sure to
not read such garbage files.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-08-28 17:18:48 -04:00
Simon Glass
dfe6f4d684 Correct sandbox filesystem commands in FIT image test
The host filesystem name has changed, so update the tests. The tests now
run again correctly:

$ make O=b/sandbox sandbox_defconfig all
...
$ test/image/test-fit.py -u b/sandbox/u-boot
FIT Tests

=========
Kernel load
Kernel + FDT load
Kernel + FDT + Ramdisk load

Tests passed
Caveat: this is only a sanity check - test coverage is poor

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-08-28 17:18:48 -04:00
Simon Glass
fe20a81a68 Fix test failure caused by bad handling of ramdisk
Commit e3a5bbce broke the FIT image tests by not loading a ramdisk even if
a load address is provided in the FIT. The rationale was that a load address
of 0 should be considered to mean 'do not load'.

Add a new load operation which supports this feature, so that the ramdisk
will be loaded if a non-zero load address is provided.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-08-28 17:18:48 -04:00
Masahiro Yamada
4a8ed8e248 kconfig: add CONFIG_CC_OPTIMIZE_FOR_SIZE
Copy the Kconfig option from "init/Kconfig" of Linux v3.16 tag
and adjust the help document.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-28 17:18:48 -04:00
Masahiro Yamada
a6f47d2434 scripts: refetch scripts/setlocalversion from Linux 3.16
Now we have CONFIG_LOCALVERSION and CONFIG_LOCALVERSION_AUTO
in Kconfig so we can use scripts/setlocalversion without
any adjustment.  Copy it from Linux 3.16 as is.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-28 17:18:48 -04:00
Masahiro Yamada
e91c3c332b kconfig: add CONFIG_LOCALVERSION and CONFIG_LOCALVERSION_AUTO
Copy Kconfig options from "init/Kconfig" of Linux v3.16 tag
and adjust some parts of the help document.

Move CONFIG_SPL, CONFIG_TPL, ... etc. to "Boot images" menu.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-28 17:18:48 -04:00
Masahiro Yamada
390f7035d3 buildman: run genboardscfg.py all the time
This commit makes sure boards.cfg is up to date before starting
the build tests.  tools/genboardscfg.py exits immediately printing
"boards.cfg is up to date. Nothing to do." when boards.cfg is
already new.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-08-28 17:18:48 -04:00
Masahiro Yamada
94ab8f411c MAKEALL: run genboardscfg.py all the time
This commit makes sure boards.cfg is up to date before starting
the build tests.  tools/genboardscfg.py exits immediately printing
"boards.cfg is up to date. Nothing to do." when boards.cfg is
already new.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-28 17:18:48 -04:00
Masahiro Yamada
9c2d60c378 tools/genboardscfg.py: fix a bug of MAINTAINERS handling
This patch fixes a minor problem:
If a block without "F:   configs/*_defconfig" is followed by another
block with "F:   configs/*_defconfig", the maintainers from the
former block are squashed into the latter.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-28 17:18:48 -04:00
Łukasz Majewski
124c599875 samsung: s5p_goni: fix: Add missing definitions for G_DNL_UMS gadget
The commit (SHA1: 8fc171318e) reintroduced correct values for vendor and
product IDs required for UMS gadget to work properly either at Windows or
Linux.

This data was missing for GONI target, so this commit corrects this mistake.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Acked-by: Robert Baldyga <r.baldyga@samsung.com>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
2014-08-28 13:47:34 -04:00
Tom Rini
3e1b36bd58 Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-08-28 13:03:25 -04:00
Tom Rini
f91df8ca17 Merge branch 'patman' of http://git.denx.de/u-boot-x86 2014-08-28 11:49:12 -04:00
Simon Glass
042a732cf5 patman: Support the 'reverse' option for 'git log'
This option is currently not supported, but needs to be, for buildman to
operate as expected.

Reported-by: York Sun <yorksun@freescale.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2014-08-28 07:56:19 -07:00
Vasili Galka
2fea4f5add axs101: Fix type mismatch warning
Initialization of pointer from integer shall be designated by explicit
type cast.

Signed-off-by: Vasili Galka <vvv444@gmail.com>
Cc: Alexey Brodkin <alexey.brodkin@synopsys.com>
2014-08-26 18:54:02 +04:00
Vasili Galka
94bcd6b0ac arc: Fix printf size_t format related warnings (again...)
The basic idea: Define size_t using the __SIZE_TYPE__ compiler-defined
type.

For detailed explanation see similar patch for the nios2 arch:
http://patchwork.ozlabs.org/patch/379938/

Signed-off-by: Vasili Galka <vvv444@gmail.com>
Cc: Alexey Brodkin <alexey.brodkin@synopsys.com>
2014-08-26 17:41:58 +04:00
Heiko Schocher
4e67c57125 mtd,ubi,ubifs: sync with linux v3.15
snyc with linux v3.15:

commit 1860e379875dfe7271c649058aeddffe5afd9d0d
Author: Linus Torvalds <torvalds@linux-foundation.org>
Date:   Sun Jun 8 11:19:54 2014 -0700

    Linux 3.15

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Tom Rini <trini@ti.com>
2014-08-25 19:25:56 -04:00
Heiko Schocher
ddf7bcfa6c mtd, ubi, ubifs: update for the sync with linux v3.14
while playing with the new mtd/ubi/ubifs sync, found some
small updates for it:

- add del_mtd_partition() to include/linux/mtd/mtd
- mtd: add a debug_printf
- remove some not used functions

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Tom Rini <trini@ti.com>
2014-08-25 19:25:56 -04:00
Heiko Schocher
ff94bc40af mtd, ubi, ubifs: resync with Linux-3.14
resync ubi subsystem with linux:

commit 455c6fdbd219161bd09b1165f11699d6d73de11c
Author: Linus Torvalds <torvalds@linux-foundation.org>
Date:   Sun Mar 30 20:40:15 2014 -0700

    Linux 3.14

A nice side effect of this, is we introduce UBI Fastmap support
to U-Boot.

Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Tom Rini <trini@ti.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Sergey Lapin <slapin@ossfans.org>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Joerg Krause <jkrause@posteo.de>
2014-08-25 19:25:55 -04:00
Heiko Schocher
0c06db5983 lib, linux: move linux specific defines to linux/compat.h
- move linux specific defines from usb and video code
  into linux/compat.h
- move common linux specific defines from include/ubi_uboot.h
  to linux/compat.h
- add for new mtd/ubi/ubifs sync new needed linux specific
  defines to linux/compat.h

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
[trini: Add spin_lock_irqsave/spin_unlock_irqrestore dummies from
usb/lin_gadet_compat.h]
Signed-off-by: Tom Rini <trini@ti.com>
2014-08-25 19:25:03 -04:00
Heiko Schocher
cc96c9a79c linux include: add ERR_CAST
add missing ERR_CAST to linux/err.h as it is needed for ubi/ubifs support

Signed-off-by: Heiko Schocher <hs@denx.de>
2014-08-25 17:02:33 -04:00
Heiko Schocher
c068d44aac lib, list_sort: add list_sort from linux 3.14
from linux 3.14:

commit 455c6fdbd219161bd09b1165f11699d6d73de11c
Author: Linus Torvalds <torvalds@linux-foundation.org>
Date:   Sun Mar 30 20:40:15 2014 -0700

    Linux 3.14

Needed for the MTD/UBI/UBIFS resync

Just copied the files from Linux, and added in the c-file
the "#define __UBOOT__" for adding U-Boot special code. In
this case we use this just for adding including U-Boot
headers.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Sergey Lapin <slapin@ossfans.org>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Tom Rini <trini@ti.com>
2014-08-25 17:02:33 -04:00
Heiko Schocher
9dd228b5e7 lib, rbtree: resync with Linux-3.14
resync with linux:

commit 455c6fdbd219161bd09b1165f11699d6d73de11c
Author: Linus Torvalds <torvalds@linux-foundation.org>
Date:   Sun Mar 30 20:40:15 2014 -0700

    Linux 3.14

Needed for the MTD/UBI/UBIFS resync

Just copied the files from Linux, changed the license file header,
and add in the c-file:

+#define __UBOOT__
 #include <linux/rbtree_augmented.h>
+#ifndef __UBOOT__
 #include <linux/export.h>
+#else
+#include <ubi_uboot.h>
+#endif

so, it compiles for U-Boot.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Sergey Lapin <slapin@ossfans.org>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Tom Rini <trini@ti.com>
2014-08-25 17:02:33 -04:00
Matwey V. Kornilov
b640b460f5 pcm051: use ti_am335x_common.h config
Include general configs/ti_am335x_common.h and drop redundant #defines.

Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
2014-08-25 14:19:13 -04:00
Lokesh Vutla
7b92252370 ARM: DRA: Enable VTT regulator
DRA7 evm REV G and later boards uses a vtt regulator for DDR3 termination
and this is controlled by gpio7_11. Configuring gpio7_11.
The pad A22(offset 0x3b4) is used by gpio7_11 on REV G and later boards,
and left unused on previous boards, so it is safe enough to enable gpio
on all DRA7 boards.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2014-08-25 10:48:13 -04:00
Tom Rini
1286b7f6ca am335x_evm: Convert CONFIG_CONS_INDEX into a menu choice
- Drop CONFIG_SERIAL[1-6] and use CONFIG_CONS_INDEX tests instead
- Add choice and help text to board/ti/am335x/Kconfig
- Correct comment about IDK in board/ti/am335x/mux.c
- Remove am335x_evm_uart* defconfig files as they're just variations
  on a config option now.

Signed-off-by: Tom Rini <trini@ti.com>
2014-08-25 10:48:13 -04:00
Dmitry Lifshitz
bbfb286b8a cm-t54: convert to generic board
Use generic board setup functions by defining
CONFIG_SYS_GENERIC_BOARD.

Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il>
2014-08-25 10:48:13 -04:00
Dmitry Lifshitz
e1c9895c8f cm-t54: fix eMMC boot mode check
Boot from eMMC boot partition corresponds to BOOT_DEVICE_MMC2
omap_bootmode, while BOOT_DEVICE_MMC2_2 corresponds to the user
data partition boot.

Fix mmc_get_env_part() boot mode check to use a correct value.

Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il>
2014-08-25 10:48:13 -04:00
Dmitry Lifshitz
91c9885e6d cm-t54: fix EEPROM read return value check
Fix cl_eeprom_read_mac_addr() return value check.
Fix long line codding style issue in board_init().

Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il>
2014-08-25 10:48:13 -04:00
Sricharan R
f2a1b93b5c ARM: DRA7: Enable software leveling for dra7
Currently hw leveling is enabled by default on DRA7/72.
But the hardware team suggested to use sw leveling as hw leveling
is not characterized and seen some test case failures.
So enabling sw leveling on all DRA7 platforms.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2014-08-25 10:48:13 -04:00
Jeroen Hofstee
457baf5489 SOM: tam3517: convert to generic board
Cc: Raphael Assenat <raph@8d.com>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-08-25 10:48:12 -04:00
Vitaly Andrianov
61f66fd5a8 keystone2: use EFUSE_BOOTROM information to configure PLLs
This patch reads EFUSE_BOOTROM register to see the maximum supported
clock for CORE and TETRIS PLLs and configure them accordingly.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-08-25 10:48:12 -04:00
pekon gupta
9352697aa0 board/ti/dra7xx: add support for parallel NOR
This patch adds support for parallel NOR device (S29GL512S10) present on J6-EVM.
The Flash device is connected to GPMC controller on chip-select[0] and accessed
as memory-mapped device. It has data-witdh=x16, capacity-64MBytes(512Mbits) and
is CFI compatible.

As multiple devices are share GPMC pins on this board, so following board
settings are required to detect NOR device:
     SW5.1 (NAND_BOOTn) = OFF (logic-1)
     SW5.2 (NOR_BOOTn)  = ON  (logic-0) /* Active-low */
     SW5.3 (eMMC_BOOTn) = OFF (logic-1)
     SW5.4 (QSPI_BOOTn) = OFF (logic-1)

And also set appropriate SYSBOOT configurations:
     SW3.1 (SYSBOOT[ 8])= ON  (logic-1) /* selects SYS_CLK1 speed */
     SW3.2 (SYSBOOT[ 9])= OFF (logic-0) /* selects SYS_CLK1 speed */
     SW3.3 (SYSBOOT[10])= ON  (logic-1) /* wait-pin monitoring = enabled */
     SW3.4 (SYSBOOT[11])= OFF (logic-0) /* device type: Non Muxed */
     SW3.5 (SYSBOOT[12])= OFF (logic-0) /* device type: Non Muxed */
     SW3.6 (SYSBOOT[13])= ON  (logic-1) /* device bus-width: 1(x16) */
     SW3.7 (SYSBOOT[14])= OFF (logic-0) /* reserved */
     SW3.8 (SYSBOOT[15])= ON  (logic-1) /* reserved */

Also, following changes are required to enable NOR Flash support in
dra7xx_evm board profile:
2014-08-25 10:48:12 -04:00
pekon gupta
54a97d2849 board/ti/dra7xx: add support for parallel NAND
This patch adds support for x16 NAND device (MT29F2G16AAD) connected to GPMC
chip-select[0] on DRA7xx EVM.
As GPMC pins are shared by multiple devices, so in addition to this patch
following board settings are required for NAND device detection [1]:

  SW5.9 (GPMC_WPN)   = OFF (logic-1)
  SW5.1 (NAND_BOOTn) = ON  (logic-0) /* Active-low */
  SW5.2 (NOR_BOOTn)  = OFF (logic-1)
  SW5.3 (eMMC_BOOTn) = OFF (logic-1)
  SW5.4 (QSPI_BOOTn) = OFF (logic-1)

And also set appropriate SYSBOOT configurations
  SW2.1 (SYSBOOT[0]) = ON  (logic-1) /* selects NAND Boot */
  SW2.2 (SYSBOOT[1]) = OFF (logic-0) /* selects NAND Boot */
  SW2.3 (SYSBOOT[2]) = OFF (logic-0) /* selects NAND Boot */
  SW2.4 (SYSBOOT[3]) = OFF (logic-0) /* selects NAND Boot */
  SW2.5 (SYSBOOT[4]) = ON  (logic-1) /* selects NAND Boot */
  SW2.6 (SYSBOOT[5]) = ON  (logic-1) /* selects NAND Boot */
  SW2.7 (SYSBOOT[6]) = OFF (logic-0) /* reserved */
  SW2.8 (SYSBOOT[7]) = OFF (logic-0) /* reserved */

  SW3.1 (SYSBOOT[ 8])= ON  (logic-1) /* selects SYS_CLK1 speed */
  SW3.2 (SYSBOOT[ 9])= OFF (logic-0) /* selects SYS_CLK1 speed */
  SW3.3 (SYSBOOT[10])= ON  (logic-1) /* wait-pin monitoring = enabled */
  SW3.4 (SYSBOOT[11])= OFF (logic-0) /* device type: Addr/Data Muxed */
  SW3.5 (SYSBOOT[12])= ON  (logic-1) /* device type: Addr/Data Muxed */
  SW3.6 (SYSBOOT[13])= ON  (logic-1) /* device bus-width: 1(x16) */
  SW3.7 (SYSBOOT[14])= OFF (logic-0) /* reserved */
  SW3.8 (SYSBOOT[15])= ON  (logic-1) /* reserved */

Following changes are required in board.cfg to enable NAND on J6-EVM:
2014-08-25 10:48:12 -04:00
pekon gupta
e53ad4b445 board/ti/am43xx: add support for parallel NAND
This patch adds support for NAND device connected to GPMC chip-select on
following AM43xx EVM boards.

am437x-gp-evm: On this board, NAND Flash signals are muxed with eMMC, thus at a
  time either eMMC or NAND can be enabled. Selection between eMMC and NAND is
  controlled by:
  (a) Statically using Jumper on connecter (J89) present on board.
  (a) If Jumper on J89 is NOT used, then selection can be dynamically controlled
      by driving SPI2_CS0[MUX_MODE=GPIO] pin via software:
      SPI2_CS0 == 0: NAND (default)
      SPI2_CS0 == 1: eMMC

am43x-epos-evm: On this board, NAND Flash control lines are muxed with QSPI,
  Thus only one of the two can be used at a time. Selection is controlled by:
  (a) Dynamically driving following GPIO pin from software
      GPMC_A0(GPIO) == 0 NAND is selected (default)

NAND device (MT29F4G08AB) on these boards has:
 - data-width=8bits
 - blocksize=256KB
 - pagesize=4KB
 - oobsize=224 bytes
For above NAND device, ROM code expects the boot-loader to be flashed in BCH16
ECC scheme for NAND boot, So by default BCH16 ECC is enabled for AM43xx EVMs.

Signed-off-by: Pekon Gupta <pekon@ti.com>
2014-08-25 10:48:12 -04:00
pekon gupta
3df3bc1e1d board/ti/am335x: add support for beaglebone NOR Cape
This patch adds support of NOR cape[1] for both Beaglebone (white) and
Beaglebone(Black) boards. NOR Flash on this cape is connected to GPMC
chip-select[0] and accesses as external memory-mapped device.
This cape has 128Mbits(16MBytes), x16, CFI compatible NOR Flash device.

As GPMC chip-select[0] can be shared by multiple capes so NOR profile is
not enabled by default in boards.cfg. Following changes are required to
enable NOR cape detection when building am335x_boneblack board profile.

Signed-off-by: Tom Rini <trini@ti.com>
2014-08-25 10:47:56 -04:00
pekon gupta
85eb0de214 board/ti/am335x: add support for beaglebone NAND cape
Beaglebone Board can be connected to expansion boards to add devices to them.
These expansion boards are called 'capes'. This patch adds support for
following versions of Beaglebone(AM335x) NAND capes
(a) NAND Device with bus-width=16, block-size=128k, page-size=2k, oob-size=64
(b) NAND Device with bus-width=16, block-size=256k, page-size=4k, oob-size=224
Further information and datasheets can be found at [1] and [2]

* How to boot from NAND using Memory Expander + NAND Cape ? *
 - Important: As BOOTSEL values are sampled only at POR, so after changing any
   setting on SW2 (DIP switch), disconnect and reconnect all board power supply
   (including mini-USB console port) to POR the beaglebone.

 - Selection of ECC scheme
  for NAND cape(a), ROM code expects BCH8_HW ecc-scheme
  for NAND cape(b), ROM code expects BCH16_HW ecc-scheme

 - Selction of boot modes can be controlled via  DIP switch(SW2) present on
   Memory Expander cape.
   SW2[SWITCH_BOOT] == OFF  follow default boot order  MMC-> SPI -> UART -> USB
   SW2[SWITCH_BOOT] == ON   boot mode selected via DIP switch(SW2)
   So to flash NAND, first boot via MMC or other sources and then switch to
   SW2[SWITCH_BOOT]=ON to boot from NAND Cape.

 - For NAND boot following switch settings need to be followed
   SW2[ 1] = OFF  (SYSBOOT[ 0]==1: NAND boot mode selected )
   SW2[ 2] = OFF  (SYSBOOT[ 1]==1:       -- do --          )
   SW2[ 3] = ON   (SYSBOOT[ 2]==0:       -- do --          )
   SW2[ 4] = ON   (SYSBOOT[ 3]==0:       -- do --          )
   SW2[ 5] = OFF  (SYSBOOT[ 4]==1:       -- do --          )
   SW2[ 6] = OFF  (SYSBOOT[ 8]==1: 0:x8 device, 1:x16 device )
   SW2[ 7] = ON   (SYSBOOT[ 9]==0: ECC done by ROM  )
   SW2[ 8] = ON   (SYSBOOT[10]==0: Non Muxed device )
   SW2[ 9] = ON   (SYSBOOT[11]==0:    -- do --      )

[1] http://beagleboardtoys.info/index.php?title=BeagleBone_Memory_Expansion
[2] http://beagleboardtoys.info/index.php?title=BeagleBone_4Gb_16-Bit_NAND_Module

*IMPORTANT NOTE*
As Beaglebone board shares the same config as AM335x EVM, so following
changes are required in addition to this patch for Beaglebone NAND cape.
(1) Enable NAND in am335x_beaglebone board profile
(2) Add CONFIG_SYS_NAND_BUSWIDTH_16BIT to board config because:
 -  AM335x EVM has NAND device with datawidth=8, whereas
 -  Beaglebone NAND cape has NAND device with data-width=16
2014-08-25 08:52:34 -04:00
pekon gupta
fea9543f1b board/ti/am335x: update configs for parallel NAND
This patch
- consolidate CONFIG_SYS_NAND_xx and CONFIG_SPL_NAND_xx from various
  configuration files into single file.
- update MTD Partition table to match AM335x_EVM DT in linux-kernel
- segregate CONFIGs based on different boot modes (like SPL and U-Boot)

Signed-off-by: Pekon Gupta <pekon@ti.com>
2014-08-25 08:52:34 -04:00
Tom Rini
83e359adf9 am335x_evm: Enable CONFIG_SPL_ENV_SUPPORT on EMMC_BOOT
When we're using EMMC_BOOT that means we have environment on eMMC so
we can make use of CONFIG_SPL_ENV_SUPPORT within Falcon Mode.

Signed-off-by: Tom Rini <trini@ti.com>
2014-08-25 08:52:34 -04:00
Tom Rini
00e385325f common/Makefile: Consolidate SPL ENV options, correct inclusion
CONFIG_SPL_NET_SUPPORT is not the only time we want SPL to ahve
environment, CONFIG_SPL_ENV_SUPPORT is when we want it.

Signed-off-by: Tom Rini <trini@ti.com>
2014-08-25 08:52:34 -04:00
Tom Rini
e017fd61c5 tseries: Set CONFIG_ENV_IS_NOWHERE for SPL+NAND
In the case of SPL on these boards we only need environment for
SPL_USBETH, so it's safe to normally use ENV_IS_NOWHERE and SPL+NAND
does not support environment today.

Cc: Hannes Petermaier <oe5hpm@oevsv.at>
Signed-off-by: Tom Rini <trini@ti.com>
2014-08-25 08:52:34 -04:00
Tom Rini
865813ed83 TI:armv7: Change CONFIG_SPL_STACK to not be CONFIG_SYS_INIT_SP_ADDR
There are times where we may need more than a few kilobytes of stack
space.  We also will not be using CONFIG_SPL_STACK location prior to DDR
being initialized (CONFIG_SYS_INIT_SP_ADDR is still used there) so pick
a good location within DDR for this to be.  Tested on
OMAP4/AM335x/OMAP5/DRA7xx.

Signed-off-by: Tom Rini <trini@ti.com>
2014-08-25 08:52:34 -04:00
Tom Rini
6d9e610ca2 am335x_evm: Move SPL network defines
On am335x_evm we only support USBETH for a networking SPL option so move
the rest of the defines under that area as that's the only time we need
(and want) environment support here.

Signed-off-by: Tom Rini <trini@ti.com>
2014-08-25 08:52:34 -04:00
Tom Rini
7bee1c91a9 Merge branch 'agust@denx.de' of git://git.denx.de/u-boot-staging 2014-08-25 08:34:39 -04:00
Thomas Chou
055626acba nios2: remove EPCS driver
The Altera EPCS is SPI flash. We have been using SPI flash driver
to access EPCS for years. The old EPCS driver could be removed.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
2014-08-24 11:28:19 +08:00
Thomas Chou
5ff10aa7e7 nios2: add generic board support
This patch implements the generic board init as described in
doc/README.generic-board.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2014-08-24 11:28:10 +08:00
Thomas Chou
70fbc46192 nios2: remove obsolete PCI5441 and PK1C20 boards
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
2014-08-24 11:27:57 +08:00
Vasili Galka
00a2517fcb nios2: Fix printf size_t format related warnings (again...)
When compiling the current code on GCC 4.8.3, the following warnings
appear:

warning: format '%zu' expects argument of type 'size_t', but argument
2 has type 'long unsigned int' [-Wformat=]

There were many mails about such warnings on different architectures.
This patch limits itself to the nios2 architecture.

The problem is that for the size_t (%zu, %zd, ...) arguments of
printf GCC does not verify the type match to size_t type. It verifies
the type match to the compiler-defined __SIZE_TYPE__ type. Thus, if
size_t is defined different from __SIZE_TYPE__ - warnings inevitably
appear.

There is a comment by Thomas Chou to the (rejected) patch:
http://patchwork.ozlabs.org/patch/272102/
which explains that the older GCC toolchains (gcc-3.4.6 and gcc-4.1.2)
expect size_t to be "unsigned long" and the newer expect it to be
"unsigned int". Thus, no matter how we define size_t - either way
warnings appear when using some GCC version.

By rejecting that patch, a choice was made to prefer older GCC versions
and leave the warnings when building with the newer toolchains.
Personally, I disagree with this choice...

In any case, this patch proposes a way to fix the warnings for any GCC
version. Just define size_t using the __SIZE_TYPE__ compiler-defined
type and the type verification will pass.

I tested that this fixes the warning on GCC 4.8.3. I don't have an
older toolchain to test with, but __SIZE_TYPE__ was definitely defined
in GCC 3.4.6, so it should work there too.

Signed-off-by: Vasili Galka <vvv444@gmail.com>
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
2014-08-24 11:27:31 +08:00
Masahiro Yamada
7f6b8315d1 buildman: refactor help message
"buildman [options]" is displayed by default.

Append the rest of help messages to parser.usage
instead of replacing it.

Besides, "-b <branch>" is not mandatory since commit fea5858e.
Drop it from the usage.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-22 10:42:36 -04:00
Masahiro Yamada
23f78aeff4 git-mailrc: add patman and buildman alias
It's easier to Cc Simon on patches related to Patman or Buildman.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Simon Glass <sjg@chromium.org>
2014-08-22 10:42:32 -04:00
Masahiro Yamada
e0a4d06af2 patman: refactor help message
"patman [options]" is displayed by default.

Append the rest of help messages to parser.usage
instead of replacing it.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-22 10:41:50 -04:00
Masahiro Yamada
3ff291f371 kconfig: convert Kconfig helper script into a shell script
Commit 51148790 added scripts/multiconfig.py written in Python 2
to adjust Kconfig for U-Boot.

It has been hard for Python 3 users because Python 2 and Python 3
are not compatible with each other.

We are not happy about adding a new host tool dependency
(in this case, Python version dependency) for the core build process.
After some discussion, we decided to use only basic tools.

The script may get a bit more unreadable by shell scripting,
but we believe it is worthwhile.

In addition, this commit revives "<board>_config" target that is
equivalent to "<board>_defconfig" for backwards compatibility.
It is annoying to adjust various projects which use U-Boot.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Suggested-by: Igor Grinberg <grinberg@compulab.co.il>
Tested-by: Igor Grinberg <grinberg@compulab.co.il>
Acked-by: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@ti.com>
Cc: Jeroen Hofstee <jeroen@myspectrum.nl>
Cc: Stephen Warren <swarren@nvidia.com>
2014-08-22 10:41:50 -04:00
Roger Meier
fd18a89e7f Makefile: remove generated boards.cfg within make distclean
Signed-off-by: Roger Meier <roger@bufferoverflow.ch>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Tested-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
2014-08-22 10:41:35 -04:00
Thierry Reding
92ac8acc01 net: More BOOTP retry timeout improvements
It's not unusual for DHCP servers to take a couple hundred milliseconds
to respond to DHCP discover messages. One possible reason for the delay
can be that the server checks (typically using an ARP request) that the
IP it's about to hand out isn't in use yet. To make matters worse, some
servers may also queue up requests and process them sequentially, which
can cause excessively long delays if clients retry too fast.

Commit f59be6e850 ("net: BOOTP retry timeout improvements") shortened
the retry timeouts significantly, but the BOOTP/DHCP implementation in
U-Boot doesn't handle that well because it will ignore incoming replies
to earlier requests. In one particular setup this increases the time it
takes to obtain a DHCP lease from 630 ms to 8313 ms.

This commit attempts to fix this in two ways. First it increases the
initial retry timeout from 10 ms to 250 ms to give DHCP servers some
more time to respond. At the same time a cache of outstanding DHCP
request IDs is kept so that the implementation will know to continue
transactions even after a retransmission of the DISCOVER message. The
maximum retry timeout is also increased from 1 second to 2 seconds. An
ID cache of size 4 will keep DHCP requests around for 8 seconds (once
the maximum retry timeout has been reached) before dropping them. This
should give servers plenty of time to respond. If it ever turns out
that this isn't enough, the size of the cache can easily be increased.

With this commit the DHCP lease on the above-mentioned setup still takes
longer (1230 ms) than originally, but that's an acceptable compromise to
improve DHCP lease acquisition time for a broader range of setups.

To make it easier to benchmark DHCP in the future, this commit also adds
the time it took to obtain a lease to the final "DHCP client bound to
address x.x.x.x" message.

Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-08-21 12:01:30 -04:00
Bryan Wu
e6c88a6bbe bootm: make sure pass NULL when argc < 1
arg[0] might not be NULL even if argc < 1, so fix this as before.

Signed-off-by: Bryan Wu <pengw@nvidia.com>
2014-08-21 12:01:30 -04:00
Bryan Wu
6c454fedf5 image: fix bootm failure for FIT image
Commit b3dd64f5d5 "bootm: use genimg_get_kernel_addr()" introduced
a bug for booting FIT image. It's because calling fit_parse_config()
twice will give us wrong value in img_addr.

Add a new function genimg_get_kernel_addr_fit() whichl will always
return fit_uname_config and fit_uname_kernel for CONFIG_FIT.
genimg_get_kernel_addr() will ignore those to parameters.

Reported-by: York Sun <yorksun@freescale.com>
Signed-off-by: Bryan Wu <pengw@nvidia.com>
2014-08-21 12:01:29 -04:00
Masahiro Yamada
f28c9708e3 kconfig: remove DEFCONFIG_LIST
CONFIG_DEFCONFIG_LIST specifies the default defconfig.
It is used by "make savedefconfig" when .config is missing.
But that's it.  I could not find other useful cases.

As a side effect, CONFIG_DEFCONFIG_LIST="configs/sandbox_defconfig"
is contained in .config of every target board, which some people
think is odd.  So, let's remove it.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
2014-08-21 12:01:29 -04:00
Masahiro Yamada
bf52b8ae9f scripts/Lindent: import from Linux 3.16
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-21 12:01:29 -04:00
Vasili Galka
cac8f38aff Makefile: Use Kbuild style for system_map.o generation step
The command generating the "common/system_map.o" file was always shown
during the build making the output messy. Now it is called using the
Kbuild "cmd" macro, so that the full command is shown only when
building in verbose mode.

Signed-off-by: Vasili Galka <vvv444@gmail.com>
2014-08-21 12:01:29 -04:00
Colin Cross
478a32875a add header for Android sparse image format
Add a BSD-3 relicensed version of the Android sparse format image
header from:
28fa5bc347/libsparse/sparse_format.h
Unchanged except for the license header.

Cc: Tom Rini <trini@ti.com>
Signed-off-by: Colin Cross <ccross@android.com>
2014-08-21 12:01:29 -04:00
Jeroen Hofstee
11db3abe66 api: fix build without CMD_NET support
Provide stubs in case that no NET interface is supported.

Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-08-21 12:01:29 -04:00
Marek Vasut
951860634f e1000: add i210 support
Add i210 support to the e1000 driver.

Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Tim Harvey <tharvey@gateworks.com>
2014-08-21 12:01:28 -04:00
Marek Vasut
873e8e0198 e1000: Implement dcache support
Implement proper support for cache flushing and invalidation into the
Intel e1000 NIC driver.

Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Tim Harvey <tharvey@gateworks.com>
2014-08-21 12:01:28 -04:00
Roger Meier
5b12b7a193 tools/genboardscfg.py: no exception if columns undetectable
The existing terminalsize detection raised an exception on build
server. Just removes the exception. This also deactivates the
progress indicator.

Remove a trainling whitespace.

Signed-off-by: Roger Meier <roger@bufferoverflow.ch>
CC: Masahiro Yamada <yamada.m@jp.panasonic.com>
CC: Tom Rini <trini@ti.com>
2014-08-21 12:01:26 -04:00
Masahiro Yamada
ca418dd74b tools/genboardscfg.py: Do not output SPLCPU field
Prior to Kconfig, the CPU field of boards.cfg could optionally have
":SPLCPU", like "armv7:arm720t".
(Actually this syntax was only used for Tegra platform.)

Now it is not necessary at all because CPU is defined by
CONFIG_SYS_CPU in Kconfig.

For Tegra platform, the Kconfig option is described as follows:

  config SYS_CPU
          string
          default "arm720t" if SPL_BUILD
          default "armv7" if !SPL_BUILD

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-21 12:01:13 -04:00
Hans de Goede
b1ba62d4ae pxe: Allow use of environment variables in append string
Use cli_simple_process_macros, so that environment
variables (e.g. ${console}) can be used in append strings.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-08-21 12:01:13 -04:00
Hans de Goede
a06be2d077 cli: Export cli_simple_process_macros for use outside of cli_simple
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-08-21 12:01:13 -04:00
Masahiro Yamada
b0d7beefc1 davinci: orphan some Davinci boards
Emails to Sandeep Paulraj <s-paulraj@ti.com>
have been bouncing.

Please assign new maintainer(s) to get these boards
back to Maintained.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
2014-08-21 12:01:13 -04:00
Masahiro Yamada
aec6f8c59f powerpc: mpc8xx: remove FLAGADM board support
This board has been orphaned for a while and old enough.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-21 12:01:12 -04:00
Masahiro Yamada
6bde1ec10f powerpc: mpc8xx: remove GEN860T, GEN806T_SC board support
These boards have been orphaned for a while and old enough.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-21 12:01:12 -04:00
Masahiro Yamada
4723ce49e5 powerpc: mpc8xx: remove SXNI855T board support
This board has been orphaned for a while and old enough.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-21 12:01:12 -04:00
Masahiro Yamada
d1a4aafd71 powerpc: mpc8xx: remove svm_sc8xx board
This board has been orphaned for a while and old enough.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-21 12:01:12 -04:00
Masahiro Yamada
0ace4d9d8f powerpc: mpc8xx: remove stxxtc board support
This board has been orphaned for a while and old enough.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-21 12:01:12 -04:00
Masahiro Yamada
62d636aa2a omap: remove omap5912osk board support
Emails to the board maintainer
"Rishi Bhattacharya <rishi@ti.com>"
have been bouncing.

Tom suggested to remove this board.

Remove also omap1510_udc.c because this is the last board
to enable it.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Suggested-by: Tom Rini <trini@ti.com>
2014-08-21 12:01:12 -04:00
Masahiro Yamada
9b586031db scripts: objdiff: sync with Linux 3.16
Import scripts/objdiff improvements from Linux v3.16, which
consists of 7 commits written by me.

  commit 7fa0e6db3cedc9b70d68a4170f1352e2b1aa0f90
  scripts: objdiff: support directories for the augument of record command

  commit 8ac28bee76eec006aac5ba5c418878a607d53a9b
  scripts: objdiff: fix a comment

  commit 8b5d0f20d64f00ffd5685879f8eb3659379f5aaa
  scripts: objdiff: change the extension of disassembly from .o to .dis

  commit 18165efa8203a34d82f60a1831ea290e7304c654
  scripts: objdiff: improve path flexibility for record command

  commit 1ecc8e489abfdaa6d8d1689f7ff62fdf1adda30c
  scripts: objdiff: remove unnecessary code

  commit 5ab370e91af70d5f1b1dbaec78798a2ff236a2d5
  scripts: objdiff: direct error messages to stderr

  commit fd6e12423311697860f30d10398a0f9eb91977d2
  scripts: objdiff: get the path to .tmp_objdiff more simply

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-21 12:01:11 -04:00
Masahiro Yamada
e773440425 kbuild: sync mixed targets handling with Linux 3.16
"make %_config all" was supported for the first time in U-Boot:
  commit 53bca5ab
  kbuild: support simultaneous board configuration and "make all"

Surprisingly it had not been working in Linux Kernel for a long time.

So I sent back the patch to the Linux Kbuild community and it was
accepted with a little code improvement, at commit 9319f453.

Now, you can do "make defconfig all" or "make %_defconfig all"
in Linux too.

This commit updates some scripts to fill the code-diff
between Linux and U-Boot.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-21 12:01:11 -04:00
Masahiro Yamada
6419e14492 kbuild: move extra gcc checks to scripts/Makefile.extrawarn
This commit was imported from Linux Kernel:
commit a86fe353 written by me.

W=... provides extra gcc checks.

Having such code in scripts/Makefile.build results in the same flags
being added to KBUILD_CFLAGS multiple times becuase
scripts/Makefile.build is invoked every time Kbuild descends into
the subdirectories.

Since the top Makefile is already too cluttered, this commit moves
all of extra gcc check stuff to a new file scripts/Makefile.extrawarn,
which is included from the top Makefile.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-21 12:01:11 -04:00
Masahiro Yamada
368b4d2b49 drivers: net: remove dead drivers
The following configs are not defined at all:

 - CONFIG_INCA_IP_SWITCH
 - CONFIG_PBL2800_ETHER
 - CONFIG_PHY_ICPLUS

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-21 12:01:11 -04:00
Masahiro Yamada
31e2141d5a tools, scripts: refactor error-out statements of Python scripts
In Python, sys.exit() function can also take an object other
than an integer.

If an integer is given to the argument, Python exits with the return
code of it.  If a non-integer argument is given, Python outputs it
to stderr and exits with the return code of 1.

That means,

    print >> sys.stderr, "Blah Blah"
    sys.exit(1)

is equivalent to

    sys.exit("Blah Blah")

The latter is a useful shorthand.

Note:
Some error messages in Buildman and Patman were output to stdout.
But they should go to stderr.  They are also fixed by this commit.
This is a nice side effect.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-08-21 12:01:11 -04:00
Masahiro Yamada
6933b5c9f3 README.kconfig: add initial version of Kconfig document
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-21 12:01:11 -04:00
Tom Rini
67ee22b068 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2014-08-20 16:07:34 -04:00
Valentin Longchamp
f38391793f kmp204x: reset the Zarlink clocking chips at power up only
There is the requirement on the chassis's backplane that when the clocks
have been enabled, they then should not disappear.

Resetting the Zarlink clocking chips at unit reset violates this
requirement because the backplane clocks are not supplied during the
reset time.

To avoid this side effect, both the Zarlink clocking chips are reset
only at power up.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
2014-08-20 10:44:42 -07:00
York Sun
8af353bb0e powerpc/t4qds: Move doc/README.t4240qds under board/freescale/t4qds
Board specific README file should be moved to board folder.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-08-20 10:44:16 -07:00
Shaohui Xie
9bf499ace8 powerpc/T4240QDS/eth: some fix for XFI
XFI is supported on T4QDS-XFI board, which removed slot3, and four LANEs
of serdes2 are routed to a SFP+ cages, which to house fiber cable or
direct attach cable(copper), the copper cable is used to emulate the
10GBASE-KR scenario.

So, for XFI usage, there are two scenarios, one will use fiber cable,
another will use copper cable. For fiber cable, there is NO PHY, while
for copper cable, we need to use internal PHY which exist in Serdes to
do auto-negotiation and link training, which implemented in kernel.
We use hwconfig to define cable type for XFI, and fixup dtb based on the
cable type.

For copper cable, set below env in hwconfig:

fsl_10gkr_copper:<10g_mac_name>

the <10g_mac_name> can be fm1_10g1, fm1_10g2, fm2_10g1, fm2_10g2. The
four <10g_mac_name>s do not have to be coexist in hwconfig. For XFI ports,
if a given 10G port will use the copper cable for 10GBASE-KR, set the
<10g_mac_name> of the port in hwconfig, otherwise, fiber cable will be
assumed to be used for the port.

For ex. if four XFI ports will both use copper cable, the hwconfig
should contain:

fsl_10gkr_copper:fm1_10g1,fm1_10g2,fm2_10g1,fm2_10g2

For fiber cable:

1. give PHY address to a XFI port, otherwise, the XFI ports will not be
available in U-boot, there is no PHY physically for XFI when using fiber
cable, this is just to make U-boot happy and we can use the XFI ports
in U-boot.
2. fixup dtb to use fixed-link in case of fiber cable which has no PHY.
Kernel requests that a MAC must have a PHY or fixed-link.

When using XFI protocol, the MAC 9/10 on FM1 should init as 10G interface.

Change serdes 2 protocol 56 to 55 which has same feature as 56 since 56
is not valid any longer.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-08-20 10:44:16 -07:00
Valentin Longchamp
2475367670 km-powerpc: define CONFIG_PRAM to protect PHRAM and PNVRAM
When u-boot initializes the RAM (early in boot) it looks for the "pram"
env variable to know which is area it cannot use. If the "pram" env variable
is not found, the default CONFIG_PRAM value is used.

This value used to be 0 (no protection at all). This patch sets it to a
value that covers PHRAM and PNVRAM that must be protected in our case.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-08-20 10:44:16 -07:00
Vijay Rai
12eeb1359a driver/qe: update status of QE microcode
This Patch updates error print for QE which should be easily understood

Signed-off-by: Vijay Rai <vijay.rai@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-08-20 10:44:16 -07:00
Shaveta Leekha
390619ddb3 powerpc/mpc85xx: Enabling CPC conditionally based on hwconfig options
If hwconfig does not contains "en_cpc" then by default all cpcs are enabled
If this config is defined then only those individual cpcs which are defined
in the subargument of "en_cpc" will be enabled e.g en_cpc:cpc1,cpc2; (this
will enable cpc1 and cpc2) or en_cpc:cpc2; (this enables just cpc2)

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-08-20 10:44:15 -07:00
Fabio Estevam
d145878d59 mx6sxsabresd: Add Ethernet support
mx6sxsabresd board has 2 FEC ports, each one connected to a AR8031.

Add support for one FEC port initially.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-08-20 13:15:23 +02:00
Fabio Estevam
5c045cddaa mx6sx: Adjust enable_fec_anatop_clock() for mx6solox
Configure and enable the ethernet clock for mx6solox.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-08-20 13:14:09 +02:00
Fabio Estevam
080d72f233 mx6sxsabresd: Convert to the new Kconfig style
mx6sxsabresd was not in the master branch when the conversion to the new Kconfig
style happened, so convert it now so that it can build again.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-08-20 13:11:12 +02:00
Lukasz Majewski
801123fe50 test: ums: Add script for testing UMS gadget operation
This commit adds new test for UMS USB gadget to u-boot mainline tree.
It is similar in operation to the one already available in test/dfu
directory.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
2014-08-20 13:10:33 +02:00
Lukasz Majewski
4c984c8136 test: dfu: cosmetic: Add missing license information to DFU test scripts
By mistake I've forgotten to add the SPDX license tags for the DFU testing
scripts.
This commit fixes that and also provides some other relevant information.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
2014-08-20 13:10:33 +02:00
Lukasz Majewski
0d7f85f057 test: dfu: Extend dfu_gadget_test_init.sh to accept sizes of test files
It is now possible to pass to the dfu_gadget_test_init.sh script the sizes
of files to be generated.

This feature is required by UMS tests which reuse this code.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
2014-08-20 13:10:32 +02:00
Lukasz Majewski
8fc171318e samsung: dfu: Provide correct Vendor and Product IDs for UMS gadget
It is necessary to provide the same Vendor and Product IDs as the one in
the original Linux kernel code.

Without this change the USB mass storage gadget is not working with Windows7.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
2014-08-20 13:10:32 +02:00
Tim Harvey
9c0fe83eb5 imx: ventana: add econfig command
The Gateworks Ventana EEPROM contains a set of configuration bits that
affect the removal of device-tree nodes that support peripherals that do not
exist on sub-loaded boards. This patch adds:
 - a structure to define a config bit name, dt node alias, bit position
 - an array of supported configuration items
 - an econfig command to get/set/list configuration bits
 - use of the array when adjusting the FDT prior to boot

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2014-08-20 13:08:37 +02:00
Tim Harvey
6a9032112e imx: ventana: leave PCI reset de-asserted if PCI enabled
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2014-08-20 13:04:12 +02:00
Tim Harvey
6a165904ac imx: ventana: add iomux for PCISKT_WDIS# gpio
The PCISKT_WDIS# gpio allows for asserting WDIS# going to the various PCIe
sockets on the Ventana board.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2014-08-20 13:03:09 +02:00
Tim Harvey
d9d4149296 imx: ventana: enable SION bit on gpio outputs
Enable the SION bit on gpio outputs that we wish to be able to read the
value of.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2014-08-20 13:02:28 +02:00
Tim Harvey
2cb6e529d3 imx: ventana: configure i2c_dis# pin properly for gw53xx
The i2c_dis# pinmux/padconf was missing for the GW53xx (this feature was
added to the GW53xx on revB PCB's). Additionally, remove the duplicate
config for GW54xx.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2014-08-20 13:01:29 +02:00
Tim Harvey
49281f4d6d imx: ventana: add missing crlf to print
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2014-08-20 12:59:50 +02:00
Tim Harvey
b40833d8ee imx: ventana: add video enable gpio pinmux for GW54xx
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2014-08-20 12:58:50 +02:00
Tim Harvey
e5131d53bf imx: ventana: add appropriate delay following GSC i2c write
The Gateworks System Controller EEPROM config is flash based. Add a delay
following writes to avoid errors on back-to-back writes.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2014-08-20 12:53:50 +02:00
Tim Harvey
2325bb1898 imx: ventana: remove caam disable per eeprom bit
During manufacturing this bit is not getting enabled when it should be, so
we will ignore it.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2014-08-20 12:52:58 +02:00
Tim Harvey
63b85adcec imx: ventana: set dynamic env var for flash layout
NAND devices have differing layouts with respect to page size and pages per
block. These parameters affect the parameters that need to be passed to
mkfs.ubifs and ubinize used to create UBI images. The various NAND chips
supported by Gateworks Ventana fall into two different layouts which we
refer to as 'normal' and 'large'. This layout is useful when referencing
ubi files to download and flash so we create a dynamic env variable for it.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2014-08-20 12:51:35 +02:00
Fabio Estevam
eb5c18078d mx6sxsabresd: Update DDR initialization
Use the latest DDR initialization values suggested by the FSL hardware team.

While at it, add some comments for clarification.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-08-20 12:41:41 +02:00
Tim Harvey
5a82e1a21d pci: mx6: fix occasional link failures
According to the IMX6 reference manuals, REF_SSP_EN (Reference clock enable
for SS function) must remain deasserted until the reference clock is running
at the appropriate frequency.

Without this patch we find a high link failure rate (>5%) on certain
IMX6 boards at various temperatures.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-08-20 12:37:15 +02:00
Marek Vasut
0351ef97d7 ARM: mx6: Enable Thumb build for SPL
Building the SPL in Thumb mode saves roughly 30% in size of the
resulting SPL binary. As the size of SPL it limited on the MX6,
this helps a lot.

Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Tim Harvey <tharvey@gateworks.com>
2014-08-20 12:23:45 +02:00
Marek Vasut
b299ab7435 ARM: mx6: Handle the MMDCx_MDCTL COL field caprices
The COL field value cannot be easily calculated from the desired
column number. Instead, there are special cases for that, see the
datasheet, MMDCx_MDCTL field description, field COL . Cater for
those special cases.

Signed-off-by: Marek Vasut <marex@denx.de>
2014-08-20 12:22:52 +02:00
Marek Vasut
fcfdfdd58c ARM: mx6: Prevent overflow in DRAM size detection
The MX6 DRAM controller can be configured to handle 4GiB of DRAM, but
only 3840 MiB of that can be really used. In case the controller is
configured to operate a 4GiB module, the imx_ddr_size() function will
correctly compute that there is 4GiB of DRAM in the system. Firstly,
the return value is 32-bit, so the function will effectively return
zero. Secondly, the MX6 cannot address the full 4GiB, but only 3840MiB
of all that. Thus, clamp the returned size to 3840MiB in such case.

Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Tim Harvey <tharvey@gateworks.com>
2014-08-20 12:21:57 +02:00
Marek Vasut
68968901e7 ARM: mx5: Fix CHSCCDR name
Fix the name of the CCM CHSCCDR register.

Signed-off-by: Marek Vasut <marex@denx.de>
2014-08-20 12:19:20 +02:00
Fabio Estevam
5494b92dea mx31pdk: Change maintainer
Currently I don't have access to a mx31pdk board.

Magnus was the original maintainer of the board and accepted to take back
this role.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Magnus Lilja <lilja.magnus@gmail.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2014-08-20 12:14:31 +02:00
Gabriel Huau
a76df70908 mx6: add support of multi-processor command
This allows u-boot to load different OS or Bare Metal application on
different cores of the i.MX6 SoC.
For example: running Android on cpu0 and a RT OS like QNX/FreeRTOS on cpu1.

Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
Acked-by: Stefano Babic <sbabic@denx.de>
2014-08-20 11:52:54 +02:00
Stephen Warren
a78cf41e79 ARM: tegra: remove custom define for Jetson TK1
Now that Kconfig has a per-board option, we can use that directly rather
than inventing a custom define for the AS3722 code to determine which
board it's being built for.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-08-19 08:44:03 -07:00
Michal Simek
ae2ee77f98 ARM: zynq: Remove spl.h
Do not specify own zynq specific SPL macros
because there is no need for that.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-19 08:48:18 +02:00
Michal Simek
dbc31f6a20 ARM: zynq: Move ps7_init() out of spl.h
Prepare for spl.h removal.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-19 08:48:00 +02:00
Stefan Agner
24d4d422c1 ARM: tegra: add Colibri T30 board support
This adds board support for the Toradex Colibri T30 module.

Working functions:
- SD card boot
- eMMC environment and boot
- USB host/USB client (on the dual role port)
- Network (via ASIX USB)

Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-08-18 16:59:04 -07:00
Stephen Warren
aeb3fcb359 ARM: tegra: Use mem size from MC rather than ODMDATA
In at least Tegra124, the Tegra memory controller (MC) has a register
that controls the memory size. Read this to determine the memory size
rather than requiring this to be redundantly encoded into the ODMDATA.
This way, changes to the BCT (i.e. MC configuration) automatically
updated SW's view of the memory size, without requiring manual changes
to the ODMDATA.

Future work potentially required:
* Clip the memory size to architectural limits; U-Boot probably doesn't
  and won't support either LPAE or Tegra's "swiss cheese" memory layout,
  at least one of which would be required for >2GB RAM.
* Subtract out any carveout required by firmware on future SoCs.

Based-on-work-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-08-18 16:57:03 -07:00
Stephen Warren
39446bcefa ARM: tegra: enable DFU too
Enable DFU protocol support (via the "dfu" command) on Tegra boards where
USB device/gadget mode is enabled.

Note that for DFU to operate correctly on Tegra, we still need some DFU
fixes/enhancements that are going through the DFU -> USB trees. However,
the code builds just fine without those changes, and applying this patch
now will allow both sets of patches to meet in the main U-Boot tree much
more quickly.

In order to run test/dfu/dfu_gadget_test.sh, you would need to add the
following to the board configuration:

CONFIG_EXT4_WRITE
CONFIG_CMD_EXT4_WRITE

However, I haven't enabled those here, since I believe the main use-case
for DFU on Tegra is raw flash writing, rather than filesystem access, so
we don't need the additional code-size hit. However, I could be persuaded
otherwise! We should probably add a separate test script for raw flash
access.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-08-18 16:57:03 -07:00
Bryan Wu
df3443dfa4 ARM: tegra: Disable VPR
On Tegra114 and Tegra124 platforms, certain display-related registers cannot
be accessed unless the VPR registers are programmed.  For bootloader, we
probably don't care about VPR, so we disable it (which counts as programming
it, and allows those display-related registers to be accessed).

This patch is based on the commit 5f499646c83ba08079f3fdff6591f638a0ce4c0c
in Chromium OS U-Boot project.

Signed-off-by: Andrew Chew <achew@nvidia.com>
Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Signed-off-by: Bryan Wu <pengw@nvidia.com>
[acourbot: ensure write went through, vpr.c style changes]
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Cc: Tom Warren <TWarren@nvidia.com>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-08-18 16:57:02 -07:00
Sascha Silbe
9fa7bbc126 openrd: fail build if U-Boot would overlap with environment in flash
Set CONFIG_BOARD_SIZE_LIMIT so we'll notice at build time if U-Boot
has grown so large that it would overlap with the environment area in
flash, rather than bricking the device at run-time on first saveenv.

Signed-off-by: Sascha Silbe <t-uboot@infra-silbe.de>
2014-08-14 16:01:05 +02:00
Sascha Silbe
feb858012f README: document CONFIG_BOARD_SIZE_LIMIT
CONFIG_BOARD_SIZE_LIMIT was introduced by f3a14d37 [Makefile: allow
boards to check file size limits] and is in use by several boards, but
never got documented.

Signed-off-by: Sascha Silbe <t-uboot@infra-silbe.de>
2014-08-14 15:57:08 +02:00
Heiko Schocher
1668d64439 mtdparts: fix usecount bug
add missing put_mtd_device, so mtd->usecount gets correct
decremented in get_mtd_info().

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Tom Rini <trini@ti.com>
2014-08-14 15:00:57 +02:00
Markus Niebel
412921d29e RTC: add support for DS1339 (using DS1307 driver)
Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com>
2014-08-14 14:45:58 +02:00
vijay rai
5be1af0198 driver/qe: update status of QE microcode
This Patch updates error print for QE which should be easily understood

Signed-off-by: Vijay Rai <vijay.rai@freescale.com>
2014-08-14 14:22:09 +02:00
Luka Perkov
31cbe80c33 mkimage: fix compilation issues on OpenBSD
Signed-off-by: Luka Perkov <luka@openwrt.org>
2014-08-14 11:48:11 +02:00
Stephen Warren
d878c9a932 pci: fix overflow in __pci_hose_bus_to_phys w/ large RAM
If a 32-bit system has 2GB of RAM, and the base address of that RAM is
2GB, then start+size will overflow a 32-bit value (to a value of 0).

To avoid such an overflow, convert __pci_hose_bus_to_phys() to calculate
the offset of a bus address into a PCI region, rather than comparing a
bus address against the end of a PCI region.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-08-14 11:38:47 +02:00
Heiko Schocher
686dca0fc4 tools, fit_info: increase buffer for command name
currently the buffer for command name is 50 bytes only. If using
fit_info with long absolute paths, this is not enough, so raise
it to 256 (as it is in fit_check_sign)

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
2014-08-14 11:20:24 +02:00
Heiko Schocher
04a710a593 tools: fix typo in tools/image-host.c
fix a typo in error printf. If FIT_CONFS_PATH is not found
print FIT_CONFS_PATH not FIT_IMAGES_PATH.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
2014-08-14 11:20:01 +02:00
Simon Glass
e49f14af13 patman: Only use git's --no-decorate when available
Older versions of git (e.g. Ubuntu 10.04) do not support this flag. By
default they do not decorate. So only enable this flag when supported.

Suggested-by: Tom Rini <trini@ti.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2014-08-13 08:34:16 -06:00
Simon Glass
cda2a61152 patman: Move the 'git log' command into a function
Move the code that builds a 'git log' command into a function so we can more
easily adjust it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-08-13 08:34:16 -06:00
Simon Glass
3b74ba5f1a buildman: Allow selection of the number of commits to build
It is useful to be able to build only some of the commits in a branch. Add
support for the -c option to allow this. It was previously parsed by
buildman but not implemented.

Suggested-by: York Sun <yorksun@freescale.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: York Sun <yorksun@freescale.com>
2014-08-13 08:34:16 -06:00
Simon Glass
6131beab69 buildman: Introduce an 'and' operator for board selection
Currently buildman allows a list of boards to build to be specified on the
command line. The list can include specific board names, architecture, SOC
and so on.

At present the list of boards is dealt with in an 'OR' fashion, and there
is no way to specify something like 'arm & freescale', meaning boards with
ARM architecture but only those made by Freescale. This would exclude the
PowerPC boards made by Freescale.

Support an '&' operator on the command line to permit this. Ensure that
arguments can be specified in a single string to permit easy shell quoting.

Suggested-by: York Sun <yorksun@freescale.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: York Sun <yorksun@freescale.com>
2014-08-13 08:34:16 -06:00
Simon Glass
e956947858 buildman: Add a few more toolchain examples to the README
The current README is a bit sparse in this area, so add a few more
examples.

Suggested-by: Tom Rini <trini@ti.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2014-08-13 08:34:16 -06:00
Simon Glass
28370c1b99 buildman: Add a message indicating there are no errors
If buildman finds no problems it prints nothing. This can be a bit confusing,
so add a message that all is well.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-08-13 08:34:15 -06:00
Simon Glass
0f7c9ddaed buildman: Add an option to specify the buildman config file
Add a new --config-file option (-G) to specify a different configuration
file from the default ~/.buildman.

Reported-by: Tom Rini <trini@ti.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2014-08-13 08:34:15 -06:00
Simon Glass
d3269ed380 buildman: Remove unused non-incremental build method code
The non-incremental build method is no longer used, so remove it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-08-13 08:34:15 -06:00
Simon Glass
e5a0e5d842 buildman: Add verbose option to display errors as they happen
Normally buildman operates in two passes - one to do the build and another
to summarise the errors. Add a verbose option (-v) to display build problems
as they happen. With -e also given, this will display errors too.

When building the current source tree (rather than a list of commits in a
branch), both -v and -e are enabled automatically.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-08-13 08:34:15 -06:00
Simon Glass
b2ea7ab252 buildman: Refactor output options
We need the output options to be available in several places. It's a pain
to pass them into each function. Make them properties of the builder and
add a single function to set them up. At the same time, add a function which
produces summary output using these options.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-08-13 08:34:15 -06:00
Simon Glass
c1de501492 buildman: Sort command line options
These options have got slightly out of order. Fix them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-08-13 08:34:15 -06:00
Simon Glass
190064b4da buildman: Move BuilderThread code to its own file
The builder.py file is getting too long, so split out some code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-08-13 08:34:14 -06:00
Simon Glass
fea5858eb9 buildman: Allow building of current source tree
Originally buildman had some support for building the current source tree.
However this was dropped before it was submitted, as part of the effort to
make it faster when building entire branches.

Reinstate this support. If no -b option is given, buildman will build the
current source tree.

Reported-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2014-08-13 08:34:14 -06:00
Simon Glass
6eede34ce6 buildman: Add some notes about moving from MAKEALL
For those used to MAKEALL, buildman seems strange. Add some notes to ease
the transition.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-08-13 08:34:14 -06:00
Simon Glass
cec83c3e63 buildman: Fix a few typos
There are several typos in the README - fix them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-08-13 08:34:14 -06:00
Iain Paton
015e215bbf embest/mx6boards: only toggle eMMC usdhc3 RST line on MarSboard
On MarS usdhc3 is eMMC, on RIoT usdhc3 is uSD and eMMC is usdhc4.

Don't run the MarS specific eMMC reset code on usdhc3 when
board_type == BOARD_IS_RIOTBOARD

Signed-off-by: Iain Paton <ipaton0@gmail.com>
2014-08-13 09:32:53 +02:00
Stefano Babic
7e9291720d Update aristainetos board to Kconfig
aristainetos board was merged in u-boot-imx before
Kconfig was integrated, but it is not yet
mainline.

Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Heiko Schocher <hs@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
2014-08-13 09:30:41 +02:00
Tom Rini
5b7d0027c2 Merge branch 'master' of git://git.denx.de/u-boot-blackfin 2014-08-12 16:54:55 -04:00
Tang Yuantian
ce249d956c powerpc/t104xrdb: support deep sleep in SPI/SD boot
Add deep sleep support in SPI/SD boot. The destination address
second stage uboot image is loaded to is changed because
currently this address will be used by kernel which means
we can't reserve it for resume.

Entry point to kernel is still placed in second stage uboot.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-08-12 12:26:47 -07:00
Tang Yuantian
3067547502 powerpc/mpc85xx: Make boot flag effective
bootflag as a parameter is passed to board_init_f().
But it is not actually used in this function.
Make it effective by assigned it to gd->flags.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-08-12 12:26:47 -07:00
Jason Jin
cf8ddacffc powerpc/t1042RDB: Add Video - HDMI support
T1042 has internal display interface unit (DIU) for driving video.
T1042RDB supports video mode via
-LCD using TI enconder
-HDMI type interface via HDMI encoder

Chrontel, CH7301C encoder which is I2C programmable is used
as HDMI connector on T1042RDB.
This patch add support to
-enable Video interface for T1042RDB
-route qixis multiplexing to enable DIU-HDMI interface on board
-program DIU pixel clock gerenartor for T1042
-program HDMI encoder via I2C on board

This patch refer to the upstream diu patch
(337b0c52b3) for T1040qds.

Signed-off-by: Jason Jin <Jason.Jin@freescale.com>
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
[York Sun: resolve conflict and move changes to T104xRDB.h]
Reviewed-by: York Sun <yorksun@freescale.com>
2014-08-12 12:26:47 -07:00
Wang Dongsheng
c53711bb62 fsl/diu: ch7301 encoder split off from t1040qds/diu.c
The ch7301 encoder not only used in t1040qds platform, so we split
it for t1042rdb and LSx platform.

Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-08-12 12:26:46 -07:00
Siarhei Siamashka
bf4ca384ad sunxi: dram: Autodetect DDR3 bus width and density
In the case if the 'dram_para' struct does not specify the exact bus
width or chip density, just use a trial and error method to find a
usable configuration.

Because all the major bugs in the DRAM initialization sequence are
now hopefully fixed, it should be safe to re-initialize the DRAM
controller multiple times until we get it configured right. The
original Allwinner's boot0 bootloader also used a similar
autodetection trick.

The DDR3 spec contains the package pinout and addressing table for
different possible chip densities. It appears to be impossible to
distinguish between a single chip with 16 I/O data lines and a pair
of chips with 8 I/O data lines in the case if they provide the same
storage capacity. Because a single 16-bit chip has a higher density
than a pair of equivalent 8-bit chips, it has stricter refresh timings.
So in the case of doubt, we assume that 16-bit chips are used.
Additionally, only Allwinner A20 has all A0-A15 address lines and
can support densities up to 8192. The older Allwinner A10 and
Allwinner A13 can only support densities up to 4096.

We deliberately leave out DDR2, dual-rank configurations and the
special case of a 8-bit chip with density 8192. None of these
configurations seem to have been ever used in real devices. And no
new devices are likely to use these exotic configurations (because
only up to 2GB of RAM can be populated in any case).

This DRAM autodetection feature potentially allows to have a single
low performance fail-safe DDR3 initialiazation for a universal single
bootloader binary, which can be compatible with all Allwinner
A10/A13/A20 based devices (if the ifdefs are replaced with a runtime
SoC type detection).

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-08-12 08:42:34 +02:00
Siarhei Siamashka
935758b1d5 sunxi: dram: Derive write recovery delay from DRAM clock speed
The write recovery time is 15ns for all JEDEC DDR3 speed bins. And
instead of hardcoding it to 10 cycles, it is possible to set tighter
timings based on accurate calculations. For example, DRAM clock
frequencies up to 533MHz need only 8 cycles for write recovery.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-08-12 08:42:33 +02:00
Siarhei Siamashka
b5c71f5f9c sunxi: dram: Drop DDR2 support and assume only single rank DDR3 memory
All the known Allwinner A10/A13/A20 devices are using just single rank
DDR3 memory. So don't pretend that we support DDR2 or more than one
rank, because nobody could ever test these configurations for real and
they are likely broken. Support for these features can be added back
in the case if such hardware actually exists.

As part of this code cleanup, also replace division by 1024 with
division by 1000 for the refresh timing calculations. This allows
to use the original non-skewed tRFC timing table from the DRR3 spec
and make code less confusing.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-08-12 08:42:33 +02:00
Siarhei Siamashka
d755a5fb20 sunxi: dram: Configurable DQS gating window mode and delay
The hardware DQS gate training is a bit unreliable and does not
always find the best delay settings.

So we introduce a 32-bit 'dqs_gating_delay' variable, where each
byte encodes the DQS gating delay for each byte lane. The delay
granularity is 1/4 cycle.

Also we allow to enable the active DQS gating window mode, which
works better than the passive mode in practice. The DDR3 spec
says that there is a 0.9 cycles preamble and 0.3 cycle postamble.
The DQS window has to be opened during preamble and closed during
postamble. In the passive window mode, the gating window is opened
and closed by just using the gating delay settings. And because
of the 1/4 cycle delay granularity, accurately hitting the 0.3
cycle long postamble is a bit tough. In the active window mode,
the gating window is auto-closing with the help of monitoring
the DQS line, which relaxes the gating delay accuracy requirements.

But the hardware DQS gate training is still performed in the passive
window mode. It is a more strict test, which is reducing the results
variance compared to the training with active window mode.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-08-12 08:42:33 +02:00
Siarhei Siamashka
e044daa33e sunxi: dram: Add a helper function 'mctl_get_number_of_lanes'
It is going to be useful in more than one place.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-08-12 08:42:33 +02:00
Siarhei Siamashka
b8f7cb6ae3 sunxi: dram: Improve DQS gate data training error handling
The stale error status should be cleared for all sun4i/sun5i/sun7i
hardware and not just for sun7i. Also there are two types of DQS
gate training errors ("found no result" and "found more than one
possible result"). Both are handled now.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-08-12 08:42:33 +02:00
Siarhei Siamashka
013f2d7469 sunxi: dram: Use divisor P=1 for PLL5
This configures the PLL5P clock frequency to something in the ballpark
of 1GHz and allows more choices for MBUS and G2D clock frequency
selection (using their own divisors). In particular, it enables the use
of 2/3 clock speed ratio between MBUS and DRAM.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-08-12 08:42:33 +02:00
Siarhei Siamashka
1a9717cbb3 sunxi: dram: Configurable MBUS clock speed (use PLL5 or PLL6)
The sun5i hardware (Allwinner A13) introduced configurable MBUS clock
speed. Allwinner A13 uses only 16-bit data bus width to connect the
external DRAM, which is halved compared to the 32-bit data bus of sun4i
(Allwinner A10), so it does not make much sense to clock a wider
internal bus at a very high speed. The Allwinner A13 manual specifies
300 MHz MBUS clock speed limit and 533 MHz DRAM clock speed limit. Newer
sun7i hardware (Allwinner A20) has a full width 32-bit external memory
interface again, but still keeps the MBUS clock speed configurable.
Clocking MBUS too low inhibits memory performance and one has to find
the optimal MBUS/DRAM clock speed ratio, which may depend on many
factors:
    http://linux-sunxi.org/A10_DRAM_Controller_Performance

This patch introduces a new 'mbus_clock' parameter for the 'dram_para'
struct and uses it as a desired MBUS clock speed target. If 'mbus_clock'
is not set, 300 MHz is used by default to match the older hardcoded
settings.

PLL5P and PLL6 are both evaluated as possible clock sources. Preferring
the one, which can provide higher clock frequency that is lower or
equal to the 'mbus_clock' target. In the case of a tie, PLL5P has
higher priority.

Attempting to set the MBUS clock speed has no effect on sun4i, but does
no harm either.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-08-12 08:42:33 +02:00
Siarhei Siamashka
5c18384dea sunxi: dram: Re-introduce the impedance calibration ond ODT
The DRAM controller allows to configure impedance either by using the
calibration against an external high precision 240 ohm resistor, or
by skipping the calibration and loading pre-defined data. The DRAM
controller register guide is available here:

    http://linux-sunxi.org/A10_DRAM_Controller_Register_Guide#SDR_ZQCR0

The new code supports both of the impedance configuration modes:
   - If the higher bits of the 'zq' parameter in the 'dram_para' struct
     are zero, then the lowest 8 bits are used as the ZPROG value, where
     two divisors encoded in lower and higher 4 bits. One divisor is
     used for calibrating the termination impedance, and another is used
     for the output impedance.
   - If bits 27:8 in the 'zq' parameters are non-zero, then they are
     used as the pre-defined ZDATA value instead of performing the ZQ
     calibration.

Two lowest bits in the 'odt_en' parameter enable ODT for the DQ and DQS
lines individually. Enabling ODT for both DQ and DQS means that the
'odt_en' parameter needs to be set to 3.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-08-12 08:42:33 +02:00
Siarhei Siamashka
94cd301988 sunxi: dram: Add 'await_bits_clear'/'await_bits_set' helper functions
The old 'await_completion' function is not sufficient, because
in some cases we want to wait for bits to be cleared, and in the
other cases we want to wait for bits to be set. So split the
'await_completion' into two new 'await_bits_clear' and
'await_bits_set' functions.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-08-12 08:42:33 +02:00
Siarhei Siamashka
cfc89b003b sunxi: dram: Do DDR3 reset in the same way on sun4i/sun5i/sun7i
The older differences were likely justified by the need to mitigate
the CKE delay timing violations on sun4i/sun5i. The CKE problem is
already resolved, so now we can use the sun7i variant of this code
everywhere.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-08-12 08:42:32 +02:00
Siarhei Siamashka
7e40e1926a sunxi: dram: Remove broken impedance and ODT configuration code
We can safely remove it, because none of the currently supported
boards uses these features.

The existing implementation had multiple problems:
   - unnecessary code duplication between sun4i/sun5i/sun7i
   - ZQ calibration was never initiated explicitly, and could be
     only triggered by setting the highest bit in the 'zq' parameter
     in the 'dram_para' struct (this was never actually done for
     any of the known Allwinner devices).
   - even if the ZQ calibration could be started, no attempts were
     made to wait for its completion, or checking whether the
     default automatically initiated ZQ calibration is still
     in progress
   - ODT was only ever enabled on sun4i, but not on sun5i/sun7i

Additionally, SDR_IOCR was set to 0x00cc0000 only on sun4i. There
are some hints in the Rockchip Linux kernel sources, indicating
that these bits are related to the automatic I/O power down
feature, which is poorly understood on sunxi hardware at the
moment. Avoiding to set these bits on sun4i too does not seem to
have any measurable/visible impact.

The impedance and ODT configuration code will be re-introdeced in
one of the next comits.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-08-12 08:42:32 +02:00
Siarhei Siamashka
f8e88b6837 sunxi: dram: Fix CKE delay handling for sun4i/sun5i
Before driving the CKE pin (Clock Enable) high, the DDR3 spec requires
to wait for additional 500 us after the RESET pin is de-asserted.

The DRAM controller takes care of this delay by itself, using a
configurable counter in the SDR_IDCR register. This works in the same
way on sun4i/sun5i/sun7i hardware (even the default register value
0x00c80064 is identical). Except that the counter is ticking a bit
slower on sun7i (3 DRAM clock cycles instead of 2), resulting in
longer actual delays for the same settings.

This patch configures the SDR_IDCR register for all sun4i/sun5i/sun7i
SoC variants and not just for sun7i alone. Also an explicit udelay(500)
is added immediately after DDR3 reset for extra safety. This is a
duplicated functionality. But since we don't have perfect documentation,
it may be reasonable to play safe. Half a millisecond boot time increase
is not that significant. Boot time can be always optimized later.
Preferebly by the people, who have the hardware equipment to check the
actual signals on the RESET and CKE lines and verify all the timings.

The old code did not configure the SDR_IDCR register for sun4i/sun5i,
but performed the DDR3 reset very early for sun4i/sun5i. This resulted
in a larger time gap between the DDR3 reset and the DDR3 initialization
steps and reduced the chances of CKE delay timing violation to cause
real troubles.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-08-12 08:42:32 +02:00
Siarhei Siamashka
e626d2d446 sunxi: dram: Respect the DDR3 reset timing requirements
The RESET pin needs to be kept low for at least 200 us according
to the DDR3 spec. So just do it the right way.

This issue did not cause any visible major problems earlier, because
the DRAM RESET pin is usually already low after the board reset. And
the time gap before reaching the sunxi u-boot DRAM initialization
code appeared to be sufficient.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-08-12 08:42:32 +02:00
Siarhei Siamashka
f257796773 sunxi: dram: Remove broken super-standby remnants
If the dram->ppwrsctl (SDR_DPCR) register has the lowest bit set to 1,
this means that DRAM is currently in self-refresh mode and retaining the
old data. Since we have no idea what to do in this situation yet, just
set this register to 0 and initialize DRAM in the same way as on any
normal reboot (discarding whatever was stored there).

This part of code was apparently used by the Allwinner boot0 bootloader
to handle resume from the so-called super-standby mode. But this
particular code got somehow mangled on the way from the boot0 bootloader
to the u-boot-sunxi bootloader and has no chance of doing anything even
remotely sane. For example:
1. in the original boot0 code we had "mctl_write_w(SDR_DPCR,
   0x16510000)" (write to the register) and in the u-boot it now looks
   like "setbits_le32(&dram->ppwrsctl, 0x16510000)" (set bits in the
   register)
2. in the original boot0 code it was issuing three commands "0x12, 0x17,
   0x13" (Self-Refresh entry, Self-Refresh exit, Refresh), but in the
   u-boot they have become "0x12, 0x12, 0x13" (Self-Refresh entry,
   Self-Refresh entry, Refresh)

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-08-12 08:42:32 +02:00
Siarhei Siamashka
34759d74a3 sunxi: dram: Remove useless 'dramc_scan_dll_para()' function
The attempt to do DRAM parameters calibration in 'dramc_scan_dll_para()'
function by trying different DLL adjustments and using the hardware
DQS gate training result as a feedback is a great source of inspiration,
but it just can't work properly the way it is implemented now. The fatal
problem of this implementation is that the DQS gating window can be
successfully found for almost every DLL delay adjustment setup that
gets tried. Thus making it unable to see any real difference between
'good' and 'bad' settings.

Also this code was supposed to be only activated by setting the highest
bit in the 'dram_tpr3' variable of the 'dram_para' struct (per-board
dram configuration). But none of the linux-sunxi devices has ever used
it for real. Basically, this code is just a dead weight.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-08-12 08:42:32 +02:00
Hans de Goede
846e325448 sunxi: Add environment settings to make extlinux.conf booting work
Automatic booting using an extlinux.conf file requires various environment
variables to be set.

Also modify CONFIG_SYS_LOAD_ADDR and CONFIG_STANDALONE_LOAD_ADDR to match
the value chosen for kernel_addr_r, see the added comment for why the new
value is chosen.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
2014-08-12 08:42:32 +02:00
Hans de Goede
2ec3a612f4 sunxi-common.h: Use new generic $bootcmd
Use the new standard bootcmd from <config_distro_bootcmd.h>.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
2014-08-12 08:42:32 +02:00
Dennis Gilmore
8cc96848f0 config: introduce a generic $bootcmd
This generic $bootcmd, and associated support macros, automatically
searches a defined set of storage devices (or network protocols) for an
extlinux configuration file or U-Boot boot script in various standardized
locations. Distros that install such a boot config file/script in those
standard locations will get easy-to-set-up booting on HW that enables
this generic $bootcmd.

Boards can define the set of devices from which boot is attempted, and
the order in which they are attempted. Users may later customize this
set/order by edting $boot_targets.

Users may interrupt the boot process and boot from a specific device
simply by executing e.g.:

$ run bootcmd_mmc1
or:
$ run bootcmd_pxe

This patch was originally written by Dennis Gilmore based on Tegra and
rpi_b boot scripts. I have made the following modifications since then:

* Boards must define the BOOT_TARGET_DEVICES macro in order to specify
  the set of devices (and order) from which to attempt boot. If needed,
  we can define a default directly in config_distro_bootcmd.h.

* Removed $env_import and related variables; nothing used them, and I
  think it's better for boards to pre-load an environment customization
  file using CONFIG_PREBOOT if they need.

* Renamed a bunch of variables to suit my whims:-)

Signed-off-by: Dennis Gilmore <dennis@ausil.us>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Acked-by: Simon Glass <sjg@chromium.org>
2014-08-12 08:42:31 +02:00
Hans de Goede
6ae66f2e89 sunxi: Kconfig: move common settings into a shared code block
SYS_CPU, SYS_BOARD and SYS_SOC are identical for all sunxi boards, move
them to a shared code block.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-08-12 08:40:12 +02:00
Hans de Goede
b9fb3b94cb sunxi-common.h: Don't undef CONFIG_CMD_NET only to redefine it again later
config_distro_defaults.h which is include later will redefine CONFIG_CMD_NET,
drop the useless / meaningless undef of it.

While at also move the undef of CONFIG_CMD_FPGA up to directly under the
include of config_cmd_defaults.h, to make it clear that it overwrites
the setting done from config_cmd_defaults.h .

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-08-12 08:40:12 +02:00
Hans de Goede
85a4455c51 sunxi-common.h: Don't undefine CONFIG_CMD_NFS
I see no reason to override the choice to include this from
config_cmd_defauls.h .

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-08-12 08:40:12 +02:00
Hans de Goede
ad0fd965f7 sunxi-common.h: Remove dead #ifdef CONFIG_CMD_NET code block
We undef CONFIG_CMD_NET at line 167, and there is nothing re-defining it
between line 167 and the #ifdef CONFIG_CMD_NET, so remove this effectively
dead block.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-08-12 08:40:12 +02:00
Hans de Goede
c17b07d4dc sunxi-common.h: Remove CONFIG_SYS_BOOT_GET_CMDLINE
sunxi does not need this and it should never have been enabled for it in
the first place.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-08-12 08:40:12 +02:00
Hannes Petermaier
a305fb155e lcd: support displaying 24bpp BMPs on >= 24bpp LCDs
most todays LCDs support 32bpp e.g. the framebuffer memory is 32bpp
organized.

To support 24bpp BMPs we need to take only 3 byte from the bpp and set
one byte from the FB to 0.

Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
2014-08-11 18:07:09 +02:00
Jeroen Hofstee
072f210a0d lcd: remove unused lcd_puts_xy
prevents a clang warning that the function is
never used.

cc: agust@denx.de
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-08-11 17:56:45 +02:00
Jeroen Hofstee
e6e9cff2dc video: ipu_disp: squash clang warning
Since rgb2ycbcr_coeff and friends are declared const, but assigned
to a void pointer, clang will warn that the const is implicity casted
away. If the pointer is changed to void const * gcc will warn when it
is implicitly casted to a const int array. Just add a correctly
typed pointer instead to prevent these casts and hence the warnings.

Cc: Troy Kisky <troy.kisky@boundarydevices.com>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-08-11 17:52:21 +02:00
Liu Ying
e66866c542 video: ipu_disp: wait for DP SF end irq when disabling sync BG flows
Instead of waiting for DC triple buffer to be cleared, this patch
changes to wait for a relevant DP sync flow end interrupt to come
when disabling sync BG flows.  In this way, we align the implement
to the freescale internal IPUv3 driver.  After applying this patch,
an uboot hang up issue at the arch_preboot_os() stage, where we
disable a relevant ipu display channel, is not observed any more on
some MX6DL platforms.

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
2014-08-11 17:31:41 +02:00
Stefano Babic
e82abaeb7f Merge branch 'master' of git://git.denx.de/u-boot-arm
Conflicts:
	boards.cfg

Signed-off-by: Stefano Babic <sbabic@denx.de>
2014-08-11 10:21:03 +02:00
Hannes Petermaier
3c5fabd139 video: Add support for TI's AM335x LCD-Controller
- Adds support for a minimal framebuffer driver of TI's AM335x SoC
  to be compatible with Wolfgang Denk's LCD-Framework (CONFIG_LCD,
  common/lcd.c)

Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
2014-08-10 15:34:27 +02:00
Hannes Petermaier
8d9eaafdd1 lcd: cleanup unused functions
This patch removes following two functions:
- lcd_getbgcolor(...)
  not used somewhere outside lcd.c, internally we use now the global
  variable lcd_color_bg (was return value of function before)
- lcd_getfgcolor(...)
  not used in any place of u-boot

Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
[agust: rebased]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
2014-08-10 15:25:19 +02:00
Hannes Petermaier
57d76a89b0 Add support for 32-bit organized framebuffers
- Adds support for 32-bit organized framebuffers to the LCD-framework.

Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
Cc: agust@denx.de
2014-08-10 14:55:19 +02:00
Tom Rini
6d1966e123 env_fat.c: Make sure our buffer is cache aligned
We must ensure the buffer we read the env into is aligned or we may get
warnings later on.

Signed-off-by: Tom Rini <trini@ti.com>
2014-08-09 11:26:34 -04:00
Bryan Wu
b3dd64f5d5 bootm: use genimg_get_kernel_addr()
Use the new API which is originally taken out from boot_get_kernel
of bootm.c

Signed-off-by: Bryan Wu <pengw@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
[trini: Fix warnings with CONFIG_FIT]
Signed-off-by: Tom Rini <trini@ti.com>
2014-08-09 11:26:15 -04:00
Bryan Wu
1fb7d0e619 pxe: detect image format before calling bootm/bootz
Trying bootm for zImage will print out several error message which
is not necessary for this case. So detect image format firstly, only
try bootm for legacy and FIT format image then try bootz for others.

This patch needs new function genimg_get_kernel_addr().

Signed-off-by: Bryan Wu <pengw@nvidia.com>
2014-08-09 11:19:01 -04:00
Bryan Wu
0f64140b69 image: introduce genimg_get_kernel_addr()
Kernel address is normally stored as a string argument of bootm or bootz.
This function is taken out from boot_get_kernel() of bootm.c, which can be
reused by others.

Signed-off-by: Bryan Wu <pengw@nvidia.com>
[trini: Fix warnings with CONFIG_FIT]
Signed-off-by: Tom Rini <trini@ti.com>
2014-08-09 11:18:47 -04:00
Daniel Schwierzeck
68dc8769e3 get_maintainer.pl: add support for scanning multiple MAINTAINERS files
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2014-08-09 11:17:05 -04:00
Daniel Schwierzeck
ee360cd26a get_maintainer.pl: adapt to U-Boot tree
Switch core maintainer to Tom Rini. Adapt directory layout for
git tree detection.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2014-08-09 11:17:05 -04:00
Daniel Schwierzeck
92bca3981d get_maintainer.pl: import script from linux 3.15
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-08-09 11:17:05 -04:00
Daniel Schwierzeck
00f141ccb3 MAINTAINERS: add initial version
MAINTAINERS contains all currently known custodians based on
infos from wiki [1] and u-boot git forks [2].

[1] http://www.denx.de/wiki/U-Boot/Custodians
[2] http://git.denx.de/?p=u-boot.git;a=forks

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2014-08-09 11:17:05 -04:00
Stephen Warren
ad3fda521b lib: lmb: fix overflow in __lmb_alloc_base w/ large RAM
If a 32-bit system has 2GB of RAM, and the base address of that RAM is
2GB, then start+size will overflow a 32-bit value (to a value of 0).

__lmb_alloc_base is affected by this; it calculates the minimum of
(start+size of RAM) and max_addr. However, when start+size is 0, it
is always less than max_addr, which causes the value of max_addr not
to be taken into account when restricting the allocation's location.

Fix this by calculating start+size separately, and if that calculation
underflows, using -1 (interpreted as the max unsigned value) as the
value instead, and then taking the min of that and max_addr. Now that
start+size doesn't overflow, it's typically large, and max_addr
dominates the min() call, and is taken into account.

The user-visible symptom of this bug is that CONFIG_BOOTMAP_SZ is ignored
on Tegra124 systems with 2GB of RAM, which in turn causes the DT to be
relocated at the very end of RAM, which the ARM Linux kernel doesn't map
during early boot, and which causes boot failures. With this fix,
CONFIG_BOOTMAP_SZ correctly restricts the relocated DT to a much lower
address, and everything works.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-08-09 11:17:05 -04:00
Stephen Warren
ed1127e42a ARM: rpi_b: use new generic $bootcmd
Replace the custom $bootcmd with that from <config_distro_bootcmd.h>.
There should be no functional change, since the new generic $bootcmd was
derived strongly from tegra-common-post.h, after which this part of
rpi_b.h was modelled.

The #defines to enable/disable U-Boot commands/features were moved
earlier in rpi_b.h, so they are set up before config_distro_bootcmd.h
is included, since it tests whether certain features should be included
based on those defines.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-08-09 11:17:04 -04:00
Stephen Warren
8dca9ff476 ARM: tegra: use new generic $bootcmd
Replace the custom $bootcmd with that from <config_distro_bootcmd.h>.
There should be no functional change, since the new generic $bootcmd was
derived strongly from tegra-common-post.h.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-08-09 11:17:04 -04:00
Dennis Gilmore
2a43201a13 config: introduce a generic $bootcmd
This generic $bootcmd, and associated support macros, automatically
searches a defined set of storage devices (or network protocols) for an
extlinux configuration file or U-Boot boot script in various standardized
locations. Distros that install such a boot config file/script in those
standard locations will get easy-to-set-up booting on HW that enables
this generic $bootcmd.

Boards can define the set of devices from which boot is attempted, and
the order in which they are attempted. Users may later customize this
set/order by edting $boot_targets.

Users may interrupt the boot process and boot from a specific device
simply by executing e.g.:

$ run bootcmd_mmc1
or:
$ run bootcmd_pxe

This patch was originally written by Dennis Gilmore based on Tegra and
rpi_b boot scripts. I have made the following modifications since then:

* Boards must define the BOOT_TARGET_DEVICES macro in order to specify
  the set of devices (and order) from which to attempt boot. If needed,
  we can define a default directly in config_distro_bootcmd.h.

* Removed $env_import and related variables; nothing used them, and I
  think it's better for boards to pre-load an environment customization
  file using CONFIG_PREBOOT if they need.

* Renamed a bunch of variables to suit my whims:-)

Signed-off-by: Dennis Gilmore <dennis@ausil.us>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Acked-by: Simon Glass <sjg@chromium.org>
2014-08-09 11:17:04 -04:00
Simon Glass
5426716231 rsa: Fix two errors in the implementation
1. Failure to set the return code correctly
2. Failure to detect the loop end condition when the value is equal to
the modulus.

Reported-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Signed-off-by: Simon Glass <sjg@chromium.org>
2014-08-09 11:17:04 -04:00
Masahiro Yamada
8ac22a60e2 omap: clean-up dead configs
The following configs are not defined at all.

 - CONFIG_OMAP1510
 - CONFIG_OMAP_1510P1
 - CONFIG_OMAP_SX1
 - CONFIG_OMAP3_DMA
 - CONFIG_OMAP3_ZOOM2
 - CONFIG_OMAP_INNOVATOR

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
2014-08-09 11:17:04 -04:00
Simon Glass
0596d35d80 fdt: Sync up with libfdt
This brings in changes up to commit f9e91a48 in the libfdt repo.
Mostly this is whitespace/minor changes. But there are a few new
features:

- fdt_size_cells() and fdt_address_cells()
- fdt_resize()

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-08-09 11:17:04 -04:00
Simon Glass
5bf58ccc8e fdt: Rename fdt_resize() to fdt_shrink_to_minimum()
Since libfdt now has an fdt_resize() function, we need to rename the
U-Boot one.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-08-09 11:17:03 -04:00
Masahiro Yamada
0b6cc51e98 cosmetic: update doc/README.scrapyard
- Add 'p1023rds' to the list since commit d0bc5140 dropped
   the board support but missed to update this file
 - Fill the Commit and Removed Date fields for boards removed
   by earlier commits
 - Move 'incaip' to keep the list sorted in reverse
   chronological order
 - Describe the soring rule in the comment block:
   "The list should be sorted in reverse chronological order."
 - Fix typos in the comment block

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-09 11:17:03 -04:00
Pavel Machek
2a72dcce24 ext4load: fix help text
Fix ext4load help text.

Signed-off-by: Pavel Machek <pavel@denx.de>
2014-08-09 11:17:03 -04:00
Simon Glass
960c3cac7f git-mailrc: Add myself as dm maintainer
Add a subsystem entry for dm with myself as maintainer.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-08-09 11:17:03 -04:00
Simon Glass
fd5058ee90 git-mailrc: Change fdt maintainer
Add myself as fdt maintainer.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-08-09 11:17:03 -04:00
Stephen Warren
f59be6e850 net: BOOTP retry timeout improvements
Currently, the BOOTP code sends out its initial request as soon as the
Ethernet driver indicates "link up". If this packet is lost or not
replied to for some reason, the code waits for a 1s timeout before
retrying. For some reason, such early packets are often lost on my
system, so this causes an annoying delay.

To optimize this, modify the BOOTP code to have very short timeouts for
the first packet transmitted, but gradually increase the timeout each
time a timeout occurs. This way, if the first packet is lost, the second
packet is transmitted quite quickly and hence the overall delay is low.
However, if there's still no response, we don't keep spewing out packets
at an insane speed.

It's arguably more correct to try and find out why the first packet is
lost. However, it seems to disappear inside my Ethenet chip; the TX chip
indicates no error during TX (not that it has much in the way of
reporting...), yet wireshark on the RX side doesn't see any packet.
FWIW, I'm using an ASIX USB Ethernet adapter. Perhaps "link up" is
reported too early or based on the wrong condition in HW, and we should
add some fixed extra delay into the driver. However, this would slow down
every link up event even if it ends up not being needed in some cases.
Having BOOTP retry quickly applies the fix/WAR to every possible
Ethernet device, and is quite simple to implement, so seems a better
solution.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2014-08-09 11:17:03 -04:00
maxin.john@enea.com
194c1ed400 emif.h: remove duplicated argument to |
Remove the duplicated argument to | in two places. Reported
by Coccinelle (http://coccinelle.lip6.fr/).

Signed-off-by: Maxin B. John <maxin.john@enea.com>
2014-08-09 11:17:03 -04:00
maxin.john@enea.com
79e86ccb37 vitesse: remove duplicated argument to ||
Remove the duplicated argument to || check

Signed-off-by: Maxin B. John <maxin.john@enea.com>
2014-08-09 11:17:02 -04:00
Ian Campbell
19ad527d8c board_r: Add missing return to initr_doc
I happened to spot this while working in the area.

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Simon Glass <sjg@chromium.org>
Cc: Simon Glass <sjg@chromium.org>
2014-08-09 11:17:02 -04:00
Chris Packham
3ce7a4fefa Makefile: use u-boot.map for binary_size_check
u-boot.map is generated automatically by the compiler and more
importantly can handle addresses >4GB.
2014-08-09 11:17:02 -04:00
Chris Packham
67b060b46b Makefile: use $(shell ...) for determining file_size
file_size was being calculated using back-ticks but map_size uses
$(shell ...). Update the file_size calculation to use $(shell ...).

From: Jeroen Hofstee <jeroen@myspectrum.nl>

The binary_size_check target relies on stat -c %s
to return the size of u-boot.bin. This only works
with GNU stat though. Use wc instead.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-08-09 11:17:02 -04:00
Stephen Warren
ded2e20ef2 pxe: clear Bootfile before returning
When "pxe boot" downloads the initrd/kernel/DTB, netboot_common() saves
the downloaded filename to global variable BootFile. If the boot
operation is aborted, this global state is not cleared. If "dhcp" is
executed later without any arguments, BootFile is not cleared, and when
the DHCP response is received, BootpCopyNetParams() writes the value into
environment variable bootfile.

This causes the following scenario:

* Boot script executes dhcp; pxe get; pxe boot

* User CTRL-C's the PXE menu, which causes the first menu item to be
  booted, which causes some file to be downloaded.

  (This boot-on-CTRL-C behaviour is arguably a bug too, but it's a
  separate bug and the bug this patch fixes would still exist if the user
  simply waited to press CTRL-C until "pxe boot" started downloading
  files)

* User CTRL-C's the file downloads, but the filename is still written to
  the bootfile environment variable.

* User re-runs the boot command, which in my case executes "dhcp; pxe get;
  pxe boot" again, and "dhcp" picks up the saved bootfile environment
  variable and proceeds to download a file that it shouldn't.

To solve this, modify the implementation of "pxe get" to clear BootFile
if the whole boot operation fails, which avoids this whole mess.

An alternative would be to modify netboot_common() such that the no-
arguments case explicitly clears the global variable BootFile. However,
that would prevent the following command sequences from working:

$ dhcp filename # downloads "filename"
$ dhcp          # downloads $bootfile, i.e. "filename"

or:
$ setenv bootfile filename
$ dhcp          # downloads $bootfile, i.e. "filename"

... and I assume someone relies on U-Boot working that way.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2014-08-09 11:17:02 -04:00
Barnes, Clifton A
183cbff706 doc: README.android-fastboot: Add note about vendor ID
The Android fastboot client only communicates with specific vendor IDs.
This addition to the documentation points out that fact so everyone is
aware that not just any vendor ID will work and where to find the IDs
that will.

Signed-off-by: Clifton Barnes <cabarnes@indesign-llc.com>
Cc: Rob Herring <robh@kernel.org>
2014-08-09 11:17:02 -04:00
Łukasz Majewski
dcb7eb66e4 ext4: trats: trats2: Modify dfu_alt_info's file names to have absolute path
After the clean up performed in the commit 1151b7ac10b81ecbb the DFU subsystem
requires absolute patch for correct operation.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
2014-08-09 11:17:02 -04:00
Michael van der Westhuizen
e0f2f15534 Implement generalised RSA public exponents for verified boot
Remove the verified boot limitation that only allows a single
RSA public exponent of 65537 (F4).  This change allows use with
existing PKI infrastructure and has been tested with HSM-based
PKI.

Change the configuration OF tree format to store the RSA public
exponent as a 64 bit integer and implement backward compatibility
for verified boot configuration trees without this extra field.

Parameterise vboot_test.sh to test different public exponents.

Mathematics and other hard work by Andrew Bott.

Tested with the following public exponents: 3, 5, 17, 257, 39981,
50457, 65537 and 4294967297.

Signed-off-by: Andrew Bott <Andrew.Bott@ipaccess.com>
Signed-off-by: Andrew Wishart <Andrew.Wishart@ipaccess.com>
Signed-off-by: Neil Piercy <Neil.Piercy@ipaccess.com>
Signed-off-by: Michael van der Westhuizen <michael@smart-africa.com>
Cc: Simon Glass <sjg@chromium.org>
2014-08-09 11:17:01 -04:00
Nobuhiro Iwamatsu
53022c3113 serial: sh: Add support External Clock mode
R8A7780 and R7A7791 of rmobile supports External Clock mode, and these uses
different from Internal Clock mode registers and calculations to the baud rate
setting. This adds function for External Clock mode.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2014-08-09 11:17:01 -04:00
Nobuhiro Iwamatsu
1a223c9324 serial: sh: Add support DL and CKS register for R8A7794
R8A7794 has DL and CKS register, and these registers are used in external clock
mode. This adds support these for R8A7794.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2014-08-09 11:17:01 -04:00
Nobuhiro Iwamatsu
5906fadefa usb: ehci: rmobile: Remove xHCI address
echi-rmobile does not support xHCI. This removes xHCI address
from address table. And this revise a value of CONFIG_USB_MAX_CONTROLLER_COUNT
for lager board and koelsh board.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-08-09 11:17:01 -04:00
Nobuhiro Iwamatsu
ed7ce836cd usb: ehci: rmobile: Add support R8A7794
R8A7794 has same IP of USB controller as R8A7790 and R8A7791.
This addes support for R8A7794.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-08-09 11:17:01 -04:00
Stephen Warren
67ab0a5e9f dfu: fix readback buffer overflow test
The buffer is too small if it's < size to read, not if it's <= the size.
This fixes the 1MB test case on Tegra, which has a 1MB buffer.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-08-09 11:17:01 -04:00
Stephen Warren
54ce79c8a5 test: dfu: add some more test cases
On Tegra, the DFU buffer size is 1M. Consequently, the 8M test always
fails. Add tests for the 1M size, and one byte less as a corner case,
so that some large tests are executed and expected to pass.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-08-09 11:17:00 -04:00
Stephen Warren
c0e6663b0a test: dfu: cleanup before execution
Call cleanup() before running tests too. If a previous test was CTRL-C'd
some stale files may have been left around. dfu-util refuses to receive
a file to a filename that already exists, which results in false test
failures if the files aren't cleaned up first.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-08-09 11:17:00 -04:00
Lukasz Majewski
90fadb5723 thor: defer parsing of device string to IO backend
Commit d4f5ef59cc7 "dfu: defer parsing of device string to IO backend" changed
the function signature of dfu_init_env_entities(). Adjust cmd_thordown.c
to match that change.

Also, apply the same change as commit d6d37d737b58e "dfu: free entities
when parsing fails" to cmd_thordown.c.

Fixes: d4f5ef59cc7 ("dfu: defer parsing of device string to IO backend")
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2014-08-09 11:17:00 -04:00
Lukasz Majewski
50a3532128 test:dfu: README file update
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
2014-08-09 11:17:00 -04:00
Stephen Warren
7ad67e5554 test: dfu: script enhancements
Various misc enhancements to dfu_gadget_test.sh:

* After every write (download), perform a write to a different file
  with different data. This ensures that the DFU buffer's content is
  replaced, so that if the read (upload) succeeds, we know that the
  correct data was actually read from the storage device, rather than
  simply being left over in the DFU buffer. This requires two alt
  setting names to be passed to the script, and a dummy data file to
  be generated by dfu_gadget_test_init.sh.

* Fix the assumption that dfu_gadget_test.sh is run from the directory
  that contains it, by cd'ing to that directory before invoking
  ./dfu_gadget_test_init.sh.

* Use $DIR$RCV_DIR consistently, rather than using plain $RCV_DIR in
  some places.

* Add 959, 961 test file sizes, to be consistent with having one
  more than and one less than all the other "round" sizes 64, 128, and
  4096.

* Remove references to $BKP_DIR from dfu_gadget_test_init.sh, since it
  isn't used.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-08-09 11:16:59 -04:00
Lukasz Majewski
a4c86bbb5a test:dfu: Add test scripts for testing DFU regression
This commit adds test scripts for testing if any commit has introduced
regression to the DFU subsystem.

It uses md5 to test if sent and received file is correct.
The test detailed description is available at README file.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
2014-08-09 11:16:59 -04:00
Stephen Warren
6f12ebf6ea dfu: add SF backend
This allows SPI Flash to be programmed using DFU.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-08-09 11:16:59 -04:00
Stephen Warren
cb7bd2e07e dfu: add free_entity() to struct dfu_entity
This allows the backend to free any resources allocated during the
relevant dfu_fill_entity_*() call. This will soon be used by the
SF backend.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-08-09 11:16:59 -04:00
Stephen Warren
7ac1b410ac dfu: allow backend to specify a maximum buffer size
CONFIG_SYS_DFU_DATA_BUF_SIZE may be large to allow for FAT/ext layouts
to transfer large files. However, this means that individual write
operations will take a long time. Allow backends to specify a maximum
buffer size, so that each write operation is limited to a smaller data
block. This prevents the DFU protocol from timing out when e.g. writing
to SPI flash. I would guess that NAND might benefit from setting this
value too, but I can't test that.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-08-09 11:16:58 -04:00
Stephen Warren
dd64827eb6 dfu: defer parsing of device string to IO backend
Devices are not all identified by a single integer. To support
this, defer the parsing of the device string to the IO backed, so that
it can apply the appropriate rules.

SPI devices are specified as controller:chip_select. SPI/SF support will
be added soon.

MMC devices can also be specified as controller[.hwpart][:partition] in
many commands, although we don't support that syntax in DFU.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-08-09 11:16:58 -04:00
Stephen Warren
3ee9593fce dfu: add write error handling
Fix calls to dfu_write() and dfu_flush() to detect errors in the I/O
itself. This could happen due to problems with the storage medium, or
simply when trying to write a FAT/ext file that is larger than the buffer
dfu_mmc.c maintains for this purpose.

Signal the error by switching the DFU state/status. This will be picked
up by the DFU client when it sends the next DFU request. Note that errors
can't simply be returned from e.g. dnload_request_complete(), since that
function has no way to pass errors back to the DFU client; a call to
dnload_request_complete() simply means that a USB OUT completed.

This error state/status needs to be cleared when the next DFU client
connects. While there is a DFU_CLRSTATUS request, no DFU client seems to
send this. Hence, clear this when selecting the USB alternate setting on
the USB interface.

Finally, dfu.c relies on a call to dfu_flush() to clear up the internal
state of the write transaction. Now that errors in dfu_write() are
detected, dfu_flush() may no longer be called for every transaction.
Separate out the cleanup code into a new function, and call it whenever
dfu_write() fails, as well as from any call to dfu_flush().

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-08-09 11:16:58 -04:00
Stephen Warren
0e285b503c dfu: fix some issues with reads/uploads
DFU read support appears to rely upon dfu->read_medium() updating the
passed-by-reference len parameter to indicate the remaining size
available for reading.

dfu_read_medium_mmc() never does this, and the implementation of
dfu_read_medium_nand() will only work if called just once; it hard-codes
the value to the total size of the NAND device irrespective of read
offset.

I believe that overloading dfu->read_medium() is confusing. As such,
this patch introduces a new function dfu->get_medium_size() which can
be used to explicitly find out the medium size, and nothing else.
dfu_read() is modified to use this function to set the initial value for
dfu->r_left, rather than attempting to use the side-effects of
dfu->read_medium() for this purpose.

Due to this change, dfu_read() must initially set dfu->b_left to 0, since
no data has been read.

dfu_read_buffer_fill() must also be modified not to adjust dfu->r_left
when simply copying data from dfu->i_buf_start to the upload request
buffer. r_left represents the amount of data left to be read from HW.
That value is not affected by the memcpy(), but only by calls to
dfu->read_medium().

After this change, I can read from either a 4MB or 1.5MB chunk of a 4MB
eMMC boot partion with CONFIG_SYS_DFU_DATA_BUF_SIZE==1MB. Without this
change, attempting to do that would result in DFU read returning no data
at all due to r_left never being set.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-08-09 11:16:58 -04:00
Stephen Warren
cf6598193a fs: implement size/fatsize/ext4size
These commands may be used to determine the size of a file without
actually reading the whole file content into memory. This may be used
to determine if the file will fit into the memory buffer that will
contain it. In particular, the DFU code will use it for this purpose
in the next commit.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-08-09 11:16:57 -04:00
Albert ARIBAUD
1899fac925 Merge branch 'u-boot-sunxi/master' into 'u-boot-arm/master' 2014-08-09 16:48:34 +02:00
Peter Crosthwaite
fb8d876698 zynq: spl: Add vectors section to linker script
The vectors section contains the _start symbol which is used as the
program entry point. Add it to the linker script in same fashion as done
for regular u-boot. This allows for correct generation of an spl elf
with a non-zero entry point.

A similar change was applied to sunxi platform in
"sunxi: Fix u-boot-spl.lds to refer to .vectors"
(sha1: 9e5f80d823)

This also allows for placement of the vector table at the hivecs
location by setting the TEXT_BASE to 0xffff0000.

Tested-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-08-08 11:27:29 +02:00
Magnus Lilja
f93f21906e i.MX31 PDK: Enable generic board for i.MX31 PDK
Enable CONFIG_SYS_GENERIC_BOARD for the i.MX31 PDK board.

Tested on actual hardware.

Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-08-08 10:29:41 +02:00
Fabio Estevam
676ac24e07 pmic: pmic_pfuze100: Use a shorter name for PMIC name
It is redundant to use 'PFUZE100_PMIC' as the PMIC name because we already
know it is a PMIC.

Call it simply 'PFUZE100' instead.

Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Markus Niebel <Markus.Niebel@tq-group.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-08-08 10:29:41 +02:00
Fabio Estevam
9cd744ff11 mx6: crm_regs: Fix MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED
According to the Reference Manual the 'mask_periph2_clk_sel_loaded' field of
register CCM_CIMR corresponds to bit 19 so fix its definition accordingly.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-08-08 10:29:40 +02:00
Fabio Estevam
326454a88d mx6: crm_regs: Fix MXC_CCM_CLPCR_WB_PER_AT_LPM definition
According to the Reference Manual the 'wb_per_at_lpm' field of register
CCM_CLPCR corresponds to bit 16 so fix its definition accordingly.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-08-08 10:29:40 +02:00
Fabio Estevam
338c9da605 mx6: crm_regs: Fix CDCDR_SPDIF0_CLK_PODF mask and offset
According to the Reference Manual the 'spdif0_clk_podf' field of register
CCM_CDCDR corresponds to bits 22, 23 and 24, so fix the mask and offset
definitions accordingly.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-08-08 10:29:40 +02:00
Fabio Estevam
2834490245 mx6: imx-regs: Remove unused 'omux' field from iomux struct
'omux' field is not used anywhere and such layout is not valid for mx6solox.

Instead of adding more ifdef's into the structure, let's simply remove this
unused 'omux' field.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2014-08-08 10:29:39 +02:00
Marek Vasut
25fe05722a arm: m53evk: Fix RTC bus number
A previous update to the I2C stack introduced a typo in the
configuration option. Fix the typo and therefore allow the
RTC to work correctly with the 'date' command again.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2014-08-08 10:29:38 +02:00
Stefano Babic
c23154aab5 Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-08-08 10:18:40 +02:00
Sonic Zhang
d54d7eb965 support blackfin board initialization in generic board_f
- init hardware watchdog if applicable
- use CONFIG_SYS_MONITOR_LEN as the gd monitor len for Blackfin
- reserve u-boot memory at the top field of the RAM for Blackfin
- avoid refer to CONFIG_SYS_MONITOR_LEN, which is not defined by Blackfin

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
2014-08-07 15:15:19 +08:00
Sonic Zhang
c49eabeffc blackfin: convert blackfin board_f and board_r to use generic board init functions
- move blackfin specific cpu init code from blackfin board.c to cpu.c
- remove blackfin specific board init code and invoke generic board_f fron cpu init entry
- rename section name bss_vma to bss_start in order to match the generic board init code
- add a fake relocate_code function to set up the new stack only

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
2014-08-07 15:15:14 +08:00
Scott Jiang
9f9a65c80a blackfin: spi clock is in sysclk1 domain instead of sysclk0
Signed-off-by: Scott Jiang <scott.jiang.linux@gmail.com>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
2014-08-07 15:15:09 +08:00
Aaron Wu
08b6a61162 bfin: add register define required by core B on dual core BF609 processor
Add register define required by core B on dual core BF609 processor.

Signed-off-by: Aaron Wu <Aaron.wu@analog.com>
2014-08-07 15:15:08 +08:00
Tom Rini
e76b933e02 Prepare v2014.10-rc1
Signed-off-by: Tom Rini <trini@ti.com>
2014-08-06 09:12:58 -04:00
Andy Fleming
b21f87a3e0 Change Andy Fleming's email address
Messages to afleming@freescale.com now bounce, and should be
directed to my personal address at afleming@gmail.com

Signed-off-by: Andy Fleming <afleming@gmail.com>
2014-08-06 09:12:30 -04:00
Holger Freyther
ab584d67c5 The _config target is not present anymore, mention _defconfig instead
The _config part is gone for sure, the _defconfig target could at least
work. I have not verified this for all targets though.
2014-08-06 09:02:46 -04:00
Stephen Warren
bfca6e0809 git-mailrc: add a kconfig alias
It's easier to Cc Masahiro on Kconfig-related changes with a git-mailrc
alias.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-06 09:02:46 -04:00
Masahiro Yamada
c01f87c8dd doc: README.SPL: adjust for Kbuild and Kconfig
Reflect the latest build system to doc/README.SPL.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-06 09:02:46 -04:00
Masahiro Yamada
e8e6d2a990 doc: delete README.ARM-SoC
This document is too old and useless.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-06 09:02:46 -04:00
Tom Rini
336450f5fc Merge branch 'master' of git://git.denx.de/u-boot-spi 2014-08-06 08:38:19 -04:00
Tom Rini
dcdb61a084 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2014-08-06 08:38:18 -04:00
Heiko Schocher
f659b57361 spi, spi_mxc: do not hang in spi_xchg_single
if status register do never set MXC_CSPICTRL_TC, spi_xchg_single
endless loops. Add a timeout here to prevent endless hang.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Dirk Behme <dirk.behme@gmail.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-08-06 00:18:01 +05:30
Simon Glass
22052c6236 spi: Support half-duplex mode in FDT decode
This parameter should also be supported.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-08-06 00:18:01 +05:30
Simon Glass
a4e29db257 exynos: spi: Fix calculation of SPI transaction start time
The SPI transaction delay is supposed to be measured from the end of one
transaction to the start of the next. The code does not work that way, so
fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-08-06 00:18:01 +05:30
Simon Glass
2001b9a641 cros_ec: Fix two bugs in the SPI implementation
An incorrect message version is passed to the EC in some cases and the
parameters of one function are switched.

Fix these problems.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-08-06 00:18:01 +05:30
Marek Vasut
a52a178f0b sf: sf_ops: Stop leaking memory
It's usually a common pattern to free() the memory that we allocated.
Implement this here to stop leaking memory.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-08-06 00:18:01 +05:30
Tom Rini
aa159e681e Merge http://git.denx.de/u-boot-dm 2014-08-04 10:16:27 -04:00
Simon Glass
76a1e584e1 arm: Support pre-relocation malloc()
Add support for re-relocation malloc() in arm's start-up code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-08-04 05:24:35 -06:00
Simon Glass
aae2aef9c8 arm: Set up global data before board_init_f()
At present arm defines CONFIG_SYS_GENERIC_GLOBAL_DATA, meaning that
the global_data pointer is set up in board_init_f(). However it is
actually set up before this, it just isn't zeroed.

If we zero the global data before calling board_init_f() then we
don't need to define CONFIG_SYS_GENERIC_GLOBAL_DATA.

Make this change (on arm32 only) to simplify the init process. I
don't have the ability to test aarch64 yet.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Tom Rini <trini@ti.com>
2014-08-04 05:23:59 -06:00
Boschung, Rainer
e3917b21c0 kmp204x: prepare to use CPU watchdog
This patch configures the qrio to trigger a core reset on
a CPU reset request.

Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-08-01 14:18:59 -07:00
Boschung, Rainer
6caa185abd kmp204x/qrio: support for setting the CPU reset request mode
To acheive this, the qrio_uprstreq() function that sets the UPRSTREQN
flag in the qrio RESCNF reg is added.

Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-08-01 14:18:53 -07:00
Boschung, Rainer
a09f470d49 kmp204x: set CPU watchdog reset reason flag
Check the core timer status register (TSR) for watchdog reset,
and and set the QRIO's reset reason flag REASON1[0] accordingly.

This allows the appliction SW to identify the cpu watchdog as a
reset reason, by setting the REASON1[0] flag in the QRIO.

Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-08-01 14:18:46 -07:00
Boschung, Rainer
807d93d6de kmp204x/qrio: prepare support for the CPU watchdog reset reason
To achieve this, the qrio_cpuwd_flag() function that sets the CPU watchdog
flag in the REASON1 reg is added.

Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-08-01 14:18:40 -07:00
Boschung, Rainer
88ac6ffabb kmp204x: CPU watchdog enabled
The booting of the board is now protected by the CPU watchdog.
A failure during the boot phase will end up in board reset.

Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-08-01 14:18:34 -07:00
Boschung, Rainer
919e05520f powerpc: mpc85xx watchdog init added to init_func
When CONFIG_WATCHDOG is defined the board initialization just performs
a WATCHDOG_RESET, an initialization of the watchdog is not done.
This has been modified fot the MPC85xx, the board initialization calls
its watchdog initialitzation allowing for full watchdog configuration
very early in the boot phase.

Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-08-01 14:18:28 -07:00
Boschung, Rainer
0f8062b25b mpc85xx: watchdog initialisation added
Function to inititialize the cpu watchdog added.

Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com>
[York Sun: Add prototype in watchdog.h]
Reviewed-by: York Sun <yorksun@freescale.com>
2014-08-01 14:18:17 -07:00
Boschung, Rainer
60b295672d powerpc: macros for e500mc timer regs added
For e500mc cores the watchdog timer period has to be set by means of a
6bit value, that defines the bit of the timebase counter used to signal
a watchdog timer exception on its 0 to 1 transition.
The macro used to set the watchdog period TCR_WP, was redefined for e500mc
to support 6 WP setting.

The parameter (x) given to the macro specifies the prescaling factor of
the time base clock (fTB):

watchdog_period = 1/fTB * 2^x

Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-08-01 14:18:07 -07:00
Boschung, Rainer
3345d18d5b mpc85xx: fix interrupt init to not affect watchdog
TCR watchdog bit are overwritten when dec interrupt is enabled.
This has been fixed with this patch.

Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-08-01 14:17:44 -07:00
Dmitry Lifshitz
6e7b7df4df env_mmc: support env partition setup in runtime
Add callback with __weak annotation to allow setup of environment
partition number in runtime from a board file.

Propagate mmc_switch_part() return value into init_mmc_for_env() instead
of -1 in case of failure.

Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il>
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-08-01 20:12:15 +03:00
Dmitry Lifshitz
ac77f42d09 env_mmc: add mmc_get_env_addr() prototype
Add missing mmc_get_env_addr() prototype in environment.h

Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-08-01 20:11:59 +03:00
Bo Shen
da55c66ec9 MMC: atmel_mci: enable high speed mode support
If the MCI IP version >= 0x300, it supports hight speed mode
option, this patch enable it.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-08-01 20:01:33 +03:00
Bo Shen
70ec3286e6 MMC: atmel_mci: add configuration register definition
Add configuration register definition, this register only
exists on MCI IP version >= 0x300.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-08-01 20:01:22 +03:00
Bo Shen
cd60ebd430 MMC: atmel_mci: refactor setting the mode register
The mode register is different between MCI IP version.
So, according to MCI IP version to set the mode register.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-08-01 20:01:09 +03:00
Chin Liang See
6ace153d13 mmc/dw_mmc: Fix clock divider calculation error for bypass mode
To fix the clock divider calculation error when the controller
clock same as the operating frequency. This is known as bypass
mode. In this mode, the divider should be 0.

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Mischa Jonker <mjonker@synopsys.com>
2014-08-01 19:45:32 +03:00
Marek Vasut
dae0f5c644 mmc: s3c: Add SD driver
Implement SD driver for the S3C24xx family. This implementation
is currently only capable of using the PIO transfers, DMA is not
supported.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-08-01 19:24:34 +03:00
Marek Vasut
7eca6b6327 arm: s3c: Unify the S3C24xx SDI structure
Unify the register structure so they can be easily used across all
of S3C24xx lineup.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-08-01 19:24:23 +03:00
Lubomir Rintel
64973023df bcm2835_sdhci: Add SDHCI_QUIRK_NO_HISPD_BIT flag
Seems like the controller doesn't support the flag. None of the hi-speed cards
I've tried could be read, while they successfully worked with the quirk enabled.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
2014-08-01 18:57:02 +03:00
DrEagle
3fe3b4fb1c ARM: kirkwood: add mvsdio driver
This patch add Marvell kirkwood MVSDIO/MMC driver
and enable it for Sheevaplugs and OpenRD boards.

Signed-off-by: Gerald Kerma <drEagle@doukki.net>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-08-01 18:44:56 +03:00
Hans de Goede
3340eab26d sun7i: Add bananapi board
The Banana Pi is an A20 based development board using Raspberry Pi compatible
IO headers. It comes with 1 GB RAM, 1 Gb ethernet, 2x USB host, sata, hdmi
and stereo audio out + various expansion headers:

http://www.lemaker.org/

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-31 15:37:24 +02:00
Marc Zyngier
cb4ccf2f21 sunxi: HYP/non-sec: configure CNTFRQ on all CPUs
CNTFRQ needs to be properly configured on all CPUs. Otherwise,
virtual machines hoping to find valuable information on secondary
CPUs will be disapointed...

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-07-31 15:37:24 +02:00
Marc Zyngier
d5db7024aa sunxi: HYP/non-sec: add sun7i PSCI backend
So far, only supporting the CPU_ON method.
Other functions can be added later.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-07-31 15:37:24 +02:00
Hans de Goede
366cc50278 sun7i: Add support for a number of new sun7i boards
Add support for boards which I own and which already have a dts file in the
upstream kernel.

Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-31 15:37:23 +02:00
Hans de Goede
f236f79e42 sun5i: Add support for a number of new sun5i boards
Add support for boards which I own and which already have a dts file in the
upstream kernel.

Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-31 15:37:23 +02:00
Hans de Goede
09f951028f sun4i: Add support for a number of new sun4i boards
Add support for boards which I own and which already have a dts file in the
upstream kernel.

Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-31 15:37:23 +02:00
Hans de Goede
fc70300136 sunxi: Add CONFIG_MACPWR option
On some boards the ethernet-phy needs to be powered up through a gpio,
add support for this.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-31 15:37:23 +02:00
Hans de Goede
0061e46462 sunxi: Enable EHCI on various sunxi boards
Most sunxi boards have the EHCI controller hooked up, enable it on all
relevant boards.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-31 15:37:23 +02:00
Hans de Goede
2111484e1f sun5i: add USB EHCI settings
Specific USB EHCI settings to be set for sun5i if CONFIG_USB_EHCI is enabled.

Note we don't specify default VBUS gpio pins for sun5i since they vary too
much from board to board.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-31 15:37:23 +02:00
Hans de Goede
906f609681 sun4i: add USB EHCI settings
Specific USB EHCI settings to be set for sun4i if CONFIG_USB_EHCI is enabled.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-31 15:37:23 +02:00
Ian Campbell
810de2fac0 cubieboard2: Enable AXP209 power controller
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-07-31 15:37:23 +02:00
Roman Byshko
fc36a58828 sun7i: cubietruck: enable USB EHCI
Cubietruck has two USB host controllers. This makes them
usable by enabling the EHCI driver for them.

Signed-off-by: Roman Byshko <rbyshko@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
[hdegoede@redhat.com: Also enable ehci for Cubietruck_FEL]
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-07-31 15:37:23 +02:00
Roman Byshko
263b012c25 sun7i: add USB EHCI settings
Specific USB EHCI settings to be set for sun7i if
CONFIG_USB_EHCI is enabled.

Signed-off-by: Roman Byshko <rbyshko@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
[hdegoede@redhat.com: Use SUNXI_GPH macro for SUNXI_USB_VBUS#_GPIO]
[hdegoede@redhat.com: Add #ifndef SUNXI_USB_VBUS#_GPIO to allow override of
 the default pins from boards.cfg]
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-07-31 15:37:23 +02:00
Roman Byshko
3584f30ce9 sunxi: add general USB settings
General configuration settings to be set if CONFIG_USB_EHCI
is enabled for an Allwinner aka sunxi SoC.

Signed-off-by: Roman Byshko <rbyshko@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-07-31 15:37:22 +02:00
Roman Byshko
8d154002f3 sunxi: add USB EHCI driver
The Allwinner aka sunxi SoCs have one or more USB host controllers.
This adds a driver for their EHCI.

Signed-off-by: Roman Byshko <rbyshko@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-07-31 15:37:22 +02:00
Roman Byshko
06cdd94077 sunxi: add defines to control USB Host clocks/resets
The commit adds three defines which will be used in
the EHCI driver to enable USB clock and assert
reset controllers of the corresponding PHYs.

Signed-off-by: Roman Byshko <rbyshko@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-07-31 15:37:22 +02:00
Ian Campbell
a6e50a88d8 ahci: provide sunxi SATA driver using AHCI platform framework
This enables the necessary clocks, in AHB0 and in PLL6_CFG. This is done
for sun7i only since I don't have access to any other sunxi platforms
with sata included.

The PHY setup is derived from the Alwinner releases and Linux, but is mostly
undocumented.

The Allwinner AHCI controller also requires some magic (and, again,
undocumented) DMA initialisation when starting a port.  This is added under a
suitable ifdef.

This option is enabled for Cubieboard, Cubieboard2 and Cubietruck based on
contents of Linux DTS files, including SATA power pin config taken from the
DTS. All build tested, but runtime tested on Cubieboard2 and Cubietruck only.

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-07-31 15:37:22 +02:00
Masahiro Yamada
25b4adbba0 include: remove CONFIG_SPL/CONFIG_TPL definition in config headers
Now CONFIG_SPL and CONFIG_TPL are defined in Kconfig.

Remove the redundant definition in config headers.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2014-07-30 14:42:03 -04:00
Masahiro Yamada
c6d12624ae powerpc: remove redundant CPU definition
CONFIG_${CPU} is defined by Kconfig.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Stefan Roese <sr@denx.de>
2014-07-30 14:42:03 -04:00
Masahiro Yamada
90f984e397 kconfig: delete redundant CONFIG_${ARCH} definition
CONFIG_${ARCH} is defined by Kconfig.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2014-07-30 14:42:02 -04:00
Masahiro Yamada
73f30b9b80 buildman: adjust for Kconfig
Use "make <board>_defconfig" instead of "make <board>_config".

Invoke tools/genboardscfg.py to generate boards.cfg when it is missing.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-07-30 14:42:02 -04:00
Masahiro Yamada
bb6da87d7e MAKEALL: adjust for Kconfig
- Use "make <board>_defconfig" instead of "make <board>_config".

 - Invoke tools/genboardscfg.py to generate boards.cfg when it is
   missing.

 - Show "Building ${BOARD_NAME} board..." message.
   (Prior to Kconfig, instead, mkconfig script displayed
   "Configuring for ${BOARD_NAME} board..." but it was removed.)
   Without this message, we cannot know which board is currently
   being built.

 - Do not show "# configuration written to .config".
   This message is useless and just annoying for MAKEALL.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-07-30 14:42:02 -04:00
Masahiro Yamada
a2580ebb72 kconfig: remove mkconfig and boards.cfg
The old configuration script is no longer necessary.
Nor is boards.cfg a primary database.
We can generate it with the genboardscfg.py tool
based on the latest Kconfig, defconfig and MAINTAINERS.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-07-30 14:42:02 -04:00
Masahiro Yamada
3c08e8b856 tools: add genboardscfg.py
Now the primary data for each board is in Kconfig, defconfig and
MAINTAINERS.

It is true boards.cfg is needed for MAKEALL and buildman and might be
useful to brouse all the supported boards in a single database.
But it would be painful to maintain the boards.cfg in sync.

So, this is the solution.
Add a tool to generate the equivalent boards.cfg file based on
the latest Kconfig, defconfig and MAINTAINERS.

We can keep all the functions of MAKEALL and buildman with it.

The best thing would be to change MAKEALL and buildman for not
depending on boards.cfg in the future, but it would take some time.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-07-30 14:42:02 -04:00
Masahiro Yamada
93d4334f7f Add board MAINTAINERS files
We have switched to Kconfig and the boards.cfg file is going to
be removed. We have to retrieve the board status and maintainers
information from it.

The MAINTAINERS format as in Linux Kernel would be nice
because we can crib the scripts/get_maintainer.pl script.

After some discussion, we chose to put a MAINTAINERS file under each
board directory, not the top-level one because we want to collect
relevant information for a board into a single place.

TODO:
Modify get_maintainer.pl to scan multiple MAINTAINERS files.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Suggested-by: Tom Rini <trini@ti.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-07-30 08:48:06 -04:00
Masahiro Yamada
51148790f2 kconfig: switch to Kconfig
This commit enables Kconfig.
Going forward, we use Kconfig for the board configuration.
mkconfig will never be used. Nor will include/config.mk be generated.

Kconfig must be adjusted for U-Boot because our situation is
a little more complicated than Linux Kernel.
We have to generate multiple boot images (Normal, SPL, TPL)
from one source tree.
Each image needs its own configuration input.

Usage:

Run "make <board>_defconfig" to do the board configuration.

It will create the .config file and additionally spl/.config, tpl/.config
if SPL, TPL is enabled, respectively.

You can use "make config", "make menuconfig" etc. to create
a new .config or modify the existing one.

Use "make spl/config", "make spl/menuconfig" etc. for spl/.config
and do likewise for tpl/.config file.

The generic syntax of configuration targets for SPL, TPL is:

  <target_image>/<config_command>

Here, <target_image> is either 'spl' or 'tpl'
      <config_command> is 'config', 'menuconfig', 'xconfig', etc.

When the configuration is done, run "make".
(Or "make <board>_defconfig all" will do the configuration and build
in one time.)

For futher information of how Kconfig works in U-Boot,
please read the comment block of scripts/multiconfig.py.

By the way, there is another item worth remarking here:
coexistence of Kconfig and board herder files.

Prior to Kconfig, we used C headers to define a set of configs.

We expect a very long term to migrate from C headers to Kconfig.
Two different infractructure must coexist in the interim.

In our former configuration scheme, include/autoconf.mk was generated
for use in makefiles.
It is still generated under include/, spl/include/, tpl/include/ directory
for the Normal, SPL, TPL image, respectively.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-07-30 08:48:03 -04:00
Masahiro Yamada
4ce9957029 include: define CONFIG_SPL and CONFIG_TPL as 1
We are about to switch to Kconfig in the next commit.
But there are something to get done beforehand.

In Kconfig, include/generated/autoconf.h defines boolean
CONFIG macros as 1.

CONFIG_SPL and CONFIG_TPL, if defined, must be set to 1.
Otherwise, when switching to Kconfig, the build log
would be sprinkled with warning messages like this:
  warning: "CONFIG_SPL" redefined [enabled by default]

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2014-07-30 08:48:02 -04:00
Masahiro Yamada
516312598a kconfig: add basic Kconfig files
This commit adds more Kconfig files, which were written by hand.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-07-30 08:48:02 -04:00
Masahiro Yamada
dd84058d24 kconfig: add board Kconfig and defconfig files
This commit adds:
 - arch/${ARCH}/Kconfig
    provide a menu to select target boards
 - board/${VENDOR}/${BOARD}/Kconfig or board/${BOARD}/Kconfig
    set CONFIG macros to the appropriate values for each board
 - configs/${TARGET_BOARD}_defconfig
    default setting of each board

(This commit was automatically generated by a conversion script
based on boards.cfg)

In Linux Kernel, defconfig files are located under
arch/${ARCH}/configs/ directory.
It works in Linux Kernel since ARCH is always given from the
command line for cross compile.

But in U-Boot, ARCH is not given from the command line.
Which means we cannot know ARCH until the board configuration is done.
That is why all the "*_defconfig" files should be gathered into a
single directory ./configs/.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-07-30 08:48:01 -04:00
Masahiro Yamada
0a9064fb47 kconfig: import Kconfig files from Linux 3.16-rc7
Import
  - scripts/kconfig/*
  - include/linux/kconfig.h
from Linux 3.16-rc7.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2014-07-30 08:47:46 -04:00
Łukasz Majewski
a98b2378e0 boards:trats2: New Trats2 board maintainer
Change-Id: I8e72b942b8816726773d5407ce405d68a1594389
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
2014-07-30 08:47:45 -04:00
Dinh Nguyen
e1b362f442 boards.cfg : Add maintainers entries for SOCFPGA
Add back the maintainers entries for Altera's SOCFPGA platform.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Signed-off-by: Chin Liang See <clsee@altera.com>
2014-07-29 11:51:03 -04:00
Masahiro Yamada
9003a72bfe cosmetic: boards.cfg: fix some maintainers fields
Add a whitespace between the name and the email address.

When switching to Kconfig, the first version of MAINTAINERS files
will be generated based on the boards.cfg file.

So, the maintainers field should be corrected even if it is a really
minor fix.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-07-29 11:48:57 -04:00
Masahiro Yamada
9979692383 buildman: make sure to invoke GNU Make
Since the command name 'make' may not be GNU Make on some platforms
such as FreeBSD, buildman should call scripts/show-gnu-make to get
the command name for GNU MAKE (and error out if it is not found).

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-07-29 11:48:40 -04:00
Masahiro Yamada
e18fd9405c MAKEALL: make sure to invoke GNU Make
Since the command name 'make' may not be GNU Make on some platforms
such as FreeBSD, MAKEALL should call scripts/show-gnu-make to get
the command name for GNU MAKE (and error out if it is not found).

The GNU Make should be searched after parsing options because we want
to allow "MAKEALL -h" even if GNU Make is missing on the system.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-07-29 11:48:38 -04:00
Masahiro Yamada
b68a406263 scripts: add scripts/show-gnu-make to get GNU Make command name
U-Boot is expected to be built on various platforms.

We should keep in mind that the command 'make' is not always GNU Make,
while all the makefiles are written for GNU Make.

For example, on Linux, people generally do:

  make <board>_config; make

But FreeBSD folks do

  gmake <board>_config; gmake

(The command 'make' on FreeBSD is BSD Make, not GNU Make)

It is not a good idea to hard-code the command name 'make'
in MAKEALL or buildman.

They should call this helper script and get the command name
for GNU Make.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-07-29 11:48:36 -04:00
Tom Rini
362f16b1e9 Merge branch 'master' of git://git.denx.de/u-boot-arm 2014-07-29 09:41:35 -04:00
Tom Rini
302e609fe6 Merge git://www.denx.de/git/u-boot-ppc4xx 2014-07-28 17:48:48 -04:00
Tom Rini
d5f8a6ddd4 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2014-07-28 14:54:29 -04:00
Marc Zyngier
9d195a5461 ARM: HYP/non-sec: remove MIDR check to validate CBAR
Having a form of whitelist to check if we know of a CPU core
and and obtain CBAR is a bit silly.

It doesn't scale (how about A12, A17, as well as other I don't know
about?), and is actually a property of the SoC, not the core.

So either it works and everybody is happy, or it doesn't and
the u-boot port to this SoC is providing the real address via
a configuration option.

The result of the above is that this code doesn't need to exist,
is thus forcefully removed.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-28 17:19:55 +02:00
Marc Zyngier
e771a3d538 ARM: HYP/non-sec/PSCI: emit DT nodes
Generate the PSCI node in the device tree.

Also add a reserve section for the "secure" code that lives in
in normal RAM, so that the kernel knows it'd better not trip on
it.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-28 17:19:52 +02:00
Ma Haijun
e29607ed97 ARM: convert arch_fixup_memory_node to a generic FDT fixup function
Some architecture needs extra device tree setup. Instead of adding
yet another hook, convert arch_fixup_memory_node to be a generic
FDT fixup function.

[maz: collapsed 3 patches into one, rewrote commit message]

Signed-off-by: Ma Haijun <mahaijuns@gmail.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-28 17:19:49 +02:00
Marc Zyngier
38510a4b34 ARM: HYP/non-sec: add the option for a second-stage monitor
Allow the switch to a second stage secure monitor just before
switching to non-secure.

This allows a resident piece of firmware to be active once the
kernel has been entered (the u-boot monitor is dead anyway,
its pages being reused).

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-28 17:19:26 +02:00
Marc Zyngier
ecf07a7930 ARM: HYP/non-sec: add generic ARMv7 PSCI code
Implement core support for PSCI. As this is generic code, it doesn't
implement anything really useful (all the functions are returning
Not Implemented).

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-28 17:19:18 +02:00
Marc Zyngier
f510aeae68 ARM: HYP/non-sec: allow relocation to secure RAM
The current non-sec switching code suffers from one major issue:
it cannot run in secure RAM, as a large part of u-boot still needs
to be run while we're switched to non-secure.

This patch reworks the whole HYP/non-secure strategy by:
- making sure the secure code is the *last* thing u-boot executes
  before entering the payload
- performing an exception return from secure mode directly into
  the payload
- allowing the code to be dynamically relocated to secure RAM
  before switching to non-secure.

This involves quite a bit of horrible code, specially as u-boot
relocation is quite primitive.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-28 17:19:09 +02:00
Marc Zyngier
bf433afd60 ARM: HYP/non-sec: add separate section for secure code
In anticipation of refactoring the HYP/non-secure code to run
from secure RAM, add a new linker section that will contain that
code.

Nothing is using it just yet.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-28 17:07:23 +02:00
Marc Zyngier
b726d22da9 ARM: add missing HYP mode constant
In order to be able to use the various mode constants (far more
readable than random hex values), add the missing HYP and A
values.

Also update arm/lib/interrupts.c to display HYP instead of an
unknown value.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-28 17:06:35 +02:00
Marc Zyngier
64fd44dcae ARM: non-sec: reset CNTVOFF to zero
Before switching to non-secure, make sure that CNTVOFF is set
to zero on all CPUs. Otherwise, kernel running in non-secure
without HYP enabled (hence using virtual timers) may observe
timers that are not synchronized, effectively seeing time
going backward...

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-28 17:06:28 +02:00
Marc Zyngier
800c83522c ARM: HYP/non-sec: add a barrier after setting SCR.NS==1
A CP15 instruction execution can be reordered, requiring an
isb to be sure it is executed in program order.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-28 17:06:19 +02:00
Marc Zyngier
c19e0dd741 ARM: HYP/non-sec: move switch to non-sec to the last boot phase
Having the switch to non-secure in the "prep" phase is causing
all kind of troubles, as that stage can be called multiple times.

Instead, move the switch to non-secure to the last possible phase,
when there is no turning back anymore.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-28 17:05:59 +02:00
Albert ARIBAUD
b1cdd8baa1 Merge branch 'u-boot-ti/master' into 'u-boot-arm/master' 2014-07-28 12:26:21 +02:00
Albert ARIBAUD
48b3ed217f Merge branch 'u-boot-sh/rmobile' into 'u-boot-arm/master' 2014-07-28 10:54:54 +02:00
Albert ARIBAUD
740f41d3cb Merge branch 'u-boot-sunxi/master' into 'u-boot-arm/master' 2014-07-28 10:12:45 +02:00
Masahiro Yamada
ee860c60d2 patman: make "No recipient" checking more tolerant
If Series-to tag is missing, Patman exits with a message
"No recipient".

This is just annoying for those who had already added
sendemail.to configuration.

I guess many developers have

  [sendemail]
          to = u-boot@lists.denx.de

in their .git/config because the 'To: u-boot@lists.denx.de' field
should always be added when sending patches.

That seems more reasonable rather than adding
'Series-to: u-boot@lists.denx.de' to every patch series.

Patman should exit only when both Series-to tag and sendemail.to
configuration are mising.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
2014-07-28 04:57:24 +01:00
Simon Glass
189a496825 buildman: Support in-tree builds
At present buildman always builds out-of-tree, that is it uses a separate
output directory from the source directory. Normally this is what you want,
but it is important that in-tree builds work also. Some Makefile changes may
break this.

Add a -i option to tell buildman to use in-tree builds, so that it is easy
to test this feature.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-28 04:52:55 +01:00
Simon Glass
97e915262e buildman: Add -C option to force a reconfigure for each commit
Normally buildman wil try to configure U-Boot for a particular board on the
first commit that it builds in a series. Subsequent commits are built
without reconfiguring which normally works. Where it doesn't, buildman
automatically reconfigures and retries.

To fully emulate the way MAKEALL works, we should have an option to disable
this optimisation.

Add a -C option to cause buildman to always reconfigure on each commit.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-28 04:52:48 +01:00
Albert ARIBAUD
f2c8d7f591 Merge branch 'u-boot-microblaze/zynq' into 'u-boot-arm/master' 2014-07-26 14:08:36 +02:00
pekon gupta
434f2cfcad ARM: omap: move board specific NAND configs out from ti_armv7_common.h
This patch moves some board specific NAND configs:
- FROM: generic config file 'ti_armv7_common.h'
- TO:   individual board config files using these configs.
So that each board can independently set the value as per its design.

Following configs are affected in this patch:
  CONFIG_SYS_NAND_U_BOOT_OFFS: <refer doc/README.nand>
  CONFIG_CMD_SPL_NAND_OFS: <refer doc/README.falcon>
  CONFIG_SYS_NAND_SPL_KERNEL_OFFS: <refer doc/README.falcon>
  CONFIG_CMD_SPL_WRITE_SIZE: <refer doc/README.falcon>

This patch also updates documentation for few of above NAND configs.

Signed-off-by: Pekon Gupta <pekon@ti.com>
2014-07-25 16:26:12 -04:00
pekon gupta
222a3113b4 ARM: omap: clean redundant PISMO_xx macros used in OMAP3
PISMO_xx macros were used to define 'Platform Independent Storage MOdule'
related GPMC configurations. This patch
- Replaces these OMAP3 specific macros with generic CONFIG_xx macros as provided
  by current u-boot infrastructure.
- Removes unused redundant macros, which are no longer required after
  merging of common platform code in following commit
      commit a0a37183bd
      ARM: omap: merge GPMC initialization code for all platform

+-----------------+-----------------------------------------------------------+
| Macro           | Reason for removal                                        |
+-----------------+-----------------------------------------------------------+
| PISMO1_NOR_BASE | duplicate of CONFIG_SYS_FLASH_BASE                        |
+-----------------+-----------------------------------------------------------+
| PISMO1_NAND_BASE| duplicate of CONFIG_SYS_NAND_BASE                         |
+-----------------+-----------------------------------------------------------+
| PISMO1_ONEN_BASE| duplicate of CONFIG_SYS_ONENAND_BASE                      |
+-----------------+-----------------------------------------------------------+
| PISMO1_NAND_SIZE| GPMC accesses NAND device via I/O mapped registers so     |
|                 | configuring GPMC chip-select for smallest allowable       |
|                 | segment (GPMC_SIZE_16M) is enough.                        |
+-----------------+-----------------------------------------------------------+
| PISMO1_ONEN_SIZE| OneNAND uses a fixed GPMC chip-select address-space of    |
|                 | 128MB (GPMC_SIZE_128M)                                    |
+-----------------+-----------------------------------------------------------+
+-----------------+-----------------------------------------------------------+
| PISMO1_NOR      |  Unused Macros                                            |
| PISMO1_NAND     |                                                           |
| PISMO2_CS0      |                                                           |
| PISMO2_CS1      |                                                           |
| PISMO1_ONENAND  |                                                           |
| PISMO2_NAND_CS0 |                                                           |
| PISMO2_NAND_CS1 |                                                           |
| PISMO1_NOR_BASE |                                                           |
| PISMO1_NAND_BASE|                                                           |
| PISMO2_CS0_BASE |                                                           |
+-----------------+-----------------------------------------------------------+

Signed-off-by: Pekon Gupta <pekon@ti.com>
2014-07-25 16:26:12 -04:00
pekon gupta
77cd89e755 ARM: omap: fix GPMC address-map size for NAND and NOR devices
Fixes commit a0a37183bd
    ARM: omap: merge GPMC initialization code for all platform

1) NAND device are not directly memory-mapped to CPU address-space, they are
 indirectly accessed via following GPMC registers:
 - GPMC_NAND_COMMAND_x
 - GPMC_NAND_ADDRESS_x
 - GPMC_NAND_DATA_x
 Therefore from CPU's point of view, NAND address-map can be limited to just
 above register addresses. But GPMC chip-select address-map can be configured
 in granularity of 16MB only.
 So this patch uses GPMC_SIZE_16M for all NAND devices.

2) NOR device are directly memory-mapped to CPU address-space, so its
 address-map size depends on actual addressable region in NOR FLASH device.
 So this patch uses CONFIG_SYS_FLASH_SIZE to derive GPMC chip-select address-map
 size configuration.

Signed-off-by: Pekon Gupta <pekon@ti.com>
2014-07-25 16:26:12 -04:00
Rajendra Nayak
8c16dd6fa7 ARM: OMAP: Fix handling of errata i727
The errata is applicable on all OMAP4 (4430 and 4460/4470) and OMAP5
ES 1.0 devices. The current revision check erroneously implements this
on all DRA7 varients and with DRA722 device (which has only 1 EMIF instance)
infact causes an asynchronous abort and ends up masking it in CPSR,
only to be uncovered once the kernel switches to userspace.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2014-07-25 16:26:11 -04:00
Hao Zhang
a906847966 board: k2e-evm: add board support
This patch adds Keystone2 k2e_evm evaluation board support.

Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:11 -04:00
Khoronzhuk, Ivan
1284246eb9 ARM: keystone2: spl: add K2E SoC support
Keystone2 K2E SoC has slightly different spl pll settings then
K2HK, so correct this.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:11 -04:00
Khoronzhuk, Ivan
7c38764606 keystone2: use CONFIG_SOC_KEYSTONE in common places
Use CONFIG_SOC_KEYSTONE in common places instead of defining
a lot of "if def .. || if def " for different Keystone2 SoC types.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:11 -04:00
Hao Zhang
20187fd11c ARM: keystone2: add MSMC cache coherency support for K2E SOC
This patch adds Keystone2 K2E SOC specific code to support
MSMC cache coherency. Also create header file for msmc to hold
its API.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:11 -04:00
Hao Zhang
4dca7f0acc ARM: keystone2: clock: add K2E clock support
This patch adds clock definitions and commands to support Keystone2
K2E SOC.

Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:11 -04:00
Hao Zhang
5c76f78858 ARM: keystone2: add K2E SoC hardware definitions
This patch adds hardware definitions specific to Keystone II
K2E device. It has a lot common definitions with k2hk SoC, so
move them to common hardware.h. This is preparation patch for
adding K2E SoC support.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:11 -04:00
Hao Zhang
b1babef856 keystone: ddr3: move K2HK DDR3 configuration to a common file
It's convenient to hold configurations for DDR3 PHY and EMIF in
separate common place. This patch moves K2HK DDR3 PHY and EMIF
configuration data with different rates and memory size to a common
ddr3_cfg.c file.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:11 -04:00
Hao Zhang
2221cd12cd configs: k2hk_evm: config: add common EVM configuration header
This patch adds a common config header file for all the Keystone II
EVM platforms. It combines a lot of general definitions in one file.
The common header included in the EVM should be specific configuration
header.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:10 -04:00
Khoronzhuk, Ivan
8dfc15f56c ARM: keystone: clock: move K2HK SoC dependent code in separate file
This patch in general spit SoC type clock dependent code and general
clock code. Before adding keystone II Edison k2e SoC which has
slightly different dpll set, move k2hk dependent clock code to
separate clock-k2hk.c file.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:10 -04:00
Hao Zhang
e595107ebb ARM: keystone2: move K2HK board files to common KS2 board directory
This patch moves K2HK board directory to a common Keystone II board
directory. The Board related common functions are moved to a common
keystone board file.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:10 -04:00
Murali Karicheri
0bedbb8135 keystone2: add env option to do unitrd dt fixup
With latest v3.13 kernel, unitrd dt fixup is not needed. However for
older kernel versions such as v3.8/v3.10, it is needed. So to work
with both, add a u-boot env variable that can be set to do dt fixup
for older kernels.

Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:10 -04:00
Khoronzhuk, Ivan
3d31538625 k2hk: use common KS2_ prefix for all hardware definitions
Use KS2_ prefix in all definitions, for that replace K2HK_ prefix and
add KS2_ prefix where it's needed. It requires to change names also
in places where they're used. Align lines and remove redundant
definitions in kardware-k2hk.h at the same time.

Using common KS2_ prefix helps resolve redundant redefinitions and
adds opportunity to use KS2_ definition across a project not thinking about
what SoC should be used. It's more convenient and we don't need to worry
about the SoC type in common files, hardware.h will think about that.
The hardware.h decides definitions of what SoC to use.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:10 -04:00
Hao Zhang
7b26c1f608 keystone2: add possibility to turn off all dsps
By default all DSPs are turned off, for another case option
to turn off them is added in this commit.
Also add command to turn off itself.

Acked-by: Murali Karicheri <m-maricheri2@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:10 -04:00
Hao Zhang
4984bce41f keystone2: move cpu_to_bus() to keystone.c
The SoC related common functions in board.c should be placed to
a common keystone.c arch file.

Acked-by: Murali Karicheri <m-maricheri2@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:10 -04:00
Khoronzhuk, Ivan
35c547c2bc ARM: keystone2: keystone_nav: make it dependent on keystone driver
This driver is needed in case if keystone driver is used.
Currently only keystone_net driver uses it. So to avoid
redundant code compilation make the keystone_nav dependent
on keystone net driver. It also leads to compilation errors
for boards that does't use it.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:09 -04:00
Hao Zhang
101eec50f0 keystone2: ddr: add DDR3 PHY configs updated for PG 2.0
Add DDR3 PHY configs updated for PG 2.0
Also add DDR3A PHY reset before init for PG2.0 SoCs.

Acked-by: Murali Karicheri <m-maricheri2@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:09 -04:00
Khoronzhuk, Ivan
0b86858956 keystone: ddr3: add ddr3.h to hold ddr3 API
It's convinient to hold ddr3 function definitions in separate file
such as ddr3.h. So move this from hardware.h to ddr3.h.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:09 -04:00
Khoronzhuk, Ivan
04b7ce0773 ARM: keystone2: psc: use common PSC base
Use common keystone2 Power Sleep controller base address instead of
directly deciding which keystone2 SoC is used in psc module.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:09 -04:00
Stefan Roese
188948e884 ARM: omap: tao3530: Convert to generic board
Use generic board setup functions by defining
CONFIG_SYS_GENERIC_BOARD.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@ti.com>
2014-07-25 16:26:09 -04:00
Stefan Roese
6d3bbdb0e7 ARM: omap: Remove unused arch/arm/cpu/armv7/omap3/mem.c
These functions have been merged into the common GPMC init code
with this commit a0a37183 (ARM: omap: merge GPMC initialization code
for all platform). The file is not compiled any more. So remove it
as well.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Pekon Gupta <pekon@ti.com>
Cc: Tom Rini <trini@ti.com>
Acked-by: Pekon Gupta <pekon@ti.com>
2014-07-25 16:26:09 -04:00
Stefan Roese
fb2fcb798a ARM: omap: Fix GPMC init for OMAP3 platforms
Commit a0a37183 (ARM: omap: merge GPMC initialization code for all
platform) broke NAND on OMAP3 based platforms. I noticed this while
testing the latest 2014.07-rc version on the TAO3530 board. NAND
detection did not work with this error message:

NAND:  nand: error: Unable to find NAND settings in GPMC Configuration - quitting

As OMAP3 configs don't set CONFIG_NAND but CONFIG_NAND_CMD. the GPMC
was not initialized for NAND at all. This patch now fixes this issue.

Tested on TAO3530 board.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Pekon Gupta <pekon@ti.com>
Cc: Tom Rini <trini@ti.com>
Acked-by: Pekon Gupta <pekon@ti.com>
2014-07-25 16:26:09 -04:00
Andreas Bießmann
e6f9d419c8 tricorder: convert to generic board
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Thomas Weber <thomas.weber@corscience.de>
2014-07-25 16:26:08 -04:00
Tom Rini
c4f80f5003 am335x_evm / gumstix pepper: Correct DDR settings
As noted by clang, we have been shifting certain values out of 32bit
range when setting some DDR registers.  Upon further inspection these
had been touching reserved fields (and having no impact).  These came in
from historical bring-up code and can be discarded.  Similarly, we had
been declaring some fields as 0 when they will be initialized that way.
Tested on Beaglebone White.

Reported-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Cc: Ash Charles <ash@gumstix.com>
Signed-off-by: Tom Rini <trini@ti.com>
Tested-By: Ash Charles <ashcharles@gmail.com>
2014-07-25 16:26:08 -04:00
Khoronzhuk, Ivan
c6ac7e3bdc k2hk_evm: add script to automate NAND flash process
Add script to automate NAND flash process. As for now the board has
two burn scripts - burn to boot from SPI NOR flash and burn to boot
from AEMIF NAND flash, rename burn_uboot script to burn_uboot_spi.
Also update README to contain NAND burn U-boot process description.

Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Acked-by: Murali Karicheri <m-karicheri2@ti.com>
2014-07-25 15:21:06 -04:00
Khoronzhuk, Ivan
0e7f2dbac6 keystone: add support for NAND gpheader image
Add support for NAND gpheader image. TI Keystone2 ROM bootloader
expects 8 bytes of trailing zeroes in the nand u-boot image.
So add zeros at the end of the nand gph image.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 15:21:06 -04:00
Khoronzhuk, Ivan
67ac6ffaee mtd: nand: davinci: add opportunity to write keystone U-boot image
The Keystone SoCs use the same NAND driver as Davinci.
This patch adds opportunity to write Keystone U-boot image to NAND
device using appropriate RBL ECC layout. This is needed only if RBL
boots U-boot from NAND device and that's supposed that raw u-boot
partition is used only for writing image.

The main problem is that default Davinci ECC layout is different from
Keystone RBL layout. To read U-boot image the RBL needs that image was
written using RBL ECC layout.

The BBT table is written using default Davinci layout and has to
be updated using one. The BBT can be updated only while erasing
chip or by forced bad block assigning, so erase function has to
use native ecc layout in order to be able to write BBT correctly.
So if we're writing to NAND U-boot address we use RBL layout for
others we use default ECC layout.

Also remove definition for CONFIG_CMD_NAND_ECCLAYOUT as there is no
reasons to use ECC layout commands. It was added by mistake.

Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 15:21:06 -04:00
Tom Rini
7aa5598aac tps65218/am43xx_evm: Add power framework support to TPS65218
Add in an init function for the drivers/power framework so we can dump
and read the registers via i2c.

Cc: Łukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Tom Rini <trini@ti.com>
2014-07-25 15:21:06 -04:00
Tom Rini
5c44dd6bbd power/pmic.h: Add prototype for power_init_board.
As this is a weak function that we may override, provide a prototype for
it.

Cc: Łukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Tom Rini <trini@ti.com>
2014-07-25 15:21:05 -04:00
Mugunthan V N
4c8014b942 ARM: dra7_evm: Add Ethernet support for dra72x platform
Set the active_slave to 1 as slave 1 is pinned out in dra72x base board

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2014-07-25 15:21:05 -04:00
Mugunthan V N
e5ff845bff ARM: DRA7xx: Add cpsw second port pinmux
Add cpsw second slave port pinmux to use it as primary ethernet port

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2014-07-25 15:21:05 -04:00
Mugunthan V N
7a0227534d drivers: net: cpsw: add support for using second port as ethernet
Add support for using the second slave port of cpsw
to be used as primary ethernet.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2014-07-25 15:21:05 -04:00
Tom Rini
772e173802 Merge branch 'master' of git://git.denx.de/u-boot-sh 2014-07-25 15:05:09 -04:00
Dirk Eibach
d9f923ffcb board: Add CONFIG_SYS_GENERIC_BOARD to all gdsys boards
Add the generic board infrastructure to all gdsys boards.

Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Stefan Roese <sr@denx.de>
2014-07-25 10:55:49 +02:00
Dirk Eibach
d29437aa77 ppc: Make ppc4xx ready for CONFIG_SYS_GENERIC_BOARD
The generic board  infrastructure assumes that gd is set by
arch code.

Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Stefan Roese <sr@denx.de>
2014-07-25 10:55:49 +02:00
Nobuhiro Iwamatsu
cff2f5f09e arm: rmobile: Add support Alt board
The alt board has R8A7794, 1GB DDR3-SDRAM, USB, Ethernet, QSPI,
MMC, SDHI and more.

This commit supports the following functions:
 - DDR3-SDRAM
 - SCIF
 - I2C
 - Ethernet
 - QSPI

Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-07-24 14:03:46 +09:00
Nobuhiro Iwamatsu
fafcfc5a98 arm: rmobile: Add support R8A7794
Renesas R8A7794 is CPU with Cortex-A15. This supports the basic register
definition and GPIO and framework of PFC.

Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-07-24 14:03:46 +09:00
Nobuhiro Iwamatsu
2f972a3c62 serial: sh: Add support R8A7794
This adds the preset value to register for R8A7794.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-07-24 14:03:46 +09:00
Nobuhiro Iwamatsu
172437472a net: sh-eth: Add support R8A7794
R8A7794 has the same sh-ether IP core as other SH/rmobile.
This patch adds support of R8A7794.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-07-24 14:03:46 +09:00
Masahiro Yamada
afc3929fac sh: unify sh2/sh3/sh4 linker scripts
The linker scripts of sh2/sh3/sh4 are almost the same.
The difference among them is essentially only one line.

They can be consolidated into a single file, arch/sh/cpu/u-boot.lds
by re-writing the diffrent line as follows:

	KEEP(*/start.o	(.text))

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2014-07-24 12:02:23 +09:00
Shengzhou Liu
fb5368789a board/freescale: use generic board architecture for t2080qds and t2080rdb
Tested with NOR boot and NAND boot on T2080QDS and T2080RDB.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
2014-07-23 12:40:30 -07:00
Simon Glass
21fe8ec355 buildman: Avoid retrying a build if it definitely failed
After a build fails buildman will reconfigure and try again, if it did not
reconfigure before the build. However it doesn't actually keep track of
whether it did reconfigure on the previous attempt.

Fix that logic to avoid a pointless rebuild. This speeds things up quite a
bit for failing builds. Previously they would always be built twice.

Change-Id: Ib37f21320baa7c60bed98f4042c0b7ed7c0dc85e
Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 09:52:36 -06:00
Simon Glass
4266dc2882 buildman: Add -F flag to retry failed builds
Generally a build failure with a particular commit cannot be fixed except
by changing that commit. Changing the commit will automatically cause
buildman to retry when you run it again: buildman sees that the commit
hash is different and that it has no previous build result for the new
commit hash.

However sometimes the build failure is due to a toolchain issue or some
other environment problem. In that case, retrying failed builds may yield
a different result.

Add a flag to retry failed builds. This differs from the force rebuild
flag (-f) in that it will not rebuild commits which are already marked as
succeeded.

Series-to: u-boot

Change-Id: Iac4306df499d65ff0888b1c60f06fc162a6faad8
2014-07-23 09:52:33 -06:00
Masahiro Yamada
327474915a zynq: disable -Wstrict-prototypes option for ps7_init.c
The files ps7_init.c and ps7_init.h are supposed to be generated by
hw projects such as Vivado, PlanAhead and then to be copied into
board/xilinx/zynq directory.

But some prototypes in them cause annoying warning messages:

  CC      spl/board/xilinx/zynq/ps7_init.o
In file included from board/xilinx/zynq/ps7_init.c:50:0:
board/xilinx/zynq/ps7_init.h:137:1: warning: function declaration isn't a prototype [-Wstrict-prototypes]
board/xilinx/zynq/ps7_init.h:138:1: warning: function declaration isn't a prototype [-Wstrict-prototypes]
board/xilinx/zynq/ps7_init.h:139:1: warning: function declaration isn't a prototype [-Wstrict-prototypes]
board/xilinx/zynq/ps7_init.h:145:1: warning: function declaration isn't a prototype [-Wstrict-prototypes]
board/xilinx/zynq/ps7_init.c:12602:1: warning: function declaration isn't a prototype [-Wstrict-prototypes]
board/xilinx/zynq/ps7_init.c:12723:1: warning: function declaration isn't a prototype [-Wstrict-prototypes]
board/xilinx/zynq/ps7_init.c:12742:1: warning: function declaration isn't a prototype [-Wstrict-prototypes]
board/xilinx/zynq/ps7_init.c:12761:1: warning: function declaration isn't a prototype [-Wstrict-prototypes]
board/xilinx/zynq/ps7_init.c:12854:6: warning: function declaration isn't a prototype [-Wstrict-prototypes]

The prototypes should be

  int ps7_init(void);
  int ps7_post_config(void);
  int ps7_debug(void);

rather than

  int ps7_init();
  int ps7_post_config();
  int ps7_debug();

We do not want to be bothered because of automatically generated files.
But we cannot touch the external projects for now.
What we can do is to disable -Wstrict-prototypes for ps7_init.c

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Tested-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-07-23 15:38:34 +02:00
Michal Simek
03606ff42e ARM: zynq: Show ECC status on the same line as DRAM size
Without this patch is DRAM size one line below DRAM:
which is not nice

Origin:
I2C:   ready
DRAM:  Memory: ECC disabled
1 GiB
MMC:   zynq_sdhci: 0

Fixed by this patch:
I2C:   ready
DRAM:  ECC disabled 1 GiB
MMC:   zynq_sdhci: 0

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-07-23 15:36:55 +02:00
Michal Simek
2b25721645 ARM: zynq: Enable generic board for Xilinx Zynq
Enable CONFIG_SYS_GENERIC_BOARD for all Zynq boards.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Masahiro Yamada <yamada.m@jp.panasonic.com> [on ZC706 board]
2014-07-23 15:28:22 +02:00
Simon Glass
74f96dada1 dm: Give the demo uclass a name
Uclasses should be named, so add a name for the demo uclass.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:08:37 +01:00
Simon Glass
bb58503d80 dm: Add dm_scan_other() to locate board-specific devices
Some boards will have devices which are not in the device tree and do not
have platform data. They may be programnatically created, for example.
Add a hook which boards can use to bind those devices early in boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:08:37 +01:00
Simon Glass
9b0ba067f9 dm: Improve errors and warnings in lists_bind_fdt()
Add a debug message for when a device tree node has no driver. Also reword
the warning when a device fails to bind, which was misleading.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:08:37 +01:00
Simon Glass
a327dee0f4 dm: Add child_pre_probe() and child_post_remove() methods
Some devices (particularly bus devices) must track their children, knowing
when a new child is added so that it can be set up for communication on the
bus.

Add a child_pre_probe() method to provide this feature, and a corresponding
child_post_remove() method.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:08:37 +01:00
Simon Glass
e59f458de6 dm: Introduce per-child data for devices
Some device types can have child devices and want to store information
about them. For example a USB flash stick attached to a USB host
controller would likely use this space. The controller can hold
information about the USB state of each of its children.

The data is stored attached to the child device in the 'parent_priv'
member. It can be auto-allocated by dm when the child is probed. To
do this, add a per_child_auto_alloc_size value to the parent driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:08:37 +01:00
Simon Glass
997c87bb0b dm: Add functions to access a device's children
Devices can have childen that can be addressed by a simple index, the
sequence number or a device tree offset. Add functions to access a child
in each of these ways.

The index is typically used as a fallback when the sequence number is not
available. For example we may use a serial UART with sequence number 0 as
the console, but if no UART has sequence number 0, then we can fall back
to just using the first UART (index 0).

The device tree offset function is useful for buses, where they want to
locate one of their children. The device tree can be scanned to find the
offset of each child, and that offset can then find the device.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:08:37 +01:00
Simon Glass
1ca7e2062b dm: Provide a function to scan child FDT nodes
At present only root nodes in the device tree are scanned for devices.
But some devices can have children. For example a SPI bus may have
several children for each of its chip selects.

Add a function which scans subnodes and binds devices for each one. This
can be used for the root node scan also, so change it.

A device can call this function in its bind() or probe() methods to bind
its children.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:08:36 +01:00
Simon Glass
0040b94429 dm: Tidy up some header file comments
Fix up the style of a few comments and add/clarify a few others.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:07:26 +01:00
Simon Glass
3234aa4bab fdt: Add a function to get the node offset of an alias
This simple function returns the node offset of a named alias.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:07:26 +01:00
Simon Glass
c910e2e2da dm: Avoid accessing uclasses before they are ready
Don't allow access to uclasses before they have been initialised.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:07:26 +01:00
Simon Glass
f4cdead24a dm: Allow a device to be found by its FDT offset
Each device that was bound from a device tree has an node that caused it to
be bound. Add functions that find and return a device based on a device tree
offset.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:07:25 +01:00
Simon Glass
b7d665705e dm: Display the sequence number for each device
Add this information to 'dm tree' and 'dm uclass' commands.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:07:25 +01:00
Simon Glass
5a66a8ff86 dm: Introduce device sequence numbering
In U-Boot it is pretty common to number devices from 0 and access them
on the command line using this numbering. While it may come to pass that
we will move away from this numbering, the possibility seems remote at
present.

Given that devices within a uclass will have an implied numbering, it
makes sense to build this into driver model as a core feature. The cost
is fairly small in terms of code and data space.

With each uclass having numbered devices we can ask for SPI port 0 or
serial port 1 and receive a single device.

Devices typically request a sequence number using aliases in the device
tree. These are resolved when the device is probed, to deal with conflicts.
Sequence numbers need not be sequential and holes are permitted.

At present there is no support for sequence numbers using static platform
data. It could easily be added to 'struct driver_info' if needed, but it
seems better to add features as we find a use for them, and the use of -1
to mean 'no sequence' makes the default value somewhat painful.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:07:25 +01:00
Simon Glass
4e8bc21170 dm: Avoid activating devices in 'dm uclass' command
This command currently activates devices as it lists them. This is not
desirable since it changes the system state. Fix it and avoid printing
a newline if there are no devices in a uclass.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:07:25 +01:00
Simon Glass
fffa24d7c5 dm: Move device display into its own function
The device display for 'dm tree' and 'dm uclass' is mostly the same, so
move it into a common function.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:07:25 +01:00
Simon Glass
5c33c9fdbb fdt: Add a function to get the alias sequence of a node
Aliases are used to provide U-Boot's numbering of devices, such as:

aliases {
	spi0 = "/spi@12330000";
}

spi@12330000 {
	...
}

This tells us that the SPI controller at 12330000 is considered to be the
first SPI controller (SPI 0). So we have a numbering for the SPI node.

Add a function that returns the numbering for a node assume that it exists
in the list of aliases.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:07:25 +01:00
Simon Glass
9ca296a1b0 dm: Move uclass error checking/probing into a function
Several functions will use this same pattern, so bring it into a function.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:07:25 +01:00
Simon Glass
093f79ab88 Add a flag indicating when the serial console is ready
For sandbox we have a fallback console which is used very early in
U-Boot, before serial drivers are available. Rather than try to guess
when to switch to the real console, add a flag so we can be sure. This
makes sure that sandbox can always output a panic() message, for example,
and avoids silent failure (which is very annoying in sandbox).

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:07:25 +01:00
Simon Glass
7793ac96c6 console: Remove vprintf() optimisation for sandbox
If the console is not present, we try to reduce overhead by stopping any
output in vprintf(), before it gets to putc(). This is of dubious merit
in general, but in the case of sandbox it is incorrect since we have a
fallback console which reports errors very early in U-Boot. If this is
defeated U-Boot can hang or exit with no indication of what is wrong.

Remove the optimisation for sandbox.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:07:24 +01:00
Simon Glass
d97143a67c stdio: Provide functions to add/remove devices using stdio_dev
The current functions for adding and removing devices require a device name.
This is not convenient for driver model, which wants to store a pointer to
the relevant device. Add new functions which provide this feature and adjust
the old ones to call these.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:07:24 +01:00
Simon Glass
ab7cd62790 dm: Support driver model prior to relocation
Initialise devices marked 'pre-reloc' and make them available prior to
relocation. Note that this requires pre-reloc malloc() to be available.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:07:24 +01:00
Simon Glass
00606d7e39 dm: Allow drivers to be marked 'before relocation'
Driver model currently only operates after relocation is complete. In this
state U-Boot typically has a small amount of memory available. In adding
support for driver model prior to relocation we must try to use as little
memory as possible.

In addition, on some machines the memory has not be inited and/or the CPU
is not running at full speed or the data cache is off. These can reduce
execution performance, so the less initialisation that is done before
relocation the better.

An immediately-obvious improvement is to only initialise drivers which are
actually going to be used before relocation. On many boards the only such
driver is a serial UART, so this provides a very large potential benefit.

Allow drivers to mark themselves as 'pre-reloc' which means that they will
be initialised prior to relocation. This can be done either with a driver
flag or with a 'dm,pre-reloc' device tree property.

To support this, the various dm scanning function now take a 'pre_reloc_only'
parameter which indicates that only drivers marked pre-reloc should be
bound.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:07:24 +01:00
Simon Glass
6133683320 sandbox: Remove all drivers before exit
Drivers are supposed to be able to close down cleanly. To set a good example,
make sandbox shut down its driver model drivers and remove them before exit.

It may be desirable to do the same more generally once driver model is more
widely-used. This could be done during bootm, before U-Boot jumps to the OS.
It seems far too early to make this change.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:07:24 +01:00
Simon Glass
9adbd7a116 dm: Provide a way to shut down driver model
Add a new method which removes and unbinds all drivers.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Marek Vasut <marex@denx.de>
2014-07-23 14:07:24 +01:00
Simon Glass
7497812d47 dm: Make sure that the root device is probed
The root device should be probed just like any other device. The effect of
this is to mark the device as activated, so that it can be removed (along
with its children) if required.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Marek Vasut <marex@denx.de>
2014-07-23 14:07:24 +01:00
Simon Glass
709ea543b9 stdio: Pass device pointer to stdio methods
At present stdio device functions do not get any clue as to which stdio
device is being acted on. Some implementations go to great lengths to work
around this, such as defining a whole separate set of functions for each
possible device.

For driver model we need to associate a stdio_dev with a device. It doesn't
seem possible to continue with this work-around approach.

Instead, add a stdio_dev pointer to each of the stdio member functions.

Note: The serial drivers have the same problem, but it is not strictly
necessary to fix that to get driver model running. Also, if we convert
serial over to driver model the problem will go away.

Code size increases by 244 bytes for Thumb2 and 428 for PowerPC.

22: stdio: Pass device pointer to stdio methods
       arm: (for 2/2 boards)  all +244.0  bss -4.0  text +248.0
   powerpc: (for 1/1 boards)  all +428.0  text +428.0

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
2014-07-23 14:07:23 +01:00
Simon Glass
91d0be1dd8 stdio: Remove redundant code around stdio_register() calls
There is no point in setting a structure's memory to NULL when it has
already been zeroed with memset().

Also, there is no need to create a stub function for stdio to call - if the
function is NULL it will not be called.

This is a clean-up, with no change in functionality.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Marek Vasut <marex@denx.de>
2014-07-23 14:07:23 +01:00
Simon Glass
eb9ef5fee7 dm: Use an explicit expect value in core tests
Rather than reusing the 'reg' property, use an explicit property for the
expected ping value used in testing.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:07:23 +01:00
Simon Glass
5b9765c7d6 dm: gpio: Don't use the driver model uclass for SPL
Driver model does not support SPL yet, so we should not use the GPIO
uclass for SPL.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:07:23 +01:00
Simon Glass
6d7601e744 sandbox: Always enable malloc debug
Tun on DEBUG in malloc(). This adds code space and slows things down but
for sandbox this is acceptable. We gain the ability to check for memory
leaks in tests.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:06:17 +01:00
Simon Glass
b53e94b132 sandbox: config: Enable pre-relocation malloc()
Enable this for sandbox so that we will be able to use driver model before
relocation.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:06:17 +01:00
Simon Glass
29afe9e6ed sandbox: Support pre-relocation malloc()
Set up and zero global data before board_init_f() is called so that we can
remove the need for CONFIG_SYS_GENERIC_GLOBAL_DATA.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:06:13 +01:00
Simon Glass
d59476b644 Add a simple malloc() implementation for pre-relocation
If we are to have driver model before relocation we need to support some
way of calling memory allocation routines.

The standard malloc() is pretty complicated:

1. It uses some BSS memory for its state, and BSS is not available before
relocation

2. It supports algorithms for reducing memory fragmentation and improving
performace of free(). Before relocation we could happily just not support
free().

3. It includes about 4KB of code (Thumb 2) and 1KB of data. However since
this has been loaded anyway this is not really a problem.

The simplest way to support pre-relocation malloc() is to reserve an area
of memory and allocate it in increasing blocks as needed. This
implementation does this.

To enable it, you need to define the size of the malloc() pool as described
in the README. It will be located above the pre-relocation stack on
supported architectures.

Note that this implementation is only useful on machines which have some
memory available before dram_init() is called - this includes those that
do no DRAM init (like tegra) and those that do it in SPL (quite a few
boards). Enabling driver model preior to relocation for the rest of the
boards is left for a later exercise.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:05:40 +01:00
Simon Glass
4d94dfa059 sandbox: Set up global data before board_init_f()
At present sandbox defines CONFIG_SYS_GENERIC_GLOBAL_DATA, meaning that
the global_data pointer is set up in board_init_f().

If we set up and zero the global data before calling board_init_f() then we
don't need to define CONFIG_SYS_GENERIC_GLOBAL_DATA.

Make this change to simplify the init process.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:05:39 +01:00
Simon Glass
d93041a4ca Remove form-feeds from dlmalloc.c
These don't really serve any purpose in the modern age. On the other hand
they show up as annoying control characters in my editor, which then happily
removes them.

I believe we can drop these characters from the file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:02:58 +01:00
Markus Niebel
cb07d74e2e Add TQ Systems TQMa6 board support
This patch adds the changes to boards.cfg and the board directory
under board/tqc.

TQMa6 is a family of modules based on Freescale i.MX6. It consists of
TQMa6Q (i.MX6 Quad), TQMa6D (i.MX6 Dual) featuring eMMC, and 1 GiB DDR3
TQMa6S (i.MX6 Solo)  featuring eMMC and 512 MiB DDR3

The modules need a baseboard. Initially the MBa6x starterkit mainboard is
supported. To easy support for other mainboards the functionality is splitted
in one file for the module (tqma6.c) and one file for the baseboard (tqma6_
mba6).

The modules can be boot from eMMC (on USDHC3) and SPI flash.

The following features are supported:
- MMC: eMMC on module (on USDHC3) and SD-card (on MBa6x mainboard)
- Ethernet: RGMII using micrel KSZ9031 phy on MBa6x mainboard for TQMa6<x> module.
  The phy needs special configurations for the pad skew registers to adjust for
  the signal routing.
  Also support for standard ethernet commands and uppdate via tftp.
- SPI: ECSPI1 with bootable serial flash on module and two additional
  chip selects on MBa6x
- I2C: This patch adds support for the I2C busses on the TQMa6<x> modules (I2C3)
  and MBa6x baseboards (I2C1). The LM75 temperature sensors on TQMa6<x> and MBa6x
  are also configured.
- USB: high speed host 1 on MBa6x and support for USB storage
- PMIC: support for pfuze 100 on TQMa6<x>

Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com>
2014-07-23 12:31:42 +02:00
Heiko Schocher
e379c03902 arm, imx6: add aristainetos board
CPU:   Freescale i.MX6DL rev1.1 at 792 MHz
Board: aristaitenos
I2C:   ready
DRAM:  1 GiB
NAND:  512 MiB
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
SF: Detected N25Q128 with page size 256 Bytes, erase size 64 KiB, total 16 MiB
Display: lb07wv8 (800x480)

- UART5 is console
- MMC 0 and 1
- USB 0 and 1
- boot from mmc0 and spi nor flash
- Splash screen support

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2014-07-23 12:31:34 +02:00
Heiko Schocher
562f8df18d spi: add config option to enable the WP pin function on st micron flashes
enable the W#/Vpp signal to disable writing to the status
register on ST MICRON flashes like the N25Q128 thorugh
the new config option CONFIG_SYS_SPI_ST_ENABLE_WP_PIN

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-07-23 12:26:45 +02:00
Heiko Schocher
a0ae0091d7 i.MX6: add enable_spi_clk()
add enable_spi_clk(), so board code can enable spi clocks.

Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Stefano Babic <sbabic@denx.de>
2014-07-23 12:25:42 +02:00
Heiko Schocher
b2f97cf279 pwm, imx6: add support for pwm modul on imx6
add basic support for the pwm modul found on imx6.
Pieces of this code are based on linux code from drivers/pwm/pwm-imx.c
Commit "cd3de83f1476 Linux 3.16-rc4"

Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
2014-07-23 12:25:42 +02:00
Heiko Schocher
aafe4020c1 i.MX6: define struct pwm_regs and PWMCR_* defines
add defines for pwm modul found on imx6.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2014-07-23 12:25:41 +02:00
Heiko Schocher
4a4d3a7db7 imx6: add gpr2 usb_otg_id iomux select control define
add IOMUXC_GPR1_USB_OTG_ID_OFFSET and IOMUXC_GPR1_USB_OTG_ID_SEL_MASK
define for the USB_OTG_ID_SEL bit.

Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2014-07-23 12:25:41 +02:00
Marek Vasut
d726d5f926 arm: mxs: Scrub useless ifdef
As a result of 0defddc851 , which did
a consolidation of the prompt string, this ifdef became empty. Remove
it.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Stefano Babic <sbabic@denx.de>
2014-07-23 12:25:41 +02:00
Fabio Estevam
aeadf0655c mx6: Adjust the GPR offset for mx6solox
On mx6solox there is an additional 0x4000 offset for the GPR registers.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2014-07-23 12:25:41 +02:00
Fabio Estevam
0a11d6f29c mx6: Remove duplication of iomuxc structure
There is no need to keep iomuxc_base_regs structure as it serves the exact same
purpose of the iomuxc structure, which is to provide access to the GPR
registers.

The additional fields of iomuxc_base_regs are not used. Other advantage of
'iomuxc' is that it has a shorter name and the variable declarations can fit
into a single line.

So remove iomuxc_base_regs structure and use iomuxc instead.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2014-07-23 12:25:41 +02:00
Fabio Estevam
fa8cf3176c mx6sxsabresd: Add PFUZE100 PMIC support
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-07-23 12:25:40 +02:00
Fabio Estevam
a3df99b50f mx6: soc: Do not apply the PFD erratum for mx6solox
The PFD issue is not present on mx6solox, so skip it in this case.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-07-23 12:25:40 +02:00
Iain Paton
6ed9c7bbba embestmx6boards: convert to generic board
Enable CONFIG_SYS_GENERIC_BOARD to remove warning on boot.

Signed-off-by: Iain Paton <ipaton0@gmail.com>
2014-07-23 12:25:40 +02:00
Shengzhou Liu
b0d97cd2ed powerpc/t1040: update i2c for t1040qds and t104xrdb
- Fix base address of I2C2 as 0x118100 instead of 0x119000.
- Add definitions for I2C3 & I2C4.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:55 -07:00
Tang Yuantian
7cb7272365 mpc85xx/t104x: Enable L2 and CPC cache when resume
When resume from deep sleep, uboot needs to enable L2 and CPC
cache, or they would be keeping unusable in kernel because
kernel didn't enble or initialized them.
This patch didn't change the existing L2 cache enabling code,
just put them in a function.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:55 -07:00
Shaveta Leekha
a1399a9187 powerpc/chassis2: Configure and enable L2 cache for PPC clusters only
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:55 -07:00
Shaohui Xie
e55782eccc powerpc/t4240qds: fix offset of serdes when checking reference clock
T4240 has 4 serdes, each serdes has 4k memory space, two PLLs.
We use PLL1CR0 to check the serdes reference clock.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:55 -07:00
York Sun
3d75ec95f5 driver/ddr: Fix DDR register timing_cfg_8
The field wrtord_bg should add 2 clocks if on the fly chop is enabled,
according to DDR controller manual for DDR4.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:55 -07:00
Shaohui Xie
de51916310 powerpc/ifc: fix invalid CSn FTIM2.TCH setting
On some platforms, CSn FTIM2.TCH is set to zero which is invalid,
an invalid hold time makes DUT timing variances, whether it works
or not on luck.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:55 -07:00
York Sun
9d0456822c powerpc/mpc85xx: Check return value of find_tlb_idx
find_tlb_idx() is called in board_early_init_r() on multiple boards.
The return value is not checked before being used to disable a TLB.
In normal case the return value wouldn't be -1. In case of a mis-
configuration during porting to a new board, checking the return value
may be helpful to reveal some user errors.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:54 -07:00
York Sun
8340e7ac86 driver/ddr: Fix DDR4 driver for ARM
Previously the driver was only tested on Power SoCs. Different barrier
instructions are needed for ARM SoCs.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:54 -07:00
vijay rai
6666017f44 powerpc/t1040qds: Initialize EPHY2 clock to RGMII only
Setting FPGA register brdcfg9 EPHY2 bits to '0' to initialize EPHY2 clock to RGMII mode.

Signed-off-by: Vijay Rai <vijay.rai@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:54 -07:00
Prabhakar Kushwaha
591dd19230 driver/nand: Add support of 16K SRAM for IFC 2.0
Internal SRAM has been incresed from 8KB to 16KB for IFC cotroller ver 2.0.

Update the page offset calculation logic to support the same.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:54 -07:00
Zang Roy-R61911
32514d259b fsl/pcie: Change 'no link' to 'undetermined' for pcie endpoint
Even u-boot boots up, the pcie link may not setup correctly when
Freescale SOC acts as endpoint.
So change the link status from 'no link' to 'undetermined' to
reduce the confusion.
The link status can check from host side eventually.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:54 -07:00
Prabhakar Kushwaha
04818bbdc3 driver/nand: Update SRAM initialize logic for IFC.
IFC controller v1.1.0 requires internal SRAM initialize by reading
NAND flash. Higher controller versions have provided "SRAM init" bit in
NCFGR register space.

update SRAM initialize logic to reflect the same.

Also print error message in case of Page read error.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:54 -07:00
Prabhakar Kushwaha
3bab3d8324 driver/nand:Define MAX_BANKS same as SoC defined for IFC
The number of chip select used by IFC controller vary from one SoC to other.
For eg. P1010 has 4, T4240 has 8.

Update MAX_BANKS same as SoC defined

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:54 -07:00
Lijun Pan
d0bc51407c powerpc/mpc85xx: Remove P1023 RDS support
Since P1023RDS is no longer supported/manufactured by Freescale,
we clean up P1023RDS related code.
Since P1023RDB is still supported by Freescale,
we keep P1023RDB releated code.

Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:54 -07:00
Sandeep Singh
d43a386a91 powerpc/mpc85xx: Removed support for G4060
G4060 has no PA cores, hence removing its support.

Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:54 -07:00
Zhao Qiang
38d67a4e55 qe: move immap_qe.h from arch directory into common directory
ls1021 is arm-core and supports qe too.
Move immap_qe.h into common directory for both arm and powerpc.

Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:54 -07:00
Shengzhou Liu
09c2046ff6 board/t2080qds: enable sst and eon spi flash for nor boot
Remove unnecessary condition CONFIG_RAMBOOT_PBL to
have SST and EON SPI flash work in case of NOR boot.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:54 -07:00
Rotariu Marian-Cristian
1155d8d853 net/fm: call fm_port_to_index() with proper checks
Some of the fm_port_to_index() callers did not check for -1 return value and
used -1 as an array index.

Signed-off-by: Marian Rotariu <marian.rotariu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:53 -07:00
Shengzhou Liu
605714f669 powerpc/85xx: add fdt_fixup_dma3
On some SoC(e.g. T2080/T4240) the 3rd DMA is not functional if SRIO2 is
chosen. we add fdt_fixup_dma3() to disable the 3rd DMA if SRIO2 is chosen.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:53 -07:00
Masahiro Yamada
fbe79a17fd m68k: define __kernel_size_t as unsinged int again
Commit ddc94378d changed the definition of __kernel_size_t
from unsigned int to unsigned long.

It is true that it fixed warnings on some crosstools
but it increased warnings on the others.

The problem is that we cannot see consistency in terms of
the typedef of __kernel_size_t on M68K architecture.

However, I'd like to suggest to have __kernel_size_t to be
unsigned int again.

Rationale:

[1] Linux Kernel defines __kernel_size_t on M68K as unsigned int.
    Let's stick to the Linux's way.

[2] We want to build boards with popular pre-built toolchains,
    not the one locally-built by indivisuals.
    I think m68-linux-gcc which can be downloaded from www.kernel.org
    is the candidate for our _recommended_ toolchains.

With this patch, all the m68k boards can be built without any warnings.

Give it a try with the following crosstools:

https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.6.3/
x86_64-gcc-4.6.3-nolibc_m68k-linux.tar.xz

or

https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.9.0/
x86_64-gcc-4.9.0-nolibc_m68k-linux.tar.xz

(The latter is newer.)

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Jason Jin <Jason.jin@freescale.com>
2014-07-22 09:46:50 -04:00
Masahiro Yamada
61f06b143e m68k: fix an undefined behavior warning of M5253DEMO board
The latest GCC is so clever that it reports more warnings
than old ones did:

 ------------------------------>8------------------------------

  board/freescale/m5253demo/flash.c: In function 'flash_get_offsets':
  board/freescale/m5253demo/flash.c:65:23: warning: iteration 2047u
  invokes undefined behavior [-Waggressive-loop-optimizations]
      info->start[k + 1] = info->start[k] + CONFIG_SYS_SST_SECTSZ;
                         ^
  board/freescale/m5253demo/flash.c:64:3: note: containing loop
     for (k = 0, j = 0; j < CONFIG_SYS_SST_SECT; j++, k++) {
     ^

 ------------------------------8<------------------------------

The cause of the warning is like this:

The for statement iterates 2048 times in flash_get_offsets() func.
(Notice CONFIG_SYS_SST_SECT is defined as 2048)

The last iteration does
  info->start[2048] = info->start[2047] + CONFIG_SYS_SST_SECTSZ;
causing an undefined behavior.

(Please note the array size of info->start is 2048.
CONFIG_SYS_MAX_FLASH_SECT is defined as 2048 for this board.)

This commit fixes that so as not to overrun the info->start array.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Jason Jin <Jason.jin@freescale.com>
2014-07-22 09:46:48 -04:00
Wolfgang Denk
e8078046b4 boards.cfg: re-claim ownership for TQM8xx boards
Signed-off-by: Wolfgang Denk <wd@denx.de>
2014-07-22 09:25:56 -04:00
Pavel Machek
75d9a45cb0 Ethernet: let user know if there is no valid ethernet address
Improve error messages in case of invalid/unset ethernet addresses.

Signed-off-by: Pavel Machek <pavel@denx.de>
2014-07-22 07:44:28 -04:00
Ian Campbell
2c997e7a8f board_r: run scsi init() on ARM too
This has been disabled for ARM in initr_scsi since that function was
introduced. However it works fine for me on Cubieboard and Cubietruck (with the
upcoming AHCI glue patch).

I also tested on two random ARM platforms which seem to define CONFIG_CMD_SCSI:
 - highbank worked fine (on midway hardware)
 - omap5_uevm built OK and I confirmed using objdump that things were as
   expected (i.e. the default weak scsi_init nop was used).

While there remove the mismatched comment from the #endif (omitting the comment
seems to be the prevailing style in this file).

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Simon Glass <sjg@chromium.org>
2014-07-22 07:44:28 -04:00
Ian Campbell
e0ddcf93b9 AHCI: Increase link timeout to 200ms
In 73545f75b6 "ahci: wait longer for link" I increased the
timeout to 40ms based on the observed behaviour of a WD disk on a
Cubietruck. Since then Karsten Merker and myself have both
observed timeouts with HGST disks (Karsten on Cubietruck, me on
Cubieboard2). Increasing the timeout to ~175ms fixes this, so go
to 200ms for a bit of headroom.

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Cc: Karsten Merker <merker@debian.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2014-07-22 07:44:28 -04:00
Masahiro Yamada
f63e36adf4 .gitignore: clean-up unnecessary entries
There have been /errlog and /reloc_off in the top level .gitignore
since commit 1b4aaffe added it about 7 years ago.

But they are no longer generated.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-07-22 07:44:27 -04:00
Masahiro Yamada
e89a07e363 Update .mailmap using scripts/mailmapper
Add more entries to .mailmap for the canonical names with
50 commits or more.

This commit was generated by the following command:

  scripts/mailmapper > tmp; mv tmp .mailmap

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-07-22 07:44:27 -04:00
Masahiro Yamada
45765eeda2 scripts: add mailmapper, a tool to create/update mailmap file
This tool helps to create/update the mailmap file.

It runs 'git shortlog' internally and searches differently spelled author
names which share the same email address. The author name with the most
commits is asuumed to be a canonical real name. If the number of commits
from the cananonical name is equal to or greater than 'MIN_COMMITS' (=50),
the entry for the cananical name will be output. ('MIN_COMMITS' is used
here because we do not want to create a fat mailmap by adding every author
with only a few commits.)

If there exists a mailmap file specified by the mailmap.file configuration
options or '.mailmap' at the toplevel of the repository, it is used as
a base file.

The base file and the newly added entries are merged together and sorted
alphabetically (but the comment block is kept untouched), and then printed
to standard output.

 Usage
 -----

  scripts/mailmapper

prints the mailmapping to standard output.

  scripts/mailmapper > tmp; mv tmp .mailmap

will be useful for updating '.mailmap' file.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-07-22 07:44:27 -04:00
Masahiro Yamada
8b90a11f7c add .mailmap for proper git-shortlog output
This is the first version of .mailmap created by hand.
Please see "man git-shortlog" for what this commit is trying to do.

Without this file, for example, "git shortlog -n -s" shows as follows:

  2693  Wolfgang Denk     <------
  1002  Stefan Roese      <------
   811  wdenk             <------
   808  Mike Frysinger
   806  Simon Glass
     [snip]
   177  Matthias Fuchs
   154  stroese           <------
   153  Timur Tabi

And then, with this file, it shows as follows:

  3504  Wolfgang Denk     <------
  1156  Stefan Roese      <------
   808  Mike Frysinger
   806  Simon Glass

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
2014-07-22 07:44:27 -04:00
Pavel Machek
3f9eb6e109 whitespace cleanups
Whitespace cleanups.

Signed-off-by: Pavel Machek <pavel@denx.de>
2014-07-22 07:44:27 -04:00
Igor Grinberg
5fc2f924dc Makefile: fix tags target documentation
Replace the TAGS target name by the actual ctags target name.
Also, add etags target documentation.

Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
2014-07-22 07:44:27 -04:00
Igor Grinberg
b3dfe43c6c Makefile: fix ctags/etags clean targets
Commit efcf861 (kbuild: use scripts/Makefile.clean)
refactored the cleaning targets and accidentially replaced the actually
generated "ctags" and "etags" files in the file list by "tags" and "TAGS".
"tags" and "TAGS" are not part of the Makefile build targets and
therefore should not be a part of the list for clean targets.

Substitute the actually generated files instead, to fix the clean
targets behavior.

Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
2014-07-22 07:44:27 -04:00
Igor Grinberg
8d819ab5e1 Makefile: fix the {c, e}tags/cscope build targets
Commit 9e41403 (kbuild: change out-of-tree build)
changed the U-Boot build working directory to the output tree
for the out-of-tree builds.
This broke the {c,e}tags/cscope build targets as TAG_SUBDIRS variable
collected directories based on assumption that the build working
directory is the U-Boot source tree directory.

Fix the {c,e}tags/cscope build targets by adding the $(srctree) prefix.
Also, remove the $(obj) prefix from the etags build target to finish
the $(obj) prefix removal started by the same commit.

Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
2014-07-22 07:44:27 -04:00
Alexander Holler
11547b2992 rpi_b: handle import of environments in files with CRLF as line endings
Use the new option -r for env import.

Signed-off-by: Alexander Holler <holler@ahsoftware.de>
2014-07-22 07:44:26 -04:00
Alexander Holler
4cfe8c3edd am335x_evm: handle import of environments in files with CRLF as line endings
Use the new option -r for env import.

Signed-off-by: Alexander Holler <holler@ahsoftware.de>
2014-07-22 07:44:26 -04:00
Alexander Holler
44bd26fa99 omap3_beagle: handle import of environments in files with CRLF as line endings
Use the new option -r for env import.

Signed-off-by: Alexander Holler <holler@ahsoftware.de>
2014-07-22 07:44:26 -04:00
Alexander Holler
ecd1446fe1 Add option -r to env import to allow import of text files with CRLF as line endings
When this option is enabled, CRLF is treated like LF when importing environments
from text files, which means CRs ('\r') in front of LFs ('\n') are just ignored.

Drawback of enabling this option is that (maybe exported) variables which have
a trailing CR in their content will get imported without that CR. But this
drawback is very unlikely and the big advantage of letting Windows user create
a *working* uEnv.txt too is likely more welcome.

Signed-off-by: Alexander Holler <holler@ahsoftware.de>
2014-07-22 07:44:26 -04:00
Tom Rini
8973601c38 h2200: Disable SHA256 on FIT images
This board is close in binary size to one of its hard limits, so disable
SHA256 FIT image support to gain some breathing room.

Signed-off-by: Tom Rini <trini@ti.com>
2014-07-22 07:44:26 -04:00
Pavel Machek
fccacd3b4c lib/time.c cleanups
As I initially suspected overflow in time handling, I took a detailed
look at lib/time.c. This adds comments about units being used, reduces
amount of type casting being done, and makes __udelay() always wait at
least one tick. (Current code could do no delaying at all for short
delays).

Signed-off-by: Pavel Machek <pavel@denx.de>
2014-07-22 07:44:26 -04:00
Jeroen Hofstee
288afdc9b9 common: cmd_ide: use __weak and add prototypes
clang chokes about the concept of having an alias to an
always_inlined function. gcc likely just ignores the always
inlined since binary sizes are equal before and after this
patch. Convert the aliases to weak functions and provide
missing prototypes.

cc: Pavel Herrmann <morpheus.ibis@gmail.com>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-07-22 07:44:26 -04:00
Jeroen Hofstee
2bb8eb8ec6 common: cmd_ide: remove PIO mode
Since no board defines CONFIG_TUNE_PIO this is just dead
code, so remove it.

cc: Pavel Herrmann <morpheus.ibis@gmail.com>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-07-22 07:44:26 -04:00
Masahiro Yamada
5b9587ae31 serial: ns16550: use a const variable instead of macro
Just for type checking.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
2014-07-22 07:44:25 -04:00
Masahiro Yamada
f8c7c2033d serial: ns16550: use DIV_ROUND_CLOSEST macro to compute the divisor
The function still returns the same value.

The comment block is no longer necessary because our intention is
clear enough by using DIV_ROUND_CLOSEST() macro.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-07-22 07:44:25 -04:00
Masahiro Yamada
841977df21 serial: ns16550: drop CONFIG_OMAP1610 from the special case
If CONFIG_OMAP1610 is defined, the code returning the fixed value (26)
is enabled. But this case is covered by the following code.

(CONFIG_SYS_NS16550_CLK + (gd->baudrate * (MODE_X_DIV / 2))) /
    (MODE_X_DIV * gd->baudrate)
= (48000000 + (115200 * (16 / 2))) / (16 * 115200)
= 48921600 / 1843200
= 26

The "#ifdef CONFIG_OMAP1610" was added by commit 6f21347d more than
ten years ago. In those days, the divide-and-round was not used.
I guess that is why this weird code was added here.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
Cc: Rishi Bhattacharya <rishi@ti.com>
2014-07-22 07:44:25 -04:00
Pavel Machek
8e8d73b4a5 bootp can use mdelay
Cleanup bootp code by using mdelay.

Signed-off-by: Pavel Machek <pavel@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
2014-07-22 07:44:25 -04:00
Masahiro Yamada
c13bb16757 spl: nand: read only in the size of image_header on the first access
For the same reason as in commit 50c8d66d, all the remaining
CONFIG_SYS_NAND_PAGE_SIZE in common/spl/spl_nand.c can be replaced
with sizeof(*header).

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2014-07-22 07:44:25 -04:00
Pavel Machek
949bbd7c86 catch wrong load address passed to fatload / ext2load
If filename is passed instead of address to ext2load or fatload,
u-boot silently accepts that, and uses 0 for load address and default
filename from environment. That is confusing, display help instead.

Signed-off-by: Pavel Machek <pavel@denx.de>
2014-07-22 07:44:25 -04:00
Pavel Machek
6b367467f1 Fix help text of ext2load and fatload.
Fix help text of ext2load and fatload to match code in fs/fs.c

Signed-off-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
2014-07-22 07:44:25 -04:00
Jeroen Hofstee
9d16e93dc2 tools: compiler.h: add missing time.h
genimg_print_time uses time_t, but time.h is never included.
Linux gets away with this since types.h includes time.h.
Explicitly include the header file so building on e.g. FreeBSD
also works.

cc: Tom Rini <trini@ti.com>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-07-22 07:44:25 -04:00
Lijun Pan
4a755f1da5 driver/usb: include upper/lower_32_bits() from linux/compat.h
upper_32_bits() and lower_32_bits() have been ported into linux/compat.h.
Start use them now in drivers/usb/host/xhci.h.

Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com>
2014-07-22 07:44:24 -04:00
Lijun Pan
8f2df5d369 linux/compat.h: port lower_32_bits and upper_32_bits from Linux
[backport from linux commit 204b885e and 218e180e7]
64 bit processors are becomming more and more popular.
lower_32_bits and upper_32_bits save our labor doing
shifts/manipulations like (u32)(n) and (u32)((n) >> 32).
They are good helpers in both little and big endian cases.
Port these two functions here from Linux:include/linux/kernel.h,
cater the comment message to little/big endian cases.
Later on, developers could include linux/compat.h if they want to
use these two functions.

Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com>
2014-07-22 07:44:24 -04:00
Masahiro Yamada
9d78b9ae8d sparc: merge LEON2 and LEON3 linker scripts
There is only one line diff between LEON2 and LEON3 linker scripts:

  -             arch/sparc/cpu/leon2/start.o (.text)
  +             arch/sparc/cpu/leon3/start.o (.text)

They can be written in the same way:

                */start.o (.text)

So, board/gaisler/grsim_leon2/u-boot.lds
and arch/sparc/cpu/leon3/u-boot.lds
can be merged into arch/sparc/cpu/u-boot.lds.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Daniel Hellstrom <daniel@gaisler.com>
2014-07-22 07:44:24 -04:00
Masahiro Yamada
9f847b8201 sparc: merge LEON3 linker scripts
The linker scripts of LEON3

 - board/gaisler/grsim/u-boot.lds
 - board/gaisler/gr_cpci_ax2000/u-boot.lds
 - board/gaisler/gr_ep2s60/u-boot.lds
 - board/gaisler/gr_xc3s_1500/u-boot.lds

are the same (except cosmetic differences such as indentation).

This commit merges them into arch/sparc/cpu/leon3/u-boot.lds.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Daniel Hellstrom <daniel@gaisler.com>
2014-07-22 07:44:24 -04:00
Tom Rini
ec4f5040f7 esd:cmd_loadpci.c: Switch from "do_source" to "source"
Rather than calling do_source directly (which is not officially exported
from cmd_source.c) call 'source' which is exported and requires a little
less code to do so as well.

Signed-off-by: Tom Rini <trini@ti.com>
2014-07-22 07:44:24 -04:00
Tom Rini
3364b1898c Merge branch 'master' of git://git.denx.de/u-boot-i2c 2014-07-21 11:04:10 -04:00
Jeroen Hofstee
c68112f3f5 common: cmd_mii: fix printf format warning
The and operator implicitly upcasts the value to
int, hence the format should expect an int type
as well. (and make checkpatch happy)

Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-07-18 17:53:24 -04:00
Jeroen Hofstee
39e1230ed0 autoboot: add its own header
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-07-18 17:53:24 -04:00
Jeroen Hofstee
5dfd162eea board: rpi_b: include mmc header and fix prototype
While at it add fdt_support.h as well.

cc: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-07-18 17:53:24 -04:00
Jeroen Hofstee
750121c350 mmc: prevent some warnings with make W=1
Add missing prototypes for global functions and
make local functions static.

cc: panto@antoniou-consulting.com
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-07-18 17:53:24 -04:00
Jeroen Hofstee
0b7df65657 common: env_common: make env_get_char_spec __weak
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-07-18 17:53:24 -04:00
Jeroen Hofstee
862c93e96e yaffs2: preprocessor cleanup
Current code uses the preprocessor to change an else case
to a statement without any if condition at all. Although
this works, change the optional code to return early, so
all optional code is contained within a single #ifdef.

Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-07-18 17:53:23 -04:00
Jeroen Hofstee
e803fa2c4b yaffs2: cosmetic: remove self assignments
Remove self assignments which is just dead code to prevent
compiler warnings about non used arguments. For u-boot this
does not prevent any warning though, on the contrary it actual
introduces warnings when compiling with clang. Remove them.

Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-07-18 17:53:23 -04:00
Jeroen Hofstee
82c3a4c445 common: bootm_os: make arch_preboot_os __weak
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-07-18 17:53:23 -04:00
Jeroen Hofstee
cee9ab7cb6 dirvers: mmc: use __weak
use weak instead of alias to prevent some clang warnings.
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-07-18 17:53:23 -04:00
Jeroen Hofstee
d7b2d9df02 lib:vsprintf: reduce scope of pack_hex_byte
pack_hex_byte is only used when CONFIG_CMD_NET is
defined so limit it to that scope. This prevents
a clang warning.

Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-07-18 17:53:23 -04:00
Jeroen Hofstee
3ea664c7c3 env_callback.h: spl: mark callback as maybe_unused
When static inline is used in a header file the function
should preferably be inlined and if not possible made a
static function. When declared inside a c file there is a
static function, which might be inlined. Since SPL uses a
define to declare the static inline it becomes part of the
c file although it is declared in a header and clang will
warn that you have introduced unused static functions. Add
maybe_unused to prevent such warnings.

Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-07-18 17:53:23 -04:00
Jeroen Hofstee
6b13f0c050 lib:sha1: remove unused constant
This prevents a clang warning.
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-07-18 17:53:23 -04:00
Jeroen Hofstee
3422299dc2 common: main.c: make show_boot_progress __weak
This not only looks a bit better it also prevents a
warning with W=1 (no previous prototype).

Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Acked-by: Simon Glass <sjg@chromium.org>
2014-07-18 17:53:23 -04:00
Jeroen Hofstee
2c34f3f547 lib:lmb: use __weak
This not only looks a bit better it also prevents a
warning with W=1 (no previous prototype).

Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-07-18 17:53:23 -04:00
Jeroen Hofstee
cc64b92cde common:splash: use __weak
This not only looks a bit better it also prevents a
warning with W=1 (no previous prototype).

cc: agust@denx.de
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-07-18 17:53:23 -04:00
Jeroen Hofstee
fd536d818d dm: add missing includes
lists.c / root.c do not include their own header and they
could potentially implement a different function. Therefore
actually include the headers.

cc: sjg@chromium.org
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Acked-by: Simon Glass <sjg@chromium.org>
2014-07-18 17:53:23 -04:00
Jeroen Hofstee
c5d4001a1c common: board_f: cosmetic use __weak for leds
First of all this looks a lot better, but it also
prevents a gcc warning (W=1), that the weak function
has no previous prototype.

cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Acked-by: Simon Glass <sjg@chromium.org>
2014-07-18 17:53:23 -04:00
Jeroen Hofstee
0e350f81e1 common: commands: make commands static
Since most commands are not public, make them static. This
prevents warnings that no common prototype is available.

Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-07-18 17:53:23 -04:00
Jeroen Hofstee
e259d6a320 lib: div64: add missing include
Include the function its prototype to prevent the warning
that it has no prototype.

Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-07-18 17:53:22 -04:00
Jeroen Hofstee
c15df21fe7 mtd: cfi_flash: fix clang warning
clang warns this check is silly; it is since s is
a local variable.

u-boot/drivers/mtd/cfi_flash.c:2363:13: warning: comparison of
  array 's' not equal to a null pointer is always true
  else if ((s != NULL) && (strcmp(s, "yes") == 0)) {

cc: Stefan Roese <sr@denx.de>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-07-18 17:53:22 -04:00
Ian Campbell
7c48b01510 sunxi: use setbits_le32 to enable the DMA clock
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2014-07-18 19:42:25 +01:00
Ian Campbell
abce2c6220 sunxi: add gpio driver
This patch enables CONFIG_CMD_GPIO for the Allwinner (sunxi) platform as well
as providing the common gpio API (gpio_request/free, direction in/out, get/set
etc).

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Ma Haijun <mahaijuns@gmail.com>
Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Cc: Henrik Nordström <henrik@henriknordstrom.net>
Cc: Tom Cubie <Mr.hipboi@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2014-07-18 19:42:25 +01:00
Ian Campbell
5c58f8b685 sunxi: add Cubieboard2 support
This is a sun7i (A20) based followup to the sun4i (A10)
Cubieboard. It has GMAC using MII mode.

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2014-07-18 19:42:23 +01:00
Jonathan Liu
b41d7d05b7 sunxi: use random parts of SID to set ethaddr
Similar to the USB NIC found on OMAP5uEVM, PandaBoard and BeagleBoard-XM
boards, the sunxi SoCs have a NIC onboard without an embedded MAC address.

Just like the omap used on these boards, the sunxi SoCs do have a unique chip
id, in the form of the 128 bit SID register:
http://linux-sunxi.org/SID_Register_Guide

So mimick the BeagleBoard-XM board code (commit 548a64d8) and use the chip id
to generate a unique fixed MAC address.

We check for the SID not being all 0, since some early A20 batches
shipped without having there SID programmed.

Note we use specific parts of the 128 bits, since some parts indicate the
SoC family / revision, and thus are fixed. The algorithm for this was taken
from the linux-sunxi.org kernels.

Signed-off-by: Jonathan Liu <net147@gmail.com>
[hdegoede@redhat.com: Expanded the commit message with some more info]
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-18 19:42:22 +01:00
Hans de Goede
ae5de5a19d sunxi: Fix reset hang on sun5i
Do the same as the Linux kernel does, this fixes the SoC hanging on reset
about 50% of the time.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-18 19:42:22 +01:00
Hans de Goede
2428920835 sunxi: Add axp152 pmic support
Add support for the x-powers axp152 pmic which is found on most A10s boards
and enable it for the r7-tv-dongle board.

Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-18 19:42:16 +01:00
Henrik Nordstrom
14bc66bd9a sunxi: Add axp209 pmic support
Add support for the x-powers axp209 pmic which is found on most A10, A13 and
A20 boards.

And enable AXP209 support for the Cubietruck and Cubieboard boards.

Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-18 19:42:10 +01:00
Hans de Goede
6620377e4b sunxi: Add i2c support
Add support for the i2c controller found on all Allwinner sunxi SoCs,
this is the same controller as found on the Marvell orion5x and kirkwood
SoC families, with a slightly different register layout, so this patch uses
the existing mvtwsi code.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-By: Prafulla Wadaskar <prafulla@marvell.com>
Acked-by: Heiko Schocher <hs@denx.de>
[ ijc -- updated u-boot-spl-fel.lds ]
2014-07-18 19:41:30 +01:00
Hans de Goede
0db2bbdc04 mvtwsi: convert to CONFIG_SYS_I2C framework
Note this has only been tested on Allwinner sunxi devices (support for which
gets introduced by a later patch).

The kirkwood changes have been compile tested using the wireless_space board
config, the orion5x changes have been compile tested using the edminiv2 board
config.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Heiko Schocher <hs@denx.de>
2014-07-16 19:56:24 +01:00
Stefano Babic
dab5e3469d Merge branch 'master' of git://git.denx.de/u-boot
Signed-off-by: Stefano Babic <sbabic@denx.de>

Conflicts:
	boards.cfg
2014-07-16 08:51:30 +02:00
Shengzhou Liu
a17fd10fb5 fsl_i2c: add support for 3rd and 4th I2C
Add support for 3rd and 4th I2C.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
2014-07-16 05:19:15 +02:00
Heiko Schocher
f7c1053535 i2c, omap24xx: add i2c deblock sequenz
If a bus busy is detected when intializing the driver,
toggle 9 times the scl pin. Therefore enable the test mode
of the controller, in which the scl, sda pins can be
controlled manually.

Tested on the siemens boards pxm2, rut and dxr2.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Hannes Petermaier <oe5hpm@oevsv.at>
Cc: Lubomir Popov <lpopov@mm-sol.com>
Cc: Steve Sakoman <steve@sakoman.com>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Vincent Stehlé <v-stehle@ti.com>
Cc: Samuel Egli <samuel.egli@siemens.com>
2014-07-16 05:18:55 +02:00
Fabio Estevam
14a1613140 mx6sx: Add initial support for mx6sxsabresd board
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-07-10 15:29:16 +02:00
Fabio Estevam
d95b6ab87c mx6: clock: Do not enable sata and ipu clocks
mx6sx does not have sata nor ipu blocks, so do not handle such clocks.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-07-10 15:29:16 +02:00
Fabio Estevam
f586040451 mx6sx: Add pin definitions
Add the pin definitions for mx6sx.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-07-10 15:29:16 +02:00
Fabio Estevam
05d54b827f mx6: Add support for the mx6solox variant
mx6solox is the newest member of the mx6 family.

Some of the new features on this variants are:
- Cortex M4 microcontroller (besides the CortexA9)
- Dual Gigabit Ethernet

Add the initial support for it.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-07-10 15:29:16 +02:00
Ian Campbell
799aff38df sunxi: Avoid unused variable warning.
Mark rc as __maybe_unused since it is infact unused on systems with neither
EMAC nor GMAC.

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Tom Rini <trini@ti.com>
2014-07-08 07:45:06 +01:00
Hans de Goede
db53073037 sunxi: Add Ian Campbell and Hans de Goede as cubietruck board-maintainers
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-06 20:12:45 +01:00
Chen-Yu Tsai
ef7e723ba1 sunxi: Add support for using MII phy-s with the GMAC nic
Many A20 boards (ie Cubieboard2, A20-OLinuXino_MICRO) use an 100 Mbit MII
phy together with the GMAC nic found in the A20 SoC, add support for this
(this will get used when we add these boards in a later patch).

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-06 20:12:45 +01:00
Hans de Goede
c26fb9db0e sunxi: Add emac glue, enable emac on the cubieboard
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-06 20:12:45 +01:00
Stefan Roese
b70ed300b0 net: Rename and cleanup sunxi (Allwinner) emac driver
There have been 3 versions of the sunxi_emac support patch during its
development. Somehow version 2 ended up in upstream u-boot where as
the u-boot-sunxi git repo got version 3.

This bumps the version in upstream u-boot to version 3 of the patch:
- Initialize MII clock earlier so mii access to allow independent use
- Name change from WEMAC to EMAC to match mainline kernel & chip manual
- Cosmetic code cleanup

Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>
Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-06 20:12:44 +01:00
Hans de Goede
f84269c5c0 sunxi: Add sun5i support
Add support for the Allwinner A13 and A10s SoCs also know as the Allwinner
sun5i family, and the A13-OLinuXinoM A13 based and r7-tv-dongle A10s based
boards.

The only differences compared to the already supported sun4i and sun7i
families are all in the DRAM controller initialization:

-Different hcpr values
-Different MBUS settings
-Some other small initialization changes

Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-06 20:12:44 +01:00
Hans de Goede
745325a97d sunxi: Add sun4i support
Add support for the Allwinner A10 SoC also known as the Allwinner sun4i family,
and add the Cubieboard board which uses the A10 SoC.

Compared to sun7 only the DRAM controller is a bit different:
-Controller reset bits are inverted, but only for Rev. A
-Different hpcr values
-No MBUS on sun4i
-Various other initialization changes

Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-06 20:12:44 +01:00
Hans de Goede
c7e79dec85 sunxi: Implement reset_cpu
There is no way to reset the cpu, so use the watchdog for this.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-06 20:12:44 +01:00
Hans de Goede
b6ae6765c5 sunxi: Remove mmc DMA support
The DMA code in sunxi_mmc.c is broken. mmc_trans_data_by_dma() allocates the
dma descriptors on the stack, and then exits while the dma transfer is in
progress, so the dma engine is reading stack memory which at that point may
be re-used. So far we've gotten away with this by luck, but recent u-boot
changes have shifted the stack start address by 16 bytes, which combined
with dma alignment now exposes this problem.

Since we end up just busy waiting for the dma engine anyway, this commit
fixes things by simply removing the dma code, resulting in smaller bug-free
code.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-06 20:12:44 +01:00
Hans de Goede
9e5f80d823 sunxi: Fix u-boot-spl.lds to refer to .vectors
Adjust the u-boot-spl.lds linker script to match the changes made in the
41623c91b0 "arm: move exception handling out
of start.S files" commit.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-06 17:41:13 +01:00
Hans de Goede
4ba73a5ac7 sunxi: mksunxiboot: Fix loading of files with a size which is not a multiple of 4
We should not be aligning the amount of bytes which we try to read from the
disk, this leads to trying to read more bytes then there are which fails.

file_size is already aligned to BLOCK_SIZE before being stored in
img.header.length, so there is no need for load_size at all.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-06 17:41:13 +01:00
3395 changed files with 106039 additions and 33550 deletions

7
.gitignore vendored
View File

@@ -34,6 +34,7 @@
/SPL
/System.map
/u-boot*
/boards.cfg
#
# git files that we don't want to ignore even it they are dot-files
@@ -44,11 +45,7 @@
#
# Generated files
#
/LOG
/errlog
/reloc_off
/spl/
/tpl/
@@ -57,8 +54,6 @@
#
/include/config/
/include/generated/
/include/spl-autoconf.mk
/include/tpl-autoconf.mk
# stgit generated dirs
patches-*

27
.mailmap Normal file
View File

@@ -0,0 +1,27 @@
#
# This list is used by git-shortlog to fix a few botched name translations
# in the git archive, either because the author's full name was messed up
# and/or not always written the same way, making contributions from the
# same person appearing not to be so or badly displayed.
#
# This file can be modified by hand or updated by the following command:
# scripts/mailmapper > tmp; mv tmp .mailmap
#
Allen Martin <amartin@nvidia.com>
Andreas Bießmann <andreas.devel@googlemail.com>
Aneesh V <aneesh@ti.com>
Dirk Behme <dirk.behme@googlemail.com>
Fabio Estevam <fabio.estevam@freescale.com>
Jagannadha Sutradharudu Teki <402jagan@gmail.com>
Markus Klotzbuecher <mk@denx.de>
Prabhakar Kushwaha <prabhakar@freescale.com>
Rajeshwari Shinde <rajeshwari.s@samsung.com>
Sandeep Paulraj <s-paulraj@ti.com>
Shaohui Xie <Shaohui.Xie@freescale.com>
Stefan Roese <stroese>
Stefano Babic <sbabic@denx.de>
TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Wolfgang Denk <wdenk>
York Sun <yorksun@freescale.com>
Łukasz Majewski <l.majewski@samsung.com>

View File

@@ -126,7 +126,7 @@ D: Palmtreo680 board, docg4 nand flash driver
N: Dave Ellis
E: DGE@sixnetio.com
D: EEPROM Speedup, SXNI855T port
D: EEPROM Speedup
N: Daniel Engstr?m
E: daniel@omicron.se

105
Kconfig Normal file
View File

@@ -0,0 +1,105 @@
#
# For a description of the syntax of this configuration file,
# see Documentation/kbuild/kconfig-language.txt.
#
mainmenu "U-Boot $UBOOTVERSION Configuration"
config UBOOTVERSION
string
option env="UBOOTVERSION"
config KCONFIG_OBJDIR
string
option env="KCONFIG_OBJDIR"
menu "General setup"
config LOCALVERSION
string "Local version - append to U-Boot release"
depends on !SPL_BUILD
help
Append an extra string to the end of your U-Boot version.
This will show up on your boot log, for example.
The string you set here will be appended after the contents of
any files with a filename matching localversion* in your
object and source tree, in that order. Your total string can
be a maximum of 64 characters.
config LOCALVERSION_AUTO
bool "Automatically append version information to the version string"
depends on !SPL_BUILD
default y
help
This will try to automatically determine if the current tree is a
release tree by looking for git tags that belong to the current
top of tree revision.
A string of the format -gxxxxxxxx will be added to the localversion
if a git-based tree is found. The string generated by this will be
appended after any matching localversion* files, and after the value
set in CONFIG_LOCALVERSION.
(The actual string used here is the first eight characters produced
by running the command:
$ git rev-parse --verify HEAD
which is done within the script "scripts/setlocalversion".)
config CC_OPTIMIZE_FOR_SIZE
bool "Optimize for size"
depends on !SPL_BUILD
default y
help
Enabling this option will pass "-Os" instead of "-O2" to gcc
resulting in a smaller U-Boot image.
This option is enabled by default for U-Boot.
endmenu # General setup
menu "Boot images"
config SPL_BUILD
bool
depends on $KCONFIG_OBJDIR="spl" || $KCONFIG_OBJDIR="tpl"
default y
config TPL_BUILD
bool
depends on $KCONFIG_OBJDIR="tpl"
default y
config SPL
bool
prompt "Enable SPL" if !SPL_BUILD
default y if SPL_BUILD
help
If you want to build SPL as well as the normal image, say Y.
config TPL
bool
depends on SPL
prompt "Enable TPL" if !SPL_BUILD
default y if TPL_BUILD
default n
help
If you want to build TPL as well as the normal image and SPL, say Y.
config SYS_EXTRA_OPTIONS
string "Extra Options (DEPRECATED)"
depends on !SPL_BUILD
help
The old configuration infrastructure (= mkconfig + boards.cfg)
provided the extra options field. It you have something like
"HAS_BAR,BAZ=64", the optional options
#define CONFIG_HAS
#define CONFIG_BAZ 64
will be defined in include/config.h.
This option was prepared for the smooth migration from the old
configuration to Kconfig. Since this option will be removed sometime,
new boards should not use this option.
endmenu # Boot images
source "arch/Kconfig"

405
MAINTAINERS Normal file
View File

@@ -0,0 +1,405 @@
Descriptions of section entries:
P: Person (obsolete)
M: Mail patches to: FullName <address@domain>
L: Mailing list that is relevant to this area
W: Web-page with status/info
Q: Patchwork web based patch tracking system site
T: SCM tree type and location.
Type is one of: git, hg, quilt, stgit, topgit
S: Status, one of the following:
Supported: Someone is actually paid to look after this.
Maintained: Someone actually looks after it.
Odd Fixes: It has a maintainer but they don't have time to do
much other than throw the odd patch in. See below..
Orphan: No current maintainer [but maybe you could take the
role as you write your new code].
Obsolete: Old code. Something tagged obsolete generally means
it has been replaced by a better system and you
should be using that.
F: Files and directories with wildcard patterns.
A trailing slash includes all files and subdirectory files.
F: drivers/net/ all files in and below drivers/net
F: drivers/net/* all files in drivers/net, but not below
F: */net/* all files in "any top level directory"/net
One pattern per line. Multiple F: lines acceptable.
N: Files and directories with regex patterns.
N: [^a-z]tegra all files whose path contains the word tegra
One pattern per line. Multiple N: lines acceptable.
scripts/get_maintainer.pl has different behavior for files that
match F: pattern and matches of N: patterns. By default,
get_maintainer will not look at git log history when an F: pattern
match occurs. When an N: match occurs, git log history is used
to also notify the people that have git commit signatures.
X: Files and directories that are NOT maintained, same rules as F:
Files exclusions are tested before file matches.
Can be useful for excluding a specific subdirectory, for instance:
F: net/
X: net/ipv6/
matches all files in and below net excluding net/ipv6/
K: Keyword perl extended regex pattern to match content in a
patch or file. For instance:
K: of_get_profile
matches patches or files that contain "of_get_profile"
K: \b(printk|pr_(info|err))\b
matches patches or files that contain one or more of the words
printk, pr_info or pr_err
One regex pattern per line. Multiple K: lines acceptable.
Note: For the hard of thinking, this list is meant to remain in alphabetical
order. If you could add yourselves to it in alphabetical order that would be
so much easier [Ed]
Maintainers List (try to look for most precise areas first)
-----------------------------------
ARC
M: Alexey Brodkin <alexey.brodkin@synopsys.com>
S: Maintained
T: git git://git.denx.de/u-boot-arc.git
F: arch/arc/
ARM
M: Albert Aribaud <albert.u.boot@aribaud.net>
S: Maintained
T: git git://git.denx.de/u-boot-arm.git
F: arch/arm/
ARM ATMEL AT91
M: Andreas Bießmann <andreas.devel@googlemail.com>
S: Maintained
T: git git://git.denx.de/u-boot-atmel.git
F: arch/arm/cpu/armv7/at91/
F: arch/arm/cpu/at91-common/
F: arch/arm/include/asm/arch-at91/
ARM FREESCALE IMX
M: Stefano Babic <sbabic@denx.de>
S: Maintained
T: git git://git.denx.de/u-boot-imx.git
F: arch/arm/cpu/arm1136/mx*/
F: arch/arm/cpu/arm926ejs/mx*/
F: arch/arm/cpu/arm926ejs/imx/
F: arch/arm/cpu/armv7/mx*/
F: arch/arm/cpu/armv7/vf610/
F: arch/arm/cpu/imx-common/
F: arch/arm/include/asm/arch-imx/
F: arch/arm/include/asm/arch-mx*/
F: arch/arm/include/asm/arch-vf610/
F: arch/arm/include/asm/imx-common/
ARM MARVELL KIRKWOOD
M: Prafulla Wadaskar <prafulla@marvell.com>
S: Maintained
T: git git://git.denx.de/u-boot-marvell.git
F: arch/arm/cpu/arm926ejs/kirkwood/
F: arch/arm/include/asm/arch-kirkwood/
ARM MARVELL PXA
M: Marek Vasut <marex@denx.de>
S: Maintained
T: git git://git.denx.de/u-boot-pxa.git
F: arch/arm/cpu/pxa/
F: arch/arm/include/asm/arch-pxa/
ARM SAMSUNG
M: Minkyu Kang <mk7.kang@samsung.com>
S: Maintained
T: git git://git.denx.de/u-boot-samsung.git
F: arch/arm/cpu/arm920t/s3c24x0/
F: arch/arm/cpu/armv7/exynos/
F: arch/arm/cpu/armv7/s5pc1xx/
F: arch/arm/cpu/armv7/s5p-common/
F: arch/arm/include/asm/arch-exynos/
F: arch/arm/include/asm/arch-s3c24x0/
F: arch/arm/include/asm/arch-s5pc1xx/
ARM STM SPEAR
M: Vipin Kumar <vipin.kumar@st.com>
S: Maintained
T: git git://git.denx.de/u-boot-stm.git
F: arch/arm/cpu/arm926ejs/spear/
F: arch/arm/include/asm/arch-spear/
ARM SUNXI
M: Ian Campbell <ijc@hellion.org.uk>
M: Hans De Goede <hdegoede@redhat.com>
S: Maintained
T: git git://git.denx.de/u-boot-sunxi.git
F: arch/arm/cpu/armv7/sunxi/
F: arch/arm/include/asm/arch-sunxi/
ARM TEGRA
M: Tom Warren <twarren@nvidia.com>
S: Maintained
T: git git://git.denx.de/u-boot-tegra.git
F: arch/arm/cpu/arm720t/tegra*/
F: arch/arm/cpu/armv7/tegra*/
F: arch/arm/cpu/tegra*/
F: arch/arm/include/asm/arch-tegra*/
ARM TI
M: Tom Rini <trini@ti.com>
S: Maintained
T: git git://git.denx.de/u-boot-ti.git
F: arch/arm/cpu/arm926ejs/davinci/
F: arch/arm/cpu/arm926ejs/omap/
F: arch/arm/cpu/armv7/omap*/
F: arch/arm/include/asm/arch-davinci/
F: arch/arm/include/asm/arch-omap*/
F: arch/arm/include/asm/ti-common/
ARM ZYNQ
M: Michal Simek <monstr@monstr.eu>
S: Maintained
F: arch/arm/cpu/armv7/zynq/
F: arch/arm/include/asm/arch-zynq/
AVR32
M: Andreas Bießmann <andreas.devel@googlemail.com>
S: Maintained
T: git git://git.denx.de/u-boot-avr32.git
F: arch/avr32/
BLACKFIN
M: Sonic Zhang <sonic.adi@gmail.com>
S: Maintained
T: git git://git.denx.de/u-boot-blackfin.git
F: arch/blackfin/
BUILDMAN
M: Simon Glass <sjg@chromium.org>
S: Maintained
F: tools/buildman/
CFI FLASH
M: Stefan Roese <sr@denx.de>
S: Maintained
T: git git://git.denx.de/u-boot-cfi-flash.git
F: drivers/mtd/*
COLDFIRE
M: Jason Jin <jason.jin@freescale.com>
S: Maintained
T: git git://git.denx.de/u-boot-coldfire.git
F: arch/m68k/
DFU
M: Lukasz Majewski <l.majewski@samsung.com>
S: Maintained
T: git git://git.denx.de/u-boot-dfu.git
F: drivers/dfu/
DRIVER MODEL
M: Simon Glass <sjg@chromium.org>
S: Maintained
F: drivers/core/
F: include/dm/
F: test/dm/
FLATTENED DEVICE TREE
M: Simon Glass <sjg@chromium.org>
S: Maintained
T: git git://git.denx.de/u-boot-fdt.git
F: lib/fdtdec*
F: lib/libfdt/
F: include/fdt*
F: include/libfdt*
F. common/cmd_fdt.c
F: common/fdt_support.c
FREEBSD
M: Rafal Jaworowski <raj@semihalf.com>
S: Maintained
T: git git://git.denx.de/u-boot-freebsd.git
FREESCALE QORIQ
M: York Sun <yorksun@freescale.com>
S: Maintained
T: git git://git.denx.de/u-boot-fsl-qoriq.git
I2C
M: Heiko Schocher <hs@denx.de>
S: Maintained
T: git git://git.denx.de/u-boot-i2c.git
F: drivers/i2c/
MICROBLAZE
M: Michal Simek <monstr@monstr.eu>
S: Maintained
T: git git://git.denx.de/u-boot-microblaze.git
F: arch/microblaze/
MIPS
M: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
S: Maintained
T: git git://git.denx.de/u-boot-mips.git
F: arch/mips/
MMC
M: Pantelis Antoniou <panto.antoniou-consulting.com>
S: Maintained
T: git git://git.denx.de/u-boot-mmc.git
F: drivers/mmc/
OPENRISC
M: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
S: Maintained
F: arch/openrisc/
PATMAN
M: Simon Glass <sjg@chromium.org>
S: Maintained
F: tools/patman/
POWERPC
M: Wolfgang Denk <wd@denx.de>
S: Maintained
F: arch/powerpc/
POWERPC MPC5XXX
M: Wolfgang Denk <wd@denx.de>
S: Maintained
T: git git://git.denx.de/u-boot-mpc5xxx.git
F: arch/powerpc/cpu/mpc5*/
POWERPC MPC8XX
M: Wolfgang Denk <wd@denx.de>
S: Maintained
T: git git://git.denx.de/u-boot-mpc8xx.git
F: arch/powerpc/cpu/mpc8xx/
POWERPC MPC82XX
M: Wolfgang Denk <wd@denx.de>
S: Maintained
T: git git://git.denx.de/u-boot-mpc82xx.git
F: arch/powerpc/cpu/mpc82*/
POWERPC MPC83XX
M: Kim Phillips <kim.phillips@freescale.com>
S: Maintained
T: git git://git.denx.de/u-boot-mpc83xx.git
F: arch/powerpc/cpu/mpc83xx/
F: arch/powerpc/include/asm/arch-mpc83xx/
POWERPC MPC85XX
M: York Sun <yorksun@freescale.com>
S: Maintained
T: git git://git.denx.de/u-boot-mpc85xx.git
F: arch/powerpc/cpu/mpc85xx/
POWERPC MPC86XX
M: York Sun <yorksun@freescale.com>
S: Maintained
T: git git://git.denx.de/u-boot-mpc86xx.git
F: arch/powerpc/cpu/mpc86xx/
POWERPC PPC74XX PPC7XX
M: Wolfgang Denk <wd@denx.de>
S: Maintained
T: git git://git.denx.de/u-boot-74xx-7xx.git
F: arch/powerpc/cpu/74xx_7xx/
POWERPC PPC4XX
M: Stefan Roese <sr@denx.de>
S: Maintained
T: git git://git.denx.de/u-boot-ppc4xx.git
F: arch/powerpc/cpu/ppc4xx/
NETWORK
M: Joe Hershberger <joe.hershberger@gmail.com>
S: Maintained
T: git git://git.denx.de/u-boot-net.git
F: drivers/net/
NAND FLASH
M: Scott Wood <scottwood@freescale.com>
S: Maintained
T: git git://git.denx.de/u-boot-nand-flash.git
F: drivers/mtd/nand/
NDS32
M: Macpaul Lin <macpaul@andestech.com>
S: Maintained
T: git git://git.denx.de/u-boot-nds32.git
F: arch/nds32/
NIOS
M: Thomas Chou <thomas@wytron.com.tw>
S: Maintained
T: git git://git.denx.de/u-boot-nios.git
F: arch/nios2/
ONENAND
M: Lukasz Majewski <l.majewski@samsung.com>
S: Maintained
T: git git://git.denx.de/u-boot-onenand.git
F: drivers/mtd/onenand/
SANDBOX
M: Simon Glass <sjg@chromium.org>
S: Maintained
F: arch/sandbox/
SH
M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
S: Maintained
T: git git://git.denx.de/u-boot-sh.git
F: arch/sh/
SPARC
M: Daniel Hellstrom <daniel@gaisler.com>
S: Maintained
T: git git://git.denx.de/u-boot-sparc.git
F: arch/sparc/
SPI
M: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
S: Maintained
T: git git://git.denx.de/u-boot-spi.git
F: drivers/mtd/spi/
F: drivers/spi/
F: include/spi*
TESTING
M: Detlev Zundel <dzu@denx.de>
S: Maintained
T: git git://git.denx.de/u-boot-testing.git
TQ GROUP
M: Martin Krause <martin.krause@tq-systems.de>
S: Maintained
T: git git://git.denx.de/u-boot-tq-group.git
UBI
M: Kyungmin Park <kmpark@infradead.org>
S: Maintained
T: git git://git.denx.de/u-boot-ubi.git
F: drivers/mtd/ubi/
USB
M: Marek Vasut <marex@denx.de>
S: Maintained
T: git git://git.denx.de/u-boot-usb.git
F: drivers/usb/
VIDEO
M: Anatolij Gustschin <agust@denx.de>
S: Maintained
T: git git://git.denx.de/u-boot-video.git
F: drivers/video/
X86
M: Simon Glass <sjg@chromium.org>
S: Maintained
T: git git://git.denx.de/u-boot-x86.git
F: arch/x86/
THE REST
M: Tom Rini <trini@ti.com>
L: u-boot@lists.denx.de
Q: http://patchwork.ozlabs.org/project/uboot/list/
S: Maintained
T: git git://git.denx.de/u-boot.git
F: *
F: */

27
MAKEALL
View File

@@ -162,9 +162,20 @@ while true ; do
echo "Internal error!" >&2 ; exit 1 ;;
esac
done
GNU_MAKE=$(scripts/show-gnu-make) || {
echo "GNU Make not found" >&2
exit 1
}
# echo "Remaining arguments:"
# for arg do echo '--> '"\`$arg'" ; done
tools/genboardscfg.py || {
echo "Failed to generate boards.cfg" >&2
exit 1
}
FILTER="\$1 !~ /^#/"
[ "$opt_a" ] && FILTER="${FILTER} && $opt_a"
[ "$opt_c" ] && FILTER="${FILTER} && $opt_c"
@@ -506,9 +517,9 @@ get_target_location() {
set ${line}
CONFIG_NAME="${7%_config}"
CONFIG_NAME="${7%_defconfig}"
[ "${BOARD_NAME}" ] || BOARD_NAME="${7%_config}"
[ "${BOARD_NAME}" ] || BOARD_NAME="${7%_defconfig}"
if [ $# -gt 5 ]; then
if [ "$6" = "-" ] ; then
@@ -633,19 +644,21 @@ build_target() {
target_arch=$(get_target_arch ${target})
eval cross_toolchain=\$CROSS_COMPILE_`echo $target_arch | tr '[:lower:]' '[:upper:]'`
if [ "${cross_toolchain}" ] ; then
MAKE="make CROSS_COMPILE=${cross_toolchain}"
MAKE="$GNU_MAKE CROSS_COMPILE=${cross_toolchain}"
elif [ "${CROSS_COMPILE}" ] ; then
MAKE="make CROSS_COMPILE=${CROSS_COMPILE}"
MAKE="$GNU_MAKE CROSS_COMPILE=${CROSS_COMPILE}"
else
MAKE=make
MAKE=$GNU_MAKE
fi
if [ "${output_dir}" != "." ] ; then
MAKE="${MAKE} O=${output_dir}"
fi
${MAKE} distclean >/dev/null
${MAKE} -s ${target}_config
${MAKE} mrproper >/dev/null
echo "Building ${target} board..."
${MAKE} -s ${target}_defconfig >/dev/null
${MAKE} ${JOBS} ${CHECK} all \
>${LOG_DIR}/$target.MAKELOG 2> ${LOG_DIR}/$target.ERR

171
Makefile
View File

@@ -6,9 +6,9 @@
#
VERSION = 2014
PATCHLEVEL = 07
PATCHLEVEL = 10
SUBLEVEL =
EXTRAVERSION =
EXTRAVERSION = -rc2
NAME =
# *DOCUMENTATION*
@@ -109,10 +109,6 @@ ifeq ("$(origin O)", "command line")
KBUILD_OUTPUT := $(O)
endif
ifeq ("$(origin W)", "command line")
export KBUILD_ENABLE_EXTRA_GCC_CHECKS := $(W)
endif
# That's our default target when none is given on the command line
PHONY := _all
_all:
@@ -166,9 +162,6 @@ VPATH := $(srctree)$(if $(KBUILD_EXTMOD),:$(KBUILD_EXTMOD))
export srctree objtree VPATH
MKCONFIG := $(srctree)/mkconfig
export MKCONFIG
# Make sure CDPATH settings don't interfere
unexport CDPATH
@@ -189,9 +182,6 @@ HOSTOS := $(shell uname -s | tr '[:upper:]' '[:lower:]' | \
export HOSTARCH HOSTOS
# Deal with colliding definitions from tcsh etc.
VENDOR=
#########################################################################
# set default to nothing for native builds
@@ -199,6 +189,9 @@ ifeq ($(HOSTARCH),$(ARCH))
CROSS_COMPILE ?=
endif
KCONFIG_CONFIG ?= .config
export KCONFIG_CONFIG
# SHELL used by kbuild
CONFIG_SHELL := $(shell if [ -x "$$BASH" ]; then echo $$BASH; \
else if [ -x /bin/bash ]; then echo /bin/bash; \
@@ -341,6 +334,7 @@ OBJCOPY = $(CROSS_COMPILE)objcopy
OBJDUMP = $(CROSS_COMPILE)objdump
AWK = awk
PERL = perl
PYTHON = python
DTC = dtc
CHECK = sparse
@@ -362,7 +356,7 @@ export VERSION PATCHLEVEL SUBLEVEL UBOOTRELEASE UBOOTVERSION
export ARCH CPU BOARD VENDOR SOC CPUDIR BOARDDIR
export CONFIG_SHELL HOSTCC HOSTCFLAGS HOSTLDFLAGS CROSS_COMPILE AS LD CC
export CPP AR NM LDR STRIP OBJCOPY OBJDUMP
export MAKE AWK PERL
export MAKE AWK PERL PYTHON
export HOSTCXX HOSTCXXFLAGS DTC CHECK CHECKFLAGS
export KBUILD_CPPFLAGS NOSTDINC_FLAGS UBOOTINCLUDE OBJCOPYFLAGS LDFLAGS
@@ -443,12 +437,12 @@ ifeq ($(mixed-targets),1)
# We're called with mixed targets (*config and build targets).
# Handle them one by one.
PHONY += $(MAKECMDGOALS) build-one-by-one
PHONY += $(MAKECMDGOALS) __build_one_by_one
$(MAKECMDGOALS): build-one-by-one
$(filter-out __build_one_by_one, $(MAKECMDGOALS)): __build_one_by_one
@:
build-one-by-one:
__build_one_by_one:
$(Q)set -e; \
for i in $(MAKECMDGOALS); do \
$(MAKE) -f $(srctree)/Makefile $$i; \
@@ -460,31 +454,49 @@ ifeq ($(config-targets),1)
# *config targets only - make sure prerequisites are updated, and descend
# in scripts/kconfig to make the *config target
# Read arch specific Makefile to set KBUILD_DEFCONFIG as needed.
# KBUILD_DEFCONFIG may point out an alternative default configuration
# used for 'make defconfig'
KBUILD_DEFCONFIG := sandbox_defconfig
export KBUILD_DEFCONFIG KBUILD_KCONFIG
%_config:: outputmakefile
@$(MKCONFIG) -A $(@:_config=)
config: scripts_basic outputmakefile FORCE
(Q)$(MAKE) $(build)=scripts/kconfig $@
%config: scripts_basic outputmakefile FORCE
+$(Q)$(CONFIG_SHELL) $(srctree)/scripts/multiconfig.sh $@
else
# ===========================================================================
# Build targets only - this includes vmlinux, arch specific targets, clean
# targets and others. In general all targets except *config targets.
# load ARCH, BOARD, and CPU configuration
-include include/config.mk
ifeq ($(dot-config),1)
# Read in config
-include include/config/auto.conf
# Read in dependencies to all Kconfig* files, make sure to run
# oldconfig if changes are detected.
-include include/config/auto.conf.cmd
# To avoid any implicit rule to kick in, define an empty command
$(KCONFIG_CONFIG) include/config/auto.conf.cmd: ;
# If .config is newer than include/config/auto.conf, someone tinkered
# with it and forgot to run make oldconfig.
# if auto.conf.cmd is missing then we are probably in a cleaned tree so
# we execute the config step to be sure to catch updated Kconfig files
include/config/%.conf: $(KCONFIG_CONFIG) include/config/auto.conf.cmd
$(Q)$(MAKE) -f $(srctree)/Makefile silentoldconfig
-include include/autoconf.mk
-include include/autoconf.mk.dep
# load other configuration
# We want to include arch/$(ARCH)/config.mk only when include/config/auto.conf
# is up-to-date. When we switch to a different board configuration, old CONFIG
# macros are still remaining in include/config/auto.conf. Without the following
# gimmick, wrong config.mk would be included leading nasty warnings/errors.
autoconf_is_current := $(if $(wildcard $(KCONFIG_CONFIG)),$(shell find . \
-path ./include/config/auto.conf -newer $(KCONFIG_CONFIG)))
ifneq ($(autoconf_is_current),)
include $(srctree)/config.mk
ifeq ($(wildcard include/config.mk),)
$(error "System not configured - see README")
endif
# If board code explicitly specified LDSCRIPT or CONFIG_SYS_LDSCRIPT, use
@@ -513,11 +525,15 @@ ifndef LDSCRIPT
endif
else
# Dummy target needed, because used as prerequisite
include/config/auto.conf: ;
endif # $(dot-config)
KBUILD_CFLAGS += -Os #-fomit-frame-pointer
ifdef CONFIG_CC_OPTIMIZE_FOR_SIZE
KBUILD_CFLAGS += -Os
else
KBUILD_CFLAGS += -O2
endif
ifdef BUILD_TAG
KBUILD_CFLAGS += -DBUILD_TAG='"$(BUILD_TAG)"'
@@ -553,6 +569,8 @@ endif
export CONFIG_SYS_TEXT_BASE
include $(srctree)/scripts/Makefile.extrawarn
# Add user supplied CPPFLAGS, AFLAGS and CFLAGS as the last assignments
KBUILD_CPPFLAGS += $(KCPPFLAGS)
KBUILD_AFLAGS += $(KAFLAGS)
@@ -563,7 +581,8 @@ KBUILD_CFLAGS += $(KCFLAGS)
UBOOTINCLUDE := \
-Iinclude \
$(if $(KBUILD_SRC), -I$(srctree)/include) \
-I$(srctree)/arch/$(ARCH)/include
-I$(srctree)/arch/$(ARCH)/include \
-include $(srctree)/include/linux/kconfig.h
NOSTDINC_FLAGS += -nostdinc -isystem $(shell $(CC) -print-file-name=include)
CHECKFLAGS += $(NOSTDINC_FLAGS)
@@ -785,14 +804,15 @@ u-boot.hex u-boot.srec: u-boot FORCE
OBJCOPYFLAGS_u-boot.bin := -O binary
binary_size_check: u-boot.bin System.map FORCE
@file_size=`stat -c %s u-boot.bin` ; \
map_size=$(shell cat System.map | \
binary_size_check: u-boot.bin FORCE
@file_size=$(shell wc -c u-boot.bin | awk '{print $$1}') ; \
map_size=$(shell cat u-boot.map | \
awk '/_image_copy_start/ {start = $$1} /_image_binary_end/ {end = $$1} END {if (start != "" && end != "") print "ibase=16; " toupper(end) " - " toupper(start)}' \
| sed 's/0X//g' \
| bc); \
if [ "" != "$$map_size" ]; then \
if test $$map_size -ne $$file_size; then \
echo "System.map shows a binary size of $$map_size" >&2 ; \
echo "u-boot.map shows a binary size of $$map_size" >&2 ; \
echo " but u-boot.bin shows $$file_size" >&2 ; \
exit 1; \
fi \
@@ -915,6 +935,12 @@ OBJCOPYFLAGS_u-boot-spi.gph = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO)
u-boot-spi.gph: spl/u-boot-spl.gph u-boot.img FORCE
$(call if_changed,pad_cat)
MKIMAGEFLAGS_u-boot-nand.gph = -A $(ARCH) -T gpimage -C none \
-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -n U-Boot
u-boot-nand.gph: u-boot.bin FORCE
$(call if_changed,mkimage)
@dd if=/dev/zero bs=8 count=1 2>/dev/null >> $@
ifneq ($(CONFIG_SUNXI),)
OBJCOPYFLAGS_u-boot-sunxi-with-spl.bin = -I binary -O binary \
--pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff
@@ -982,13 +1008,17 @@ quiet_cmd_u-boot__ ?= LD $@
--start-group $(u-boot-main) --end-group \
$(PLATFORM_LIBS) -Map u-boot.map
u-boot: $(u-boot-init) $(u-boot-main) u-boot.lds
$(call if_changed,u-boot__)
ifeq ($(CONFIG_KALLSYMS),y)
quiet_cmd_smap = GEN common/system_map.o
cmd_smap = \
smap=`$(call SYSTEM_MAP,u-boot) | \
awk '$$2 ~ /[tTwW]/ {printf $$1 $$3 "\\\\000"}'` ; \
$(CC) $(c_flags) -DSYSTEM_MAP="\"$${smap}\"" \
-c $(srctree)/common/system_map.c -o common/system_map.o
u-boot: $(u-boot-init) $(u-boot-main) u-boot.lds
$(call if_changed,u-boot__)
ifeq ($(CONFIG_KALLSYMS),y)
$(call cmd,smap)
$(call cmd,u-boot__) common/system_map.o
endif
@@ -1018,7 +1048,7 @@ define filechk_uboot.release
endef
# Store (new) UBOOTRELEASE string in include/config/uboot.release
include/config/uboot.release: Makefile FORCE
include/config/uboot.release: include/config/auto.conf FORCE
$(call filechk,uboot.release)
@@ -1036,8 +1066,8 @@ PHONY += prepare archprepare prepare0 prepare1 prepare2 prepare3
# 1) Check that make has not been executed in the kernel src $(srctree)
prepare3: include/config/uboot.release
ifneq ($(KBUILD_SRC),)
@$(kecho) ' Using $(srctree) as source for u-boot'
$(Q)if [ -f $(srctree)/include/config.mk ]; then \
@$(kecho) ' Using $(srctree) as source for U-Boot'
$(Q)if [ -f $(srctree)/.config -o -d $(srctree)/include/config ]; then \
echo >&2 " $(srctree) is not clean, please run 'make mrproper'"; \
echo >&2 " in the '$(srctree)' directory.";\
/bin/false; \
@@ -1047,7 +1077,8 @@ endif
# prepare2 creates a makefile if using a separate output directory
prepare2: prepare3 outputmakefile
prepare1: prepare2 $(version_h) $(timestamp_h)
prepare1: prepare2 $(version_h) $(timestamp_h) \
include/config/auto.conf
ifeq ($(__HAVE_ARCH_GENERIC_BOARD),)
ifeq ($(CONFIG_SYS_GENERIC_BOARD),y)
@echo >&2 " Your architecture does not support generic board."
@@ -1089,29 +1120,6 @@ $(version_h): include/config/uboot.release FORCE
$(timestamp_h): $(srctree)/Makefile FORCE
$(call filechk,timestamp.h)
#
# Auto-generate the autoconf.mk file (which is included by all makefiles)
#
# This target actually generates 2 files; autoconf.mk and autoconf.mk.dep.
# the dep file is only include in this top level makefile to determine when
# to regenerate the autoconf.mk file.
quiet_cmd_autoconf_dep = GEN $@
cmd_autoconf_dep = $(CC) -x c -DDO_DEPS_ONLY -M $(c_flags) \
-MQ include/autoconf.mk $(srctree)/include/common.h > $@ || rm $@
include/autoconf.mk.dep: include/config.h include/common.h
$(call cmd,autoconf_dep)
quiet_cmd_autoconf = GEN $@
cmd_autoconf = \
$(CPP) $(c_flags) -DDO_DEPS_ONLY -dM $(srctree)/include/common.h > $@.tmp && \
sed -n -f $(srctree)/tools/scripts/define2mk.sed $@.tmp > $@; \
rm $@.tmp
include/autoconf.mk: include/config.h
$(call cmd,autoconf)
# ---------------------------------------------------------------------------
PHONY += depend dep
@@ -1135,9 +1143,9 @@ spl/sunxi-spl.bin: spl/u-boot-spl
@:
tpl/u-boot-tpl.bin: tools prepare
$(Q)$(MAKE) obj=tpl -f $(srctree)/scripts/Makefile.spl all CONFIG_TPL_BUILD=y
$(Q)$(MAKE) obj=tpl -f $(srctree)/scripts/Makefile.spl all
TAG_SUBDIRS := $(u-boot-dirs) include
TAG_SUBDIRS := $(patsubst %,$(srctree)/%,$(u-boot-dirs) include)
FIND := find
FINDFLAGS := -L
@@ -1147,7 +1155,7 @@ tags ctags:
-name '*.[chS]' -print`
etags:
etags -a -o $(obj)etags `$(FIND) $(FINDFLAGS) $(TAG_SUBDIRS) \
etags -a -o etags `$(FIND) $(FINDFLAGS) $(TAG_SUBDIRS) \
-name '*.[chS]' -print`
cscope:
$(FIND) $(FINDFLAGS) $(TAG_SUBDIRS) -name '*.[chS]' -print > \
@@ -1210,20 +1218,18 @@ include/license.h: tools/bin2header COPYING
# Directories & files removed with 'make clean'
CLEAN_DIRS += $(MODVERDIR)
CLEAN_FILES += u-boot.lds include/bmp_logo.h include/bmp_logo_data.h \
include/autoconf.mk* include/spl-autoconf.mk \
include/tpl-autoconf.mk
CLEAN_FILES += u-boot.lds include/bmp_logo.h include/bmp_logo_data.h
# Directories & files removed with 'make clobber'
CLOBBER_DIRS += spl tpl
CLOBBER_DIRS += $(foreach d, spl tpl, $(patsubst %,$d/%, \
$(filter-out include, $(shell ls -1 $d 2>/dev/null))))
CLOBBER_FILES += u-boot* MLO* SPL System.map
# Directories & files removed with 'make mrproper'
MRPROPER_DIRS += include/config include/generated \
MRPROPER_DIRS += include/config include/generated spl tpl \
.tmp_objdiff
MRPROPER_FILES += .config .config.old \
tags TAGS cscope* GPATH GTAGS GRTAGS GSYMS \
include/config.h include/config.mk
MRPROPER_FILES += .config .config.old include/autoconf.mk* include/config.h \
ctags etags TAGS cscope* GPATH GTAGS GRTAGS GSYMS
# clean - Delete most, but leave enough to build external modules
#
@@ -1287,6 +1293,7 @@ distclean: mrproper
-o -name '.*.rej' -o -name '*%' -o -name 'core' \
-o -name '*.pyc' \) \
-type f -print | xargs rm -f
@rm -f boards.cfg
backup:
F=`basename $(srctree)` ; cd .. ; \
@@ -1300,10 +1307,9 @@ help:
@echo ' mrproper - Remove all generated files + config + various backup files'
@echo ' distclean - mrproper + remove editor backup and patch files'
@echo ''
# uncomment after adding Kconfig feature
# @echo 'Configuration targets:'
# @$(MAKE) -f $(srctree)/scripts/kconfig/Makefile help
# @echo ''
@echo 'Configuration targets:'
@$(MAKE) -f $(srctree)/scripts/kconfig/Makefile help
@echo ''
@echo 'Other generic targets:'
@echo ' all - Build all necessary images depending on configuration'
@echo ' u-boot - Build the bare u-boot'
@@ -1311,7 +1317,8 @@ help:
@echo ' dir/file.[oisS] - Build specified target only'
@echo ' dir/file.lst - Build specified mixed source/assembly target only'
@echo ' (requires a recent binutils and recent build (System.map))'
@echo ' tags/TAGS - Generate tags file for editors'
@echo ' tags/ctags - Generate ctags file for editors'
@echo ' etags - Generate etags file for editors'
@echo ' cscope - Generate cscope index'
@echo ' ubootrelease - Output the release version string'
@echo ' ubootversion - Output the version stored in Makefile'

146
README
View File

@@ -252,15 +252,15 @@ Selection of Processor Architecture and Board Type:
---------------------------------------------------
For all supported boards there are ready-to-use default
configurations available; just type "make <board_name>_config".
configurations available; just type "make <board_name>_defconfig".
Example: For a TQM823L module type:
cd u-boot
make TQM823L_config
make TQM823L_defconfig
For the Cogent platform, you need to specify the CPU type as well;
e.g. "make cogent_mpc8xx_config". And also configure the cogent
e.g. "make cogent_mpc8xx_defconfig". And also configure the cogent
directory according to the instructions in cogent/README.
@@ -959,6 +959,7 @@ The following options need to be configured:
CONFIG_CMD_BMP * BMP support
CONFIG_CMD_BSP * Board specific commands
CONFIG_CMD_BOOTD bootd
CONFIG_CMD_BOOTI * ARM64 Linux kernel Image support
CONFIG_CMD_CACHE * icache, dcache
CONFIG_CMD_CLK * clock command support
CONFIG_CMD_CONSOLE coninfo
@@ -1152,6 +1153,7 @@ The following options need to be configured:
CONFIG_RTC_DS1307 - use Maxim, Inc. DS1307 RTC
CONFIG_RTC_DS1337 - use Maxim, Inc. DS1337 RTC
CONFIG_RTC_DS1338 - use Maxim, Inc. DS1338 RTC
CONFIG_RTC_DS1339 - use Maxim, Inc. DS1339 RTC
CONFIG_RTC_DS164x - use Dallas DS164x RTC
CONFIG_RTC_ISL1208 - use Intersil ISL1208 RTC
CONFIG_RTC_MAX6900 - use Maxim, Inc. MAX6900 RTC
@@ -1377,6 +1379,10 @@ The following options need to be configured:
CONFIG_SH_ETHER_CACHE_WRITEBACK
If this option is set, the driver enables cache flush.
- PWM Support:
CONFIG_PWM_IMX
Support for PWM modul on the imx6.
- TPM Support:
CONFIG_TPM
Support TPM devices.
@@ -2036,6 +2042,24 @@ CBFS (Coreboot Filesystem) support
4th and following
BOOTP requests: delay 0 ... 8 sec
CONFIG_BOOTP_ID_CACHE_SIZE
BOOTP packets are uniquely identified using a 32-bit ID. The
server will copy the ID from client requests to responses and
U-Boot will use this to determine if it is the destination of
an incoming response. Some servers will check that addresses
aren't in use before handing them out (usually using an ARP
ping) and therefore take up to a few hundred milliseconds to
respond. Network congestion may also influence the time it
takes for a response to make it back to the client. If that
time is too long, U-Boot will retransmit requests. In order
to allow earlier responses to still be accepted after these
retransmissions, U-Boot's BOOTP client keeps a small cache of
IDs. The CONFIG_BOOTP_ID_CACHE_SIZE controls the size of this
cache. The default is to keep IDs for up to four outstanding
requests. Increasing this will allow U-Boot to accept offers
from a BOOTP client in networks with unusually high latency.
- DHCP Advanced Options:
You can fine tune the DHCP functionality by defining
CONFIG_BOOTP_* symbols:
@@ -2597,6 +2621,10 @@ CBFS (Coreboot Filesystem) support
Enables the driver for the SPI controllers on i.MX and MXC
SoCs. Currently i.MX31/35/51 are supported.
CONFIG_SYS_SPI_MXC_WAIT
Timeout for waiting until spi transfer completed.
default: (CONFIG_SYS_HZ/100) /* 10 ms */
- FPGA Support: CONFIG_FPGA
Enables FPGA subsystem.
@@ -2926,6 +2954,17 @@ CBFS (Coreboot Filesystem) support
memories can be connected with a given cs line.
currently Xilinx Zynq qspi support these type of connections.
CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
enable the W#/Vpp signal to disable writing to the status
register on ST MICRON flashes like the N25Q128.
The status register write enable/disable bit, combined with
the W#/VPP signal provides hardware data protection for the
device as follows: When the enable/disable bit is set to 1,
and the W#/VPP signal is driven LOW, the status register
nonvolatile bits become read-only and the WRITE STATUS REGISTER
operation will not execute. The only way to exit this
hardware-protected mode is to drive W#/VPP HIGH.
- SystemACE Support:
CONFIG_SYSTEMACE
@@ -3315,6 +3354,9 @@ FIT uImage format:
Adds the MTD partitioning infrastructure from the Linux
kernel. Needed for UBI support.
CONFIG_MTD_NAND_VERIFY_WRITE
verify if the written data is correct reread.
- UBI support
CONFIG_CMD_UBI
@@ -3328,6 +3370,64 @@ FIT uImage format:
Make the verbose messages from UBI stop printing. This leaves
warnings and errors enabled.
CONFIG_MTD_UBI_WL_THRESHOLD
This parameter defines the maximum difference between the highest
erase counter value and the lowest erase counter value of eraseblocks
of UBI devices. When this threshold is exceeded, UBI starts performing
wear leveling by means of moving data from eraseblock with low erase
counter to eraseblocks with high erase counter.
The default value should be OK for SLC NAND flashes, NOR flashes and
other flashes which have eraseblock life-cycle 100000 or more.
However, in case of MLC NAND flashes which typically have eraseblock
life-cycle less than 10000, the threshold should be lessened (e.g.,
to 128 or 256, although it does not have to be power of 2).
default: 4096
CONFIG_MTD_UBI_BEB_LIMIT
This option specifies the maximum bad physical eraseblocks UBI
expects on the MTD device (per 1024 eraseblocks). If the
underlying flash does not admit of bad eraseblocks (e.g. NOR
flash), this value is ignored.
NAND datasheets often specify the minimum and maximum NVM
(Number of Valid Blocks) for the flashes' endurance lifetime.
The maximum expected bad eraseblocks per 1024 eraseblocks
then can be calculated as "1024 * (1 - MinNVB / MaxNVB)",
which gives 20 for most NANDs (MaxNVB is basically the total
count of eraseblocks on the chip).
To put it differently, if this value is 20, UBI will try to
reserve about 1.9% of physical eraseblocks for bad blocks
handling. And that will be 1.9% of eraseblocks on the entire
NAND chip, not just the MTD partition UBI attaches. This means
that if you have, say, a NAND flash chip admits maximum 40 bad
eraseblocks, and it is split on two MTD partitions of the same
size, UBI will reserve 40 eraseblocks when attaching a
partition.
default: 20
CONFIG_MTD_UBI_FASTMAP
Fastmap is a mechanism which allows attaching an UBI device
in nearly constant time. Instead of scanning the whole MTD device it
only has to locate a checkpoint (called fastmap) on the device.
The on-flash fastmap contains all information needed to attach
the device. Using fastmap makes only sense on large devices where
attaching by scanning takes long. UBI will not automatically install
a fastmap on old images, but you can set the UBI parameter
CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT to 1 if you want so. Please note
that fastmap-enabled images are still usable with UBI implementations
without fastmap support. On typical flash devices the whole fastmap
fits into one PEB. UBI will reserve PEBs to hold two fastmaps.
CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT
Set this parameter to enable fastmap automatically on images
without a fastmap.
default: 0
- UBIFS support
CONFIG_CMD_UBIFS
@@ -3736,6 +3836,25 @@ Configuration Settings:
- CONFIG_SYS_MALLOC_LEN:
Size of DRAM reserved for malloc() use.
- CONFIG_SYS_MALLOC_F_LEN
Size of the malloc() pool for use before relocation. If
this is defined, then a very simple malloc() implementation
will become available before relocation. The address is just
below the global data, and the stack is moved down to make
space.
This feature allocates regions with increasing addresses
within the region. calloc() is supported, but realloc()
is not available. free() is supported but does nothing.
The memory will be freed (or in fact just forgotton) when
U-Boot relocates itself.
Pre-relocation malloc() is only supported on sandbox
at present but is fairly easy to enable for other archs.
Pre-relocation malloc() is only supported on ARM at present
but is fairly easy to enable for other archs.
- CONFIG_SYS_BOOTM_LEN:
Normally compressed uImages are limited to an
uncompressed size of 8 MBytes. If this is not enough,
@@ -4347,6 +4466,11 @@ use the "saveenv" command to store a valid environment.
later, once stdio is running and output goes to the LCD, if
present.
- CONFIG_BOARD_SIZE_LIMIT:
Maximum size of the U-Boot image. When defined, the
build system checks that the actual size does not
exceed it.
Low Level (hardware related) configuration options:
---------------------------------------------------
@@ -4824,9 +4948,9 @@ U-Boot is intended to be simple to build. After installing the
sources you must configure U-Boot for one specific board type. This
is done by typing:
make NAME_config
make NAME_defconfig
where "NAME_config" is the name of one of the existing configu-
where "NAME_defconfig" is the name of one of the existing configu-
rations; see boards.cfg for supported names.
Note: for some board special configuration names may exist; check if
@@ -4835,10 +4959,10 @@ Note: for some board special configuration names may exist; check if
or with LCD support. You can select such additional "features"
when choosing the configuration, i. e.
make TQM823L_config
make TQM823L_defconfig
- will configure for a plain TQM823L, i. e. no LCD support
make TQM823L_LCD_config
make TQM823L_LCD_defconfig
- will configure for a TQM823L with U-Boot console on LCD
etc.
@@ -4858,14 +4982,14 @@ this behavior and build U-Boot to some external directory:
1. Add O= to the make command line invocations:
make O=/tmp/build distclean
make O=/tmp/build NAME_config
make O=/tmp/build NAME_defconfig
make O=/tmp/build all
2. Set environment variable BUILD_DIR to point to the desired location:
export BUILD_DIR=/tmp/build
make distclean
make NAME_config
make NAME_defconfig
make all
Note that the command line "O=" setting overrides the BUILD_DIR environment
@@ -4891,7 +5015,7 @@ steps:
your board
3. If you're porting U-Boot to a new CPU, then also create a new
directory to hold your CPU specific code. Add any files you need.
4. Run "make <board>_config" with your new name.
4. Run "make <board>_defconfig" with your new name.
5. Type "make", and you should get a working "u-boot.srec" file
to be installed on your target system.
6. Debug and solve any problems that might arise.
@@ -5471,7 +5595,7 @@ which was introduced for our predecessor project PPCBoot and uses a
Example:
make TQM850L_config
make TQM850L_defconfig
make oldconfig
make dep
make uImage

View File

@@ -25,6 +25,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define errf(fmt, args...) do { printf("ERROR @ %s(): ", __func__); printf(fmt, ##args); } while (0)
#ifdef CONFIG_CMD_NET
static int dev_valid_net(void *cookie)
{
@@ -85,3 +86,32 @@ int dev_read_net(void *cookie, void *buf, int len)
return eth_receive(buf, len);
}
#else
int dev_open_net(void *cookie)
{
return API_ENODEV;
}
int dev_close_net(void *cookie)
{
return API_ENODEV;
}
int dev_enum_net(struct device_info *di)
{
return 0;
}
int dev_write_net(void *cookie, void *buf, int len)
{
return API_ENODEV;
}
int dev_read_net(void *cookie, void *buf, int len)
{
return API_ENODEV;
}
#endif

66
arch/Kconfig Normal file
View File

@@ -0,0 +1,66 @@
choice
prompt "Architecture select"
default SANDBOX
config ARC
bool "ARC architecture"
config ARM
bool "ARM architecture"
config AVR32
bool "AVR32 architecture"
config BLACKFIN
bool "Blackfin architecture"
config M68K
bool "M68000 architecture"
config MICROBLAZE
bool "MicroBlaze architecture"
config MIPS
bool "MIPS architecture"
config NDS32
bool "NDS32 architecture"
config NIOS2
bool "Nios II architecture"
config OPENRISC
bool "OpenRISC architecture"
config PPC
bool "PowerPC architecture"
config SANDBOX
bool "Sandbox"
config SH
bool "SuperH architecture"
config SPARC
bool "SPARC architecture"
config X86
bool "x86 architecture"
endchoice
source "arch/arc/Kconfig"
source "arch/arm/Kconfig"
source "arch/avr32/Kconfig"
source "arch/blackfin/Kconfig"
source "arch/m68k/Kconfig"
source "arch/microblaze/Kconfig"
source "arch/mips/Kconfig"
source "arch/nds32/Kconfig"
source "arch/nios2/Kconfig"
source "arch/openrisc/Kconfig"
source "arch/powerpc/Kconfig"
source "arch/sandbox/Kconfig"
source "arch/sh/Kconfig"
source "arch/sparc/Kconfig"
source "arch/x86/Kconfig"

29
arch/arc/Kconfig Normal file
View File

@@ -0,0 +1,29 @@
menu "ARC architecture"
depends on ARC
config SYS_ARCH
string
default "arc"
choice
prompt "Target select"
config TARGET_TB100
bool "Support tb100"
config TARGET_ARCANGEL4
bool "Support arcangel4"
config TARGET_ARCANGEL4_BE
bool "Support arcangel4-be"
config TARGET_AXS101
bool "Support axs101"
endchoice
source "board/abilis/tb100/Kconfig"
source "board/synopsys/Kconfig"
source "board/synopsys/axs101/Kconfig"
endmenu

View File

@@ -21,7 +21,7 @@ ifeq ($(CROSS_COMPILE),)
CROSS_COMPILE := $(ARC_CROSS_COMPILE)
endif
PLATFORM_CPPFLAGS += -ffixed-r25 -D__ARC__ -DCONFIG_ARC -gdwarf-2
PLATFORM_CPPFLAGS += -ffixed-r25 -D__ARC__ -gdwarf-2
# Needed for relocation
LDFLAGS_FINAL += -pie

View File

@@ -16,7 +16,11 @@ typedef int __kernel_pid_t;
typedef unsigned short __kernel_ipc_pid_t;
typedef unsigned short __kernel_uid_t;
typedef unsigned short __kernel_gid_t;
#ifdef __GNUC__
typedef __SIZE_TYPE__ __kernel_size_t;
#else
typedef unsigned int __kernel_size_t;
#endif
typedef int __kernel_ssize_t;
typedef int __kernel_ptrdiff_t;
typedef long __kernel_time_t;

679
arch/arm/Kconfig Normal file
View File

@@ -0,0 +1,679 @@
menu "ARM architecture"
depends on ARM
config SYS_ARCH
string
default "arm"
choice
prompt "Target select"
config TARGET_INTEGRATORAP_CM720T
bool "Support integratorap_cm720t"
config TARGET_INTEGRATORAP_CM920T
bool "Support integratorap_cm920t"
config TARGET_INTEGRATORCP_CM920T
bool "Support integratorcp_cm920t"
config TARGET_A320EVB
bool "Support a320evb"
config TARGET_AT91RM9200EK
bool "Support at91rm9200ek"
config TARGET_EB_CPUX9K2
bool "Support eb_cpux9k2"
config TARGET_CPUAT91
bool "Support cpuat91"
config TARGET_EDB93XX
bool "Support edb93xx"
config TARGET_SCB9328
bool "Support scb9328"
config TARGET_CM4008
bool "Support cm4008"
config TARGET_CM41XX
bool "Support cm41xx"
config TARGET_VCMA9
bool "Support VCMA9"
config TARGET_SMDK2410
bool "Support smdk2410"
config TARGET_INTEGRATORAP_CM926EJS
bool "Support integratorap_cm926ejs"
config TARGET_INTEGRATORCP_CM926EJS
bool "Support integratorcp_cm926ejs"
config TARGET_ASPENITE
bool "Support aspenite"
config TARGET_GPLUGD
bool "Support gplugd"
config TARGET_AFEB9260
bool "Support afeb9260"
config TARGET_AT91SAM9260EK
bool "Support at91sam9260ek"
config TARGET_AT91SAM9261EK
bool "Support at91sam9261ek"
config TARGET_AT91SAM9263EK
bool "Support at91sam9263ek"
config TARGET_AT91SAM9M10G45EK
bool "Support at91sam9m10g45ek"
config TARGET_AT91SAM9N12EK
bool "Support at91sam9n12ek"
config TARGET_AT91SAM9RLEK
bool "Support at91sam9rlek"
config TARGET_AT91SAM9X5EK
bool "Support at91sam9x5ek"
config TARGET_SNAPPER9260
bool "Support snapper9260"
config TARGET_VL_MA2SC
bool "Support vl_ma2sc"
config TARGET_SBC35_A9G20
bool "Support sbc35_a9g20"
config TARGET_TNY_A9260
bool "Support tny_a9260"
config TARGET_USB_A9263
bool "Support usb_a9263"
config TARGET_ETHERNUT5
bool "Support ethernut5"
config TARGET_TOP9000
bool "Support top9000"
config TARGET_MEESC
bool "Support meesc"
config TARGET_OTC570
bool "Support otc570"
config TARGET_CPU9260
bool "Support cpu9260"
config TARGET_PM9261
bool "Support pm9261"
config TARGET_PM9263
bool "Support pm9263"
config TARGET_PM9G45
bool "Support pm9g45"
config TARGET_CORVUS
bool "Support corvus"
config TARGET_TAURUS
bool "Support taurus"
config TARGET_STAMP9G20
bool "Support stamp9g20"
config ARCH_DAVINCI
bool "TI DaVinci"
help
Support for TI's DaVinci platform.
config KIRKWOOD
bool "Marvell Kirkwood"
config TARGET_DEVKIT3250
bool "Support devkit3250"
config TARGET_JADECPU
bool "Support jadecpu"
config TARGET_MX25PDK
bool "Support mx25pdk"
config TARGET_TX25
bool "Support tx25"
config TARGET_ZMX25
bool "Support zmx25"
config TARGET_APF27
bool "Support apf27"
config TARGET_IMX27LITE
bool "Support imx27lite"
config TARGET_MAGNESIUM
bool "Support magnesium"
config TARGET_APX4DEVKIT
bool "Support apx4devkit"
config TARGET_XFI3
bool "Support xfi3"
config TARGET_M28EVK
bool "Support m28evk"
config TARGET_MX23EVK
bool "Support mx23evk"
config TARGET_MX28EVK
bool "Support mx28evk"
config TARGET_MX23_OLINUXINO
bool "Support mx23_olinuxino"
config TARGET_BG0900
bool "Support bg0900"
config TARGET_SANSA_FUZE_PLUS
bool "Support sansa_fuze_plus"
config TARGET_SC_SPS_1
bool "Support sc_sps_1"
config ARCH_NOMADIK
bool "ST-Ericsson Nomadik"
config ORION5X
bool "Marvell Orion"
config TARGET_DKB
bool "Support dkb"
config TARGET_SPEAR300
bool "Support spear300"
config TARGET_SPEAR310
bool "Support spear310"
config TARGET_SPEAR320
bool "Support spear320"
config TARGET_SPEAR600
bool "Support spear600"
config TARGET_X600
bool "Support x600"
config ARCH_VERSATILE
bool "ARM Ltd. Versatile family"
config TARGET_INTEGRATORCP_CM1136
bool "Support integratorcp_cm1136"
config TARGET_IMX31_PHYCORE
bool "Support imx31_phycore"
config TARGET_QONG
bool "Support qong"
config TARGET_MX31ADS
bool "Support mx31ads"
config TARGET_MX31PDK
bool "Support mx31pdk"
config TARGET_TT01
bool "Support tt01"
config TARGET_IMX31_LITEKIT
bool "Support imx31_litekit"
config TARGET_WOODBURN
bool "Support woodburn"
config TARGET_WOODBURN_SD
bool "Support woodburn_sd"
config TARGET_FLEA3
bool "Support flea3"
config TARGET_MX35PDK
bool "Support mx35pdk"
config TARGET_RPI_B
bool "Support rpi_b"
config TARGET_TNETV107X_EVM
bool "Support tnetv107x_evm"
config TARGET_INTEGRATORAP_CM946ES
bool "Support integratorap_cm946es"
config TARGET_INTEGRATORCP_CM946ES
bool "Support integratorcp_cm946es"
config TARGET_VEXPRESS_CA15_TC2
bool "Support vexpress_ca15_tc2"
config TARGET_VEXPRESS_CA5X2
bool "Support vexpress_ca5x2"
config TARGET_VEXPRESS_CA9X4
bool "Support vexpress_ca9x4"
config TARGET_KWB
bool "Support kwb"
config TARGET_TSERIES
bool "Support tseries"
config TARGET_CM_T335
bool "Support cm_t335"
config TARGET_PEPPER
bool "Support pepper"
config TARGET_AM335X_IGEP0033
bool "Support am335x_igep0033"
config TARGET_PCM051
bool "Support pcm051"
config TARGET_DRACO
bool "Support draco"
config TARGET_DXR2
bool "Support dxr2"
config TARGET_PXM2
bool "Support pxm2"
config TARGET_RUT
bool "Support rut"
config TARGET_PENGWYN
bool "Support pengwyn"
config TARGET_AM335X_EVM
bool "Support am335x_evm"
config TARGET_AM43XX_EVM
bool "Support am43xx_evm"
config TARGET_TI814X_EVM
bool "Support ti814x_evm"
config TARGET_TI816X_EVM
bool "Support ti816x_evm"
config TARGET_SAMA5D3_XPLAINED
bool "Support sama5d3_xplained"
config TARGET_SAMA5D3XEK
bool "Support sama5d3xek"
config TARGET_BCM28155_AP
bool "Support bcm28155_ap"
config TARGET_BCM958300K
bool "Support bcm958300k"
config TARGET_BCM958622HR
bool "Support bcm958622hr"
config ARCH_EXYNOS
bool "Samsung EXYNOS"
config ARCH_HIGHBANK
bool "Calxeda Highbank"
config ARCH_KEYSTONE
bool "TI Keystone"
config TARGET_M53EVK
bool "Support m53evk"
config TARGET_IMA3_MX53
bool "Support ima3-mx53"
config TARGET_MX51EVK
bool "Support mx51evk"
config TARGET_MX53ARD
bool "Support mx53ard"
config TARGET_MX53EVK
bool "Support mx53evk"
config TARGET_MX53LOCO
bool "Support mx53loco"
config TARGET_MX53SMD
bool "Support mx53smd"
config TARGET_MX51_EFIKAMX
bool "Support mx51_efikamx"
config TARGET_VISION2
bool "Support vision2"
config TARGET_UDOO
bool "Support udoo"
config TARGET_WANDBOARD
bool "Support wandboard"
config TARGET_TITANIUM
bool "Support titanium"
config TARGET_NITROGEN6X
bool "Support nitrogen6x"
config TARGET_CGTQMX6EVAL
bool "Support cgtqmx6eval"
config TARGET_EMBESTMX6BOARDS
bool "Support embestmx6boards"
config TARGET_ARISTAINETOS
bool "Support aristainetos"
config TARGET_MX6QARM2
bool "Support mx6qarm2"
config TARGET_MX6QSABREAUTO
bool "Support mx6qsabreauto"
config TARGET_MX6SABRESD
bool "Support mx6sabresd"
config TARGET_MX6SLEVK
bool "Support mx6slevk"
config TARGET_MX6SXSABRESD
bool "Support mx6sxsabresd"
config TARGET_GW_VENTANA
bool "Support gw_ventana"
config TARGET_HUMMINGBOARD
bool "Support hummingboard"
config TARGET_TQMA6
bool "TQ Systems TQMa6 board"
config OMAP34XX
bool "OMAP34XX SoC"
config OMAP44XX
bool "OMAP44XX SoC"
config OMAP54XX
bool "OMAP54XX SoC"
config RMOBILE
bool "Renesas ARM SoCs"
config TARGET_S5P_GONI
bool "Support s5p_goni"
config TARGET_SMDKC100
bool "Support smdkc100"
config TARGET_SOCFPGA_CYCLONE5
bool "Support socfpga_cyclone5"
config TARGET_SUN4I
bool "Support sun4i"
config TARGET_SUN5I
bool "Support sun5i"
config TARGET_SUN7I
bool "Support sun7i"
config TARGET_SNOWBALL
bool "Support snowball"
config TARGET_U8500_HREF
bool "Support u8500_href"
config TARGET_VF610TWR
bool "Support vf610twr"
config ZYNQ
bool "Xilinx Zynq Platform"
config TEGRA
bool "NVIDIA Tegra"
select SPL
config TARGET_VEXPRESS_AEMV8A
bool "Support vexpress_aemv8a"
config TARGET_VEXPRESS_AEMV8A_SEMI
bool "Support vexpress_aemv8a_semi"
config TARGET_LS2085A_EMU
bool "Support ls2085a_emu"
config TARGET_LS2085A_SIMU
bool "Support ls2085a_simu"
config TARGET_BALLOON3
bool "Support balloon3"
config TARGET_H2200
bool "Support h2200"
config TARGET_PALMLD
bool "Support palmld"
config TARGET_PALMTC
bool "Support palmtc"
config TARGET_PALMTREO680
bool "Support palmtreo680"
config TARGET_PXA255_IDP
bool "Support pxa255_idp"
config TARGET_TRIZEPSIV
bool "Support trizepsiv"
config TARGET_VPAC270
bool "Support vpac270"
config TARGET_XAENIAX
bool "Support xaeniax"
config TARGET_ZIPITZ2
bool "Support zipitz2"
config TARGET_LP8X4X
bool "Support lp8x4x"
config TARGET_COLIBRI_PXA270
bool "Support colibri_pxa270"
config TARGET_JORNADA
bool "Support jornada"
endchoice
source "arch/arm/cpu/arm926ejs/davinci/Kconfig"
source "arch/arm/cpu/armv7/exynos/Kconfig"
source "arch/arm/cpu/armv7/highbank/Kconfig"
source "arch/arm/cpu/armv7/keystone/Kconfig"
source "arch/arm/cpu/arm926ejs/kirkwood/Kconfig"
source "arch/arm/cpu/arm926ejs/nomadik/Kconfig"
source "arch/arm/cpu/armv7/omap3/Kconfig"
source "arch/arm/cpu/armv7/omap4/Kconfig"
source "arch/arm/cpu/armv7/omap5/Kconfig"
source "arch/arm/cpu/arm926ejs/orion5x/Kconfig"
source "arch/arm/cpu/armv7/rmobile/Kconfig"
source "arch/arm/cpu/armv7/tegra-common/Kconfig"
source "arch/arm/cpu/arm926ejs/versatile/Kconfig"
source "arch/arm/cpu/armv7/zynq/Kconfig"
source "board/aristainetos/Kconfig"
source "board/BuR/kwb/Kconfig"
source "board/BuR/tseries/Kconfig"
source "board/BuS/eb_cpux9k2/Kconfig"
source "board/BuS/vl_ma2sc/Kconfig"
source "board/CarMediaLab/flea3/Kconfig"
source "board/Marvell/aspenite/Kconfig"
source "board/Marvell/dkb/Kconfig"
source "board/Marvell/gplugd/Kconfig"
source "board/afeb9260/Kconfig"
source "board/altera/socfpga/Kconfig"
source "board/armadeus/apf27/Kconfig"
source "board/armltd/integrator/Kconfig"
source "board/armltd/vexpress/Kconfig"
source "board/armltd/vexpress64/Kconfig"
source "board/atmel/at91rm9200ek/Kconfig"
source "board/atmel/at91sam9260ek/Kconfig"
source "board/atmel/at91sam9261ek/Kconfig"
source "board/atmel/at91sam9263ek/Kconfig"
source "board/atmel/at91sam9m10g45ek/Kconfig"
source "board/atmel/at91sam9n12ek/Kconfig"
source "board/atmel/at91sam9rlek/Kconfig"
source "board/atmel/at91sam9x5ek/Kconfig"
source "board/atmel/sama5d3_xplained/Kconfig"
source "board/atmel/sama5d3xek/Kconfig"
source "board/balloon3/Kconfig"
source "board/barco/titanium/Kconfig"
source "board/bluegiga/apx4devkit/Kconfig"
source "board/bluewater/snapper9260/Kconfig"
source "board/boundary/nitrogen6x/Kconfig"
source "board/broadcom/bcm28155_ap/Kconfig"
source "board/broadcom/bcm958300k/Kconfig"
source "board/broadcom/bcm958622hr/Kconfig"
source "board/calao/sbc35_a9g20/Kconfig"
source "board/calao/tny_a9260/Kconfig"
source "board/calao/usb_a9263/Kconfig"
source "board/cirrus/edb93xx/Kconfig"
source "board/cm4008/Kconfig"
source "board/cm41xx/Kconfig"
source "board/compulab/cm_t335/Kconfig"
source "board/congatec/cgtqmx6eval/Kconfig"
source "board/creative/xfi3/Kconfig"
source "board/davedenx/qong/Kconfig"
source "board/denx/m28evk/Kconfig"
source "board/denx/m53evk/Kconfig"
source "board/egnite/ethernut5/Kconfig"
source "board/embest/mx6boards/Kconfig"
source "board/emk/top9000/Kconfig"
source "board/esd/meesc/Kconfig"
source "board/esd/otc570/Kconfig"
source "board/esg/ima3-mx53/Kconfig"
source "board/eukrea/cpu9260/Kconfig"
source "board/eukrea/cpuat91/Kconfig"
source "board/faraday/a320evb/Kconfig"
source "board/freescale/ls2085a/Kconfig"
source "board/freescale/mx23evk/Kconfig"
source "board/freescale/mx25pdk/Kconfig"
source "board/freescale/mx28evk/Kconfig"
source "board/freescale/mx31ads/Kconfig"
source "board/freescale/mx31pdk/Kconfig"
source "board/freescale/mx35pdk/Kconfig"
source "board/freescale/mx51evk/Kconfig"
source "board/freescale/mx53ard/Kconfig"
source "board/freescale/mx53evk/Kconfig"
source "board/freescale/mx53loco/Kconfig"
source "board/freescale/mx53smd/Kconfig"
source "board/freescale/mx6qarm2/Kconfig"
source "board/freescale/mx6qsabreauto/Kconfig"
source "board/freescale/mx6sabresd/Kconfig"
source "board/freescale/mx6slevk/Kconfig"
source "board/freescale/mx6sxsabresd/Kconfig"
source "board/freescale/vf610twr/Kconfig"
source "board/gateworks/gw_ventana/Kconfig"
source "board/genesi/mx51_efikamx/Kconfig"
source "board/gumstix/pepper/Kconfig"
source "board/h2200/Kconfig"
source "board/hale/tt01/Kconfig"
source "board/icpdas/lp8x4x/Kconfig"
source "board/imx31_phycore/Kconfig"
source "board/isee/igep0033/Kconfig"
source "board/jornada/Kconfig"
source "board/karo/tx25/Kconfig"
source "board/logicpd/imx27lite/Kconfig"
source "board/logicpd/imx31_litekit/Kconfig"
source "board/mpl/vcma9/Kconfig"
source "board/olimex/mx23_olinuxino/Kconfig"
source "board/palmld/Kconfig"
source "board/palmtc/Kconfig"
source "board/palmtreo680/Kconfig"
source "board/phytec/pcm051/Kconfig"
source "board/ppcag/bg0900/Kconfig"
source "board/pxa255_idp/Kconfig"
source "board/raspberrypi/rpi_b/Kconfig"
source "board/ronetix/pm9261/Kconfig"
source "board/ronetix/pm9263/Kconfig"
source "board/ronetix/pm9g45/Kconfig"
source "board/samsung/goni/Kconfig"
source "board/samsung/smdk2410/Kconfig"
source "board/samsung/smdkc100/Kconfig"
source "board/sandisk/sansa_fuze_plus/Kconfig"
source "board/scb9328/Kconfig"
source "board/schulercontrol/sc_sps_1/Kconfig"
source "board/siemens/corvus/Kconfig"
source "board/siemens/draco/Kconfig"
source "board/siemens/pxm2/Kconfig"
source "board/siemens/rut/Kconfig"
source "board/siemens/taurus/Kconfig"
source "board/silica/pengwyn/Kconfig"
source "board/solidrun/hummingboard/Kconfig"
source "board/spear/spear300/Kconfig"
source "board/spear/spear310/Kconfig"
source "board/spear/spear320/Kconfig"
source "board/spear/spear600/Kconfig"
source "board/spear/x600/Kconfig"
source "board/st-ericsson/snowball/Kconfig"
source "board/st-ericsson/u8500/Kconfig"
source "board/sunxi/Kconfig"
source "board/syteco/jadecpu/Kconfig"
source "board/syteco/zmx25/Kconfig"
source "board/taskit/stamp9g20/Kconfig"
source "board/ti/am335x/Kconfig"
source "board/ti/am43xx/Kconfig"
source "board/ti/ti814x/Kconfig"
source "board/ti/ti816x/Kconfig"
source "board/ti/tnetv107xevm/Kconfig"
source "board/timll/devkit3250/Kconfig"
source "board/toradex/colibri_pxa270/Kconfig"
source "board/tqc/tqma6/Kconfig"
source "board/trizepsiv/Kconfig"
source "board/ttcontrol/vision2/Kconfig"
source "board/udoo/Kconfig"
source "board/vpac270/Kconfig"
source "board/wandboard/Kconfig"
source "board/woodburn/Kconfig"
source "board/xaeniax/Kconfig"
source "board/zipitz2/Kconfig"
endmenu

View File

@@ -22,7 +22,7 @@ PLATFORM_RELFLAGS += $(call cc-option, -msoft-float) \
# Support generic board on ARM
__HAVE_ARCH_GENERIC_BOARD := y
PLATFORM_CPPFLAGS += -DCONFIG_ARM -D__ARM__
PLATFORM_CPPFLAGS += -D__ARM__
# Choose between ARM/Thumb instruction sets
ifeq ($(CONFIG_SYS_THUMB_BUILD),y)
@@ -113,7 +113,7 @@ endif
ifdef CONFIG_ARM64
OBJCOPYFLAGS += -j .text -j .rodata -j .data -j .u_boot_list -j .rela.dyn
else
OBJCOPYFLAGS += -j .text -j .rodata -j .hash -j .data -j .got.plt -j .u_boot_list -j .rel.dyn
OBJCOPYFLAGS += -j .text -j .secure_text -j .rodata -j .hash -j .data -j .got.plt -j .u_boot_list -j .rel.dyn
endif
ifdef CONFIG_OF_EMBED

View File

@@ -22,6 +22,7 @@ SECTIONS
.text :
{
__start = .;
*(.vectors)
arch/arm/cpu/arm1136/start.o (.text*)
*(.text*)
} >.sram

View File

@@ -1,58 +0,0 @@
/*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = ALIGN(4);
.text :
{
*(.__image_copy_start)
*(.vectors)
arch/arm/cpu/arm920t/start.o (.text*)
/* the EP93xx expects to find the pattern 'CRUS' at 0x1000 */
. = 0x1000;
LONG(0x53555243)
*(.text*)
}
. = ALIGN(4);
.rodata : { *(.rodata*) }
. = ALIGN(4);
.data : { *(.data*) }
. = ALIGN(4);
.got : { *(.got) }
. = .;
. = ALIGN(4);
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.image_copy_end :
{
*(.__image_copy_end)
}
__bss_start = .;
.bss : { *(.bss*) }
__bss_end = .;
.end :
{
*(.__end)
}
}

View File

@@ -0,0 +1,79 @@
if ARCH_DAVINCI
choice
prompt "DaVinci board select"
config TARGET_ENBW_CMC
bool "EnBW CMC board"
config TARGET_IPAM390
bool "IPAM390 board"
config TARGET_DA830EVM
bool "DA830 EVM board"
config TARGET_DA850EVM
bool "DA850 EVM board"
config TARGET_CAM_ENC_4XX
bool "CAM ENC 4xx board"
config TARGET_HAWKBOARD
bool "Hawkboard"
config TARGET_DAVINCI_DM355EVM
bool "DM355 EVM board"
config TARGET_DAVINCI_DM355LEOPARD
bool "DM355 Leopard board"
config TARGET_DAVINCI_DM365EVM
bool "DM365 EVM board"
config TARGET_DAVINCI_DM6467EVM
bool "DM6467 EVM board"
config TARGET_DAVINCI_DVEVM
bool "DVEVM board"
config TARGET_EA20
bool "EA20 board"
config TARGET_DAVINCI_SCHMOOGIE
bool "Schmoogie board"
config TARGET_DAVINCI_SFFSDR
bool "SFFSDR board"
config TARGET_DAVINCI_SONATA
bool "Sonata board"
config TARGET_CALIMAIN
bool "Calimain board"
endchoice
config SYS_CPU
string
default "arm926ejs"
config SYS_SOC
string
default "davinci"
source "board/enbw/enbw_cmc/Kconfig"
source "board/ait/cam_enc_4xx/Kconfig"
source "board/Barix/ipam390/Kconfig"
source "board/davinci/da8xxevm/Kconfig"
source "board/davinci/dm355evm/Kconfig"
source "board/davinci/dm355leopard/Kconfig"
source "board/davinci/dm365evm/Kconfig"
source "board/davinci/dm6467evm/Kconfig"
source "board/davinci/dvevm/Kconfig"
source "board/davinci/ea20/Kconfig"
source "board/davinci/schmoogie/Kconfig"
source "board/davinci/sffsdr/Kconfig"
source "board/davinci/sonata/Kconfig"
source "board/omicron/calimain/Kconfig"
endif

View File

@@ -0,0 +1,89 @@
if KIRKWOOD
choice
prompt "Marvell Kirkwood board select"
config TARGET_OPENRD
bool "Marvell OpenRD Board"
config TARGET_MV88F6281GTW_GE
bool "MV88f6281GTW_GE Board"
config TARGET_RD6281A
bool "RD6281A Board"
config TARGET_DREAMPLUG
bool "DreamPlug Board"
config TARGET_GURUPLUG
bool "GuruPlug Board"
config TARGET_SHEEVAPLUG
bool "SheevaPlug Board"
config TARGET_LSXL
bool "lsxl Board"
config TARGET_POGO_E02
bool "pogo_e02 Board"
config TARGET_DNS325
bool "dns325 Board"
config TARGET_ICONNECT
bool "iconnect Board"
config TARGET_TK71
bool "TK71 Board"
config TARGET_KM_KIRKWOOD
bool "KM_KIRKWOOD Board"
config TARGET_NET2BIG_V2
bool "LaCie 2Big Network v2 NAS Board"
config TARGET_NETSPACE_V2
bool "LaCie netspace_v2 Board"
config TARGET_WIRELESS_SPACE
bool "LaCie Wireless_space Board"
config TARGET_IB62X0
bool "ib62x0 Board"
config TARGET_DOCKSTAR
bool "Dockstar Board"
config TARGET_GOFLEXHOME
bool "GoFlex Home Board"
endchoice
config SYS_CPU
string
default "arm926ejs"
config SYS_SOC
string
default "kirkwood"
source "board/Marvell/openrd/Kconfig"
source "board/Marvell/mv88f6281gtw_ge/Kconfig"
source "board/Marvell/rd6281a/Kconfig"
source "board/Marvell/dreamplug/Kconfig"
source "board/Marvell/guruplug/Kconfig"
source "board/Marvell/sheevaplug/Kconfig"
source "board/buffalo/lsxl/Kconfig"
source "board/cloudengines/pogo_e02/Kconfig"
source "board/d-link/dns325/Kconfig"
source "board/iomega/iconnect/Kconfig"
source "board/karo/tk71/Kconfig"
source "board/keymile/km_arm/Kconfig"
source "board/LaCie/net2big_v2/Kconfig"
source "board/LaCie/netspace_v2/Kconfig"
source "board/LaCie/wireless_space/Kconfig"
source "board/raidsonic/ib62x0/Kconfig"
source "board/Seagate/dockstar/Kconfig"
source "board/Seagate/goflexhome/Kconfig"
endif

View File

@@ -13,6 +13,7 @@
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/kirkwood.h>
#include <mvebu_mmc.h>
#define BUFLEN 16
@@ -377,3 +378,11 @@ int cpu_eth_init(bd_t *bis)
return 0;
}
#endif
#ifdef CONFIG_MVEBU_MMC
int board_mmc_init(bd_t *bis)
{
mvebu_mmc_init(bis);
return 0;
}
#endif /* CONFIG_MVEBU_MMC */

View File

@@ -21,6 +21,7 @@ SECTIONS
. = ALIGN(4);
.text :
{
*(.vectors)
arch/arm/cpu/arm926ejs/mxs/start.o (.text*)
*(.text*)
}

View File

@@ -0,0 +1,21 @@
if ARCH_NOMADIK
choice
prompt "Nomadik board select"
config NOMADIK_NHK8815
bool "ST 8815 Nomadik Hardware Kit"
endchoice
config SYS_CPU
string
default "arm926ejs"
config SYS_SOC
string
default "nomadik"
source "board/st/nhk8815/Kconfig"
endif

View File

@@ -0,0 +1,21 @@
if ORION5X
choice
prompt "Marvell Orion board select"
config TARGET_EDMINIV2
bool "LaCie Ethernet Disk mini V2"
endchoice
config SYS_CPU
string
default "arm926ejs"
config SYS_SOC
string
default "orion5x"
source "board/LaCie/edminiv2/Kconfig"
endif

View File

@@ -0,0 +1,23 @@
if ARCH_VERSATILE
config SYS_CPU
string
default "arm926ejs"
config SYS_BOARD
string
default "versatile"
config SYS_VENDOR
string
default "armltd"
config SYS_SOC
string
default "versatile"
config SYS_CONFIG_NAME
string
default "versatile"
endif

View File

@@ -21,8 +21,14 @@ endif
ifneq ($(CONFIG_ARMV7_NONSEC)$(CONFIG_ARMV7_VIRT),)
obj-y += nonsec_virt.o
obj-y += virt-v7.o
obj-y += virt-dt.o
endif
ifneq ($(CONFIG_ARMV7_PSCI),)
obj-y += psci.o
endif
obj-$(CONFIG_IPROC) += iproc-common/
obj-$(CONFIG_KONA) += kona-common/
obj-$(CONFIG_OMAP_COMMON) += omap-common/
obj-$(CONFIG_SYS_ARCH_TIMER) += arch_timer.o

View File

@@ -22,6 +22,7 @@ SECTIONS
.text :
{
__start = .;
*(.vectors)
arch/arm/cpu/armv7/start.o (.text)
*(.text*)
} >.sram

View File

@@ -9,3 +9,4 @@ obj-y += clk-core.o
obj-y += clk-bcm281xx.o
obj-y += clk-sdio.o
obj-y += clk-bsc.o
obj-$(CONFIG_BCM_SF2_ETH) += clk-eth.o

View File

@@ -118,6 +118,16 @@ unsigned long slave_apb_freq_tbl[8] = {
78 * CLOCK_1M
};
unsigned long esub_freq_tbl[8] = {
78 * CLOCK_1M,
156 * CLOCK_1M,
156 * CLOCK_1M,
156 * CLOCK_1M,
208 * CLOCK_1M,
208 * CLOCK_1M,
208 * CLOCK_1M
};
static struct bus_clk_data bsc1_apb_data = {
.gate = HW_SW_GATE_AUTO(0x0458, 16, 0, 1),
};
@@ -295,6 +305,27 @@ static struct ccu_clock kps_ccu_clk = {
.freq_tbl = slave_axi_freq_tbl,
};
#ifdef CONFIG_BCM_SF2_ETH
static struct ccu_clock esub_ccu_clk = {
.clk = {
.name = "esub_ccu_clk",
.ops = &ccu_clk_ops,
.ccu_clk_mgr_base = ESUB_CLK_BASE_ADDR,
},
.num_policy_masks = 1,
.policy_freq_offset = 0x00000008,
.freq_bit_shift = 8,
.policy_ctl_offset = 0x0000000c,
.policy0_mask_offset = 0x00000010,
.policy1_mask_offset = 0x00000014,
.policy2_mask_offset = 0x00000018,
.policy3_mask_offset = 0x0000001c,
.lvm_en_offset = 0x00000034,
.freq_id = 2,
.freq_tbl = esub_freq_tbl,
};
#endif
/*
* Bus clocks
*/
@@ -517,6 +548,9 @@ struct clk_lookup arch_clk_tbl[] = {
CLK_LK(bsc1_apb),
CLK_LK(bsc2_apb),
CLK_LK(bsc3_apb),
#ifdef CONFIG_BCM_SF2_ETH
CLK_LK(esub_ccu),
#endif
};
/* public array size */

View File

@@ -0,0 +1,143 @@
/*
* Copyright 2014 Broadcom Corporation.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/arch/sysmap.h>
#include <asm/kona-common/clk.h>
#include "clk-core.h"
#define WR_ACCESS_ADDR ESUB_CLK_BASE_ADDR
#define WR_ACCESS_PASSWORD 0xA5A500
#define PLLE_POST_RESETB_ADDR (ESUB_CLK_BASE_ADDR + 0x00000C00)
#define PLLE_RESETB_ADDR (ESUB_CLK_BASE_ADDR + 0x00000C58)
#define PLLE_RESETB_I_PLL_RESETB_PLLE_MASK 0x00010000
#define PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK 0x00000001
#define PLL_LOCK_ADDR (ESUB_CLK_BASE_ADDR + 0x00000C38)
#define PLL_LOCK_PLL_LOCK_PLLE_MASK 0x00000001
#define ESW_SYS_DIV_ADDR (ESUB_CLK_BASE_ADDR + 0x00000A04)
#define ESW_SYS_DIV_PLL_SELECT_MASK 0x00000300
#define ESW_SYS_DIV_DIV_MASK 0x0000001C
#define ESW_SYS_DIV_PLL_VAR_208M_CLK_SELECT 0x00000100
#define ESW_SYS_DIV_DIV_SELECT 0x4
#define ESW_SYS_DIV_TRIGGER_MASK 0x00000001
#define ESUB_AXI_DIV_DEBUG_ADDR (ESUB_CLK_BASE_ADDR + 0x00000E04)
#define ESUB_AXI_DIV_DEBUG_PLL_SELECT_MASK 0x0000001C
#define ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK 0x00000040
#define ESUB_AXI_DIV_DEBUG_PLL_VAR_208M_CLK_SELECT 0x0
#define ESUB_AXI_DIV_DEBUG_TRIGGER_MASK 0x00000001
#define PLL_MAX_RETRY 100
/* Enable appropriate clocks for Ethernet */
int clk_eth_enable(void)
{
int rc = -1;
int retry_count = 0;
rc = clk_get_and_enable("esub_ccu_clk");
/* Enable Access to CCU registers */
writel((1 | WR_ACCESS_PASSWORD), WR_ACCESS_ADDR);
writel(readl(PLLE_POST_RESETB_ADDR) &
~PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK,
PLLE_POST_RESETB_ADDR);
/* Take PLL out of reset and put into normal mode */
writel(readl(PLLE_RESETB_ADDR) | PLLE_RESETB_I_PLL_RESETB_PLLE_MASK,
PLLE_RESETB_ADDR);
/* Wait for PLL lock */
rc = -1;
while (retry_count < PLL_MAX_RETRY) {
udelay(100);
if (readl(PLL_LOCK_ADDR) & PLL_LOCK_PLL_LOCK_PLLE_MASK) {
rc = 0;
break;
}
retry_count++;
}
if (rc == -1) {
printf("%s: ETH-PLL lock timeout, Ethernet is not enabled!\n",
__func__);
return -1;
}
writel(readl(PLLE_POST_RESETB_ADDR) |
PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK,
PLLE_POST_RESETB_ADDR);
/* Switch esw_sys_clk to use 104MHz(208MHz/2) clock */
writel((readl(ESW_SYS_DIV_ADDR) &
~(ESW_SYS_DIV_PLL_SELECT_MASK | ESW_SYS_DIV_DIV_MASK)) |
ESW_SYS_DIV_PLL_VAR_208M_CLK_SELECT | ESW_SYS_DIV_DIV_SELECT,
ESW_SYS_DIV_ADDR);
writel(readl(ESW_SYS_DIV_ADDR) | ESW_SYS_DIV_TRIGGER_MASK,
ESW_SYS_DIV_ADDR);
/* Wait for trigger complete */
rc = -1;
retry_count = 0;
while (retry_count < PLL_MAX_RETRY) {
udelay(100);
if (!(readl(ESW_SYS_DIV_ADDR) & ESW_SYS_DIV_TRIGGER_MASK)) {
rc = 0;
break;
}
retry_count++;
}
if (rc == -1) {
printf("%s: SYS CLK Trigger timeout, Ethernet is not enabled!\n",
__func__);
return -1;
}
/* switch Esub AXI clock to 208MHz */
writel((readl(ESUB_AXI_DIV_DEBUG_ADDR) &
~(ESUB_AXI_DIV_DEBUG_PLL_SELECT_MASK |
ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK |
ESUB_AXI_DIV_DEBUG_TRIGGER_MASK)) |
ESUB_AXI_DIV_DEBUG_PLL_VAR_208M_CLK_SELECT |
ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK,
ESUB_AXI_DIV_DEBUG_ADDR);
writel(readl(ESUB_AXI_DIV_DEBUG_ADDR) |
ESUB_AXI_DIV_DEBUG_TRIGGER_MASK,
ESUB_AXI_DIV_DEBUG_ADDR);
/* Wait for trigger complete */
rc = -1;
retry_count = 0;
while (retry_count < PLL_MAX_RETRY) {
udelay(100);
if (!(readl(ESUB_AXI_DIV_DEBUG_ADDR) &
ESUB_AXI_DIV_DEBUG_TRIGGER_MASK)) {
rc = 0;
break;
}
retry_count++;
}
if (rc == -1) {
printf("%s: AXI CLK Trigger timeout, Ethernet is not enabled!\n",
__func__);
return -1;
}
/* Disable Access to CCU registers */
writel(WR_ACCESS_PASSWORD, WR_ACCESS_ADDR);
return rc;
}

View File

@@ -0,0 +1,7 @@
#
# Copyright 2014 Broadcom Corporation.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += reset.o

View File

@@ -0,0 +1,20 @@
/*
* Copyright 2014 Broadcom Corporation.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#define CRMU_MAIL_BOX1 0x03024028
#define CRMU_SOFT_RESET_CMD 0xFFFFFFFF
void reset_cpu(ulong ignored)
{
/* Send soft reset command via Mailbox. */
writel(CRMU_SOFT_RESET_CMD, CRMU_MAIL_BOX1);
while (1)
; /* loop forever till reset */
}

View File

@@ -0,0 +1,7 @@
#
# Copyright 2014 Broadcom Corporation.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += reset.o

View File

@@ -0,0 +1,19 @@
/*
* Copyright 2014 Broadcom Corporation.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#define CRU_RESET_OFFSET 0x1803F184
void reset_cpu(ulong ignored)
{
/* Reset the cpu by setting software reset request bit */
writel(0x1, CRU_RESET_OFFSET);
while (1)
; /* loop forever till reset */
}

View File

@@ -0,0 +1,55 @@
if ARCH_EXYNOS
choice
prompt "EXYNOS board select"
config TARGET_SMDKV310
bool "Exynos4210 SMDKV310 board"
config TARGET_TRATS
bool "Exynos4210 Trats board"
config TARGET_S5PC210_UNIVERSAL
bool "EXYNOS4210 Universal C210 board"
config TARGET_ORIGEN
bool "Exynos4412 Origen board"
config TARGET_TRATS2
bool "Exynos4412 Trat2 board"
config TARGET_ARNDALE
bool "Exynos5250 Arndale board"
config TARGET_SMDK5250
bool "SMDK5250 board"
config TARGET_SNOW
bool "Snow board"
config TARGET_SMDK5420
bool "SMDK5420 board"
config TARGET_PEACH_PIT
bool "Peach Pi board"
endchoice
config SYS_CPU
string
default "armv7"
config SYS_SOC
string
default "exynos"
source "board/samsung/smdkv310/Kconfig"
source "board/samsung/trats/Kconfig"
source "board/samsung/universal_c210/Kconfig"
source "board/samsung/origen/Kconfig"
source "board/samsung/trats2/Kconfig"
source "board/samsung/arndale/Kconfig"
source "board/samsung/smdk5250/Kconfig"
source "board/samsung/smdk5420/Kconfig"
endif

View File

@@ -0,0 +1,19 @@
if ARCH_HIGHBANK
config SYS_CPU
string
default "armv7"
config SYS_BOARD
string
default "highbank"
config SYS_SOC
string
default "highbank"
config SYS_CONFIG_NAME
string
default "highbank"
endif

View File

@@ -0,0 +1,9 @@
#
# Copyright 2014 Broadcom Corporation.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += armpll.o
obj-y += hwinit-common.o
obj-y += timer.o

View File

@@ -0,0 +1,170 @@
/*
* Copyright 2014 Broadcom Corporation.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/iproc-common/armpll.h>
#include <asm/iproc-common/sysmap.h>
#define NELEMS(x) (sizeof(x) / sizeof(x[0]))
struct armpll_parameters {
unsigned int mode;
unsigned int ndiv_int;
unsigned int ndiv_frac;
unsigned int pdiv;
unsigned int freqid;
};
struct armpll_parameters armpll_clk_tab[] = {
{ 25, 64, 1, 1, 0},
{ 100, 64, 1, 1, 2},
{ 400, 64, 1, 1, 6},
{ 448, 71, 713050, 1, 6},
{ 500, 80, 1, 1, 6},
{ 560, 89, 629145, 1, 6},
{ 600, 96, 1, 1, 6},
{ 800, 64, 1, 1, 7},
{ 896, 71, 713050, 1, 7},
{ 1000, 80, 1, 1, 7},
{ 1100, 88, 1, 1, 7},
{ 1120, 89, 629145, 1, 7},
{ 1200, 96, 1, 1, 7},
};
uint32_t armpll_config(uint32_t clkmhz)
{
uint32_t freqid;
uint32_t ndiv_frac;
uint32_t pll;
uint32_t status = 1;
uint32_t timeout_countdown;
int i;
for (i = 0; i < NELEMS(armpll_clk_tab); i++) {
if (armpll_clk_tab[i].mode == clkmhz) {
status = 0;
break;
}
}
if (status) {
printf("Error: Clock configuration not supported\n");
goto armpll_config_done;
}
/* Enable write access */
writel(IPROC_REG_WRITE_ACCESS, IHOST_PROC_CLK_WR_ACCESS);
if (clkmhz == 25)
freqid = 0;
else
freqid = 2;
/* Bypass ARM clock and run on sysclk */
writel(1 << IHOST_PROC_CLK_POLICY_FREQ__PRIV_ACCESS_MODE |
freqid << IHOST_PROC_CLK_POLICY_FREQ__POLICY3_FREQ_R |
freqid << IHOST_PROC_CLK_POLICY_FREQ__POLICY2_FREQ_R |
freqid << IHOST_PROC_CLK_POLICY_FREQ__POLICY1_FREQ_R |
freqid << IHOST_PROC_CLK_POLICY_FREQ__POLICY0_FREQ_R,
IHOST_PROC_CLK_POLICY_FREQ);
writel(1 << IHOST_PROC_CLK_POLICY_CTL__GO |
1 << IHOST_PROC_CLK_POLICY_CTL__GO_AC,
IHOST_PROC_CLK_POLICY_CTL);
/* Poll CCU until operation complete */
timeout_countdown = 0x100000;
while (readl(IHOST_PROC_CLK_POLICY_CTL) &
(1 << IHOST_PROC_CLK_POLICY_CTL__GO)) {
timeout_countdown--;
if (timeout_countdown == 0) {
printf("CCU polling timedout\n");
status = 1;
goto armpll_config_done;
}
}
if (clkmhz == 25 || clkmhz == 100) {
status = 0;
goto armpll_config_done;
}
/* Now it is safe to program the PLL */
pll = readl(IHOST_PROC_CLK_PLLARMB);
pll &= ~((1 << IHOST_PROC_CLK_PLLARMB__PLLARM_NDIV_FRAC_WIDTH) - 1);
ndiv_frac =
((1 << IHOST_PROC_CLK_PLLARMB__PLLARM_NDIV_FRAC_WIDTH) - 1) &
(armpll_clk_tab[i].ndiv_frac <<
IHOST_PROC_CLK_PLLARMB__PLLARM_NDIV_FRAC_R);
pll |= ndiv_frac;
writel(pll, IHOST_PROC_CLK_PLLARMB);
writel(1 << IHOST_PROC_CLK_PLLARMA__PLLARM_LOCK |
armpll_clk_tab[i].ndiv_int <<
IHOST_PROC_CLK_PLLARMA__PLLARM_NDIV_INT_R |
armpll_clk_tab[i].pdiv <<
IHOST_PROC_CLK_PLLARMA__PLLARM_PDIV_R |
1 << IHOST_PROC_CLK_PLLARMA__PLLARM_SOFT_RESETB,
IHOST_PROC_CLK_PLLARMA);
/* Poll ARM PLL Lock until operation complete */
timeout_countdown = 0x100000;
while (readl(IHOST_PROC_CLK_PLLARMA) &
(1 << IHOST_PROC_CLK_PLLARMA__PLLARM_LOCK)) {
timeout_countdown--;
if (timeout_countdown == 0) {
printf("ARM PLL lock failed\n");
status = 1;
goto armpll_config_done;
}
}
pll = readl(IHOST_PROC_CLK_PLLARMA);
pll |= (1 << IHOST_PROC_CLK_PLLARMA__PLLARM_SOFT_POST_RESETB);
writel(pll, IHOST_PROC_CLK_PLLARMA);
/* Set the policy */
writel(1 << IHOST_PROC_CLK_POLICY_FREQ__PRIV_ACCESS_MODE |
armpll_clk_tab[i].freqid <<
IHOST_PROC_CLK_POLICY_FREQ__POLICY3_FREQ_R |
armpll_clk_tab[i].freqid <<
IHOST_PROC_CLK_POLICY_FREQ__POLICY2_FREQ_R |
armpll_clk_tab[i].freqid <<
IHOST_PROC_CLK_POLICY_FREQ__POLICY1_FREQ_R |
armpll_clk_tab[i+4].freqid <<
IHOST_PROC_CLK_POLICY_FREQ__POLICY0_FREQ_R,
IHOST_PROC_CLK_POLICY_FREQ);
writel(IPROC_CLKCT_HDELAY_SW_EN, IHOST_PROC_CLK_CORE0_CLKGATE);
writel(IPROC_CLKCT_HDELAY_SW_EN, IHOST_PROC_CLK_CORE1_CLKGATE);
writel(IPROC_CLKCT_HDELAY_SW_EN, IHOST_PROC_CLK_ARM_SWITCH_CLKGATE);
writel(IPROC_CLKCT_HDELAY_SW_EN, IHOST_PROC_CLK_ARM_PERIPH_CLKGATE);
writel(IPROC_CLKCT_HDELAY_SW_EN, IHOST_PROC_CLK_APB0_CLKGATE);
writel(1 << IHOST_PROC_CLK_POLICY_CTL__GO |
1 << IHOST_PROC_CLK_POLICY_CTL__GO_AC,
IHOST_PROC_CLK_POLICY_CTL);
/* Poll CCU until operation complete */
timeout_countdown = 0x100000;
while (readl(IHOST_PROC_CLK_POLICY_CTL) &
(1 << IHOST_PROC_CLK_POLICY_CTL__GO)) {
timeout_countdown--;
if (timeout_countdown == 0) {
printf("CCU polling failed\n");
status = 1;
goto armpll_config_done;
}
}
status = 0;
armpll_config_done:
/* Disable access to PLL registers */
writel(0, IHOST_PROC_CLK_WR_ACCESS);
return status;
}

View File

@@ -0,0 +1,15 @@
/*
* Copyright 2014 Broadcom Corporation.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
}
#endif

View File

@@ -0,0 +1,130 @@
/*
* Copyright 2014 Broadcom Corporation.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <div64.h>
#include <asm/io.h>
#include <asm/iproc-common/timer.h>
#include <asm/iproc-common/sysmap.h>
static inline uint64_t timer_global_read(void)
{
uint64_t cur_tick;
uint32_t count_h;
uint32_t count_l;
do {
count_h = readl(IPROC_PERIPH_GLB_TIM_REG_BASE +
TIMER_GLB_HI_OFFSET);
count_l = readl(IPROC_PERIPH_GLB_TIM_REG_BASE +
TIMER_GLB_LOW_OFFSET);
cur_tick = readl(IPROC_PERIPH_GLB_TIM_REG_BASE +
TIMER_GLB_HI_OFFSET);
} while (cur_tick != count_h);
return (cur_tick << 32) + count_l;
}
void timer_global_init(void)
{
writel(0, IPROC_PERIPH_GLB_TIM_REG_BASE + TIMER_GLB_CTRL_OFFSET);
writel(0, IPROC_PERIPH_GLB_TIM_REG_BASE + TIMER_GLB_LOW_OFFSET);
writel(0, IPROC_PERIPH_GLB_TIM_REG_BASE + TIMER_GLB_HI_OFFSET);
writel(TIMER_GLB_TIM_CTRL_TIM_EN,
IPROC_PERIPH_GLB_TIM_REG_BASE + TIMER_GLB_CTRL_OFFSET);
}
int timer_init(void)
{
timer_global_init();
return 0;
}
unsigned long get_timer(unsigned long base)
{
uint64_t count;
uint64_t ret;
uint64_t tim_clk;
uint64_t periph_clk;
count = timer_global_read();
/* default arm clk is 1GHz, periph_clk=arm_clk/2, tick per msec */
periph_clk = 500000;
tim_clk = lldiv(periph_clk,
(((readl(IPROC_PERIPH_GLB_TIM_REG_BASE +
TIMER_GLB_CTRL_OFFSET) &
TIMER_GLB_TIM_CTRL_PRESC_MASK) >> 8) + 1));
ret = lldiv(count, (uint32_t)tim_clk);
/* returns msec */
return ret - base;
}
void __udelay(unsigned long usec)
{
uint64_t cur_tick, end_tick;
uint64_t tim_clk;
uint64_t periph_clk;
/* default arm clk is 1GHz, periph_clk=arm_clk/2, tick per usec */
periph_clk = 500;
tim_clk = lldiv(periph_clk,
(((readl(IPROC_PERIPH_GLB_TIM_REG_BASE +
TIMER_GLB_CTRL_OFFSET) &
TIMER_GLB_TIM_CTRL_PRESC_MASK) >> 8) + 1));
cur_tick = timer_global_read();
end_tick = tim_clk;
end_tick *= usec;
end_tick += cur_tick;
do {
cur_tick = timer_global_read();
} while (cur_tick < end_tick);
}
void timer_systick_init(uint32_t tick_ms)
{
/* Disable timer and clear interrupt status*/
writel(0, IPROC_PERIPH_PVT_TIM_REG_BASE + TIMER_PVT_CTRL_OFFSET);
writel(TIMER_PVT_TIM_INT_STATUS_SET,
IPROC_PERIPH_PVT_TIM_REG_BASE + TIMER_PVT_STATUS_OFFSET);
writel((PLL_AXI_CLK/1000) * tick_ms,
IPROC_PERIPH_PVT_TIM_REG_BASE + TIMER_PVT_LOAD_OFFSET);
writel(TIMER_PVT_TIM_CTRL_INT_EN |
TIMER_PVT_TIM_CTRL_AUTO_RELD |
TIMER_PVT_TIM_CTRL_TIM_EN,
IPROC_PERIPH_PVT_TIM_REG_BASE + TIMER_PVT_CTRL_OFFSET);
}
void timer_systick_isr(void *data)
{
writel(TIMER_PVT_TIM_INT_STATUS_SET,
IPROC_PERIPH_PVT_TIM_REG_BASE + TIMER_PVT_STATUS_OFFSET);
}
/*
* This function is derived from PowerPC code (read timebase as long long).
* On ARM it just returns the timer value in msec.
*/
unsigned long long get_ticks(void)
{
return get_timer(0);
}
/*
* This is used in conjuction with get_ticks, which returns msec as ticks.
* Here we just return ticks/sec = msec/sec = 1000
*/
ulong get_tbclk(void)
{
return 1000;
}

View File

@@ -0,0 +1,24 @@
if ARCH_KEYSTONE
choice
prompt "TI Keystone board select"
config TARGET_K2HK_EVM
bool "TI Keystone 2 Kepler/Hawking EVM"
config TARGET_K2E_EVM
bool "TI Keystone 2 Edison EVM"
endchoice
config SYS_CPU
string
default "armv7"
config SYS_SOC
string
default "keystone"
source "board/ti/ks2_evm/Kconfig"
endif

View File

@@ -8,9 +8,12 @@
obj-y += init.o
obj-y += psc.o
obj-y += clock.o
obj-$(CONFIG_SOC_K2HK) += clock-k2hk.o
obj-$(CONFIG_SOC_K2E) += clock-k2e.o
obj-y += cmd_clock.o
obj-y += cmd_mon.o
obj-y += keystone_nav.o
obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_nav.o
obj-y += msmc.o
obj-$(CONFIG_SPL_BUILD) += spl.o
obj-y += ddr3.o
obj-y += keystone.o

View File

@@ -0,0 +1,117 @@
/*
* Keystone2: get clk rate for K2E
*
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/clock.h>
#include <asm/arch/clock_defs.h>
const struct keystone_pll_regs keystone_pll_regs[] = {
[CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
[PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
[DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
};
int dev_speeds[] = {
SPD800,
SPD850,
SPD1000,
SPD1250,
SPD1350,
SPD1400,
SPD1500,
SPD1400,
SPD1350,
SPD1250,
SPD1000,
SPD850,
SPD800
};
/**
* pll_freq_get - get pll frequency
* Fout = Fref * NF(mult) / NR(prediv) / OD
* @pll: pll identifier
*/
static unsigned long pll_freq_get(int pll)
{
unsigned long mult = 1, prediv = 1, output_div = 2;
unsigned long ret;
u32 tmp, reg;
if (pll == CORE_PLL) {
ret = external_clk[sys_clk];
if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
/* PLL mode */
tmp = __raw_readl(KS2_MAINPLLCTL0);
prediv = (tmp & PLL_DIV_MASK) + 1;
mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
(pllctl_reg_read(pll, mult) &
PLLM_MULT_LO_MASK)) + 1;
output_div = ((pllctl_reg_read(pll, secctl) >>
PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
ret = ret / prediv / output_div * mult;
}
} else {
switch (pll) {
case PASS_PLL:
ret = external_clk[pa_clk];
reg = KS2_PASSPLLCTL0;
break;
case DDR3_PLL:
ret = external_clk[ddr3_clk];
reg = KS2_DDR3APLLCTL0;
break;
default:
return 0;
}
tmp = __raw_readl(reg);
if (!(tmp & PLLCTL_BYPASS)) {
/* Bypass disabled */
prediv = (tmp & PLL_DIV_MASK) + 1;
mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
output_div = ((tmp >> PLL_CLKOD_SHIFT) &
PLL_CLKOD_MASK) + 1;
ret = ((ret / prediv) * mult) / output_div;
}
}
return ret;
}
unsigned long clk_get_rate(unsigned int clk)
{
switch (clk) {
case core_pll_clk: return pll_freq_get(CORE_PLL);
case pass_pll_clk: return pll_freq_get(PASS_PLL);
case ddr3_pll_clk: return pll_freq_get(DDR3_PLL);
case sys_clk0_1_clk:
case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1);
case sys_clk1_clk: return pll_freq_get(CORE_PLL) / pll0div_read(2);
case sys_clk2_clk: return pll_freq_get(CORE_PLL) / pll0div_read(3);
case sys_clk3_clk: return pll_freq_get(CORE_PLL) / pll0div_read(4);
case sys_clk0_2_clk: return clk_get_rate(sys_clk0_clk) / 2;
case sys_clk0_3_clk: return clk_get_rate(sys_clk0_clk) / 3;
case sys_clk0_4_clk: return clk_get_rate(sys_clk0_clk) / 4;
case sys_clk0_6_clk: return clk_get_rate(sys_clk0_clk) / 6;
case sys_clk0_8_clk: return clk_get_rate(sys_clk0_clk) / 8;
case sys_clk0_12_clk: return clk_get_rate(sys_clk0_clk) / 12;
case sys_clk0_24_clk: return clk_get_rate(sys_clk0_clk) / 24;
case sys_clk1_3_clk: return clk_get_rate(sys_clk1_clk) / 3;
case sys_clk1_4_clk: return clk_get_rate(sys_clk1_clk) / 4;
case sys_clk1_6_clk: return clk_get_rate(sys_clk1_clk) / 6;
case sys_clk1_12_clk: return clk_get_rate(sys_clk1_clk) / 12;
default:
break;
}
return 0;
}

View File

@@ -0,0 +1,145 @@
/*
* Keystone2: get clk rate for K2HK
*
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/clock.h>
#include <asm/arch/clock_defs.h>
const struct keystone_pll_regs keystone_pll_regs[] = {
[CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
[PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
[TETRIS_PLL] = {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1},
[DDR3A_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
[DDR3B_PLL] = {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1},
};
int dev_speeds[] = {
SPD800,
SPD1000,
SPD1200,
SPD800,
SPD800,
SPD800,
SPD800,
SPD800,
SPD1200,
SPD1000,
SPD800,
SPD800,
SPD800,
};
int arm_speeds[] = {
SPD800,
SPD1000,
SPD1200,
SPD1350,
SPD1400,
SPD800,
SPD1400,
SPD1350,
SPD1200,
SPD1000,
SPD800,
SPD800,
SPD800,
};
/**
* pll_freq_get - get pll frequency
* Fout = Fref * NF(mult) / NR(prediv) / OD
* @pll: pll identifier
*/
static unsigned long pll_freq_get(int pll)
{
unsigned long mult = 1, prediv = 1, output_div = 2;
unsigned long ret;
u32 tmp, reg;
if (pll == CORE_PLL) {
ret = external_clk[sys_clk];
if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
/* PLL mode */
tmp = __raw_readl(KS2_MAINPLLCTL0);
prediv = (tmp & PLL_DIV_MASK) + 1;
mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
(pllctl_reg_read(pll, mult) &
PLLM_MULT_LO_MASK)) + 1;
output_div = ((pllctl_reg_read(pll, secctl) >>
PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
ret = ret / prediv / output_div * mult;
}
} else {
switch (pll) {
case PASS_PLL:
ret = external_clk[pa_clk];
reg = KS2_PASSPLLCTL0;
break;
case TETRIS_PLL:
ret = external_clk[tetris_clk];
reg = KS2_ARMPLLCTL0;
break;
case DDR3A_PLL:
ret = external_clk[ddr3a_clk];
reg = KS2_DDR3APLLCTL0;
break;
case DDR3B_PLL:
ret = external_clk[ddr3b_clk];
reg = KS2_DDR3BPLLCTL0;
break;
default:
return 0;
}
tmp = __raw_readl(reg);
if (!(tmp & PLLCTL_BYPASS)) {
/* Bypass disabled */
prediv = (tmp & PLL_DIV_MASK) + 1;
mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
output_div = ((tmp >> PLL_CLKOD_SHIFT) &
PLL_CLKOD_MASK) + 1;
ret = ((ret / prediv) * mult) / output_div;
}
}
return ret;
}
unsigned long clk_get_rate(unsigned int clk)
{
switch (clk) {
case core_pll_clk: return pll_freq_get(CORE_PLL);
case pass_pll_clk: return pll_freq_get(PASS_PLL);
case tetris_pll_clk: return pll_freq_get(TETRIS_PLL);
case ddr3a_pll_clk: return pll_freq_get(DDR3A_PLL);
case ddr3b_pll_clk: return pll_freq_get(DDR3B_PLL);
case sys_clk0_1_clk:
case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1);
case sys_clk1_clk: return pll_freq_get(CORE_PLL) / pll0div_read(2);
case sys_clk2_clk: return pll_freq_get(CORE_PLL) / pll0div_read(3);
case sys_clk3_clk: return pll_freq_get(CORE_PLL) / pll0div_read(4);
case sys_clk0_2_clk: return clk_get_rate(sys_clk0_clk) / 2;
case sys_clk0_3_clk: return clk_get_rate(sys_clk0_clk) / 3;
case sys_clk0_4_clk: return clk_get_rate(sys_clk0_clk) / 4;
case sys_clk0_6_clk: return clk_get_rate(sys_clk0_clk) / 6;
case sys_clk0_8_clk: return clk_get_rate(sys_clk0_clk) / 8;
case sys_clk0_12_clk: return clk_get_rate(sys_clk0_clk) / 12;
case sys_clk0_24_clk: return clk_get_rate(sys_clk0_clk) / 24;
case sys_clk1_3_clk: return clk_get_rate(sys_clk1_clk) / 3;
case sys_clk1_4_clk: return clk_get_rate(sys_clk1_clk) / 4;
case sys_clk1_6_clk: return clk_get_rate(sys_clk1_clk) / 6;
case sys_clk1_12_clk: return clk_get_rate(sys_clk1_clk) / 12;
default:
break;
}
return 0;
}

View File

@@ -8,12 +8,11 @@
*/
#include <common.h>
#include <asm-generic/errno.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <asm/arch/clock.h>
#include <asm/arch/clock_defs.h>
#define MAX_SPEEDS 13
static void wait_for_completion(const struct pll_init_data *data)
{
int i;
@@ -24,106 +23,6 @@ static void wait_for_completion(const struct pll_init_data *data)
}
}
struct pll_regs {
u32 reg0, reg1;
};
static const struct pll_regs pll_regs[] = {
[CORE_PLL] = { K2HK_MAINPLLCTL0, K2HK_MAINPLLCTL1},
[PASS_PLL] = { K2HK_PASSPLLCTL0, K2HK_PASSPLLCTL1},
[TETRIS_PLL] = { K2HK_ARMPLLCTL0, K2HK_ARMPLLCTL1},
[DDR3A_PLL] = { K2HK_DDR3APLLCTL0, K2HK_DDR3APLLCTL1},
[DDR3B_PLL] = { K2HK_DDR3BPLLCTL0, K2HK_DDR3BPLLCTL1},
};
/* Fout = Fref * NF(mult) / NR(prediv) / OD */
static unsigned long pll_freq_get(int pll)
{
unsigned long mult = 1, prediv = 1, output_div = 2;
unsigned long ret;
u32 tmp, reg;
if (pll == CORE_PLL) {
ret = external_clk[sys_clk];
if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
/* PLL mode */
tmp = __raw_readl(K2HK_MAINPLLCTL0);
prediv = (tmp & PLL_DIV_MASK) + 1;
mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
(pllctl_reg_read(pll, mult) &
PLLM_MULT_LO_MASK)) + 1;
output_div = ((pllctl_reg_read(pll, secctl) >>
PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
ret = ret / prediv / output_div * mult;
}
} else {
switch (pll) {
case PASS_PLL:
ret = external_clk[pa_clk];
reg = K2HK_PASSPLLCTL0;
break;
case TETRIS_PLL:
ret = external_clk[tetris_clk];
reg = K2HK_ARMPLLCTL0;
break;
case DDR3A_PLL:
ret = external_clk[ddr3a_clk];
reg = K2HK_DDR3APLLCTL0;
break;
case DDR3B_PLL:
ret = external_clk[ddr3b_clk];
reg = K2HK_DDR3BPLLCTL0;
break;
default:
return 0;
}
tmp = __raw_readl(reg);
if (!(tmp & PLLCTL_BYPASS)) {
/* Bypass disabled */
prediv = (tmp & PLL_DIV_MASK) + 1;
mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
output_div = ((tmp >> PLL_CLKOD_SHIFT) &
PLL_CLKOD_MASK) + 1;
ret = ((ret / prediv) * mult) / output_div;
}
}
return ret;
}
unsigned long clk_get_rate(unsigned int clk)
{
switch (clk) {
case core_pll_clk: return pll_freq_get(CORE_PLL);
case pass_pll_clk: return pll_freq_get(PASS_PLL);
case tetris_pll_clk: return pll_freq_get(TETRIS_PLL);
case ddr3a_pll_clk: return pll_freq_get(DDR3A_PLL);
case ddr3b_pll_clk: return pll_freq_get(DDR3B_PLL);
case sys_clk0_1_clk:
case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1);
case sys_clk1_clk: return pll_freq_get(CORE_PLL) / pll0div_read(2);
case sys_clk2_clk: return pll_freq_get(CORE_PLL) / pll0div_read(3);
case sys_clk3_clk: return pll_freq_get(CORE_PLL) / pll0div_read(4);
case sys_clk0_2_clk: return clk_get_rate(sys_clk0_clk) / 2;
case sys_clk0_3_clk: return clk_get_rate(sys_clk0_clk) / 3;
case sys_clk0_4_clk: return clk_get_rate(sys_clk0_clk) / 4;
case sys_clk0_6_clk: return clk_get_rate(sys_clk0_clk) / 6;
case sys_clk0_8_clk: return clk_get_rate(sys_clk0_clk) / 8;
case sys_clk0_12_clk: return clk_get_rate(sys_clk0_clk) / 12;
case sys_clk0_24_clk: return clk_get_rate(sys_clk0_clk) / 24;
case sys_clk1_3_clk: return clk_get_rate(sys_clk1_clk) / 3;
case sys_clk1_4_clk: return clk_get_rate(sys_clk1_clk) / 4;
case sys_clk1_6_clk: return clk_get_rate(sys_clk1_clk) / 6;
case sys_clk1_12_clk: return clk_get_rate(sys_clk1_clk) / 12;
default:
break;
}
return 0;
}
void init_pll(const struct pll_init_data *data)
{
u32 tmp, tmp_ctl, pllm, plld, pllod, bwadj;
@@ -139,7 +38,7 @@ void init_pll(const struct pll_init_data *data)
tmp = pllctl_reg_read(data->pll, secctl);
if (tmp & (PLLCTL_BYPASS)) {
setbits_le32(pll_regs[data->pll].reg1,
setbits_le32(keystone_pll_regs[data->pll].reg1,
BIT(MAIN_ENSAT_OFFSET));
pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN |
@@ -159,21 +58,24 @@ void init_pll(const struct pll_init_data *data)
pllctl_reg_write(data->pll, mult, pllm & PLLM_MULT_LO_MASK);
clrsetbits_le32(pll_regs[data->pll].reg0, PLLM_MULT_HI_SMASK,
(pllm << 6));
clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
PLLM_MULT_HI_SMASK, (pllm << 6));
/* Set the BWADJ (12 bit field) */
tmp_ctl = pllm >> 1; /* Divide the pllm by 2 */
clrsetbits_le32(pll_regs[data->pll].reg0, PLL_BWADJ_LO_SMASK,
clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
PLL_BWADJ_LO_SMASK,
(tmp_ctl << PLL_BWADJ_LO_SHIFT));
clrsetbits_le32(pll_regs[data->pll].reg1, PLL_BWADJ_HI_MASK,
clrsetbits_le32(keystone_pll_regs[data->pll].reg1,
PLL_BWADJ_HI_MASK,
(tmp_ctl >> 8));
/*
* Set the pll divider (6 bit field) *
* PLLD[5:0] is located in MAINPLLCTL0
*/
clrsetbits_le32(pll_regs[data->pll].reg0, PLL_DIV_MASK, plld);
clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
PLL_DIV_MASK, plld);
/* Set the OUTPUT DIVIDE (4 bit field) in SECCTL */
pllctl_reg_rmw(data->pll, secctl, PLL_CLKOD_SMASK,
@@ -206,17 +108,18 @@ void init_pll(const struct pll_init_data *data)
tmp = pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN);
#ifndef CONFIG_SOC_K2E
} else if (data->pll == TETRIS_PLL) {
bwadj = pllm >> 1;
/* 1.5 Set PLLCTL0[BYPASS] =1 (enable bypass), */
setbits_le32(pll_regs[data->pll].reg0, PLLCTL_BYPASS);
setbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS);
/*
* Set CHIPMISCCTL1[13] = 0 (enable glitchfree bypass)
* only applicable for Kepler
*/
clrbits_le32(K2HK_MISC_CTRL, ARM_PLL_EN);
clrbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN);
/* 2 In PLLCTL1, write PLLRST = 1 (PLL is reset) */
setbits_le32(pll_regs[data->pll].reg1 ,
setbits_le32(keystone_pll_regs[data->pll].reg1 ,
PLL_PLLRST | PLLCTL_ENSAT);
/*
@@ -229,13 +132,13 @@ void init_pll(const struct pll_init_data *data)
(pllm << 6) |
(plld & PLL_DIV_MASK) |
(pllod << PLL_CLKOD_SHIFT) | PLLCTL_BYPASS;
__raw_writel(tmp, pll_regs[data->pll].reg0);
__raw_writel(tmp, keystone_pll_regs[data->pll].reg0);
/* Set BWADJ[11:8] bits */
tmp = __raw_readl(pll_regs[data->pll].reg1);
tmp = __raw_readl(keystone_pll_regs[data->pll].reg1);
tmp &= ~(PLL_BWADJ_HI_MASK);
tmp |= ((bwadj>>8) & PLL_BWADJ_HI_MASK);
__raw_writel(tmp, pll_regs[data->pll].reg1);
__raw_writel(tmp, keystone_pll_regs[data->pll].reg1);
/*
* 5 Wait for at least 5 us based on the reference
* clock (PLL reset time)
@@ -243,26 +146,27 @@ void init_pll(const struct pll_init_data *data)
sdelay(21000); /* Wait for a minimum of 7 us*/
/* 6 In PLLCTL1, write PLLRST = 0 (PLL reset is released) */
clrbits_le32(pll_regs[data->pll].reg1, PLL_PLLRST);
clrbits_le32(keystone_pll_regs[data->pll].reg1, PLL_PLLRST);
/*
* 7 Wait for at least 500 * REFCLK cycles * (PLLD + 1)
* (PLL lock time)
*/
sdelay(105000);
/* 8 disable bypass */
clrbits_le32(pll_regs[data->pll].reg0, PLLCTL_BYPASS);
clrbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS);
/*
* 9 Set CHIPMISCCTL1[13] = 1 (disable glitchfree bypass)
* only applicable for Kepler
*/
setbits_le32(K2HK_MISC_CTRL, ARM_PLL_EN);
setbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN);
#endif
} else {
setbits_le32(pll_regs[data->pll].reg1, PLLCTL_ENSAT);
setbits_le32(keystone_pll_regs[data->pll].reg1, PLLCTL_ENSAT);
/*
* process keeps state of Bypass bit while programming
* all other DDR PLL settings
*/
tmp = __raw_readl(pll_regs[data->pll].reg0);
tmp = __raw_readl(keystone_pll_regs[data->pll].reg0);
tmp &= PLLCTL_BYPASS; /* clear everything except Bypass */
/*
@@ -274,10 +178,10 @@ void init_pll(const struct pll_init_data *data)
(pllm << PLL_MULT_SHIFT) |
(plld & PLL_DIV_MASK) |
(pllod << PLL_CLKOD_SHIFT);
__raw_writel(tmp, pll_regs[data->pll].reg0);
__raw_writel(tmp, keystone_pll_regs[data->pll].reg0);
/* Set BWADJ[11:8] bits */
tmp = __raw_readl(pll_regs[data->pll].reg1);
tmp = __raw_readl(keystone_pll_regs[data->pll].reg1);
tmp &= ~(PLL_BWADJ_HI_MASK);
tmp |= ((bwadj >> 8) & PLL_BWADJ_HI_MASK);
@@ -285,20 +189,20 @@ void init_pll(const struct pll_init_data *data)
if (data->pll == PASS_PLL)
tmp |= PLLCTL_PAPLL;
__raw_writel(tmp, pll_regs[data->pll].reg1);
__raw_writel(tmp, keystone_pll_regs[data->pll].reg1);
/* Reset bit: bit 14 for both DDR3 & PASS PLL */
tmp = PLL_PLLRST;
/* Set RESET bit = 1 */
setbits_le32(pll_regs[data->pll].reg1, tmp);
setbits_le32(keystone_pll_regs[data->pll].reg1, tmp);
/* Wait for a minimum of 7 us*/
sdelay(21000);
/* Clear RESET bit */
clrbits_le32(pll_regs[data->pll].reg1, tmp);
clrbits_le32(keystone_pll_regs[data->pll].reg1, tmp);
sdelay(105000);
/* clear BYPASS (Enable PLL Mode) */
clrbits_le32(pll_regs[data->pll].reg0, PLLCTL_BYPASS);
clrbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS);
sdelay(21000); /* Wait for a minimum of 7 us*/
}
@@ -316,3 +220,44 @@ void init_plls(int num_pll, struct pll_init_data *config)
for (i = 0; i < num_pll; i++)
init_pll(&config[i]);
}
static int get_max_speed(u32 val, int *speeds)
{
int j;
if (!val)
return speeds[0];
for (j = 1; j < MAX_SPEEDS; j++) {
if (val == 1)
return speeds[j];
val >>= 1;
}
return SPD800;
}
#ifdef CONFIG_SOC_K2HK
static u32 read_efuse_bootrom(void)
{
return (cpu_revision() > 1) ? __raw_readl(KS2_EFUSE_BOOTROM) :
__raw_readl(KS2_REV1_DEVSPEED);
}
#else
static inline u32 read_efuse_bootrom(void)
{
return __raw_readl(KS2_EFUSE_BOOTROM);
}
#endif
inline int get_max_dev_speed(void)
{
return get_max_speed(read_efuse_bootrom() & 0xffff, dev_speeds);
}
#ifndef CONFIG_SOC_K2E
inline int get_max_arm_speed(void)
{
return get_max_speed((read_efuse_bootrom() >> 16) & 0xffff, arm_speeds);
}
#endif

View File

@@ -14,10 +14,10 @@
#include <asm/arch/psc_defs.h>
struct pll_init_data cmd_pll_data = {
.pll = MAIN_PLL,
.pll_m = 16,
.pll_d = 1,
.pll_od = 2,
.pll = MAIN_PLL,
.pll_m = 16,
.pll_d = 1,
.pll_od = 2,
};
int do_pll_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
@@ -27,12 +27,19 @@ int do_pll_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
if (strncmp(argv[1], "pa", 2) == 0)
cmd_pll_data.pll = PASS_PLL;
#ifndef CONFIG_SOC_K2E
else if (strncmp(argv[1], "arm", 3) == 0)
cmd_pll_data.pll = TETRIS_PLL;
#endif
#ifdef CONFIG_SOC_K2HK
else if (strncmp(argv[1], "ddr3a", 5) == 0)
cmd_pll_data.pll = DDR3A_PLL;
else if (strncmp(argv[1], "ddr3b", 5) == 0)
cmd_pll_data.pll = DDR3B_PLL;
#else
else if (strncmp(argv[1], "ddr3", 4) == 0)
cmd_pll_data.pll = DDR3_PLL;
#endif
else
goto pll_cmd_usage;
@@ -51,11 +58,20 @@ pll_cmd_usage:
return cmd_usage(cmdtp);
}
#ifdef CONFIG_SOC_K2HK
U_BOOT_CMD(
pllset, 5, 0, do_pll_cmd,
"set pll multiplier and pre divider",
"<pa|arm|ddr3a|ddr3b> <mult> <div> <OD>\n"
);
#endif
#ifdef CONFIG_SOC_K2E
U_BOOT_CMD(
pllset, 5, 0, do_pll_cmd,
"set pll multiplier and pre divider",
"<pa|ddr3> <mult> <div> <OD>\n"
);
#endif
int do_getclk_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
@@ -79,7 +95,12 @@ U_BOOT_CMD(
getclk, 2, 0, do_getclk_cmd,
"get clock rate",
"<clk index>\n"
"See the 'enum clk_e' in the k2hk clock.h for clk indexes\n"
#ifdef CONFIG_SOC_K2HK
"See the 'enum clk_e' in the clock-k2hk.h for clk indexes\n"
#endif
#ifdef CONFIG_SOC_K2E
"See the 'enum clk_e' in the clock-k2e.h for clk indexes\n"
#endif
);
int do_psc_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])

View File

@@ -7,10 +7,11 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/arch/hardware.h>
#include <asm/io.h>
#include <common.h>
#include <asm/arch/ddr3.h>
void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
{
unsigned int tmp;
@@ -57,7 +58,7 @@ void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
;
}
void init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg)
void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg)
{
__raw_writel(emif_cfg->sdcfg, base + KS2_DDR3_SDCFG_OFFSET);
__raw_writel(emif_cfg->sdtim1, base + KS2_DDR3_SDTIM1_OFFSET);
@@ -67,3 +68,21 @@ void init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg)
__raw_writel(emif_cfg->zqcfg, base + KS2_DDR3_ZQCFG_OFFSET);
__raw_writel(emif_cfg->sdrfc, base + KS2_DDR3_SDRFC_OFFSET);
}
void ddr3_reset_ddrphy(void)
{
u32 tmp;
/* Assert DDR3A PHY reset */
tmp = readl(KS2_DDR3APLLCTL1);
tmp |= KS2_DDR3_PLLCTRL_PHY_RESET;
writel(tmp, KS2_DDR3APLLCTL1);
/* wait 10us to catch the reset */
udelay(10);
/* Release DDR3A PHY reset */
tmp = readl(KS2_DDR3APLLCTL1);
tmp &= ~KS2_DDR3_PLLCTRL_PHY_RESET;
__raw_writel(tmp, KS2_DDR3APLLCTL1);
}

View File

@@ -10,13 +10,14 @@
#include <common.h>
#include <ns16550.h>
#include <asm/io.h>
#include <asm/arch/msmc.h>
#include <asm/arch/clock.h>
#include <asm/arch/hardware.h>
void chip_configuration_unlock(void)
{
__raw_writel(KEYSTONE_KICK0_MAGIC, KEYSTONE_KICK0);
__raw_writel(KEYSTONE_KICK1_MAGIC, KEYSTONE_KICK1);
__raw_writel(KS2_KICK0_MAGIC, KS2_KICK0);
__raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);
}
int arch_cpu_init(void)
@@ -24,11 +25,12 @@ int arch_cpu_init(void)
chip_configuration_unlock();
icache_enable();
#ifdef CONFIG_SOC_K2HK
share_all_segments(8);
share_all_segments(9);
share_all_segments(10); /* QM PDSP */
share_all_segments(11); /* PCIE */
msmc_share_all_segments(8); /* TETRIS */
msmc_share_all_segments(9); /* NETCP */
msmc_share_all_segments(10); /* QM PDSP */
msmc_share_all_segments(11); /* PCIE 0 */
#ifdef CONFIG_SOC_K2E
msmc_share_all_segments(13); /* PCIE 1 */
#endif
/*

View File

@@ -0,0 +1,87 @@
/*
* Keystone EVM : Board initialization
*
* (C) Copyright 2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/mon.h>
#include <asm/arch/psc_defs.h>
#include <asm/arch/hardware.h>
#include <asm/arch/hardware.h>
/**
* cpu_to_bus - swap bytes of the 32-bit data if the device is BE
* @ptr - array of data
* @length - lenght of data array
*/
int cpu_to_bus(u32 *ptr, u32 length)
{
u32 i;
if (!(readl(KS2_DEVSTAT) & 0x1))
for (i = 0; i < length; i++, ptr++)
*ptr = cpu_to_be32(*ptr);
return 0;
}
static int turn_off_myself(void)
{
printf("Turning off ourselves\r\n");
mon_power_off(0);
psc_disable_module(KS2_LPSC_TETRIS);
psc_disable_domain(KS2_TETRIS_PWR_DOMAIN);
asm volatile ("isb\n"
"dsb\n"
"wfi\n");
printf("What! Should not see that\n");
return 0;
}
static void turn_off_all_dsps(int num_dsps)
{
int i;
for (i = 0; i < num_dsps; i++) {
if (psc_disable_module(i + KS2_LPSC_GEM_0))
printf("Cannot disable module for #%d DSP", i);
if (psc_disable_domain(i + 8))
printf("Cannot disable domain for #%d DSP", i);
}
}
int do_killme_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
return turn_off_myself();
}
U_BOOT_CMD(
killme, 1, 0, do_killme_cmd,
"turn off main ARM core",
"turn off main ARM core. Should not live after that :(\n"
);
int misc_init_r(void)
{
char *env;
long ks2_debug = 0;
env = getenv("ks2_debug");
if (env)
ks2_debug = simple_strtol(env, NULL, 0);
if ((ks2_debug & DBG_LEAVE_DSPS_ON) == 0)
turn_off_all_dsps(KS2_NUM_DSPS);
return 0;
}

View File

@@ -8,7 +8,7 @@
*/
#include <common.h>
#include <asm/arch/hardware.h>
#include <asm/arch/msmc.h>
struct mpax {
u32 mpaxl;
@@ -56,9 +56,9 @@ struct msms_regs {
};
void share_all_segments(int priv_id)
void msmc_share_all_segments(int priv_id)
{
struct msms_regs *msmc = (struct msms_regs *)K2HK_MSMC_CTRL_BASE;
struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE;
int j;
for (j = 0; j < 8; j++) {

View File

@@ -16,10 +16,6 @@
#define DEVICE_REG32_R(addr) __raw_readl((u32 *)(addr))
#define DEVICE_REG32_W(addr, val) __raw_writel(val, (u32 *)(addr))
#ifdef CONFIG_SOC_K2HK
#define DEVICE_PSC_BASE K2HK_PSC_BASE
#endif
int psc_delay(void)
{
udelay(10);
@@ -55,7 +51,7 @@ int psc_wait(u32 domain_num)
retry = 0;
do {
ptstat = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PSTAT);
ptstat = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PSTAT);
ptstat = ptstat & (1 << domain_num);
} while ((ptstat != 0) && ((retry += psc_delay()) <
PSC_PTSTAT_TIMEOUT_LIMIT));
@@ -71,7 +67,7 @@ u32 psc_get_domain_num(u32 mod_num)
u32 domain_num;
/* Get the power domain associated with the module number */
domain_num = DEVICE_REG32_R(DEVICE_PSC_BASE +
domain_num = DEVICE_REG32_R(KS2_PSC_BASE +
PSC_REG_MDCFG(mod_num));
domain_num = PSC_REG_MDCFG_GET_PD(domain_num);
@@ -106,7 +102,7 @@ int psc_set_state(u32 mod_num, u32 state)
* Get the power domain associated with the module number, and reset
* isolation functionality
*/
v = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCFG(mod_num));
v = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num));
domain_num = PSC_REG_MDCFG_GET_PD(v);
reset_iso = PSC_REG_MDCFG_GET_RESET_ISO(v);
@@ -123,24 +119,24 @@ int psc_set_state(u32 mod_num, u32 state)
* change is made if the new state is power down.
*/
if (state == PSC_REG_VAL_MDCTL_NEXT_ON) {
pdctl = DEVICE_REG32_R(DEVICE_PSC_BASE +
pdctl = DEVICE_REG32_R(KS2_PSC_BASE +
PSC_REG_PDCTL(domain_num));
pdctl = PSC_REG_PDCTL_SET_NEXT(pdctl,
PSC_REG_VAL_PDCTL_NEXT_ON);
DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PDCTL(domain_num),
DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num),
pdctl);
}
/* Set the next state for the module to enabled/disabled */
mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
mdctl = PSC_REG_MDCTL_SET_NEXT(mdctl, state);
mdctl = PSC_REG_MDCTL_SET_RESET_ISO(mdctl, reset_iso);
DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
/* Trigger the enable */
ptcmd = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PTCMD);
ptcmd = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PTCMD);
ptcmd |= (u32)(1<<domain_num);
DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PTCMD, ptcmd);
DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_PTCMD, ptcmd);
/* Wait on the complete */
return psc_wait(domain_num);
@@ -161,7 +157,7 @@ int psc_enable_module(u32 mod_num)
u32 mdctl;
/* Set the bit to apply reset */
mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
if ((mdctl & 0x3f) == PSC_REG_VAL_MDSTAT_STATE_ON)
return 0;
@@ -180,11 +176,11 @@ int psc_disable_module(u32 mod_num)
u32 mdctl;
/* Set the bit to apply reset */
mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
if ((mdctl & 0x3f) == 0)
return 0;
mdctl = PSC_REG_MDCTL_SET_LRSTZ(mdctl, 0);
DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
return psc_set_state(mod_num, PSC_REG_VAL_MDCTL_NEXT_SWRSTDISABLE);
}
@@ -203,11 +199,11 @@ int psc_set_reset_iso(u32 mod_num)
u32 mdctl;
/* Set the reset isolation bit */
mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num));
mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
mdctl = PSC_REG_MDCTL_SET_RESET_ISO(mdctl, 1);
DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl);
v = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCFG(mod_num));
v = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num));
if (PSC_REG_MDCFG_GET_RESET_ISO(v) == 1)
return 0;
@@ -224,14 +220,14 @@ int psc_disable_domain(u32 domain_num)
u32 pdctl;
u32 ptcmd;
pdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PDCTL(domain_num));
pdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num));
pdctl = PSC_REG_PDCTL_SET_NEXT(pdctl, PSC_REG_VAL_PDCTL_NEXT_OFF);
pdctl = PSC_REG_PDCTL_SET_PDMODE(pdctl, PSC_REG_VAL_PDCTL_PDMODE_SLEEP);
DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PDCTL(domain_num), pdctl);
DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num), pdctl);
ptcmd = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PTCMD);
ptcmd = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PTCMD);
ptcmd |= (u32)(1 << domain_num);
DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PTCMD, ptcmd);
DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_PTCMD, ptcmd);
return psc_wait(domain_num);
}

View File

@@ -18,10 +18,18 @@
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_K2HK_EVM
static struct pll_init_data spl_pll_config[] = {
CORE_PLL_799,
TETRIS_PLL_500,
};
#endif
#ifdef CONFIG_K2E_EVM
static struct pll_init_data spl_pll_config[] = {
CORE_PLL_800,
};
#endif
void spl_init_keystone_plls(void)
{

View File

@@ -10,3 +10,4 @@
obj-y := soc.o clock.o
obj-$(CONFIG_SPL_BUILD) += ddr.o
obj-$(CONFIG_SECURE_BOOT) += hab.o
obj-$(CONFIG_MP) += mp.o

View File

@@ -71,6 +71,24 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
}
#endif
/* spi_num can be from 0 - SPI_MAX_NUM */
int enable_spi_clk(unsigned char enable, unsigned spi_num)
{
u32 reg;
u32 mask;
if (spi_num > SPI_MAX_NUM)
return -EINVAL;
mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1);
reg = __raw_readl(&imx_ccm->CCGR1);
if (enable)
reg |= mask;
else
reg &= ~mask;
__raw_writel(reg, &imx_ccm->CCGR1);
return 0;
}
static u32 decode_pll(enum pll_clocks pll, u32 infreq)
{
u32 div;
@@ -214,7 +232,7 @@ static u32 get_uart_clk(void)
u32 reg, uart_podf;
u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
reg = __raw_readl(&imx_ccm->cscdr1);
#ifdef CONFIG_MX6SL
#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
freq = MXC_HCLK;
#endif
@@ -282,7 +300,7 @@ static u32 get_emi_slow_clk(void)
return root_freq / (emi_slow_podf + 1);
}
#ifdef CONFIG_MX6SL
#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
static u32 get_mmdc_ch0_clk(void)
{
u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
@@ -355,6 +373,27 @@ int enable_fec_anatop_clock(enum enet_freq freq)
reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
writel(reg, &anatop->pll_enet);
#ifdef CONFIG_MX6SX
/*
* Set enet ahb clock to 200MHz
* pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
*/
reg = readl(&imx_ccm->chsccdr);
reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK
| MXC_CCM_CHSCCDR_ENET_PODF_MASK
| MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK);
/* PLL2 PFD2 */
reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET);
/* Div = 2*/
reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET);
reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET);
writel(reg, &imx_ccm->chsccdr);
/* Enable enet system clock */
reg = readl(&imx_ccm->CCGR3);
reg |= MXC_CCM_CCGR3_ENET_MASK;
writel(reg, &imx_ccm->CCGR3);
#endif
return 0;
}
#endif
@@ -437,6 +476,7 @@ static int enable_enet_pll(uint32_t en)
return 0;
}
#ifndef CONFIG_MX6SX
static void ungate_sata_clock(void)
{
struct mxc_ccm_reg *const imx_ccm =
@@ -445,6 +485,7 @@ static void ungate_sata_clock(void)
/* Enable SATA clock. */
setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
}
#endif
static void ungate_pcie_clock(void)
{
@@ -455,11 +496,13 @@ static void ungate_pcie_clock(void)
setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
}
#ifndef CONFIG_MX6SX
int enable_sata_clock(void)
{
ungate_sata_clock();
return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
}
#endif
int enable_pcie_clock(void)
{
@@ -491,7 +534,9 @@ int enable_pcie_clock(void)
clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
/* Party time! Ungate the clock to the PCIe. */
#ifndef CONFIG_MX6SX
ungate_sata_clock();
#endif
ungate_pcie_clock();
return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
@@ -573,6 +618,7 @@ int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
return 0;
}
#ifndef CONFIG_MX6SX
void enable_ipu_clock(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
@@ -581,6 +627,7 @@ void enable_ipu_clock(void)
reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
writel(reg, &mxc_ccm->CCGR3);
}
#endif
/***************************************************/
U_BOOT_CMD(

View File

@@ -197,6 +197,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,
u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr;
u16 CS0_END;
u16 tdllk = 0x1ff; /* DLL locking time: 512 cycles (JEDEC DDR3) */
u8 coladdr;
int clkper; /* clock period in picoseconds */
int clock; /* clock freq in mHz */
int cs;
@@ -422,8 +423,13 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,
mmdc0->mdor = reg;
/* Step 5: Configure DDR physical parameters (density and burst len) */
coladdr = m->coladdr;
if (m->coladdr == 8) /* 8-bit COL is 0x3 */
coladdr += 4;
else if (m->coladdr == 12) /* 12-bit COL is 0x4 */
coladdr += 1;
reg = (m->rowaddr - 11) << 24 | /* ROW */
(m->coladdr - 9) << 20 | /* COL */
(coladdr - 9) << 20 | /* COL */
(1 << 19) | /* Burst Length = 8 for DDR3 */
(i->dsize << 16); /* DDR data bus size */
mmdc0->mdctl = reg;

View File

@@ -0,0 +1,87 @@
/*
* (C) Copyright 2014
* Gabriel Huau <contact@huau-gabriel.fr>
*
* (C) Copyright 2009 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/imx-regs.h>
#define MAX_CPUS 4
static struct src *src = (struct src *)SRC_BASE_ADDR;
static uint32_t cpu_reset_mask[MAX_CPUS] = {
0, /* We don't really want to modify the cpu0 */
SRC_SCR_CORE_1_RESET_MASK,
SRC_SCR_CORE_2_RESET_MASK,
SRC_SCR_CORE_3_RESET_MASK
};
static uint32_t cpu_ctrl_mask[MAX_CPUS] = {
0, /* We don't really want to modify the cpu0 */
SRC_SCR_CORE_1_ENABLE_MASK,
SRC_SCR_CORE_2_ENABLE_MASK,
SRC_SCR_CORE_3_ENABLE_MASK
};
int cpu_reset(int nr)
{
/* Software reset of the CPU N */
src->scr |= cpu_reset_mask[nr];
return 0;
}
int cpu_status(int nr)
{
printf("core %d => %d\n", nr, !!(src->scr & cpu_ctrl_mask[nr]));
return 0;
}
int cpu_release(int nr, int argc, char *const argv[])
{
uint32_t boot_addr;
boot_addr = simple_strtoul(argv[0], NULL, 16);
switch (nr) {
case 1:
src->gpr3 = boot_addr;
break;
case 2:
src->gpr5 = boot_addr;
break;
case 3:
src->gpr7 = boot_addr;
break;
default:
return 1;
}
/* CPU N is ready to start */
src->scr |= cpu_ctrl_mask[nr];
return 0;
}
int is_core_valid(unsigned int core)
{
uint32_t nr_cores = get_nr_cpus();
if (core > nr_cores)
return 0;
return 1;
}
int cpu_disable(int nr)
{
/* Disable the CPU N */
src->scr &= ~cpu_ctrl_mask[nr];
return 0;
}

View File

@@ -35,6 +35,12 @@ struct scu_regs {
u32 fpga_rev;
};
u32 get_nr_cpus(void)
{
struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
return readl(&scu->config) & 3;
}
u32 get_cpu_rev(void)
{
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
@@ -79,9 +85,15 @@ u32 __weak get_board_rev(void)
void init_aips(void)
{
struct aipstz_regs *aips1, *aips2;
#ifdef CONFIG_MX6SX
struct aipstz_regs *aips3;
#endif
aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
#ifdef CONFIG_MX6SX
aips3 = (struct aipstz_regs *)AIPS3_BASE_ADDR;
#endif
/*
* Set all MPROTx to be non-bufferable, trusted for R/W,
@@ -107,6 +119,26 @@ void init_aips(void)
writel(0x00000000, &aips2->opacr2);
writel(0x00000000, &aips2->opacr3);
writel(0x00000000, &aips2->opacr4);
#ifdef CONFIG_MX6SX
/*
* Set all MPROTx to be non-bufferable, trusted for R/W,
* not forced to user-mode.
*/
writel(0x77777777, &aips3->mprot0);
writel(0x77777777, &aips3->mprot1);
/*
* Set all OPACRx to be non-bufferable, not require
* supervisor privilege level for access,allow for
* write access and untrusted master access.
*/
writel(0x00000000, &aips3->opacr0);
writel(0x00000000, &aips3->opacr1);
writel(0x00000000, &aips3->opacr2);
writel(0x00000000, &aips3->opacr3);
writel(0x00000000, &aips3->opacr4);
#endif
}
static void clear_ldo_ramp(void)
@@ -311,6 +343,10 @@ void s_init(void)
u32 mask480;
u32 mask528;
if (is_cpu_type(MXC_CPU_MX6SX))
return;
/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
* to make sure PFD is working right, otherwise, PFDs may
* not output clock after reset, MX6DL and MX6SL have added 396M pfd

View File

@@ -10,10 +10,13 @@
#include <linux/linkage.h>
#include <asm/gic.h>
#include <asm/armv7.h>
#include <asm/proc-armv/ptrace.h>
.arch_extension sec
.arch_extension virt
.pushsection ._secure.text, "ax"
.align 5
/* the vector table for secure state and HYP mode */
_monitor_vectors:
@@ -22,43 +25,95 @@ _monitor_vectors:
adr pc, _secure_monitor
.word 0
.word 0
adr pc, _hyp_trap
.word 0
.word 0
.word 0
.macro is_cpu_virt_capable tmp
mrc p15, 0, \tmp, c0, c1, 1 @ read ID_PFR1
and \tmp, \tmp, #CPUID_ARM_VIRT_MASK @ mask virtualization bits
cmp \tmp, #(1 << CPUID_ARM_VIRT_SHIFT)
.endm
/*
* secure monitor handler
* U-boot calls this "software interrupt" in start.S
* This is executed on a "smc" instruction, we use a "smc #0" to switch
* to non-secure state.
* We use only r0 and r1 here, due to constraints in the caller.
* r0, r1, r2: passed to the callee
* ip: target PC
*/
_secure_monitor:
mrc p15, 0, r1, c1, c1, 0 @ read SCR
bic r1, r1, #0x4e @ clear IRQ, FIQ, EA, nET bits
orr r1, r1, #0x31 @ enable NS, AW, FW bits
#ifdef CONFIG_ARMV7_PSCI
ldr r5, =_psci_vectors @ Switch to the next monitor
mcr p15, 0, r5, c12, c0, 1
isb
#ifdef CONFIG_ARMV7_VIRT
mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1
and r0, r0, #CPUID_ARM_VIRT_MASK @ mask virtualization bits
cmp r0, #(1 << CPUID_ARM_VIRT_SHIFT)
orreq r1, r1, #0x100 @ allow HVC instruction
@ Obtain a secure stack, and configure the PSCI backend
bl psci_arch_init
#endif
mcr p15, 0, r1, c1, c1, 0 @ write SCR (with NS bit set)
mrc p15, 0, r5, c1, c1, 0 @ read SCR
bic r5, r5, #0x4a @ clear IRQ, EA, nET bits
orr r5, r5, #0x31 @ enable NS, AW, FW bits
@ FIQ preserved for secure mode
mov r6, #SVC_MODE @ default mode is SVC
is_cpu_virt_capable r4
#ifdef CONFIG_ARMV7_VIRT
mrceq p15, 0, r0, c12, c0, 1 @ get MVBAR value
mcreq p15, 4, r0, c12, c0, 0 @ write HVBAR
orreq r5, r5, #0x100 @ allow HVC instruction
moveq r6, #HYP_MODE @ Enter the kernel as HYP
#endif
movs pc, lr @ return to non-secure SVC
mcr p15, 0, r5, c1, c1, 0 @ write SCR (with NS bit set)
isb
_hyp_trap:
mrs lr, elr_hyp @ for older asm: .byte 0x00, 0xe3, 0x0e, 0xe1
mov pc, lr @ do no switch modes, but
@ return to caller
bne 1f
@ Reset CNTVOFF to 0 before leaving monitor mode
mrc p15, 0, r4, c0, c1, 1 @ read ID_PFR1
ands r4, r4, #CPUID_ARM_GENTIMER_MASK @ test arch timer bits
movne r4, #0
mcrrne p15, 4, r4, r4, c14 @ Reset CNTVOFF to zero
1:
mov lr, ip
mov ip, #(F_BIT | I_BIT | A_BIT) @ Set A, I and F
tst lr, #1 @ Check for Thumb PC
orrne ip, ip, #T_BIT @ Set T if Thumb
orr ip, ip, r6 @ Slot target mode in
msr spsr_cxfs, ip @ Set full SPSR
movs pc, lr @ ERET to non-secure
ENTRY(_do_nonsec_entry)
mov ip, r0
mov r0, r1
mov r1, r2
mov r2, r3
smc #0
ENDPROC(_do_nonsec_entry)
.macro get_cbar_addr addr
#ifdef CONFIG_ARM_GIC_BASE_ADDRESS
ldr \addr, =CONFIG_ARM_GIC_BASE_ADDRESS
#else
mrc p15, 4, \addr, c15, c0, 0 @ read CBAR
bfc \addr, #0, #15 @ clear reserved bits
#endif
.endm
.macro get_gicd_addr addr
get_cbar_addr \addr
add \addr, \addr, #GIC_DIST_OFFSET @ GIC dist i/f offset
.endm
.macro get_gicc_addr addr, tmp
get_cbar_addr \addr
is_cpu_virt_capable \tmp
movne \tmp, #GIC_CPU_OFFSET_A9 @ GIC CPU offset for A9
moveq \tmp, #GIC_CPU_OFFSET_A15 @ GIC CPU offset for A15/A7
add \addr, \addr, \tmp
.endm
#ifndef CONFIG_ARMV7_PSCI
/*
* Secondary CPUs start here and call the code for the core specific parts
* of the non-secure and HYP mode transition. The GIC distributor specific
@@ -66,31 +121,21 @@ _hyp_trap:
* Then they go back to wfi and wait to be woken up by the kernel again.
*/
ENTRY(_smp_pen)
mrs r0, cpsr
orr r0, r0, #0xc0
msr cpsr, r0 @ disable interrupts
ldr r1, =_start
mcr p15, 0, r1, c12, c0, 0 @ set VBAR
cpsid i
cpsid f
bl _nonsec_init
mov r12, r0 @ save GICC address
#ifdef CONFIG_ARMV7_VIRT
bl _switch_to_hyp
#endif
ldr r1, [r12, #GICC_IAR] @ acknowledge IPI
str r1, [r12, #GICC_EOIR] @ signal end of interrupt
adr r0, _smp_pen @ do not use this address again
b smp_waitloop @ wait for IPIs, board specific
ENDPROC(_smp_pen)
#endif
/*
* Switch a core to non-secure state.
*
* 1. initialize the GIC per-core interface
* 2. allow coprocessor access in non-secure modes
* 3. switch the cpu mode (by calling "smc #0")
*
* Called from smp_pen by secondary cores and directly by the BSP.
* Do not assume that the stack is available and only use registers
@@ -100,38 +145,23 @@ ENDPROC(_smp_pen)
* though, but we check this in C before calling this function.
*/
ENTRY(_nonsec_init)
#ifdef CONFIG_ARM_GIC_BASE_ADDRESS
ldr r2, =CONFIG_ARM_GIC_BASE_ADDRESS
#else
mrc p15, 4, r2, c15, c0, 0 @ read CBAR
bfc r2, #0, #15 @ clear reserved bits
#endif
add r3, r2, #GIC_DIST_OFFSET @ GIC dist i/f offset
get_gicd_addr r3
mvn r1, #0 @ all bits to 1
str r1, [r3, #GICD_IGROUPRn] @ allow private interrupts
mrc p15, 0, r0, c0, c0, 0 @ read MIDR
ldr r1, =MIDR_PRIMARY_PART_MASK
and r0, r0, r1 @ mask out variant and revision
get_gicc_addr r3, r1
ldr r1, =MIDR_CORTEX_A7_R0P0 & MIDR_PRIMARY_PART_MASK
cmp r0, r1 @ check for Cortex-A7
ldr r1, =MIDR_CORTEX_A15_R0P0 & MIDR_PRIMARY_PART_MASK
cmpne r0, r1 @ check for Cortex-A15
movne r1, #GIC_CPU_OFFSET_A9 @ GIC CPU offset for A9
moveq r1, #GIC_CPU_OFFSET_A15 @ GIC CPU offset for A15/A7
add r3, r2, r1 @ r3 = GIC CPU i/f addr
mov r1, #1 @ set GICC_CTLR[enable]
mov r1, #3 @ Enable both groups
str r1, [r3, #GICC_CTLR] @ and clear all other bits
mov r1, #0xff
str r1, [r3, #GICC_PMR] @ set priority mask register
mrc p15, 0, r0, c1, c1, 2
movw r1, #0x3fff
movt r1, #0x0006
mcr p15, 0, r1, c1, c1, 2 @ NSACR = all copros to non-sec
movt r1, #0x0004
orr r0, r0, r1
mcr p15, 0, r0, c1, c1, 2 @ NSACR = all copros to non-sec
/* The CNTFRQ register of the generic timer needs to be
* programmed in secure state. Some primary bootloaders / firmware
@@ -149,21 +179,9 @@ ENTRY(_nonsec_init)
adr r1, _monitor_vectors
mcr p15, 0, r1, c12, c0, 1 @ set MVBAR to secure vectors
mrc p15, 0, ip, c12, c0, 0 @ save secure copy of VBAR
isb
smc #0 @ call into MONITOR mode
mcr p15, 0, ip, c12, c0, 0 @ write non-secure copy of VBAR
mov r1, #1
str r1, [r3, #GICC_CTLR] @ enable non-secure CPU i/f
add r2, r2, #GIC_DIST_OFFSET
str r1, [r2, #GICD_CTLR] @ allow private interrupts
mov r0, r3 @ return GICC address
bx lr
ENDPROC(_nonsec_init)
@@ -175,18 +193,10 @@ ENTRY(smp_waitloop)
ldr r1, [r1]
cmp r0, r1 @ make sure we dont execute this code
beq smp_waitloop @ again (due to a spurious wakeup)
mov pc, r1
mov r0, r1
b _do_nonsec_entry
ENDPROC(smp_waitloop)
.weak smp_waitloop
#endif
ENTRY(_switch_to_hyp)
mov r0, lr
mov r1, sp @ save SVC copy of LR and SP
isb
hvc #0 @ for older asm: .byte 0x70, 0x00, 0x40, 0xe1
mov sp, r1
mov lr, r0 @ restore SVC copy of LR and SP
bx lr
ENDPROC(_switch_to_hyp)
.popsection

View File

@@ -242,46 +242,10 @@ static void omap5_ddr3_leveling(u32 base, const struct emif_regs *regs)
__udelay(130);
}
static void dra7_ddr3_leveling(u32 base, const struct emif_regs *regs)
{
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
u32 fifo_reg;
fifo_reg = readl(&emif->emif_ddr_fifo_misaligned_clear_1);
writel(fifo_reg | 0x00000100,
&emif->emif_ddr_fifo_misaligned_clear_1);
fifo_reg = readl(&emif->emif_ddr_fifo_misaligned_clear_2);
writel(fifo_reg | 0x00000100,
&emif->emif_ddr_fifo_misaligned_clear_2);
/* Launch Full leveling */
writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
/* Wait till full leveling is complete */
readl(&emif->emif_rd_wr_lvl_ctl);
__udelay(130);
/* Read data eye leveling no of samples */
config_data_eye_leveling_samples(base);
/*
* Disable leveling. This is because if leveling is kept
* enabled, then PHY triggers a false leveling during
* EMIF-idle scenario which results in wrong delay
* values getting updated. After this the EMIF becomes
* unaccessible. So disable it after the first time
*/
writel(0x0, &emif->emif_rd_wr_lvl_rmp_ctl);
}
static void ddr3_leveling(u32 base, const struct emif_regs *regs)
{
if (is_omap54xx())
omap5_ddr3_leveling(base, regs);
else
dra7_ddr3_leveling(base, regs);
}
static void ddr3_init(u32 base, const struct emif_regs *regs)
@@ -1383,7 +1347,7 @@ void sdram_init(void)
}
if (sdram_type == EMIF_SDRAM_TYPE_DDR3 &&
(!in_sdram && !warm_reset())) {
(!in_sdram && !warm_reset()) && (!is_dra7xx())) {
if (emif1_enabled)
do_bug0039_workaround(EMIF1_BASE);
if (emif2_enabled)

View File

@@ -123,7 +123,8 @@ void s_init(void)
hw_data_init();
#ifdef CONFIG_SPL_BUILD
if (warm_reset() && (omap_revision() <= OMAP5430_ES1_0))
if (warm_reset() &&
(is_omap44xx() || (omap_revision() == OMAP5430_ES1_0)))
force_emif_self_refresh();
#endif
watchdog_init();
@@ -139,6 +140,9 @@ void s_init(void)
#endif
prcm_init();
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_BOARD_EARLY_INIT_F
board_early_init_f();
#endif
/* For regular u-boot sdram_init() is called from dram_init() */
sdram_init();
#endif

View File

@@ -87,9 +87,13 @@ void gpmc_init(void)
STNOR_GPMC_CONFIG6,
STNOR_GPMC_CONFIG7
};
u32 size = GPMC_SIZE_16M;
u32 base = CONFIG_SYS_FLASH_BASE;
#elif defined(CONFIG_NAND)
u32 size = (CONFIG_SYS_FLASH_SIZE > 0x08000000) ? GPMC_SIZE_256M :
/* > 64MB */ ((CONFIG_SYS_FLASH_SIZE > 0x04000000) ? GPMC_SIZE_128M :
/* > 32MB */ ((CONFIG_SYS_FLASH_SIZE > 0x02000000) ? GPMC_SIZE_64M :
/* > 16MB */ ((CONFIG_SYS_FLASH_SIZE > 0x01000000) ? GPMC_SIZE_32M :
/* min 16MB */ GPMC_SIZE_16M)));
#elif defined(CONFIG_NAND) || defined(CONFIG_CMD_NAND)
/* configure GPMC for NAND */
const u32 gpmc_regs[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG1,
M_NAND_GPMC_CONFIG2,
@@ -99,8 +103,9 @@ void gpmc_init(void)
M_NAND_GPMC_CONFIG6,
0
};
u32 size = GPMC_SIZE_256M;
u32 base = CONFIG_SYS_NAND_BASE;
u32 size = GPMC_SIZE_16M;
#elif defined(CONFIG_CMD_ONENAND)
const u32 gpmc_regs[GPMC_MAX_REG] = { ONENAND_GPMC_CONFIG1,
ONENAND_GPMC_CONFIG2,
@@ -110,8 +115,8 @@ void gpmc_init(void)
ONENAND_GPMC_CONFIG6,
0
};
u32 base = PISMO1_ONEN_BASE;
u32 size = PISMO1_ONEN_SIZE;
u32 size = GPMC_SIZE_128M;
u32 base = CONFIG_SYS_ONENAND_BASE;
#else
const u32 gpmc_regs[GPMC_MAX_REG] = { 0, 0, 0, 0, 0, 0, 0 };
u32 size = 0;

View File

@@ -22,6 +22,7 @@ SECTIONS
.text :
{
__start = .;
*(.vectors)
arch/arm/cpu/armv7/start.o (.text*)
*(.text*)
} >.sram

View File

@@ -0,0 +1,107 @@
if OMAP34XX
choice
prompt "OMAP3 board select"
config TARGET_AM3517_EVM
bool "AM3517 EVM"
config TARGET_MT_VENTOUX
bool "TeeJet Mt.Ventoux"
config TARGET_OMAP3_SDP3430
bool "TI OMAP3430 SDP"
config TARGET_OMAP3_BEAGLE
bool "TI OMAP3 BeagleBoard"
config TARGET_CM_T35
bool "CompuLab CM-T35"
config TARGET_DEVKIT8000
bool "TimLL OMAP3 Devkit8000"
config TARGET_OMAP3_EVM
bool "TI OMAP3 EVM"
config TARGET_OMAP3_EVM_QUICK_MMC
bool "TI OMAP3 EVM Quick MMC"
config TARGET_OMAP3_EVM_QUICK_NAND
bool "TI OMAP3 EVM Quick NAND"
config TARGET_OMAP3_IGEP00X0
bool "IGEP"
config TARGET_OMAP3_OVERO
bool "OMAP35xx Gumstix Overo"
config TARGET_OMAP3_ZOOM1
bool "TI Zoom1"
config TARGET_AM3517_CRANE
bool "am3517_crane"
config TARGET_OMAP3_PANDORA
bool "OMAP3 Pandora"
config TARGET_ECO5PK
bool "ECO5PK"
config TARGET_DIG297
bool "DIG297"
config TARGET_TRICORDER
bool "Tricorder"
config TARGET_MCX
bool "MCX"
config TARGET_OMAP3_LOGIC
bool "OMAP3 Logic"
config TARGET_OMAP3_MVBLX
bool "OMAP3 MVBLX"
config TARGET_NOKIA_RX51
bool "Nokia RX51"
config TARGET_TAO3530
bool "TAO3530"
config TARGET_TWISTER
bool "Twister"
endchoice
config SYS_CPU
string
default "armv7"
config SYS_SOC
string
default "omap3"
source "board/logicpd/am3517evm/Kconfig"
source "board/teejet/mt_ventoux/Kconfig"
source "board/ti/sdp3430/Kconfig"
source "board/ti/beagle/Kconfig"
source "board/compulab/cm_t35/Kconfig"
source "board/timll/devkit8000/Kconfig"
source "board/ti/evm/Kconfig"
source "board/isee/igep00x0/Kconfig"
source "board/overo/Kconfig"
source "board/logicpd/zoom1/Kconfig"
source "board/ti/am3517crane/Kconfig"
source "board/pandora/Kconfig"
source "board/8dtech/eco5pk/Kconfig"
source "board/comelit/dig297/Kconfig"
source "board/corscience/tricorder/Kconfig"
source "board/htkw/mcx/Kconfig"
source "board/logicpd/omap3som/Kconfig"
source "board/matrix_vision/mvblx/Kconfig"
source "board/nokia/rx51/Kconfig"
source "board/technexion/tao3530/Kconfig"
source "board/technexion/twister/Kconfig"
endif

View File

@@ -1,139 +0,0 @@
/*
* (C) Copyright 2008
* Texas Instruments, <www.ti.com>
*
* Author :
* Manikandan Pillai <mani.pillai@ti.com>
*
* Initial Code from:
* Richard Woodruff <r-woodruff2@ti.com>
* Syed Mohammed Khasim <khasim@ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/mem.h>
#include <asm/arch/sys_proto.h>
#include <command.h>
struct gpmc *gpmc_cfg;
#if defined(CONFIG_CMD_NAND)
static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
M_NAND_GPMC_CONFIG1,
M_NAND_GPMC_CONFIG2,
M_NAND_GPMC_CONFIG3,
M_NAND_GPMC_CONFIG4,
M_NAND_GPMC_CONFIG5,
M_NAND_GPMC_CONFIG6, 0
};
#endif /* CONFIG_CMD_NAND */
#if defined(CONFIG_CMD_ONENAND)
static const u32 gpmc_onenand[GPMC_MAX_REG] = {
ONENAND_GPMC_CONFIG1,
ONENAND_GPMC_CONFIG2,
ONENAND_GPMC_CONFIG3,
ONENAND_GPMC_CONFIG4,
ONENAND_GPMC_CONFIG5,
ONENAND_GPMC_CONFIG6, 0
};
#endif /* CONFIG_CMD_ONENAND */
/********************************************************
* mem_ok() - test used to see if timings are correct
* for a part. Helps in guessing which part
* we are currently using.
*******************************************************/
u32 mem_ok(u32 cs)
{
u32 val1, val2, addr;
u32 pattern = 0x12345678;
addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs);
writel(0x0, addr + 0x400); /* clear pos A */
writel(pattern, addr); /* pattern to pos B */
writel(0x0, addr + 4); /* remove pattern off the bus */
val1 = readl(addr + 0x400); /* get pos A value */
val2 = readl(addr); /* get val2 */
writel(0x0, addr + 0x400); /* clear pos A */
if ((val1 != 0) || (val2 != pattern)) /* see if pos A val changed */
return 0;
else
return 1;
}
void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
u32 size)
{
writel(0, &cs->config7);
sdelay(1000);
/* Delay for settling */
writel(gpmc_config[0], &cs->config1);
writel(gpmc_config[1], &cs->config2);
writel(gpmc_config[2], &cs->config3);
writel(gpmc_config[3], &cs->config4);
writel(gpmc_config[4], &cs->config5);
writel(gpmc_config[5], &cs->config6);
/*
* Enable the config. size is the CS size and goes in
* bits 11:8. We set bit 6 to enable this CS and the base
* address goes into bits 5:0.
*/
writel((size << 8) | (GPMC_CS_ENABLE << 6) |
((base >> 24) & GPMC_BASEADDR_MASK),
&cs->config7);
sdelay(2000);
}
/*****************************************************
* gpmc_init(): init gpmc bus
* Init GPMC for x16, MuxMode (SDRAM in x32).
* This code can only be executed from SRAM or SDRAM.
*****************************************************/
void gpmc_init(void)
{
/* putting a blanket check on GPMC based on ZeBu for now */
gpmc_cfg = (struct gpmc *)GPMC_BASE;
#if defined(CONFIG_CMD_NAND) || defined(CONFIG_CMD_ONENAND)
const u32 *gpmc_config = NULL;
u32 base = 0;
u32 size = 0;
#endif
u32 config = 0;
/* global settings */
writel(0, &gpmc_cfg->irqenable); /* isr's sources masked */
writel(0, &gpmc_cfg->timeout_control);/* timeout disable */
config = readl(&gpmc_cfg->config);
config &= (~0xf00);
writel(config, &gpmc_cfg->config);
/*
* Disable the GPMC0 config set by ROM code
* It conflicts with our MPDB (both at 0x08000000)
*/
writel(0, &gpmc_cfg->cs[0].config7);
sdelay(1000);
#if defined(CONFIG_CMD_NAND) /* CS 0 */
gpmc_config = gpmc_m_nand;
base = PISMO1_NAND_BASE;
size = PISMO1_NAND_SIZE;
enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
#endif
#if defined(CONFIG_CMD_ONENAND)
gpmc_config = gpmc_onenand;
base = PISMO1_ONEN_BASE;
size = PISMO1_ONEN_SIZE;
enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
#endif
}

View File

@@ -0,0 +1,29 @@
if OMAP44XX
choice
prompt "OMAP4 board select"
config TARGET_DUOVERO
bool "OMAP4430 Gumstix Duovero"
config TARGET_OMAP4_PANDA
bool "TI OMAP4 PandaBoard"
config TARGET_OMAP4_SDP4430
bool "TI OMAP4 SDP4430"
endchoice
config SYS_CPU
string
default "armv7"
config SYS_SOC
string
default "omap4"
source "board/gumstix/duovero/Kconfig"
source "board/ti/panda/Kconfig"
source "board/ti/sdp4430/Kconfig"
endif

View File

@@ -0,0 +1,29 @@
if OMAP54XX
choice
prompt "OMAP5 board select"
config TARGET_CM_T54
bool "CompuLab CM-T54"
config TARGET_OMAP5_UEVM
bool "TI OMAP5 uEVM board"
config TARGET_DRA7XX_EVM
bool "TI DRA7XX"
endchoice
config SYS_CPU
string
default "armv7"
config SYS_SOC
string
default "omap5"
source "board/compulab/cm_t54/Kconfig"
source "board/ti/omap5_uevm/Kconfig"
source "board/ti/dra7xx/Kconfig"
endif

View File

@@ -556,7 +556,7 @@ const struct ctrl_ioregs ioregs_dra7xx_es1 = {
.ctrl_ddrio_1 = 0x84210840,
.ctrl_ddrio_2 = 0x84210000,
.ctrl_emif_sdram_config_ext = 0x0001C1A7,
.ctrl_emif_sdram_config_ext_final = 0x000101A7,
.ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
.ctrl_ddr_ctrl_ext_0 = 0xA2000000,
};

View File

@@ -145,18 +145,18 @@ const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x308F7FDA,
.sdram_tim3 = 0x027F88A8,
.read_idle_ctrl = 0x00050000,
.read_idle_ctrl = 0x00050001,
.zq_config = 0x0007190B,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0024400A,
.emif_ddr_phy_ctlr_1 = 0x0024400A,
.emif_ddr_phy_ctlr_1_init = 0x0E24400A,
.emif_ddr_phy_ctlr_1 = 0x0E24400A,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00B000B0,
.emif_ddr_ext_phy_ctrl_3 = 0x00B000B0,
.emif_ddr_ext_phy_ctrl_4 = 0x00B000B0,
.emif_ddr_ext_phy_ctrl_5 = 0x00B000B0,
.emif_ddr_ext_phy_ctrl_2 = 0x00BB00BB,
.emif_ddr_ext_phy_ctrl_3 = 0x00BB00BB,
.emif_ddr_ext_phy_ctrl_4 = 0x00BB00BB,
.emif_ddr_ext_phy_ctrl_5 = 0x00BB00BB,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_rmp_ctl = 0x00000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
@@ -169,18 +169,18 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x308F7FDA,
.sdram_tim3 = 0x027F88A8,
.read_idle_ctrl = 0x00050000,
.read_idle_ctrl = 0x00050001,
.zq_config = 0x0007190B,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0024400A,
.emif_ddr_phy_ctlr_1 = 0x0024400A,
.emif_ddr_phy_ctlr_1_init = 0x0E24400A,
.emif_ddr_phy_ctlr_1 = 0x0E24400A,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00B000B0,
.emif_ddr_ext_phy_ctrl_3 = 0x00B000B0,
.emif_ddr_ext_phy_ctrl_4 = 0x00B000B0,
.emif_ddr_ext_phy_ctrl_5 = 0x00B000B0,
.emif_ddr_ext_phy_ctrl_2 = 0x00BB00BB,
.emif_ddr_ext_phy_ctrl_3 = 0x00BB00BB,
.emif_ddr_ext_phy_ctrl_4 = 0x00BB00BB,
.emif_ddr_ext_phy_ctrl_5 = 0x00BB00BB,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_rmp_ctl = 0x00000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
@@ -394,24 +394,24 @@ const u32 ddr3_ext_phy_ctrl_const_base_es2[] = {
const u32
dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
0x00B000B0,
0x00400040,
0x00400040,
0x00400040,
0x00400040,
0x00400040,
0x00800080,
0x00800080,
0x00800080,
0x00800080,
0x00800080,
0x00BB00BB,
0x00440044,
0x00440044,
0x00440044,
0x00440044,
0x00440044,
0x007F007F,
0x007F007F,
0x007F007F,
0x007F007F,
0x007F007F,
0x00600060,
0x00600060,
0x00600060,
0x00600060,
0x00600060,
0x00800080,
0x00800080,
0x00000000,
0x00600020,
0x40010080,
0x08102040,
0x0,
@@ -439,7 +439,7 @@ dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = {
0x00600060,
0x00600060,
0x00600060,
0x0,
0x00000000,
0x00600020,
0x40010080,
0x08102040,

102
arch/arm/cpu/armv7/psci.S Normal file
View File

@@ -0,0 +1,102 @@
/*
* Copyright (C) 2013,2014 - ARM Ltd
* Author: Marc Zyngier <marc.zyngier@arm.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <config.h>
#include <linux/linkage.h>
#include <asm/psci.h>
.pushsection ._secure.text, "ax"
.arch_extension sec
.align 5
.globl _psci_vectors
_psci_vectors:
b default_psci_vector @ reset
b default_psci_vector @ undef
b _smc_psci @ smc
b default_psci_vector @ pabort
b default_psci_vector @ dabort
b default_psci_vector @ hyp
b default_psci_vector @ irq
b psci_fiq_enter @ fiq
ENTRY(psci_fiq_enter)
movs pc, lr
ENDPROC(psci_fiq_enter)
.weak psci_fiq_enter
ENTRY(default_psci_vector)
movs pc, lr
ENDPROC(default_psci_vector)
.weak default_psci_vector
ENTRY(psci_cpu_suspend)
ENTRY(psci_cpu_off)
ENTRY(psci_cpu_on)
ENTRY(psci_migrate)
mov r0, #ARM_PSCI_RET_NI @ Return -1 (Not Implemented)
mov pc, lr
ENDPROC(psci_migrate)
ENDPROC(psci_cpu_on)
ENDPROC(psci_cpu_off)
ENDPROC(psci_cpu_suspend)
.weak psci_cpu_suspend
.weak psci_cpu_off
.weak psci_cpu_on
.weak psci_migrate
_psci_table:
.word ARM_PSCI_FN_CPU_SUSPEND
.word psci_cpu_suspend
.word ARM_PSCI_FN_CPU_OFF
.word psci_cpu_off
.word ARM_PSCI_FN_CPU_ON
.word psci_cpu_on
.word ARM_PSCI_FN_MIGRATE
.word psci_migrate
.word 0
.word 0
_smc_psci:
push {r4-r7,lr}
@ Switch to secure
mrc p15, 0, r7, c1, c1, 0
bic r4, r7, #1
mcr p15, 0, r4, c1, c1, 0
isb
adr r4, _psci_table
1: ldr r5, [r4] @ Load PSCI function ID
ldr r6, [r4, #4] @ Load target PC
cmp r5, #0 @ If reach the end, bail out
moveq r0, #ARM_PSCI_RET_INVAL @ Return -2 (Invalid)
beq 2f
cmp r0, r5 @ If not matching, try next entry
addne r4, r4, #8
bne 1b
blx r6 @ Execute PSCI function
@ Switch back to non-secure
2: mcr p15, 0, r7, c1, c1, 0
pop {r4-r7, lr}
movs pc, lr @ Return to the kernel
.popsection

View File

@@ -0,0 +1,37 @@
if RMOBILE
choice
prompt "Renesus ARM SoCs board select"
config TARGET_ARMADILLO_800EVA
bool "armadillo 800 eva board"
config TARGET_KOELSCH
bool "Koelsch board"
config TARGET_LAGER
bool "Lager board"
config TARGET_KZM9G
bool "KZM9D board"
config TARGET_ALT
bool "Alt board"
endchoice
config SYS_CPU
string
default "armv7"
config SYS_SOC
string
default "rmobile"
source "board/atmark-techno/armadillo-800eva/Kconfig"
source "board/renesas/koelsch/Kconfig"
source "board/renesas/lager/Kconfig"
source "board/kmc/kzm9g/Kconfig"
source "board/renesas/alt/Kconfig"
endif

View File

@@ -13,5 +13,6 @@ obj-$(CONFIG_GLOBAL_TIMER) += timer.o
obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o
obj-$(CONFIG_R8A7790) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7790.o
obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7791.o
obj-$(CONFIG_R8A7794) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7794.o
obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o
obj-$(CONFIG_TMU_TIMER) += ../../../../sh/lib/time.o

View File

@@ -53,6 +53,7 @@ static const struct {
{ 0x40, "R8A7740" },
{ 0x45, "R8A7790" },
{ 0x47, "R8A7791" },
{ 0x4C, "R8A7794" },
{ 0x0, "CPU" },
};

File diff suppressed because it is too large Load Diff

View File

@@ -110,8 +110,8 @@ void cm_basic_init(const cm_config_t *cfg)
* gatting off the rest of the periperal clocks.
*/
writel(~CLKMGR_PERPLLGRP_EN_NANDCLK_MASK &
readl(&clock_manager_base->per_pll_en),
&clock_manager_base->per_pll_en);
readl(&clock_manager_base->per_pll.en),
&clock_manager_base->per_pll.en);
/* DO NOT GATE OFF DEBUG CLOCKS & BRIDGE CLOCKS */
writel(CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK |
@@ -120,12 +120,12 @@ void cm_basic_init(const cm_config_t *cfg)
CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK |
CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK |
CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK,
&clock_manager_base->main_pll_en);
&clock_manager_base->main_pll.en);
writel(0, &clock_manager_base->sdr_pll_en);
writel(0, &clock_manager_base->sdr_pll.en);
/* now we can gate off the rest of the peripheral clocks */
writel(0, &clock_manager_base->per_pll_en);
writel(0, &clock_manager_base->per_pll.en);
/* Put all plls in bypass */
cm_write_bypass(
@@ -142,11 +142,11 @@ void cm_basic_init(const cm_config_t *cfg)
* Some code might have messed with them.
*/
writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE,
&clock_manager_base->main_pll_vco);
&clock_manager_base->main_pll.vco);
writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE,
&clock_manager_base->per_pll_vco);
&clock_manager_base->per_pll.vco);
writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE,
&clock_manager_base->sdr_pll_vco);
&clock_manager_base->sdr_pll.vco);
/*
* The clocks to the flash devices and the L4_MAIN clocks can
@@ -156,14 +156,14 @@ void cm_basic_init(const cm_config_t *cfg)
* after exiting safe mode but before ungating the clocks.
*/
writel(CLKMGR_PERPLLGRP_SRC_RESET_VALUE,
&clock_manager_base->per_pll_src);
&clock_manager_base->per_pll.src);
writel(CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE,
&clock_manager_base->main_pll_l4src);
&clock_manager_base->main_pll.l4src);
/* read back for the required 5 us delay. */
readl(&clock_manager_base->main_pll_vco);
readl(&clock_manager_base->per_pll_vco);
readl(&clock_manager_base->sdr_pll_vco);
readl(&clock_manager_base->main_pll.vco);
readl(&clock_manager_base->per_pll.vco);
readl(&clock_manager_base->sdr_pll.vco);
/*
@@ -172,60 +172,59 @@ void cm_basic_init(const cm_config_t *cfg)
*/
writel(cfg->main_vco_base | CLEAR_BGP_EN_PWRDN |
CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
&clock_manager_base->main_pll_vco);
&clock_manager_base->main_pll.vco);
writel(cfg->peri_vco_base | CLEAR_BGP_EN_PWRDN |
CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
&clock_manager_base->per_pll_vco);
&clock_manager_base->per_pll.vco);
writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) |
CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
cfg->sdram_vco_base | CLEAR_BGP_EN_PWRDN |
CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
&clock_manager_base->sdr_pll_vco);
&clock_manager_base->sdr_pll.vco);
/*
* Time starts here
* must wait 7 us from BGPWRDN_SET(0) to VCO_ENABLE_SET(1)
*/
reset_timer();
start = get_timer(0);
/* timeout in unit of us as CONFIG_SYS_HZ = 1000*1000 */
timeout = 7;
/* main mpu */
writel(cfg->mpuclk, &clock_manager_base->main_pll_mpuclk);
writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk);
/* main main clock */
writel(cfg->mainclk, &clock_manager_base->main_pll_mainclk);
writel(cfg->mainclk, &clock_manager_base->main_pll.mainclk);
/* main for dbg */
writel(cfg->dbgatclk, &clock_manager_base->main_pll_dbgatclk);
writel(cfg->dbgatclk, &clock_manager_base->main_pll.dbgatclk);
/* main for cfgs2fuser0clk */
writel(cfg->cfg2fuser0clk,
&clock_manager_base->main_pll_cfgs2fuser0clk);
&clock_manager_base->main_pll.cfgs2fuser0clk);
/* Peri emac0 50 MHz default to RMII */
writel(cfg->emac0clk, &clock_manager_base->per_pll_emac0clk);
writel(cfg->emac0clk, &clock_manager_base->per_pll.emac0clk);
/* Peri emac1 50 MHz default to RMII */
writel(cfg->emac1clk, &clock_manager_base->per_pll_emac1clk);
writel(cfg->emac1clk, &clock_manager_base->per_pll.emac1clk);
/* Peri QSPI */
writel(cfg->mainqspiclk, &clock_manager_base->main_pll_mainqspiclk);
writel(cfg->mainqspiclk, &clock_manager_base->main_pll.mainqspiclk);
writel(cfg->perqspiclk, &clock_manager_base->per_pll_perqspiclk);
writel(cfg->perqspiclk, &clock_manager_base->per_pll.perqspiclk);
/* Peri pernandsdmmcclk */
writel(cfg->pernandsdmmcclk,
&clock_manager_base->per_pll_pernandsdmmcclk);
&clock_manager_base->per_pll.pernandsdmmcclk);
/* Peri perbaseclk */
writel(cfg->perbaseclk, &clock_manager_base->per_pll_perbaseclk);
writel(cfg->perbaseclk, &clock_manager_base->per_pll.perbaseclk);
/* Peri s2fuser1clk */
writel(cfg->s2fuser1clk, &clock_manager_base->per_pll_s2fuser1clk);
writel(cfg->s2fuser1clk, &clock_manager_base->per_pll.s2fuser1clk);
/* 7 us must have elapsed before we can enable the VCO */
while (get_timer(start) < timeout)
@@ -234,29 +233,29 @@ void cm_basic_init(const cm_config_t *cfg)
/* Enable vco */
/* main pll vco */
writel(cfg->main_vco_base | VCO_EN_BASE,
&clock_manager_base->main_pll_vco);
&clock_manager_base->main_pll.vco);
/* periferal pll */
writel(cfg->peri_vco_base | VCO_EN_BASE,
&clock_manager_base->per_pll_vco);
&clock_manager_base->per_pll.vco);
/* sdram pll vco */
writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) |
CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
cfg->sdram_vco_base | VCO_EN_BASE,
&clock_manager_base->sdr_pll_vco);
&clock_manager_base->sdr_pll.vco);
/* L3 MP and L3 SP */
writel(cfg->maindiv, &clock_manager_base->main_pll_maindiv);
writel(cfg->maindiv, &clock_manager_base->main_pll.maindiv);
writel(cfg->dbgdiv, &clock_manager_base->main_pll_dbgdiv);
writel(cfg->dbgdiv, &clock_manager_base->main_pll.dbgdiv);
writel(cfg->tracediv, &clock_manager_base->main_pll_tracediv);
writel(cfg->tracediv, &clock_manager_base->main_pll.tracediv);
/* L4 MP, L4 SP, can0, and can1 */
writel(cfg->perdiv, &clock_manager_base->per_pll_div);
writel(cfg->perdiv, &clock_manager_base->per_pll.div);
writel(cfg->gpiodiv, &clock_manager_base->per_pll_gpiodiv);
writel(cfg->gpiodiv, &clock_manager_base->per_pll.gpiodiv);
#define LOCKED_MASK \
(CLKMGR_INTER_SDRPLLLOCKED_MASK | \
@@ -267,70 +266,70 @@ void cm_basic_init(const cm_config_t *cfg)
/* write the sdram clock counters before toggling outreset all */
writel(cfg->ddrdqsclk & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK,
&clock_manager_base->sdr_pll_ddrdqsclk);
&clock_manager_base->sdr_pll.ddrdqsclk);
writel(cfg->ddr2xdqsclk & CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK,
&clock_manager_base->sdr_pll_ddr2xdqsclk);
&clock_manager_base->sdr_pll.ddr2xdqsclk);
writel(cfg->ddrdqclk & CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK,
&clock_manager_base->sdr_pll_ddrdqclk);
&clock_manager_base->sdr_pll.ddrdqclk);
writel(cfg->s2fuser2clk & CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK,
&clock_manager_base->sdr_pll_s2fuser2clk);
&clock_manager_base->sdr_pll.s2fuser2clk);
/*
* after locking, but before taking out of bypass
* assert/deassert outresetall
*/
uint32_t mainvco = readl(&clock_manager_base->main_pll_vco);
uint32_t mainvco = readl(&clock_manager_base->main_pll.vco);
/* assert main outresetall */
writel(mainvco | CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
&clock_manager_base->main_pll_vco);
&clock_manager_base->main_pll.vco);
uint32_t periphvco = readl(&clock_manager_base->per_pll_vco);
uint32_t periphvco = readl(&clock_manager_base->per_pll.vco);
/* assert pheriph outresetall */
writel(periphvco | CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
&clock_manager_base->per_pll_vco);
&clock_manager_base->per_pll.vco);
/* assert sdram outresetall */
writel(cfg->sdram_vco_base | VCO_EN_BASE|
CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(1),
&clock_manager_base->sdr_pll_vco);
&clock_manager_base->sdr_pll.vco);
/* deassert main outresetall */
writel(mainvco & ~CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
&clock_manager_base->main_pll_vco);
&clock_manager_base->main_pll.vco);
/* deassert pheriph outresetall */
writel(periphvco & ~CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
&clock_manager_base->per_pll_vco);
&clock_manager_base->per_pll.vco);
/* deassert sdram outresetall */
writel(CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
cfg->sdram_vco_base | VCO_EN_BASE,
&clock_manager_base->sdr_pll_vco);
&clock_manager_base->sdr_pll.vco);
/*
* now that we've toggled outreset all, all the clocks
* are aligned nicely; so we can change any phase.
*/
cm_write_with_phase(cfg->ddrdqsclk,
(uint32_t)&clock_manager_base->sdr_pll_ddrdqsclk,
(uint32_t)&clock_manager_base->sdr_pll.ddrdqsclk,
CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK);
/* SDRAM DDR2XDQSCLK */
cm_write_with_phase(cfg->ddr2xdqsclk,
(uint32_t)&clock_manager_base->sdr_pll_ddr2xdqsclk,
(uint32_t)&clock_manager_base->sdr_pll.ddr2xdqsclk,
CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK);
cm_write_with_phase(cfg->ddrdqclk,
(uint32_t)&clock_manager_base->sdr_pll_ddrdqclk,
(uint32_t)&clock_manager_base->sdr_pll.ddrdqclk,
CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK);
cm_write_with_phase(cfg->s2fuser2clk,
(uint32_t)&clock_manager_base->sdr_pll_s2fuser2clk,
(uint32_t)&clock_manager_base->sdr_pll.s2fuser2clk,
CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK);
/* Take all three PLLs out of bypass when safe mode is cleared. */
@@ -351,11 +350,11 @@ void cm_basic_init(const cm_config_t *cfg)
* now that safe mode is clear with clocks gated
* it safe to change the source mux for the flashes the the L4_MAIN
*/
writel(cfg->persrc, &clock_manager_base->per_pll_src);
writel(cfg->l4src, &clock_manager_base->main_pll_l4src);
writel(cfg->persrc, &clock_manager_base->per_pll.src);
writel(cfg->l4src, &clock_manager_base->main_pll.l4src);
/* Now ungate non-hw-managed clocks */
writel(~0, &clock_manager_base->main_pll_en);
writel(~0, &clock_manager_base->per_pll_en);
writel(~0, &clock_manager_base->sdr_pll_en);
writel(~0, &clock_manager_base->main_pll.en);
writel(~0, &clock_manager_base->per_pll.en);
writel(~0, &clock_manager_base->sdr_pll.en);
}

View File

@@ -6,3 +6,6 @@
ifndef CONFIG_SPL_BUILD
ALL-y += u-boot.img
endif
# Added for handoff support
PLATFORM_RELFLAGS += -Iboard/$(VENDOR)/$(BOARD)

View File

@@ -6,6 +6,8 @@
#include <common.h>
#include <asm/io.h>
#include <miiphy.h>
#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -38,3 +40,18 @@ int misc_init_r(void)
{
return 0;
}
/*
* DesignWare Ethernet initialization
*/
int cpu_eth_init(bd_t *bis)
{
#if !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) && !defined(CONFIG_SPL_BUILD)
/* initialize and register the emac */
return designware_initialize(CONFIG_EMAC_BASE,
CONFIG_PHY_INTERFACE_MODE);
#else
return 0;
#endif
}

View File

@@ -14,6 +14,8 @@
#include <spl.h>
#include <asm/arch/system_manager.h>
#include <asm/arch/freeze_controller.h>
#include <asm/arch/clock_manager.h>
#include <asm/arch/scan_manager.h>
DECLARE_GLOBAL_DATA_PTR;

View File

@@ -16,6 +16,7 @@ SECTIONS
. = ALIGN(4);
.text :
{
*(.vectors)
arch/arm/cpu/armv7/start.o (.text*)
*(.text*)
} >.sdram

View File

@@ -11,13 +11,20 @@ obj-y += timer.o
obj-y += board.o
obj-y += clock.o
obj-y += pinmux.o
obj-$(CONFIG_SUN4I) += clock_sun4i.o
obj-$(CONFIG_SUN5I) += clock_sun4i.o
obj-$(CONFIG_SUN7I) += clock_sun4i.o
ifndef CONFIG_SPL_BUILD
obj-y += cpu_info.o
ifdef CONFIG_ARMV7_PSCI
obj-y += psci.o
endif
endif
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SUN4I) += dram.o
obj-$(CONFIG_SUN5I) += dram.o
obj-$(CONFIG_SUN7I) += dram.o
ifdef CONFIG_SPL_FEL
obj-y += start.o

View File

@@ -11,6 +11,7 @@
*/
#include <common.h>
#include <i2c.h>
#include <netdev.h>
#include <miiphy.h>
#include <serial.h>
@@ -24,6 +25,8 @@
#include <asm/arch/sys_proto.h>
#include <asm/arch/timer.h>
#include <linux/compiler.h>
#ifdef CONFIG_SPL_BUILD
/* Pointer to the global data structure for SPL */
DECLARE_GLOBAL_DATA_PTR;
@@ -47,15 +50,38 @@ u32 spl_boot_mode(void)
int gpio_init(void)
{
#if CONFIG_CONS_INDEX == 1 && (defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I))
sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX);
sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX);
sunxi_gpio_set_pull(SUNXI_GPB(23), 1);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN5I)
sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX);
sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX);
sunxi_gpio_set_pull(SUNXI_GPB(20), 1);
#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_SUN5I)
sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX);
sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX);
sunxi_gpio_set_pull(SUNXI_GPG(4), 1);
#else
#error Unsupported console port number. Please fix pin mux settings in board.c
#endif
return 0;
}
void reset_cpu(ulong addr)
{
static const struct sunxi_wdog *wdog =
&((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
/* Set the watchdog for its shortest interval (.5s) and wait */
writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
while (1) {
/* sun5i sometimes gets stuck without this */
writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
}
}
/* do some early init */
@@ -72,11 +98,16 @@ void s_init(void)
clock_init();
timer_init();
gpio_init();
i2c_init_board();
#ifdef CONFIG_SPL_BUILD
gd = &gdata;
preloader_console_init();
#ifdef CONFIG_SPL_I2C_SUPPORT
/* Needed early by sunxi_board_init if PMU is enabled */
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
sunxi_board_init();
#endif
}
@@ -96,7 +127,20 @@ void enable_caches(void)
*/
int cpu_eth_init(bd_t *bis)
{
int rc;
__maybe_unused int rc;
#ifdef CONFIG_MACPWR
gpio_direction_output(CONFIG_MACPWR, 1);
mdelay(200);
#endif
#ifdef CONFIG_SUNXI_EMAC
rc = sunxi_emac_initialize(bis);
if (rc < 0) {
printf("sunxi: failed to initialize emac\n");
return rc;
}
#endif
#ifdef CONFIG_SUNXI_GMAC
rc = sunxi_gmac_initialize(bis);

View File

@@ -36,10 +36,13 @@ void clock_init_safe(void)
CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
&ccm->cpu_ahb_apb0_cfg);
#ifdef CONFIG_SUN7I
writel(0x1 << AHB_GATE_OFFSET_DMA | readl(&ccm->ahb_gate0),
&ccm->ahb_gate0);
setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA);
#endif
writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
#ifdef CONFIG_SUNXI_AHCI
setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_SATA);
setbits_le32(&ccm->pll6_cfg, 0x1 << CCM_PLL6_CTRL_SATA_EN_SHIFT);
#endif
}
#endif

View File

@@ -13,7 +13,22 @@
#ifdef CONFIG_DISPLAY_CPUINFO
int print_cpuinfo(void)
{
#ifdef CONFIG_SUN4I
puts("CPU: Allwinner A10 (SUN4I)\n");
#elif defined CONFIG_SUN5I
u32 val = readl(SUNXI_SID_BASE + 0x08);
switch ((val >> 12) & 0xf) {
case 0: puts("CPU: Allwinner A12 (SUN5I)\n"); break;
case 3: puts("CPU: Allwinner A13 (SUN5I)\n"); break;
case 7: puts("CPU: Allwinner A10s (SUN5I)\n"); break;
default: puts("CPU: Allwinner A1X (SUN5I)\n");
}
#elif defined CONFIG_SUN7I
puts("CPU: Allwinner A20 (SUN7I)\n");
#else
#warning Please update cpu_info.c with correct CPU information
puts("CPU: SUNXI Family\n");
#endif
return 0;
}
#endif

View File

@@ -36,33 +36,88 @@
#define CPU_CFG_CHIP_REV_B 0x3
/*
* Wait up to 1s for mask to be clear in given reg.
* Wait up to 1s for value to be set in given part of reg.
*/
static void await_completion(u32 *reg, u32 mask)
static void await_completion(u32 *reg, u32 mask, u32 val)
{
unsigned long tmo = timer_get_us() + 1000000;
while (readl(reg) & mask) {
while ((readl(reg) & mask) != val) {
if (timer_get_us() > tmo)
panic("Timeout initialising DRAM\n");
}
}
/*
* Wait up to 1s for mask to be clear in given reg.
*/
static inline void await_bits_clear(u32 *reg, u32 mask)
{
await_completion(reg, mask, 0);
}
/*
* Wait up to 1s for mask to be set in given reg.
*/
static inline void await_bits_set(u32 *reg, u32 mask)
{
await_completion(reg, mask, mask);
}
/*
* This performs the external DRAM reset by driving the RESET pin low and
* then high again. According to the DDR3 spec, the RESET pin needs to be
* kept low for at least 200 us.
*/
static void mctl_ddr3_reset(void)
{
struct sunxi_dram_reg *dram =
(struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
clrbits_le32(&dram->mcr, DRAM_MCR_RESET);
udelay(2);
setbits_le32(&dram->mcr, DRAM_MCR_RESET);
#ifdef CONFIG_SUN4I
struct sunxi_timer_reg *timer =
(struct sunxi_timer_reg *)SUNXI_TIMER_BASE;
u32 reg_val;
writel(0, &timer->cpu_cfg);
reg_val = readl(&timer->cpu_cfg);
if ((reg_val & CPU_CFG_CHIP_VER_MASK) !=
CPU_CFG_CHIP_VER(CPU_CFG_CHIP_REV_A)) {
setbits_le32(&dram->mcr, DRAM_MCR_RESET);
udelay(200);
clrbits_le32(&dram->mcr, DRAM_MCR_RESET);
} else
#endif
{
clrbits_le32(&dram->mcr, DRAM_MCR_RESET);
udelay(200);
setbits_le32(&dram->mcr, DRAM_MCR_RESET);
}
/* After the RESET pin is de-asserted, the DDR3 spec requires to wait
* for additional 500 us before driving the CKE pin (Clock Enable)
* high. The duration of this delay can be configured in the SDR_IDCR
* (Initialization Delay Configuration Register) and applied
* automatically by the DRAM controller during the DDR3 initialization
* step. But SDR_IDCR has limited range on sun4i/sun5i hardware and
* can't provide sufficient delay at DRAM clock frequencies higher than
* 524 MHz (while Allwinner A13 supports DRAM clock frequency up to
* 533 MHz according to the datasheet). Additionally, there is no
* official documentation for the SDR_IDCR register anywhere, and
* there is always a chance that we are interpreting it wrong.
* Better be safe than sorry, so add an explicit delay here. */
udelay(500);
}
static void mctl_set_drive(void)
{
struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
#ifdef CONFIG_SUN7I
clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3) | (0x3 << 28),
#else
clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3),
#endif
DRAM_MCR_MODE_EN(0x3) |
0xffc);
}
@@ -81,6 +136,14 @@ static void mctl_itm_enable(void)
clrbits_le32(&dram->ccr, DRAM_CCR_ITM_OFF);
}
static void mctl_itm_reset(void)
{
mctl_itm_disable();
udelay(1); /* ITM reset needs a bit of delay */
mctl_itm_enable();
udelay(1);
}
static void mctl_enable_dll0(u32 phase)
{
struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
@@ -97,23 +160,28 @@ static void mctl_enable_dll0(u32 phase)
udelay(22);
}
/* Get the number of DDR byte lanes */
static u32 mctl_get_number_of_lanes(void)
{
struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
if ((readl(&dram->dcr) & DRAM_DCR_BUS_WIDTH_MASK) ==
DRAM_DCR_BUS_WIDTH(DRAM_DCR_BUS_WIDTH_32BIT))
return 4;
else
return 2;
}
/*
* Note: This differs from pm/standby in that it checks the bus width
*/
static void mctl_enable_dllx(u32 phase)
{
struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
u32 i, n, bus_width;
u32 i, number_of_lanes;
bus_width = readl(&dram->dcr);
number_of_lanes = mctl_get_number_of_lanes();
if ((bus_width & DRAM_DCR_BUS_WIDTH_MASK) ==
DRAM_DCR_BUS_WIDTH(DRAM_DCR_BUS_WIDTH_32BIT))
n = DRAM_DCR_NR_DLLCR_32BIT;
else
n = DRAM_DCR_NR_DLLCR_16BIT;
for (i = 1; i < n; i++) {
for (i = 1; i <= number_of_lanes; i++) {
clrsetbits_le32(&dram->dllcr[i], 0xf << 14,
(phase & 0xf) << 14);
clrsetbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET,
@@ -122,18 +190,38 @@ static void mctl_enable_dllx(u32 phase)
}
udelay(2);
for (i = 1; i < n; i++)
for (i = 1; i <= number_of_lanes; i++)
clrbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET |
DRAM_DLLCR_DISABLE);
udelay(22);
for (i = 1; i < n; i++)
for (i = 1; i <= number_of_lanes; i++)
clrsetbits_le32(&dram->dllcr[i], DRAM_DLLCR_DISABLE,
DRAM_DLLCR_NRESET);
udelay(22);
}
static u32 hpcr_value[32] = {
#ifdef CONFIG_SUN5I
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0x1031, 0x1031, 0x0735, 0x1035,
0x1035, 0x0731, 0x1031, 0,
0x0301, 0x0301, 0x0301, 0x0301,
0x0301, 0x0301, 0x0301, 0
#endif
#ifdef CONFIG_SUN4I
0x0301, 0x0301, 0x0301, 0x0301,
0x0301, 0x0301, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0x1031, 0x1031, 0x0735, 0x5031,
0x1035, 0x0731, 0x1031, 0x0735,
0x1035, 0x1031, 0x0731, 0x1035,
0x1031, 0x0301, 0x0301, 0x0731
#endif
#ifdef CONFIG_SUN7I
0x0301, 0x0301, 0x0301, 0x0301,
0x0301, 0x0301, 0x0301, 0x0301,
@@ -160,11 +248,20 @@ static void mctl_configure_hostport(void)
writel(hpcr_value[i], &dram->hpcr[i]);
}
static void mctl_setup_dram_clock(u32 clk)
static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk)
{
u32 reg_val;
struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
/* PLL5P and PLL6 are the potential clock sources for MBUS */
u32 pll6x_div, pll5p_div;
u32 pll6x_clk = clock_get_pll6() / 1000000;
u32 pll5p_clk = clk / 24 * 48;
u32 pll5p_rate, pll6x_rate;
#ifdef CONFIG_SUN7I
pll6x_clk *= 2; /* sun7i uses PLL6*2, sun5i uses just PLL6 */
#endif
/* setup DRAM PLL */
reg_val = readl(&ccm->pll5_cfg);
reg_val &= ~CCM_PLL5_CTRL_M_MASK; /* set M to 0 (x1) */
@@ -172,41 +269,40 @@ static void mctl_setup_dram_clock(u32 clk)
reg_val &= ~CCM_PLL5_CTRL_N_MASK; /* set N to 0 (x0) */
reg_val &= ~CCM_PLL5_CTRL_P_MASK; /* set P to 0 (x1) */
if (clk >= 540 && clk < 552) {
/* dram = 540MHz, pll5p = 540MHz */
/* dram = 540MHz, pll5p = 1080MHz */
pll5p_clk = 1080;
reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(15));
reg_val |= CCM_PLL5_CTRL_P(1);
} else if (clk >= 512 && clk < 528) {
/* dram = 512MHz, pll5p = 384MHz */
/* dram = 512MHz, pll5p = 1536MHz */
pll5p_clk = 1536;
reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(3));
reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(4));
reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(16));
reg_val |= CCM_PLL5_CTRL_P(2);
} else if (clk >= 496 && clk < 504) {
/* dram = 496MHz, pll5p = 372MHz */
/* dram = 496MHz, pll5p = 1488MHz */
pll5p_clk = 1488;
reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(3));
reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2));
reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(31));
reg_val |= CCM_PLL5_CTRL_P(2);
} else if (clk >= 468 && clk < 480) {
/* dram = 468MHz, pll5p = 468MHz */
/* dram = 468MHz, pll5p = 936MHz */
pll5p_clk = 936;
reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(13));
reg_val |= CCM_PLL5_CTRL_P(1);
} else if (clk >= 396 && clk < 408) {
/* dram = 396MHz, pll5p = 396MHz */
/* dram = 396MHz, pll5p = 792MHz */
pll5p_clk = 792;
reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11));
reg_val |= CCM_PLL5_CTRL_P(1);
} else {
/* any other frequency that is a multiple of 24 */
reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2));
reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(clk / 24));
reg_val |= CCM_PLL5_CTRL_P(CCM_PLL5_CTRL_P_X(2));
}
reg_val &= ~CCM_PLL5_CTRL_VCO_GAIN; /* PLL VCO Gain off */
reg_val |= CCM_PLL5_CTRL_EN; /* PLL On */
@@ -224,37 +320,92 @@ static void mctl_setup_dram_clock(u32 clk)
#endif
/* setup MBUS clock */
reg_val = CCM_MBUS_CTRL_GATE |
CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL6) |
CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(2)) |
CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(2));
if (!mbus_clk)
mbus_clk = 300;
pll6x_div = DIV_ROUND_UP(pll6x_clk, mbus_clk);
pll5p_div = DIV_ROUND_UP(pll5p_clk, mbus_clk);
pll6x_rate = pll6x_clk / pll6x_div;
pll5p_rate = pll5p_clk / pll5p_div;
if (pll6x_div <= 16 && pll6x_rate > pll5p_rate) {
/* use PLL6 as the MBUS clock source */
reg_val = CCM_MBUS_CTRL_GATE |
CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL6) |
CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(1)) |
CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(pll6x_div));
} else if (pll5p_div <= 16) {
/* use PLL5P as the MBUS clock source */
reg_val = CCM_MBUS_CTRL_GATE |
CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL5) |
CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(1)) |
CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(pll5p_div));
} else {
panic("Bad mbus_clk\n");
}
writel(reg_val, &ccm->mbus_clk_cfg);
/*
* open DRAMC AHB & DLL register clock
* close it first
*/
#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL);
#else
clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM);
#endif
udelay(22);
/* then open it */
#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL);
#else
setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM);
#endif
udelay(22);
}
/*
* The data from rslrX and rdgrX registers (X=rank) is stored
* in a single 32-bit value using the following format:
* bits [31:26] - DQS gating system latency for byte lane 3
* bits [25:24] - DQS gating phase select for byte lane 3
* bits [23:18] - DQS gating system latency for byte lane 2
* bits [17:16] - DQS gating phase select for byte lane 2
* bits [15:10] - DQS gating system latency for byte lane 1
* bits [ 9:8 ] - DQS gating phase select for byte lane 1
* bits [ 7:2 ] - DQS gating system latency for byte lane 0
* bits [ 1:0 ] - DQS gating phase select for byte lane 0
*/
static void mctl_set_dqs_gating_delay(int rank, u32 dqs_gating_delay)
{
struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
u32 lane, number_of_lanes = mctl_get_number_of_lanes();
/* rank0 gating system latency (3 bits per lane: cycles) */
u32 slr = readl(rank == 0 ? &dram->rslr0 : &dram->rslr1);
/* rank0 gating phase select (2 bits per lane: 90, 180, 270, 360) */
u32 dgr = readl(rank == 0 ? &dram->rdgr0 : &dram->rdgr1);
for (lane = 0; lane < number_of_lanes; lane++) {
u32 tmp = dqs_gating_delay >> (lane * 8);
slr &= ~(7 << (lane * 3));
slr |= ((tmp >> 2) & 7) << (lane * 3);
dgr &= ~(3 << (lane * 2));
dgr |= (tmp & 3) << (lane * 2);
}
writel(slr, rank == 0 ? &dram->rslr0 : &dram->rslr1);
writel(dgr, rank == 0 ? &dram->rdgr0 : &dram->rdgr1);
}
static int dramc_scan_readpipe(void)
{
struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
u32 reg_val;
/* data training trigger */
#ifdef CONFIG_SUN7I
clrbits_le32(&dram->csr, DRAM_CSR_FAILED);
#endif
setbits_le32(&dram->ccr, DRAM_CCR_DATA_TRAINING);
/* check whether data training process has completed */
await_completion(&dram->ccr, DRAM_CCR_DATA_TRAINING);
await_bits_clear(&dram->ccr, DRAM_CCR_DATA_TRAINING);
/* check data training result */
reg_val = readl(&dram->csr);
@@ -264,117 +415,6 @@ static int dramc_scan_readpipe(void)
return 0;
}
static int dramc_scan_dll_para(void)
{
struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
const u32 dqs_dly[7] = {0x3, 0x2, 0x1, 0x0, 0xe, 0xd, 0xc};
const u32 clk_dly[15] = {0x07, 0x06, 0x05, 0x04, 0x03,
0x02, 0x01, 0x00, 0x08, 0x10,
0x18, 0x20, 0x28, 0x30, 0x38};
u32 clk_dqs_count[15];
u32 dqs_i, clk_i, cr_i;
u32 max_val, min_val;
u32 dqs_index, clk_index;
/* Find DQS_DLY Pass Count for every CLK_DLY */
for (clk_i = 0; clk_i < 15; clk_i++) {
clk_dqs_count[clk_i] = 0;
clrsetbits_le32(&dram->dllcr[0], 0x3f << 6,
(clk_dly[clk_i] & 0x3f) << 6);
for (dqs_i = 0; dqs_i < 7; dqs_i++) {
for (cr_i = 1; cr_i < 5; cr_i++) {
clrsetbits_le32(&dram->dllcr[cr_i],
0x4f << 14,
(dqs_dly[dqs_i] & 0x4f) << 14);
}
udelay(2);
if (dramc_scan_readpipe() == 0)
clk_dqs_count[clk_i]++;
}
}
/* Test DQS_DLY Pass Count for every CLK_DLY from up to down */
for (dqs_i = 15; dqs_i > 0; dqs_i--) {
max_val = 15;
min_val = 15;
for (clk_i = 0; clk_i < 15; clk_i++) {
if (clk_dqs_count[clk_i] == dqs_i) {
max_val = clk_i;
if (min_val == 15)
min_val = clk_i;
}
}
if (max_val < 15)
break;
}
/* Check if Find a CLK_DLY failed */
if (!dqs_i)
goto fail;
/* Find the middle index of CLK_DLY */
clk_index = (max_val + min_val) >> 1;
if ((max_val == (15 - 1)) && (min_val > 0))
/* if CLK_DLY[MCTL_CLK_DLY_COUNT] is very good, then the middle
* value can be more close to the max_val
*/
clk_index = (15 + clk_index) >> 1;
else if ((max_val < (15 - 1)) && (min_val == 0))
/* if CLK_DLY[0] is very good, then the middle value can be more
* close to the min_val
*/
clk_index >>= 1;
if (clk_dqs_count[clk_index] < dqs_i)
clk_index = min_val;
/* Find the middle index of DQS_DLY for the CLK_DLY got above, and Scan
* read pipe again
*/
clrsetbits_le32(&dram->dllcr[0], 0x3f << 6,
(clk_dly[clk_index] & 0x3f) << 6);
max_val = 7;
min_val = 7;
for (dqs_i = 0; dqs_i < 7; dqs_i++) {
clk_dqs_count[dqs_i] = 0;
for (cr_i = 1; cr_i < 5; cr_i++) {
clrsetbits_le32(&dram->dllcr[cr_i],
0x4f << 14,
(dqs_dly[dqs_i] & 0x4f) << 14);
}
udelay(2);
if (dramc_scan_readpipe() == 0) {
clk_dqs_count[dqs_i] = 1;
max_val = dqs_i;
if (min_val == 7)
min_val = dqs_i;
}
}
if (max_val < 7) {
dqs_index = (max_val + min_val) >> 1;
if ((max_val == (7-1)) && (min_val > 0))
dqs_index = (7 + dqs_index) >> 1;
else if ((max_val < (7-1)) && (min_val == 0))
dqs_index >>= 1;
if (!clk_dqs_count[dqs_index])
dqs_index = min_val;
for (cr_i = 1; cr_i < 5; cr_i++) {
clrsetbits_le32(&dram->dllcr[cr_i],
0x4f << 14,
(dqs_dly[dqs_index] & 0x4f) << 14);
}
udelay(2);
return dramc_scan_readpipe();
}
fail:
clrbits_le32(&dram->dllcr[0], 0x3f << 6);
for (cr_i = 1; cr_i < 5; cr_i++)
clrbits_le32(&dram->dllcr[cr_i], 0x4f << 14);
udelay(2);
return dramc_scan_readpipe();
}
static void dramc_clock_output_en(u32 on)
{
#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
@@ -385,54 +425,188 @@ static void dramc_clock_output_en(u32 on)
else
clrbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT);
#endif
#ifdef CONFIG_SUN4I
struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
if (on)
setbits_le32(&ccm->dram_clk_cfg, CCM_DRAM_CTRL_DCLK_OUT);
else
clrbits_le32(&ccm->dram_clk_cfg, CCM_DRAM_CTRL_DCLK_OUT);
#endif
}
static const u16 tRFC_table[2][6] = {
/* 256Mb 512Mb 1Gb 2Gb 4Gb 8Gb */
/* DDR2 75ns 105ns 127.5ns 195ns 327.5ns invalid */
{ 77, 108, 131, 200, 336, 336 },
/* DDR3 invalid 90ns 110ns 160ns 300ns 350ns */
{ 93, 93, 113, 164, 308, 359 }
/* tRFC in nanoseconds for different densities (from the DDR3 spec) */
static const u16 tRFC_DDR3_table[6] = {
/* 256Mb 512Mb 1Gb 2Gb 4Gb 8Gb */
90, 90, 110, 160, 300, 350
};
static void dramc_set_autorefresh_cycle(u32 clk, u32 type, u32 density)
static void dramc_set_autorefresh_cycle(u32 clk, u32 density)
{
struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
u32 tRFC, tREFI;
tRFC = (tRFC_table[type][density] * clk + 1023) >> 10;
tRFC = (tRFC_DDR3_table[density] * clk + 999) / 1000;
tREFI = (7987 * clk) >> 10; /* <= 7.8us */
writel(DRAM_DRR_TREFI(tREFI) | DRAM_DRR_TRFC(tRFC), &dram->drr);
}
unsigned long dramc_init(struct dram_para *para)
/* Calculate the value for A11, A10, A9 bits in MR0 (write recovery) */
static u32 ddr3_write_recovery(u32 clk)
{
u32 twr_ns = 15; /* DDR3 spec says that it is 15ns for all speed bins */
u32 twr_ck = (twr_ns * clk + 999) / 1000;
if (twr_ck < 5)
return 1;
else if (twr_ck <= 8)
return twr_ck - 4;
else if (twr_ck <= 10)
return 5;
else
return 6;
}
/*
* If the dram->ppwrsctl (SDR_DPCR) register has the lowest bit set to 1, this
* means that DRAM is currently in self-refresh mode and retaining the old
* data. Since we have no idea what to do in this situation yet, just set this
* register to 0 and initialize DRAM in the same way as on any normal reboot
* (discarding whatever was stored there).
*
* Note: on sun7i hardware, the highest 16 bits need to be set to 0x1651 magic
* value for this write operation to have any effect. On sun5i hadware this
* magic value is not necessary. And on sun4i hardware the writes to this
* register seem to have no effect at all.
*/
static void mctl_disable_power_save(void)
{
struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
writel(0x16510000, &dram->ppwrsctl);
}
/*
* After the DRAM is powered up or reset, the DDR3 spec requires to wait at
* least 500 us before driving the CKE pin (Clock Enable) high. The dram->idct
* (SDR_IDCR) register appears to configure this delay, which gets applied
* right at the time when the DRAM initialization is activated in the
* 'mctl_ddr3_initialize' function.
*/
static void mctl_set_cke_delay(void)
{
struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
/* The CKE delay is represented in DRAM clock cycles, multiplied by N
* (where N=2 for sun4i/sun5i and N=3 for sun7i). Here it is set to
* the maximum possible value 0x1ffff, just like in the Allwinner's
* boot0 bootloader. The resulting delay value is somewhere between
* ~0.4 ms (sun5i with 648 MHz DRAM clock speed) and ~1.1 ms (sun7i
* with 360 MHz DRAM clock speed). */
setbits_le32(&dram->idcr, 0x1ffff);
}
/*
* This triggers the DRAM initialization. It performs sending the mode registers
* to the DRAM among other things. Very likely the ZQCL command is also getting
* executed (to do the initial impedance calibration on the DRAM side of the
* wire). The memory controller and the PHY must be already configured before
* calling this function.
*/
static void mctl_ddr3_initialize(void)
{
struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
setbits_le32(&dram->ccr, DRAM_CCR_INIT);
await_bits_clear(&dram->ccr, DRAM_CCR_INIT);
}
/*
* Perform impedance calibration on the DRAM controller side of the wire.
*/
static void mctl_set_impedance(u32 zq, u32 odt_en)
{
struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
u32 reg_val;
u32 zprog = zq & 0xFF, zdata = (zq >> 8) & 0xFFFFF;
#ifndef CONFIG_SUN7I
/* Appears that some kind of automatically initiated default
* ZQ calibration is already in progress at this point on sun4i/sun5i
* hardware, but not on sun7i. So it is reasonable to wait for its
* completion before doing anything else. */
await_bits_set(&dram->zqsr, DRAM_ZQSR_ZDONE);
#endif
/* ZQ calibration is not really useful unless ODT is enabled */
if (!odt_en)
return;
#ifdef CONFIG_SUN7I
/* Enabling ODT in SDR_IOCR on sun7i hardware results in a deadlock
* unless bit 24 is set in SDR_ZQCR1. Not much is known about the
* SDR_ZQCR1 register, but there are hints indicating that it might
* be related to periodic impedance re-calibration. This particular
* magic value is borrowed from the Allwinner boot0 bootloader, and
* using it helps to avoid troubles */
writel((1 << 24) | (1 << 1), &dram->zqcr1);
#endif
/* Needed at least for sun5i, because it does not self clear there */
clrbits_le32(&dram->zqcr0, DRAM_ZQCR0_ZCAL);
if (zdata) {
/* Set the user supplied impedance data */
reg_val = DRAM_ZQCR0_ZDEN | zdata;
writel(reg_val, &dram->zqcr0);
/* no need to wait, this takes effect immediately */
} else {
/* Do the calibration using the external resistor */
reg_val = DRAM_ZQCR0_ZCAL | DRAM_ZQCR0_IMP_DIV(zprog);
writel(reg_val, &dram->zqcr0);
/* Wait for the new impedance configuration to settle */
await_bits_set(&dram->zqsr, DRAM_ZQSR_ZDONE);
}
/* Needed at least for sun5i, because it does not self clear there */
clrbits_le32(&dram->zqcr0, DRAM_ZQCR0_ZCAL);
/* Set I/O configure register */
writel(DRAM_IOCR_ODT_EN(odt_en), &dram->iocr);
}
static unsigned long dramc_init_helper(struct dram_para *para)
{
struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
u32 reg_val;
u32 density;
int ret_val;
/* check input dram parameter structure */
if (!para)
/*
* only single rank DDR3 is supported by this code even though the
* hardware can theoretically support DDR2 and up to two ranks
*/
if (para->type != DRAM_MEMORY_TYPE_DDR3 || para->rank_num != 1)
return 0;
/* setup DRAM relative clock */
mctl_setup_dram_clock(para->clock);
mctl_setup_dram_clock(para->clock, para->mbus_clock);
/* Disable any pad power save control */
mctl_disable_power_save();
/* reset external DRAM */
mctl_set_drive();
/* dram clock off */
dramc_clock_output_en(0);
#ifdef CONFIG_SUN4I
/* select dram controller 1 */
writel(DRAM_CSEL_MAGIC, &dram->csel);
#endif
mctl_itm_disable();
mctl_enable_dll0(para->tpr3);
/* configure external DRAM */
reg_val = 0x0;
if (para->type == DRAM_MEMORY_TYPE_DDR3)
reg_val |= DRAM_DCR_TYPE_DDR3;
reg_val = DRAM_DCR_TYPE_DDR3;
reg_val |= DRAM_DCR_IO_WIDTH(para->io_width >> 3);
if (para->density == 256)
@@ -457,66 +631,41 @@ unsigned long dramc_init(struct dram_para *para)
reg_val |= DRAM_DCR_MODE(DRAM_DCR_MODE_INTERLEAVE);
writel(reg_val, &dram->dcr);
#ifdef CONFIG_SUN7I
setbits_le32(&dram->zqcr1, (0x1 << 24) | (0x1 << 1));
if (para->tpr4 & 0x2)
clrsetbits_le32(&dram->zqcr1, (0x1 << 24), (0x1 << 1));
dramc_clock_output_en(1);
#endif
#if (defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I))
/* set odt impendance divide ratio */
reg_val = ((para->zq) >> 8) & 0xfffff;
reg_val |= ((para->zq) & 0xff) << 20;
reg_val |= (para->zq) & 0xf0000000;
writel(reg_val, &dram->zqcr0);
#endif
mctl_set_impedance(para->zq, para->odt_en);
#ifdef CONFIG_SUN7I
/* Set CKE Delay to about 1ms */
setbits_le32(&dram->idcr, 0x1ffff);
#endif
mctl_set_cke_delay();
#ifdef CONFIG_SUN7I
if ((readl(&dram->ppwrsctl) & 0x1) != 0x1)
mctl_ddr3_reset();
else
setbits_le32(&dram->mcr, DRAM_MCR_RESET);
#endif
mctl_ddr3_reset();
udelay(1);
await_completion(&dram->ccr, DRAM_CCR_INIT);
await_bits_clear(&dram->ccr, DRAM_CCR_INIT);
mctl_enable_dllx(para->tpr3);
/* set refresh period */
dramc_set_autorefresh_cycle(para->clock, para->type - 2, density);
dramc_set_autorefresh_cycle(para->clock, density);
/* set timing parameters */
writel(para->tpr0, &dram->tpr0);
writel(para->tpr1, &dram->tpr1);
writel(para->tpr2, &dram->tpr2);
if (para->type == DRAM_MEMORY_TYPE_DDR3) {
reg_val = DRAM_MR_BURST_LENGTH(0x0);
reg_val = DRAM_MR_BURST_LENGTH(0x0);
#if (defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I))
reg_val |= DRAM_MR_POWER_DOWN;
reg_val |= DRAM_MR_POWER_DOWN;
#endif
reg_val |= DRAM_MR_CAS_LAT(para->cas - 4);
reg_val |= DRAM_MR_WRITE_RECOVERY(0x5);
} else if (para->type == DRAM_MEMORY_TYPE_DDR2) {
reg_val = DRAM_MR_BURST_LENGTH(0x2);
reg_val |= DRAM_MR_CAS_LAT(para->cas);
reg_val |= DRAM_MR_WRITE_RECOVERY(0x5);
}
reg_val |= DRAM_MR_CAS_LAT(para->cas - 4);
reg_val |= DRAM_MR_WRITE_RECOVERY(ddr3_write_recovery(para->clock));
writel(reg_val, &dram->mr);
writel(para->emr1, &dram->emr);
writel(para->emr2, &dram->emr2);
writel(para->emr3, &dram->emr3);
/* set DQS window mode */
/* disable drift compensation and set passive DQS window mode */
clrsetbits_le32(&dram->ccr, DRAM_CCR_DQS_DRIFT_COMP, DRAM_CCR_DQS_GATE);
#ifdef CONFIG_SUN7I
@@ -524,70 +673,78 @@ unsigned long dramc_init(struct dram_para *para)
if (para->tpr4 & 0x1)
setbits_le32(&dram->ccr, DRAM_CCR_COMMAND_RATE_1T);
#endif
/* reset external DRAM */
setbits_le32(&dram->ccr, DRAM_CCR_INIT);
await_completion(&dram->ccr, DRAM_CCR_INIT);
#ifdef CONFIG_SUN7I
/* setup zq calibration manual */
reg_val = readl(&dram->ppwrsctl);
if ((reg_val & 0x1) == 1) {
/* super_standby_flag = 1 */
reg_val = readl(0x01c20c00 + 0x120); /* rtc */
reg_val &= 0x000fffff;
reg_val |= 0x17b00000;
writel(reg_val, &dram->zqcr0);
/* exit self-refresh state */
clrsetbits_le32(&dram->dcr, 0x1f << 27, 0x12 << 27);
/* check whether command has been executed */
await_completion(&dram->dcr, 0x1 << 31);
udelay(2);
/* dram pad hold off */
setbits_le32(&dram->ppwrsctl, 0x16510000);
await_completion(&dram->ppwrsctl, 0x1);
/* exit self-refresh state */
clrsetbits_le32(&dram->dcr, 0x1f << 27, 0x12 << 27);
/* check whether command has been executed */
await_completion(&dram->dcr, 0x1 << 31);
udelay(2);
/* issue a refresh command */
clrsetbits_le32(&dram->dcr, 0x1f << 27, 0x13 << 27);
await_completion(&dram->dcr, 0x1 << 31);
udelay(2);
}
#endif
/* initialize external DRAM */
mctl_ddr3_initialize();
/* scan read pipe value */
mctl_itm_enable();
if (para->tpr3 & (0x1 << 31)) {
ret_val = dramc_scan_dll_para();
if (ret_val == 0)
para->tpr3 =
(((readl(&dram->dllcr[0]) >> 6) & 0x3f) << 16) |
(((readl(&dram->dllcr[1]) >> 14) & 0xf) << 0) |
(((readl(&dram->dllcr[2]) >> 14) & 0xf) << 4) |
(((readl(&dram->dllcr[3]) >> 14) & 0xf) << 8) |
(((readl(&dram->dllcr[4]) >> 14) & 0xf) << 12
);
} else {
ret_val = dramc_scan_readpipe();
}
/* Hardware DQS gate training */
ret_val = dramc_scan_readpipe();
if (ret_val < 0)
return 0;
/* allow to override the DQS training results with a custom delay */
if (para->dqs_gating_delay)
mctl_set_dqs_gating_delay(0, para->dqs_gating_delay);
/* set the DQS gating window type */
if (para->active_windowing)
clrbits_le32(&dram->ccr, DRAM_CCR_DQS_GATE);
else
setbits_le32(&dram->ccr, DRAM_CCR_DQS_GATE);
mctl_itm_reset();
/* configure all host port */
mctl_configure_hostport();
return get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE);
}
unsigned long dramc_init(struct dram_para *para)
{
unsigned long dram_size, actual_density;
/* If the dram configuration is not provided, use a default */
if (!para)
return 0;
/* if everything is known, then autodetection is not necessary */
if (para->io_width && para->bus_width && para->density)
return dramc_init_helper(para);
/* try to autodetect the DRAM bus width and density */
para->io_width = 16;
para->bus_width = 32;
#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN5I)
/* only A0-A14 address lines on A10/A13, limiting max density to 4096 */
para->density = 4096;
#else
/* all A0-A15 address lines on A20, which allow density 8192 */
para->density = 8192;
#endif
dram_size = dramc_init_helper(para);
if (!dram_size) {
/* if 32-bit bus width failed, try 16-bit bus width instead */
para->bus_width = 16;
dram_size = dramc_init_helper(para);
if (!dram_size) {
/* if 16-bit bus width also failed, then bail out */
return dram_size;
}
}
/* check if we need to adjust the density */
actual_density = (dram_size >> 17) * para->io_width / para->bus_width;
if (actual_density != para->density) {
/* update the density and re-initialize DRAM again */
para->density = actual_density;
dram_size = dramc_init_helper(para);
}
return dram_size;
}

View File

@@ -0,0 +1,162 @@
/*
* Copyright (C) 2013 - ARM Ltd
* Author: Marc Zyngier <marc.zyngier@arm.com>
*
* Based on code by Carl van Schaik <carl@ok-labs.com>.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <config.h>
#include <asm/psci.h>
#include <asm/arch/cpu.h>
/*
* Memory layout:
*
* SECURE_RAM to text_end :
* ._secure_text section
* text_end to ALIGN_PAGE(text_end):
* nothing
* ALIGN_PAGE(text_end) to ALIGN_PAGE(text_end) + 0x1000)
* 1kB of stack per CPU (4 CPUs max).
*/
.pushsection ._secure.text, "ax"
.arch_extension sec
#define ONE_MS (CONFIG_SYS_CLK_FREQ / 1000)
#define TEN_MS (10 * ONE_MS)
.macro timer_wait reg, ticks
@ Program CNTP_TVAL
movw \reg, #(\ticks & 0xffff)
movt \reg, #(\ticks >> 16)
mcr p15, 0, \reg, c14, c2, 0
isb
@ Enable physical timer, mask interrupt
mov \reg, #3
mcr p15, 0, \reg, c14, c2, 1
@ Poll physical timer until ISTATUS is on
1: isb
mrc p15, 0, \reg, c14, c2, 1
ands \reg, \reg, #4
bne 1b
@ Disable timer
mov \reg, #0
mcr p15, 0, \reg, c14, c2, 1
isb
.endm
.globl psci_arch_init
psci_arch_init:
mrc p15, 0, r5, c1, c1, 0 @ Read SCR
bic r5, r5, #1 @ Secure mode
mcr p15, 0, r5, c1, c1, 0 @ Write SCR
isb
mrc p15, 0, r4, c0, c0, 5 @ MPIDR
and r4, r4, #3 @ cpu number in cluster
mov r5, #400 @ 1kB of stack per CPU
mul r4, r4, r5
adr r5, text_end @ end of text
add r5, r5, #0x2000 @ Skip two pages
lsr r5, r5, #12 @ Align to start of page
lsl r5, r5, #12
sub sp, r5, r4 @ here's our stack!
bx lr
@ r1 = target CPU
@ r2 = target PC
.globl psci_cpu_on
psci_cpu_on:
adr r0, _target_pc
str r2, [r0]
dsb
movw r0, #(SUNXI_CPUCFG_BASE & 0xffff)
movt r0, #(SUNXI_CPUCFG_BASE >> 16)
@ CPU mask
and r1, r1, #3 @ only care about first cluster
mov r4, #1
lsl r4, r4, r1
adr r6, _sunxi_cpu_entry
str r6, [r0, #0x1a4] @ PRIVATE_REG (boot vector)
@ Assert reset on target CPU
mov r6, #0
lsl r5, r1, #6 @ 64 bytes per CPU
add r5, r5, #0x40 @ Offset from base
add r5, r5, r0 @ CPU control block
str r6, [r5] @ Reset CPU
@ l1 invalidate
ldr r6, [r0, #0x184]
bic r6, r6, r4
str r6, [r0, #0x184]
@ Lock CPU
ldr r6, [r0, #0x1e4]
bic r6, r6, r4
str r6, [r0, #0x1e4]
@ Release power clamp
movw r6, #0x1ff
movt r6, #0
1: lsrs r6, r6, #1
str r6, [r0, #0x1b0]
bne 1b
timer_wait r1, TEN_MS
@ Clear power gating
ldr r6, [r0, #0x1b4]
bic r6, r6, #1
str r6, [r0, #0x1b4]
@ Deassert reset on target CPU
mov r6, #3
str r6, [r5]
@ Unlock CPU
ldr r6, [r0, #0x1e4]
orr r6, r6, r4
str r6, [r0, #0x1e4]
mov r0, #ARM_PSCI_RET_SUCCESS @ Return PSCI_RET_SUCCESS
mov pc, lr
_target_pc:
.word 0
_sunxi_cpu_entry:
@ Set SMP bit
mrc p15, 0, r0, c1, c0, 1
orr r0, r0, #0x40
mcr p15, 0, r0, c1, c0, 1
isb
bl _nonsec_init
bl psci_arch_init
adr r0, _target_pc
ldr r0, [r0]
b _do_nonsec_entry
text_end:
.popsection

View File

@@ -26,6 +26,11 @@ SECTIONS
*(.data*)
}
. = ALIGN(4);
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
. = .;

View File

@@ -27,6 +27,7 @@ SECTIONS
.text :
{
__start = .;
*(.vectors)
arch/arm/cpu/armv7/start.o (.text)
*(.text*)
} > .sram
@@ -37,6 +38,11 @@ SECTIONS
. = ALIGN(4);
.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
. = ALIGN(4);
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
} > .sram
. = ALIGN(4);
__image_copy_end = .;
_end = .;

View File

@@ -0,0 +1,30 @@
if TEGRA
choice
prompt "Tegra SoC select"
config TEGRA20
bool "Tegra20 family"
config TEGRA30
bool "Tegra30 family"
config TEGRA114
bool "Tegra114 family"
config TEGRA124
bool "Tegra124 family"
endchoice
config SYS_CPU
string
default "arm720t" if SPL_BUILD
default "armv7" if !SPL_BUILD
source "arch/arm/cpu/armv7/tegra20/Kconfig"
source "arch/arm/cpu/armv7/tegra30/Kconfig"
source "arch/arm/cpu/armv7/tegra114/Kconfig"
source "arch/arm/cpu/armv7/tegra124/Kconfig"
endif

View File

@@ -0,0 +1,17 @@
if TEGRA114
choice
prompt "Tegra114 board select"
config TARGET_DALMORE
bool "NVIDIA Tegra114 Dalmore evaluation board"
endchoice
config SYS_SOC
string
default "tegra114"
source "board/nvidia/dalmore/Kconfig"
endif

View File

@@ -0,0 +1,21 @@
if TEGRA124
choice
prompt "Tegra124 board select"
config TARGET_JETSON_TK1
bool "NVIDIA Tegra124 Jetson TK1 board"
config TARGET_VENICE2
bool "NVIDIA Tegra124 Venice2"
endchoice
config SYS_SOC
string
default "tegra124"
source "board/nvidia/jetson-tk1/Kconfig"
source "board/nvidia/venice2/Kconfig"
endif

View File

@@ -0,0 +1,53 @@
if TEGRA20
choice
prompt "Tegra20 board select"
config TARGET_HARMONY
bool "NVIDIA Tegra20 Harmony evaluation board"
config TARGET_MEDCOM_WIDE
bool "Avionic Design Medcom-Wide board"
config TARGET_PAZ00
bool "Paz00 board"
config TARGET_PLUTUX
bool "Avionic Design Plutux board"
config TARGET_SEABOARD
bool "NVIDIA Seaboard"
config TARGET_TEC
bool "Avionic Design Tamonten Evaluation Carrier"
config TARGET_TRIMSLICE
bool "Compulab TrimSlice board"
config TARGET_VENTANA
bool "NVIDIA Tegra20 Ventana evaluation board"
config TARGET_WHISTLER
bool "NVIDIA Tegra20 Whistler evaluation board"
config TARGET_COLIBRI_T20_IRIS
bool "Toradex Colibri T20 board"
endchoice
config SYS_SOC
string
default "tegra20"
source "board/nvidia/harmony/Kconfig"
source "board/avionic-design/medcom-wide/Kconfig"
source "board/compal/paz00/Kconfig"
source "board/avionic-design/plutux/Kconfig"
source "board/nvidia/seaboard/Kconfig"
source "board/avionic-design/tec/Kconfig"
source "board/compulab/trimslice/Kconfig"
source "board/nvidia/ventana/Kconfig"
source "board/nvidia/whistler/Kconfig"
source "board/toradex/colibri_t20_iris/Kconfig"
endif

View File

@@ -0,0 +1,29 @@
if TEGRA30
choice
prompt "Tegra30 board select"
config TARGET_BEAVER
bool "NVIDIA Tegra30 Beaver evaluation board"
config TARGET_CARDHU
bool "NVIDIA Tegra30 Cardhu evaluation board"
config TARGET_COLIBRI_T30
bool "Toradex Colibri T30 board"
config TARGET_TEC_NG
bool "Avionic Design TEC-NG board"
endchoice
config SYS_SOC
string
default "tegra30"
source "board/nvidia/beaver/Kconfig"
source "board/nvidia/cardhu/Kconfig"
source "board/toradex/colibri_t30/Kconfig"
source "board/avionic-design/tec-ng/Kconfig"
endif

View File

@@ -0,0 +1,100 @@
/*
* Copyright (C) 2013 - ARM Ltd
* Author: Marc Zyngier <marc.zyngier@arm.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <common.h>
#include <stdio_dev.h>
#include <linux/ctype.h>
#include <linux/types.h>
#include <asm/global_data.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <asm/armv7.h>
#include <asm/psci.h>
static int fdt_psci(void *fdt)
{
#ifdef CONFIG_ARMV7_PSCI
int nodeoff;
int tmp;
nodeoff = fdt_path_offset(fdt, "/cpus");
if (nodeoff < 0) {
printf("couldn't find /cpus\n");
return nodeoff;
}
/* add 'enable-method = "psci"' to each cpu node */
for (tmp = fdt_first_subnode(fdt, nodeoff);
tmp >= 0;
tmp = fdt_next_subnode(fdt, tmp)) {
const struct fdt_property *prop;
int len;
prop = fdt_get_property(fdt, tmp, "device_type", &len);
if (!prop)
continue;
if (len < 4)
continue;
if (strcmp(prop->data, "cpu"))
continue;
fdt_setprop_string(fdt, tmp, "enable-method", "psci");
}
nodeoff = fdt_path_offset(fdt, "/psci");
if (nodeoff < 0) {
nodeoff = fdt_path_offset(fdt, "/");
if (nodeoff < 0)
return nodeoff;
nodeoff = fdt_add_subnode(fdt, nodeoff, "psci");
if (nodeoff < 0)
return nodeoff;
}
tmp = fdt_setprop_string(fdt, nodeoff, "compatible", "arm,psci");
if (tmp)
return tmp;
tmp = fdt_setprop_string(fdt, nodeoff, "method", "smc");
if (tmp)
return tmp;
tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_suspend", ARM_PSCI_FN_CPU_SUSPEND);
if (tmp)
return tmp;
tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_off", ARM_PSCI_FN_CPU_OFF);
if (tmp)
return tmp;
tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_on", ARM_PSCI_FN_CPU_ON);
if (tmp)
return tmp;
tmp = fdt_setprop_u32(fdt, nodeoff, "migrate", ARM_PSCI_FN_MIGRATE);
if (tmp)
return tmp;
#endif
return 0;
}
int armv7_update_dt(void *fdt)
{
#ifndef CONFIG_ARMV7_SECURE_BASE
/* secure code lives in RAM, keep it alive */
fdt_add_mem_rsv(fdt, (unsigned long)__secure_start,
__secure_end - __secure_start);
#endif
return fdt_psci(fdt);
}

View File

@@ -13,17 +13,10 @@
#include <asm/armv7.h>
#include <asm/gic.h>
#include <asm/io.h>
#include <asm/secure.h>
unsigned long gic_dist_addr;
static unsigned int read_cpsr(void)
{
unsigned int reg;
asm volatile ("mrs %0, cpsr\n" : "=r" (reg));
return reg;
}
static unsigned int read_id_pfr1(void)
{
unsigned int reg;
@@ -37,25 +30,8 @@ static unsigned long get_gicd_base_address(void)
#ifdef CONFIG_ARM_GIC_BASE_ADDRESS
return CONFIG_ARM_GIC_BASE_ADDRESS + GIC_DIST_OFFSET;
#else
unsigned midr;
unsigned periphbase;
/* check whether we are an Cortex-A15 or A7.
* The actual HYP switch should work with all CPUs supporting
* the virtualization extension, but we need the GIC address,
* which we know only for sure for those two CPUs.
*/
asm("mrc p15, 0, %0, c0, c0, 0\n" : "=r"(midr));
switch (midr & MIDR_PRIMARY_PART_MASK) {
case MIDR_CORTEX_A9_R0P1:
case MIDR_CORTEX_A15_R0P0:
case MIDR_CORTEX_A7_R0P0:
break;
default:
printf("nonsec: could not determine GIC address.\n");
return -1;
}
/* get the GIC base address from the CBAR register */
asm("mrc p15, 4, %0, c15, c0, 0\n" : "=r" (periphbase));
@@ -72,6 +48,18 @@ static unsigned long get_gicd_base_address(void)
#endif
}
static void relocate_secure_section(void)
{
#ifdef CONFIG_ARMV7_SECURE_BASE
size_t sz = __secure_end - __secure_start;
memcpy((void *)CONFIG_ARMV7_SECURE_BASE, __secure_start, sz);
flush_dcache_range(CONFIG_ARMV7_SECURE_BASE,
CONFIG_ARMV7_SECURE_BASE + sz + 1);
invalidate_icache_all();
#endif
}
static void kick_secondary_cpus_gic(unsigned long gicdaddr)
{
/* kick all CPUs (except this one) by writing to GICD_SGIR */
@@ -83,35 +71,7 @@ void __weak smp_kick_all_cpus(void)
kick_secondary_cpus_gic(gic_dist_addr);
}
int armv7_switch_hyp(void)
{
unsigned int reg;
/* check whether we are in HYP mode already */
if ((read_cpsr() & 0x1f) == 0x1a) {
debug("CPU already in HYP mode\n");
return 0;
}
/* check whether the CPU supports the virtualization extensions */
reg = read_id_pfr1();
if ((reg & CPUID_ARM_VIRT_MASK) != 1 << CPUID_ARM_VIRT_SHIFT) {
printf("HYP mode: Virtualization extensions not implemented.\n");
return -1;
}
/* call the HYP switching code on this CPU also */
_switch_to_hyp();
if ((read_cpsr() & 0x1F) != 0x1a) {
printf("HYP mode: switch not successful.\n");
return -1;
}
return 0;
}
int armv7_switch_nonsec(void)
int armv7_init_nonsec(void)
{
unsigned int reg;
unsigned itlinesnr, i;
@@ -147,11 +107,13 @@ int armv7_switch_nonsec(void)
for (i = 1; i <= itlinesnr; i++)
writel((unsigned)-1, gic_dist_addr + GICD_IGROUPRn + 4 * i);
smp_set_core_boot_addr((unsigned long)_smp_pen, -1);
#ifndef CONFIG_ARMV7_PSCI
smp_set_core_boot_addr((unsigned long)secure_ram_addr(_smp_pen), -1);
smp_kick_all_cpus();
#endif
/* call the non-sec switching code on this CPU also */
_nonsec_init();
relocate_secure_section();
secure_ram_addr(_nonsec_init)();
return 0;
}

View File

@@ -0,0 +1,43 @@
if ZYNQ
choice
prompt "Xilinx Zynq board select"
config TARGET_ZYNQ_ZED
bool "Zynq ZedBoard"
config TARGET_ZYNQ_MICROZED
bool "Zynq MicroZed"
config TARGET_ZYNQ_ZC70X
bool "Zynq ZC702/ZC706 Board"
config TARGET_ZYNQ_ZC770
bool "Zynq ZC770 Board"
endchoice
config SYS_CPU
string
default "armv7"
config SYS_BOARD
string
default "zynq"
config SYS_VENDOR
string
default "xilinx"
config SYS_SOC
string
default "zynq"
config SYS_CONFIG_NAME
string
default "zynq_zed" if TARGET_ZYNQ_ZED
default "zynq_microzed" if TARGET_ZYNQ_MICROZED
default "zynq_zc70x" if TARGET_ZYNQ_ZC70X
default "zynq_zc770" if TARGET_ZYNQ_ZC770
endif

View File

@@ -34,7 +34,7 @@ void zynq_ddrc_init(void)
/* ECC is enabled when memory is in 16bit mode and it is enabled */
if ((ecctype == ZYNQ_DDRC_ECC_SCRUBREG_ECCMODE_SECDED) &&
(width == ZYNQ_DDRC_CTRLREG_BUSWIDTH_16BIT)) {
puts("Memory: ECC enabled\n");
puts("ECC enabled ");
/*
* Clear the first 1MB because it is not initialized from
* first stage bootloader. To get ECC to work all memory has
@@ -42,6 +42,6 @@ void zynq_ddrc_init(void)
*/
memset((void *)0, 0, 1 * 1024 * 1024);
} else {
puts("Memory: ECC disabled\n");
puts("ECC disabled ");
}
}

View File

@@ -8,7 +8,7 @@
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/spl.h>
#include <asm/spl.h>
#include <asm/arch/sys_proto.h>
DECLARE_GLOBAL_DATA_PTR;

View File

@@ -22,6 +22,7 @@ SECTIONS
.text :
{
__image_copy_start = .;
*(.vectors)
CPUDIR/start.o (.text*)
*(.text*)
} > .sram

View File

@@ -25,6 +25,7 @@ SECTIONS
.text :
{
__start = .;
*(.vectors)
arch/arm/cpu/armv7/start.o (.text*)
*(.text*)
} >.sram

View File

@@ -14,3 +14,4 @@ obj-y += clock.o
obj-y += lowlevel_init.o
obj-y += pinmux-common.o
obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o
obj-$(CONFIG_TEGRA124) += vpr.o

View File

@@ -163,4 +163,7 @@ void s_init(void)
/* init the cache */
config_cache();
/* init vpr */
config_vpr();
}

View File

@@ -27,11 +27,12 @@ enum {
UART_COUNT = 5,
};
#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) || \
defined(CONFIG_TEGRA114)
/*
* Boot ROM initializes the odmdata in APBDEV_PMC_SCRATCH20_0,
* so we are using this value to identify memory size.
*/
unsigned int query_sdram_size(void)
{
struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
@@ -72,6 +73,21 @@ unsigned int query_sdram_size(void)
}
#endif
}
#else
#include <asm/arch/mc.h>
/* Read the RAM size directly from the memory controller */
unsigned int query_sdram_size(void)
{
struct mc_ctlr *const mc = (struct mc_ctlr *)NV_PA_MC_BASE;
u32 size_mb;
size_mb = readl(&mc->mc_emem_cfg);
debug("mc->mc_emem_cfg (MEM_SIZE_MB) = 0x%08x\n", size_mb);
return size_mb * 1024 * 1024;
}
#endif
int dram_init(void)
{

Some files were not shown because too many files have changed in this diff Show More