Currently uboot wrongly uses 25mV / step for dcdc3, this is a copy and paste
error introduced when adding the axp152_mvolt_to_target during review of the
axp152.c driver. This results in u-boot setting Vddr to 2.3V instead of 1.5V.
This commit fixes this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
With the introduction of CONFIG_LOCALVERSION support we cannot build
tools without having a config file (as we won't know our PLAIN_VERSION
until then).
Reported-by: Otavio Salvador <otavio@ossystems.com.br>
Signed-off-by: Tom Rini <trini@ti.com>
Commit 832472 "tools: socfpga: Add socfpga preloader signing
to mkimage" added tools/socfpga.c which relies on htole32,
le32toh and friends. While compiler.h includes these protypes
for linux from endian.h, it doesn't do so for FreeBSD. Hence
include <sys/endian.h> for FreeBSD.
Cc: Marek Vasut <marex@denx.de>
CC: Tom Rini <trini@ti.com>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Update readme file for Keystone II EVM boards to actual sources.
Also correct some typos. For now the Edison evaluation board is
added, README for K2E is mostly the same, so update README to
contain information also for K2E evm. Rename file to README as
it contains information for all keystone evm boards.
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
The K2HK and K2E boards support SPL by default, so add
CONFIG_SPL option. Also export CONFIG_ARM, CONFIG_ARCH_KEYSTONE
and TARGET_K2*_EVM options to spl/.config as they are the same.
So now it's convinient to build gph images using only two commands:
make k2hk_evm_defconfig
make u-boot-spi.gph
Acked-By: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Since on powerpc phys_size_t can be unsigned long long, this printout
line can result in a not nice compile warning.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Acked-by: Simon Glass <sjg@chromium.org>
The lines COL (collision detect) and CRS (carrier sense) needs to be connected
and muxed to the CPSW MAC for a proper function in half-duplex Mode of the
interface.
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
Cc: Tom Rini <trini@ti.com>
A SPL/TPL enabled target would was not recognized as
such by BSD sed, since it relies on a GNU extension.
Instead of or-ing just spell out both matches.
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Acked-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
remove the seldomly used EXT2 support because the U-Boot binary will
not fit into the 512KiB flash otherwise.
Signed-off-by: David Müller <d.mueller@elsoft.ch>
fix broken SPI access by adding/activating BOARD_EARLY_INIT_F
functionality and calling spi_init_f() from there.
Signed-off-by: David Müller <d.mueller@elsoft.ch>
A number of network related files were imported from the LiMon
project; these contain a somewhat unclear license statement:
Copyright 1994 - 2000 Neil Russell.
(See License)
I analyzed the source code of LiMon v1.4.2 which was used for this
import. It does not contain any "License" file, but the top level
directory contains a file "COPYING", which turns out to be GPL v2
of June 1991. So it is legitimate to conclude that the LiMon derived
files are also to be released under GPLv2. Mark them as such.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Fix typo of commit d4e53f063d.
i2c2 pullup resisters are controlled by bit 0 of CONTROL_PROG_IO1.
It's value after reset is 0x00100001.
In order to clear bit 0, original code write 0xfffffffe to
CONTROL_PROG_IO1 and toggle almost all default values.
Original code affect following:
* disable i2c1 pullup resisters
* increase far end load setting for many modules
* setup invalid SC/LB combination
Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
CC: Tom Rini <trini@ti.com>
CC: Steve Kipisz <s-kipisz2@ti.com>
This board has been orphaned for more than 6 months.
It is the last board defining CONFIG_APM821XX.
The code inside #ifdef CONFIG_APM821XX should be removed too.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
In some cases, the last lines of SPL or TPL are not output to a file.
The entries remaining in the "unmatched" variable must be flushed.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
At least on OMAP, init_sata() no longer performs scsi_scan()
so we must do it explicitly here.
Cc: Dan Murphy <dmurphy@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
On OMAP platforms, SATA controller provides the SCSI subsystem
so implement scsi_init().
Get rid of the unnecessary sata_init() call from dra7xx-evm
and omap5-uevm board files.
Signed-off-by: Roger Quadros <rogerq@ti.com>
The DMA/FIS buffers are set in ahci_port_start() which is called
after ahci_host_init(). So don't start the DMA engine here
(i.e. don't set FIS_RX)
This fixes the following error at kernel boot on OMAP platforms (e.g. DRA7x)
WARNING: CPU: 0 PID: 0 at drivers/bus/omap_l3_noc.c:147 l3_interrupt_handler+0x260/0x358()
44000000.ocp:L3 Custom Error: MASTER SATA TARGET GPMC (Idle): Data Access in User mode during Functional access
Signed-off-by: Roger Quadros <rogerq@ti.com>
Commit 12cc543767 'omap3: overo: Select
fdtfile for expansion board' wrongly missed the operator in the fdtfile
test. Update the test to only overwrite an empty fdtfile environment
variable.
Signed-off-by: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
Commit 294b91a581 moved initr_malloc
earlier than initr_unlock_ram_in_cache. This causes issue on T4240.
It may be related to locked L1 d-cache and unlocked L2 cache. D-
cache could and should be unlock earlier for normal operation.
This patch moves initr_unlock_ram_in_cache before initr_malloc. It
has been verified on the following boards, in which only T4240QDS
suffered and has been since fixed: T4240QDS, T2080QDS, P5040DS,
P4080DS, MPC8572DS, MPC8536DS, MPC8641HPCN, B4860QDS.
Signed-off-by: York Sun <yorksun@freescale.com>
CC: Scott Wood <scottwood@freescale.com>
CC: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
On a couple of platforms I've tripped over long PXE append lines overflowing
this array, due to having CONFIG_SYS_CBSIZE == 256. When doing preseeded Debian
installs it's pretty trivial to exceed that.
Since the symptom can be a silent hang or a crash add a check. Of course the
affected boards would also need an increased CBSIZE to actually work.
Note that due to the printing of the final bootargs string CONFIG_SYS_PBSIZE
also needs to be sufficiently large.
Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
[trini: Use %zd not %d in printf for all args]
Signed-off-by: Tom Rini <trini@ti.com>
The function nand_flash_detect_ext_param_page() requires
NAND_CMD_RNDOUT command supported. It is necessary to detect some
types of ONFi-compliant devices. Without it, the error message
"unsupported command received 0x5" is shown.
Let's support this command on the Denali NAND controller driver.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Chin Liang See <clsee@altera.com>
NAND_CMD_PARAM (0xEC) command is not working on the Denali
NAND controller driver.
Unlike NAND_CMD_READID (0x90), when the NAND_CMD_PARAM command
is followed by an address cycle, the target device goes busy.
(R/B# is deasserted)
Wait until the parameter data are ready.
In addition, unnecessary clear_interrupts() should be removed.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Chin Liang See <clsee@altera.com>
rmobile/lowlevel_init_ca15.S are common in r8a7790, r8a7791 and r8a7794 of
rmobile SoCs. The initialize L2 cache in lowlevel_init_ca15.S only needed
for Cortex-A15. The r8a7794 is Cortex-A7, not Cortex-A15.
This adds Skip to initialize L2 cache when r8a7794.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
rmobile/lowlevel_init_ca15.S are common in r8a7790 and r8a7791 of
rmobile SoC. But L2 cache of r8a7791 does not use L2CTLR[5].
This adds fix to set L2CTLR [5] only when the r8a7790.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
SCIF of koelsch use external clock mode.
This enables external clock mode on koelsch board.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
SCIF of lager use external clock mode.
This enables external clock mode on lager board.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
The clock of SCIF (serial port) of lager is supplied from External
Clock. And value of clock is 14.7456MHz.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
In order for the gmac nic to work reliable on the Bananapi, we need to set
bits 10-12 GTXDC "GMAC Transmit Clock Delay Chain" of the GMAC clk register
(0x01c20164) to 3.
Without this about 9 out of 10 ethernet packets get lost, with this setting
there is no packet loss.
So far setting these bits is only necessary on the Bananapi, so this commit
solves this with a bit of #ifdef CONFIG_BANANAPI code. If in the future we
need to do something similar for other boards, we can create a specific
CONFIG_FOO option for this then.
Reported-by: Karsten Merker <merker@debian.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Tested-by: Karsten Merker <merker@debian.org>
Tested-by: Zoltan HERPAI <wigyori@openwrt.org>
Tested-by: Tony Zhang <tony.zhang@lemaker.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
This change fixes suspend/resume issue in the kernel caused
by the wrong 'aclk_cores' clock value expected by the kernel.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Move cache handling code to C file, and add enable_caches() and
disable_caches() functions.
Signed-off-by: Robert Baldyga <r.baldyga@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Enable this feature to support driver model before relocation.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Change this board to add a device tree.
This also adds a pinmux header file although it is not used as yet.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Most of the smdkv310 features are common with other exynos4 boards. To
permit easier addition of driver model support, use the common file and
add a device tree file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Most of the arndale features are common with other exynos5250 boards. To
permit easier addition of driver model support, use the common file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
These boards do not in fact have a Chrome OS EC, nor a TPS565090 PMIC, so
move the settings into a separate common file to be used by those that need
it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
A few things are common but are not in the common file. Fix this and
rename the file to fit with the other exynos*-common files.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Since exynos4 and exyno5 share many settings, we should move these into
a common file to avoid duplication.
In effect the changes are that all exynos boards now have EXT4 and FAT
write support. This affects exynos5250 and exynos5420 which previously
did not. This also disables the ext2 commands which are equivalent to
ext4 anyway.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
We want exynos5250-dt.h to be a board which can support any exynos5250
device. This matches the naming used by Linux. As a first step, rename
the existing -dt files to -common to make it clear they are common files,
and not specific boards.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Add a keyboard definition so that the keyboard can be used on pit.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
With the driver model conversion we are going to be using driver model for
SPI and not for I2C. This works OK so long as a board doesn't need both
dm and non-dm versions of the cros_ec driver. Since pit uses SPI and snow
uses I2C we need to split the configs so that only one driver is compiled
for each platform.
We can fix this later when driver model supports I2C.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Exynos 5250 boards (snow, spring) use the I2C driver but Exynos 5420 boards
cannot due to a hardware design decision. Select the correct driver to use
in each case.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Unfortunately on Pit the AP has no direct access to the tps65090 but must
talk through the EC (over SPI) to the EC's I2C bus.
When driver model supports PMICs this will be relatively easy. In the
meantime the best approach is to duplicate the driver. It will be refactored
once driver model support is expanded.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Things run faster when the data cache is enabled, so turn it on along with
the 'dcache' command.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
The device seems to hang in SPL if the full speed is used when booting from
USB, perhaps because the PMIC has not been set to the maximum ARM core
voltage yet. Slow it down to a reliable speed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Removed settings in unsupported register fields. They didn’t
do anything, and in most cases, were not documented in the
reference manual.
Changed register settings to comply with JEDEC required values.
Changed timing parameters because they included full clock
periods that were doing nothing.
Signed-off-by: Anthony Felice <tony.felice@timesys.com>
[rebased on v2014.10-rc2]
Signed-off-by: Stefan Agner <stefan@agner.ch>
Without NULL termination, various commands will read past the
end of input. In particular, this was noticed with error()
calls in cb_getvar and simple_strtoul() in cb_download.
Since the download callback happens elsewhere, the 4k buffer
should always be sufficient to handle command arguments.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
This bit allows the MUSB controller to negotiate for high-speed mode when
the device is reset by the hub. If unset, Babble errors occur with
high-speed mass storage devices right after the first packet. This condition
is not caught by the interrupt handles in U-Boot, so no recovery is done,
and the USB communication is stuck.
To fix this, set the bit unconditionally, not only for
CONFIG_USB_GADGET_DUALSPEED but also for host-only modes.
Signed-off-by: Daniel Mack <zonque@gmail.com>
Enable 'fastboot' command.
This is currently enabled but not yet functional. Including it in the
configuration will ease further testing and development as discussed
on the mailing list.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Some users (QNX and Windows CE users in particular) have asked
to disable the Penguin shown on the display at boot time.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Increase the maximum number of arguments allowed by the Hush parser.
This prevents errors when users or scripts aren't quoting parameters
when setting the "bootargs" variable et al.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Enable the "i2c edid" command to query data from an attached
HDMI monitor.
Usage is typically this:
U-Boot > i2c dev 1
U-Boot > i2c edid 0x50
...
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
If no boot script was found, expose internal storage over the
USB mass storage gadget to allow easy programming.
This is especially useful when SD cards are inaccessible or when
loading SATA drives.
More details are available in this blog post:
http://boundarydevices.com/u-boot-usb-mass-storage-gadget/
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Remove the individual attempts to load using ext2 and fat, replace with the
generic load command supporting available filesystem types.
Signed-off-by: Kevin Mihelich <kevin@archlinuxarm.org>
This patch enables boot to USB storage devices by expanding on the list
of boot devices.
Because the USB startup currently takes a long time, it places USB at
the end of the list of supported devices.
You can over-ride the boot order using the bootdevs environment variable.
For instance, this will make USB the first (highest priority) device:
U-Boot > setenv bootdevs usb mmc sata
U-Boot > saveenv
Signed-off-by: Diego Rondini <diego.rondini@kynetics.it>
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
The HPD pin and RX_SENSE registers have proven to be less reliable
than using I2C on the EDID pins for detection of an HDMI monitor.
In particular, when the HDMI output is reset through a "reboot"
cycle, the detect_hdmi() routine often bounces, resulting in
a failure to detect a connected monitor.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Add support for WVGA (800x480) panels using VESA GTF timings over
LVDS.
No auto-detection is supported, so you must configure this panel
manually through the 'panel' environment variable:
U-Boot > setenv panel svga
U-Boot > saveenv && reset
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Add support for an Ampire 1024x600 LVDS panel with integrated Ilitek
capacitive touch screen.
Auto-detection is enabled, so no explicit configuration is needed.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Add support for 800x600 18-bit RGB displays using VESA GTF timings.
No auto-detection is supported, so you must configure this panel
manually through the 'panel' environment variable:
U-Boot > setenv panel svga
U-Boot > saveenv && reset
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Add support for the Touch Revolution Fusion7 display: 800x480 RGB
with a custom F0710A resistive touch controller.
Auto-detection of this panel is supported so no configuration is
required.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
This patch adds support for LVDS WXGA displays that use the SPWG encoding
standard instead of JEIDA.
No auto-detection is enabled and you must explicitly set the 'panel'
environment variable:
U-Boot > setenv panel LDB-WXGA-S
U-Boot > saveenv && reset
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Add support for LG 9.7" LVDS panel (1024x768) with integrated eGalax
touch screen.
Note that this panel differs only slightly from the Hannstar XGA panel
(margins).
No auto-detection is available because it shares the same touch controller
as the Hannstar-XGA display, so you'll need to configure it through the
'panel' environment variable:
U-Boot > setenv panel LG-9.7
U-Boot > saveenv && reset
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Add support for a 1/4 VGA panel with a 24-bit RGB interface.
No auto-detection is enabled, so you must configure the 'panel'
environment variable to use this display:
U-Boot > setenv panel qvga
U-Boot > saveenv && reset
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Add support for Boundary Devices 7" and 10.1" 1280x800 displays with
integrated FocalTech ft5x06 10-point touch controller.
Because they share the touch controller with the 1024x600 displays,
auto-detection is disabled and you must explicitly set the 'panel'
environment variable:
U-Boot > setenv panel LDB-WXGA
U-Boot > saveenv && reset
Signed-off-by: Robert Winkler <robert.winkler@boundarydevices.com>
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Include declarations of board_ehci callbacks to prevent compiler warnings
and enforce function prototypes.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Declare locally-used data structures and functions as
static and pull in header files to prevent compiler warnings
of "Should it be static?" when building with "make C=1".
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Configure CLKO outputs for SGTL5000, CSI camera.
The sys_mclk output for the SGTL500 in particular prevents
Windows CE from properly driving audio.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Pads SD2_CLK/CMD/DAT0-3 are connected to an SDIO WiFi device on
Nitrogen and unconnected on BD-SL-i.MX6 (sabre lite).
Configure them as SDIO pins to prevent them from being in a state
that confuses the WiFi part.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
The same logic applies to both SD card slots, only with different
GPIOs and the code should make that easier to see.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Several customers have asked to leave the display quiet during
boot, so allow the user to express this request by the presence
of environment variable "novideo".
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Split the SoCFPGA configuration into SoC-specific part which is
common for all boards (socfpga_cyclone5_common.h) and a board
specific part. There is currently only one board, which is the
generic SoCFPGA board (socfpga_cyclone5.h), but there are more
to come.
This is necessary due to various features of the boards, which
unfortunatelly cannot be autodetected.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
Reorganize and cleanup the configuration file for SoCFPGA. There
is no functional change after this cleanup. This was necessary,
since the file was a wild mess and it was impossible to make sense
of it's content, let alone change something without breaking some
other thing. This patch puts the contents on par with regular U-Boot
standards.
Also remove unused preprocessor symbols CONFIG_SINGLE_BOOTOADER
and CONFIG_USE_IRQ, which is undefined by default. Finally, do
logical reordering of the defines in the file so it's much more
readable. The reordering was also necessary for the splitting
as the initial one was messy.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Add command to enable and disable the bridges between HPS and FPGA.
This patch does have a checkpatch issue with the assembler portion,
checkpatch correctly complains that there should be no whitespace
before quoted newline. I do not agree that fixing this specific
checkpatch issue will improve the readability, thus this one is not
addressed.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Wolfgang Denk <wd@denx.de>
Move icache_enable() and dcache_enable() function calls from
board code into the CPU code and into the enable_caches()
function. This is how the cache enabling code was designed
to work.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Wolfgang Denk <wd@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
Add code which configures the AMBA NIC-301 and the SCU on the SoCFPGA .
The code sets the access permissions for the CPU to the AMBA slaves such
that the CPU can access them in both secure and non-secure mode.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Add function to enable and disable FPGA bridges. This code is used
by the FPGA manager to disable the bridges before programming the
FPGA and will later be also used by the initialization code for the
chip to put the chip into well defined state during startup.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
Add code necessary to program the FPGA part of SoCFPGA from U-Boot
with an RBF blob. This patch also integrates the code into the
FPGA driver framework in U-Boot so it can be used via the 'fpga'
command.
Signed-off-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
V2: Move the not-CPU specific stuff into drivers/fpga/ and base
this on the cleaned up altera FPGA support.
Add function to initialize the EMAC blocks upon board startup.
The preprocessor guards against building on SoCFPGA-VT and against
SPL build are not needed as those are handled implicitly via both
SPL framework and the socfpga_cyclone5.h config file, which will
not define CONFIG_DESIGNWARE_ETH if building for SoCFPGA-VT.
We cannot handle two EMAC ethernet blocks yet, therefore the ifdefs.
Once there is hardware using both EMAC blocks, this ifdef will have
to go.
Signed-off-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Add functions to reset the EMAC ethernet blocks. We cannot handle
two EMAC ethernet blocks yet, therefore the ifdefs. Once there is
hardware using both EMAC blocks, this ifdef will have to go.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
Add the missing pieces from the reference clock code from Altera. This
puts the code on par with the Altera U-Boot fork for all but the SDRAM
self-refresh bits, which are not part of this patch.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
Add the entire bulk of code to read out clock configuration from the SoCFPGA
CPU registers. This is important for MMC, QSPI and UART drivers as otherwise
they cannot determine the frequency of their upstream clock.
Signed-off-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
V2: Fixed the L4 MP clock divider and synced the clock code with latest
rocketboards codebase (thanks Dinh for pointing this out)
This adds watchdog disable. It is neccessary for running Linux kernel.
Signed-off-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
V2: Move RSTMGR_PERMODRST_L4WD0_LSB to reset_manager.h
Reset watchdog only if CONFIG_HW_WATCHDOG is undefined (the default)
Like many platforms, the Altera socfpga platform requires that the
preloader be "signed" in a certain way or the built-in boot ROM will
not boot the code.
This change automatically creates an appropriately signed preloader
from an SPL image.
The signed image includes a CRC which must, of course, be generated
with a CRC generator that the SoCFPGA boot ROM agrees with otherwise
the boot ROM will reject the image.
Unfortunately the CRC used in this boot ROM is not the same as the
Adler CRC in lib/crc32.c. Indeed the Adler code is not technically a
CRC but is more correctly described as a checksum.
Thus, the appropriate CRC generator is added to lib/ as crc32_alt.c.
Signed-off-by: Charles Manning <cdhmanning@gmail.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
V2: - Zap unused constant
- Explicitly print an error message in case of error
- Rework the hdr_checksum() function to take the *header directly
instead of a plan buffer pointer
Fix remaining cache alignment issues in the DWC Ethernet driver.
Please note that the cache handling in the driver is making the
code hideous and thus the next patch cleans that up. In order to
make this change reviewable though, the cleanup is split from it.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Acked-by: Pavel Machek <pavel@denx.de>
The DMA descriptors used by the DW MMC block must be aligned to cacheline
size, otherwise we are unable to properly flush/inval cache over them and
we get data corruption.
The reason I chose this approach of expanding the structure is because
the driver allocates the descriptors in bulk. This approach does waste
space by inserting slop inbetween the descriptors, but it makes access
to the descriptors easy as the compiler does know the real size of the
structure. It also makes cache operations easy, since the size of the
structure is cache aligned and the structure start address is as well.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Acked-by: Pavel Machek <pavel@denx.de>
Add a table of FPGA family with matching functions associated with
it and make all the code just look up the family in that table and
call the associated function instead of the horrible switch voodoo
which was duplicated all over the place.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
This patch adds support for the OT1200 series of devices.
Following components are used in u-boot:
+ ethernet
+ i2c
+ emmc
+ gpio
For more details see README.
Changes v1 > v2
- make use of enable_cspi_clock(..)
- fix usage of OUTPUT_40OHM define
- added README
Changes v2 > v3
- improve spelling in README
- added own copy of mx6q_4x_mt41j128.cfg
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Update DDR calibration settings based on a larger test set.
The initial values were gathered on a small number of boards,
and have been found to fail on some boards under load.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
PERST_GPIO and POWER_GPIO are currently swapped.
Fix the GPIO assignments as per the board schematics.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Trying to enumerate USB devices connected via ULPI to T20 failed as
follows:
USB2: ULPI integrity check failed
Git bisecting revealed the following commit being at odds:
commit 2d34151f75
usb: tegra: refactor PHY type selection
Looking at above commit one quickly identifies a copy paste error which
this patch fixes. Happy ULPIing again (;-p).
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Besides converting the LS-XHL and LS-CHLv2 to generic board, fix a typo
which accidentally reverted the bootsource to 'hdd' although the default
bootsource should be 'legacy'.
Cc: Tom Rini <trini@ti.com>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
Force full-speed (12 Mbit/s) operation if CONFIG_USB_GADGET_DUALSPEED
is not defined.
The controller is capable of high-speed (480 Mbit/s) operation,
but some designs may require the use of lower-speed operation.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
When download is ongoing, if the actual size of one transfer
is not the same as BYTES_PER_DOT, which will cause the dot
won't print anymore. Then it will let the user thinking it
is stuck, actually it is transfering without dot printed.
So, improve the method to show the progress bar (print dot).
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Marek Vasut <marex@denx.de>
Without this flag, tools like Alex Page's USB Image Tool
won't see drives exposed over USB Gadget as removable,
and won't allow access to them.
http://www.alexpage.de/usb-image-tool/
The code was pulled from the main-line kernel:
drivers/usb/gadget/function/f_mass_storage.c
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Use the new force parameter to make the stdio_deregister succeed, replacing
stdin with a nulldev, and assume that the usb keyboard will come back after
the reset.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
In some cases we really want to move forward with a deregister, add a force
parameter to allow this, and replace the dev with a nulldev in this case.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
We now always properly deregister the keyboard before calling
drv_usb_kbd_init(), so we can drop the check for already being registered.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
We need to call usb_kbd_deregister() before calling usb_stop().
usbkbd's stdio_dev->priv points to the usb_device, and usb_kbd_testc
dereferences usb_device->privptr.
usb_stop zeros usb_device, leaving usb_device->privptr NULL, causing
bad things (tm) to happen once control returns to the main loop and
usb_kbd_testc gets called.
Calling usb_kbd_deregister() avoids this. Note that we do not allow
the "usb reset" to continue when the deregister fails. This will be fixed
in a later patch.
For the same reasons always fail "usb stop" if the usb_kbd_deregister() fails,
even in the force path. This can happen when CONFIG_SYS_STDIO_DEREGISTER is
not set.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Periodic schedules tracks how many int_queue-s are active, and decides whether
or not to en/disable the periodic schedule based on this. This is clearly
a per controller thing.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
When we first start an int queue, the qh's overlay area is all zeros. This
gets filled by the hc with the actual qtd values as soon as it advances
the queue, but we may call poll_int_queue before then, in which case we
would think the transfer has completed as the hc has not yet copied the
qt_token to the overlay, so the active flag is not set.
This fixes this by checking the actual qtd token, rather then the overlay.
This also fixes a (theoretical) race where we see the completion in the
overlay and free and re-use the qtd before the hc has completed writing back
the overlay to the actual qtd.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
For full / low speed devices we need to get the devnum and portnr of the tt,
so of the first upstream usb-2 hub, not of the parent device (which may be a
usb-1 hub).
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Partially revert commit 0d01f66d23 (CFI: cfi_flash write fix for AMD
legacy).
flash_full_status_check() used to skip status register parsing when
flash_status_check() returns OK. This is wrong since flash_status_check()
must return OK for other status bits to be valid.
Cc: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>
The SPL-mode driver for Denali(Cadence) NAND Flash Memory Controller IP.
This driver requires two CONFIG macros:
- CONFIG_SPL_NAND_DENALI
Define to enable this driver.
- CONFIG_SYS_NAND_BAD_BLOCK_POS
Specify bad block mark position in the oob space. Typically 0.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Scott Wood <scottwood@freescale.com>
Commit 3eb3e72a3f (nand/denali: Adding Denali NAND driver support)
introduced some new options, and some of them were documented by
commit f9860cf081 (nand/denali: Document CONFIG symbols).
This commit allows users to enable/disable them via Kconfig
with more detailed help docs.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Scott Wood <scottwood@freescale.com>
dw_mmc driver was responding to errors with debug(). Change that to
prinf so that any errors are immediately obvious. Also adjust english
in comments.
Signed-off-by: Pavel Machek <pavel@denx.de>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
sub-command 'bootpart-resize' check for argc == 4,
it will retrun CMD_RET_FAILURE when argc value not matched.
but bootpart-resize's maxarg is 3, which means you never execute
this sub-command successfully.
fix it by change bootpart-resize maxarg to 4.
Signed-off-by: wally.yeh <wally.yeh@atrustcorp.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pierre Aubert <p.aubert@staubli.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
After setting the bus width, the extended CSD register is read. Some selected
fields are compared with previously read extended CSD register fields. In this
comparison the EXT_CSD_ERASE_GROUP_DEF field is compared. But this field is
previously written under certain circumstances. And then the comparison fails.
Only compare read-only fields. Therefore compare field EXT_CSD_HC_WP_GRP_SIZE
instead of field EXT_CSD_ERASE_GROUP_DEF.
Signed-off-by: Mario Schuknecht <mario.schuknecht@dresearch-fe.de>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
In function mvebu_mmc_write notice command timeout. It is possible that a
command is done, but a timeout occurred.
Enable timeout in set bus function.
Set window registers. Without that I could not use the driver on a Kirkwood
88F6282 SoC.
Set high capacity and 52MHz driver feature.
Signed-off-by: Mario Schuknecht <mario.schuknecht@dresearch-fe.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
The code to set the MMC partition uses an weak function to obtain the
correct partition number. Use that instead of the compile-time default
when deciding whether it needs to switch back.
Fixes: 6e7b7df4df ("env_mmc: support env partition setup in runtime")
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Acked-by: Dmitry Lifshitz <lifshitz@compulab.co.il>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
The capacity and lba for an MMC device with part_num 0 reflects the
whole device. When mmc_switch_part() successfully switches to a
partition, the capacity is changed to that partition. As partition 0
does not physically exist, attempts to switch back to the whole device
will indicate an error, but the capacity setting for the whole device
must still be restored to match the partition.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Tested-by: Tom Rini <trini@ti.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
if we set manually this bit on the eMMC card using mmc_switch(...),
we also have to set it within our (before read) internal structure
'ext_csd'.
Otherwise following checks on this will fail.
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
This patch add MTDIDS and MTDPARTS defaults settings to sheevaplug
Signed-off-by: Gerald Kerma <drEagle@doukki.net>
Changes in v1:
- add MTDIDS and MTDPARTS default to sheevaplug
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
This patch move the environment offset in sheevaplug.
The size of the u-boot binary is become too big.
Fix saving environments was result of corrupting the u-boot.
Signed-off-by: Gerald Kerma <drEagle@doukki.net>
Changes in v2:
- patch description
Changes in v1:
- fix sheevaplug environment offset
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
Zeroing GD in board_init_f() is not needed any more. As its now done in
crt0.S. The patch that clears the GD in crt0.S is this one:
aae2aef9 [arm: Set up global data before board_init_f()] from Simon.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Tim Harvey <tharvey@gateworks.com>
i.MX6SX ROM implements unified table sections.
The HAB function table is at offset 0x100. Update
the HAB function pointers accordingly.
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
Update the ddr scripts for LPDDR2 and add two build configs for LPDDR2
arm2 board. Since the LPDDR2 arm2 board has different DDR size, use
CONFIG_DDR_MB in defconfig to replace the PHYS_SDRAM_SIZE.
Signed-off-by: Ye.Li <B37916@freescale.com>
This patch adds the i.MX6DL arm2 board support. The i.MX6DL ARM2
shared the same board with i.MX6Q ARM2 board since the i.MX6DL is
pin-pin compatible with i.MX6Q.
The patch also support the DDR 32-BIT mode option. Please define
CONFIG_DDR_32BIT in the board configure file to enable DDR 32-BIT
mode.But due to the board design, it's 64bit DDR buswidth physically,
so, if you CONFIG_DDR_32BIT, the DDR memory size will be half of it.
Signed-off-by: Ye.Li <B37916@freescale.com>
Enable the CONFIG_CMD_FS_GENERIC on m53evk to avoid per-fs specific commands
and tweak the environment to cater for this new option.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Enable the CONFIG_CMD_FS_GENERIC on m28evk to avoid per-fs specific commands
and tweak the environment to cater for this new option.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Make sure the boot.scr exists on the card before loading it
from the card to avoid annoying message on the console.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Make sure the boot.scr exists on the card before loading it
from the card to avoid annoying message on the console.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
The mx6sl/mx6sx has 2 OTG and 1 host. So they have name
"USBO2H_USB_BASE_ADDR" in imx-regs.h. The driver hard codes
the USB base address name to "USBOH3", which causes the driver
failed to build for mx6sl/mx6sx.
This patch uniform the address name to "USB_BASE_ADDR" for all
mx6 series.
Signed-off-by: Ye.Li <B37916@freescale.com>
Checking the pre_periph_clk_sel and pre_periph2_clk of CCM CBCMR
register, if the PLL2 PFD0 or PLL2 PFD2 is used for the clock source,
do not reset this PFD to avoid system hang. Customers may set this
in DDR script or use BT_FREQ to select low freq boot.
Signed-off-by: Ye.Li <B37916@freescale.com>
1. Set the image load partition to the first FAT partition.
2. Set the kernel rootfs partition to the second partition.
Signed-off-by: Ye.Li <B37916@freescale.com>
To support loading FDT file for kernel, add the fdt address,
file and loading script to arm2 board default environment.
Signed-off-by: Ye.Li <B37916@freescale.com>
Add fine-tuning for the DRAM configuration according to the DRAM chip
datasheet. THis configuration applies to both Hynix HY5DU12622DTP and
Samsung K5H511538J-D43 .
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Enable the power to the USB port only when the USB port is really needed.
Do not enable the power unconditionally.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Instead of waiting for a fixed period of time and hoping for the best
that the DRAM will start, read back an EMI status register which tells
us exactly when the DRAM started.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
According to i.MX23 datasheet Table 32-17, we must wait for the supply
to settle before disabling the current limiter. Indeed, not waiting a
little here causes the system to crash at times.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Add board-specific callbacks for enabling/disabling port power
into the MXS EHCI controller driver. This is in-line with the
names of callbacks on other systems.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Some of the #defines in spi.h are not bracketed. To avoid future mistakes
add brackets. Also add an explanatory comment for SPI_CONN_DUAL_...
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
In preparation for changing the error handling in this code for driver
model, move it into its own function.
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Sandbox may as well support everything. This increases the amount of code
that is built/tested by sandbox, and also provides access to all the
supported SPI flash devices.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
At present sandbox has its own table of supported SPI flash chips. Now that
the SPI flash system is fully consolidated and has its own list, sandbox
should use that.
This enables us to expand the number of chips that sandbox supports.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
The ioread16_rep() and iowrite16_rep() implementations are U-Boot specific
and have been introduced with the Linux MTD v3.14 sync. While introducing
these functions, the length for the loop has been miscalculated. The ">> 1"
is already present in the caller. So lets remove it in the function.
Tested on omap3_ha.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Scott Wood <scottwood@freescale.com>
Acked-by: Heiko Schocher <hs@denx.de>
OMAP GPMC driver used with some NAND Flash devices
(e.g. Spansion S34ML08G1) causes that U-boot shows
hundreds of 'nand: bit-flip corrected' error messages.
Possible cause was discussed in the mailinglist thread:
http://lists.denx.de/pipermail/u-boot/2014-April/177508.html
The issue was partially fixed with the cc81a5291910d7a.git
however this has to be done to fix the SPL.
The original author of the code is Belisko Marek
<marek.belisko@gmail.com>
Signed-off-by: Rostislav Lisovy <lisovy@merica.cz>
With some versions of gcc (that we know of 4.6.3 and 4.8.2 are affected)
it is necessary to specify --bss-plt to get the final blrl in the
_GOT2_TABLE_. Without this the last symbol does not get it's address
relocated. For the P2041RDB board this ended up being
NetArpWaitTimerStart which caused the ARP packets to timeout
immediately.
Signed-off-by: Joakim Tjernlund <joakim.tjernlund@transmode.se>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joakim Tjernlund <joakim.tjernlund@transmode.se>
Acked-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
LS1021AQDS has a variant with DDR4 slot. This patch adds a new defconfig
for this variant to enable DDR4 support. RAW timing parameters are not
added for DDR4. The board timing parameters are only tuned for single-
rank 1600 and 1800MT/s with Micron DIMM 9ASF51272AZ-2G1A1 due to DIMM
availability.
Signed-off-by: York Sun <yorksun@freescale.com>
CC: Alison Wang <alison.wang@freescale.com>
When accumulated ECC is enabled, the DQ_MAP for ECC[4:7] needs to be set
to 0, i.e. 0->0, 1->1, etc., required by controller logic, even these pins
are not actually connected.
Also fix a bug when reading from DDR register to use proper accessor for
correct endianess.
Signed-off-by: York Sun <yorksun@freescale.com>
Spin table is at the very beginning of boot code. Each core has an individual
release address within the spin table, the ft_cpu_setup fn updates the
"cpu-release-addr" property of each cpu node with the corresponding release
address.
Also fix CPU_RELEASE_ADDR to point to secondary_boot_func.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
Secondary cores need to be released from holdoff by boot release
registers. With GPP bootrom, they can boot from main memory
directly. Individual spin table is used for each core. Spin table
and the boot page is reserved in device tree so OS won't overwrite.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
of_bus_default_count_cells can be used to get the #address-cells
and #size-cells defined by the current node's parent node. This
is required when using of_read_number to read from FDT nodes that
can be 32 or 64 bytes depending on values defined by the parent.
Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
CC: Scott Wood <scottwood@freescale.com>
This is being done so that it can be used outside 'fdt_support.c'. Making
life more convenient when reading device node properties that can be 32
or 64 bits long.
Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
Cc: Scott Wood <scottwood@freescale.com>
The driver was written using old DDR3 spec which only covers low speeds.
The value would be suboptimal for higher speeds. Fix both timing according
to latest DDR3 spec, remove tCKE as an config option.
Signed-off-by: York Sun <yorksun@freescale.com>
DP-DDR is used for DPAA, separated from main memory pool for general
use. It has 32-bit bus width and use a standard DDR4 DIMM (64-bit).
Signed-off-by: York Sun <yorksun@freescale.com>
U-boot has been initializing DDR for the main memory. The presumption
is the memory stays as a big continuous block, either linear or
interleaved. This change is to support putting some DDR controllers
to separated space without counting into main memory. The standalone
memory controller could use different number of DIMM slots.
Signed-off-by: York Sun <yorksun@freescale.com>
Add support of NOR and NAND flash for simulator target.
Here
IFC - CS0: NOR flash
IFC - CS1: NAND flash
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Freescale's flash control driver is using architecture specific timer API
i.e. usec2ticks
Replace usec2ticks with get_timer() (generic timer API)
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Pick the following commit from Linux kernel:
commit 66cb4ee0e52ca721f609fd5eec16187189ae5fda
Author: Joe Perches <joe@perches.com>
Date: Wed Sep 10 09:40:47 2014 +1000
checkpatch: remove unnecessary + after {8,8}
There's a useless "+" use that needs to be removed as perl 5.20 emits a
"Useless use of greediness modifier '+'" message each time it's hit.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@ti.com>
This commit moves:
CONFIG_OF_CONTROL
CONFIG_OF_SEPARATE
CONFIG_OF_EMBED
CONFIG_OF_HOSTFILE
Because these options are currently not supported for SPL,
the "Device Tree Control" menu does not appear in the SPL
configuration.
Note:
zynq-common.h should be adjusted so as not to change the
default value of CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
This tools is unnecessary since commit f6c8f38ec6
(tools/genboardscfg.py: improve performance more with Kconfiglib).
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
The mentioned binutils port got removed while the patch was
pending. As Ian pointed out there is another port providing
the binutils for arm now. Update the instructions accordingly.
Cc: ian@FreeBSD.org
Cc: Tom Rini <trini@ti.com>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
The libc headers on FreeBSD and likely related projects as well contain an
header file, cdefs.h which provides similiar functionality as linux/compiler.h.
It provides compiler independent defines like __weak __packed, to allow
compiling with multiple compilers which might have a different syntax for such
extension.
Since that header file is included in multiple standard headers, like stddef.h
and stdarg.h, multiple definitions of those defines will be present if both are
included. When compiling u-boot the compiler will warn about it hundreds of
times since e.g. common.h will include both files indirectly.
commit 7ea50d5284 "compiler_gcc: do not redefine
__gnu_attributes" prevented such redefinitions, but this was undone by commit
fb8ffd7cfc "compiler*.h: sync
include/linux/compiler*.h with Linux 3.16".
Add the checks back where necessary to prevent such warnings.
As the original patch this checkpatch warning is ignored:
"WARNING: Adding new packed members is to be done with care"
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Acked-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
[1] Move driver/core/, driver/input/ and drivers/input/ entries
from the top Makefile to drivers/Makefile
[2] Remove the conditional by CONFIG_DM in drivers/core/Makefile
because the whole drivers/core directory is already selected
by CONFIG_DM in the upper level
[3] Likewise for CONFIG_DM_DEMO in drivers/demo/Makefile
[4] Simplify common/Makefile - both CONFIG_DDR_SPD and
CONFIG_SPD_EEPROM are boolean macros so they can directly
select objects
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Marek Vasut <marex@denx.de>
Since clang has a different definition for uninitialized_var
it will complain that it is redefined in include/compiler.h.
Since these are already defined in linux/compiler.h just remove
this instance.
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
The arg_off() and arg_off_size() update the 'current NAND
device' variable (dev). This is then used when assigning the
(nand_info_t*)nand value. Place the assignment after the
arg_off(_size) calls to prevent using incorrect (nand_info_t*)
nand value.
Signed-off-by: Rostislav Lisovy <lisovy@merica.cz>
Since CONFIG_CMD_IMPORTENV is defined in config_cmd_defaults.h,
it should be enabled for all the boards except bf506f-ezkit
that undefs it explicitely.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Since CONFIG_CMD_GO is defined in config_cmd_defaults.h
(and no board undefs it its own header), it can be moved to
Kconfig with the default value "y".
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Since CONFIG_CMD_EXPORTENV is defined in config_cmd_defaults.h,
it should be enabled for all the boards except bf506f-ezkit
that undefs it explicitely.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Since CONFIG_CMD_CRC32 is defined in config_cmd_defaults.h,
it is enabled for all the boards except the ones undefining it
explicitly:
kwb
tseries_mmc
tseries_nand
tseries_spi
vct_platinum_onenand_small
vct_platinum_small
vct_platinumavc_onenand_small
vct_platinumavc_small
vct_premium_onenand_small
vct_premium_small
The default value of this config option should be "y" and
"# CONFIG_CMD_CRC32 is not set" should be added for those exceptions.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
CONFIG_CMD_BOOTM is defined in config_cmd_defaults.h
which is forcebly included from each board.
So, the default value of "config CMD_BOOTM" should be "y".
For some boards undefining it (bf506f-ezkit, controlcenterd_TRAILBLA,
controlcenterd_TRAILBLAZER_DEVELOP, controlcenterd_TRAILBLAZER),
"# CONFIG_CMD_BOOTM is not set" should be added to their defconfig.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
If this option is enabled, the objects under lib/ directory
are compiled with speed optimization, not size optimization.
(Currently, only used by some Blackfin boards.)
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Scsi disks need to be probed before we try to access them, otherwise all
accesses fail with: ** Bad device size - scsi 0 **.
Reported-by: Karsten Merker <merker@debian.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Karsten Merker <merker@debian.org>
Since commit ddaf5c8f30
(patman: RunPipe() should not pipe stdout/stderr unless asked),
Patman spits lots of "Invalid MAINTAINERS address: '-'"
error messages for patches with global changes.
It takes too long for Patman to process them.
Anyway, "M: -" does not carry any important information.
Rather, it is just like a place holder in case of assigning
a new board maintainer. Let's comment out.
This commit can be reproduced by the following command:
find . -name MAINTAINERS | xargs sed -i -e '/^M:[[:blank:]]*-$/s/^/#/'
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
The "S: Orphan" in MAINTAINERS means that the maintainer in the
"M:" field is unreachable (i.e. the email address is not working).
(Refer to the definition of "Orphan" adopted in U-Boot
in the log of commit 31f1b654b2,
"boards.cfg: move boards with invalid emails to Orphan")
For patch files adding global changes, scripts/get_maintainer.pl
adds bunch of such invalid email addresses, which results in
tons of annoying bounce emails.
This commit can be reproduced by the following command:
find . -name MAINTAINERS | xargs sed -i -e '
/^M:[[:blank:]]/ {
N
/S:[[:blank:]]Orphan/s/^/#/
}
'
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
We are still keeping invalid email addressed in MAINTAINERS
because they carry information.
The problem is that scripts/get_maintainer.pl adds emails in the
"M:" field including invalid ones.
We want to comment out invalid email addresses in MAINTAINERS
to prevent scripts/get_maintainer.pl from picking them up.
On the other hand, we want to collect them for boards.cfg
to know the last known maintainer of each board.
This commit adjusts tools/genboardscfg.py to parse also
the commented "M:" fields, which is useful for the next commit.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
These cause U-Boot to print a list of available commands. It doesn't break
the test, but it is best to remove them from the output.
Signed-off-by: Simon Glass <sjg@chromium.org>
This is not supported properly on sandbox, and interferes with running
tests, since when a test script is piped in, some commands will call
ctrlc() which will drop characters from the test script.
Signed-off-by: Simon Glass <sjg@chromium.org>
This was lost sometime in the Kbuild conversion. Add it back.
Check that the trace test now passes:
$ ./test/trace/test-trace.sh
Simple trace test / sanity check using sandbox
/tmp/filemHKPGw
Build sandbox
O=sandbox FTRACE=1
GEN /home/sjg/c/src/third_party/u-boot/files/sandbox/Makefile
Configuring for sandbox board...
Check results
Test passed
Signed-off-by: Simon Glass <sjg@chromium.org>
Each CPU of PowerPC has its default linker script under the CPU
directory, except mpc8xx.
Every mpc8xx board has its own linker script under the board
directory, resulting in lots of duplication of linker scripts.
I notice eight mpc8xx boards have the same linker script.
We can decrease the number of linker scripts by putting a single
default linker script, arch/powerpc/cpu/mpc8xx/u-boot.lds.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
Acked-by: Stefan Roese <sr@denx.de>
Fix the following build error in case CONFIG_E1000_NO_NVM is enabled:
CC drivers/net/e1000.o
drivers/net/e1000.c: In function ‘e1000_initialize’:
drivers/net/e1000.c:5365:5: error: ‘struct e1000_hw’ has no
member named ‘eeprom_semaphore_present’
make[1]: *** [drivers/net/e1000.o] Error 1
make: *** [drivers/net] Error 2
Acked-by: Marek Vasut <marex@denx.de>
When building the U-Boot tools for non-ELF platforms (such as Blackfin
FLAT), since commit 79fc0c5f49
("tools/env: cross-compile fw_printenv without setting HOSTCC"), the
build fails because it tries to strip a FLAT binary, which does not
make sense.
This commit solves this by changing the stripping logic in
tools/env/Makefile to be similar to the one in tools/Makefile. This
logic continues to apply strip to the final binary, but does not abort
the build if it fails, and does the stripping in place on the final
binary. This allows the logic to work fine if stripping doesn't work,
as it leaves the final binary untouched.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Sonic Zhang <sonic.zhang@analog.com>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Sonic Zhang <sonic.zhang@analog.com>
- add capability to "fastboot flash" with sparse format images
Signed-off-by: Steve Rae <srae@broadcom.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
- update static function
- additional debugging statements
- update "fastboot command" information
- add missing include file
- update spelling
Signed-off-by: Steve Rae <srae@broadcom.com>
T1042QDS (T1042 is T1040 Personality without L2 switch) supports following
sgmii interfaces with serdes protocol 0xA7
-SGMII-MAC3 on Lane B - slot 7
-SGMII-MAC5 on Lane H - slot 7
-SGMII2.5G-MAC1 on Lane C - slot 6
-SGMII2.5G-MAC2 on Lane D - slot 5
Add support of above sgmii interfaces
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
DDR-ODT require cfg_dram_type switch set properly as per DDR type.
T1040RDB, T1042RDB boards have DDR3L type DDR, so cfg_dram_type
should be set to OFF for DDR3L
Update t104xrdb/README for switch setting
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
"0x00" is a valid serdes protocol for QorIQ parts, and can not be
used to test whether the serdes is enabled or disabled.
Signed-off-by: Ebony Zhu <b45385@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
One of the I2C EEPROM is used to store/save and edit mac
addresses of ports.
this patch add required CONFIG to support the same
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
CPC1 is not being enabled by default as powerpc is supposed to
use only CPC2. Though by editing hwconfig en_cpc option,
CPC1 can also be enabled.
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Fix following issues in USB device-tree fixup:
- returns when either dr_mode or phy_type not defined.
This was terminating fix-up when only either property
was defined in hwconfig string
- updates dr_mode_type or dr_phy_type with junk value when
their index is -1. Now these are updated only when their
respective index is pointing to relevant types
in modes[] and phys[] array
- dr_mode_type and dr_phy_type were not NULL for
each controller
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
T1042RDB is a Freescale reference board that hosts the T1042 SoC
(and variants). The board is similar to T1040RDB, T1042 is a reduced
personality of T1040 SoC without Integrated 8-port Gigabit(L2 Switch).
T1042RDB is configured with serdes protocol 0x86 which can support
following interfaces
- 2 RGMII's on DTSEC4, DTSEC5
- 1 SGMII on DTSEC3
DTSEC1, DTSEC2 are not connected on board.
This Patch
- add T1042RDB support
- updates README file for T1042RDB details and update commands for switching
to alternate banks from vBank0 to vBank4 and vice versa
This patch also does minor clean ups for fdt defines for T1042RDB and
T1042RDB_PI board
Signed-off-by: Vijay Rai <vijay.rai@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This patch adds support of rcw for T1042RDB, it makes following changes :
- Adds t1042_rcw.cfg file for serdes protocol 0x86 for T1042RDB
- Renames t1042_pi_rcw.cfg file from t1042_rcw.cfg and also updates
comments for valid serdes protocol which is 0x06
- Also updates CONFIG_SYS_FSL_PBL_RCW for T1042RDB
Signed-off-by: Vijay Rai <vijay.rai@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
LS2085a has 2 regions in system memory map. Region1 is default map from
where system boots. Once u-boot is moved to DDR, IFC is re-mapped to
Region2.
So, update gd->env_addr to reflect correct address.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Enable the Extend address to support SPI flash more than 16MB.
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
This patch introduces the clrsetbits_le32() accessor functions in the
kirkwood SPI driver. Note that it also includes a fix:
- writel(~KWSPI_CSN_ACT | KWSPI_SMEMRDY, &spireg->ctrl);
+ writel(KWSPI_SMEMRDY, &spireg->ctrl);
Here the bit KWSPI_CSN_ACT (0x1) should have been cleared. Instead
0xfffffffe is written into this control register. This is the main
reason to use the clrsetbits() functions now. As they make clearing
bits much less error prone.
Additionally KWSPI_IRQUNMASK is not used in spi_cs_activate() and
spi_cs_deactivate() any more. Its the wrong macro but has the same
value as the correct one (KWSPI_CSN_ACT).
This is in preparation for use of this driver on the Marvell Armada XP
platform as well.
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
Tested-by: Luka Perkov <luka@openwrt.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Add ID for this Numonix / STMicro chip.
Tested on Marvell DB-78460-BP board.
Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Luka Perkov <luka@openwrt.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Currently, CONFIG_SPL_SPI_* #defines are used for controlling SPI boot in
SPL. These #defines do not allow the user to select SPI mode for the SPI flash
(there's no CONFIG_SPL_SPI_MODE, so the SPI mode is hardcoded in
spi_spl_load.c), and duplicate information already provided by
CONFIG_SF_DEFAULT_* #defines.
Kill CONFIG_SPL_SPI_*, and use CONFIG_SF_DEFAULT_* instead.
Cc: Tom Rini <trini@ti.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Vitaly Andrianov <vitalya@ti.com>
Cc: Lars Poeschel <poeschel@lemonage.de>
Cc: Bo Shen <voice.shen@atmel.com>
Cc: Hannes Petermaier <hannes.petermaier@br-automation.com>
Cc: Michal Simek <monstr@monstr.eu>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
MXC SPI driver has a feature whereas a GPIO line can be used to force CS high
across multiple transactions. This is set up by embedding the GPIO information
in the CS value:
cs = (cs | gpio << 8)
This merge of cs and gpio data into one value breaks the sf probe command:
if the use of gpio is required, invoking "sf probe <cs>" will not work, because
the CS argument doesn't have the GPIO information in it. Instead, the user must
use "sf probe <cs | gpio << 8>". For example, if bank 2 gpio 30 is used to force
cs high on cs 0, bus 0, then instead of typing "sf probe 0" the user now must
type "sf probe 15872".
This is inconsistent with the description of the sf probe command, and forces
the user to be aware of implementaiton details.
Fix this by introducing a new board function: board_spi_cs_gpio(), which will
accept a naked CS value, and provide the driver with the relevant GPIO, if one
is necessary.
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Eric Benard <eric@eukrea.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Marek Vasut <marex@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Since dev->req_seq value is initialized from "reg" property of fdt node,
there is posibility, that address value contained in fdt is greater than
INT_MAX, and then value in dev->req_seq is negative which led to probe()
fail.
This patch fix this problem by ensuring that req_seq is positive, unless
it's one of errno codes.
Signed-off-by: Robert Baldyga <r.baldyga@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
The sequence number support in driver model requires device tree control.
It should be skipped if CONFIG_OF_CONTROL is not defined, and should not
require functions from fdtdec.
Signed-off-by: Simon Glass <sjg@chromium.org>
The list is supposed to be terminated with a NULL name, but is not. If a
board probes a chip which does not appear in the table, U-Boot will crash
(at least on sandbox).
Signed-off-by: Simon Glass <sjg@chromium.org>
When CONFIG_SECURE_BOOT is enabled, the signed images
like kernel and dtb can be authenticated using iMX6 CAAM.
The added command hab_auth_img can be used for HAB
authentication of images. The command takes the image
DDR location, IVT (Image Vector Table) offset inside
image as parameters. Detailed info about signing images
can be found in Freescale AppNote AN4581.
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Let's enable CONFIG_SYS_GENERIC_BOARD in order to get rid of warnings related
to generic board support is not in place.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Provide cgtqmx6eval board its own variant of ddr
setup config file. Move board/freescale/imx/ddr/
mx6q_4x_mt41j128.cfg to board/freescale/mx6sabresd/
as this is was designed for the mx6sabresd board.
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Let's enable CONFIG_SYS_GENERIC_BOARD in order to get rid of warnings related
to generic board not being supported.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
The get_maintainers script is a useful default, but sometimes is copies
too many people, or takes a long time to run.
Add an option to disable it and update the README.
Signed-off-by: Simon Glass <sjg@chromium.org>
This check should now be done whatever mode buildman is running in, since
we may be displaying information while building.
Signed-off-by: Simon Glass <sjg@chromium.org>
- Use _defconfig instead of _config, but still _config is working.
- Corrected README.sandbox path in ./README
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Disable subpage write when using PMECC to prevent buggy partial page write.
This fix has been taken from linux sources (see commit
90445ff6241e2a13445310803e2efa606c61f276)
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
If the SoC has pcr, we use pcr (peripheral control register)
to enable or disable clock.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
If the SoC has pcr, we use pcr (peripheral control register)
to enable or disable clock.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
When use pcr (peripheral control register), then we won't need
to care about the peripheral ID.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
We defined the macro pmecc_readl(b)/pmecc_writel for pmecc register access.
But in the driver we also use the readl(b)/writel.
To keep consistent, this patch make all use pmecc_readl(b)/pmecc_writel.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
This patch uses generic 'load' command instead of 'fatload' for 'loadbootscript' and 'loadbootenv' as already done for 'loadimage' and 'loaduimage' for OMAP4 boards.
This allows to use EXT partition instead of FAT, while keeping FAT compatibility.
Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr>
Cc: Tom Rini <trini@ti.com>
This patch implements a workaround to fix DDR3 memory issue.
The code for workaround detects PGSR0 errors and then preps for
and executes a software-controlled hard reset.In board_early_init,
where logic has been added to identify whether or not the previous
reset was a PORz. PLL initialization is skipped in the case of a
software-controlled hard reset.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Keegan Garcia <kgarcia@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
commit d6d07a9b... arm: vf610: add NAND support for vf610twr
generates the following warnings:
WARNING: no status info for 'vf610twr_nand'
WARNING: no maintainers for 'vf610twr_nand'WARNING: no status info for
'vf610twr_nand'
This is due to the fact that vf610twr_nand_defconfig has no Maintainer.
This patch proposed Alison as Maintainer and fix it.
Signed-off-by: Stefano Babic <sbabic@denx.de>
Acked-by: Alison Wang <b18965@freescale.com>
CC: Stefan Agner <stefan@agner.ch>
At the high level, the problem is that we set gd multiple times (and
still do, even after the commit we're reverting). We set important
parts of gd to the copy which is not above stack but rather in the data
section. For the release, we're going to revert this change and for the
next release we shall correct things to only, really, set gd once to an
appropriate location and ensure that comments about it are correct too.
This reverts commit f0c3a6c4ad.
Acked-by: Albert Aribaud <albert.u.boot@aribaud.net>
Signed-off-by: Tom Rini <trini@ti.com>
We do not have to distinguish CONFIG_TARGET_VEXPRESS_AEMV8A_SEMI
from CONFIG_TARGET_VEXPRESS_AEMV8A. Rename the former to the latter.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Steve Rae <srae@broadcom.com>
Cc: David Feng <fenghua@phytium.com.cn>
When a DNS query is sent out, the ethernet packet can get directed to
the MAC address of a server that was communicated to before. This is
wrong when the previously stored MAC address corresponds to a different
server's IP address, i.e. when the IP address of the previous and the
current communication are different.
The error can get reproduced by running a sequence of e.g. a TFTP
download and a DNS query, where the TFTP and DNS servers reside on
individual machines.
The fix is to clear the server's MAC address that might be left from a
previous operation, and to fetch the peer's MAC address in a new ARP
lookup, before the DNS query is sent. This is the approach taken in
other network services, like 8e52533d10 ("net: tftpsrv: Get correct
client MAC address").
Reported-by: Dirk Zimoch <dirk.zimoch@psi.ch>
Signed-off-by: Gerhard Sittig <gsi@denx.de>
For the SPL configuration, "make <dir>/<target>" is used.
Here,
<dir> is either "spl" or "tpl"
<target> is one of "config", "menuconfig", "xconfig", etc.
This commit adds two checks:
[1] If <dir> is given an unsupported subimage, the configuration
should error out like this:
$ make qpl/menuconfig
***
*** "make qpl/menuconfig" is not supported.
***
[2] Make sure that "CONFIG_SPL" is enabled in the ".config" before
running "make spl/menuconfig. Otherwise, the SPL image
is not built at all. Having "spl/.config" makes no sense.
In such a case, the configuration should exit with a message:
$ make spl/menuconfig
***
*** Create ".config" with "CONFIG_SPL" enabled
*** before "make spl/menuconfig".
***
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Suggested-by: Simon Glass <sjg@chromium.org>
After mtd was synced with Linux 3.14
(ff94bc40af)
the number of parameters for write_page function of nand_chip was
changed. The additional two var were needed for subpage write.
As keystone has no supbage write they are not needed. So correct
only function definition by upgrading it's parameter list.
That helps to get ritd of compilation warning.
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
gd->fdt_blob is used for FDT control of U-Boot.
If CONFIG_OF_CONTROL is not defined, it is useless.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Since 3ff291f371
(kconfig: convert Kconfig helper script into a shell script),
"make config" is not working because of a missing '$' before '(Q)'.
Besides, "make config" should be invoked via scripts/multiconfig.sh
to avoid a warning message:
Kconfig:11:warning: environment variable KCONFIG_OBJDIR undefined
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
This commit is a backport from Linux Kernel,
commit 9d5db8949f1ecf4019785b04d8986835d3c0e99e,
written by me.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Since 3ff291f371
(kconfig: convert Kconfig helper script into a shell script),
"make savedefconfig" of TPL boards has not been working.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.o.rg
Acked-by: Simon Glass <sjg@chromium.org>
When a non-existing defconfig is specified,
display an easy-to-understand message
(fake the error message on Linux Kernel):
$ make foo_defconfig
***
*** Can't find default configuration "confis/foo_defconfig"!
***
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Commit 3ff291f371
(kconfig: convert Kconfig helper script into a shell script)
introduced another regression.
Shell usually handles whitespaces as separators,
so "make saveconfig" outputs
# CONFIG_FOO is not set
into:
#
CONFIG_FOO
is
not
set
Whitespaces should not be treated as separators here.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
This was breaking the build for some boards:
MPC8536DS MPC8536DS_36BIT MPC8536DS_SDCARD MPC8536DS_SPIFLASH qemu-ppce500
Include only these features for some PPC boards if the configuration for MultiProcessor
is enabled.
Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
Cc: Tom Rini <trini@ti.com>
Cc: York Sun <yorksun@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
Commit 3ff291f371
(kconfig: convert Kconfig helper script into a shell script)
introduced a minor regression.
make alldefconfig; make savedefconfig
should create an empty 'defconfig'.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
Now GCC_VERSION is defined in include/linux/compiler-gcc.h
(with a little different definition).
Use it and delete the one in examples/standlone/stub.c.
This should work on Clang too because __GNUC__, __GNUC_MINOR__,
__GNUC_PATCHLEVEL__ are also defined on Clang.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Jeroen Hofstee <jeroen@myspectrum.nl>
Copy them from Linux v3.16 tag.
My main motivation of this commit is to add compiler-clang.h.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Jeroen Hofstee <jeroen@myspectrum.nl>
There are two ways to run into handle_exception, run command 'kgdb' and
encounter a breakpoint which triggers exception handling.
The origin source code only saves regs when first run command 'kgdb'.
Take the following for example, When run 'kgdb', regs is saved to entry_regs.
When run 'bootz', regs is not saved. However, if we set a breakpoint, then
continue. When breakpoint is reached, run `quit`, and Now return to the
instruction which follows kgdb, but not bootz.This may cause errors. So,
save regs for each handle_exception call to return to the correct place.
Example:
Target | Host
=>kgdb | (gdb)b bootz
| (gdb)c
=>bootz |
| (gdb)Here stop because of breakpoint
| (gdb)q
Signed-off-by: Peng Fan <van.freenix@gmail.com>
The idea of using Kconfiglib was given by Tom Rini.
It allows us to scan lots of defconfigs very quickly.
This commit also uses multiprocessing for further acceleration.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Suggested-by: Tom Rini <trini@ti.com>
Acked-by: Simon Glass <sjg@chromium.org>
U-Boot has imported various source files from other projects,
mostly Linux.
Something like
#ifdef __UBOOT__
[ modification for U-Boot ]
#else
[ original code ]
#endif
is an often used strategy for clarification of adjusted parts,
that is, easier re-sync in future.
Instead of defining __UBOOT__ in each source file,
passing it from the top Makefile would be easier.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
When network protocol errors occur (such as a file not being found on a
TFTP server), the processing done by the NetReceive() function will end
up calling the driver's .halt() implementation. However, after that the
device no longer has access to the memory buffers and will cause errors
such as this in the rtl_recv() function when trying to hand descriptors
back to the device:
pci_hose_bus_to_phys: invalid physical address
This can be fixed by deferring processing of network packets until the
descriptors have been handed back. That way rtl_halt() tearing down
network buffers is not going to prevent access to the buffers.
Reported-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
i2c_pad_info1 is only used locally, so it can be made static.
Fix the following sparse warning:
board/freescale/mx6sxsabresd/mx6sxsabresd.c:160:22: warning: symbol 'i2c_pad_info1' was not declared. Should it be static?
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Define CONFIG_SYS_FSL_ESDHC_ADDR using USDHC4_BASE_ADDR.
USDHC3 and USDHC4 are both initialized in board_mmc_init. There is
no restriction on USDHC3 addr or USDHC4 addr should be assigned to
CONFIG_SYS_FSL_ESDHC_ADDR. So, just choose USDHC4_BASE_ADDR to avoid
errors when fsl_esdhc_mmc_init is invoked.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Define CONFIG_SYS_FSL_ESDHC_ADDR using USDHC4_BASE_ADDR which is used
in board_mmc_init.
If board_mmc_init failed, cpu_mmc_init->fsl_esdhc_mmc_init will use
CONFIG_SYS_FSL_ESDHC_ADDR to initialize sdhc. So set this macro to
correct value.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
This adds NAND support for the Vybrid tower system (TWR-VF65GS10)
provided by the vf610_nfc driver. Full 16-Bit bus width is
supported. Also an aditional config vf610twr_nand is introduced
which gets the environment from NAND. However, booting U-Boot from
NAND is not yet possible due to missing boot configuration block
(BCB).
Signed-off-by: Stefan Agner <stefan@agner.ch>
This adds initial support for Freescale NFC (NAND Flash Controller)
found in ARM Vybrid SoC's, Power Architecture MPC5125 and others.
The driver is called vf610_nfc since this is the first supported
and tested hardware platform supported by the driver.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Bill Pringlemeir <bpringlemeir@nbsps.com>
This patch moves mx35 to the common timer functions added in commit
8dfafdd - Introduce common timer functions <Rob Herring>
The (removed) mx35 timer code (specifically __udelay()) could deadlock at
the 32-bit boundary of get_ticks(). get_ticks() returned a 32-bit value
cast up to a 64-bit value. If get_ticks() + tmo in __udelay() crossed
the 32-bit boundary, the while condition became unconditionally true and
locks the processor. Rather than patch the specific mx35 issues, simply
move everything over to the common code.
Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
This patch moves mx31 to the common timer functions added in commit
8dfafdd - Introduce common timer functions <Rob Herring>
The (removed) mx31 timer code (specifically __udelay()) could deadlock at
the 32-bit boundary of get_ticks(). get_ticks() returned a 32-bit value
cast up to a 64-bit value. If get_ticks() + tmo in __udelay() crossed
the 32-bit boundary, the while condition became unconditionally true and
locks the processor. Rather than patch the specific mx31 issues, simply
move everything over to the common code.
Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Helmut Raiger <helmut.raiger@hale.at>
Use size_t type for positive offsets instead of the loff_t type. The
later is defined as long long, which is larger than the pointer type
on OpenRISC architecture and therefore the following warning was
generated:
"warning: cast to pointer from integer of different size"
Signed-off-by: Vasili Galka <vvv444@gmail.com>
The parameters of size_t type shall be formatted using "%zu" and not
using "%d".
Precision argument for the "%.*s" parameters shall be of int type.
Signed-off-by: Vasili Galka <vvv444@gmail.com>
Commit 70fbc461 removed obsolete PCI5441 and PK1C20 boards.
This commit adds them to README.scrapyard and also fills
some commit IDs and dates for removed boards.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Thomas Chou <thomas@wytron.com.tw>
Now the types of CONFIG_SYS_{ARCH, CPU, SOC, VENDOR, BOARD, CONFIG_NAME}
are specified in arch/Kconfig.
We can delete the ones in arch and board Kconfig files.
This commit can be easily reproduced by the following command:
find . -name Kconfig -a ! -path ./arch/Kconfig | xargs sed -i -e '
/config[[:space:]]SYS_\(ARCH\|CPU\|SOC\|\VENDOR\|BOARD\|CONFIG_NAME\)/ {
N
s/\n[[:space:]]*string//
}
'
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
This commit adds the type definitions (+ help messages) of
CONFIG_SYS_{ARCH, CPU, SOC, VENDOR, BOARD, CONFIG_NAME} to arch/Kconfig,
which would save lots of type defs for taget boards.
(See also the next commit.)
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
The boards using CONFIG_SYS_DV_NOR_BOOT_CFG (i.e. calimain,
da850evm_direct_nor and enbw_cmc) had the _start symbol defined after
the CONFIG_SYS_DV_NOR_BOOT_CFG word rather than before it in
arch/arm/lib/vectors.S. Because of that, if by lack of luck
'gd->mon_len = (ulong)&__bss_end - (ulong)_start' (see setup_mon_len())
was a multiple of 4 kiB (see reserve_uboot()), then the last BSS word
overlapped the first word of the following reserved RAM area (or went
beyond the top of RAM without such an area) after relocation because
__image_copy_start did not match _start (see relocate_code()).
This was broken by commit 41623c9 'arm: move exception handling out of
start.S files', which defined _start twice (before and after the
CONFIG_SYS_DV_NOR_BOOT_CFG word), then by commit 0a26e1d 'arm: fix a
double-definition error of _start symbol', which kept the definition of
the _start symbol after the CONFIG_SYS_DV_NOR_BOOT_CFG word. This new
commit fixes this issue by restoring the original behavior, i.e. by
defining the _start symbol before the CONFIG_SYS_DV_NOR_BOOT_CFG word.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Manfred Rudigier <manfred.rudigier@omicron.at>
Cc: Christian Riesch <christian.riesch@omicron.at>
Cc: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
Cc: Heiko Schocher <hs@denx.de>
Some boards, like mx31pdk and tx25, require the beginning of the SPL
code to be position-independent. For these two boards, this is because
they use the i.MX external NAND boot, which starts by executing the
first NAND Flash page from the NFC page buffer. The SPL then needs to
copy itself to its actual link address in order to free the NFC page
buffer and use it to load the non-SPL image from Flash before running
it. This means that the SPL runtime address differs from its link
address between the reset and the initial copy performed by
board_init_f(), so this part of the SPL binary must be
position-independent.
This requirement was broken by commit 41623c9 'arm: move exception
handling out of start.S files', which used an absolute address to branch
to the reset routine. This new commit restores the original behavior,
which just performed a relative branch. This fixes the boot of mx31pdk
and tx25.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
Reported-by: Helmut Raiger <helmut.raiger@hale.at>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Magnus Lilja <lilja.magnus@gmail.com>
Cc: John Rigby <jcrigby@gmail.com>
Tested-by: Magnus Lilja <lilja.magnus@gmail.com>
In commit 021e79c853 ("tools: imximage: Fix the maximum DCD size for
mx53/mx6") we have fixed the maximum DCD size for mx53/mx53.
Do the same on the README document for consistency.
Reported-by: Jonas Karlsson <jonas.d.karlsson@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Use driver model for serial ports.
Since Tegra now uses driver model for serial, adjust the definition of
V_NS16550_CLK so that it is clear that this is only used for SPL.
Signed-off-by: Simon Glass <sjg@chromium.org>
Some Tegra device tree files do not include information about the serial
ports. Add this and also add information about the input clock speed.
The console alias needs to be set up to indicate which port is used for
the console.
Also add a binding file since this is missing.
Series-changes; 5
- Add full serial port nodes from Linux tree (commit fc9d4dbe)
- Use /chosen/stdout-path instead of /aliases/console to specify the console
Signed-off-by: Simon Glass <sjg@chromium.org>
Add driver model support so that ns16550 can support operation both with
and without driver model.
The driver needs a clock frequency so cannot stand alone unfortunately. The
clock frequency must be provided by a separate driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
The same sequence is used in several places, so move it into a function.
Note that UART_LCR_BKSE is an alias for UART_LCR_DLAB.
Signed-off-by: Simon Glass <sjg@chromium.org>
If the sandbox device tree is provided to U-Boot (with the -d flag) then it
will use the device tree version in preference to the built-in device. The
only difference is the colour.
Signed-off-by: Simon Glass <sjg@chromium.org>
The current sandbox serial driver is a pretty trivial example and does not
have the featues that might be needed for other board serial drivers. To
help provide a better example, add a text colour property to the device
tree for sandbox. This uses platform data, a device tree node, driver
private data and a remove() method.
Signed-off-by: Simon Glass <sjg@chromium.org>
Adjust the sandbox serial driver to use the new driver model uclass. The
driver works much as before, but within the new framework.
Signed-off-by: Simon Glass <sjg@chromium.org>
Serial devices support simple byte input/output and a few operations to find
out whether data is available. Add a basic uclass for serial devices to be
used by drivers that are converted to driver model.
Signed-off-by: Simon Glass <sjg@chromium.org>
Within /chosen we may have a node which points to another node, similar
to how /aliases works. Add a helper function to do this lookup.
Signed-off-by: Simon Glass <sjg@chromium.org>
The stdio_dev structure has a private pointer for its creator, but it is
not set up by the serial system. Set it to point to the serial device so
that it can be found by code called by stdio.
Signed-off-by: Simon Glass <sjg@chromium.org>
This is an implementation of GPIOs for Tegra that uses driver model. It has
been tested on trimslice and also using the new iotrace feature.
The implementation uses a top-level GPIO device (which has no actual GPIOS).
Under this all the banks are created as separate GPIO devices.
The GPIOs are named as per the Tegra datasheet/header files: A0..A7, B0..B7,
..., Z0..Z7, AA0..AA7, etc.
Since driver model is not yet available before relocation, or in SPL, a
special function is provided for seaboard's SPL code.
Signed-off-by: Simon Glass <sjg@chromium.org>
For some boards board_init() will change GPIOs, so we need to have driver
model available before then. Adjust the board init to arrange this, but
enable it for driver model only, just to be safe.
This does create additional #ifdef logic, but it is safer than trying to
make a pervasive change which may cause some boards to break.
Signed-off-by: Simon Glass <sjg@chromium.org>
Since driver model registers itself with the stdio subsystem, and we
want to avoid delayed registration and other complexity associated with
the current serial console, move the stdio subsystem init earlier when
driver model is used for serial.
This simplifies the implementation. Should there be any problems with
this approach they can be dealt with as boards are converted over to
use driver model for serial.
Signed-off-by: Simon Glass <sjg@chromium.org>
In order to support GPIO access in board_early_init_f() we must set up
driver model before this function is called. In any case, earlier is
better since driver model is (or will become) a key function for most
init.
Signed-off-by: Simon Glass <sjg@chromium.org>
The microblaze-generic board fails to build at least
with the kernel.org crosstool:
https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.9.0/
x86_64-gcc-4.9.0-nolibc_microblaze-linux.tar.xz
$ make CROSS_COMPILE=microblaze-linux- microblaze-generic_defconfig all
[ snip ]
CC disk/part.o
CC disk/part_dos.o
LD disk/built-in.o
CC drivers/block/systemace.o
{standard input}: Assembler messages:
{standard input}:2495: Error: operation combines symbols in different segments
{standard input}:2496: Error: operation combines symbols in different segments
{standard input}:2499: Error: operation combines symbols in different segments
{standard input}:2500: Error: operation combines symbols in different segments
{standard input}:2505: Error: operation combines symbols in different segments
{standard input}:2506: Error: operation combines symbols in different segments
{standard input}:2515: Error: operation combines symbols in different segments
{standard input}:2516: Error: operation combines symbols in different segments
{standard input}:2519: Error: operation combines symbols in different segments
{standard input}:2520: Error: operation combines symbols in different segments
{standard input}:2529: Error: operation combines symbols in different segments
{standard input}:2530: Error: operation combines symbols in different segments
{standard input}:2533: Error: operation combines symbols in different segments
{standard input}:2534: Error: operation combines symbols in different segments
{standard input}:2539: Error: operation combines symbols in different segments
{standard input}:2540: Error: operation combines symbols in different segments
{standard input}:2549: Error: operation combines symbols in different segments
{standard input}:2550: Error: operation combines symbols in different segments
make[3]: *** [drivers/block/systemace.o] Error 1
make[2]: *** [drivers/block] Error 2
make[1]: *** [drivers] Error 2
make: *** [__build_one_by_one] Error 2
It looks like the cause of this error message is the "#ident" directive.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
try run => dry run
no nothing => do nothing
"..." => '...'
The last one is for consistency with the other option helps.
Change-Id: I1d69047d1fae6ef095a18f69f44ee13c448db9b7
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
When creating build directories also create parents as necessary. This
fixes a failure when building a hierarchical branch (i.e. foo/bar).
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Rini <trini@ti.com>
For an occasional user of patman some failures are not obvious: for
instance when checkpatch reports warnings, the dry run still reports
that the email would be sent. If it is not dry run, the warnings are
shown on the screen, but it is not clear that the email was not sent.
Add some code to report failure to send email explicitly.
Tested by running the script on a patch with style violations,
observed error messages in the script output.
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Tags like Series-version are normally expected to appear once, and with a
unique value. But buildman doesn't actually look at these tags. So ignore
conflicts.
This allows bulidman to build a branch containing multiple patman series.
Reported-by: Steve Rae <srae@broadcom.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
At present buildman naively uses the branch name as part of its directory
path, which causes problems if the name has an embedded '/'.
Replace these with '_' to fix the problem.
Reported-by: Steve Rae <srae@broadcom.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Now that buildman supports removing the build directory prefix from output,
add a test for it. Also ensure that output directories are removed when the
test completes.
Signed-off-by: Simon Glass <sjg@chromium.org>
This adds coverage of core features of the builder, including the
command-line options which affect building.
Signed-off-by: Simon Glass <sjg@chromium.org>
For reasons that are not well-understood, GetMetaDataForList() can end up
adding to an existing series even when it appears that it should be
starting a new one.
Change from using a default constructor parameter to an explicit one, to
work around this problem.
Signed-off-by: Simon Glass <sjg@chromium.org>
For testing it is useful to clean the output directory before running a
test. This avoids a test interfering with the results of a subsequent
test by leaving data around.
Add this feature as an optional parameter to the control logic.
Signed-off-by: Simon Glass <sjg@chromium.org>
When a build is to be performed, buildman checks to see if it has already
been done. In most cases it will not bother trying again. However, it was
not reading the return code from the 'done' file, so if the result was a
failure, it would not be counted. This depresses the 'failure' count stats
that buildman prints in this case.
Fix this bug by always reading the return code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Rather than reading boards.cfg, which may take time to generate and is not
necessarily suitable for running tests, create our own list of boards.
Signed-off-by: Simon Glass <sjg@chromium.org>
These files may not exist in the environment, or may not be suitable for
testing. Provide our own config file and our own toolchains when running
tests.
Signed-off-by: Simon Glass <sjg@chromium.org>
Move the bsettings code back to the main buildman.py file, so we can do
something different when testing.
Signed-off-by: Simon Glass <sjg@chromium.org>
Buildman currently lacks testing in many areas, including its use of git,
make and many command-line flags.
Add a functional test which covers some of these areas. So far it does
a fake 'build' of all boards for the current source tree.
This version reads the real ~/.buildman and boards.cfg files. Future work
will improve this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a test point for the command module. This allows tests to emulate
the execution of commands. This provides more control (since we can make
the fake 'commands' do whatever we like), makes it faster to write tests
since we don't need to set up as much environment, and speeds up test
execution.
Signed-off-by: Simon Glass <sjg@chromium.org>
We want to be able to issue parser commands from within buildman for test
purposes. Move the parser code into its own file so we don't end up needing
the buildman and test modules to reference each other.
Signed-off-by: Simon Glass <sjg@chromium.org>
RunPipe() currently pipes the output of stdout and stderr to a pty, but
this is not the intended behaviour. Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Adjust the basic test so that it checks all console output. This will help
to ensure that the builder is behaving correctly with printing summary
information.
Signed-off-by: Simon Glass <sjg@chromium.org>
To allow us to verify the builder's console output, send it through a
function which can collect it when running in test mode.
Signed-off-by: Simon Glass <sjg@chromium.org>
When running unit tests we don't want output to go to the terminal.
Provide a way of collecting it so that it can be examined by test code
later.
Signed-off-by: Simon Glass <sjg@chromium.org>
Commit fa9c021632 ("mx6: add example DTB for mx6qsabreauto") introduced
'imx6q-sabreauto.dts' but it adds no real value as the dts file only contains
the 'model' and 'compatible' strings.
After this commit the final binary is also changed from 'u-boot.imx' to
'u-boot-dtb.imx', which may confuse users.
So revert it until a more complete and useful device tree could be provided.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
nitrogen6x.h file defines CONFIG_CMD_FS_GENERIC, so we are able to use generic
'load' command instead of 'fatload'. It allows to use ext filesystem and keep
compatibilty with fat filesystem.
Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr>
Cc: Stefano Babic <sbabic@denx.de>
Acked-By: Eric Nelson <eric.nelson@boundarydevices.com>
Currently mx6dlsabresd shares the same DCD settings with the nitrogen board.
Provide a DCD configuration file specific to mx6dlsabresd with the settings
recommended by the Freescale hardware team.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
UART does not use the UART FIFO, but we should also not rely that
the UART FIFO is diabled by default. For instance, when loading
U-Boot using the boot ROMs serial downloader protocol over UART,
FIFO is enabled at U-Boot start time.
This patch disables the RX and TX FIFO, sets back their thresholds
and flushes them.
Signed-off-by: Stefan Agner <stefan@agner.ch>
The status register 1 (S1) is not writeable, hence we should not
write it. In order to clear the RDRF flag we only need to read
the data register.
Also, when stressing U-Boot a lot with serial input, an overflow can
occur which asserts the S1_OR flag (while not asserting the S1_RDRF
flag). To clear this flag we again just need to read the data
register, hence add this flag to the abort conditions for the while
loop.
Insert a compiler barrier to make sure reading the data register
gets executed after reading the status register.
Signed-off-by: Stefan Agner <stefan@agner.ch>
The load region size of EIM-NOR are defined to 0. For this case,
the parameter "imximage_init_loadsize" must be calculated.
The imximage tool implements the calculation in the "imximage_generate"
function, but the following function "imximage_set_header" resets the value
and not calculate. This bug cause some fields of IVT head are not
correct, for example the boot_data and DCD overlay the application area.
Signed-off-by: Ye.Li <B37916@freescale.com>
The Latency parameters of PL310 Tag RAM latency control register and
Data RAM Latency control register are set in L2 cache enable. And
setting these registers must have PL310 NOT enabled.
But when using Plugin mode boot, the PL310 is enabled by bootrom.
The patch disables the PL310 before applying this setting.
Signed-off-by: Ye.Li <Ye.Li@freescale.com>
The leds array within struct ventana has space for 3 elements, but the
setup_board_gpio() function tries to set up 4 GPIOs for LEDs. Recent
versions of GCC complain about that:
board/gateworks/gw_ventana/gw_ventana.c: In function 'setup_board_gpio':
board/gateworks/gw_ventana/gw_ventana.c:987:27: warning: iteration 3u invokes undefined behavior [-Waggressive-loop-optimizations]
if (gpio_cfg[board].leds[i])
^
board/gateworks/gw_ventana/gw_ventana.c:986:2: note: containing loop
for (i = 0; i < 4; i++) {
^
Fix this by making the upper bound of the loop match the array size.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Tim Harvey <tharvey@gateworks.com>
According to mx53 and mx6 reference manuals:
"The maximum size of the DCD limited to 1768 bytes."
As each DCD entry consists of 8 bytes, we have a total of 1768 / 8 = 221, and
excluding the first entry, which is the header leads to 220 as the maximum
number for DCD size.
Reported-by: Jonas Karlsson <jonas.d.karlsson@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Nitin Garg <nitin.garg@freescale.com>
Acked-by: Nitin Garg <nitin.garg@freescale.com>
Most Gateworks Ventana boards use a PLX PEX860x PCIe switch for PCIe expansion.
These boards use GPIO on the PLX device as PERST# for the downstream ports
thus we assert this when the PLX is enumerated.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Current way of calculation CS0_END field for MMDCx_MDASP register
is problematic because in most cases the user is forced to define
cs_density in an unnatural way: as value - 2, instead of value.
This breaks the abstraction provided by struct mx6_ddr_sysinfo
because the user is forced to be aware of the way the calculation
is performed.
Refactor the calculation.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
According to MX6 TRM, both MMDC and DRAM should be configured to
the same powerdown precharge. Currently, mx6_dram_cfg()
configures MMDC for fast pd (MDPDC[7] = 0), and the DRAM for
'slow exit (DLL off)' (MR0[12] = 0).
Configure MMDC for slow pd.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Tim Harvey <tharvey@gateworks.com>
Add macro which defines i2c_pads_info structs for multiple SoC types,
and a macro which selects the appropriate struct based on CPU type,
thus eliminating the need to manage multiple i2c pad configurations
manually when supporting multiple SoC types.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Acked-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Define the new common function sata_port_status() which can be
used to query the sata driver for the state of ports, and implement it
for dwc_ahsata.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Marek Vasut <marex@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
There are many similarities between the IMX6QUAD/IMX6DUAL and there are
many similarities between the IMX6SOLO/IMX6DUALITE. Add a 'soctype' env
variable that tells you which type you have.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
The GW5520 has an IMX6Q SoC with 512MB of DDR3, 256MB of NAND flash as well as:
* 2x MiniPCIe sockets
* 2x USB host sockets
* 2x i210 GigE
* HDMI out
* digital I/O expansion
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
The IMX6 MMDC calibration registers depend on propagation delay and capacitive
loading between the SoC's MMDC and the DDR3 chips. On the Ventana boards the
board layout varies little in trace-lengths such that propagation delays are
irrelevant thus we can simply things by using calibration values obtained
from various board layouts based on a common SoC and DDR chip configuration.
This eliminates board-model from being needed allowing more flexibility. These
values were tested on a large sample size of Gateworks Ventana boards ranging
in layout, and memory configuration over the entire temperature range supported.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
When testing the FEC driver on a mx6solox we noticed that the TDAR bit gets
always cleared prior then the READY bit is cleared in the last BD, which causes
FEC packets reception to always fail.
As explained by Ye Li:
"The TDAR bit is cleared when the descriptors are all out from TX ring, but on
mx6solox we noticed that the READY bit is still not cleared right after TDAR.
These are two distinct signals, and in IC simulation, we found that TDAR always
gets cleared prior than the READY bit of last BD becomes cleared.
In mx6solox, we use a later version of FEC IP. It looks like that this
intrinsic behaviour of TDAR bit has changed in this newer FEC version."
Fix this by polling the READY bit of BD after the TDAR polling, which covers the
mx6solox case and does not harm the other SoCs.
No performance drop has been noticed with this patch applied when testing TFTP
transfers on several boards of different i.mx SoCs.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
mx6solox has a requirement for 64 bytes alignment for RX DMA transfer.
Other SoCs work with the standard 32 bytes alignment.
Adjust it accordingly by using 64 bytes aligment in the FEC RX DMA buffers,
which addresses the needs from mx6solox and also works for the other SoCs.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
KBuild abuses the asm statement to write to a file and
clang chokes about these invalid asm statements. Hack it
even more by fooling this is actual valid asm code.
cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
cc: Tom Rini <trini@ti.com>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
"clang does not support global register variables; this is
unlikely to be implemented soon because it requires additional
LLVM backend support" [1]
Workaround it by obtaining the value of gd/r9 by an inline
asm routine. Note there is no set routine added for ARM at the
moment, since most if not all updates of gd from c are actually
not needed for ARM.
[1] http://clang.llvm.org/docs/UsersManual.html
cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
By default clang will echo a warning if a warning option is
unknown. Turning warnings into errors when polling for options
also catches such cases and prevents passing arguments to the
compiler which cause warnings.
cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
cc: Tom Rini <trini@ti.com>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Just before calling board_init_f, crt0.S has already
reserved space for the initial gd on the stack. There
should be no need to allocate it again.
cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
For ARM / ARM64 the relocation routines already updated
gd to the new value. Don't set it again. This allows
compilation with clang as it cannot update gd directly.
cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
The basic idea: Define size_t using the __SIZE_TYPE__ compiler-defined
type.
For detailed explanation see similar patch for the nios2 arch:
"nios2: Fix printf size_t format related warnings (again...)"
(sha1: 00a2517fcb)
Signed-off-by: Vasili Galka <vvv444@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch adds the TWR_LCD_RGB card/HDMI options and the common
configuration for DCU on LS1021ATWR board.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
On LS1021ATWR, Silicon's Sii9022A HDMI Transmitter
is used. This patch adds the common setting for this
chip.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
This patch is to add DCU driver support. DCU also named
2D-ACE(Two Dimensional Animation and Compositing Engine)
is a system master that fetches graphics stored in internal
or external memory and displays them on a TFT LCD panel.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
On vybrid, lpuart's registers are 8-bit. On LS102xA, lpuart's registers
are 32-bit. This patch adds the support for 32-bit registers on
LS102xA.
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Remove the DMCTRL Tx snooping bits (TDSEN and TBDSEN) as a
workaround for LS1. It has been observed that currently
the Tx stops functioning after a fair amount of Tx traffic
with these settings on. These bits are sticky and once set
they cannot be reset from Linux, for instance.
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
LS102xA is an ARMv7 implementation. This patch is to add
basic support for LS1021ATWR board.
One DDR controller
DUART1 is used as the console
For the detail board information, please refer to README.
Signed-off-by: Chen Lu <chen.lu@freescale.com>
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
LS102xA is an ARMv7 implementation. This patch is to add
basic support for LS1021AQDS board.
One DDR controller
DUART1 is used as the console
For the detail board information, please refer to README.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Jason Jin <jason.jin@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This
is not an issue unless some DQ pins are not connected. If a platform uses
regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on
those floating pins for the second rank. The workaround is to use a known
good chip select for this purpose.
Signed-off-by: York Sun <yorksun@freescale.com>
Reading DDR register should use ddr_in32() for proper endianess.
This patch fixes incorrect waiting time for ARM platforms.
Signed-off-by: York Sun <yorksun@freescale.com>
If less than 8 ECC pins are used for DDR data bus width smaller than 64
bits, the 8-bit ECC code will be transmitted/received across several beats,
and it will be used to check 64-bits of data once 8-bits of ECC are
accumulated.
Signed-off-by: York Sun <yorksun@freescale.com>
For LS1, esdhc is big-endian IP. Accessing the registers
should be in big-endian mode. So we use esdhc_read32()
to read Host controller capabilities register for LS1.
For LS1, when using CMD12, cmdtype need to be set to
ABORT, otherwise, next read command will hang.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
For LS102xA, the processor is in little-endian mode, while esdhc IP is
in big-endian mode. CONFIG_SYS_FSL_ESDHC_LE and CONFIG_SYS_FSL_ESDHC_BE
are added. So accessing ESDHC registers can be determined by ESDHC IP's
endian mode.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
This patch is to add etsec support for LS102xA. First, Little-endian
descriptor mode should be enabled. So RxBDs and TxBDs are interpreted
with little-endian byte ordering. Second, TSEC_SIZE and TSEC_MDIO_OFFSET
are different from PowerPC, redefine them for LS1021xA.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
fsl_enet.h defines the mapping of the usual MII management
registers, which are included in the MDIO register block
common to Freescale ethernet controllers. So it shouldn't
depend on the CPU architecture but it should be actually
part of the arch independent fsl_mdio.h.
To remove the arch dependency, merge the content of
asm/fsl_enet.h into fsl_mdio.h.
Some files (like fm_eth.h) were simply including fsl_enet.h
only for phy.h. These were updated to include phy.h instead.
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
The existing i.MX's I2C driver mxc_i2c.c is compatible
with the controller of LS102xA. As I2C's registers
are 8-bit on LS102xA, I2C_QUIRK_REG is enabled to
use 8-bit driver.
This patch is to add I2C 1,2,3 support for LS102xA.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
The QorIQ LS1 family is built on Layerscape architecture,
the industry's first software-aware, core-agnostic networking
architecture to offer unprecedented efficiency and scale.
Freescale LS102xA is a set of SoCs combines two ARM
Cortex-A7 cores that have been optimized for high
reliability and pack the highest level of integration
available for sub-3 W embedded communications processors
with Layerscape architecture and with a comprehensive
enablement model focused on ease of programmability.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Jason Jin <jason.jin@freescale.com>
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Some boards unfortunately build with warnings and it is useful to be able
to easily distinguish the warnings from the errors.
Use a simple pattern match to categorise gcc output into warnings and
errors, and display each separately. New warnings are shown in magenta (with
a w+ prefix) and fixed warnings are shown in yellow with a w- prefix.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a -l option to display a list of offending boards against each
error/warning line. The information will be shown in brackets as below:
02: wip
sandbox: + sandbox
arm: + seaboard
+(sandbox) arch/sandbox/cpu/cpu.c: In function 'timer_get_us':
+(sandbox) arch/sandbox/cpu/cpu.c:40:9: warning: unused variable 'i' [-Wunused-variable]
+(seaboard) board/nvidia/seaboard/seaboard.c: In function 'pin_mux_mmc':
+(seaboard) board/nvidia/seaboard/seaboard.c:36:9: warning: unused variable 'fred' [-Wunused-variable]
+(seaboard) int fred;
+(seaboard) ^
Signed-off-by: Simon Glass <sjg@chromium.org>
The full path is long and also includes buildman private directories.
Clean this up, so that only a relative U-Boot path is shown.
This will change warnings like these:
/home/sjg/c/src/third_party/u-boot/buildman5/.bm-work/00/arch/sandbox/cpu/cpu.c: In function 'timer_get_us':
/home/sjg/c/src/third_party/u-boot/buildman5/.bm-work/00/arch/sandbox/cpu/cpu.c:40:9: warning: unused variable 'i' [-Wunused-variable]
/home/sjg/c/src/third_party/u-boot/files/arch/sandbox/cpu/cpu.c: In function 'timer_get_us':
/home/sjg/c/src/third_party/u-boot/files/arch/sandbox/cpu/cpu.c:40:9: warning: unused variable 'i' [-Wunused-variable]
to:
arch/sandbox/cpu/cpu.c: In function 'timer_get_us':
arch/sandbox/cpu/cpu.c:40:9: warning: unused variable 'i' [-Wunused-variable]
Signed-off-by: Simon Glass <sjg@chromium.org>
Some boards are known to be broken and it is convenient to be able to
exclude them from the build.
Add an --exclude option to specific boards to exclude. This uses the
same matching rules as the normal 'include' arguments, and is a comma-
separated list of regular expressions.
Suggested-by: York Sun <yorksun@freescale.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
These characters are commonly used in variables, so permit them. Also
document the permitted characters.
Reported-by: Tom Rini <trini@ti.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
When buildman finds errors/warnings when building, set the return code to
indicate this.
Suggested-by: York Sun <yorksun@freescale.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
patman collects tags that it sees in the commit and places them nicely
sorted at the end of the patch. However, this is not really necessary and
in fact is apparently not desirable.
Suggested-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
In a headless environment the pager can apparently hang. We don't want a
pager anyway so let's request that none be used.
Reported-by: Tom Rini <trini@ti.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
It seems that this is no longer needed, since checkpatch.pl will catch
whitespace problems in patches. Also the option is not widely used, so
it seems safe to just remove it.
Suggested-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
It seems that doctest behaves differently now, and some of the unit tests
do not run. Adjust the tests to work correctly.
./tools/patman/patman --test
<unittest.result.TestResult run=10 errors=0 failures=0>
Signed-off-by: Simon Glass <sjg@chromium.org>
This patch adds DT properties for fimd and the parade bridge chip
present on peach_pit. The panel supports 1366x768 resolution.
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
On Exynos5420 and newer versions, the FIMD sysmmus are in
"on state" by default.
We have to disable them in order to make FIMD DMA work.
This patch adds the required framework to exynos_fimd driver,
and disables FIMD sysmmu on Exynos5420.
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 needed by
exynos video driver.
Also, configure ACLK_400_DISP1 as the parent for MUX_ACLK_400_DISP1_SUB_SEL.
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Previously, we used to statically assign values for vl_col, vl_row and
vl_bpix using #defines like LCD_XRES, LCD_YRES and LCD_COLOR16.
Introducing the function exynos_lcd_early_init() would take care of this
assignment on the fly by parsing FIMD DT properties, thereby allowing us
to remove LCD_XRES and LCD_YRES from the main config file.
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch adds support for Olimex A20-OLinuXino-LIME board.
Signed-off-by: FUKAUMI Naoki <naobsd@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Patch is the result of:
sed -i -e 's/FTDFILE/FDTFILE/g' board/sunxi/Kconfig configs/* include/configs/sunxi-common.h
sed -i -e 's/ftdfile/fdtfile/g' board/sunxi/Kconfig
Reported-by: Vagrant Cascadian <vagrant@debian.org>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Hans de Goede <hdegoede@redhat.com>
[ ijc -- s/Spotted-by/Reported-by/ and resolve conflict vs "remove
redundant "SPL" from CONFIG_SYS_EXTRA_OPTIONS" ]
CONFIG_SPL is defined as a primary option in Kconfig.
It should not be added to CONFIG_SYS_EXTRA_OPTIONS.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
This patch changes MPLL from 800MHz to 880MHz on Odroid.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This board file supports standard features of Odroid X2 and U3 boards:
- Exynos4412 core clock set to 1000MHz and MPLL peripherial clock set to 800MHz,
- MAX77686 power regulator,
- USB PHY,
- enable XCL205 - power for board peripherials
- check board type: U3 or X2.
- enable Odroid U3 FAN cooler
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This change adds setup of environmental board info using
get_board_name() and get_board_type() functions for config
CONFIG_BOARD_TYPES.
This is useful in case of running many boards with just one config.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This change adds declaration of functions:
- set_board_type() - called at board_early_init_f()
- get_board_type() - called at checkboard()
For supporting multiple board types in a one config - it is welcome
to display the current board model. This is what get_board_type()
should return.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
On an Odroid U3 board, the SOC is unable to reset the eMMC card
in the DWMMC mode by the cpu software reset. Manual reset of the card
by switching proper gpio pin - fixes this issue.
Such solution needs to add a call to pre reset function.
This is done by the reset_misc() function, which is called before reset_cpu().
The function reset_misc() is a weak function.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Changes v4:
- arch/arm/reset: fix weak function attribute to proper style
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This change enable automatic setting of dfu alt info
on every boot. This is useful in case of booting one
u-boot binary from multiple media.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This change introduces new common function:
- set_dfu_alt_info() - put dfu system and bootloader setting
into $dfu_alt_info.
functions declaration:
- char *get_dfu_alt_system(void)
- char *get_dfu_alt_boot(void)
- void set_dfu_alt_info(void)
and new config:
- CONFIG_SET_DFU_ALT_INFO
This function can be used for auto setting dfu configuration on boot.
Such feature is useful for multi board support by one u-boot binary.
Each board should define two functions:
- get_dfu_alt_system()
- get_dfu_alt_boot()
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
It is possible to boot device using a micro SD or eMMC slots.
In this situation, boot device should be registered as a block
device 0 in the MMC framework, because CONFIG_SYS_MMC_ENV_DEV
is usually set to "0" in the most config cases.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
On DRA72x, EMIF supports DDR3 upto 667MHz.
Adding the required settings for DDR3 at 666MHz and enabling it.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
To reduce code duplication update am335x_igep0033.h to use ti_am335x_common.h
and convert to generic board.
Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
OMAP GPMC driver used with some NAND Flash devices (e.g. Spansion
S34ML08G1) causes that U-boot shows hundreds of 'nand: bit-flip
corrected' error messages. Possible cause was discussed in the
mailinglist thread:
http://lists.denx.de/pipermail/u-boot/2014-April/177508.html
Quote (Author: Pekon Gupta <pekon@ti.com>): "The issue is mainly
due to a NAND protocol violation in the omap driver since the
Random Data Output command (05h-E0h) expects to see only the
column address that should be addressed within the already loaded
read page into the read buffer. Only 2 address cycles with ALE
active should be provided between the 05h and E0h commands. The
Page read command expects the full address footprint (2bytes for
column address + 3bytes for row address), but once the page is
loaded into the read buffer, Random Data Output should be used
with only 2bytes for column address."
This patch combines the solution proposed in the mailinglist and
the patch provided by the Spansion company (GPLv2 code, source:
http://www.spansion.com/Support/Software/u-boot-psp-04.04.00.01-NAND.zip)
Signed-off-by: Rostislav Lisovy <lisovy@merica.cz>
Since the CS of a device connected to the GPMC was
stored in the global variable, it was not possible to
use multiple devices. In this patch the CS is stored per
device in its 'struct omap_nand_info'. This makes it
possible to use up to 'GPMC_MAX_CS' NAND Flash devices
connected to U-boot.
Signed-off-by: Rostislav Lisovy <lisovy@merica.cz>
In case when 4K page keystone RBL layout is used the compilation
error is appeared. That's because the #ifdef has to be placed under
struct name. This patch correct it.
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
The help message in board/ti/am335x/Kconfig says AM335x has
6 UARTs, so the valid number for CONFIG_CONS_INDEX is from 1 to 6.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
There is no reason to redefine pure readl/writel functions.
So remove this redundancy.
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Acked-by: Vitaly Andrianov <vitalya@ti.com>
The mask for BWADJ field of PASSPLLCTL0 register has to be 0xff, but
by mistake, here is used shift instead of mask, so correct it.
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-09-04 13:05:57 -04:00
1751 changed files with 35141 additions and 19149 deletions
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