Prepare v2015.04

Signed-off-by: Tom Rini <trini@konsulko.com>

MAINTAINERS

@@ -151,10 +151,10 @@ ARM TI
 M:	Tom Rini <trini@konsulko.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-ti.git
-F:	arch/arm/cpu/arm926ejs/davinci/
+F:	arch/arm/mach-davinci/
+F:	arch/arm/mach-keystone/
 F:	arch/arm/cpu/arm926ejs/omap/
 F:	arch/arm/cpu/armv7/omap*/
-F:	arch/arm/include/asm/arch-davinci/
 F:	arch/arm/include/asm/arch-omap*/
 F:	arch/arm/include/asm/ti-common/
 

MAKEALL

@@ -551,13 +551,7 @@ get_target_maintainers() {
 get_target_arch() {
 	local target=$1
 
-	# Automatic mode
-	local line=`awk '\$7 == "'"$target"'" { print \$0 }' boards.cfg`
-
-	if [ -z "${line}" ] ; then echo "" ; return ; fi
-
-	set ${line}
-	echo "$2"
+	awk '$7 == "'$target'" { print $2 }' boards.cfg
 }
 
 list_target() {

Makefile

@@ -1,7 +1,7 @@
 VERSION = 2015
 PATCHLEVEL = 04
 SUBLEVEL =
-EXTRAVERSION = -rc5
+EXTRAVERSION =
 NAME =
 
 # *DOCUMENTATION*
@@ -513,12 +513,16 @@ include/config/%.conf: $(KCONFIG_CONFIG) include/config/auto.conf.cmd
 # is up-to-date. When we switch to a different board configuration, old CONFIG
 # macros are still remaining in include/config/auto.conf. Without the following
 # gimmick, wrong config.mk would be included leading nasty warnings/errors.
-autoconf_is_current := $(if $(wildcard $(KCONFIG_CONFIG)),$(shell find . \
-		-path ./include/config/auto.conf -newer $(KCONFIG_CONFIG)))
-ifneq ($(autoconf_is_current),)
+ifneq ($(wildcard $(KCONFIG_CONFIG)),)
+ifneq ($(wildcard include/config/auto.conf),)
+autoconf_is_old := $(shell find . -path ./$(KCONFIG_CONFIG) -newer \
+						include/config/auto.conf)
+ifeq ($(autoconf_is_old),)
 include $(srctree)/config.mk
 include $(srctree)/arch/$(ARCH)/Makefile
 endif
+endif
+endif
 
 # If board code explicitly specified LDSCRIPT or CONFIG_SYS_LDSCRIPT, use
 # that (or fail if absent).  Otherwise, search for a linker script in a
@@ -905,6 +909,26 @@ OBJCOPYFLAGS_u-boot-with-spl.bin = -I binary -O binary \
 u-boot-with-spl.bin: spl/u-boot-spl.bin $(SPL_PAYLOAD) FORCE
 	$(call if_changed,pad_cat)
 
+MKIMAGEFLAGS_lpc32xx-spl.img = -T lpc32xximage -a $(CONFIG_SPL_TEXT_BASE)
+
+lpc32xx-spl.img: spl/u-boot-spl.bin FORCE
+	$(call if_changed,mkimage)
+
+OBJCOPYFLAGS_lpc32xx-boot-0.bin = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO)
+
+lpc32xx-boot-0.bin: lpc32xx-spl.img
+	$(call if_changed,objcopy)
+
+OBJCOPYFLAGS_lpc32xx-boot-1.bin = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO)
+
+lpc32xx-boot-1.bin: lpc32xx-spl.img
+	$(call if_changed,objcopy)
+
+lpc32xx-full.bin: lpc32xx-boot-0.bin lpc32xx-boot-1.bin u-boot.img
+	$(call if_changed,cat)
+
+CLEAN_FILES += lpc32xx-*
+
 OBJCOPYFLAGS_u-boot-with-tpl.bin = -I binary -O binary \
 				   --pad-to=$(CONFIG_TPL_PAD_TO)
 tpl/u-boot-with-tpl.bin: tpl/u-boot-tpl.bin u-boot.bin FORCE

README

@@ -3607,6 +3607,16 @@ FIT uImage format:
 		CONFIG_SPL_STACK
 		Adress of the start of the stack SPL will use
 
+		CONFIG_SPL_PANIC_ON_RAW_IMAGE
+		When defined, SPL will panic() if the image it has
+		loaded does not have a signature.
+		Defining this is useful when code which loads images
+		in SPL cannot guarantee that absolutely all read errors
+		will be caught.
+		An example is the LPC32XX MLC NAND driver, which will
+		consider that a completely unreadable NAND block is bad,
+		and thus should be skipped silently.
+
 		CONFIG_SPL_RELOC_STACK
 		Adress of the start of the stack SPL will use after
 		relocation.  If unspecified, this is equal to

arch/Kconfig

@@ -14,6 +14,7 @@ config ARC
 	select HAVE_PRIVATE_LIBGCC
 	select HAVE_GENERIC_BOARD
 	select SYS_GENERIC_BOARD
+	select SUPPORT_OF_CONTROL
 
 config ARM
 	bool "ARM architecture"

arch/arc/Kconfig

@@ -123,7 +123,7 @@ config ARC_CACHE_LINE_SHIFT
 	int "Cache Line Length (as power of 2)"
 	range 5 7
 	default "6"
-	depends on !SYS_DCACHE_OFF || !SYS_DCACHE_OFF
+	depends on !SYS_DCACHE_OFF || !SYS_ICACHE_OFF
 	help
 	  Starting with ARC700 4.9, Cache line length is configurable,
 	  This option specifies "N", with Line-len = 2 power N
@@ -133,6 +133,14 @@ config ARC_CACHE_LINE_SHIFT
 choice
 	prompt "Target select"
 
+config TARGET_DUMMY
+	bool "Dummy target"
+	help
+	  Please select one of real target boards below!
+	  This target is only meant to force "makedefconfig" to put
+	  TARGET_xxx in defconfig even this is the first target from the list
+	  below.
+
 config TARGET_TB100
 	bool "Support tb100"
 

arch/arc/cpu/arcv1/Makefile

@@ -4,4 +4,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-y += start.o
+obj-y += ivt.o

arch/arc/cpu/arcv1/ivt.S

@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+.section .ivt, "ax",@progbits
+.align 4
+_ivt:
+	/* Critical system events */
+	j	_start			/* 0 - 0x000 */
+	j	memory_error		/* 1 - 0x008 */
+	j	instruction_error	/* 2 - 0x010 */
+
+	/* Device interrupts */
+.rept	29
+	j	interrupt_handler	/* 3:31 - 0x018:0xF8 */
+.endr
+	/* Exceptions */
+	j	EV_MachineCheck		/* 0x100, Fatal Machine check  (0x20) */
+	j	EV_TLBMissI		/* 0x108, Intruction TLB miss  (0x21) */
+	j	EV_TLBMissD		/* 0x110, Data TLB miss        (0x22) */
+	j	EV_TLBProtV		/* 0x118, Protection Violation (0x23)
+							or Misaligned Access  */
+	j	EV_PrivilegeV		/* 0x120, Privilege Violation  (0x24) */
+	j	EV_Trap			/* 0x128, Trap exception       (0x25) */
+	j	EV_Extension		/* 0x130, Extn Intruction Excp (0x26) */

arch/arc/cpu/arcv1/start.S

@@ -1,254 +0,0 @@
-/*
- * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <asm/arcregs.h>
-
-/*
- * Note on the LD/ST addressing modes with address register write-back
- *
- * LD.a same as LD.aw
- *
- * LD.a    reg1, [reg2, x]  => Pre Incr
- *      Eff Addr for load = [reg2 + x]
- *
- * LD.ab   reg1, [reg2, x]  => Post Incr
- *      Eff Addr for load = [reg2]
- */
-
-.macro PUSH reg
-	st.a	\reg, [%sp, -4]
-.endm
-
-.macro PUSHAX aux
-	lr	%r9, [\aux]
-	PUSH	%r9
-.endm
-
-.macro  SAVE_R1_TO_R24
-	PUSH	%r1
-	PUSH	%r2
-	PUSH	%r3
-	PUSH	%r4
-	PUSH	%r5
-	PUSH	%r6
-	PUSH	%r7
-	PUSH	%r8
-	PUSH	%r9
-	PUSH	%r10
-	PUSH	%r11
-	PUSH	%r12
-	PUSH	%r13
-	PUSH	%r14
-	PUSH	%r15
-	PUSH	%r16
-	PUSH	%r17
-	PUSH	%r18
-	PUSH	%r19
-	PUSH	%r20
-	PUSH	%r21
-	PUSH	%r22
-	PUSH	%r23
-	PUSH	%r24
-.endm
-
-.macro SAVE_ALL_SYS
-	/* saving %r0 to reg->r0 in advance since we read %ecr into it */
-	st	%r0, [%sp, -8]
-	lr	%r0, [%ecr]	/* all stack addressing is manual so far */
-	st	%r0, [%sp]
-	st	%sp, [%sp, -4]
-	/* now move %sp to reg->r0 position so we can do "push" automatically */
-	sub	%sp, %sp, 8
-
-	SAVE_R1_TO_R24
-	PUSH	%r25
-	PUSH	%gp
-	PUSH	%fp
-	PUSH	%blink
-	PUSHAX	%eret
-	PUSHAX	%erstatus
-	PUSH	%lp_count
-	PUSHAX	%lp_end
-	PUSHAX	%lp_start
-	PUSHAX	%erbta
-.endm
-
-.macro SAVE_EXCEPTION_SOURCE
-#ifdef CONFIG_MMU
-	/* If MMU exists exception faulting address is loaded in EFA reg */
-	lr	%r0, [%efa]
-#else
-	/* Otherwise in ERET (exception return) reg */
-	lr	%r0, [%eret]
-#endif
-.endm
-
-.section .ivt, "ax",@progbits
-.align 4
-_ivt:
-	/* Critical system events */
-	j	_start			/* 0 - 0x000 */
-	j	memory_error		/* 1 - 0x008 */
-	j	instruction_error	/* 2 - 0x010 */
-
-	/* Device interrupts */
-.rept	29
-	j	interrupt_handler	/* 3:31 - 0x018:0xF8 */
-.endr
-	/* Exceptions */
-	j	EV_MachineCheck		/* 0x100, Fatal Machine check  (0x20) */
-	j	EV_TLBMissI		/* 0x108, Intruction TLB miss  (0x21) */
-	j	EV_TLBMissD		/* 0x110, Data TLB miss        (0x22) */
-	j	EV_TLBProtV		/* 0x118, Protection Violation (0x23)
-							or Misaligned Access  */
-	j	EV_PrivilegeV		/* 0x120, Privilege Violation  (0x24) */
-	j	EV_Trap			/* 0x128, Trap exception       (0x25) */
-	j	EV_Extension		/* 0x130, Extn Intruction Excp (0x26) */
-
-.text
-.globl _start
-_start:
-	/* Setup interrupt vector base that matches "__text_start" */
-	sr	__ivt_start, [ARC_AUX_INTR_VEC_BASE]
-
-	/* Setup stack pointer */
-	mov	%sp, CONFIG_SYS_INIT_SP_ADDR
-	mov	%fp, %sp
-
-	/* Clear bss */
-	mov	%r0, __bss_start
-	mov	%r1, __bss_end
-
-clear_bss:
-	st.ab	0, [%r0, 4]
-	brlt	%r0, %r1, clear_bss
-
-	/* Zero the one and only argument of "board_init_f" */
-	mov_s	%r0, 0
-	j	board_init_f
-
-memory_error:
-	SAVE_ALL_SYS
-	SAVE_EXCEPTION_SOURCE
-	mov	%r1, %sp
-	j	do_memory_error
-
-instruction_error:
-	SAVE_ALL_SYS
-	SAVE_EXCEPTION_SOURCE
-	mov	%r1, %sp
-	j	do_instruction_error
-
-interrupt_handler:
-	/* Todo - save and restore CPU context when interrupts will be in use */
-	bl	do_interrupt_handler
-	rtie
-
-EV_MachineCheck:
-	SAVE_ALL_SYS
-	SAVE_EXCEPTION_SOURCE
-	mov	%r1, %sp
-	j	do_machine_check_fault
-
-EV_TLBMissI:
-	SAVE_ALL_SYS
-	mov	%r0, %sp
-	j	do_itlb_miss
-
-EV_TLBMissD:
-	SAVE_ALL_SYS
-	mov	%r0, %sp
-	j	do_dtlb_miss
-
-EV_TLBProtV:
-	SAVE_ALL_SYS
-	SAVE_EXCEPTION_SOURCE
-	mov	%r1, %sp
-	j	do_tlb_prot_violation
-
-EV_PrivilegeV:
-	SAVE_ALL_SYS
-	mov	%r0, %sp
-	j	do_privilege_violation
-
-EV_Trap:
-	SAVE_ALL_SYS
-	mov	%r0, %sp
-	j	do_trap
-
-EV_Extension:
-	SAVE_ALL_SYS
-	mov	%r0, %sp
-	j	do_extension
-
-/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
- *
- * r0 = start_addr_sp
- * r1 = new__gd
- * r2 = relocaddr
- */
-.align 4
-.globl	relocate_code
-relocate_code:
-	/*
-	 * r0-r12 might be clobbered by C functions
-	 * so we use r13-r16 for storage here
-	 */
-	mov	%r13, %r0		/* save addr_sp */
-	mov	%r14, %r1		/* save addr of gd */
-	mov	%r15, %r2		/* save addr of destination */
-
-	mov	%r16, %r2		/* %r9 - relocation offset */
-	sub	%r16, %r16, __image_copy_start
-
-/* Set up the stack */
-stack_setup:
-	mov	%sp, %r13
-	mov	%fp, %sp
-
-/* Check if monitor is loaded right in place for relocation */
-	mov	%r0, __image_copy_start
-	cmp	%r0, %r15		/* skip relocation if code loaded */
-	bz	do_board_init_r		/* in target location already */
-
-/* Copy data (__image_copy_start - __image_copy_end) to new location */
-	mov	%r1, %r15
-	mov	%r2, __image_copy_end
-	sub	%r2, %r2, %r0		/* r3 <- amount of bytes to copy */
-	asr	%r2, %r2, 2		/* r3 <- amount of words to copy */
-	mov	%lp_count, %r2
-	lp	copy_end
-	ld.ab	%r2,[%r0,4]
-	st.ab	%r2,[%r1,4]
-copy_end:
-
-/* Fix relocations related issues */
-	bl	do_elf_reloc_fixups
-#ifndef CONFIG_SYS_ICACHE_OFF
-	bl	invalidate_icache_all
-#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
-	bl	flush_dcache_all
-#endif
-
-/* Update position of intterupt vector table */
-	lr	%r0, [ARC_AUX_INTR_VEC_BASE]	/* Read current position */
-	add	%r0, %r0, %r16			/* Update address */
-	sr	%r0, [ARC_AUX_INTR_VEC_BASE]	/* Write new position */
-
-do_board_init_r:
-/* Prepare for exection of "board_init_r" in relocated monitor */
-	mov	%r2, board_init_r	/* old address of "board_init_r()" */
-	add	%r2, %r2, %r16		/* new address of "board_init_r()" */
-	mov	%r0, %r14		/* 1-st parameter: gd_t */
-	mov	%r1, %r15		/* 2-nd parameter: dest_addr */
-	j	[%r2]

arch/arc/cpu/arcv2/Makefile

@@ -4,4 +4,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-y += start.o
+obj-y += ivt.o

arch/arc/cpu/arcv2/ivt.S

@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2013-2015 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+.section .ivt, "a",@progbits
+.align 4
+	/* Critical system events */
+.word	_start			/* 0 - 0x000 */
+.word	memory_error		/* 1 - 0x008 */
+.word	instruction_error	/* 2 - 0x010 */
+
+	/* Exceptions */
+.word	EV_MachineCheck		/* 0x100, Fatal Machine check  (0x20) */
+.word	EV_TLBMissI		/* 0x108, Intruction TLB miss  (0x21) */
+.word	EV_TLBMissD		/* 0x110, Data TLB miss        (0x22) */
+.word	EV_TLBProtV		/* 0x118, Protection Violation (0x23)
+							or Misaligned Access  */
+.word	EV_PrivilegeV		/* 0x120, Privilege Violation  (0x24) */
+.word	EV_Trap			/* 0x128, Trap exception       (0x25) */
+.word	EV_Extension		/* 0x130, Extn Intruction Excp (0x26) */
+
+	/* Device interrupts */
+.rept	29
+	j	interrupt_handler	/* 3:31 - 0x018:0xF8 */
+.endr

arch/arc/cpu/arcv2/start.S

@@ -1,254 +0,0 @@
-/*
- * Copyright (C) 2013-2015 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <asm/arcregs.h>
-
-/*
- * Note on the LD/ST addressing modes with address register write-back
- *
- * LD.a same as LD.aw
- *
- * LD.a    reg1, [reg2, x]  => Pre Incr
- *      Eff Addr for load = [reg2 + x]
- *
- * LD.ab   reg1, [reg2, x]  => Post Incr
- *      Eff Addr for load = [reg2]
- */
-
-.macro PUSH reg
-	st.a	\reg, [%sp, -4]
-.endm
-
-.macro PUSHAX aux
-	lr	%r9, [\aux]
-	PUSH	%r9
-.endm
-
-.macro  SAVE_R1_TO_R24
-	PUSH	%r1
-	PUSH	%r2
-	PUSH	%r3
-	PUSH	%r4
-	PUSH	%r5
-	PUSH	%r6
-	PUSH	%r7
-	PUSH	%r8
-	PUSH	%r9
-	PUSH	%r10
-	PUSH	%r11
-	PUSH	%r12
-	PUSH	%r13
-	PUSH	%r14
-	PUSH	%r15
-	PUSH	%r16
-	PUSH	%r17
-	PUSH	%r18
-	PUSH	%r19
-	PUSH	%r20
-	PUSH	%r21
-	PUSH	%r22
-	PUSH	%r23
-	PUSH	%r24
-.endm
-
-.macro SAVE_ALL_SYS
-	/* saving %r0 to reg->r0 in advance since weread %ecr into it */
-	st	%r0, [%sp, -8]
-	lr	%r0, [%ecr]	/* all stack addressing is manual so far */
-	st	%r0, [%sp]
-	st	%sp, [%sp, -4]
-	/* now move %sp to reg->r0 position so we can do "push" automatically */
-	sub	%sp, %sp, 8
-
-	SAVE_R1_TO_R24
-	PUSH	%r25
-	PUSH	%gp
-	PUSH	%fp
-	PUSH	%blink
-	PUSHAX	%eret
-	PUSHAX	%erstatus
-	PUSH	%lp_count
-	PUSHAX	%lp_end
-	PUSHAX	%lp_start
-	PUSHAX	%erbta
-.endm
-
-.macro SAVE_EXCEPTION_SOURCE
-#ifdef CONFIG_MMU
-	/* If MMU exists exception faulting address is loaded in EFA reg */
-	lr	%r0, [%efa]
-#else
-	/* Otherwise in ERET (exception return) reg */
-	lr	%r0, [%eret]
-#endif
-.endm
-
-.section .ivt, "a",@progbits
-.align 4
-	/* Critical system events */
-.word	_start			/* 0 - 0x000 */
-.word	memory_error		/* 1 - 0x008 */
-.word	instruction_error	/* 2 - 0x010 */
-
-	/* Exceptions */
-.word	EV_MachineCheck		/* 0x100, Fatal Machine check  (0x20) */
-.word	EV_TLBMissI		/* 0x108, Intruction TLB miss  (0x21) */
-.word	EV_TLBMissD		/* 0x110, Data TLB miss        (0x22) */
-.word	EV_TLBProtV		/* 0x118, Protection Violation (0x23)
-							or Misaligned Access  */
-.word	EV_PrivilegeV		/* 0x120, Privilege Violation  (0x24) */
-.word	EV_Trap			/* 0x128, Trap exception       (0x25) */
-.word	EV_Extension		/* 0x130, Extn Intruction Excp (0x26) */
-
-	/* Device interrupts */
-.rept	29
-	j	interrupt_handler	/* 3:31 - 0x018:0xF8 */
-.endr
-
-.text
-.globl _start
-_start:
-	/* Setup interrupt vector base that matches "__text_start" */
-	sr	__ivt_start, [ARC_AUX_INTR_VEC_BASE]
-
-	/* Setup stack pointer */
-	mov	%sp, CONFIG_SYS_INIT_SP_ADDR
-	mov	%fp, %sp
-
-	/* Clear bss */
-	mov	%r0, __bss_start
-	mov	%r1, __bss_end
-
-clear_bss:
-	st.ab	0, [%r0, 4]
-	brlt	%r0, %r1, clear_bss
-
-	/* Zero the one and only argument of "board_init_f" */
-	mov_s	%r0, 0
-	j	board_init_f
-
-memory_error:
-	SAVE_ALL_SYS
-	SAVE_EXCEPTION_SOURCE
-	mov	%r1, %sp
-	j	do_memory_error
-
-instruction_error:
-	SAVE_ALL_SYS
-	SAVE_EXCEPTION_SOURCE
-	mov	%r1, %sp
-	j	do_instruction_error
-
-interrupt_handler:
-	/* Todo - save and restore CPU context when interrupts will be in use */
-	bl	do_interrupt_handler
-	rtie
-
-EV_MachineCheck:
-	SAVE_ALL_SYS
-	SAVE_EXCEPTION_SOURCE
-	mov	%r1, %sp
-	j	do_machine_check_fault
-
-EV_TLBMissI:
-	SAVE_ALL_SYS
-	mov	%r0, %sp
-	j	do_itlb_miss
-
-EV_TLBMissD:
-	SAVE_ALL_SYS
-	mov	%r0, %sp
-	j	do_dtlb_miss
-
-EV_TLBProtV:
-	SAVE_ALL_SYS
-	SAVE_EXCEPTION_SOURCE
-	mov	%r1, %sp
-	j	do_tlb_prot_violation
-
-EV_PrivilegeV:
-	SAVE_ALL_SYS
-	mov	%r0, %sp
-	j	do_privilege_violation
-
-EV_Trap:
-	SAVE_ALL_SYS
-	mov	%r0, %sp
-	j	do_trap
-
-EV_Extension:
-	SAVE_ALL_SYS
-	mov	%r0, %sp
-	j	do_extension
-
-/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
- *
- * r0 = start_addr_sp
- * r1 = new__gd
- * r2 = relocaddr
- */
-.align 4
-.globl	relocate_code
-relocate_code:
-	/*
-	 * r0-r12 might be clobbered by C functions
-	 * so we use r13-r16 for storage here
-	 */
-	mov	%r13, %r0		/* save addr_sp */
-	mov	%r14, %r1		/* save addr of gd */
-	mov	%r15, %r2		/* save addr of destination */
-
-	mov	%r16, %r2		/* %r9 - relocation offset */
-	sub	%r16, %r16, __image_copy_start
-
-/* Set up the stack */
-stack_setup:
-	mov	%sp, %r13
-	mov	%fp, %sp
-
-/* Check if monitor is loaded right in place for relocation */
-	mov	%r0, __image_copy_start
-	cmp	%r0, %r15		/* skip relocation if code loaded */
-	bz	do_board_init_r		/* in target location already */
-
-/* Copy data (__image_copy_start - __image_copy_end) to new location */
-	mov	%r1, %r15
-	mov	%r2, __image_copy_end
-	sub	%r2, %r2, %r0		/* r3 <- amount of bytes to copy */
-	asr	%r2, %r2, 2		/* r3 <- amount of words to copy */
-	mov	%lp_count, %r2
-	lp	copy_end
-	ld.ab	%r2,[%r0,4]
-	st.ab	%r2,[%r1,4]
-copy_end:
-
-/* Fix relocations related issues */
-	bl	do_elf_reloc_fixups
-#ifndef CONFIG_SYS_ICACHE_OFF
-	bl	invalidate_icache_all
-#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
-	bl	flush_dcache_all
-#endif
-
-/* Update position of intterupt vector table */
-	lr	%r0, [ARC_AUX_INTR_VEC_BASE]	/* Read current position */
-	add	%r0, %r0, %r16			/* Update address */
-	sr	%r0, [ARC_AUX_INTR_VEC_BASE]	/* Write new position */
-
-do_board_init_r:
-/* Prepare for exection of "board_init_r" in relocated monitor */
-	mov	%r2, board_init_r	/* old address of "board_init_r()" */
-	add	%r2, %r2, %r16		/* new address of "board_init_r()" */
-	mov	%r0, %r14		/* 1-st parameter: gd_t */
-	mov	%r1, %r15		/* 2-nd parameter: dest_addr */
-	j	[%r2]

arch/arc/cpu/u-boot.lds

@@ -13,6 +13,7 @@ SECTIONS
 	.text :	{
 		*(.__text_start)
 		*(.__image_copy_start)
+		arch/arc/lib/start.o (.text*)
 		*(.text*)
 	}
 

arch/arc/dts/Makefile

@@ -0,0 +1,12 @@
+dtb-$(CONFIG_TARGET_ARCANGEL4) +=  arcangel4.dtb
+dtb-$(CONFIG_TARGET_TB100) +=  abilis_tb100.dtb
+
+targets += $(dtb-y)
+
+DTC_FLAGS += -R 4 -p 0x1000
+
+PHONY += dtbs
+dtbs: $(addprefix $(obj)/, $(dtb-y))
+	@:
+
+clean-files := *.dtb

arch/arc/dts/abilis_tb100.dts

@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2015 Synopsys, Inc. (www.synopsys.com)
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/dts-v1/;
+
+#include "skeleton.dtsi"
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	aliases {
+		console = &uart0;
+	};
+
+	uart0: serial@ff100000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0xff100000 0x1000>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+	};
+};

arch/arc/dts/arcangel4.dts

@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2015 Synopsys, Inc. (www.synopsys.com)
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/dts-v1/;
+
+#include "skeleton.dtsi"
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	aliases {
+		console = &arcuart0;
+	};
+
+	arcuart0: serial@0xc0fc1000 {
+		compatible = "snps,arc-uart";
+		reg = <0xc0fc1000 0x100>;
+		clock-frequency = <80000000>;
+	};
+
+};

arch/arc/dts/skeleton.dtsi

@@ -0,0 +1,13 @@
+/*
+ * Skeleton device tree; the bare minimum needed to boot; just include and
+ * add a compatible value.  The bootloader will typically populate the memory
+ * node.
+ */
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	chosen { };
+	aliases { };
+	memory { device_type = "memory"; reg = <0 0>; };
+};

arch/arc/include/asm/arcregs.h

@@ -46,6 +46,10 @@
 #define ARC_AUX_DC_PTAG		0x5C
 #endif
 #define ARC_BCR_DC_BUILD	0x72
+#define ARC_BCR_SLC		0xce
+#define ARC_AUX_SLC_CONTROL	0x903
+#define ARC_AUX_SLC_FLUSH	0x904
+#define ARC_AUX_SLC_INVALIDATE	0x905
 
 #ifndef __ASSEMBLY__
 /* Accessors for auxiliary registers */

arch/arc/include/asm/cache.h

@@ -27,4 +27,15 @@
 #define CONFIG_ARC_MMU_VER 4
 #endif
 
+#ifndef __ASSEMBLY__
+
+#ifdef CONFIG_ISA_ARCV2
+void slc_enable(void);
+void slc_disable(void);
+void slc_flush(void);
+void slc_invalidate(void);
+#endif
+
+#endif /* __ASSEMBLY__ */
+
 #endif /* __ASM_ARC_CACHE_H */

arch/arc/include/asm/config.h

@@ -7,7 +7,6 @@
 #ifndef __ASM_ARC_CONFIG_H_
 #define __ASM_ARC_CONFIG_H_
 
-#define CONFIG_SYS_GENERIC_GLOBAL_DATA
 #define CONFIG_SYS_BOOT_RAMDISK_HIGH
 #define CONFIG_ARCH_EARLY_INIT_R
 

arch/arc/include/asm/init_helpers.h

@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) 2013-2015 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_ARC_INIT_HELPERS_H
+#define _ASM_ARC_INIT_HELPERS_H
+
+int init_cache_f_r(void);
+
+#endif	/* _ASM_ARC_INIT_HELPERS_H */

arch/arc/include/asm/relocate.h

@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2013-2015 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_ARC_RELOCATE_H
+#define _ASM_ARC_RELOCATE_H
+
+#include <common.h>
+
+int copy_uboot_to_ram(void);
+int clear_bss(void);
+int do_elf_reloc_fixups(void);
+
+#endif	/* _ASM_ARC_RELOCATE_H */

arch/arc/include/asm/u-boot-arc.h

@@ -9,4 +9,7 @@
 
 int arch_early_init_r(void);
 
+void	board_init_f_r_trampoline(ulong) __attribute__ ((noreturn));
+void	board_init_f_r(void) __attribute__ ((noreturn));
+
 #endif	/* __ASM_ARC_U_BOOT_ARC_H__ */

arch/arc/lib/Makefile

@@ -4,6 +4,8 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
+extra-y	= start.o
+head-y := start.o
 obj-y += cache.o
 obj-y += cpu.o
 obj-y += interrupts.o
@@ -18,6 +20,8 @@ obj-y += memcpy-700.o
 obj-y += memset.o
 obj-y += reset.o
 obj-y += timer.o
+obj-y += ints_low.o
+obj-y += init_helpers.o
 
 obj-$(CONFIG_CMD_BOOTM) += bootm.o
 

arch/arc/lib/cache.c

@@ -16,6 +16,7 @@
 #define DC_CTRL_INV_MODE_FLUSH	(1 << 6)
 #define DC_CTRL_FLUSH_STATUS	(1 << 8)
 #define CACHE_VER_NUM_MASK	0xF
+#define SLC_CTRL_SB		(1 << 2)
 
 int icache_status(void)
 {
@@ -49,10 +50,12 @@ void icache_disable(void)
 
 void invalidate_icache_all(void)
 {
-#ifndef CONFIG_SYS_ICACHE_OFF
+	/* If no cache in CPU exit immediately */
+	if (!(read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK))
+		return;
+
 	/* Any write to IC_IVIC register triggers invalidation of entire I$ */
 	write_aux_reg(ARC_AUX_IC_IVIC, 1);
-#endif /* CONFIG_SYS_ICACHE_OFF */
 }
 
 int dcache_status(void)
@@ -156,13 +159,60 @@ void invalidate_dcache_range(unsigned long start, unsigned long end)
 
 void invalidate_dcache_all(void)
 {
-#ifndef CONFIG_SYS_DCACHE_OFF
+	/* If no cache in CPU exit immediately */
+	if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
+		return;
+
 	/* Write 1 to DC_IVDC register triggers invalidation of entire D$ */
 	write_aux_reg(ARC_AUX_DC_IVDC, 1);
-#endif /* CONFIG_SYS_DCACHE_OFF */
 }
 
 void flush_cache(unsigned long start, unsigned long size)
 {
 	flush_dcache_range(start, start + size);
 }
+
+#ifdef CONFIG_ISA_ARCV2
+void slc_enable(void)
+{
+	/* If SLC ver = 0, no SLC present in CPU */
+	if (!(read_aux_reg(ARC_BCR_SLC) & 0xff))
+		return;
+
+	write_aux_reg(ARC_AUX_SLC_CONTROL,
+		      read_aux_reg(ARC_AUX_SLC_CONTROL) & ~1);
+}
+
+void slc_disable(void)
+{
+	/* If SLC ver = 0, no SLC present in CPU */
+	if (!(read_aux_reg(ARC_BCR_SLC) & 0xff))
+		return;
+
+	write_aux_reg(ARC_AUX_SLC_CONTROL,
+		      read_aux_reg(ARC_AUX_SLC_CONTROL) | 1);
+}
+
+void slc_flush(void)
+{
+	/* If SLC ver = 0, no SLC present in CPU */
+	if (!(read_aux_reg(ARC_BCR_SLC) & 0xff))
+		return;
+
+	write_aux_reg(ARC_AUX_SLC_FLUSH, 1);
+
+	/* Wait flush end */
+	while (read_aux_reg(ARC_AUX_SLC_CONTROL) & SLC_CTRL_SB)
+		;
+}
+
+void slc_invalidate(void)
+{
+	/* If SLC ver = 0, no SLC present in CPU */
+	if (!(read_aux_reg(ARC_BCR_SLC) & 0xff))
+		return;
+
+	write_aux_reg(ARC_AUX_SLC_INVALIDATE, 1);
+}
+
+#endif /* CONFIG_ISA_ARCV2 */

arch/arc/lib/cpu.c

@@ -12,19 +12,6 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int arch_cpu_init(void)
 {
-#ifdef CONFIG_SYS_ICACHE_OFF
-	icache_disable();
-#else
-	icache_enable();
-	invalidate_icache_all();
-#endif
-
-	flush_dcache_all();
-#ifdef CONFIG_SYS_DCACHE_OFF
-	dcache_disable();
-#else
-	dcache_enable();
-#endif
 	timer_init();
 
 /* In simulation (ISS) "CHIPID" and "ARCNUM" are all "ff" */

arch/arc/lib/init_helpers.c

@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2013-2015 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int init_cache_f_r(void)
+{
+#ifndef CONFIG_SYS_ICACHE_OFF
+	icache_enable();
+	/* Make sure no stale entries persist from before we disabled cache */
+	invalidate_icache_all();
+#endif
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+	dcache_enable();
+	/* Make sure no stale entries persist from before we disabled cache */
+	invalidate_dcache_all();
+#endif
+	return 0;
+}

arch/arc/lib/ints_low.S

@@ -0,0 +1,151 @@
+/*
+ * Copyright (C) 2013-2015 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <linux/linkage.h>
+
+/*
+ * Note on the LD/ST addressing modes with address register write-back
+ *
+ * LD.a same as LD.aw
+ *
+ * LD.a    reg1, [reg2, x]  => Pre Incr
+ *      Eff Addr for load = [reg2 + x]
+ *
+ * LD.ab   reg1, [reg2, x]  => Post Incr
+ *      Eff Addr for load = [reg2]
+ */
+
+.macro PUSH reg
+	st.a	\reg, [%sp, -4]
+.endm
+
+.macro PUSHAX aux
+	lr	%r9, [\aux]
+	PUSH	%r9
+.endm
+
+.macro  SAVE_R1_TO_R24
+	PUSH	%r1
+	PUSH	%r2
+	PUSH	%r3
+	PUSH	%r4
+	PUSH	%r5
+	PUSH	%r6
+	PUSH	%r7
+	PUSH	%r8
+	PUSH	%r9
+	PUSH	%r10
+	PUSH	%r11
+	PUSH	%r12
+	PUSH	%r13
+	PUSH	%r14
+	PUSH	%r15
+	PUSH	%r16
+	PUSH	%r17
+	PUSH	%r18
+	PUSH	%r19
+	PUSH	%r20
+	PUSH	%r21
+	PUSH	%r22
+	PUSH	%r23
+	PUSH	%r24
+.endm
+
+.macro SAVE_ALL_SYS
+	/* saving %r0 to reg->r0 in advance since we read %ecr into it */
+	st	%r0, [%sp, -8]
+	lr	%r0, [%ecr]	/* all stack addressing is manual so far */
+	st	%r0, [%sp]
+	st	%sp, [%sp, -4]
+	/* now move %sp to reg->r0 position so we can do "push" automatically */
+	sub	%sp, %sp, 8
+
+	SAVE_R1_TO_R24
+	PUSH	%r25
+	PUSH	%gp
+	PUSH	%fp
+	PUSH	%blink
+	PUSHAX	%eret
+	PUSHAX	%erstatus
+	PUSH	%lp_count
+	PUSHAX	%lp_end
+	PUSHAX	%lp_start
+	PUSHAX	%erbta
+.endm
+
+.macro SAVE_EXCEPTION_SOURCE
+#ifdef CONFIG_MMU
+	/* If MMU exists exception faulting address is loaded in EFA reg */
+	lr	%r0, [%efa]
+#else
+	/* Otherwise in ERET (exception return) reg */
+	lr	%r0, [%eret]
+#endif
+.endm
+
+ENTRY(memory_error)
+	SAVE_ALL_SYS
+	SAVE_EXCEPTION_SOURCE
+	mov	%r1, %sp
+	j	do_memory_error
+ENDPROC(memory_error)
+
+ENTRY(instruction_error)
+	SAVE_ALL_SYS
+	SAVE_EXCEPTION_SOURCE
+	mov	%r1, %sp
+	j	do_instruction_error
+ENDPROC(instruction_error)
+
+ENTRY(interrupt_handler)
+	/* Todo - save and restore CPU context when interrupts will be in use */
+	bl	do_interrupt_handler
+	rtie
+ENDPROC(interrupt_handler)
+
+ENTRY(EV_MachineCheck)
+	SAVE_ALL_SYS
+	SAVE_EXCEPTION_SOURCE
+	mov	%r1, %sp
+	j	do_machine_check_fault
+ENDPROC(EV_MachineCheck)
+
+ENTRY(EV_TLBMissI)
+	SAVE_ALL_SYS
+	mov	%r0, %sp
+	j	do_itlb_miss
+ENDPROC(EV_TLBMissI)
+
+ENTRY(EV_TLBMissD)
+	SAVE_ALL_SYS
+	mov	%r0, %sp
+	j	do_dtlb_miss
+ENDPROC(EV_TLBMissD)
+
+ENTRY(EV_TLBProtV)
+	SAVE_ALL_SYS
+	SAVE_EXCEPTION_SOURCE
+	mov	%r1, %sp
+	j	do_tlb_prot_violation
+ENDPROC(EV_TLBProtV)
+
+ENTRY(EV_PrivilegeV)
+	SAVE_ALL_SYS
+	mov	%r0, %sp
+	j	do_privilege_violation
+ENDPROC(EV_PrivilegeV)
+
+ENTRY(EV_Trap)
+	SAVE_ALL_SYS
+	mov	%r0, %sp
+	j	do_trap
+ENDPROC(EV_Trap)
+
+ENTRY(EV_Extension)
+	SAVE_ALL_SYS
+	mov	%r0, %sp
+	j	do_extension
+ENDPROC(EV_Extension)

arch/arc/lib/relocate.c

@@ -10,6 +10,25 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+int copy_uboot_to_ram(void)
+{
+	size_t len = (size_t)&__image_copy_end - (size_t)&__image_copy_start;
+
+	memcpy((void *)gd->relocaddr, (void *)&__image_copy_start, len);
+
+	return 0;
+}
+
+int clear_bss(void)
+{
+	ulong dst_addr = (ulong)&__bss_start + gd->reloc_off;
+	size_t len = (size_t)&__bss_end - (size_t)&__bss_start;
+
+	memset((void *)dst_addr, 0x00, len);
+
+	return 0;
+}
+
 /*
  * Base functionality is taken from x86 version with added ARC-specifics
  */

arch/arc/lib/start.S

@@ -0,0 +1,63 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <linux/linkage.h>
+#include <asm/arcregs.h>
+
+ENTRY(_start)
+	/* Setup interrupt vector base that matches "__text_start" */
+	sr	__ivt_start, [ARC_AUX_INTR_VEC_BASE]
+
+	/* Setup stack- and frame-pointers */
+	mov	%sp, CONFIG_SYS_INIT_SP_ADDR
+	mov	%fp, %sp
+
+	/* Unconditionally disable caches */
+#ifdef CONFIG_ISA_ARCV2
+	bl	slc_flush
+	bl	slc_disable
+#endif
+	bl	flush_dcache_all
+	bl	dcache_disable
+	bl	icache_disable
+
+	/* Allocate and zero GD, update SP */
+	mov	%r0, %sp
+	bl	board_init_f_mem
+
+	/* Update stack- and frame-pointers */
+	mov	%sp, %r0
+	mov	%fp, %sp
+
+	/* Zero the one and only argument of "board_init_f" */
+	mov_s	%r0, 0
+	j	board_init_f
+ENDPROC(_start)
+
+/*
+ * void board_init_f_r_trampoline(stack-pointer address)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ * r0 = new stack-pointer
+ */
+ENTRY(board_init_f_r_trampoline)
+	/* Set up the stack- and frame-pointers */
+	mov	%sp, %r0
+	mov	%fp, %sp
+
+	/* Update position of intterupt vector table */
+	lr	%r0, [ARC_AUX_INTR_VEC_BASE]
+	ld	%r1, [%r25, GD_RELOC_OFF]
+	add	%r0, %r0, %r1
+	sr	%r0, [ARC_AUX_INTR_VEC_BASE]
+
+	/* Re-enter U-Boot by calling board_init_f_r */
+	j	board_init_f_r
+ENDPROC(board_init_f_r_trampoline)

arch/arm/Kconfig

@@ -132,6 +132,11 @@ config TARGET_DEVKIT3250
 	bool "Support devkit3250"
 	select CPU_ARM926EJS
 
+config TARGET_WORK_92105
+	bool "Support work_92105"
+	select CPU_ARM926EJS
+	select SUPPORT_SPL
+
 config TARGET_MX25PDK
 	bool "Support mx25pdk"
 	select CPU_ARM926EJS
@@ -432,6 +437,10 @@ config ARCH_MX6
 	bool "Freescale MX6"
 	select CPU_V7
 
+config ARCH_MX5
+	bool "Freescale MX5"
+	select CPU_V7
+
 config TARGET_M53EVK
 	bool "Support m53evk"
 	select CPU_V7
@@ -736,6 +745,8 @@ source "arch/arm/mach-kirkwood/Kconfig"
 
 source "arch/arm/cpu/armv7/mx6/Kconfig"
 
+source "arch/arm/cpu/armv7/mx5/Kconfig"
+
 source "arch/arm/mach-nomadik/Kconfig"
 
 source "arch/arm/cpu/armv7/omap3/Kconfig"
@@ -872,6 +883,7 @@ source "board/vpac270/Kconfig"
 source "board/wandboard/Kconfig"
 source "board/warp/Kconfig"
 source "board/woodburn/Kconfig"
+source "board/work-microwave/work_92105/Kconfig"
 source "board/xaeniax/Kconfig"
 source "board/xilinx/zynqmp/Kconfig"
 source "board/zipitz2/Kconfig"

arch/arm/Makefile

@@ -2,6 +2,43 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
+ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TEGRA),yy)
+CONFIG_CPU_V7=
+CONFIG_CPU_ARM720T=y
+endif
+
+# This selects which instruction set is used.
+arch-$(CONFIG_CPU_ARM720T)	=-march=armv4
+arch-$(CONFIG_CPU_ARM920T)	=-march=armv4
+arch-$(CONFIG_CPU_ARM926EJS)	=-march=armv5te
+arch-$(CONFIG_CPU_ARM946ES)	=-march=armv4
+arch-$(CONFIG_CPU_SA1100)	=-march=armv4
+arch-$(CONFIG_CPU_PXA)		=
+arch-$(CONFIG_CPU_ARM1136)	=-march=armv5
+arch-$(CONFIG_CPU_ARM1176)	=-march=armv5t
+arch-$(CONFIG_CPU_V7)		=$(call cc-option, -march=armv7-a, -march=armv5)
+arch-$(CONFIG_ARM64)		=-march=armv8-a
+
+# Evaluate arch cc-option calls now
+arch-y := $(arch-y)
+
+# This selects how we optimise for the processor.
+tune-$(CONFIG_CPU_ARM720T)	=-mtune=arm7tdmi
+tune-$(CONFIG_CPU_ARM920T)	=
+tune-$(CONFIG_CPU_ARM926EJS)	=
+tune-$(CONFIG_CPU_ARM946ES)	=
+tune-$(CONFIG_CPU_SA1100)	=-mtune=strongarm1100
+tune-$(CONFIG_CPU_PXA)		=-mcpu=xscale
+tune-$(CONFIG_CPU_ARM1136)	=
+tune-$(CONFIG_CPU_ARM1176)	=
+tune-$(CONFIG_CPU_V7)		=
+tune-$(CONFIG_ARM64)		=
+
+# Evaluate tune cc-option calls now
+tune-y := $(tune-y)
+
+PLATFORM_CPPFLAGS += $(arch-y) $(tune-y)
+
 # Machine directory name.  This list is sorted alphanumerically
 # by CONFIG_* macro name.
 machine-$(CONFIG_ARCH_AT91)		+= at91

arch/arm/cpu/arm1136/config.mk

@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-# Make ARMv5 to allow more compilers to work, even though its v6.
-PLATFORM_CPPFLAGS += -march=armv5

arch/arm/cpu/arm1176/config.mk

@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-# Make ARMv5 to allow more compilers to work, even though its v6.
-PLATFORM_CPPFLAGS += -march=armv5t

arch/arm/cpu/arm720t/config.mk

@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2002
-# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
-# Marius Groeger <mgroeger@sysgo.de>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -march=armv4 -mtune=arm7tdmi

arch/arm/cpu/arm920t/config.mk

@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -march=armv4

arch/arm/cpu/arm926ejs/config.mk

@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -march=armv5te

arch/arm/cpu/arm926ejs/lpc32xx/Makefile

@@ -6,3 +6,5 @@
 #
 
 obj-y   = cpu.o clk.o devices.o timer.o
+
+obj-$(CONFIG_SPL_BUILD) += dram.o lowlevel_init.o

arch/arm/cpu/arm926ejs/lpc32xx/clk.c

@@ -98,6 +98,40 @@ unsigned int get_periph_clk_rate(void)
 	return get_hclk_pll_rate() / get_periph_clk_div();
 }
 
+unsigned int get_sdram_clk_rate(void)
+{
+	unsigned int src_clk;
+
+	if (!(readl(&clk->pwr_ctrl) & CLK_PWR_NORMAL_RUN))
+		return get_sys_clk_rate();
+
+	src_clk = get_hclk_pll_rate();
+
+	if (readl(&clk->sdramclk_ctrl) & CLK_SDRAM_DDR_SEL) {
+		/* using DDR */
+		switch (readl(&clk->hclkdiv_ctrl) & CLK_HCLK_DDRAM_MASK) {
+		case CLK_HCLK_DDRAM_HALF:
+			return src_clk/2;
+		case CLK_HCLK_DDRAM_NOMINAL:
+			return src_clk;
+		default:
+			return 0;
+		}
+	} else {
+		/* using SDR */
+		switch (readl(&clk->hclkdiv_ctrl) & CLK_HCLK_ARM_PLL_DIV_MASK) {
+		case CLK_HCLK_ARM_PLL_DIV_4:
+			return src_clk/4;
+		case CLK_HCLK_ARM_PLL_DIV_2:
+			return src_clk/2;
+		case CLK_HCLK_ARM_PLL_DIV_1:
+			return src_clk;
+		default:
+			return 0;
+		}
+	}
+}
+
 int get_serial_clock(void)
 {
 	return get_periph_clk_rate();

arch/arm/cpu/arm926ejs/lpc32xx/cpu.c

@@ -5,9 +5,11 @@
  */
 
 #include <common.h>
+#include <netdev.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/clk.h>
 #include <asm/arch/wdt.h>
+#include <asm/arch/sys_proto.h>
 #include <asm/io.h>
 
 static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
@@ -55,3 +57,11 @@ int print_cpuinfo(void)
 	return 0;
 }
 #endif
+
+#ifdef CONFIG_LPC32XX_ETH
+int cpu_eth_init(bd_t *bis)
+{
+	lpc32xx_eth_initialize(bis);
+	return 0;
+}
+#endif

arch/arm/cpu/arm926ejs/lpc32xx/devices.c

@@ -8,10 +8,13 @@
 #include <asm/arch/cpu.h>
 #include <asm/arch/clk.h>
 #include <asm/arch/uart.h>
+#include <asm/arch/mux.h>
 #include <asm/io.h>
+#include <dm.h>
 
 static struct clk_pm_regs    *clk  = (struct clk_pm_regs *)CLK_PM_BASE;
 static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE;
+static struct mux_regs *mux = (struct mux_regs *)MUX_BASE;
 
 void lpc32xx_uart_init(unsigned int uart_id)
 {
@@ -37,3 +40,43 @@ void lpc32xx_uart_init(unsigned int uart_id)
 	writel(CLK_UART_X_DIV(1) | CLK_UART_Y_DIV(1),
 	       &clk->u3clk + (uart_id - 3));
 }
+
+void lpc32xx_mac_init(void)
+{
+	/* Enable MAC interface */
+	writel(CLK_MAC_REG | CLK_MAC_SLAVE | CLK_MAC_MASTER
+		| CLK_MAC_MII, &clk->macclk_ctrl);
+}
+
+void lpc32xx_mlc_nand_init(void)
+{
+	/* Enable NAND interface */
+	writel(CLK_NAND_MLC | CLK_NAND_MLC_INT, &clk->flashclk_ctrl);
+}
+
+void lpc32xx_i2c_init(unsigned int devnum)
+{
+	/* Enable I2C interface */
+	uint32_t ctrl = readl(&clk->i2cclk_ctrl);
+	if (devnum == 1)
+		ctrl |= CLK_I2C1_ENABLE;
+	if (devnum == 2)
+		ctrl |= CLK_I2C2_ENABLE;
+	writel(ctrl, &clk->i2cclk_ctrl);
+}
+
+U_BOOT_DEVICE(lpc32xx_gpios) = {
+	.name = "gpio_lpc32xx"
+};
+
+/* Mux for SCK0, MISO0, MOSI0. We do not use SSEL0. */
+
+#define P_MUX_SET_SSP0 0x1600
+
+void lpc32xx_ssp_init(void)
+{
+	/* Enable SSP0 interface */
+	writel(CLK_SSP0_ENABLE_CLOCK, &clk->ssp_ctrl);
+	/* Mux SSP0 pins */
+	writel(P_MUX_SET_SSP0, &mux->p_mux_set);
+}

arch/arm/cpu/arm926ejs/lpc32xx/dram.c

@@ -0,0 +1,77 @@
+/*
+ * LPC32xx dram init
+ *
+ * (C) Copyright 2014  DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
+ *
+ * This is called by SPL to gain access to the SDR DRAM.
+ *
+ * This code runs from SRAM.
+ *
+ * Actual CONFIG_LPC32XX_SDRAM_* parameters must be provided
+ * by the board configuration file.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/wdt.h>
+#include <asm/arch/emc.h>
+#include <asm/io.h>
+
+static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
+static struct emc_regs *emc = (struct emc_regs *)EMC_BASE;
+
+void ddr_init(struct emc_dram_settings *dram)
+{
+	uint32_t ck;
+
+	/* Enable EMC interface and choose little endian mode */
+	writel(1, &emc->ctrl);
+	writel(0, &emc->config);
+	/* Select maximum EMC Dynamic Memory Refresh Time */
+	writel(0x7FF, &emc->refresh);
+	/* Determine CLK */
+	ck = get_sdram_clk_rate();
+	/* Configure SDRAM */
+	writel(dram->cmddelay, &clk->sdramclk_ctrl);
+	writel(dram->config0, &emc->config0);
+	writel(dram->rascas0, &emc->rascas0);
+	writel(dram->rdconfig, &emc->read_config);
+	/* Set timings */
+	writel((ck / dram->trp) & 0x0000000F, &emc->t_rp);
+	writel((ck / dram->tras) & 0x0000000F, &emc->t_ras);
+	writel((ck / dram->tsrex) & 0x0000007F, &emc->t_srex);
+	writel((ck / dram->twr) & 0x0000000F, &emc->t_wr);
+	writel((ck / dram->trc) & 0x0000001F, &emc->t_rc);
+	writel((ck / dram->trfc) & 0x0000001F, &emc->t_rfc);
+	writel((ck / dram->txsr) & 0x000000FF, &emc->t_xsr);
+	writel(dram->trrd, &emc->t_rrd);
+	writel(dram->tmrd, &emc->t_mrd);
+	writel(dram->tcdlr, &emc->t_cdlr);
+	/* Dynamic refresh */
+	writel((((ck / dram->refresh) >> 4) & 0x7FF), &emc->refresh);
+	udelay(10);
+	/* Force all clocks, enable inverted ck, issue NOP command */
+	writel(0x00000193, &emc->control);
+	udelay(100);
+	/* Keep all clocks enabled, issue a PRECHARGE ALL command */
+	writel(0x00000113, &emc->control);
+	/* Fast dynamic refresh for at least a few SDRAM ck cycles */
+	writel((((128) >> 4) & 0x7FF), &emc->refresh);
+	udelay(10);
+	/* set correct dynamic refresh timing */
+	writel((((ck / dram->refresh) >> 4) & 0x7FF), &emc->refresh);
+	udelay(10);
+	/* set normal mode to CAS=3 */
+	writel(0x00000093, &emc->control);
+	readl(EMC_DYCS0_BASE | dram->mode);
+	/* set extended mode to all zeroes */
+	writel(0x00000093, &emc->control);
+	readl(EMC_DYCS0_BASE | dram->emode);
+	/* stop forcing clocks, keep inverted clock, issue normal mode */
+	writel(0x00000010, &emc->control);
+}

arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S

@@ -0,0 +1,45 @@
+/*
+ * WORK Microwave work_92105 board low level init
+ *
+ * (C) Copyright 2014  DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
+ *
+ * Low level init is called from SPL to set up the clocks.
+ * On entry, the LPC3250 is in Direct Run mode with all clocks
+ * running at 13 MHz; on exit, ARM clock is 208 MHz, HCLK is
+ * 104 MHz and PCLK is 13 MHz.
+ *
+ * This code must run from SRAM so that the clock changes do
+ * not prevent it from executing.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+.globl lowlevel_init
+
+lowlevel_init:
+
+	/* Set ARM, HCLK, PCLK dividers for normal mode */
+	ldr	r0, =0x0000003D
+	ldr	r1, =0x40004040
+	str	r0, [r1]
+
+	/* Start HCLK PLL for 208 MHz */
+	ldr	r0, =0x0001401E
+	ldr	r1, =0x40004058
+	str	r0, [r1]
+
+	/* wait for HCLK PLL to lock */
+1:
+	ldr	r0, [r1]
+	ands	r0, r0, #1
+	beq	1b
+
+	/* switch to normal mode */
+	ldr	r1, =0x40004044
+	ldr	r0, [r1]
+	orr	r0, #0x00000004
+	str	r0, [r1]
+
+	/* Return to U-boot via saved link register */
+	mov	pc, lr

arch/arm/cpu/arm946es/config.mk

@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS +=  -march=armv4

arch/arm/cpu/armv7/am33xx/ddr.c

@@ -164,9 +164,9 @@ void config_sdram(const struct emif_regs *regs, int nr)
 		writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
 		writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
 	}
-	writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
 	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
 	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
+	writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
 }
 
 /**

arch/arm/cpu/armv7/armada-xp/lowlevel_spl.S

@@ -6,7 +6,7 @@
 #include <linux/linkage.h>
 
 ENTRY(save_boot_params)
-	bx	lr
+	b	save_boot_params_ret
 ENDPROC(save_boot_params)
 
 /*

arch/arm/cpu/armv7/config.mk

@@ -5,11 +5,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-# If armv7-a is not supported by GCC fall-back to armv5, which is
-# supported by more tool-chains
-PF_CPPFLAGS_ARMV7 := $(call cc-option, -march=armv7-a, -march=armv5)
-PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_ARMV7)
-
 # On supported platforms we set the bit which causes us to trap on unaligned
 # memory access.  This is the opposite of what the compiler expects to be
 # the default so we must pass in -mno-unaligned-access so that it is aware

arch/arm/cpu/armv7/exynos/clock.c

@@ -14,7 +14,6 @@
 #define PLL_DIV_1024	1024
 #define PLL_DIV_65535	65535
 #define PLL_DIV_65536	65536
-
 /* *
  * This structure is to store the src bit, div bit and prediv bit
  * positions of the peripheral clocks of the src and div registers
@@ -423,8 +422,8 @@ static unsigned long exynos5_get_periph_rate(int peripheral)
 	case PERIPH_ID_I2C6:
 	case PERIPH_ID_I2C7:
 		src = EXYNOS_SRC_MPLL;
-		div = readl(&clk->div_top0);
-		sub_div = readl(&clk->div_top1);
+		div = readl(&clk->div_top1);
+		sub_div = readl(&clk->div_top0);
 		break;
 	default:
 		debug("%s: invalid peripheral %d", __func__, peripheral);
@@ -1028,6 +1027,40 @@ static unsigned long exynos5420_get_lcd_clk(void)
 	return pclk;
 }
 
+static unsigned long exynos5800_get_lcd_clk(void)
+{
+	struct exynos5420_clock *clk =
+		(struct exynos5420_clock *)samsung_get_base_clock();
+	unsigned long sclk;
+	unsigned int sel;
+	unsigned int ratio;
+
+	/*
+	 * CLK_SRC_DISP10
+	 * CLKMUX_FIMD1 [6:4]
+	 */
+	sel = (readl(&clk->src_disp10) >> 4) & 0x7;
+
+	if (sel) {
+		/*
+		 * Mapping of CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4] values into
+		 * PLLs. The first element is a placeholder to bypass the
+		 * default settig.
+		 */
+		const int reg_map[] = {0, CPLL, DPLL, MPLL, SPLL, IPLL, EPLL,
+									RPLL};
+		sclk = get_pll_clk(reg_map[sel]);
+	} else
+		sclk = CONFIG_SYS_CLK_FREQ;
+	/*
+	 * CLK_DIV_DISP10
+	 * FIMD1_RATIO [3:0]
+	 */
+	ratio = readl(&clk->div_disp10) & 0xf;
+
+	return sclk / (ratio + 1);
+}
+
 void exynos4_set_lcd_clk(void)
 {
 	struct exynos4_clock *clk =
@@ -1159,6 +1192,28 @@ void exynos5420_set_lcd_clk(void)
 	writel(cfg, &clk->div_disp10);
 }
 
+void exynos5800_set_lcd_clk(void)
+{
+	struct exynos5420_clock *clk =
+		(struct exynos5420_clock *)samsung_get_base_clock();
+	unsigned int cfg;
+
+	/*
+	 * Use RPLL for pixel clock
+	 * CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4]
+	 * ==================
+	 * 111: SCLK_RPLL
+	 */
+	cfg = readl(&clk->src_disp10) | (0x7 << 4);
+	writel(cfg, &clk->src_disp10);
+
+	/*
+	 * CLK_DIV_DISP10
+	 * FIMD1_RATIO		[3:0]
+	 */
+	clrsetbits_le32(&clk->div_disp10, 0xf << 0, 0x0 << 0);
+}
+
 void exynos4_set_mipi_clk(void)
 {
 	struct exynos4_clock *clk =
@@ -1646,8 +1701,10 @@ unsigned long get_lcd_clk(void)
 	if (cpu_is_exynos4())
 		return exynos4_get_lcd_clk();
 	else {
-		if (proid_is_exynos5420() || proid_is_exynos5800())
+		if (proid_is_exynos5420())
 			return exynos5420_get_lcd_clk();
+		else if (proid_is_exynos5800())
+			return exynos5800_get_lcd_clk();
 		else
 			return exynos5_get_lcd_clk();
 	}
@@ -1660,8 +1717,10 @@ void set_lcd_clk(void)
 	else {
 		if (proid_is_exynos5250())
 			exynos5_set_lcd_clk();
-		else if (proid_is_exynos5420() || proid_is_exynos5800())
+		else if (proid_is_exynos5420())
 			exynos5420_set_lcd_clk();
+		else
+			exynos5800_set_lcd_clk();
 	}
 }
 

arch/arm/cpu/armv7/exynos/clock_init_exynos5.c

@@ -179,10 +179,10 @@ struct mem_timings mem_timings[] = {
 		.spll_mdiv = 0xc8,
 		.spll_pdiv = 0x3,
 		.spll_sdiv = 0x2,
-		/* RPLL @70.5Mhz */
+		/* RPLL @141Mhz */
 		.rpll_mdiv = 0x5E,
 		.rpll_pdiv = 0x2,
-		.rpll_sdiv = 0x4,
+		.rpll_sdiv = 0x3,
 
 		.direct_cmd_msr = {
 			0x00020018, 0x00030000, 0x00010046, 0x00000d70,

arch/arm/cpu/armv7/mx5/Kconfig

@@ -0,0 +1,27 @@
+if ARCH_MX5
+
+config MX5
+	bool
+	default y
+
+config MX51
+	bool
+
+config MX53
+	bool
+
+choice
+	prompt "MX5 board select"
+
+config TARGET_USBARMORY
+	bool "Support USB armory"
+	select CPU_V7
+
+endchoice
+
+config SYS_SOC
+	default "mx5"
+
+source "board/inversepath/usbarmory/Kconfig"
+
+endif

arch/arm/cpu/armv8/config.mk

@@ -6,7 +6,5 @@
 #
 PLATFORM_RELFLAGS += -fno-common -ffixed-x18
 
-PF_CPPFLAGS_ARMV8 := $(call cc-option, -march=armv8-a)
 PF_NO_UNALIGNED := $(call cc-option, -mstrict-align)
-PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_ARMV8)
 PLATFORM_CPPFLAGS += $(PF_NO_UNALIGNED)

arch/arm/cpu/pxa/config.mk

@@ -6,8 +6,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-PLATFORM_CPPFLAGS += -mcpu=xscale
-
 #
 # !WARNING!
 # The PXA's OneNAND SPL uses .text.0 and .text.1 segments to allow booting from

arch/arm/cpu/sa1100/config.mk

@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2002
-# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
-# Marius Groeger <mgroeger@sysgo.de>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -march=armv4 -mtune=strongarm1100

arch/arm/dts/Makefile

@@ -24,7 +24,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
 	tegra20-trimslice.dtb \
 	tegra20-ventana.dtb \
 	tegra20-whistler.dtb \
-	tegra20-colibri_t20_iris.dtb \
+	tegra20-colibri.dtb \
 	tegra30-apalis.dtb \
 	tegra30-beaver.dtb \
 	tegra30-cardhu.dtb \

arch/arm/dts/exynos5420-peach-pit.dts

@@ -67,6 +67,8 @@
 	        edp-lvds-bridge@48 {
 	                compatible = "parade,ps8625";
 	                reg = <0x48>;
+			sleep-gpio = <&gpx3 5 GPIO_ACTIVE_HIGH>;
+			reset-gpio = <&gpy7 7 GPIO_ACTIVE_HIGH>;
 	        };
 	};
 

arch/arm/dts/exynos54xx.dtsi

@@ -168,6 +168,7 @@
 	fimd@14400000 {
 		/* sysmmu is not used in U-Boot */
 		samsung,disable-sysmmu;
+		samsung,pwm-out-gpio = <&gpb2 0 GPIO_ACTIVE_HIGH>;
 	};
 
 	dp@145b0000 {

arch/arm/dts/exynos5800-peach-pi.dts

@@ -144,10 +144,13 @@
 		samsung,vl-vfpd = <10>;
 		samsung,vl-cmd-allow-len = <0xf>;
 
+		samsung,power-on-delay = <30000>;
 		samsung,winid = <3>;
 		samsung,interface-mode = <1>;
 		samsung,dp-enabled = <1>;
 		samsung,dual-lcd-enabled = <0>;
+
+		samsung,bl-en-gpio = <&gpx2 2 GPIO_ACTIVE_HIGH>;
 	};
 };
 

arch/arm/include/asm/arch-exynos/clk.h

@@ -16,6 +16,9 @@
 #define BPLL	5
 #define RPLL	6
 #define SPLL	7
+#define CPLL	8
+#define DPLL	9
+#define IPLL	10
 
 #define MASK_PRE_RATIO(x)	(0xff << ((x << 4) + 8))
 #define MASK_RATIO(x)		(0xf << (x << 4))

arch/arm/include/asm/arch-lpc32xx/clk.h

@@ -71,6 +71,7 @@ struct clk_pm_regs {
 };
 
 /* HCLK Divider Control Register bits */
+#define CLK_HCLK_DDRAM_MASK		(0x3 << 7)
 #define CLK_HCLK_DDRAM_HALF		(0x2 << 7)
 #define CLK_HCLK_DDRAM_NOMINAL		(0x1 << 7)
 #define CLK_HCLK_DDRAM_STOPPED		(0x0 << 7)
@@ -123,6 +124,10 @@ struct clk_pm_regs {
 #define CLK_MAC_SLAVE			(1 << 1)
 #define CLK_MAC_REG			(1 << 0)
 
+/* I2C Clock Control Register bits	*/
+#define CLK_I2C2_ENABLE			(1 << 1)
+#define CLK_I2C1_ENABLE			(1 << 0)
+
 /* Timer Clock Control1 Register bits */
 #define CLK_TIMCLK_MOTOR		(1 << 6)
 #define CLK_TIMCLK_TIMER3		(1 << 5)
@@ -147,11 +152,22 @@ struct clk_pm_regs {
 /* DMA Clock Control Register bits */
 #define CLK_DMA_ENABLE			(1 << 0)
 
+/* NAND Clock Control Register bits */
+#define CLK_NAND_MLC			(1 << 1)
+#define CLK_NAND_MLC_INT		(1 << 5)
+
+/* SSP Clock Control Register bits */
+#define CLK_SSP0_ENABLE_CLOCK		(1 << 0)
+
+/* SDRAMCLK register bits */
+#define CLK_SDRAM_DDR_SEL		(1 << 1)
+
 unsigned int get_sys_clk_rate(void);
 unsigned int get_hclk_pll_rate(void);
 unsigned int get_hclk_clk_div(void);
 unsigned int get_hclk_clk_rate(void);
 unsigned int get_periph_clk_div(void);
 unsigned int get_periph_clk_rate(void);
+unsigned int get_sdram_clk_rate(void);
 
 #endif /* _LPC32XX_CLK_H */

arch/arm/include/asm/arch-lpc32xx/config.h

@@ -52,6 +52,9 @@
 #define CONFIG_SYS_BAUDRATE_TABLE	\
 		{ 9600, 19200, 38400, 57600, 115200, 230400, 460800 }
 
+/* Ethernet */
+#define LPC32XX_ETH_BASE ETHERNET_BASE
+
 /* NOR Flash */
 #if defined(CONFIG_SYS_FLASH_CFI)
 #define CONFIG_FLASH_CFI_DRIVER

arch/arm/include/asm/arch-lpc32xx/cpu.h

@@ -27,6 +27,7 @@
 #define HS_UART7_BASE	0x4001C000	/* High speed UART 7 registers base */
 #define RTC_BASE	0x40024000	/* RTC registers base               */
 #define GPIO_BASE	0x40028000	/* GPIO registers base              */
+#define MUX_BASE	0x40028100	/* MUX registers base               */
 #define WDT_BASE	0x4003C000	/* Watchdog timer registers base    */
 #define TIMER0_BASE	0x40044000	/* Timer0 registers base            */
 #define TIMER1_BASE	0x4004C000	/* Timer1 registers base            */
@@ -37,6 +38,8 @@
 #define UART4_BASE	0x40088000	/* UART 4 registers base            */
 #define UART5_BASE	0x40090000	/* UART 5 registers base            */
 #define UART6_BASE	0x40098000	/* UART 6 registers base            */
+#define I2C1_BASE	0x400A0000	/* I2C  1 registers base            */
+#define I2C2_BASE	0x400A8000	/* I2C  2 registers base            */
 
 /* External SDRAM Memory Bank base addresses */
 #define EMC_DYCS0_BASE	0x80000000	/* SDRAM DYCS0 base address         */

arch/arm/include/asm/arch-lpc32xx/emc.h

@@ -76,4 +76,25 @@ struct emc_regs {
 #define EMC_STAT_WAITWR(n)		(((n) - 2) & 0x1F)
 #define EMC_STAT_WAITTURN(n)		(((n) - 1) & 0x0F)
 
+/* EMC settings for DRAM */
+struct emc_dram_settings {
+	u32	cmddelay;
+	u32	config0;
+	u32	rascas0;
+	u32	rdconfig;
+	u32	trp;
+	u32	tras;
+	u32	tsrex;
+	u32	twr;
+	u32	trc;
+	u32	trfc;
+	u32	txsr;
+	u32	trrd;
+	u32	tmrd;
+	u32	tcdlr;
+	u32	refresh;
+	u32	mode;
+	u32	emode;
+};
+
 #endif /* _LPC32XX_EMC_H */

arch/arm/include/asm/arch-lpc32xx/gpio.h

@@ -0,0 +1,43 @@
+/*
+ * LPC32xx GPIO interface
+ *
+ * (C) Copyright 2014  DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/**
+ * GPIO Register map for LPC32xx
+ */
+
+struct gpio_regs {
+	u32 p3_inp_state;
+	u32 p3_outp_set;
+	u32 p3_outp_clr;
+	u32 p3_outp_state;
+	/* Watch out! the following are shared between p2 and p3 */
+	u32 p2_p3_dir_set;
+	u32 p2_p3_dir_clr;
+	u32 p2_p3_dir_state;
+	/* Now back to 'one register for one port' */
+	u32 p2_inp_state;
+	u32 p2_outp_set;
+	u32 p2_outp_clr;
+	u32 reserved1[6];
+	u32 p0_inp_state;
+	u32 p0_outp_set;
+	u32 p0_outp_clr;
+	u32 p0_outp_state;
+	u32 p0_dir_set;
+	u32 p0_dir_clr;
+	u32 p0_dir_state;
+	u32 reserved2;
+	u32 p1_inp_state;
+	u32 p1_outp_set;
+	u32 p1_outp_clr;
+	u32 p1_outp_state;
+	u32 p1_dir_set;
+	u32 p1_dir_clr;
+	u32 p1_dir_state;
+};

arch/arm/include/asm/arch-lpc32xx/mux.h

@@ -0,0 +1,18 @@
+/*
+ * LPC32xx MUX interface
+ *
+ * (C) Copyright 2015  DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/**
+ * MUX register map for LPC32xx
+ */
+
+struct mux_regs {
+	u32 p_mux_set;
+	u32 p_mux_clr;
+	u32 p_mux_state;
+};

arch/arm/include/asm/arch-lpc32xx/sys_proto.h

@@ -7,6 +7,14 @@
 #ifndef _LPC32XX_SYS_PROTO_H
 #define _LPC32XX_SYS_PROTO_H
 
-void lpc32xx_uart_init(unsigned int uart_id);
+#include <asm/arch/emc.h>
 
+void lpc32xx_uart_init(unsigned int uart_id);
+void lpc32xx_mac_init(void);
+void lpc32xx_mlc_nand_init(void);
+void lpc32xx_i2c_init(unsigned int devnum);
+void lpc32xx_ssp_init(void);
+#if defined(CONFIG_SPL_BUILD)
+void ddr_init(const struct emc_dram_settings *dram);
+#endif
 #endif /* _LPC32XX_SYS_PROTO_H */

arch/arm/include/asm/arch-tegra/pinmux.h

@@ -170,6 +170,16 @@ void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
 void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
 				int len);
 
+struct pmux_pingrp_desc {
+	u8 funcs[4];
+#if defined(CONFIG_TEGRA20)
+	u8 ctl_id;
+	u8 pull_id;
+#endif /* CONFIG_TEGRA20 */
+};
+
+extern const struct pmux_pingrp_desc *tegra_soc_pingroups;
+
 #ifdef TEGRA_PMX_SOC_HAS_DRVGRPS
 
 #define PMUX_SLWF_MIN	0
@@ -219,14 +229,20 @@ void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config,
 
 #endif /* TEGRA_PMX_SOC_HAS_DRVGRPS */
 
-struct pmux_pingrp_desc {
-	u8 funcs[4];
-#if defined(CONFIG_TEGRA20)
-	u8 ctl_id;
-	u8 pull_id;
-#endif /* CONFIG_TEGRA20 */
+#ifdef TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS
+struct pmux_mipipadctrlgrp_config {
+	u32 grp:16;	/* pin group PMUX_MIPIPADCTRLGRP_x   */
+	u32 func:8;	/* function to assign PMUX_FUNC_... */
 };
 
-extern const struct pmux_pingrp_desc *tegra_soc_pingroups;
+void pinmux_config_mipipadctrlgrp_table(
+	const struct pmux_mipipadctrlgrp_config *config, int len);
+
+struct pmux_mipipadctrlgrp_desc {
+	u8 funcs[2];
+};
+
+extern const struct pmux_mipipadctrlgrp_desc *tegra_soc_mipipadctrl_groups;
+#endif /* TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS */
 
 #endif /* _TEGRA_PINMUX_H_ */

arch/arm/include/asm/arch-tegra124/pinmux.h

@@ -246,6 +246,11 @@ enum pmux_drvgrp {
 	PMUX_DRVGRP_COUNT,
 };
 
+enum pmux_mipipadctrlgrp {
+	PMUX_MIPIPADCTRLGRP_DSI_B,
+	PMUX_MIPIPADCTRLGRP_COUNT,
+};
+
 enum pmux_func {
 	PMUX_FUNC_DEFAULT,
 	PMUX_FUNC_BLINK,
@@ -255,6 +260,7 @@ enum pmux_func {
 	PMUX_FUNC_CLK,
 	PMUX_FUNC_CLK12,
 	PMUX_FUNC_CPU,
+	PMUX_FUNC_CSI,
 	PMUX_FUNC_DAP,
 	PMUX_FUNC_DAP1,
 	PMUX_FUNC_DAP2,
@@ -263,6 +269,7 @@ enum pmux_func {
 	PMUX_FUNC_DISPLAYA_ALT,
 	PMUX_FUNC_DISPLAYB,
 	PMUX_FUNC_DP,
+	PMUX_FUNC_DSI_B,
 	PMUX_FUNC_DTV,
 	PMUX_FUNC_EXTPERIPH1,
 	PMUX_FUNC_EXTPERIPH2,
@@ -336,8 +343,10 @@ enum pmux_func {
 };
 
 #define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868
+#define TEGRA_PMX_SOC_MIPIPADCTRL_BASE_REG 0x820
 #define TEGRA_PMX_SOC_HAS_IO_CLAMPING
 #define TEGRA_PMX_SOC_HAS_DRVGRPS
+#define TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS
 #define TEGRA_PMX_GRPS_HAVE_LPMD
 #define TEGRA_PMX_GRPS_HAVE_SCHMT
 #define TEGRA_PMX_GRPS_HAVE_HSM

arch/arm/include/asm/config.h

@@ -7,10 +7,6 @@
 #ifndef _ASM_CONFIG_H_
 #define _ASM_CONFIG_H_
 
-#ifdef __aarch64__
-#define CONFIG_SYS_GENERIC_GLOBAL_DATA
-#endif
-
 #define CONFIG_LMB
 #define CONFIG_SYS_BOOT_RAMDISK_HIGH
 

arch/arm/include/asm/mach-types.h

@@ -936,7 +936,7 @@ extern unsigned int __machine_arch_type;
 #define MACH_TYPE_CWME9210             3320
 #define MACH_TYPE_CWME9210JS           3321
 #define MACH_TYPE_PGS_SITARA           3322
-#define MACH_TYPE_COLIBRI_TEGRA2       3323
+#define MACH_TYPE_COLIBRI_T20          3323
 #define MACH_TYPE_W21                  3324
 #define MACH_TYPE_POLYSAT1             3325
 #define MACH_TYPE_DATAWAY              3326
@@ -12197,16 +12197,16 @@ extern unsigned int __machine_arch_type;
 # define machine_is_pgs_v1()	(0)
 #endif
 
-#ifdef CONFIG_MACH_COLIBRI_TEGRA2
+#ifdef CONFIG_MACH_COLIBRI_T20
 # ifdef machine_arch_type
 #  undef machine_arch_type
 #  define machine_arch_type	__machine_arch_type
 # else
-#  define machine_arch_type	MACH_TYPE_COLIBRI_TEGRA2
+#  define machine_arch_type	MACH_TYPE_COLIBRI_T20
 # endif
-# define machine_is_colibri_tegra2()	(machine_arch_type == MACH_TYPE_COLIBRI_TEGRA2)
+# define machine_is_colibri_t20()	(machine_arch_type == MACH_TYPE_COLIBRI_T20)
 #else
-# define machine_is_colibri_tegra2()	(0)
+# define machine_is_colibri_t20()	(0)
 #endif
 
 #ifdef CONFIG_MACH_W21

arch/arm/include/asm/u-boot.h

@@ -49,4 +49,8 @@ typedef struct bd_info {
 #define IH_ARCH_DEFAULT IH_ARCH_ARM64
 #endif
 
+#if defined(CONFIG_USE_PRIVATE_LIBGCC) && defined(CONFIG_SYS_THUMB_BUILD)
+#error Thumb build does not work with private libgcc.
+#endif
+
 #endif	/* _U_BOOT_H_ */

arch/arm/lib/crt0_64.S

@@ -62,9 +62,18 @@ ENTRY(_main)
  * Set up initial C runtime environment and call board_init_f(0).
  */
 	ldr	x0, =(CONFIG_SYS_INIT_SP_ADDR)
-	sub	x0, x0, #GD_SIZE	/* allocate one GD above SP */
+	sub	x18, x0, #GD_SIZE	/* allocate one GD above SP */
+	bic	x18, x18, #0x7		/* 8-byte alignment for GD */
+zero_gd:
+	sub	x0, x0, #0x8
+	str	xzr, [x0]
+	cmp	x0, x18
+	b.gt	zero_gd
+#if defined(CONFIG_SYS_MALLOC_F_LEN)
+	sub	x0, x18, #CONFIG_SYS_MALLOC_F_LEN
+	str	x0, [x18, #GD_MALLOC_BASE]
+#endif
 	bic	sp, x0, #0xf	/* 16-byte alignment for ABI compliance */
-	mov	x18, sp			/* GD is above SP */
 	mov	x0, #0
 	bl	board_init_f
 

arch/arm/mach-bcm283x/include/mach/mbox.h

@@ -132,7 +132,7 @@ struct bcm2835_mbox_tag_hdr {
  * 0x2..0xf from:
  * http://raspberryalphaomega.org.uk/2013/02/06/automatic-raspberry-pi-board-revision-detection-model-a-b1-and-b2/
  * http://www.raspberrypi.org/forums/viewtopic.php?f=63&t=32733
- * 0x10, 0x11 from swarren's testing
+ * http://git.drogon.net/?p=wiringPi;a=blob_plain;f=wiringPi/wiringPi.c;hb=5edd177112c99416f68ba3e8c6c4db6ed942e796
  */
 #define BCM2835_BOARD_REV_B_I2C0_2	0x2
 #define BCM2835_BOARD_REV_B_I2C0_3	0x3
@@ -148,6 +148,8 @@ struct bcm2835_mbox_tag_hdr {
 #define BCM2835_BOARD_REV_B_PLUS	0x10
 #define BCM2835_BOARD_REV_CM		0x11
 #define BCM2835_BOARD_REV_A_PLUS	0x12
+#define BCM2835_BOARD_REV_B_PLUS_13	0x13
+#define BCM2835_BOARD_REV_CM_14		0x14
 #endif
 
 struct bcm2835_mbox_tag_get_board_rev {

arch/arm/mach-tegra/pinmux-common.c

@@ -108,6 +108,8 @@
 
 #define DRV_REG(group)	_R(TEGRA_PMX_SOC_DRV_GROUP_BASE_REG + ((group) * 4))
 
+#define MIPIPADCTRL_REG(group)	_R(TEGRA_PMX_SOC_MIPIPADCTRL_BASE_REG + ((group) * 4))
+
 /*
  * We could force arch-tegraNN/pinmux.h to define all of these. However,
  * that's a lot of defines, and for now it's manageable to just put a
@@ -695,4 +697,59 @@ void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config,
 	for (i = 0; i < len; i++)
 		pinmux_config_drvgrp(&config[i]);
 }
-#endif /* TEGRA_PMX_HAS_DRVGRPS */
+#endif /* TEGRA_PMX_SOC_HAS_DRVGRPS */
+
+#ifdef TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS
+
+#define pmux_mipipadctrlgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PMUX_MIPIPADCTRLGRP_COUNT))
+
+static void pinmux_mipipadctrl_set_func(enum pmux_mipipadctrlgrp grp,
+	enum pmux_func func)
+{
+	u32 *reg = MIPIPADCTRL_REG(grp);
+	int i, mux = -1;
+	u32 val;
+
+	if (func == PMUX_FUNC_DEFAULT)
+		return;
+
+	/* Error check grp and func */
+	assert(pmux_mipipadctrlgrp_isvalid(grp));
+	assert(pmux_func_isvalid(func));
+
+	if (func >= PMUX_FUNC_RSVD1) {
+		mux = (func - PMUX_FUNC_RSVD1) & 1;
+	} else {
+		/* Search for the appropriate function */
+		for (i = 0; i < 2; i++) {
+			if (tegra_soc_mipipadctrl_groups[grp].funcs[i]
+			    == func) {
+				mux = i;
+				break;
+			}
+		}
+	}
+	assert(mux != -1);
+
+	val = readl(reg);
+	val &= ~(1 << 1);
+	val |= (mux << 1);
+	writel(val, reg);
+}
+
+static void pinmux_config_mipipadctrlgrp(const struct pmux_mipipadctrlgrp_config *config)
+{
+	enum pmux_mipipadctrlgrp grp = config->grp;
+
+	pinmux_mipipadctrl_set_func(grp, config->func);
+}
+
+void pinmux_config_mipipadctrlgrp_table(
+	const struct pmux_mipipadctrlgrp_config *config, int len)
+{
+	int i;
+
+	for (i = 0; i < len; i++)
+		pinmux_config_mipipadctrlgrp(&config[i]);
+}
+#endif /* TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS */

arch/arm/mach-tegra/tegra124/pinmux.c

@@ -304,3 +304,20 @@ static const struct pmux_pingrp_desc tegra124_pingroups[] = {
 	PIN(DP_HPD_PFF0,            DP,         RSVD2,    RSVD3,        RSVD4),
 };
 const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra124_pingroups;
+
+#define MIPIPADCTRL_GRP(grp, f0, f1)	\
+	{				\
+		.funcs = {		\
+			PMUX_FUNC_##f0,	\
+			PMUX_FUNC_##f1,	\
+		},			\
+	}
+
+#define MIPIPADCTRL_RESERVED {}
+
+static const struct pmux_mipipadctrlgrp_desc tegra124_mipipadctrl_groups[] = {
+	/*              pin,   f0,  f1 */
+	/* Offset 0x820 */
+	MIPIPADCTRL_GRP(DSI_B, CSI, DSI_B),
+};
+const struct pmux_mipipadctrlgrp_desc *tegra_soc_mipipadctrl_groups = tegra124_mipipadctrl_groups;

arch/arm/mach-tegra/tegra20/Kconfig

@@ -30,7 +30,7 @@ config TARGET_VENTANA
 config TARGET_WHISTLER
 	bool "NVIDIA Tegra20 Whistler evaluation board"
 
-config TARGET_COLIBRI_T20_IRIS
+config TARGET_COLIBRI_T20
 	bool "Toradex Colibri T20 board"
 
 endchoice
@@ -47,6 +47,6 @@ source "board/avionic-design/tec/Kconfig"
 source "board/compulab/trimslice/Kconfig"
 source "board/nvidia/ventana/Kconfig"
 source "board/nvidia/whistler/Kconfig"
-source "board/toradex/colibri_t20_iris/Kconfig"
+source "board/toradex/colibri_t20/Kconfig"
 
 endif

arch/arm/mach-tegra/tegra20/funcmux.c

@@ -252,12 +252,14 @@ int funcmux_select(enum periph_id id, int config)
 			break;
 		case FUNCMUX_NDFLASH_KBC_8_BIT:
 			pinmux_set_func(PMUX_PINGRP_KBCA, PMUX_FUNC_NAND);
+			pinmux_set_func(PMUX_PINGRP_KBCB, PMUX_FUNC_NAND);
 			pinmux_set_func(PMUX_PINGRP_KBCC, PMUX_FUNC_NAND);
 			pinmux_set_func(PMUX_PINGRP_KBCD, PMUX_FUNC_NAND);
 			pinmux_set_func(PMUX_PINGRP_KBCE, PMUX_FUNC_NAND);
 			pinmux_set_func(PMUX_PINGRP_KBCF, PMUX_FUNC_NAND);
 
 			pinmux_tristate_disable(PMUX_PINGRP_KBCA);
+			pinmux_tristate_disable(PMUX_PINGRP_KBCB);
 			pinmux_tristate_disable(PMUX_PINGRP_KBCC);
 			pinmux_tristate_disable(PMUX_PINGRP_KBCD);
 			pinmux_tristate_disable(PMUX_PINGRP_KBCE);

arch/nios2/cpu/fdt.c

@@ -34,7 +34,5 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 	 * Note: aliases in the dts are required for this
 	 */
 	fdt_fixup_ethernet(blob);
-
-	return 0;
 }
 #endif /* CONFIG_OF_LIBFDT && CONFIG_OF_BOARD_SETUP */

board/armltd/vexpress64/vexpress64.c

@@ -11,9 +11,22 @@
 #include <netdev.h>
 #include <asm/io.h>
 #include <linux/compiler.h>
+#include <dm/platdata.h>
+#include <dm/platform_data/serial_pl01x.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static const struct pl01x_serial_platdata serial_platdata = {
+	.base = V2M_UART0,
+	.type = TYPE_PL011,
+	.clock = 2400 * 1000,
+};
+
+U_BOOT_DEVICE(vexpress_serials) = {
+	.name = "serial_pl01x",
+	.platdata = &serial_platdata,
+};
+
 int board_init(void)
 {
 	return 0;

board/freescale/mx53loco/mx53loco.c

@@ -389,7 +389,6 @@ int board_late_init(void)
 {
 	if (!power_init())
 		clock_1GHz();
-	print_cpuinfo();
 
 	return 0;
 }

board/htkw/mcx/MAINTAINERS

@@ -1,5 +1,5 @@
 MCX BOARD
-M:	Ilya Yanok <yanok@emcraft.com>
+M:	Anatolij Gustschin <agust@denx.de>
 S:	Maintained
 F:	board/htkw/mcx/
 F:	include/configs/mcx.h

board/inversepath/usbarmory/Kconfig

@@ -0,0 +1,15 @@
+if TARGET_USBARMORY
+
+config IMX_CONFIG
+	default "board/inversepath/usbarmory/imximage.cfg"
+
+config SYS_BOARD
+	default "usbarmory"
+
+config SYS_VENDOR
+	default "inversepath"
+
+config SYS_CONFIG_NAME
+	default "usbarmory"
+
+endif

board/inversepath/usbarmory/MAINTAINERS

@@ -0,0 +1,6 @@
+USBARMORY BOARD
+M:	Andrej Rosano <andrej@inversepath.com>
+S:	Maintained
+F:	board/inversepath/usbarmory/
+F:	include/configs/usbarmory.h
+F:	configs/usbarmory_defconfig

board/inversepath/usbarmory/Makefile

@@ -0,0 +1,10 @@
+#
+# USB armory MkI board Makefile
+# http://inversepath.com/usbarmory
+#
+# Copyright (C) 2015, Inverse Path
+# Andrej Rosano <andrej@inversepath.com>
+#
+# SPDX-License-Identifier:|____GPL-2.0+
+
+obj-y	:= usbarmory.o

board/inversepath/usbarmory/imximage.cfg

@@ -0,0 +1,82 @@
+/*
+ * USB armory MkI board imximage configuration
+ * http://inversepath.com/usbarmory
+ *
+ * Copyright (C) 2015, Inverse Path
+ * Andrej Rosano <andrej@inversepath.com>
+ *
+ * SPDX-License-Identifier:|____GPL-2.0+
+ */
+
+IMAGE_VERSION 2
+BOOT_FROM sd
+
+
+/* IOMUX */
+
+DATA 4 0x53fa86f4 0x00000000 /* GRP_DDRMODE_CTL */
+DATA 4 0x53fa8714 0x00000000 /* GRP_DDRMODE     */
+DATA 4 0x53fa86fc 0x00000000 /* GRP_DDRPKE      */
+DATA 4 0x53fa8724 0x04000000 /* GRP_DDR_TYPE    */
+
+DATA 4 0x53fa872c 0x00300000 /* GRP_B3DS   */
+DATA 4 0x53fa8554 0x00300000 /* DRAM_DQM3  */
+DATA 4 0x53fa8558 0x00300040 /* DRAM_SDQS3 */
+
+DATA 4 0x53fa8728 0x00300000 /* GRP_B2DS   */
+DATA 4 0x53fa8560 0x00300000 /* DRAM_DQM2  */
+DATA 4 0x53fa8568 0x00300040 /* DRAM_SDQS2 */
+
+DATA 4 0x53fa871c 0x00300000 /* GRP_B1DS   */
+DATA 4 0x53fa8594 0x00300000 /* DRAM_DQM1  */
+DATA 4 0x53fa8590 0x00300040 /* DRAM_SDQS1 */
+
+DATA 4 0x53fa8718 0x00300000 /* GRP_B0DS   */
+DATA 4 0x53fa8584 0x00300000 /* DRAM_DQM0  */
+DATA 4 0x53fa857c 0x00300040 /* DRAM_SDQS0 */
+
+DATA 4 0x53fa8578 0x00300000 /* DRAM_SDCLK0 */
+DATA 4 0x53fa8570 0x00300000 /* DRAM_SDCLK1 */
+
+DATA 4 0x53fa8574 0x00300000 /* DRAM_CAS  */
+DATA 4 0x53fa8588 0x00300000 /* DRAM_RAS  */
+DATA 4 0x53fa86f0 0x00300000 /* GRP_ADDS  */
+DATA 4 0x53fa8720 0x00300000 /* GRP_CTLDS */
+
+DATA 4 0x53fa8564 0x00300040 /* DRAM_SDODT1 */
+DATA 4 0x53fa8580 0x00300040 /* DRAM_SDODT0 */
+
+
+/* ESDCTL */
+
+DATA 4 0x63fd9000 0x84180000 /* ESDCTL_ESDCTL  */
+
+DATA 4 0x63fd9004 0x0002002d /* ESDCTL_ESDPTC  */
+DATA 4 0x63fd9008 0x12273030 /* ESDCTL_ESDOTC  */
+DATA 4 0x63fd900c 0x9f5152e3 /* ESDCTL_ESDCFG0 */
+DATA 4 0x63fd9010 0xb68e8a63 /* ESDCTL_ESDCFG1 */
+DATA 4 0x63fd9014 0x01ff00db /* ESDCTL_ESDCFG2 */
+DATA 4 0x63fd9018 0x00011740 /* ESDCTL_ESDMISC */
+
+DATA 4 0x63fd901c 0x00008032 /* ESDCTL_ESDSCR  */
+DATA 4 0x63fd901c 0x00008033
+DATA 4 0x63fd901c 0x00028031
+DATA 4 0x63fd901c 0x052080b0
+DATA 4 0x63fd901c 0x04008040
+DATA 4 0x63fd901c 0x0000803a
+DATA 4 0x63fd901c 0x0000803b
+DATA 4 0x63fd901c 0x00028039
+DATA 4 0x63fd901c 0x05208138
+DATA 4 0x63fd901c 0x04008048
+DATA 4 0x63fd901c 0x00000000
+
+DATA 4 0x63fd9020 0x00005800 /* ESDCTL_ESDREF   */
+DATA 4 0x63fd902c 0x000026d2 /* ESDCTL_ESDEWD   */
+DATA 4 0x63fd9030 0x009f0e21 /* ESDCTL_ESDOR    */
+DATA 4 0x63fd9040 0x05380003 /* ESDCTL_ZQHWCTRL */
+DATA 4 0x63fd9058 0x00022227 /* ESDCTL_ODTCTRL  */
+
+DATA 4 0x63fd907c 0x01370138 /* ESDCTL_DGCTRL0  */
+DATA 4 0x63fd9080 0x013b013c /* ESDCTL_DGCTRL1  */
+DATA 4 0x63fd9088 0x35343535 /* ESDCTL_RDDLCTL  */
+DATA 4 0x63fd9090 0x4d444c44 /* ESDCTL_WRDLCTL  */

board/inversepath/usbarmory/usbarmory.c

@@ -0,0 +1,417 @@
+/*
+ * USB armory MkI board initialization
+ * http://inversepath.com/usbarmory
+ *
+ * Copyright (C) 2015, Inverse Path
+ * Andrej Rosano <andrej@inversepath.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux-mx53.h>
+#include <asm/errno.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <asm/gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 get_board_rev(void)
+{
+	struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
+	struct fuse_bank *bank = &iim->bank[0];
+	struct fuse_bank0_regs *fuse =
+		(struct fuse_bank0_regs *)bank->fuse_regs;
+
+	int rev = readl(&fuse->gp[6]);
+
+	return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
+}
+
+struct fsl_esdhc_cfg esdhc_cfg[1] = {
+	{MMC_SDHC1_BASE_ADDR}
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	/* CD not present */
+	return 1;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	int ret = 0;
+
+	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+	ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
+
+	return ret;
+}
+
+#define SD_CMD_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+			PAD_CTL_PUS_100K_UP)
+#define I2C_PAD_CTRL	(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
+			PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
+#define PAD_CTRL_UP	PAD_CTL_PUS_100K_UP
+#define PAD_CTRL_GND	PAD_CTL_PUS_100K_DOWN
+
+static void setup_iomux_sd(void)
+{
+	static const iomux_v3_cfg_t pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, MX53_SDHC_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
+			     MX53_SDHC_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
+			     MX53_SDHC_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
+			     MX53_SDHC_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
+			     MX53_SDHC_PAD_CTRL),
+		MX53_PAD_EIM_DA13__GPIO3_13,
+	};
+
+	imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads));
+}
+
+static void setup_iomux_led(void)
+{
+	static const iomux_v3_cfg_t pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_DISP0_DAT6__GPIO4_27,
+			     PAD_CTL_PUS_100K_DOWN),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads));
+}
+
+static void setup_iomux_i2c(void)
+{
+	static const iomux_v3_cfg_t pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_EIM_D28__I2C1_SDA, I2C_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D21__I2C1_SCL, I2C_PAD_CTRL),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads));
+}
+
+static void setup_iomux_pinheader(void)
+{
+	static const iomux_v3_cfg_t pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__GPIO5_26, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__GPIO5_27, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
+			     MX53_UART_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
+			     MX53_UART_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT12__GPIO5_30, PAD_CTRL_UP),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads));
+}
+
+static void setup_iomux_unused_boot(void)
+{
+	static const iomux_v3_cfg_t pads[] = {
+		/* Pulled-up pads */
+		NEW_PAD_CTRL(MX53_PAD_EIM_A21__GPIO2_17, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA0__GPIO3_0, PAD_CTRL_UP),
+
+		/* Grounded pads */
+		NEW_PAD_CTRL(MX53_PAD_EIM_LBA__GPIO2_27, PAD_CTRL_GND),
+		NEW_PAD_CTRL(MX53_PAD_EIM_EB0__GPIO2_28, PAD_CTRL_GND),
+		NEW_PAD_CTRL(MX53_PAD_EIM_EB1__GPIO2_29, PAD_CTRL_GND),
+		NEW_PAD_CTRL(MX53_PAD_EIM_A16__GPIO2_22, PAD_CTRL_GND),
+		NEW_PAD_CTRL(MX53_PAD_EIM_A17__GPIO2_21, PAD_CTRL_GND),
+		NEW_PAD_CTRL(MX53_PAD_EIM_A18__GPIO2_20, PAD_CTRL_GND),
+		NEW_PAD_CTRL(MX53_PAD_EIM_A19__GPIO2_19, PAD_CTRL_GND),
+		NEW_PAD_CTRL(MX53_PAD_EIM_A20__GPIO2_18, PAD_CTRL_GND),
+		NEW_PAD_CTRL(MX53_PAD_EIM_A22__GPIO2_16, PAD_CTRL_GND),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA1__GPIO3_1, PAD_CTRL_GND),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA2__GPIO3_2, PAD_CTRL_GND),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA3__GPIO3_3, PAD_CTRL_GND),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA4__GPIO3_4, PAD_CTRL_GND),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA5__GPIO3_5, PAD_CTRL_GND),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA6__GPIO3_6, PAD_CTRL_GND),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA7__GPIO3_7, PAD_CTRL_GND),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA8__GPIO3_8, PAD_CTRL_GND),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA9__GPIO3_9, PAD_CTRL_GND),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA10__GPIO3_10, PAD_CTRL_GND),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads));
+}
+
+static void setup_iomux_unused_nc(void)
+{
+	/* Out of reset values define the pin values before the
+	   ROM is executed so we force all the not connected pins
+	   to a known state */
+	static const iomux_v3_cfg_t pads[] = {
+		/* CONTROL PINS block */
+		NEW_PAD_CTRL(MX53_PAD_GPIO_0__GPIO1_0, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_GPIO_1__GPIO1_1, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_GPIO_2__GPIO1_2, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_GPIO_3__GPIO1_3, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_GPIO_4__GPIO1_4, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_GPIO_5__GPIO1_5, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_GPIO_6__GPIO1_6, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_GPIO_7__GPIO1_7, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_GPIO_8__GPIO1_8, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_GPIO_9__GPIO1_9, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_GPIO_10__GPIO4_0, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_GPIO_11__GPIO4_1, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_GPIO_12__GPIO4_2, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_GPIO_13__GPIO4_3, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_GPIO_14__GPIO4_4, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_GPIO_16__GPIO7_11, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_GPIO_17__GPIO7_12, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_GPIO_18__GPIO7_13, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_GPIO_19__GPIO4_5, PAD_CTRL_UP),
+
+		/* EIM block */
+		NEW_PAD_CTRL(MX53_PAD_EIM_OE__GPIO2_25, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_EIM_WAIT__GPIO5_0, PAD_CTRL_UP),
+		/* EIM_LBA: setup_iomux_unused_boot() */
+		NEW_PAD_CTRL(MX53_PAD_EIM_RW__GPIO2_26, PAD_CTRL_UP),
+		/* EIM_EB0: setup_iomux_unused_boot() */
+		/* EIM_EB1: setup_iomux_unused_boot() */
+		NEW_PAD_CTRL(MX53_PAD_EIM_EB2__GPIO2_30, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_EIM_EB3__GPIO2_31, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_EIM_CS0__GPIO2_23, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_EIM_CS1__GPIO2_24, PAD_CTRL_UP),
+		/* EIM_A16: setup_iomux_unused_boot() */
+		/* EIM_A17: setup_iomux_unused_boot() */
+		/* EIM_A18: setup_iomux_unused_boot() */
+		/* EIM_A19: setup_iomux_unused_boot() */
+		/* EIM_A20: setup_iomux_unused_boot() */
+		/* EIM_A21: setup_iomux_unused_boot() */
+		/* EIM_A22: setup_iomux_unused_boot() */
+		NEW_PAD_CTRL(MX53_PAD_EIM_A23__GPIO6_6, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_EIM_A24__GPIO5_4, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_EIM_A25__GPIO5_2, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D16__GPIO3_16, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D17__GPIO3_17, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D18__GPIO3_18, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D19__GPIO3_19, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D20__GPIO3_20, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D21__GPIO3_21, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D22__GPIO3_22, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D23__GPIO3_23, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D24__GPIO3_24, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D25__GPIO3_25, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D26__GPIO3_26, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D27__GPIO3_27, PAD_CTRL_UP),
+		/* EIM_D28: setup_iomux_unused_boot() */
+		/* EIM_D29: setup_iomux_unused_boot() */
+		NEW_PAD_CTRL(MX53_PAD_EIM_D30__GPIO3_30, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D31__GPIO3_31, PAD_CTRL_UP),
+		/* EIM_DA0: setup_iomux_unused_boot() */
+		/* EIM_DA1: setup_iomux_unused_boot() */
+		/* EIM_DA2: setup_iomux_unused_boot() */
+		/* EIM_DA3: setup_iomux_unused_boot() */
+		/* EIM_DA4: setup_iomux_unused_boot() */
+		/* EIM_DA5: setup_iomux_unused_boot() */
+		/* EIM_DA6: setup_iomux_unused_boot() */
+		/* EIM_DA7: setup_iomux_unused_boot() */
+		/* EIM_DA8: setup_iomux_unused_boot() */
+		/* EIM_DA9: setup_iomux_unused_boot() */
+		/* EIM_DA10: setup_iomux_unused_boot() */
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA11__GPIO3_11, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA12__GPIO3_12, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA13__GPIO3_13, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA14__GPIO3_14, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA15__GPIO3_15, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__GPIO6_12, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__GPIO6_13, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__GPIO6_8, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__GPIO6_7, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__GPIO6_9, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__GPIO6_10, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__GPIO6_11, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_NANDF_CS1__GPIO6_14, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_NANDF_CS2__GPIO6_15, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_NANDF_CS3__GPIO6_16, PAD_CTRL_UP),
+
+		/* MISC block */
+		NEW_PAD_CTRL(MX53_PAD_FEC_MDC__GPIO1_31, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__GPIO1_22, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__GPIO1_25, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__GPIO1_23, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__GPIO1_24, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__GPIO1_28, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__GPIO1_27, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__GPIO1_26, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__GPIO1_30, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__GPIO1_29, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_KEY_COL0__GPIO4_6, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_KEY_ROW0__GPIO4_7, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_KEY_COL1__GPIO4_8, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__GPIO4_9, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_KEY_COL2__GPIO4_10, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__GPIO4_11, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_KEY_COL3__GPIO4_12, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_KEY_ROW3__GPIO4_13, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_KEY_COL4__GPIO4_14, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_KEY_ROW4__GPIO4_15, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_SD2_CMD__GPIO1_11, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_SD2_CLK__GPIO1_10, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_SD2_DATA0__GPIO1_15, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_SD2_DATA1__GPIO1_14, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_SD2_DATA2__GPIO1_13, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_SD2_DATA3__GPIO1_12, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_BUFFER_EN__GPIO7_1, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_CS_0__GPIO7_9, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_CS_1__GPIO7_10, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DA_0__GPIO7_6, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DA_1__GPIO7_7, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DA_2__GPIO7_8, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__GPIO2_0, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__GPIO2_1, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__GPIO2_2, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__GPIO2_3, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA4__GPIO2_4, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA5__GPIO2_5, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA6__GPIO2_6, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA7__GPIO2_7, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__GPIO2_8, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__GPIO2_9, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__GPIO2_10, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__GPIO2_11, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA12__GPIO2_12, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA13__GPIO2_13, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA14__GPIO2_14, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA15__GPIO2_15, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DIOR__GPIO7_3, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DIOW__GPIO6_17, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DMACK__GPIO6_18, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DMARQ__GPIO7_0, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_INTRQ__GPIO7_2, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__GPIO7_5, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__GPIO7_4, PAD_CTRL_UP),
+
+		/* IPU block */
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT4__GPIO5_22, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT5__GPIO5_23, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT6__GPIO5_24, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT7__GPIO5_25, PAD_CTRL_UP),
+		/* CSI0_DAT8: setup_iomux_pinheader() */
+		/* CSI0_DAT9: setup_iomux_pinheader() */
+		/* CSI0_DAT10: setup_iomux_pinheader() */
+		/* CSI0_DAT11: setup_iomux_pinheader() */
+		/* CSI0_DAT12: setup_iomux_pinheader() */
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT13__GPIO5_31, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT14__GPIO6_0, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT15__GPIO6_1, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT16__GPIO6_2, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT17__GPIO6_3, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT18__GPIO6_4, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT19__GPIO6_5, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_CSI0_VSYNC__GPIO5_21, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_CSI0_PIXCLK__GPIO5_18, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_CSI0_MCLK__GPIO5_19, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DATA_EN__GPIO5_20, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_DI0_PIN2__GPIO4_18, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_DI0_PIN3__GPIO4_19, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_DI0_PIN4__GPIO4_20, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_DI0_PIN15__GPIO4_17, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_DISP0_DAT0__GPIO4_21, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_DISP0_DAT1__GPIO4_22, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_DISP0_DAT2__GPIO4_23, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_DISP0_DAT3__GPIO4_24, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_DISP0_DAT4__GPIO4_25, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_DISP0_DAT5__GPIO4_26, PAD_CTRL_UP),
+		/* DISP0_DAT6: setup_iomux_led() */
+		NEW_PAD_CTRL(MX53_PAD_DISP0_DAT7__GPIO4_28, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_DISP0_DAT8__GPIO4_29, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_DISP0_DAT9__GPIO4_30, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_DISP0_DAT10__GPIO4_31, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_DISP0_DAT11__GPIO5_5, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_DISP0_DAT12__GPIO5_6, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_DISP0_DAT13__GPIO5_7, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_DISP0_DAT14__GPIO5_8, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_DISP0_DAT15__GPIO5_9, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_DISP0_DAT16__GPIO5_10, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_DISP0_DAT17__GPIO5_11, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_DISP0_DAT18__GPIO5_12, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_DISP0_DAT19__GPIO5_13, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_DISP0_DAT20__GPIO5_14, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_DISP0_DAT21__GPIO5_15, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_DISP0_DAT22__GPIO5_16, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_DISP0_DAT23__GPIO5_17, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_DI0_DISP_CLK__GPIO4_16, PAD_CTRL_UP),
+
+		/* LVDS block */
+		NEW_PAD_CTRL(MX53_PAD_LVDS0_TX0_P__GPIO7_30, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_LVDS0_TX1_P__GPIO7_28, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_LVDS0_TX2_P__GPIO7_26, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_LVDS0_TX3_P__GPIO7_22, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_LVDS1_TX0_P__GPIO6_30, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_LVDS1_TX1_P__GPIO6_28, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_LVDS1_TX2_P__GPIO6_24, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_LVDS1_TX3_P__GPIO6_22, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_LVDS0_CLK_P__GPIO7_24, PAD_CTRL_UP),
+		NEW_PAD_CTRL(MX53_PAD_LVDS1_CLK_P__GPIO6_26, PAD_CTRL_UP),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads));
+}
+
+#define CPU_CLOCK 800
+
+static void set_clock(void)
+{
+	u32 ref_clk = MXC_HCLK;
+	const uint32_t cpuclk = CPU_CLOCK;
+	const uint32_t dramclk = 400;
+	int ret;
+
+	ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK);
+	if (ret)
+		printf("CPU:   Switch CPU clock to %dMHZ failed\n", cpuclk);
+
+	ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK);
+	if (ret)
+		printf("CPU:   Switch peripheral clock to %dMHz failed\n",
+		       dramclk);
+
+	ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK);
+	if (ret)
+		printf("CPU:   Switch DDR clock to %dMHz failed\n", dramclk);
+}
+
+int board_early_init_f(void)
+{
+	setup_iomux_unused_nc();
+	setup_iomux_unused_boot();
+	setup_iomux_sd();
+	setup_iomux_led();
+	setup_iomux_pinheader();
+	set_clock();
+	return 0;
+}
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+	setup_iomux_i2c();
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 1 << 30);
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: Inverse Path USB armory MkI\n");
+	return 0;
+}

board/nvidia/seaboard/seaboard.c

@@ -20,7 +20,7 @@
 void gpio_early_init_uart(void)
 {
 	/* Enable UART via GPIO_PI3 (port 8, bit 3) so serial console works */
-	gpio_request(GPIO_PI3, NULL);
+	gpio_request(GPIO_PI3, "uart_en");
 	gpio_direction_output(GPIO_PI3, 0);
 }
 #endif

board/raspberrypi/rpi/rpi.c

@@ -165,6 +165,16 @@ static const struct {
 		"bcm2835-rpi-a-plus.dtb",
 		false,
 	},
+	[BCM2835_BOARD_REV_B_PLUS_13] = {
+		"Model B+",
+		"bcm2835-rpi-b-plus.dtb",
+		true,
+	},
+	[BCM2835_BOARD_REV_CM_14] = {
+		"Compute Module",
+		"bcm2835-rpi-cm.dtb",
+		false,
+	},
 #endif
 };
 

board/samsung/smdk5420/MAINTAINERS

@@ -8,3 +8,9 @@ F:	include/configs/smdk5420.h
 F:	configs/smdk5420_defconfig
 F:	include/configs/peach-pi.h
 F:	configs/peach-pi_defconfig
+
+ODROID-XU3 BOARD
+M:	Przemyslaw Marczak <p.marczak@samsung.com>
+S:	Maintained
+F:	board/samsung/smdk5420/
+F:	include/configs/odroid_xu3.h

board/samsung/smdk5420/smdk5420.c

@@ -58,16 +58,6 @@ void exynos_lcd_power_on(void)
 
 	mdelay(5);
 
-	/* TODO(ajaykumar.rs@samsung.com): Use device tree */
-	gpio_request(EXYNOS5420_GPIO_X35, "edp_slp#");
-	gpio_direction_output(EXYNOS5420_GPIO_X35, 1);	/* EDP_SLP# */
-	mdelay(10);
-	gpio_request(EXYNOS5420_GPIO_Y77, "edp_rst#");
-	gpio_direction_output(EXYNOS5420_GPIO_Y77, 1);	/* EDP_RST# */
-	gpio_request(EXYNOS5420_GPIO_X26, "edp_hpd");
-	gpio_direction_input(EXYNOS5420_GPIO_X26);	/* EDP_HPD */
-	gpio_set_pull(EXYNOS5420_GPIO_X26, S5P_GPIO_PULL_NONE);
-
 	if (has_edp_bridge())
 		if (parade_init(gd->fdt_blob))
 			printf("%s: ps8625_init() failed\n", __func__);
@@ -75,11 +65,6 @@ void exynos_lcd_power_on(void)
 
 void exynos_backlight_on(unsigned int onoff)
 {
-	/* For PWM */
-	gpio_request(EXYNOS5420_GPIO_B20, "backlight_on");
-	gpio_cfg_pin(EXYNOS5420_GPIO_B20, S5P_GPIO_FUNC(0x1));
-	gpio_set_value(EXYNOS5420_GPIO_B20, 1);
-
 #ifdef CONFIG_POWER_TPS65090
 	tps65090_fet_enable(1);
 #endif

board/synopsys/axs101/axs101.c

@@ -9,6 +9,7 @@
 #include <malloc.h>
 #include <netdev.h>
 #include <phy.h>
+#include "axs10x.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -27,9 +28,9 @@ int board_mmc_init(bd_t *bis)
 	host->ioaddr = (void *)ARC_DWMMC_BASE;
 	host->buswidth = 4;
 	host->dev_index = 0;
-	host->bus_hz = 25000000;
+	host->bus_hz = 50000000;
 
-	add_dwmci(host, 52000000, 400000);
+	add_dwmci(host, host->bus_hz, 400000);
 
 	return 0;
 }
@@ -42,3 +43,16 @@ int board_eth_init(bd_t *bis)
 
 	return 0;
 }
+
+
+#define AXS_MB_CREG	0xE0011000
+
+int board_early_init_f(void)
+{
+	if (readl((void __iomem *)AXS_MB_CREG + 0x234) & (1 << 28))
+		gd->board_type = AXS_MB_V3;
+	else
+		gd->board_type = AXS_MB_V2;
+
+	return 0;
+}

board/synopsys/axs101/axs10x.h

@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2015 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _BOARD_SYNOPSYS_AXS10X_H
+#define _BOARD_SYNOPSYS_AXS10X_H
+
+enum {
+	AXS_MB_V2,
+	AXS_MB_V3
+};
+
+#endif /* _BOARD_SYNOPSYS_AXS10X_H */
+

board/synopsys/axs101/nand.c

@@ -9,6 +9,9 @@
 #include <malloc.h>
 #include <nand.h>
 #include <asm/io.h>
+#include "axs10x.h"
+
+DECLARE_GLOBAL_DATA_PTR;
 
 #define BUS_WIDTH	8		/* AXI data bus width in bytes	*/
 
@@ -232,5 +235,9 @@ int board_nand_init(struct nand_chip *nand)
 	nand->write_buf = axs101_nand_write_buf;
 	nand->read_buf = axs101_nand_read_buf;
 
+	/* MBv3 has NAND IC with 16-bit data bus */
+	if (gd->board_type == AXS_MB_V3)
+		nand->options |= NAND_BUSWIDTH_16;
+
 	return 0;
 }

board/toradex/colibri_t20-common/colibri_t20-common.h

@@ -1,7 +0,0 @@
-/*
- *  Copyright (C) 2012 Lucas Stach
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-void colibri_t20_common_pin_mux_usb(void);

board/toradex/colibri_t20/Kconfig

@@ -1,12 +1,12 @@
-if TARGET_COLIBRI_T20_IRIS
+if TARGET_COLIBRI_T20
 
 config SYS_BOARD
-	default "colibri_t20_iris"
+	default "colibri_t20"
 
 config SYS_VENDOR
 	default "toradex"
 
 config SYS_CONFIG_NAME
-	default "colibri_t20_iris"
+	default "colibri_t20"
 
 endif

board/toradex/colibri_t20/MAINTAINERS

@@ -0,0 +1,7 @@
+COLIBRI_T20
+M:	Lucas Stach <dev@lynxeye.de>
+S:	Maintained
+F:	board/toradex/colibri_t20/
+F:	include/configs/colibri_t20.h
+F:	configs/colibri_t20_defconfig
+F:	arch/arm/dts/tegra20-colibri.dtb

board/toradex/colibri_t20/Makefile

@@ -0,0 +1,9 @@
+#
+#  (C) Copyright 2012 Lucas Stach
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+include $(srctree)/board/nvidia/common/common.mk
+
+obj-y	+= colibri_t20.o

board/toradex/colibri_t20/colibri_t20.c

@@ -9,21 +9,17 @@
 #include <asm/arch/funcmux.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch-tegra/board.h>
+#include <asm/gpio.h>
 
-#include "colibri_t20-common.h"
-
-#ifdef CONFIG_USB_EHCI_TEGRA
-void colibri_t20_common_pin_mux_usb(void)
+#ifdef CONFIG_TEGRA_MMC
+/*
+ * Routine: pin_mux_mmc
+ * Description: setup the pin muxes/tristate values for the SDMMC(s)
+ */
+void pin_mux_mmc(void)
 {
-	/* module internal USB bus to connect ethernet chipset */
-	funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI);
-	/* ULPI reference clock output */
-	pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4);
-	pinmux_tristate_disable(PMUX_PINGRP_CDEV2);
-	/* PHY reset GPIO */
-	pinmux_tristate_disable(PMUX_PINGRP_UAC);
-	/* VBus GPIO */
-	pinmux_tristate_disable(PMUX_PINGRP_DTE);
+	funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT);
+	pinmux_tristate_disable(PMUX_PINGRP_GMB);
 }
 #endif
 
@@ -31,5 +27,39 @@ void colibri_t20_common_pin_mux_usb(void)
 void pin_mux_nand(void)
 {
 	funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_NDFLASH_KBC_8_BIT);
+
+	/*
+	 * configure pingroup ATC to something unrelated to
+	 * avoid ATC overriding KBC
+	 */
+	pinmux_set_func(PMUX_PINGRP_ATC, PMUX_FUNC_GMI);
+}
+#endif
+
+#ifdef CONFIG_USB_EHCI_TEGRA
+void pin_mux_usb(void)
+{
+	/* module internal USB bus to connect ethernet chipset */
+	funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI);
+
+	/* ULPI reference clock output */
+	pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4);
+	pinmux_tristate_disable(PMUX_PINGRP_CDEV2);
+
+	/* PHY reset GPIO */
+	pinmux_tristate_disable(PMUX_PINGRP_UAC);
+
+	/* VBus GPIO */
+	pinmux_tristate_disable(PMUX_PINGRP_DTE);
+
+	/* Reset ASIX using LAN_RESET */
+	gpio_request(GPIO_PV4, "LAN_RESET");
+	gpio_direction_output(GPIO_PV4, 0);
+	pinmux_tristate_disable(PMUX_PINGRP_GPV);
+	udelay(5);
+	gpio_set_value(GPIO_PV4, 1);
+
+	/* USBH_PEN: USB 1 aka Tegra USB port 3 VBus */
+	pinmux_tristate_disable(PMUX_PINGRP_SPIG);
 }
 #endif

board/toradex/colibri_t20_iris/MAINTAINERS

@@ -1,6 +0,0 @@
-COLIBRI_T20_IRIS BOARD
-M:	Lucas Stach <dev@lynxeye.de>
-S:	Maintained
-F:	board/toradex/colibri_t20_iris/
-F:	include/configs/colibri_t20_iris.h
-F:	configs/colibri_t20_iris_defconfig