Fix:
undefined reference to `spi_flash_free'
undefined reference to `spi_flash_probe'
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Stefan Roese <sr@denx.de>
Cc: Markus Niebel <Markus.Niebel@tq-group.com>
Acked-by: Stefan Roese <sr@denx.de>
1. Define two structures mx6ul_iomux_ddr_regs and mx6ul_iomux_grp_regs.
2. Add a new function mx6ul_dram_iocfg to configure dram io.
3. Refactor MMDC1 macro, discard "#ifdef CONFIG_MX6SX". Since
only mmdc0 channel exists on i.MX6SX/UL, redefine MMDC1 macro support
runtime check, but not hardcoding #ifdef macros.
4. Introduce mx6ul-ddr.h, which includes the register address for DRAM
IO configuration.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
i.MX6UL features an Cortex-A7 core, it does not have PL310 as other i.MX6
chips. To Cortex-A7 core, If D-Cache is enabled, L2 Cache is enabled.
There is on specific switch for on/off L2 Cache, so default select
SYS_L2CACHE_OFF.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
1. Add enet, uart, i2c, ipg clock support for i.MX6UL.
2. Correct get_periph_clk, it should account for
MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK.
3. Refactor get_mmdc_ch0_clk to make all i.MX6 share one function,
but not use 'ifdef'.
4. Use CONFIG_FSL_QSPI for enable_qspi_clk, but not #ifdef CONFIG_MX6SX.
5. Use CONFIG_PCIE_IMX for pcie clock settings, use CONFIG_CMD_SATA for
sata clock settings. In this way, we not need "#if defined(CONFIG_MX6Q)
|| defined....", only need one CONFIG_PCIE_IMX in header file.
Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Since i.MX6UL use A7 core, but not A9 core, we do not need
the erratas for i.MX6UL.
Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Since i.MX6UL's cache line size is 64bytes, need to
define the macro CONFIG_SYS_CACHELINE_SIZE to 64 for i.MX6UL.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
1. Update imx register base address for i.MX6UL.
2. Remove duplicated MXS_APBH/GPMI/BCH_BASE.
3. Remove #ifdef for register addresses that equal to
"AIPS2_OFF_BASE_ADDR + 0x34000" for different chips.
4. According fuse map, complete fuse_bank4_regs.
5. Move AIPS3_ARB_BASE_ADDR and AIPS3_ARB_END_ADDR out of #ifdef CONFIG_MX6SX,
because we can use runtime check
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Add MXC_CPU_MX6UL for i.MX6UL CPU type which is got at runtime from
DIGPROG register. But the value has been occupied by MXC_CPU_MX6D which
is not real id from DIGPROG register, so change i.MX6D to value 0x67 which
was not occupied.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
With recent additions to USB Kconfig the number of USB options had grown
large enough to warrant a separate menu for USB.
Add a Kconfig menu for USB.
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Add support for selecting display preset using the environment variable
"displaytype". This is a preparation for future merging of compulab
omap3_display.c display selection code with the cm-fx6 display selection code.
The "panel" environment variable is retained for backwards compatibility.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Implement a cm-fx6 specific board_video_skip() to provide the option to not
initialize the display.
The new function does not init display if the environment variable "panel" is
not defined, or if it is set to an unsupported value.
Collateral changes:
- Don't use the global displays array (it's CONFIG_IMX_VIDEO_SKIP specific).
- Don't use detect_hdmi(), since env controlled init makes it unnecessary.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
U-Boot does not explicitly assign the display to an IPU interface. Instead, it
relies on the power-on default of DI0.
Since the kernel reassigns HDMI display to DI1, after a warm reset the HDMI
display no longer works in U-Boot.
Fix this by explicitly assigning HDMI to IPU1 DI0 in U-Boot.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
1. Add DDR script for mx6qpsabreauto board.
2. On CPU3 board, enet RGMII tx clock is from internal PLL. Set the GPR5[9]
and init the enet pll output to 125Mhz.
3. On CPU3 board, SW1ABC=VDDSOC_IN, SW2=VDDARM_IN.
Build target: mx6qpsabreauto_config
Boot Log:
U-Boot 2015.07-rc2-00071-gfd985ff (Jun 29 2015 - 22:10:55 +0800)
CPU: Freescale i.MX6QP rev1.0 996 MHz (running at 792 MHz)
CPU: Automotive temperature grade (-40C to 125C) at 34C
Reset cause: POR
Board: MX6Q-Sabreauto revA
I2C: ready
DRAM: 2 GiB
PMIC: PFUZE100 ID=0x10
Flash: 32 MiB
NAND: 0 MiB
MMC: FSL_SDHC: 0
*** Warning - bad CRC, using default environment
No panel detected: default to HDMI
Display: HDMI (1024x768)
In: serial
Out: serial
Err: serial
Net: FEC [PRIME]
Hit any key to stop autoboot: 0
Note:
In this patch, we still add a new config mx6qpsabreauto_config,
since SPL is not supported now, and IMX_CONFIG is needed at
build time, so add this config. Future, when SPL is converted,
this config can be removed.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Robin Gong <b38343@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Detect the SOC and board variant at runtime and change the dtb name,
but not hardcoding the fdt_file env variable.
Take the following patch as a reference.
Íd58699b157df75f1aa0b363ea9c21add21a0c
"mx6cuboxi: Load the correct 'fdtfile' variable"
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Since i.MX6QP changes some CCM registers, so modify the clocks settings to
follow the hardware changes.
In c files, use runtime check and discard #ifdef.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Add cpu type for i.MX6QP/DP.
This patch also fix is_mx6dqp(), since get_cpu_rev can return MXC_CPU_MX6QP
and MXC_CPU_MX6DP, we should use:
(is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)).
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
sw variable in checkboard function is storing vbank value
which can only take 3-bit value.
So check of sw value for if greater than 7 is redundant.
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
eMMC has no CD and WP pins, it needs to add board-specific
board_mmc_getcd() and board_mmc_getwp() in SPL to support
eMMC boot without external SD card inserted.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Serdes Lanes availability on T4160 and T4080 are same, which serdes 2 & 3
support 8 Lanes, but serdes 1 & 4 support only 4 Lanes E/F/G/H, Lanes
A/B/C/D are not available, updated the serdes table accordingly with
some minor fix.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Add support for NOR flash and GPIO/I2C switch control on RevC.
- NOR support
- bank0/bank4 switch
- SD/eMMC switch
- board version
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
For running Chain of Trust when doing Secure Boot from NAND,
the Bootscript header and bootscript must be copied from NAND
to RAM(DDR).
The addresses and commands for the same have been defined.
Signed-off-by: Saksham Jain <saksham@freescale.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Secure Boot Target is added for NAND for P5020 and P5040.
The Secure boot target has already been added for P3041 by
enabling CONFIG_SYS_RAMBOOT and configuring CPC as SRAM.
The targets for P5020 and P5040 are added in the same manner.
Signed-off-by: Saksham Jain <saksham@freescale.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Secure Boot Target is added for NAND for P3041.
For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC.
In case of secure boot, this default address maps to Boot ROM.
The Boot ROM code requires that the bootloader(U-boot) must lie
in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF.
In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is
configured as SRAM. U-Boot binary will be located on SRAM configured
at address 0xBFF00000.
In the U-Boot code, TLB entries are created to map the virtual address
0xFFF00000 to physical address 0xBFF00000 of CPC configured as SRAM.
Signed-off-by: Saksham Jain <saksham@freescale.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Commit 488d19c (patman: add distutils based installer) has the side effect
of making patman run twice with each invocation. Fix this by checking for
'main program' invocation in patman.py. This is good practice in any case.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Added routine mmu_set_region_dcache_behaviour() to set a
particular region as non cacheable.
Define dummy routine for mmu_set_region_dcache_behaviour()
to handle incase of dcache off.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
IFC nand ecc encode and decode mode are not correctly
set in CSOR register during nand initialization.Enable
ecc encode/decode in 4-bit mode
Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Correct the value CONFIG_USB_MAX_CONTROLLER_COUNT macro to 1
for p1025 as it has one USB controller
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
The board manual desribes ON as boolean 1 and OFF as boolean 0.
Updating README with correct boolean values.
Signed-off-by: Raghav Dogra <raghav@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
MAC1 acts as 1G/10G dual-role MAC on T1024. We introduce
macro SET_FMAN_RX_10G_TYPE2_LIODN for 10G MACs which have
same Port ID and same offset of address with 1G MAC.
Update it to match with the setting of fman in t1024 device
tree, otherwise there is no 'fsl,liodn' in
/proc/device-tree/soc@ffe000000/fman@400000/port@88000/
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Update PBI command in pbi_cfg files to keep register bit
to default reset value while configuring CPC
as SRAM
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Because the function ft_board_setup() delete the USB2 device node, it
leads to can't find the device node and hung up.
In fact only P1020RDB needs to delete the USB2 node, this patch fixes
this issue.
Signed-off-by: Ying Zhang <b40530@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
T1040D4RDB is a Freescale reference board that hosts the T1040 SoC.
T1040D4RDB is re-designed T1040RDB board with following changes :
- Support of DDR4 memory
- Support of 0x66 serdes protocol which can support following interfaces
- 2 RGMII's on DTSEC4, DTSEC5
- 1 SGMII on DTSEC3
- Support of QE-TDM
Similarily T1042D4RDB is a Freescale reference board that hosts the T1040
SoC. T1042D4RDB is re-designed T1042RDB board with following changes :
- Support of DDR4 memory
- Support for 0x86 serdes protocol which can support following interfaces
- 2 RGMII's on DTSEC4, DTSEC5
- 3 SGMII on DTSEC1, DTSEC2 & DTSEC3
- Support of DIU
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Based on Venice2, incorporates Stephen Warren's
latest P2571 pinmux table.
With Thierry Reding's 64-bit build fixes, this
will build and and boot in 64-bit on my P2571
(when used with a 32-bit AVP loader).
Signed-off-by: Tom Warren <twarren@nvidia.com>
Derived from Tegra124, modified as appropriate during T210
board bringup. Cleaned up debug statements to conserve
string space, too. This also adds misc 64-bit changes
from Thierry Reding/Stephen Warren.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
All based off of Tegra124. As a Tegra210 board is brought
up, these may change a bit to match the HW more closely,
but probably 90% of this is identical to T124.
Note that since T210 is a 64-bit build, it has no SPL
component, and hence no cpu.c for Tegra210.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Moved Tegra config options to mach-tegra/Kconfig so that both
32-bit and 64-bit builds can co-exist for Tegra SoCs.
T210 will be 64-bit only (no SPL) and will require a 32-bit
AVP/BPMP loader.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon's 'tegra124: Implement spl_was_boot_source()' needs
a prototype for save_boot_params_ret() to build cleanly
for 64-bit Tegra210.
Signed-off-by: Tom Warren <twarren@nvidia.com>
ARMv8 requires an architected timer to be present, so it can be used
instead of the Tegra US timer. This allows for better code reuse.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
A subsequent patch will enable the use of the architected timer on
ARMv8. Doing so implies that udelay() will be backed by this timer
implementation, and hence the architected timer must be ready when
udelay() is first called. The first time udelay() is used is while
resetting the debug UART, which happens very early. Make sure that
arch_timer_init() is called before that.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
For 64-bit ARM SoCs we rely on non-U-Boot code to bring up the CPU in
AArch64 mode so that we don't need the SPL. Non-cached memory is not
implemented (yet) for 64-bit ARM.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
On 64-bit SoCs the I-cache isn't enabled in early code, so the default
cache enable functions for 64-bit ARM can be used.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Most peripherals on Tegra can do DMA only to the lower 32-bit
address space, even on 64-bit SoCs. This limitation is
typically overcome by the use of an IOMMU. Since the IOMMU is
not entirely trivial to set up and serves no other purpose
(I/O protection, ...) in U-Boot, restrict 64-bit Tegra SoCs to
the lower 32-bit address space for RAM. This ensures that the
physical addresses of buffers that are programmed into the
various DMA engines are valid and don't alias to lower addresses.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
While generating the page tables, a running integer index is shifted by
SECTION_SHIFT (29) and causes overflow for any integer bigger than 7.
The page tables therefore alias to the same 8 sections and cause U-Boot
to hang once the MMU is enabled.
Fix this by making the index a 64-bit unsigned integer and so avoid the
overflow.
swarren notes: currently "i" ranges from 0..8191 on all ARM64 boards, and
"j" varies depending on RAM size; from 4 to 11 for a board with 4GB at
physical address 2GB, as some Tegra boards have.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
To make it easier to use patman on other projects add a distutils style
installer. Now patman can be installed with
cd u-boot/tools/patman && python setup.py install
There are also the usual distutils options for creating source/binary
distributions of patman.
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
We should mark PCIe ECAM address range in the E820 table as reserved
otherwise kernel will not attempt to use ECAM.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Currently cpu-x86 driver is probed only for SMP. We add the same
support for UP when there is only one cpu node in the deive tree.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
The PIIX3 chipset does not integrate an I/O APIC, instead it supports
connecting to an external I/O APIC which needs to be enabled manually.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
On some platforms the I/O APIC interrupt pin#0-15 may be connected
to platform pci devices' interrupt pin. In such cases the legacy ISA
IRQ is not available so we should not write ISA interrupt entry if
it is already occupied.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Currently during writing MP table I/O interrupt assignment entry, we
assume the PIRQ is directly mapped to I/O APIC INTPIN#16-23, which
however is not always the case on some platforms.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Commit aec241d "dm: pci: Use the correct hose when configuring devices"
was an attempt to fix pci bridge device configuration, but unfortunately
that does not work 100%. In pciauto_config_devices(), the fix tried to
call pciauto_config_device() with a ctlr_hose which is supposed to be
the root controller hose, however when walking through a pci topology
with 2 or more pci bridges this logic simply fails.
The call chain is: pciauto_config_devices()->pciauto_config_device()
->dm_pci_hose_probe_bus(). Here the call to dm_pci_hose_probe_bus()
does not make any sense as the given hose is not the bridge device's
hose, instead it is either the root controller's hose (case#1: if it
is the 2nd pci bridge), or the bridge's parent bridge's hose (case#2:
if it is the 3rd pci bridge). In both cases the logic is wrong.
For example, for failing case#1 if the bridge device to config has the
same devfn as one of the devices under the root controller, the call
to pci_bus_find_devfn() will return the udevice of that pci device
under the root controller as the bus, but this is wrong as the udevice
is not a bus which does not contain all the necessary bits associated
with the udevice which causes further failures.
To correctly support pci bridge device configuration, we should still
call pciauto_config_device() with the pci bridge's hose directly.
In order to access valid pci region information, we need to refer to
the root controller simply by a call to pci_bus_to_hose(0) and get the
region information there in the pciauto_prescan_setup_bridge(),
pciauto_postscan_setup_bridge() and pciauto_config_device().
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
In dm_pci_hose_probe_bus(), pci_bus_find_devfn() is called with a bdf
which includes a bus number, but it really should not as this routine
only expects a device/function encoding.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Currently pci_bus_read_config() and pci_bus_write_config() are
called with bus number masked off in the parameter bdf, and bus
number is supposed to be added back in the bridge driver's pci
config read/write ops if the device is behind a pci bridge.
However this logic only works for a pci topology where there is
only one bridge off the root controller. If there is addtional
bridge in the system, the logic will create a non-existent bdf
where its bus number gets accumulated across bridges.
To correct this, we change all pci config read/write routines
to use complete bdf all the way up to the root controller.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
In driver model, each pci bridge device has its own hose structure.
hose->first_busno points to the bridge device's device number, so
we should not substract hose->first_busno before programming the
bridge device's primary/secondary/subordinate bus number registers.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
This corrects several typos in the comment block as well as some
indentions and nits in the linker_lists.h.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
The doc wrongly put sandbox in the '--fetch-arch' command. Remove it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
We need walk through all functions within a PCI device and assign
their IRQs accordingly.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Add a RTC node in the device tree to enable DM RTC support.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
(Squashed in 'x86: Fix RTC build error on ivybridge')
Turn on cache on the pci option rom area to improve the performance.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Instead of using switch..case for architecture defined exceptions,
simply unify the handling by printing a message of exception name,
followed by registers dump then halt the CPU.
With this unification, it also fixes the wrong exception numbers
for #MF/#AC/#MC/#XM which should be 16/17/18/19 not 15/16/17/18.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Some exceptions cause an error code to be saved on the current stack
after the EIP value. We should extract CS/EIP/EFLAGS from different
position on the stack based on the exception number.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Use one command for showing overall CPU status than several without
knowing how many cpus is available in the system.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Adds the two MIO connected pushbuttons on the zc702 board to the
devicetree as a single multi-key device for us with the gpio-keys driver.
Signed-off-by: Ezra Savard <ezra.savard@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Remove unneeded address-cells form intc node because it is already setup
in parent node.
Add missing address-cells and size-cells to eth node to be shared for
every platform DTSes.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Use the new zynq binding for macb ethernet, since it will disable half
duplex gigabit like the Zynq TRM says to do. Also allow the compatible
cadence gem binding that won't disable half duplex but works otherwise.
Signed-off-by: Nathan Sullivan <nathan.sullivan@ni.com>
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Zynq is using Cadence IP where binding is documented in the Linux kernel
and there is no reason to use different binding.
Synchronize it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Due to dependencies between timer and CPU frequency, only changes by
powers of two are allowed. The clocksource driver prevents other
changes, but with cpufreq and its governors it can result in being
spammed with error messages constantly. Hence, remove the 222 MHz OPP.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
To silence the warning
cpufreq_cpu0: failed to get cpu0 regulator: -19
from the cpufreq driver regarding a missing regulator,
add a fixed regulator to the DT.
Zynq does not support voltage scaling and the CPU rail should always be
supplied with 1 V, hence it is added in the SOC-level dtsi.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Pass directly boot_addr which is LOVEC (0) or HIVEC (0xffff0000).
No reason to use magic values 0 and 1.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Provide option to enable uart dcc support for zynqmp
This config can be enabled as per board config file.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Move CONFIG_SYS_TEXT_BASE of ZynqMP_ep to its
respective defconfig
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Define a new config "zynqmp_ep" for ZynqMP instead
of xilinx_zynqmp. This defconfig supports all emulation
platforms of ZynqMP. Also renamed TARGET_XILINX_ZYNQMP
to ARCH_ZYNQMP.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Move the zynqmp Kconfig from board to arch
as there may be different boards under same
architecture.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Increase the Rx Buffer descriptors to 32. This will avoid
Rx buffer descriptors overflow if more packets were received
at one shot before we process the received ones.
This fixes the issue of intermittent timeouts during tftp
on a 1Gb connection with tftp server running on windows.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Flush and invalidate the rx buffers while sending the
tx packet it self as armv8 does flush also while doing
invalidation.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The encoding of the sub instruction used to handle CONFIG_SYS_MALLOC_F_LEN
can only accept certain values, and the set of acceptable values differs
between the AArch32 and AArch64 instructions sets. The default value of
CONFIG_SYS_MALLOC_F_LEN works with either ISA. Tegra uses a non-default
value that can only be encoded in the AArch32 ISA. Fix the AArch64 crt0
assembly so it can handle completely arbitrary values.
Signed-off-by: Thierry Reding <treding@nvidia.com>
[twarren: trimmed Thierry's patch to remove changes already present]
Signed-off-by: Tom Warren <twarren@nvidia.com>
[swarren, cleaned up patch, wrote description, re-wrote subject]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Use %p to print pointers.
The max value of (i_buf - i_buf_start) should be dfu_buf_size, which is
an unsigned long, so cast the pointer difference to that type to print.
Change-Id: Iee242df9f8eb091aecfe0cea4c282b28b547acfe
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The sysboot and pxe commands currently support either U-Boot formats or
raw zImages. Add support for the AArch64 Linux port's native image format
too.
As with zImage support, there is no auto-detection of the native image
format. Rather, if the image is auto-detected as a U-Boot format, U-Boot
will try to interpret it as such. Otherwise, U-Boot will fall back to a
raw/native image format, if one is enabled.
My belief is that CONFIG_CMD_BOOTZ won't ever be enabled for any AArch64
port, hence there's never a need to differentiate between CONFIG_CMD_
_BOOTI and _BOOTZ at run-time; compile-time will do. Even if this isn't
true, we want to prefer _BOOTI over _BOOTZ when defined, since _BOOTI is
definitely the native format for AArch64.
Change-Id: I83c5cc7566032afd72516de46f4e5eb7a780284a
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
We are getting very close to running out of space in SPL, and with the
currently Chrome OS gcc 4.9 we exceed the limit. Add a litle more space.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Enable the I2C3 pins so that the TPM can be used.
Note: There is an DP change also, caused by running board-to-uboot.py
script in the latest tegra-pinmux-script tree.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
In order to achieve reproducible builds in U-Boot, timestamps that are defined
at build-time have to be somewhat eliminated. The SOURCE_DATE_EPOCH environment
variable allows setting a fixed value for those timestamps.
Simply by setting SOURCE_DATE_EPOCH to a fixed value, a number of targets can be
built reproducibly. This is the case for e.g. sunxi devices.
However, some other devices might need some more tweaks, especially regarding
the image generation tools.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
This is commented out in the Makefile for more than 10 years.
I assume it is proof that this tool is unused.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Pantelis Antoniou <panto@intracom.gr>
Switch to using zImage instead of uImage. and while at it, start using
bootz as default. While at it, get rid of BOOTIMAGE define and start
using Linux upstream dtb file names.
Reviewed-by: Murali Karicheri <m-karicheri2@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Use the defaults defined in DEFAULT_LINUX_BOOT_ENV
Reviewed-by: Murali Karicheri <m-karicheri2@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Try to maintain as much commonality by conditionally including stuff
in armv7_common as necessary and removing the common defines from
keystone2 header.
Note: as part of this change, all keystone2 platforms will now start
using the generic u-boot prompt instead of the custom prompt.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
rename the keystone2 common header into an keystone2 architecture
specific header which can then reuse the common ti_armv7 config headers.
Acked-by: Vitaly Andrianov <vitalya@ti.com>
Acked-By: Murali Karicheri <m-karicheri2@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
CONFIG_LINUX_BOOT_PARAM_ADDR is not a valid configuration option. Do
just like what the rest of the world does.
Acked-by: Vitaly Andrianov <vitalya@ti.com>
Acked-By: Murali Karicheri <m-karicheri2@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Commit bd2c4522c2 ("ti: armv7: enable EXT support in SPL (using
ti_armv7_common.h)") enabled thumb mode only for SPL builds, however,
All TI armv7 platforms do support thumb, and there is no reason why the
space savings cannot be exploited for u-boot as well.
Reported-by: Murali Karicheri <m-karicheri2@ti.com>
Suggested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
TI armv7 based SoCs are based on two architectures - one based on OMAP
generation architecture and others based on Keystone architecture.
Many of the options are architecture specific, however a lot are common
with v7 architecture. So, step 1 will be to move out OMAP specific stuff
from ti_armv7_common into a ti_armv7_omap.h header which is then used
by all the relevant architecture headers.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Read device unique ID and set environment variable "serial#".
Value would then be passed to kernel through DTB.
To read ID from DTB, kernel is required to have commit:
3f599875e5202986b350618a617527ab441bf206 (ARM: 8355/1: arch: Show
the serial number from devicetree in cpuinfo)
This commit is already mainline since v4.1-rc1.
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
To: Albert Aribaud <albert.u.boot@aribaud.net>
To: Tom Rini <trini@konsulko.com>
To: Kamil Lulko <rev13@wp.pl>
Cc: u-boot@lists.denx.de
Because the top-level Makefile forces all the source files
to include include/linux/kconfig.h (see the UBOOTINCLUDE define),
these includes are redundant.
By the way, there are exceptions for the statement above; host
programs. In fact, host tools in U-Boot depend on a particular
board configuration, although I think they should not. So, some
files still include <linux/config.h> to work around build errors
on host tools.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Simon Glass <sjg@chromium.org>
All am33xx device tree are using device-tree, so get_board_rev is never actually
called. Thus, we can get rid of it to make the code easier to maintain.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
Despite being defined with __weak, this declaration of get_board_rev will
conflict with the fallback one when ONFIG_REVISION_TAG is not defined.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
This introduces code to read the value of the SYS_BOOT pins on the OMAP5, as
well as the memory-preferred scheme for the interpretation of each value.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
This introduces code to read the value of the SYS_BOOT pins on the OMAP4, as
well as the memory-preferred scheme for the interpretation of each value.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
This introduces code to read the value of the SYS_BOOT pins on the OMAP3, as
well as the memory-preferred scheme for the interpretation of each value.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
OMAP devices might boot from peripheral devices, such as UART or USB.
When that happens, the U-Boot SPL tries to boot the next stage (complete U-Boot)
from that peripheral device, but in most cases, this is not a valid boot device.
This introduces a fallback option that reads the SYS_BOOT pins, that are used by
the bootrom to determine which device to boot from. It is intended for the
SYS_BOOT value to be interpreted in the memory-preferred scheme, so that the
U-Boot SPL can load the next stage from a valid location.
Practically, this options allows loading the U-Boot SPL through USB and have it
load the next stage according to the memory device selected by SYS_BOOT instead
of stalling.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
The config file for the siemens-am33x-common was using OMAP_I2C_STANDARD, which
is defined in a header that is not included in the config header. In most cases,
it was being included by the code using CONFIG_SYS_OMAP24_I2C_SPEED, but it
might not always be the case.
In particular, when introducing I2C SPL support in omap-common's boot-common.c,
the header is missing and including it breaks other devices.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Now that SPL boot devices are clearly defined, we can use BOOT_DEVICE_QSPI_4
instead of a hardcoded value.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
This cleans up the SPL boot devices for omap platforms and introduces support
for missing boot devices.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
This introduces OMAP3 support for the common omap boot code, as well as a
major cleanup of the common omap boot code.
First, the omap_boot_parameters structure becomes platform-specific, since its
definition differs a bit across omap platforms. The offsets are removed as well
since it is U-Boot's coding style to use structures for mapping such kind of
data (in the sense that it is similar to registers). It is correct to assume
that romcode structure encoding is the same as U-Boot, given the description
of these structures in the TRMs.
The original address provided by the bootrom is passed to the U-Boot binary
instead of a duplicate of the structure stored in global data. This allows to
have only the relevant (boot device and mode) information stored in global data.
It is also expected that the address where the bootrom stores that information
is not overridden by the U-Boot SPL or U-Boot.
The save_omap_boot_params is expected to handle all special cases where the data
provided by the bootrom cannot be used as-is, so that spl_boot_device and
spl_boot_mode only return the data from global data.
All of this is only relevant when the U-Boot SPL is used. In cases it is not,
save_boot_params should fallback to its weak (or board-specific) definition.
save_omap_boot_params should not be called in that context either.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
The symbolic link to SoC/CPU specific header directory is created
during the build, while it is only necessary for ARM, AVR32, SPARC,
x86, and some CPUs of PowerPC. For the other architectures, it just
results in a broken symbolic link.
Introduce CONFIG_CREATE_ARCH_SYMLINK to not create unneeded symbolic
links.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
There are only two SoC-specific headers for this architecture:
- arch/nds32/include/asm/arch-ag101/ag101.h
- arch/nds32/include/asm/arch-ag102/ag102.h
Those two have different file names, so there is no advantage to
include them via symbolic linked directory.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
In case of enable CONFIG_OF_CONTROL and has a "model" property in the root node,
the board special "checkboard" will not be called.
Usually we show some useful version information in the function.
This patch enable call "checkboard" in any case.
It is not conflicting with showing "model" at the same time.
For example on LS2085AQDS:
Showing "model" only:
Model: Freescale Layerscape 2085a QDS Board
Showing "checkboard" only:
Board: LS2085E-QDS, Board Arch: V1, Board version: B, boot from vBank: 4
Showing both:
Model: Freescale Layerscape 2085a QDS Board
Board: LS2085E-QDS, Board Arch: V1, Board version: B, boot from vBank: 4
Signed-off-by: Haikun Wang <haikun.wang@freescale.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The MCAST_TFTP support requires that network drivers has mcast functon
implemented. This commit adds dummy keystone2_eth_bcast_addr() to meet
the requirement. As far as the driver doesn't use ALE and doesn't filter
any incoming packets, the function is empty.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
When core A turning of core B, via tetris DPSC it places the core
B DPSC into transitional state. The core B has to execute wfi instruction
to move its DPSC to the OFF state. This patch add such instruction.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Only 2 frequencies are supported. The current driver implementation does
not always use the 2 last configured blink frequencies. This patch
fixes this problem. So that the last two entered frequencies are
active.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Tom Rini <trini@konsulko.com>
Prior to this commit, it was impossible to use relative path to
include Makefiles from the top level Makefile because the option
"--include-dir=$(srctree)" becomes effective when Make enters into
sub Makefiles.
To use relative path in any places, this commit moves the option
above the "sub-make" target.
This was imported from Linux (commit a436bb7b8063) and adjusted for
U-Boot.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Michal Marek <mmarek@suse.cz>
$(always) is added to targets by scripts/Makefile.build.
Moreover, filechk does not need .*.cmd files.
Adding these two files to targets is redundant.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Update some build scripts to match Linux 4.1. Commit-based syncing
was done so as not to break U-Boot specific changes.
The previous big sync was from Linux 3.18-rc1 by commit 176d098277
(kbuild: sync misc scripts with Linux 3.18-rc1).
The commits imported from Linux (some with adjustments) are:
[1] commit 9fb5e5372208973984a23ee6f5f025c05d364633
Author: Robert Richter <rrichter@cavium.com>
dts, kbuild: Factor out dtbs install rules to Makefile.dtbinst
[2] commit 371fdc77af44f4cb32475fd499e1d912ccc30890
Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
kbuild: collect shorthands into scripts/Kbuild.include
[3] commit a29b82326ed4eb5567b03c85b52c6891578d5a03
Author: Michal Marek <mmarek@suse.cz>
kbuild: Remove duplicate $(cmd) definition in Makefile.clean
[4] commit 1846dfbde3e8a53f3673dcb1c1b79fd9b3f8d40d
Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
kbuild: remove redundant -rR flag of hdr-inst
[5] commit 34948e0bbf98640fc1821751b01d2f0cd17d84d5
Author: Michal Marek <mmarek@suse.cz>
kbuild: Drop support for clean-rule
[6] commit a16c5f99a28c9945165c46da27fff8e6f26f8736
Author: Michal Marek <mmarek@suse.cz>
kbuild: Fix removal of the debian/ directory
[7] commit d0d38cd9e853db11e0242b3df4c9c3c4a663fbb4
Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
kbuild: use mixed-targets when two or more config targets are given
[8] commit dd33c03b18b3f2db791eb6a17c37d2de66e4de18
Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
kbuild: fix cc-ifversion macro
[9] commit 665d92e38f65d70796aad2b8e49e42e80815d4a4
Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
kbuild: do not add $(call ...) to invoke cc-version or cc-fullversion
[10] commit 6dcb4e5edf39e3b65a75ca76f087b2fdbee8a808
Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
kbuild: allow cc-ifversion to have the argument for false condition
[11] commit c0a80c0c27e5e65b180a25e6c4c2f7ef9e386cd3
Author: Heiko Carstens <heiko.carstens@de.ibm.com>
ftrace: allow architectures to specify ftrace compile options
[12] commit 0b24becc810dc3be6e3f94103a866f214c282394
Author: Andrey Ryabinin <a.ryabinin@samsung.com>
kasan: add kernel address sanitizer infrastructure
[13] commit 4218affdf57f938c04e3a916a9685ee27079f377
Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
kbuild: remove warning about "make depend"
[14] commit 77479b38e2f58890eb221a0418357502a5b41cd6
Author: Nathan Rossi <nathan.rossi@xilinx.com>
kbuild: Create directory for target DTB
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Robert Richter <rrichter@cavium.com>
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Signed-off-by: Andrey Ryabinin <a.ryabinin@samsung.com>
Signed-off-by: Nathan Rossi <nathan.rossi@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Michal Marek <mmarek@suse.cz>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Update the files under scripts/kconfig/ to match Linux 4.1.
Some Kconfig sources have diverged from those in the kernel,
so commit-base syncing was done not to lose U-Boot specific updates.
The commits cherry-picked from Linux are:
[1] commit be8af2d54a66911693eddc556e4f7a866670082b
Author: Bjørn Forsman <bjorn.forsman@gmail.com>
kconfig/lxdialog: get ncurses CFLAGS with pkg-config
[2] commit 3943f42c11896ce82ad3da132c8a5630313bdd0e
Author: Andrey Utkin <andrey.krieger.utkin@gmail.com>
Replace mentions of "list_struct" to "list_head"
[3] commit e4e458b45c5861808674eebfea94cee2258bb2ea
Author: Arjun Sreedharan <arjun024@gmail.com>
calloc/xcalloc: Fix argument order
[4] commit 09950bc256e3628d275f90e016e6f5a039fbdcab
Author: Olof Johansson <olof@lixom.net>
merge_config.sh: Display usage if given too few arguments
[5] commit b6a2ab2cd4739a9573ed41677e53171987b8da34
Author: Colin Ian King <colin.king@canonical.com>
kconfig: use va_end to match corresponding va_start
[6] commit 70529b1a1784503169416df19ce3d68746401340
Author: Michal Marek <mmarek@suse.cz>
kconfig: Get rid of the P() macro in headers
[7] commit 463157444e377bf9b279101b1f16a94c4648c03a
Author: Michal Marek <mmarek@suse.cz>
kconfig: Remove dead code
[8] commit ad8d40cda3ad22ad9e8863d55a5c88f85c0173f0
Author: Michal Marek <mmarek@suse.cz>
kconfig: Remove unnecessary prototypes from headers
[9] commit de4619937229378e81f95e99c9866acc8e207d34
Author: Masahiro Yamada <yamada.masahiro@socionext.com>
kbuild: mergeconfig: fix "jobserver unavailable" warning
[10] commit b9fe99c5b994c6ddc57780993966b18899526c0b
Author: Masahiro Yamada <yamada.masahiro@socionext.com>
kbuild: mergeconfig: move an error check to merge_config.sh
[11] commit 371cfd4ff0611d8bc5d18bbb9cc6a2bc3d56cd3d
Author: Masahiro Yamada <yamada.masahiro@socionext.com>
kbuild: mergeconfig: remove redundant $(objtree)
[12] commit 3a975b8cfcbe026b535f83bde9a3c009bae214f9
Author: Masahiro Yamada <yamada.masahiro@socionext.com>
merge_config.sh: improve indentation
[13] commit bc8f8f5fc47cd02c2c5f3580dac2fe6695af1edd
Author: Masahiro Yamada <yamada.masahiro@socionext.com>
merge_config.sh: rename MAKE to RUNMAKE
[14] commit 63a91033d52e64a22e571fe84924c0b7f21c280d
Author: Masahiro Yamada <yamada.masahiro@socionext.com>
kbuild: add generic mergeconfig target, %.config
[15] commit 1cba0c305758c3c1786ecaceb03e142c95a4edc9
Author: Michal Marek <mmarek@suse.cz>
kconfig: Simplify Makefile
[16] commit 0a1f00a1c86421cc07cec87011c7cf4df68ee54b
Author: Michal Marek <mmarek@suse.cz>
kconfig: Do not print status messages in make -s mode
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Bjørn Forsman <bjorn.forsman@gmail.com>
Signed-off-by: Andrey Utkin <andrey.krieger.utkin@gmail.com>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
Signed-off-by: Arjun Sreedharan <arjun024@gmail.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Michal Marek <mmarek@suse.cz>
Palmas power support is required for OMAP5 devices such as the OMAP5 uEVM, that
need to e.g. enable MMC power at SPL stage.
This is especially important when booting from a peripheral (such as USB, UART),
where the bootrom will not enable power for the MMC device that will hold the
main U-Boot.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
Add thermal support so that we can see the following message on boot:
CPU: Industrial temperature grade (-40C to 105C) at 33C
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Perfoming an OR operation on the error is not a good approach.
Return the error immediately for each ESDHC instance instead.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Entering the maximum number of characters defined by CONFIG_SYS_CBSIZE into
the console and hitting enter afterwards, causes a hang in the system because
CONFIG_SYS_PBSIZE is not capable of storing the extra characters of the error
message:
"Unknown command '' - try 'help'".
Use the default CONFIG_SYS_PBSIZE definition from config_fallbacks.h to solve
this problem.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
DCIMVAC is upgraded to DCCIMVAC for the individual processor
(Cortex-A7) that the DCIMVAC is executed on.
We should follow the linux dma follow. Before DMA read, first
invalidate dcache then after DMA read, invalidate dcache again.
With the DMA direction DMA_FROM_DEVICE, the dcache need be
invalidated again after the DMA completion. The reason is
that we need explicity make sure the dcache been invalidated
thus to get the DMA'ed memory correctly from the physical memory.
Any cache-line fill during the DMA operations such as the
pre-fetching can cause the DMA coherency issue, thus CPU get the stale data.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Signed-off-by: Jason Liu <r64343@freescale.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
The variable 'ret' is used to store the value returned by pfuze_mode_init(),
so it should be of type 'int' instead of 'unsigned int' in order to
correctly handle negative numbers.
Fix the variable type.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
The variable 'ret' is used to store the value returned by pfuze_mode_init(),
so it should of type 'int' instead of 'unsigned int' in order to correctly
handle negative numbers.
Fix the variable type.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
This patch adds support for the "OHB System AG" baseboard
with is equipped with the TQMa6S SoM.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Markus Niebel <Markus.Niebel@tq-group.com>
Cc: Stefano Babic <sbabic@denx.de>
Now that the device-model port of the musb mode makes it possible, enable
both the ehci and otg in host mode on boards where the musb is wired up in
host only mode, either via an usb-a receptacle or via an usb <-> sata
converter.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
This allows using devices plugged into both ports of the tablet.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
On some boards the otg is wired up in host-only mode in this case we
have no vbus-det gpio.
Stop logging an error from sunxi_usb_phy_vbus_detect() in this case, and
stop treating sunxi_usb_phy_vbus_detect() returning a negative errno, as
if a charger is plugged into the otg port.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
When we return an error the usb core will print an error-message, so in this
case do not print anything.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Acked-by: Ian Campbell <ian.campbell@citrix.com>
Modify the sunxi musb glue to use the device-model for musb host mode.
This allows using musb in host mode together with other host drivers
such as ehci / ohci, which is esp. useful on boards which use the
musb controller in host-only mode, these boards have e.g. an usb-a
receptacle or an usb to sata converter attached to the musb controller.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Move the musb config and platdata to the sunxi-musb glue, which is where
it really belongs. This is preparation patch for adding device-model
support for the sunxi-musb-host code.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
When in host mode check if there is a host cable inserted into the otg
port by checking the id pin. If there is no host cable return an error to
make usb_lowlevel_init() exit early, rather then waiting for 1 second
for a device which will never show up.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Add support for reading the id pin value of the otg connector to the usb
phy code.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Start using the new Kconfig options which are available for these now,
and simply always enable them by selecting them as sunxi builds always
include USB support.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Reviewed-by: Simon Glass <sjg@chromium.org>
With certain features being convert to DM now we want sunxi to default
to having DM enabled for ETH/SERIAL and USB in some cases.
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Tom Rini <trini@konsulko.com>
[hdegoede@redhat.com: Also select CONFIG_USB for all sunxi builds]
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Reviewed-by: Simon Glass <sjg@chromium.org>
At one point in time the utoo-p66 dts file in the kernel had a bogus
uart entry, and it seems like we synced with the kernel at just the wrong
moment.
This commit removes the bogus uart entry, which breaks booting the utoo-p66
when DM_SERIAL=y.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The ci_udc driver request allocation assumes that the endpoint descriptor
pointer is set to retrieve the endpoint number, but that is only true
when the endpoint is enabled. This results in a NULL ptr dereference
which for me happens to return 0 value. This causes the EP0 request
struct to be returned for other endpoints. Some gadget drivers like
fastboot and USB MS work fine, but ethernet does not.
Really, the ci_udc driver is the oddball here doing this EP0 special
case handling Stephen added. All the other drivers alloc/free functions
are pretty much the same with the only variation being the size of the
private struct. This could all be consolidated to a common function.
Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Stephen Warren <swarren@nvidia.com>
Remove the boot signature check from board_mmc_init() in spl mode, as it
is already done in spl_boot_device() in this case, and update the comments
to reflect this.
Signed-off-by: Daniel Kochmański <dkochmanski@turtle-solutions.eu>
CC: Roy Spliet <r.spliet@ultimaker.com>
Cc: Ian Campbell <ijc@hellion.org.uk>
[hdegoede@redhat.com: Disable the check only for SPL instead of always]
Acked-by: Hans De Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Make possible using a single `u-boot-sunxi-with-spl.bin` binary for both NAND
memory and SD card. Detection where SPL was read from is implemented in
`spl_boot_device`.
Signed-off-by: Daniel Kochmański <dkochmanski@turtle-solutions.eu>
CC: Roy Spliet <r.spliet@ultimaker.com>
Cc: Ian Campbell <ijc@hellion.org.uk>
[hdegoede@redhat.com: Some small coding style fixes]
Acked-by: Hans De Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This patch extracts checking for valid SD card "eGON.BT0" signature from
`board_mmc_init` into function `sunxi_mmc_has_egon_boot_signature`.
Buffer for mmc sector is allocated and freed at runtime. `panic` is
triggered on malloc failure.
Signed-off-by: Daniel Kochmański <dkochmanski@turtle-solutions.eu>
CC: Roy Spliet <r.spliet@ultimaker.com>
Cc: Ian Campbell <ijc@hellion.org.uk>
[hdegoede@redhat.com: Small bugfix to make it work for devs other then mmc0]
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This patch adds the configuration options to boot via SDIO/MMC on the
Marvell DB-88F6820-GP Armada A38x board. The default boot device
is still SPI NOR flash.
To enable MMC booting on this board 2 things need to be changes:
a) Change kwbimage.cfg
BOOT_FROM sdio
b) In the config header select
#define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SDIO_MMC_CARD
The generated image needs to be copied to the first bootable MMC
partition:
dd if=u-boot-spl.kwb of=/dev/sdX1
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Dirk Eibach <eibach@gdsys.de>
This patch introduces the option to boot from a MMC card parition with
an offset. This can be done by using both defines together:
define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1
define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR ((160 << 10) / 512)
The example above loads the main U-Boot at offset 160KiB from the MMC
partition 1.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Dirk Eibach <eibach@gdsys.de>
Cc: Tom Rini <trini@konsulko.com>
To use this offset for other boot device (like SDIO/MMC), lets rename
it to a more generic name. This will be used be the SDIO/MMC SPL boot
support for the A38x.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Dirk Eibach <eibach@gdsys.de>
This patch adds support to select the "sdio" as boot device in the
kwbimage.cfg file. This line selects this SDIO device:
BOOT_FROM sdio
Tested on Marvell DB-88F6820-GP board.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Dirk Eibach <eibach@gdsys.de>
This patch adds basic SDIO/MMC booting support to MVEBU SoC's. Since
I don't know of a way to test the boot-device upon runtime, this patch
hardcodes the spl_boot_device instead.
Tested on Marvell DB-88F6820-GP board.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Dirk Eibach <eibach@gdsys.de>
The init code for UMC (Unified Memory Controller) and PLL has not
been mainlined yet, but U-boot proper should work.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
To use FIT boot, we have to describe Image Tree Source in addition.
So, it is not intended for beginners. Disable it by default.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The command "run tftpboot" downloads some files onto the RAM
via TFTP and boots the kernel.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Currently, the environment variables "norboot" and "nandboot" only
work with CONFIG_FIT, but we do not want to depend on CONFIG_FIT to
boot the kernel.
This commit adds environments useful for booting Linux with separate
uImage + ramdisk + DTB.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
For the record, describe exactly which device of which vendor
is used on this board.
I2C EEPROM is bound by the generic compatible string, "i2c-eeprom",
so this commit has no impact on the functionality.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This patch adds SPL support for the Marvell DB-88F6820-GP board.
With this change, the bin_hdr from the original Marvell U-boot
is not needed any more on this board. The sources from bin_hdr
(SERDES/PHY and DDR setup) are now integrated in mainline
U-Boot. And this patch enables them for this board.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds the DDR3 setup and training code taken from the Marvell
U-Boot repository. This code used to be included as a binary (bin_hdr)
into the Armada A38x boot image. Not linked with the main U-Boot. With this
code addition and the serdes/PHY setup code, the Armada A38x support
in mainline U-Boot is finally self-contained. So the complete image
for booting can be built from mainline U-Boot. Without any additional
external inclusion.
Note:
This code has undergone many hours (days!) of coding-style cleanup and
refactoring. It still is not checkpatch clean though, I'm afraid. As the
factoring of the code has so many levels of indentation that many lines
are longer than 80 chars.
Signed-off-by: Stefan Roese <sr@denx.de>
With the upcoming addition of the Armada 38x DDR support, which is not
compatible to the Armada XP DDR init code, we need to introduce a new
directory infrastructure. To support multiple Marvell DDR controller.
This will be the new structure:
drivers/ddr/marvell/axp
Supporting Armada XP (AXP) devices (and perhaps Armada 370)
drivers/ddr/marvell/a38x
Supporting Armada 38x devices (and perhaps Armada 39x)
Signed-off-by: Stefan Roese <sr@denx.de>
This code is ported from the Marvell bin_hdr code into mainline
SPL U-Boot. It needs to be executed very early so that the devices
connected to the serdes PHY are configured correctly.
Signed-off-by: Stefan Roese <sr@denx.de>
With the upcoming addition of the Armada 38x SPL support, which is not
compatible to the Armada XP SERDES init code, we need to introduce a new
directory infrastructure. So lets move the AXP serdes init code into
a new directory. This way the A38x code can be added in a clean way.
Signed-off-by: Stefan Roese <sr@denx.de>
Only with disabled MMU its possible to switch the base register address on
Armada 38x. Without this the SDRAM located at >= 0x4000.0000 is also not
accessible, as its still locked to cache.
Signed-off-by: Stefan Roese <sr@denx.de>
Pin muxing needs to be done before UART output, since on A38x the UART
pins need some re-muxing for output to work.
Signed-off-by: Stefan Roese <sr@denx.de>
On A38x switching the regs base address without running from
SDRAM doesn't seem to work. So let the SPL still use the
default base address and switch to the new address in the
mail u-boot later.
Signed-off-by: Stefan Roese <sr@denx.de>
Without calling timer_init(), the xdelay() functions return immediately.
We need to call timer_init() early, so that these functions work and
the PHY and DDR init code works correctly.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Anton Schubert <anton.schubert@gmx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
This patch initializes the SATA address windows on Armada XP and
allows it to work with the existing mvsata_ide driver.
It also adds the necessary configuration for the db-mv784mp-gp board.
Signed-off-by: Anton Schubert <anton.schubert@gmx.de>
Tested-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Currently, kzalloc() returns zero-filled memory, while kmalloc()
simply ignores the second argument and never fills the memory
area with zeros.
I want kmalloc(size, __GFP_ZERO) to behave as kzalloc() does,
which will make it easier to add more memory allocator variants.
With the introduction of __GFP_ZERO flag, going forward, kzmalloc()
variants can fall back to kmalloc() enabling the __GFP_ZERO flag.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Acked-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
The vzalloc(size) is equivalent to kzalloc(size, 0). Move it to
include/linux/compat.h as an inline function in order to avoid the
function call overhead.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Acked-by: Simon Glass <sjg@chromium.org>
The macro cpu_relax() is defined by several headers in different
ways.
arch/{arm,avr32,mips}/include/asm/processor.h defines it as follows:
#define cpu_relax() barrier()
On the other hand, include/linux/compat.h defines it as follows:
#define cpu_relax() do {} while (0)
If both headers are included from the same source file, the warning
warning: "cpu_relax" redefined [enabled by default]
is displayed.
It effectively makes it impossible to include <linux/compat.h>
from some sources. Drop the latter.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Acked-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
These two declarations in arch/x86/include/asm/interrupt.h conflict
with ones in include/linux/compat.h, so x86 boards cannot include
<linux/compat.h>.
The comment /* arch/x86/lib/interrupts.c */ is bogus now, and we do
not see any definitions of disable_irq() and enable_irq() in there.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
This patch removes the wrl accessor function from the Marvell EHCI
driver by replacing it with the writel function.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
FASTBOOT is defined both by CONFIG_USB_FUNCTION_FASTBOOT AND CONFIG_CMD_FASTBOOT, so it doesn't
make much sense to have a CONFIG_USB_FASTBOOT prefix for fastboot-specific options, especially
given that other config options for fastboot use the CONFIG_FASTBOOT prefix.
This replaces the CONFIG_USB_FASTBOOT prefix with CONFIG_FASTBOOT, for consistency.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Add the required files for the Broadcom UDC OTG interface.
Signed-off-by: Jiandong Zheng <jdzheng@broadcom.com>
Signed-off-by: Steve Rae <srae@broadcom.com>
Recent versions of the fastboot tool will query the partition type before doing
an operation on a partition (such as erase, flash, etc). It will then submit
the operation as soon as the response for the partition type is received.
Usually, the MUSB controller will see that the partition type request return
status was read by the host at the very same time as the actual operation
request is submitted by the host. However, the operation will be read first
(int_rx is handled first in musb_interrupt) and after it is completed, the
fastboot USB gadget driver will send another return status. Hence, this happens
before the musb gadget framework has had a chance to handle the previous
acknowledgement that the host read the return status and dequeue the request.
The host will then usually empty the FIFO by the time musb_interrupt gets around
handling the return status acknowledgement (for the previous request, this is
still on the same musb_interrupt call), so no other interrupt is generated and
the most recent return status acknowledgement remains unaccounted for.
It will then be used as a response for the next command, and the proper response
for it will be delayed to the next command, and so on.
Dequeuing the previous IN request in the fastboot code ensures that no previous
return status remains. It is acceptable to do it since there is no callback to
it anyways.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
This avoids handling requests that have an error status or no data.
In particular, this avoids showing unnecessary error messages when the USB
gadget gets disconnected (e.g. with fastboot continue) and the fastboot USB
gadget driver sends an error back to the host (that has disconnected already).
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Since we're now using a dynamic controller index for fastboot too,
usb_gadget_handle_interrupts should be using it instead of 0 (despite the fact
that it's currently not being used at all in the musb-new implementation).
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Weak versions of board_usb_init and board_usb_cleanup are defined in common USB
host code, but it is also used for USB device gadgets, so we also need a weak
definition of it when there is no USB host enabled.
Both weak definitions do not conflict.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
Test HW: Odroid_XU3 (Exynos5422), trats (Exynos4210)
Each USB download function command calls board_usb_init before registering the
USB gadget and board_usb_cleanup after de-registering it. On devices currently
using fasboot, musb-new is usually initialized earlier, but some other boards
might need the board_usb_init call to properly initialize musb-new.
This requires adding an argument (the USB controller index) to the fastboot
command, as it is currently done with other USB download gadget functions.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
Test HW: Odroid_XU3 (Exynos5422), trats (Exynos4210)
USB download gadget functions such as thor and dfu have a separate config option
for the USB gadget part of the code, independent from the command part.
This switches the fastboot USB gadget to the same scheme, for better
consistency.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
Test HW: Odroid_XU3 (Exynos5422), trats (Exynos4210)
This introduces a coherent scheme for naming USB download gadget and functions
config options. The download USB gadget config option is moved to
CONFIG_USB_GADGET_DOWNLOAD for better consistency with other gadgets and each
function's config option is moved to a CONFIG_USB_FUNCTION_ prefix.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
Test HW: Odroid_XU3 (Exynos5422), trats (Exynos4210)
Remove LS102XA immap header inclusion from xhci fsl driver.
It removes redefinition warnings when built for platforms
other than LS102XA
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Move USB controller Base address mapping from ls102xa immap
to fsl xhci header. This is required to remove any warnings when
controller base addresses are mapped for multiple platforms
in their respective files.
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
This adjusts (micro)frame length to appropriate value thus
avoiding USB devices to time out over a longer run
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Some drivers may want to implement this method for some of their devices but
not for others. So it is not possible to just leave the operation out of
the table. Drivers could get around this by masquerading as two separate
drivers but that seems unpleasant.
Allow the driver to return an error when it does not want to process the
write_hwaddr() method.
Signed-off-by: Simon Glass <sjg@chromium.org>
This USB Ethernet driver is quite widely use. Allow it to work with
CONFIG_DM_ETH enabled. Most of the code remains common but there is a new
packet receive flow which is handled specially.
Signed-off-by: Simon Glass <sjg@chromium.org>
Support driver model in this driver. This uses the normal USB driver search
mechanism. Any EHCI controllers will be set up as they are found during
usb_init().
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Now that the RTL8169 driver warning is fixed we can drop this. The incorrect
value is causing problems with USB EHCI.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
In Linux USB_DEVICE() is used to declare a USB device by vendor/device ID.
We should follow the same convention in U-Boot. Rename the existing
USB_DEVICE() macro to U_BOOT_USB_DEVICE() and bring in the USB_DEVICE()
macro from Linux for use in U-Boot.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present USB Ethernet does not work with CONFIG_DM_ETH. Add driver model
support to this feature, so that it can work alongside other Ethernet
devices with driver model.
It was found that quite a bit of code is common in most of the USB Ethernet
drivers. Add this code to the common layer to reduce the amount of duplicate
code needed in USB Ethernet drivers when CONFIG_DM_ETH is used.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Some devices can take a long time to work out whether they have a new packet
or now. For example the ASIX USB Ethernet dongle can take 5 seconds to do
this, since it waits until it gets a new packet on the wire before allowing
the USB bulk read packet to be submitted.
At present with driver mode the Ethernet receive code reads 32 packets. This
can take a very long time if we must wait for all 32 packets. The old code
(before driver model) worked by reading a single set of packets from the USB
device, then processing all the packets with in. It would be nice to use
the same behaviour with driver model.
Add a flag to the receive method which indicates that the driver should try
to find a packet if available, by consulting the hardware. When the flag is
not set, it should just return any packet data it has already received. If
there is none, it should return -EAGAIN so that the loop will terminate.
Signed-off-by: Simon Glass <sjg@chromium.org>
If driver model is used for Ethernet then USB Ethernet does not build. This
can be made to work with driver model is used for USB also. Add #ifdef logic
to make this clear when building.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
It is useful to be able to find the full PCI address (bus, device and
function) for a PCI device. Add a function to provide this.
Adjust the existing code to use this.
Signed-off-by: Simon Glass <sjg@chromium.org>
This driver is used by the Intel Minnowmax board. Convert it to driver model
so it can use the new Ethernet implementation.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present all PCI devices must be present in the device tree in order to
be used. Many or most PCI devices don't require any configuration other than
that which is done automatically by U-Boot. It is inefficent to add a node
with nothing but a compatible string in order to get a device working.
Add a mechanism whereby PCI drivers can be declared along with the device
parameters they support (vendor/device/class). When no suitable driver is
found in the device tree the list of such devices is consulted to determine
the correct driver. If this also fails, then a generic driver is used as
before.
The mechanism used is very similar to that provided by Linux and the header
file defintions are copied from Linux 4.1.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Add device-model support to the musb-host u-boot glue, note this only
adds device-model support to the musb-core glue code, it does not add
support for device-model to any of the SoC specific musb glue code.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Simon Glass <sjg@chromium.org>
Add a musb_host_data struct to hold all the global data host related musb
data. This is a preparation patch for adding device-model support.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Simon Glass <sjg@chromium.org>
Rename and wrap the usb host API public functions, this is a preparation
patch for adding device-model support.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Simon Glass <sjg@chromium.org>
When building with CONFIG_DM_USB=y struct usb_device does not have a parent
pointer. This commit adds support to the musb code to deal with this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Simon Glass <sjg@chromium.org>
Allow musb_platform_enable to return an error code and propagate it up to
usb_lowlevel_init().
This allows moving the checks for an external vbus being present to be
moved from platform_init to platform_enable, so that the user can unplug a
charger, plug in a host adapter with a usb-device, do a "usb reset" and
have things working.
This also allows adding a check for the id-pin to platform_enable, so that
it can short circuit the 1s delay in usb_lowlevel_init() when no host cable
is plugged in and thus waiting for a device to show up is useless.
Note that all the changes to code shared with the kernel are wrapped in
the kernel.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Simon Glass <sjg@chromium.org>
On some single port (otg) controllers there is no emulated root hub, so
the first child (if any) may be one of: UCLASS_MASS_STORAGE,
UCLASS_USB_DEV_GENERIC or UCLASS_USB_HUB.
All three of these (and in the future others) are suitable for our
purposes, remove the check for the device being a hub, and add a check to
deal with the fact that there may be no child-dev.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Simon Glass <sjg@chromium.org>
Allow usb uclass host drivers to implement usb_reset_root_port, this is
used by single port usb hosts which do not emulate a hub, such as otg
controllers.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Simon Glass <sjg@chromium.org>
Now that we unbind usb devices from usb_stop() usb_find_child() is
only necessary to deal with emulated usb devices.
Rename it to make this clear and add a #ifdef to make it a nop in
other cases.
Note the #ifdef turns usb_find_emul_child() into a nop, rather then not
building it and adding another #ifdef to the caller, this is done this way
because adding a #ifdef to the caller is somewhat hairy.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Simon Glass <sjg@chromium.org>
On an usb stop instead of leaving orphan usb devices behind simply remove
them.
The result of this commit is best seen in the output of "dm tree" after
plugging out an usb hub with 2 devices plugges in and plugging in a keyb.
instead, before this commit the output would be:
usb [ + ] `-- sunxi-musb
usb_hub [ ] |-- usb_hub
usb_mass_st [ ] | |-- usb_mass_storage
usb_dev_gen [ ] | `-- generic_bus_0_dev_3
usb_dev_gen [ + ] `-- generic_bus_0_dev_1
Notice the non active usb_hub child and its 2 non active children. The
first child being non-active as in this example also causes usb_get_dev_index
to return NULL when probing the first child, which results in the usb kbd
code not binding to the keyboard.
With this commit in place the output after swapping and "usb reset" is:
usb [ + ] `-- sunxi-musb
usb_dev_gen [ + ] `-- generic_bus_0_dev_1
As expected, and usb_get_dev_index works properly and the keyboard works.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Simon Glass <sjg@chromium.org>
Document that mixing DM_DEVICE_REMOVE and DM_USB is a bad idea, and also why
this is a bad idea.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Simon Glass <sjg@chromium.org>
last_child was abused by the old usb code to first store 1 if the
usb_device was not the root of the usb tree, and then later on re-used
to store whether or not the usb_device is actually the last child.
The dm-usb code was always setting it to actually reflect the last-child
status which is wrong for the last child leading to output like this:
USB device tree:
1 Hub (12 Mb/s, 100mA)
| ALCOR USB Hub 2.0
|
| 2 Mass Storage (12 Mb/s, 100mA)
| USB Flash Disk 4C0E960F
|
+-3 Human Interface (1.5 Mb/s, 100mA)
SINO WEALTH USB Composite Device
Instead of this:
USB device tree:
1 Hub (12 Mb/s, 100mA)
| ALCOR USB Hub 2.0
|
+-2 Mass Storage (12 Mb/s, 100mA)
| USB Flash Disk 4C0E960F
|
+-3 Human Interface (1.5 Mb/s, 100mA)
SINO WEALTH USB Composite Device
This commit fixes this by first checking that the device is not root,
and then setting last_child. This commit also updates the old code to not
abuse the last_child variable to store the root check result.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Simon Glass <sjg@chromium.org>
These functions are useful to remove all children from an usb bus before
rescanning the bus. Give them a better name and export them.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Simon Glass <sjg@chromium.org>
Add an usb_device parameter to usb_reset_root_port so that it knows which
root-port it is resetting. This is necessary for proper device-model support
for usb_reset_root_port.
Also remove a duplicate declaration of usb_reset_root_port() from usb.h .
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Simon Glass <sjg@chromium.org>
Pass the usb_device instead of the portnr to usb_legacy_port_reset and
rename it to usb_hub_port_reset as there is nothing legacy about it.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Simon Glass <sjg@chromium.org>
Drop the unneeded portnr function argument, the portnr is part of the
usb_device struct which is passed via the dev argument.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Simon Glass <sjg@chromium.org>
The device-model usb_legacy_port_reset function calls the device-model
usb_port_reset function which is a 1 on 1 copy of the non dm
usb_legacy_port_reset and this is the only use of usb_port_reset in all
of u-boot.
Drop both, and alway use the usb_legacy_port_reset() version in
common/usb.c .
Also while at it make it static as it is only used in common/usb.c .
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Simon Glass <sjg@chromium.org>
As you see in driver/Makefile, Kbuild descends into the driver/core/
directory only when CONFIG_DM is enabled.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
Currently, DM_FLAG_ACTIVATED is set twice; before calling
uclass_pre_probe_device() and again before calling drv->probe().
It looks like Simon's intention is the first one.
The DM_FLAG_ACTIVATED was moved twice, by commit 02eeb1bbb1
(dm: core: Mark device as active before calling its probe()
method), and then by commit 206d4d2b4b (dm: core: Mark device
as active before calling uclass probe() methods).
The first marking was added by the last move.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
The command "dm uclass" tries to display all the UClasses, but
some of them might be disabled by Kconfig.
The function do_dm_dump_uclass() iterates over all the UClass IDs
and calls uclass_get() for each of them. Then, it displays annoying
message "Cannot find uclass for id ..." every time it fails to get
the UClass.
As a result, we get much noisier log for the "dm uclass" command.
=> dm uclass
uclass 0: root
- * root_driver @ bfb54028, seq 0, (req -1)
Cannot find uclass for id 1: please add the UCLASS_DRIVER() ...
Cannot find uclass for id 2: please add the UCLASS_DRIVER() ...
Cannot find uclass for id 3: please add the UCLASS_DRIVER() ...
Cannot find uclass for id 4: please add the UCLASS_DRIVER() ...
Cannot find uclass for id 5: please add the UCLASS_DRIVER() ...
Cannot find uclass for id 6: please add the UCLASS_DRIVER() ...
This commit suppresses these warnings.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
This function can only handle a syscon device. It is possible that someone
will make a mistake, so add a check for this.
Also we should return -ENODEV when a device cannot be found, so update the
syscon_get_regmap_by_driver_data() to follow this convention.
Signed-off-by: Simon Glass <sjg@chromium.org>
Some functions can return ERR_PTR(errval). Add a unit test macro to check
that no error is returned in a pointer.
Signed-off-by: Simon Glass <sjg@chromium.org>
Each sandbox peripheral should have a size as well as a base address. This
is required for regmaps to work, so make this change for all nodes that have
an address.
Signed-off-by: Simon Glass <sjg@chromium.org>
We normally use -ENODEV for a missing device, rather than -ENOENT. The
latter is reserved for when we have a device but cannot find something
within it.
Also avoid looking at the root LED device since it is only a container.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a test to confirm that we can probe this device. Since there is no
MMC stack support in sandbox at present, this is as far as the test goes.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add tests that confirm that the drivers work as expected, and we can walk
through the available reset types trying to reset the board.
Signed-off-by: Simon Glass <sjg@chromium.org>
Move sandbox over to use the reset uclass for reset, instead of a direct
call to do_reset(). This allows us to add tests.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add drivers for sandbox. One can only perform a warm reset (which does
nothing). The other can perform a cold reset or a power reset (the
latter will quit U-Boot). These can be used for testing the reset uclass.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a new reset_walk_halt() function to cause a reset and then halt on
failure. The reset_walk() function returns an error code.
This is needed for testing since otherwise U-Boot will halt in the middle
of a test.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add settings for the last reset generated, and the types of resets which
are permitted. This will be used for testing.
Signed-off-by: Simon Glass <sjg@chromium.org>
All driver model tests have a dm_test_ prefix. Ignore it when matching a
test name. This makes it easier to run individual tests, like this:
./sandbox/u-boot -d ./sandbox/arch/sandbox/dts/test.dtb \
-c "ut dm clk_periph"
We can use 'clk_periph' instead of 'dm_test_clk_periph'.
Also print a message if the requested test is not found.
Signed-off-by: Simon Glass <sjg@chromium.org>
We should guide people more strongly towards device tree to avoid the
proliferation of platform data structures. Add documentation to the driver
model README, and also the platform data header file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Use the common function to obtain the number from the end of the string,
instead of a local function. Also tweak the position of a debug() statement.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Clocks are an important feature of platforms and have become increasing
complex with time. Most modern SoCs have multiple PLLs and dozens of clock
dividers which distribute clocks to on-chip peripherals.
Some SoC implementations have a clock API which is private to that SoC family,
e.g. Tegra and Exynos. This is useful but it would be better to have a
common API that can be understood and used throughout U-Boot.
Add a simple clock API as a starting point. It supports querying and setting
the rate of a clock. Each clock is a device. To reduce memory and processing
overhead the concept of peripheral clocks is provided. These do not need to
be explicit devices - it is possible to write a driver that can adjust the
I2C clock (for example) without an explicit I2C clock device. This can
dramatically reduce the number of devices (and associated overhead) in a
complex SoC.
Clocks are referenced by a number, and it is expected that SoCs will define
that numbering themselves via an enum.
Signed-off-by: Simon Glass <sjg@chromium.org>
Since we want clk_ops to be used in U-Boot as a whole, rename the Zynq
version until it can be converted to driver model.
Signed-off-by: Simon Glass <sjg@chromium.org>
It is common for system reset to be available at multiple levels in modern
hardware. For example, an SoC may provide a reset option, and a board may
provide its own reset for reasons of security or thoroughness. It is useful
to be able to model this hardware without hard-coding the behaviour in the
SoC or board. Also there is a distinction sometimes between resetting just
the CPU (leaving GPIO state alone) and resetting all the PMICs, just cutting
power.
To achieve this, add a simple system reset uclass. It allows multiple devices
to provide reset functionality and provides a way to walk through them,
requesting a particular reset type until is it provided.
Signed-off-by: Simon Glass <sjg@chromium.org>
Some functions called by mkimage would like to know the output file size.
Initially this is the same as the input file size, but it may be affected by
adding headers, etc.
Add this information to the image parameters.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
As a debug option, add positive confirmation that SPL has completed
execution. This can help with diagnosing the location of unexpected hangs.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add an spl_init() function that does basic init such that board_init_f() can
use simple malloc(), device tree and driver model. Each one is set up only
if enabled for SPL.
Note: We really should refactor SPL such that there is a single
board_init_f() and rename the existing weak board_init_f() functions
provided by boards, calling them from the single board_init_f().
Signed-off-by: Simon Glass <sjg@chromium.org>
It can be quite confusing with a new platform to figure out why the device
tree cannot be located. Add some debug information for this case.
Signed-off-by: Simon Glass <sjg@chromium.org>
Split out the code in fdtdec which finds a number at the end of a string. It
can be useful in other situations.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add an implementation of RC4. This will be used by Rockchip booting but may
be useful in other situations.
Signed-off-by: Simon Glass <sjg@chromium.org>
Since Rockchip requires 32-bit serial access, add this to the driver.
Refactor a little to make this easier.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add support for a driver which sets up DRAM and can return information about
the amount of RAM available. This is a first step towards moving RAM init
to driver model.
Signed-off-by: Simon Glass <sjg@chromium.org>
This bloats the code size quite a bit and is less useful in SPL where there
is no command line.
Avoid including this code in SPL.
Signed-off-by: Simon Glass <sjg@chromium.org>
It is a common requirement to update some PMIC registers. Provide some
simple convenience functions to do this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
To reduce unnecessary code size in an uncommon code path, use debug()
where possible(). The driver returns an error which indicates failure.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
The device tree provides information about which regulators should be
on at boot, or always on. Use this to set them up automatically.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
The regulator_autoset() function mixes printf() output and PMIC adjustment
code. It provides a boolean to control the output. It is better to avoid
missing logic and output, and this permits a smaller SPL code size. So
split the output into a separate function.
Also rename the function to have a by_name() suffix, since we would like
to be able to pass a device when we know it, and thus avoid the name
search.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Decide when the regulator is set up whether we want to auto-set the voltage
or current. This avoids the complex logic spilling into the processing code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
This is not user input (i.e. from the command line). It should be possible
to get the case correct and avoid the case-insensitive match. This will
help avoid sloppy device tree setups.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
It took a little while to figure this out, so this patch adds documentation
to help the next person who needs to do this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add basic support for MMC, providing a uclass which can set up an MMC
device. This allows MMC drivers to move to using driver model.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a simple uclass for LEDs, so that these can be controlled by the device
tree and activated when needed. LEDs are referred to by their label.
This implementation requires a driver for each type of LED (e.g GPIO, I2C).
Signed-off-by: Simon Glass <sjg@chromium.org>
Many SoCs have a number of system controllers which are dealt with as a
group by a single driver. It is a pain to have to add lots of compatible
strings and/or separate drivers for each. Instead we can identify the
controllers by a number and request the address of the one we want.
Add a simple implementation of this which can be used by SoC driver code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a simple implementaton of register maps, supporting only direct I/O
for now. This can be enhanced later to support buses which have registers,
such as I2C, SPI and PCI.
It allows drivers which can operate with multiple buses to avoid dealing
with the particulars of register access on that bus.
Signed-off-by: Simon Glass <sjg@chromium.org>
This function can be used for testing to manually request a GPIO for use,
without resorting to the legacy GPIO API.
Signed-off-by: Simon Glass <sjg@chromium.org>
In some rare cases it is useful to be able to locate a device given a device
tree node offset. An example is when you have an alias that points to a node
and you want to find the associated device. The device may be SPI, MMC or
something else, but you don't need to know the uclass to find it.
Add a function to do a global search for a device, given its device tree
offset.
Signed-off-by: Simon Glass <sjg@chromium.org>
To avoid bloating SPL code, use debug() where possible in the driver model
core code. The error code is already returned, and can be investigated as
needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
In SPL it is sometimes useful to be able to obtain a dump of the current
driver model state. Since commands are not available, provide a way to
directly call the functions to output this information.
Adjust the existing commands to use these functions.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present printf() skips output if it can see there is no console. This
is really just an optimisation, and is not necessary. Also it is currently
incorrect in some cases. Rather than update the logic, just remove it so
that we don't need to keep it in sync.
Signed-off-by: Simon Glass <sjg@chromium.org>
When there is no console ready, allow the debug UART to be used for output.
This makes debugging of early code considerably easier.
Signed-off-by: Simon Glass <sjg@chromium.org>
This does not actually help any current arch. For x86 it makes it harder
to call (requires stack) and for ARM it has no effect. Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
U-Boot uses structures for hardware access so it is important that these
structures are correct. Add a way of asserting that a structure member is
at a particular offset. This can be created using the datasheet for the
hardware.
This implementation uses Static_assert() since BUILD_BUG_ON() only works
within functions.
Signed-off-by: Simon Glass <sjg@chromium.org>
Driver-model I2C drivers can be picked up by the linker script rule for
legacy drivers. Change the order to avoid this.
We could make the legacy code depend on !CONFIG_DM_I2C but that is not
necessary and it is good to keep conditions to a minimum.
Signed-off-by: Simon Glass <sjg@chromium.org>
The SPL device tree size must be minimised to save memory. Only include
properties that are needed by SPL - this is determined by the presence
of the "u-boot,dm-pre-reloc" property. Also remove a predefined list of
unused properties from the nodes that remain.
Signed-off-by: Simon Glass <sjg@chromium.org>
This tool allows us to extract subsets of a device tree file. It is used by
the SPL vuild, which needs to cut down the device tree size for use in
limited memory.
This tool was originally written for libfdt but it has not been accepted
upstream, so for now, include it in U-Boot. Several utilfdt library
functions been included inline here.
If fdtgrep is eventually accepted in libfdt then we can bring that version
of libfdt in here, and drop fdtgrep (requiring that fdtgrep is provided by
the user).
If it is not accepted then another approach would be to write a special
tool for chopping down device tree files for SPL. While it would use the
same libfdt support, it would be less code than fdtgrep.c because it would
not have general-purpose functions.
Another approach (which was used with v1 of this series) is to sprinkler all
the device tree files with #ifdef. I don't like that idea.
Signed-off-by: Simon Glass <sjg@chromium.org>
These have been sent upstream but not accepted to libfdt. For now, bring
these into U-Boot to enable fdtgrep to operate. We will use fdtgrep to
cut device tree files down for SPL.
Signed-off-by: Simon Glass <sjg@chromium.org>
Property names are stored in a string table. When a node property is
removed, the string table is not updated since other nodes may have a
property with the same name.
Thus it is possible for the string table to build up a number of unused
strings. Add a function to remove these. This works by building a new device
tree from the old one, adding strings one by one as needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Offer to display the available image types in help. Also, rather than
hacking the genimg_get_type_id() function to display a list of types,
do this in the tool. Also, sort the list.
The list of image types is quite long, and hard to discover. Print it out
when we show help information.
Signed-off-by: Simon Glass <sjg@chromium.org>
Drystone provides a convenient sanity check that the CPU is running at full
speed. Add this as a command which can be enabled as needed.
Note: I investigated using Coremark for this but there was a license
agreement and I could not work out if it was GPL-compatible.
Signed-off-by: Simon Glass <sjg@chromium.org>
When final MMU table is setup in DDR, TCR attributes must match
those of the memroy for cacheability and shareability.
Signed-off-by: Zhichun Hua <zhichun.hua@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
For ARMv8, outer shareable is 0b10, inner shareable is 0b11 at bit
position [13:12] of TCR_ELx register.
Signed-off-by: Zhichun Hua <zhichun.hua@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Freescale DSPI driver has been converted to Driver Model.
The new driver depends on OF_CONTROL, DM, DM_SPI.
This patch enable FSL_DSPI and its dependence configure options.
Signed-off-by: Haikun Wang <haikun.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
DSPI has pin muxing with SDHC and other IPs, this patch check the
value of RCW SPI_PCS_BASE and SPI_BASE_BASE fields, it also check
the "hwconfig" variable. If those pins are configured to DSPI and
"hwconfig" enable DSPI, set the BRDCFG5 of QIXIS CPLD to configure
the routing to on-board SPI memory. Otherwise will configure to SDHC.
DSPI is enabled in "hwconfig" by appending "dspi", eg.
setenv hwconfig "$hwconfig;dspi"
Signed-off-by: Haikun Wang <Haikun.Wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
DSPI has pin muxing with SDHC and other IPs, this patch check the
value of RCW SPI_PCS_BASE and SPI_BASE_BASE fields, it also check
the "hwconfig" variable. If those pins are configured to DSPI and
"hwconfig" enable DSPI, set the BRDCFG5 of QIXIS FPGA to configure
the routing to on-board SPI memory. Otherwise will configure to SDHC.
DSPI is enabled in "hwconfig" by appending "dspi", eg.
setenv hwconfig "$hwconfig;dspi"
Signed-off-by: Haikun Wang <haikun.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Bring in required device tree files for ls2085a from Linux. These are
initially unchanged and have a number of pieces not needed by U-Boot.
Signed-off-by: Haikun Wang <Haikun.Wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
As SCFG_ENDIANCR register is added to choose little-endian or big-endian
for audio IPs on Rev2.0 silion, little-endian mode is selected.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Base on PSCI services, implement CPU_ON/CPU_OFF for ls102xa platform.
Tested on LS1021AQDS, LS1021ATWR.
Test CPU hotplug times: 60K
Test kernel boot times: 1.2K
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Acked-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
timer_wait is moved from sunxi/psci_sun7i.S, and it can be converted
completely into a reusable armv7 generic timer. LS1021A will use it
as well.
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: York Sun <yorksun@freescale.com>
As the function 'sprintf' does not check buffer boundaries but outputs
to the buffer 'enet' of fixed size (16), this patch removes the function
'sprintf', and uses 'strcpy' instead. It will assign the character
arrays 'enet' and 'phy' the corresponding character strings.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Linux itb image size has been increased from 30MB.
So updating kernel_size to 40MB in env variable.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Change infinite loop mechanism to timer based polling for QBMAN release in
ldpaa_eth_rx.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Polling of TX conf frames is not a mandatory option.
Packets can be transferred via WRIOP without TX conf frame.
Configure ldpaa_eth driver to use TX path without confirmation frame
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Volatile command does not return frame immidiately, need to wait till a frame
is available in DQRR. Ideally it should be a blocking call.
Add timeout handling for DQRR frame instead of retry counter.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Do not immediately return if the enqueue function returns -EBUSY; re-try
mulitple times.
if timeout occures, release the buffer.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This patch adds the infrastructure to update device
tree nodes to convey SMMU stream IDs in the device
tree. Fixups are implemented for PCI controllers
initially.
Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Stream IDs on ls2085a devices are not hardwired and are
programmed by sw. There are a limited number of stream IDs
available, and the partitioning of them is scenario dependent.
This header defines the partitioning between legacy, PCI,
and DPAA2 devices.
Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Management complex major version should match to the firmware present in flash.
Return error during mismatch of major version.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Update flibs changes to mc-0.6.0.1 for dpmang, dprc, dpni and dpio objects
Also rename qbman_portal_ce/ci_paddr to qbman_portal_ce/ci_offset in
dpio_attr. These are now offsets from the SoC QBMan portals base.
Signed-off-by: J. German Rivera <German.Rivera@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Flush buffer before releasing to BMan after TX_conf to ensure, the core does
not have any cachelines that the WRIOP will DMA to.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Signed-off-by: Stuart Yoder <stuart.yoder at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
The agreed split of the top of memory is 256M for debug server and 256M
for MC. This patch implements the split.
In addition, the MC mem must be 512MB aligned, so the amount of memory
to hide must be 512MB to achieve that alignment.
Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This patch updates the setting of required bits for A57 cores erratas
- 828024 and 826974
Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com>
Signed-off-by: Dai Haruki <dai.haruki at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This patch fixes the DDR hide logic for LS2085a, correcting the way
the Debug Server FW and MC FW images are placed on the top of system
DDR and how the rest of the system DDR space is made visibile to Linux.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Update SoC README to provide details of
- Memory regions
- Memory used by MC and Debug server
Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This patch allows u-boot to expose the complete DDR region(s) to Linux
(after subtracting the memory hidden via MEM_TOP_HIDE mechanism).
This allows the u-boot to support the 48-bit VA support provided by
ARM64 Linux in flavors 3.18 and above, by passing the appropriate
'memory' DTS nodes.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Board rev C and earlier has duplicated SPD address on 2nd DDR
controller slots. It is fixed on rev D and later. SPD addresses
need to be updated accordingly.
Signed-off-by: York Sun <yorksun at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
In case SPD address changes between board revisions, updating SPD
address can be called from board file.
Signed-off-by: York Sun <yorksun at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
LS2085A supports 6 personalities i.e. LS2045AE, LS2045A, LS2080AE,
LS2080A, LS2085AE and LS2085A personlities.
Instead of hard-coding, board name should change as per selected
personality.
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This patch adds support to print out the SoC personality.
Freescale LS20xx SoCs (compliant to Chassis-3 specifications) can
have 6 personalities: LS2045AE, LS2045A, LS2080AE, LS2080A,
LS2085AE and LS2085A
Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
DDR speed should be in MT/s, not MHz.
Signed-off-by: York Sun <yorksun at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
As per updated board document, no need to substract 1 from arch[BRD]
bit field. Default value + 'A' represents the board revision.
So update board version print logic to reflect the same.
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
SYSTEM ID EPPROM always store SYSTEM version info in big endian format.
SoC with ARM or PowerPC core should read/write version info from eeprom
in BIG endian format.
So use cpu-specific APIs to read SYSTEM version.
Signed-off-by: Jaiprakash Singh <b44839 at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Increases the kernel size supported for LS2085A platforms:-
- Update environment variables
- Add ramdisk_size in bootargs env variable
- Define CONFIG_SYS_BOOTM_LEN to 64MB
Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Primary Mux on I2C1 controller has slave address as 0x75.
So update its address.
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
FPGA BRDCFG9[SFP_TX] should be clear in order to enable XFI ports.
Signed-off-by: Dai Haruki <Dai.Haruki at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
call ft_pci_setup() to disable PCIe dts node if corresponding
PCIe controller is disabled according to RCW
Signed-off-by: Minghuan Lian <Minghuan.Lian at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Compatible field "fsl,20851a-pcie" is not correct.
So update it to "fsl,ls2085a-pcie"
Signed-off-by: Minghuan Lian <Minghuan.Lian at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
SerDes Protocol 0x49 enables 4 SGMII, PEX4, SATA1 and SATA2.
Add support of 0x49 SerDes protocol to enable 4SGMII on slot4 of
ls2085aqds platform.
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Enable "date" command for QDS and RDB boards
Signed-off-by: Priyanka Jain <Priyanka.Jain at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Add hwconfig setting for eSDHC since it shares some pins with other
IP block.
Signed-off-by: Yangbo Lu <yangbo.lu at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Add support for board eth initialization and support for loading phy
firmware. PHY firmware needs to be loaded from board_eth_init() because
all the MACs are not initialized by ldpaa_eth driver.
Signed-off-by: pankaj chauhan <pankaj.chauhan at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Currently, this function returns a positive value on error,
so we never know whether this function has succeeded or failed.
For example, if the given property is not found, fdt_getprop()
returns -FDT_ERR_NOTFOUND, and then this function inverts it,
i.e., returns FDT_ERR_NOTFOUND (=1).
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Fixes: bc4147ab2d ("fdt: Add a function to count strings")
Acked-by: Simon Glass <sjg@chromium.org>
As mentioned in the comment block in include/libfdt.h,
fdt_get_string_index() is supposed to return a negative value
on error.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Fixes: 5094eb408a ("fdt: Add functions to retrieve strings")
Acked-by: Simon Glass <sjg@chromium.org>
Looks like this comment was copied from that of
fdt_get_string_index().
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Fixes: 5094eb408a ("fdt: Add functions to retrieve strings")
Acked-by: Simon Glass <sjg@chromium.org>
Commit 90fbee3e40 ("cmd_fdt: Actually fix fdt command in sandbox")
changed the format(from hex address to unsigned long) in which "fdtaddr"
is saved . However do_fdt continues reads the "fdtaddr" assuming it to
be in hex format. This may lead to fdt being either loaded or attempted
to load at erroneous address generating fault if the address is out of
memory.
This patch changes back the format to hex while saving the "fdtaddr"
as it was done before.
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Hua Yanghao <huayanghao@gmail.com>
Cc: Heiko Schocher <hs@denx.de>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Simon Glass <sjg@chromium.org>
Fix below build warnings on armv8,
drivers/spi/fsl_dspi.c: In function ‘fsl_dspi_ofdata_to_platdata’:
drivers/spi/fsl_dspi.c:667:2:
warning: format ‘%x’ expects argument of type ‘unsigned int’,
but argument 2 has type ‘fdt_addr_t’ [-Wformat=]
debug("DSPI: regs=0x%x, max-frequency=%d, endianess=%s, num-cs=%d\n",
^
lib/fdtdec.c: In function ‘fdtdec_get_addr_size’:
lib/fdtdec.c:105:4:
warning: format ‘%lx’ expects argument of type ‘long unsigned int’,
but argument 3 has type ‘fdt_size_t’ [-Wformat=]
debug("addr=%08lx, size=%08lx\n",
^
Signed-off-by: Haikun Wang <haikun.wang@freescale.com>
Acked-by: Simon Glass <sjg@chromium.org>
Avoid clearing the reg property in the memory DT node if no memory
banks have been specified for a board (CONFIG_NR_DRAM_BANKS == 0).
This allows boards to let U-Boot skip the DT memory tinkering in case
other firmware has already setup the node properly before.
This should be safe as all callers of fdt_fixup_memory_banks that use
a computed <banks> value put at least 1 in there.
Add some documentation comments to the header file.
Signed-off-by: Andre Przywara <osp@andrep.de>
Acked-by: Simon Glass <sjg@chromium.org>
Currently PCI expansion ROM address is assigned by a call to
pciauto_setup_rom() outside of the pci auto config process.
This does not work when expansion ROM is on a device behind
PCI bridge where bridge's memory limit register was already
programmed to a value that does not cover the newly assigned
expansion ROM address. To fix this, we should configure the
ROM address during the auto config process.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
This driver was originally added to support the native IDE mode for
Intel chipset, however it has some bugs like not supporting ATAPI
devices, endianness issue, or even broken build when CONFIG_LAB48.
Given no board is using this driver as of today, rather than fixing
all these issues we just remove it from the source tree.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Update crownbay_defconfig and minnowmax_defconfig with 'savedefconfig'
result so that the config option order matches Kconfig.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
On 32-bit machine strtol() returns LONG_MAX which is 0x7fffffff,
which is wrong for u-boot.rom components like u-boot-x86-16bit.bin.
Change to use strtoll() so that it works on both 32-bit and 64-bit
machines.
Reported-by: Fei Wang <wangfei.jimei@gmail.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
To try to reduce the pain of confusion of binary blobs, add MD5 checksums
for the current versions. This may worsen the situation as new versions
appear, but it should still be possible to obtain these versions, and thus
get a working setup.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Commit afbbd413a fixed this for non-driver-model. Make sure that the driver
model code handles this also.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Adjust minnowmax to use driver model for PCI. This requires adding a device
tree node to specify the ranges, removing the board-specific PCI code and
ensuring that the host bridge is configured.
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
This driver should use the x86 PCI configuration functions. Also adjust its
compatible string to something generic (i.e. without a vendor name).
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The layout of the ROM is a bit hard to discover by reading the code. Add
a table to make it easier.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The logic is incorrect and currently has no effect. Fix it so that we can
write to SPI flash, since by default it is write-protected.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
The status register on ICH9 is a single byte, so use byte access when
writing to it, to avoid updating the control register also.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Enable graphics support on Intel Crown Bay board With the help of
vgabios for Intel TunnelCreek IGD. Tested with an external LVDS
panel connected to X4 connector and SDVO adapter connected to X9
connector on the board.
Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
MARK_GRAPHICS_MEM_WRCOMB is not referenced anywhere in the code,
hence remove it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Move X86_OPTION_ROM_FILE & X86_OPTION_ROM_ADDR to arch/x86/Kconfig
and rename them to VGA_BIOS_FILE & VGA_BIOS_ADDR which depend on
HAVE_VGA_BIOS. The new names are consistent with other x86 binary
blob options like HAVE_FSP/FSP_FILE/FSP_ADDR.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Print the meaningful base address and mask of an MTRR range without showing
the memory type encoding or valid bit.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Per CPUID:80000008h result, the maximum physical address bits of
TunnelCreek processor is 32 instead of default 36. This will fix
the incorrect decoding of MTRR range mask.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
We should setup fixed range MTRRs for some legacy regions like VGA
RAM and PCI ROM areas as uncacheable. Note FSP may setup these to
other cache settings, but we can override this in x86_cpu_init_f().
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
The TunnelCreek IGD VBE reports 32-bit color depth regardless 24-bit
color depth is configured. Since 24-bit mode already uses 4 bytes
internally, it should be OK to just add this option in switch case.
Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
We should allow pci config read/write to host bridge (b.d.f = 0.0.0)
in the int1a_handler() which is a valid pci device.
Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
PCI option rom may use different SS during its execution, so it is not
safe to assume esp pointed to the same location in the protected mode.
Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Per PCI spec, VGA device reports its class as standard 030000h in
its configuration space, so we can use it to determine if we need
run option rom instead of testing the supported vendor/device ids.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
The sub-bus passed to pciauto_prescan_setup_bridge() is incorrect. Fix it
so that sub-buses are numbered correctly.
Signed-off-by: Simon Glass <sjg@chromium.org>
Only the PCI controller has access to the PCI region information. Make sure
to use the controller (rather than any attached bridges) when configuring
devices.
This corrects a failure to scan and configure devices when driver model is
enabled for PCI.
Also add a comment to explain the problem.
Signed-off-by: Simon Glass <sjg@chromium.org>
So far interrupt routing works pretty well for any on-chip devices
on Intel Crown Bay. When inserting any PCIe card to any PCIe slot,
Linux kernel is smart enough to do interrupt swizzling and figure
out device's irq using its parent bridge's interrupt routing info
all the way up to its root port. In U-Boot all PCIe root ports'
interrupts were routed to PIRQ E/F/G/H before, while actually all
PCIe downstream ports received INTx are routed to PIRQ A/B/C/D
directly and not configurable. Now we change this mapping so that
any external PCIe device can work correctly.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Document U-Boot multi-processor support as well as configuration
tables like SFI and MP tables for SMP OS kernel.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Implement write_mp_table() to create a minimal working MP table.
This includes an MP floating table, a configuration table header
and all of the 5 base configuration table entries. The I/O interrupt
assignment table entry is created based on the same information used
in the creation of PIRQ routing table from device tree. A check
duplicated entry logic is applied to prevent writing multiple I/O
interrupt entries with the same information.
Use a Kconfig option GENERATE_MP_TABLE to tell U-Boot whether we
need actually write the MP table at the F seg, just like we did for
PIRQ routing and SFI tables. With MP table existence, linux kernel
will switch to I/O APIC and local APIC to process all the peripheral
interrupts instead of 8259 PICs. This takes full advantage of the
multicore hardware and the SMP kernel.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
The MP table provides a way for the operating system to support
for symmetric multiprocessing as well as symmetric I/O interrupt
handling with the local APIC and I/O APIC. We provide a bunch of
APIs for U-Boot to write the floating table, configuration table
header as well as base and extended table entries.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Remove inline for lapic access routines and expose lapic_read()
& lapic_write() as APIs to read/write lapic registers. Also move
stop_this_cpu() to mp_init.c as it has nothing to do with lapic.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
I/O APIC registers are addressed indirectly. Add io_apic_read() and
io_apic_write() routines to help register access. Two macros for I/O
APIC ID and version register offset are also added.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
There is no need to populate multiple irq info entries with the same
bus number and device number, but with different interrupt pin. We
can use the same entry to store all the 4 interrupt pin (INT A/B/C/D)
routing information to reduce the whole PIRQ routing table size.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
In fill_irq_info() pci device's function number is written into
the table, however this is not really necessary. The function
number can be anything as OS doesn't care about this field,
neither does the PIRQ routing specification. Change to always
writing 0 as the function number.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
We should write correct bus number to the PIRQ routing table for the
irq router from device tree, instead of hard-coded zero.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
There are 4 usb ports on the Intel Crown Bay board, 2 of which are
connected to Topcliff usb host 0 and the other 2 connected to usb
host 1. USB devices inserted in the ports connected to usb host 1
cannot get detected due to wrong IRQ assigned to the controller.
Actually we need apply the PCI interrupt pin swizzling logic to all
devices on the Topcliff chipset when configuring the PIRQ routing.
This was observed on usb ports, but device 6 and 10 irqs are also
wrong. Correct them all together.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Currently CONFIG_DM_I2C is used in cmd_date.c for driver model,
but it should be actually CONFIG_DM_RTC.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Add driver model support to the mc146818 rtc driver. Also clean up
the driver a little bit for coding convention issues.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Intel Crown Bay board has a TunnelCreek processor which supports
hyper-threading. Add /cpus node in the crownbay.dts and enable
the MP initialization.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
(modified to remove error:
overriding the value of OF_CONTROL. Old value: "y", new value: "y")
This commit cleans up the lapic codes:
- Delete arch/x86/include/asm/lapic_def.h, and move register and bit
defines into arch/x86/include/asm/lapic.h
- Use MSR defines from msr-index.h in enable_lapic() and disable_lapic()
- Remove unnecessary stuff like NEED_LAPIC, X86_GOOD_APIC and
CONFIG_AP_IN_SIPI_WAIT
- Move struct x86_cpu_priv defines to asm/arch-ivybridge/bd82x6x.h, as
it is not apic related and only used by ivybridge
- Fix coding convention issues
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Currently lapic_setup() is called before calling mp_init(), which
then calls init_bsp() where it calls enable_lapic(), which was
already enabled in lapic_setup(). Hence move lapic_setup() call
into init_bsp() to avoid the duplication.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Most of the MP initialization codes in arch/x86/cpu/baytrail/cpu.c is
common to all x86 processors, except detect_num_cpus() which varies
from cpu to cpu. Move these to arch/x86/cpu/cpu.c and implement the
new 'get_count' method for baytrail and cpu_x86 drivers. Now we call
cpu_get_count() in mp_init() to get the number of CPUs.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Introduce a new method 'get_count' in the UCLASS_CPU ops to get
the number of CPUs in the system.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Move MAX_CPUS definition after SMP so that it shows below SMP in the
menuconfig. Also replace the leading spaces in the MAX_CPUS section
with tabs to conform coding standard.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
This commit does the following to clean up x86 cpu dm drivers:
- Move cpu_x86 driver codes from arch/x86/cpu/cpu.c to a dedicated
file arch/x86/cpu/cpu_x86.c
- Rename x86_cpu_get_desc() to cpu_x86_get_desc() to keep consistent
naming with other dm drivers
- Add a new cpu_x86_bind() in the cpu_x86 driver which does exactly
the same as the one in the intel baytrail cpu driver
- Update intel baytrail cpu driver to use cpu_x86_get_desc() and
cpu_x86_bind()
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
In cpu_get_info() it wrongly tests against cpu_ops->get_desc to see
if it is NULL. It should test against cpu_ops->get_info.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Rather than just 'ERROR', display the error code, which may be useful, at
least with driver model.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>
The call to FspInitEntry is done in arch/x86/lib/fsp/fsp_car.S so far.
It worked pretty well but looks not that good. Apart from doing too
much work than just enabling CAR, it cannot read the configuration
data from device tree at that time. Now we want to move it a little
bit later as part of init_sequence_f[] being called by board_init_f().
This way it looks and works better in the U-Boot initialization path.
Due to FSP's design, after calling FspInitEntry it will not return to
its caller, instead it jumps to a continuation function which is given
by bootloader with a new stack in system memory. The original stack in
the CAR is gone, but its content is perserved by FSP and described by
a bootloader temporary memory HOB. Technically we can recover anything
we had before in the previous stack, but that is way too complicated.
To make life much easier, in the FSP continuation routine we just
simply call fsp_init_done() and jump back to car_init_ret() to redo
the whole board_init_f() initialization, but this time with a non-zero
HOB list pointer saved in U-Boot's global data so that we can bypass
the FspInitEntry for the second time.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
Tested-by: Simon Glass <sjg@chromium.org>
Currently the FSP execution environment GDT is setup by U-Boot in
arch/x86/cpu/start16.S, which works pretty well. But if we try to
move the FspInitEntry call a little bit later to better fit into
U-Boot's initialization sequence, FSP will fail to bring up the AP
due to #GP fault as AP's GDT is duplicated from BSP whose GDT is
now moved into CAR, and unfortunately FSP calls AP initialization
after it disables the CAR. So basically the BSP's GDT still refers
to the one in the CAR, whose content is no longer available, so
when AP starts up and loads its segment register, it blows up.
To resolve this, we load GDT before calling into FspInitEntry.
The GDT is the same one used in arch/x86/cpu/start16.S, which is
in the ROM and exists forever.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
Tested-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Since buildman now includes most of the features of MAKEALL it is probably
time to talk about deprecating MAKEALL.
Comments welcome.
Signed-off-by: Simon Glass <sjg@chromium.org>
The temperature calculation must be typecasted to keep the compiler
from sign extending a negative value prior to division.
This fixes an issue where if the CPU temperature is <0C it will get stuck
in the busywait loop until the CPU heats up to 0C.
Cc: Ye Li <b37916@freescale.com>
Cc: Jason Liu <r64343@freescale.com>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
imximage header size is 4-byte, not 8-byte aligned.
This produces .imx images that a Vybrid cannot boot
on.
Fix by adding a "padding" field in header.
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
Add support in mxc_i2c driver, iomux_v3 and vf610 architecture for the four
I2C instances available in VF610.
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
This locally defined struct is actually only used once
and as an opaque type. Remove it for clarity.
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
hab_status command returns a memory dump of the hab event log. But the
raw data is not human-readable. Parsing such data into readable event
will help to minimize debbuging time.
Signed-off-by: Ulises Cardenas <Ulises.Cardenas@freescale.com>
Add I2C4 clock support for i.MX6SX. Since we use runtime check,
but not macro, we need to remove `#ifdef ..` in crm_regs.h, or
gcc will fail to compile the code succesfully.
Making the macros only for i.MX6SX open to other i.MX6x maybe not
a good choice, but we have runtime check.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
enable_spi_clock does the same thing with enable_cspi_clock, so
remove enable_cspi_clock.
Remove enable_cspi_clock prototype in header file
convert cm_fx6/spl.c to use enable_spi_clk
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
According to README.mxc_ocotp the OCOTP is a stanard i.MX6 SoC feature
so centralise the config in mx6_common.h so functionality is standard
across all boards
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Remove the check for temperature being within the min/max range and enter the
busywait cooling loop whenever the CPU temperature is over the critical temp.
This fixes the issue where if a board was booted at a temp greater than
the CPU temperature max, it would skip the loop and never indicate or try
to address the overtemp issue.
Cc: Ye Li <b37916@freescale.com>
Cc: Jason Liu <r64343@freescale.com>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
This patch uses generic 'load' command instead of 'fatload' for 'loadbootscript', 'loadimage' and 'loadfdt' for mx53loco board.
This allows to use EXT partition instead of FAT, while keeping FAT compatibility.
Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr>
Cc: Jason Liu <r64343@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Jason Liu <r64343@freescale.com>
This patch adds the device tree binding doc for the cadence qspi controller &
also removes the not needed properties from the stv0991 device tree.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Jagannadh Teki <jteki@openedev.com>
This patch makes the code compatible with FIFO depths other than 4
bytes. It also simplify read/write FIFO loops.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagannadh Teki <jteki@openedev.com>
sram size could be different on different socs, e.g. on stv0991 it is 256 while
on altera platform it is 128. It is better to receive it from device tree.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagannadh Teki <jteki@openedev.com>
There is no need to re-configure sram partition for every read/write for
better full use of sram for read or write. This patch divides the half
sram for read & half for write once at initialization.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagannadh Teki <jteki@openedev.com>
This patch add the device tree entry for qspi controller & spi flash
memory.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Jagannadh Teki <jteki@openedev.com>
This patch does all the board configurations required to use the qspi
controller & attached spi flash memory.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Jagannadh Teki <jteki@openedev.com>
stv0991 has cadence qspi controller for flash interfacing, this
patch configures the device pads & clock for the controller.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Jagannadh Teki <jteki@openedev.com>
CONFIG_OF_SEPARATE is default define with CONFIG_OF_CONTROL, removing
this define from the board file to avoid multiple definition warning.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Jagannadh Teki <jteki@openedev.com>
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