Prepare v2016.03

Signed-off-by: Tom Rini <trini@konsulko.com>

Makefile

@@ -5,7 +5,7 @@
 VERSION = 2016
 PATCHLEVEL = 03
 SUBLEVEL =
-EXTRAVERSION = -rc3
+EXTRAVERSION =
 NAME =
 
 # *DOCUMENTATION*

api/api.c

@@ -661,6 +661,7 @@ void api_init(void)
 		return;
 	}
 
+	setenv_hex("api_address", (unsigned long)sig);
 	debugf("API sig @ 0x%08x\n", sig);
 	memcpy(sig->magic, API_SIG_MAGIC, 8);
 	sig->version = API_SIG_VERSION;

arch/arm/cpu/armv7/omap-common/boot-common.c

@@ -111,8 +111,6 @@ void save_omap_boot_params(void)
 	    (boot_device <= MMC_BOOT_DEVICES_END)) {
 		switch (boot_device) {
 		case BOOT_DEVICE_MMC1:
-			boot_mode = MMCSD_MODE_FS;
-			break;
 		case BOOT_DEVICE_MMC2:
 			boot_mode = MMCSD_MODE_RAW;
 			break;

arch/arm/include/asm/arch-vf610/iomux-vf610.h

@@ -34,7 +34,7 @@
 				PAD_CTL_PUS_22K_UP | PAD_CTL_OBE_IBE_ENABLE)
 
 #define VF610_GPIO_PAD_CTRL	(PAD_CTL_SPEED_MED | PAD_CTL_DSE_50ohm | \
-				PAD_CTL_PUS_47K_UP | PAD_CTL_IBE_ENABLE)
+				PAD_CTL_IBE_ENABLE)
 
 #define VF610_DSPI_PAD_CTRL	(PAD_CTL_OBE_ENABLE | PAD_CTL_DSE_20ohm | \
 				PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH)

arch/arm/mach-rockchip/rk3036/sdram_rk3036.c

@@ -37,7 +37,7 @@ struct rk3036_sdram_priv {
 /* use integer mode, 396MHz dpll setting
  * refdiv, fbdiv, postdiv1, postdiv2
  */
-const struct pll_div dpll_init_cfg = {1, 66, 4, 1};
+const struct pll_div dpll_init_cfg = {1, 50, 3, 1};
 
 /* 396Mhz ddr timing */
 const struct rk3036_ddr_timing ddr_timing = {0x18c,

arch/arm/mach-rockchip/rk3288-board-spl.c

@@ -114,7 +114,7 @@ static void configure_l2ctlr(void)
 #ifdef CONFIG_SPL_MMC_SUPPORT
 static int configure_emmc(struct udevice *pinctrl)
 {
-#ifndef CONFIG_TARGET_ROCK2
+#if !defined(CONFIG_TARGET_ROCK2) && !defined(CONFIG_TARGET_FIREFLY_RK3288)
 	struct gpio_desc desc;
 	int ret;
 

arch/arm/mach-rockchip/rk3288/sdram_rk3288.c

@@ -561,14 +561,14 @@ static void dram_all_config(const struct dram_info *dram,
 			&sdram_params->ch[chan];
 
 		sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan);
-		sys_reg |= chan << SYS_REG_CHINFO_SHIFT(chan);
+		sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan);
 		sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan);
 		sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan);
-		sys_reg |= info->bk == 3 ? 1 << SYS_REG_BK_SHIFT(chan) : 0;
+		sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan);
 		sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan);
 		sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan);
-		sys_reg |= info->bw << SYS_REG_BW_SHIFT(chan);
-		sys_reg |= info->dbw << SYS_REG_DBW_SHIFT(chan);
+		sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan);
+		sys_reg |= (2 >>info->dbw) << SYS_REG_DBW_SHIFT(chan);
 
 		dram_cfg_rbc(&dram->chan[chan], chan, sdram_params);
 	}
@@ -720,13 +720,13 @@ size_t sdram_size_mb(struct rk3288_pmu *pmu)
 		rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) &
 			SYS_REG_RANK_MASK);
 		col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK);
-		bk = sys_reg & (1 << SYS_REG_BK_SHIFT(ch)) ? 3 : 0;
+		bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK) ;
 		cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) &
 				SYS_REG_CS0_ROW_MASK);
 		cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) &
 				SYS_REG_CS1_ROW_MASK);
-		bw = (sys_reg >> SYS_REG_BW_SHIFT(ch)) &
-			SYS_REG_BW_MASK;
+		bw = (2 >> (sys_reg >> SYS_REG_BW_SHIFT(ch)) &
+			SYS_REG_BW_MASK);
 		row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) &
 			SYS_REG_ROW_3_4_MASK;
 

arch/arm/mach-uniphier/arm32/debug_ll.S

@@ -175,6 +175,7 @@ proxstream2_end:
 	b		init_uart
 ph1_ld6b_end:
 #endif
+	mov		pc, lr
 
 init_uart:
 	addruart	r0, r1, r2

arch/arm/mach-uniphier/dram/cmd_ddrmphy.c

@@ -28,28 +28,14 @@ static int get_nr_ch(void)
 {
 	const struct uniphier_board_data *bd = uniphier_get_board_param();
 
-	return bd->dram_ch2_width ? 3 : 2;
+	return bd->dram_ch[2].size ? 3 : 2;
 }
 
 static int get_nr_datx8(int ch)
 {
-	unsigned int width;
-
 	const struct uniphier_board_data *bd = uniphier_get_board_param();
 
-	switch (ch) {
-	case 0:
-		width = bd->dram_ch0_width;
-		break;
-	case 1:
-		width = bd->dram_ch1_width;
-		break;
-	default:
-		width = bd->dram_ch2_width;
-		break;
-	}
-
-	return width / 8;
+	return bd->dram_ch[ch].width / 8;
 }
 
 static void print_bdl(void __iomem *reg, int n)

arch/mips/include/asm/cacheops.h

@@ -16,7 +16,7 @@ static inline void mips_cache(int op, const volatile void *addr)
 #ifdef __GCC_HAVE_BUILTIN_MIPS_CACHE
 	__builtin_mips_cache(op, addr);
 #else
-	__asm__ __volatile__("cache %0, %1" : : "i"(op), "R"(addr));
+	__asm__ __volatile__("cache %0, 0(%1)" : : "i"(op), "r"(addr));
 #endif
 }
 

arch/sandbox/config.mk

@@ -16,7 +16,7 @@ PLATFORM_CPPFLAGS += $(shell sdl-config --cflags)
 endif
 endif
 
-cmd_u-boot__ = $(CC) -o $@ -T u-boot.lds \
+cmd_u-boot__ = $(CC) -o $@ -Wl,-T u-boot.lds \
 	-Wl,--start-group $(u-boot-main) -Wl,--end-group \
 	$(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot.map
 

arch/sandbox/include/asm/cache.h

@@ -12,7 +12,13 @@
  * the contents of stack buffers to something reasonable.  The
  * GCC macro __BIGGEST_ALIGNMENT__ is defined to be the maximum
  * required alignment for any basic type.  This seems reasonable.
+ * This is however GCC specific so if we don't have that available
+ * assume that 16 is large enough.
  */
+#ifdef __BIGGEST_ALIGNMENT__
 #define ARCH_DMA_MINALIGN	__BIGGEST_ALIGNMENT__
+#else
+#define ARCH_DMA_MINALIGN	16
+#endif
 
 #endif /* __SANDBOX_CACHE_H__ */

board/freescale/mx6qarm2/MAINTAINERS

@@ -1,6 +1,6 @@
 MX6QARM2 BOARD
-M:	Jason Liu <r64343@freescale.com>
-M:	Ye Li <b37916@freescale.com>
+M:	Jason Liu <jason.hui.liu@nxp.com>
+M:	Ye Li <ye.li@nxp.com>
 S:	Maintained
 F:	board/freescale/mx6qarm2/
 F:	include/configs/mx6qarm2.h

board/freescale/mx6qsabreauto/MAINTAINERS

@@ -1,6 +1,6 @@
 MX6QSABREAUTO BOARD
 M:	Fabio Estevam <fabio.estevam@nxp.com>
-M:	Peng Fan <Peng.Fan@freescale.com>
+M:	Peng Fan <peng.fan@nxp.com>
 S:	Maintained
 F:	board/freescale/mx6qsabreauto/
 F:	include/configs/mx6qsabreauto.h

board/freescale/mx6slevk/MAINTAINERS

@@ -1,6 +1,6 @@
 MX6SLEVK BOARD
 M:	Fabio Estevam <fabio.estevam@nxp.com>
-M:	Peng Fan <Peng.Fan@freescale.com>
+M:	Peng Fan <peng.fan@nxp.com>
 S:	Maintained
 F:	board/freescale/mx6slevk/
 F:	include/configs/mx6slevk.h

board/freescale/mx6slevk/mx6slevk.c

@@ -57,7 +57,7 @@ DECLARE_GLOBAL_DATA_PTR;
 			PAD_CTL_DSE_80ohm | PAD_CTL_HYS |	\
 			PAD_CTL_SRE_FAST)
 
-#define ETH_PHY_RESET	IMX_GPIO_NR(4, 21)
+#define ETH_PHY_POWER	IMX_GPIO_NR(4, 21)
 
 int dram_init(void)
 {
@@ -154,10 +154,9 @@ static void setup_iomux_fec(void)
 {
 	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
 
-	/* Reset LAN8720 PHY */
-	gpio_direction_output(ETH_PHY_RESET , 0);
-	udelay(25000);
-	gpio_set_value(ETH_PHY_RESET, 1);
+	/* Power up LAN8720 PHY */
+	gpio_direction_output(ETH_PHY_POWER , 1);
+	udelay(15000);
 }
 
 #define USDHC1_CD_GPIO	IMX_GPIO_NR(4, 7)

board/freescale/mx6ul_14x14_evk/MAINTAINERS

@@ -1,5 +1,5 @@
 MX6ULEVK BOARD
-M:	Peng Fan <Peng.Fan@freescale.com>
+M:	Peng Fan <peng.fan@nxp.com>
 S:	Maintained
 F:	board/freescale/mx6ul_14x14_evk/
 F:	include/configs/mx6ul_14x14_evk.h

board/tbs/tbs2910/tbs2910.c

@@ -378,7 +378,7 @@ static const struct boot_mode board_boot_modes[] = {
 	{"sd2",	 MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 	{"sd3",	 MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 	/* 8 bit bus width */
-	{"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
+	{"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
 	{NULL,	 0},
 };
 #endif

common/dlmalloc.c

@@ -2184,7 +2184,7 @@ Void_t* mALLOc(bytes) size_t bytes;
   INTERNAL_SIZE_T nb;
 
 #ifdef CONFIG_SYS_MALLOC_F_LEN
-	if (gd && !(gd->flags & GD_FLG_FULL_MALLOC_INIT))
+	if (!(gd->flags & GD_FLG_FULL_MALLOC_INIT))
 		return malloc_simple(bytes);
 #endif
 

configs/am3517_evm_defconfig

@@ -4,9 +4,11 @@ CONFIG_TARGET_AM3517_EVM=y
 CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_SYS_PROMPT="AM3517_EVM # "
+CONFIG_SYS_EXTRA_OPTIONS="NAND"
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_GPIO=y
 CONFIG_SYS_NS16550=y

configs/pic32mzdask_defconfig

@@ -29,6 +29,6 @@ CONFIG_DM_ETH=y
 CONFIG_PIC32_ETH=y
 CONFIG_PINCTRL=y
 # CONFIG_PINCTRL_FULL is not set
-CONFIG_SYS_VSNPRINTF=y
+CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_CMD_DHRYSTONE=y

doc/README.uniphier

@@ -44,6 +44,14 @@ PH1-Pro4 reference board:
     $ make uniphier_pro4_defconfig
     $ make CROSS_COMPILE=arm-linux-gnueabi-
 
+PH1-Pro4 Ace board:
+    $ make uniphier_pro4_defconfig
+    $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-ph1-pro4-ace
+
+PH1-Pro4 Sanji board:
+    $ make uniphier_pro4_defconfig
+    $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-ph1-pro4-sanji
+
 PH1-Pro5 4KBOX Board:
     $ make uniphier_pxs2_ld6b_defconfig
     $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-ph1-pro5-4kbox

drivers/mtd/spi/spi_flash.c

@@ -665,7 +665,7 @@ int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len,
 
 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
 static void stm_get_locked_range(struct spi_flash *flash, u8 sr, loff_t *ofs,
-				 u32 *len)
+				 u64 *len)
 {
 	u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
 	int shift = ffs(mask) - 1;
@@ -685,11 +685,11 @@ static void stm_get_locked_range(struct spi_flash *flash, u8 sr, loff_t *ofs,
 /*
  * Return 1 if the entire region is locked, 0 otherwise
  */
-static int stm_is_locked_sr(struct spi_flash *flash, u32 ofs, u32 len,
+static int stm_is_locked_sr(struct spi_flash *flash, loff_t ofs, u64 len,
 			    u8 sr)
 {
 	loff_t lock_offs;
-	u32 lock_len;
+	u64 lock_len;
 
 	stm_get_locked_range(flash, sr, &lock_offs, &lock_len);
 

drivers/pinctrl/Makefile

@@ -9,5 +9,5 @@ obj-y					+= nxp/
 obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
 obj-$(CONFIG_PINCTRL_SANDBOX)	+= pinctrl-sandbox.o
 
-obj-$(CONFIG_ARCH_UNIPHIER)	+= uniphier/
+obj-$(CONFIG_PINCTRL_UNIPHIER)	+= uniphier/
 obj-$(CONFIG_PIC32_PINCTRL)	+= pinctrl_pic32.o

drivers/pinctrl/uniphier/Kconfig

@@ -1,42 +1,42 @@
 if ARCH_UNIPHIER
 
-config PINCTRL_UNIPHIER_CORE
+config PINCTRL_UNIPHIER
 	bool
 
 config PINCTRL_UNIPHIER_PH1_LD4
 	bool "UniPhier PH1-LD4 SoC pinctrl driver"
 	depends on ARCH_UNIPHIER_PH1_LD4
 	default y
-	select PINCTRL_UNIPHIER_CORE
+	select PINCTRL_UNIPHIER
 
 config PINCTRL_UNIPHIER_PH1_PRO4
 	bool "UniPhier PH1-Pro4 SoC pinctrl driver"
 	depends on ARCH_UNIPHIER_PH1_PRO4
 	default y
-	select PINCTRL_UNIPHIER_CORE
+	select PINCTRL_UNIPHIER
 
 config PINCTRL_UNIPHIER_PH1_SLD8
 	bool "UniPhier PH1-sLD8 SoC pinctrl driver"
 	depends on ARCH_UNIPHIER_PH1_SLD8
 	default y
-	select PINCTRL_UNIPHIER_CORE
+	select PINCTRL_UNIPHIER
 
 config PINCTRL_UNIPHIER_PH1_PRO5
 	bool "UniPhier PH1-Pro5 SoC pinctrl driver"
 	depends on ARCH_UNIPHIER_PH1_PRO5
 	default y
-	select PINCTRL_UNIPHIER_CORE
+	select PINCTRL_UNIPHIER
 
 config PINCTRL_UNIPHIER_PROXSTREAM2
 	bool "UniPhier ProXstream2 SoC pinctrl driver"
 	depends on ARCH_UNIPHIER_PROXSTREAM2
 	default y
-	select PINCTRL_UNIPHIER_CORE
+	select PINCTRL_UNIPHIER
 
 config PINCTRL_UNIPHIER_PH1_LD6B
 	bool "UniPhier PH1-LD6b SoC pinctrl driver"
 	depends on ARCH_UNIPHIER_PH1_LD6B
 	default y
-	select PINCTRL_UNIPHIER_CORE
+	select PINCTRL_UNIPHIER
 
 endif

drivers/pinctrl/uniphier/Makefile

@@ -2,7 +2,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-$(CONFIG_PINCTRL_UNIPHIER_CORE)		+= pinctrl-uniphier-core.o
+obj-y						+= pinctrl-uniphier-core.o
 
 obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_LD4)		+= pinctrl-ph1-ld4.o
 obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_PRO4)		+= pinctrl-ph1-pro4.o

drivers/pinctrl/uniphier/pinctrl-uniphier-core.c

@@ -74,6 +74,9 @@ static void uniphier_pinmux_set_one(struct udevice *dev, unsigned pin,
 	unsigned reg, reg_end, shift, mask;
 	u32 tmp;
 
+	/* some pins need input-enabling */
+	uniphier_pinconf_input_enable(dev, pin);
+
 	reg = UNIPHIER_PINCTRL_PINMUX_BASE + pin * mux_bits / 32 * reg_stride;
 	reg_end = reg + reg_stride;
 	shift = pin * mux_bits % 32;
@@ -94,9 +97,6 @@ static void uniphier_pinmux_set_one(struct udevice *dev, unsigned pin,
 
 	if (priv->socdata->load_pinctrl)
 		writel(1, priv->base + UNIPHIER_PINCTRL_LOAD_PINMUX);
-
-	/* some pins need input-enabling */
-	uniphier_pinconf_input_enable(dev, pin);
 }
 
 static int uniphier_pinmux_group_set(struct udevice *dev,

drivers/spi/ti_qspi.c

@@ -534,11 +534,15 @@ static int ti_qspi_ofdata_to_platdata(struct udevice *bus)
 	const void *blob = gd->fdt_blob;
 	int node = bus->of_offset;
 	fdt_addr_t addr;
+	void *mmap;
 
-	priv->base = (struct ti_qspi_regs *)dev_get_addr(bus);
-	priv->memory_map = (void *)dev_get_addr_index(bus, 1);
+	priv->base = map_physmem(dev_get_addr(bus), sizeof(struct ti_qspi_regs),
+				 MAP_NOCACHE);
+	priv->memory_map = map_physmem(dev_get_addr_index(bus, 1), 0,
+				       MAP_NOCACHE);
 	addr = dev_get_addr_index(bus, 2);
-	priv->ctrl_mod_mmap = (addr == FDT_ADDR_T_NONE) ? NULL : (void *)addr;
+	mmap = map_physmem(dev_get_addr_index(bus, 2), 0, MAP_NOCACHE);
+	priv->ctrl_mod_mmap = (addr == FDT_ADDR_T_NONE) ? NULL : mmap;
 
 	priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1);
 	if (priv->max_hz < 0) {

drivers/usb/gadget/composite.c

@@ -1077,6 +1077,8 @@ static struct usb_gadget_driver composite_driver = {
  */
 int usb_composite_register(struct usb_composite_driver *driver)
 {
+	int res;
+
 	if (!driver || !driver->dev || !driver->bind || composite)
 		return -EINVAL;
 
@@ -1084,7 +1086,11 @@ int usb_composite_register(struct usb_composite_driver *driver)
 		driver->name = "composite";
 	composite = driver;
 
-	return usb_gadget_register_driver(&composite_driver);
+	res = usb_gadget_register_driver(&composite_driver);
+	if (res != 0)
+		composite = NULL;
+
+	return res;
 }
 
 /**

drivers/usb/host/dwc2.c

@@ -263,7 +263,9 @@ static void dwc_otg_core_init(struct dwc2_core_regs *regs)
 
 	/* Program the ULPI External VBUS bit if needed */
 #ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS
-	usbcfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
+	usbcfg |= (DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV |
+		   DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR |
+		   DWC2_GUSBCFG_INDICATOR_PASSTHROUGH);
 #else
 	usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
 #endif

drivers/usb/host/dwc2.h

@@ -152,6 +152,8 @@ struct dwc2_core_regs {
 #define DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR_OFFSET	21
 #define DWC2_GUSBCFG_TERM_SEL_DL_PULSE			(1 << 22)
 #define DWC2_GUSBCFG_TERM_SEL_DL_PULSE_OFFSET		22
+#define DWC2_GUSBCFG_INDICATOR_PASSTHROUGH		(1 << 24)
+#define DWC2_GUSBCFG_INDICATOR_PASSTHROUGH_OFFSET	24
 #define DWC2_GUSBCFG_IC_USB_CAP				(1 << 26)
 #define DWC2_GUSBCFG_IC_USB_CAP_OFFSET			26
 #define DWC2_GUSBCFG_IC_TRAFFIC_PULL_REMOVE		(1 << 27)

include/configs/am3517_evm.h

@@ -13,14 +13,17 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+/* High Level Configuration Options */
+
+#define CONFIG_OMAP
+#define CONFIG_OMAP_COMMON
+
 #define CONFIG_SYS_CACHELINE_SIZE	64
 
-/*
- * High Level Configuration Options
- */
-#define CONFIG_OMAP		1	/* in a TI OMAP core */
-#define CONFIG_OMAP3_AM3517EVM	1	/* working with AM3517EVM */
-#define CONFIG_OMAP_COMMON
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
+
 /* Common ARM Erratas */
 #define CONFIG_ARM_ERRATA_454179
 #define CONFIG_ARM_ERRATA_430973
@@ -28,59 +31,48 @@
 
 #define CONFIG_EMIF4	/* The chip has EMIF4 controller */
 
+/*
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
+ * other needs.
+ */
+#define CONFIG_SYS_TEXT_BASE		0x80100000
+#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
+
 #include <asm/arch/cpu.h>		/* get chip and board defs */
 #include <asm/arch/omap.h>
 
-/*
- * Display CPU and Board information
- */
-#define CONFIG_DISPLAY_CPUINFO		1
-#define CONFIG_DISPLAY_BOARDINFO	1
+/* Display CPU and Board information */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_OF_LIBFDT
+#define CONFIG_MISC_INIT_R
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
 
 /* Clock Defines */
 #define V_OSCK			26000000	/* Clock output from T2 */
 #define V_SCLK			(V_OSCK >> 1)
 
-#define CONFIG_MISC_INIT_R
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(16 << 20)
 
-#define CONFIG_OF_LIBFDT
+/* Hardware drivers */
 
-#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS	1
-#define CONFIG_INITRD_TAG		1
-#define CONFIG_REVISION_TAG		1
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB sector */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
-/*
- * DDR related
- */
-#define CONFIG_SYS_CS0_SIZE		(256 * 1024 * 1024)
-
-/*
- * Hardware drivers
- */
-
-/*
- * OMAP GPIO configuration
- */
+/* OMAP GPIO configuration */
 #define CONFIG_OMAP_GPIO
 
-/*
- * NS16550 Configuration
- */
+/* NS16550 Configuration */
 #define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
-
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	(-4)
 #define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
 
-/*
- * select serial console configuration
- */
+/* select serial console configuration */
 #define CONFIG_CONS_INDEX		3
 #define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
 #define CONFIG_SERIAL3			3	/* UART3 on AM3517 EVM */
@@ -90,10 +82,12 @@
 #define CONFIG_BAUDRATE			115200
 #define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
 					115200}
-#define CONFIG_MMC			1
-#define CONFIG_GENERIC_MMC		1
-#define CONFIG_OMAP_HSMMC		1
-#define CONFIG_DOS_PARTITION		1
+
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_OMAP_HSMMC
+#define CONFIG_DOS_PARTITION
 
 /*
  * USB configuration
@@ -111,7 +105,6 @@
 
 #define CONFIG_USB_STORAGE
 #define CONGIG_CMD_STORAGE
-#define CONFIG_CMD_FAT
 
 #ifdef CONFIG_USB_KEYBOARD
 #define CONFIG_SYS_USB_EVENT_POLL
@@ -129,30 +122,29 @@
 #endif /* CONFIG_USB_MUSB_AM35X */
 
 /* commands to include */
-#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
-#define CONFIG_CMD_FAT		/* FAT support			*/
-#define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
 #define CONFIG_CMD_EXT4
 #define CONFIG_CMD_EXT4_WRITE
-
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_PART
+#define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_BOOTZ
-
-#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
-#define CONFIG_CMD_MMC		/* MMC support			*/
-#define CONFIG_CMD_NAND		/* NAND support			*/
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MMC
 #define CONFIG_CMD_DHCP
-#undef CONFIG_CMD_PING
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_MTDPARTS
 
-
-#define CONFIG_SYS_NO_FLASH
+/* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_OMAP24_I2C_SPEED	100000
 #define CONFIG_SYS_OMAP24_I2C_SLAVE	1
 #define CONFIG_SYS_I2C_OMAP34XX
 
-/*
- * Ethernet
- */
+/* Ethernet */
 #define CONFIG_DRIVER_TI_EMAC
 #define CONFIG_DRIVER_TI_EMAC_USE_RMII
 #define CONFIG_MII
@@ -162,23 +154,66 @@
 #define CONFIG_BOOTP_SEND_HOSTNAME
 #define CONFIG_NET_RETRY_COUNT		10
 
-/*
- * Board NAND Info.
- */
+/* Board NAND Info. */
+#ifdef CONFIG_NAND
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_NAND_OMAP_GPMC_PREFETCH
+#define CONFIG_BCH
+#define CONFIG_CMD_UBI			/* UBI-formated MTD partition support */
+#define CONFIG_CMD_UBIFS		/* Read-only UBI volume operations */
+#define CONFIG_RBTREE			/* required by CONFIG_CMD_UBI */
+#define CONFIG_LZO			/* required by CONFIG_CMD_UBIFS */
 #define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
 							/* to access nand */
 #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
 							/* to access */
 							/* nand at CS0 */
-
 #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
 							/* NAND devices */
-#define CONFIG_JFFS2_NAND
-/* nand device jffs2 lives on */
-#define CONFIG_JFFS2_DEV		"nand0"
-/* start of jffs2 partition */
-#define CONFIG_JFFS2_PART_OFFSET	0x680000
-#define CONFIG_JFFS2_PART_SIZE		0xf980000	/* sz of jffs2 part */
+#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS		{ 2,  3,  4,  5,  6,  7,  8,  9, 10, \
+					 11, 12, 13, 14, 16, 17, 18, 19, 20, \
+					 21, 22, 23, 24, 25, 26, 27, 28, 30, \
+					 31, 32, 33, 34, 35, 36, 37, 38, 39, \
+					 40, 41, 42, 44, 45, 46, 47, 48, 49, \
+					 50, 51, 52, 53, 54, 55, 56 }
+
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	13
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
+#define CONFIG_SYS_NAND_MAX_OOBFREE	2
+#define CONFIG_SYS_NAND_MAX_ECCPOS	56
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+#define CONFIG_MTD_PARTITIONS		/* required for UBI partition support */
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+/* NAND block size is 128 KiB.  Synchronize these values with
+ * corresponding Device Tree entries in Linux:
+ *  MLO(SPL)             4 * NAND_BLOCK_SIZE = 512 KiB  @ 0x000000
+ *  U-Boot              15 * NAND_BLOCK_SIZE = 1920 KiB @ 0x080000
+ *  U-Boot environment   2 * NAND_BLOCK_SIZE = 256 KiB  @ 0x260000
+ *  Kernel              64 * NAND_BLOCK_SIZE = 8 MiB    @ 0x2A0000
+ *  DTB                  4 * NAND_BLOCK_SIZE = 512 KiB  @ 0xAA0000
+ *  RootFS              Remaining Flash Space           @ 0xB20000
+ */
+#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
+#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:"	\
+	"512k(MLO),"					\
+	"1920k(u-boot),"				\
+	"256k(u-boot-env),"				\
+	"8m(kernel),"					\
+	"512k(dtb),"					\
+	"-(rootfs)"
+#else
+#define MTDIDS_DEFAULT
+#define MTDPARTS_DEFAULT
+#endif /* CONFIG_NAND */
 
 /* Environment information */
 #define CONFIG_BOOTDELAY	10
@@ -194,18 +229,24 @@
 	"bootenv=uEnv.txt\0" \
 	"cmdline=\0" \
 	"optargs=\0" \
+	"mtdids=" MTDIDS_DEFAULT "\0" \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
 	"mmcdev=0\0" \
 	"mmcpart=1\0" \
 	"mmcroot=/dev/mmcblk0p2 rw\0" \
 	"mmcrootfstype=ext4 rootwait fixrtc\0" \
 	"mmcargs=setenv bootargs console=${console} " \
+		"${mtdparts} " \
 		"${optargs} " \
 		"root=${mmcroot} " \
 		"rootfstype=${mmcrootfstype} " \
 		"${cmdline}\0" \
 	"nandargs=setenv bootargs console=${console} " \
-		"root=/dev/mtdblock4 rw " \
-		"rootfstype=jffs2\0" \
+		"${mtdparts} " \
+		"${optargs} " \
+		"root=ubi0:rootfs rw ubi.mtd=rootfs " \
+		"rootfstype=ubifs rootwait " \
+		"${cmdline}\0" \
 	"loadbootenv=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${bootenv}\0"\
 	"importbootenv=echo Importing environment from mmc ...; " \
 		"env import -t ${loadaddr} ${filesize}\0" \
@@ -218,8 +259,9 @@
 		"bootz ${loadaddr} - ${fdtaddr}\0" \
 	"nandboot=echo Booting from nand ...; " \
 		"run nandargs; " \
-		"nand read ${loadaddr} 280000 400000; " \
-		"bootm ${loadaddr}\0" \
+		"nand read ${loadaddr} 2a0000 800000; " \
+		"nand read ${fdtaddr} aa0000 80000; " \
+		"bootm ${loadaddr} - ${fdtaddr}\0" \
 
 #define CONFIG_BOOTCOMMAND \
 	"mmc dev ${mmcdev}; if mmc rescan; then " \
@@ -240,20 +282,25 @@
 		"fi; " \
 	"else run nandboot; fi"
 
-#define CONFIG_AUTO_COMPLETE	1
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
-#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+/* Miscellaneous configurable options */
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_PARTITION_UUIDS
+
+/* We set the max number of command args high to avoid HUSH bugs. */
+#define CONFIG_SYS_MAXARGS		64
+
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		512
 /* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
-					sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS		32	/* max number of command */
-						/* args */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE \
+					+ sizeof(CONFIG_SYS_PROMPT) + 16)
 /* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
 /* memtest works on */
 #define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
 #define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
@@ -270,53 +317,10 @@
 #define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
 #define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
 
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
-#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-
-/* **** PISMO SUPPORT *** */
-#define CONFIG_SYS_MAX_FLASH_SECT	520	/* max number of sectors */
-						/* on one chip */
-#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of flash banks */
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
-
-#if defined(CONFIG_CMD_NAND)
-#define CONFIG_SYS_FLASH_BASE		NAND_BASE
-#endif
-
-/* Monitor at start of flash */
-#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
-
-#define CONFIG_NAND_OMAP_GPMC
-#define CONFIG_ENV_IS_IN_NAND		1
-#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
-
-#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
-#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
-#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
-
-/*-----------------------------------------------------------------------
- * CFI FLASH driver setup
- */
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT	(100 * CONFIG_SYS_HZ)
-#define CONFIG_SYS_FLASH_WRITE_TOUT	(100 * CONFIG_SYS_HZ)
-
-/* Flash banks JFFS2 should use */
-#define CONFIG_SYS_MAX_MTD_BANKS	(CONFIG_SYS_MAX_FLASH_BANKS + \
-					CONFIG_SYS_MAX_NAND_DEVICE)
-#define CONFIG_SYS_JFFS2_MEM_NAND
-/* use flash_info[2] */
-#define CONFIG_SYS_JFFS2_FIRST_BANK	CONFIG_SYS_MAX_FLASH_BANKS
-#define CONFIG_SYS_JFFS2_NUM_BANKS	1
-
+/* Physical Memory Map */
+#define PHYS_SDRAM_1			OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_2			OMAP34XX_SDRC_CS1
+#define CONFIG_SYS_CS0_SIZE		(256 * 1024 * 1024)
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
 #define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
 #define CONFIG_SYS_INIT_RAM_SIZE	0x800
@@ -324,12 +328,34 @@
 					 CONFIG_SYS_INIT_RAM_SIZE - \
 					 GENERATED_GBL_DATA_SIZE)
 
+/* FLASH and environment organization */
+
+/* **** PISMO SUPPORT *** */
+#define CONFIG_SYS_MAX_FLASH_SECT	520	/* max number of sectors */
+						/* on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of flash banks */
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
+
+#if defined(CONFIG_NAND)
+#define CONFIG_SYS_FLASH_BASE		NAND_BASE
+#endif
+
+/* Monitor at start of flash */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
+#define CONFIG_ENV_SIZE			CONFIG_SYS_ENV_SECT_SIZE
+#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
+#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
+#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
+#define CONFIG_ENV_IS_IN_NAND
+
 /* Defines for SPL */
 #define CONFIG_SPL_FRAMEWORK
 #define CONFIG_SPL_BOARD_INIT
 #define CONFIG_SPL_NAND_SIMPLE
-#define CONFIG_SPL_TEXT_BASE		0x40200800
-#define CONFIG_SPL_MAX_SIZE		(54 * 1024)	/* 8 KB for stack */
+#define CONFIG_SPL_TEXT_BASE		0x40200000
+#define CONFIG_SPL_MAX_SIZE		(64 * 1024)
 
 #define CONFIG_SPL_BSS_START_ADDR	0x80000000
 #define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
@@ -337,7 +363,7 @@
 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
-#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot.img"
 
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 #define CONFIG_SPL_LIBDISK_SUPPORT
@@ -350,32 +376,8 @@
 #define CONFIG_SPL_NAND_BASE
 #define CONFIG_SPL_NAND_DRIVERS
 #define CONFIG_SPL_NAND_ECC
+#define CONFIG_SPL_MTD_SUPPORT
 #define CONFIG_SPL_POWER_SUPPORT
 #define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
 
-/* NAND boot config */
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_COUNT	64
-#define CONFIG_SYS_NAND_PAGE_SIZE	2048
-#define CONFIG_SYS_NAND_OOBSIZE		64
-#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
-#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9,\
-						10, 11, 12, 13}
-#define CONFIG_SYS_NAND_ECCSIZE		512
-#define CONFIG_SYS_NAND_ECCBYTES	3
-#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_HW
-#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
-
-/*
- * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
- * 64 bytes before this address should be set aside for u-boot.img's
- * header. That is 0x800FFFC0--0x80100000 should not be used for any
- * other needs.
- */
-#define CONFIG_SYS_TEXT_BASE		0x80100000
-#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
-#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
-
 #endif /* __CONFIG_H */

include/configs/exynos5-common.h

@@ -170,6 +170,7 @@
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_ASIX
 #define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_USB_ETHER_RTL8152
 
 /* USB boot mode */
 #define CONFIG_USB_BOOTING

include/configs/mx53ard.h

@@ -31,6 +31,8 @@
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_MXC_GPIO
 
+#define CONFIG_CMD_BOOTZ
+
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_SYS_NAND_BASE		NFC_BASE_ADDR_AXI
 #define CONFIG_NAND_MXC
@@ -93,12 +95,12 @@
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"script=boot.scr\0" \
-	"uimage=uImage\0" \
+	"uimage=zImage\0" \
 	"console=ttymxc0\0" \
 	"fdt_high=0xffffffff\0" \
 	"initrd_high=0xffffffff\0" \
 	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
-	"fdt_addr=0x71000000\0" \
+	"fdt_addr=0x78000000\0" \
 	"boot_fdt=try\0" \
 	"ip_dyn=yes\0" \
 	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
@@ -130,16 +132,16 @@
 		"run mmcargs; " \
 		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
 			"if run loadfdt; then " \
-				"bootm ${loadaddr} - ${fdt_addr}; " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
 			"else " \
 				"if test ${boot_fdt} = try; then " \
-					"bootm; " \
+					"bootz; " \
 				"else " \
 					"echo WARN: Cannot load the DT; " \
 				"fi; " \
 			"fi; " \
 		"else " \
-			"bootm; " \
+			"bootz; " \
 		"fi;\0" \
 	"netargs=setenv bootargs console=${console},${baudrate} " \
 		"root=/dev/nfs " \
@@ -154,16 +156,16 @@
 		"${get_cmd} ${uimage}; " \
 		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
 			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
-				"bootm ${loadaddr} - ${fdt_addr}; " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
 			"else " \
 				"if test ${boot_fdt} = try; then " \
-					"bootm; " \
+					"bootz; " \
 				"else " \
 					"echo WARN: Cannot load the DT; " \
 				"fi; " \
 			"fi; " \
 		"else " \
-			"bootm; " \
+			"bootz; " \
 		"fi;\0"
 
 #define CONFIG_BOOTCOMMAND \

include/malloc.h

@@ -914,6 +914,7 @@ int initf_malloc(void);
 /* Simple versions which can be used when space is tight */
 void *malloc_simple(size_t size);
 
+#pragma GCC visibility push(hidden)
 # if __STD_C
 
 Void_t* mALLOc(size_t);
@@ -945,6 +946,7 @@ int     mALLOPt();
 struct mallinfo mALLINFo();
 # endif
 #endif
+#pragma GCC visibility pop
 
 /*
  * Begin and End of memory area for malloc(), and current "brk"