Prepare v2016.05

Signed-off-by: Tom Rini <trini@konsulko.com>

.mailmap

@@ -10,6 +10,7 @@
 
 Allen Martin <amartin@nvidia.com>
 Andreas Bießmann <andreas.devel@googlemail.com>
+Andreas Bießmann <andreas@biessmann.org>
 Aneesh V <aneesh@ti.com>
 Dirk Behme <dirk.behme@googlemail.com>
 Fabio Estevam <fabio.estevam@nxp.com>

MAINTAINERS

@@ -73,7 +73,7 @@ F:	arch/arm/cpu/armv7/socfpga/
 F:	board/altera/socfpga/
 
 ARM ATMEL AT91
-M:	Andreas Bießmann <andreas.devel@googlemail.com>
+M:	Andreas Bießmann <andreas@biessmann.org>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-atmel.git
 F:	arch/arm/mach-at91/
@@ -103,6 +103,12 @@ F:	arch/arm/include/asm/arch-mx*/
 F:	arch/arm/include/asm/arch-vf610/
 F:	arch/arm/include/asm/imx-common/
 
+ARM HISILICON
+M:	Peter Griffin <peter.griffin@linaro.org>
+S:	Maintained
+F:	arch/arm/cpu/armv8/hisilicon
+F:	arm/include/asm/arch-hi6220/
+
 ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X
 M:	Prafulla Wadaskar <prafulla@marvell.com>
 M:	Luka Perkov <luka.perkov@sartura.hr>
@@ -200,7 +206,7 @@ F:	arch/arm/cpu/armv8/zynqmp/
 F:	arch/arm/include/asm/arch-zynqmp/
 
 AVR32
-M:	Andreas Bießmann <andreas.devel@googlemail.com>
+M:	Andreas Bießmann <andreas@biessmann.org>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-avr32.git
 F:	arch/avr32/

Makefile

@@ -5,7 +5,7 @@
 VERSION = 2016
 PATCHLEVEL = 05
 SUBLEVEL =
-EXTRAVERSION = -rc2
+EXTRAVERSION =
 NAME =
 
 # *DOCUMENTATION*
@@ -898,7 +898,7 @@ ifdef CONFIG_SPL_LOAD_FIT
 MKIMAGEFLAGS_u-boot.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
 	-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
 	-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \
-	-b $(patsubst %,arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST)))
+	$(patsubst %,-b arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST)))
 else
 MKIMAGEFLAGS_u-boot.img = -A $(ARCH) -T firmware -C none -O u-boot \
 	-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \

arch/arc/lib/cache.c

@@ -430,13 +430,10 @@ void invalidate_dcache_all(void)
 
 void flush_dcache_all(void)
 {
-#ifdef CONFIG_ISA_ARCV2
-	if (!ioc_exists)
-#endif
-		__dc_entire_op(OP_FLUSH);
+	__dc_entire_op(OP_FLUSH);
 
 #ifdef CONFIG_ISA_ARCV2
-	if (slc_exists && !ioc_exists)
+	if (slc_exists)
 		__slc_entire_op(OP_FLUSH);
 #endif
 }

arch/arm/Kconfig

@@ -668,6 +668,7 @@ config TARGET_HIKEY
 	select DM
 	select DM_GPIO
 	select DM_SERIAL
+	select OF_CONTROL
 	  help
 	  Support for HiKey 96boards platform. It features a HI6220
 	  SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.

arch/arm/cpu/armv7/am33xx/clock.c

@@ -237,4 +237,5 @@ void prcm_init()
 	enable_basic_clocks();
 	scale_vcores();
 	setup_dplls();
+	timer_init();
 }

arch/arm/cpu/armv7/mx6/Kconfig

@@ -136,6 +136,10 @@ config TARGET_OT1200
 	bool "Bachmann OT1200"
 	select SUPPORT_SPL
 
+config TARGET_PICO_IMX6UL
+	bool "PICO-IMX6UL-EMMC"
+	select MX6UL
+
 config TARGET_PLATINUM_PICON
 	bool "platinum-picon"
 	select SUPPORT_SPL
@@ -200,6 +204,7 @@ source "board/gateworks/gw_ventana/Kconfig"
 source "board/kosagi/novena/Kconfig"
 source "board/seco/Kconfig"
 source "board/solidrun/mx6cuboxi/Kconfig"
+source "board/technexion/pico-imx6ul/Kconfig"
 source "board/tbs/tbs2910/Kconfig"
 source "board/tqc/tqma6/Kconfig"
 source "board/udoo/Kconfig"

arch/arm/cpu/armv7/mx6/clock.c

@@ -1217,6 +1217,157 @@ void enable_ipu_clock(void)
 	}
 }
 #endif
+
+#if defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) || defined(CONFIG_MX6DL) || \
+	defined(CONFIG_MX6S)
+static void disable_ldb_di_clock_sources(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	int reg;
+
+	/* Make sure PFDs are disabled at boot. */
+	reg = readl(&mxc_ccm->analog_pfd_528);
+	/* Cannot disable pll2_pfd2_396M, as it is the MMDC clock in iMX6DL */
+	if (is_cpu_type(MXC_CPU_MX6DL))
+		reg |= 0x80008080;
+	else
+		reg |= 0x80808080;
+	writel(reg, &mxc_ccm->analog_pfd_528);
+
+	/* Disable PLL3 PFDs */
+	reg = readl(&mxc_ccm->analog_pfd_480);
+	reg |= 0x80808080;
+	writel(reg, &mxc_ccm->analog_pfd_480);
+
+	/* Disable PLL5 */
+	reg = readl(&mxc_ccm->analog_pll_video);
+	reg &= ~(1 << 13);
+	writel(reg, &mxc_ccm->analog_pll_video);
+}
+
+static void enable_ldb_di_clock_sources(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	int reg;
+
+	reg = readl(&mxc_ccm->analog_pfd_528);
+	if (is_cpu_type(MXC_CPU_MX6DL))
+		reg &= ~(0x80008080);
+	else
+		reg &= ~(0x80808080);
+	writel(reg, &mxc_ccm->analog_pfd_528);
+
+	reg = readl(&mxc_ccm->analog_pfd_480);
+	reg &= ~(0x80808080);
+	writel(reg, &mxc_ccm->analog_pfd_480);
+}
+
+/*
+ * Try call this function as early in the boot process as possible since the
+ * function temporarily disables PLL2 PFD's, PLL3 PFD's and PLL5.
+ */
+void select_ldb_di_clock_source(enum ldb_di_clock clk)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	int reg;
+
+	/*
+	 * Need to follow a strict procedure when changing the LDB
+	 * clock, else we can introduce a glitch. Things to keep in
+	 * mind:
+	 * 1. The current and new parent clocks must be disabled.
+	 * 2. The default clock for ldb_dio_clk is mmdc_ch1 which has
+	 * no CG bit.
+	 * 3. In the RTL implementation of the LDB_DI_CLK_SEL mux
+	 * the top four options are in one mux and the PLL3 option along
+	 * with another option is in the second mux. There is third mux
+	 * used to decide between the first and second mux.
+	 * The code below switches the parent to the bottom mux first
+	 * and then manipulates the top mux. This ensures that no glitch
+	 * will enter the divider.
+	 *
+	 * Need to disable MMDC_CH1 clock manually as there is no CG bit
+	 * for this clock. The only way to disable this clock is to move
+	 * it to pll3_sw_clk and then to disable pll3_sw_clk
+	 * Make sure periph2_clk2_sel is set to pll3_sw_clk
+	 */
+
+	/* Disable all ldb_di clock parents */
+	disable_ldb_di_clock_sources();
+
+	/* Set MMDC_CH1 mask bit */
+	reg = readl(&mxc_ccm->ccdr);
+	reg |= MXC_CCM_CCDR_MMDC_CH1_HS_MASK;
+	writel(reg, &mxc_ccm->ccdr);
+
+	/* Set periph2_clk2_sel to be sourced from PLL3_sw_clk */
+	reg = readl(&mxc_ccm->cbcmr);
+	reg &= ~MXC_CCM_CBCMR_PERIPH2_CLK2_SEL;
+	writel(reg, &mxc_ccm->cbcmr);
+
+	/*
+	 * Set the periph2_clk_sel to the top mux so that
+	 * mmdc_ch1 is from pll3_sw_clk.
+	 */
+	reg = readl(&mxc_ccm->cbcdr);
+	reg |= MXC_CCM_CBCDR_PERIPH2_CLK_SEL;
+	writel(reg, &mxc_ccm->cbcdr);
+
+	/* Wait for the clock switch */
+	while (readl(&mxc_ccm->cdhipr))
+		;
+	/* Disable pll3_sw_clk by selecting bypass clock source */
+	reg = readl(&mxc_ccm->ccsr);
+	reg |= MXC_CCM_CCSR_PLL3_SW_CLK_SEL;
+	writel(reg, &mxc_ccm->ccsr);
+
+	/* Set the ldb_di0_clk and ldb_di1_clk to 111b */
+	reg = readl(&mxc_ccm->cs2cdr);
+	reg |= ((7 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
+	      | (7 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
+	writel(reg, &mxc_ccm->cs2cdr);
+
+	/* Set the ldb_di0_clk and ldb_di1_clk to 100b */
+	reg = readl(&mxc_ccm->cs2cdr);
+	reg &= ~(MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK
+	      | MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK);
+	reg |= ((4 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
+	      | (4 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
+	writel(reg, &mxc_ccm->cs2cdr);
+
+	/* Set the ldb_di0_clk and ldb_di1_clk to desired source */
+	reg = readl(&mxc_ccm->cs2cdr);
+	reg &= ~(MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK
+	      | MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK);
+	reg |= ((clk << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
+	      | (clk << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
+	writel(reg, &mxc_ccm->cs2cdr);
+
+	/* Unbypass pll3_sw_clk */
+	reg = readl(&mxc_ccm->ccsr);
+	reg &= ~MXC_CCM_CCSR_PLL3_SW_CLK_SEL;
+	writel(reg, &mxc_ccm->ccsr);
+
+	/*
+	 * Set the periph2_clk_sel back to the bottom mux so that
+	 * mmdc_ch1 is from its original parent.
+	 */
+	reg = readl(&mxc_ccm->cbcdr);
+	reg &= ~MXC_CCM_CBCDR_PERIPH2_CLK_SEL;
+	writel(reg, &mxc_ccm->cbcdr);
+
+	/* Wait for the clock switch */
+	while (readl(&mxc_ccm->cdhipr))
+		;
+	/* Clear MMDC_CH1 mask bit */
+	reg = readl(&mxc_ccm->ccdr);
+	reg &= ~MXC_CCM_CCDR_MMDC_CH1_HS_MASK;
+	writel(reg, &mxc_ccm->ccdr);
+
+	enable_ldb_di_clock_sources();
+}
+#endif
+
 /***************************************************/
 
 U_BOOT_CMD(

arch/arm/cpu/armv7/omap-common/boot-common.c

@@ -111,6 +111,8 @@ void save_omap_boot_params(void)
 	    (boot_device <= MMC_BOOT_DEVICES_END)) {
 		switch (boot_device) {
 		case BOOT_DEVICE_MMC1:
+			boot_mode = MMCSD_MODE_FS;
+			break;
 		case BOOT_DEVICE_MMC2:
 			boot_mode = MMCSD_MODE_RAW;
 			break;

arch/arm/cpu/armv7/omap-common/clocks-common.c

@@ -584,22 +584,46 @@ void scale_vcores(struct vcores_data const *vcores)
 	debug("mpu: %d\n", vcores->mpu.value);
 	do_scale_vcore(vcores->mpu.addr, vcores->mpu.value, vcores->mpu.pmic);
 	/* Configure MPU ABB LDO after scale */
-	abb_setup((*ctrl)->control_std_fuse_opp_vdd_mpu_2,
+	abb_setup(vcores->mpu.efuse.reg,
 		  (*ctrl)->control_wkup_ldovbb_mpu_voltage_ctrl,
 		  (*prcm)->prm_abbldo_mpu_setup,
 		  (*prcm)->prm_abbldo_mpu_ctrl,
 		  (*prcm)->prm_irqstatus_mpu_2,
-		  OMAP_ABB_MPU_TXDONE_MASK,
+		  vcores->mpu.abb_tx_done_mask,
 		  OMAP_ABB_FAST_OPP);
 
 	/* The .mm member is not used for the DRA7xx */
 
 	debug("gpu: %d\n", vcores->gpu.value);
 	do_scale_vcore(vcores->gpu.addr, vcores->gpu.value, vcores->gpu.pmic);
+	/* Configure GPU ABB LDO after scale */
+	abb_setup(vcores->gpu.efuse.reg,
+		  (*ctrl)->control_wkup_ldovbb_gpu_voltage_ctrl,
+		  (*prcm)->prm_abbldo_gpu_setup,
+		  (*prcm)->prm_abbldo_gpu_ctrl,
+		  (*prcm)->prm_irqstatus_mpu,
+		  vcores->gpu.abb_tx_done_mask,
+		  OMAP_ABB_FAST_OPP);
 	debug("eve: %d\n", vcores->eve.value);
 	do_scale_vcore(vcores->eve.addr, vcores->eve.value, vcores->eve.pmic);
+	/* Configure EVE ABB LDO after scale */
+	abb_setup(vcores->eve.efuse.reg,
+		  (*ctrl)->control_wkup_ldovbb_eve_voltage_ctrl,
+		  (*prcm)->prm_abbldo_eve_setup,
+		  (*prcm)->prm_abbldo_eve_ctrl,
+		  (*prcm)->prm_irqstatus_mpu,
+		  vcores->eve.abb_tx_done_mask,
+		  OMAP_ABB_FAST_OPP);
 	debug("iva: %d\n", vcores->iva.value);
 	do_scale_vcore(vcores->iva.addr, vcores->iva.value, vcores->iva.pmic);
+	/* Configure IVA ABB LDO after scale */
+	abb_setup(vcores->iva.efuse.reg,
+		  (*ctrl)->control_wkup_ldovbb_iva_voltage_ctrl,
+		  (*prcm)->prm_abbldo_iva_setup,
+		  (*prcm)->prm_abbldo_iva_ctrl,
+		  (*prcm)->prm_irqstatus_mpu,
+		  vcores->iva.abb_tx_done_mask,
+		  OMAP_ABB_FAST_OPP);
 	/* Might need udelay(1000) here if debug is enabled to see all prints */
 #else
 	u32 val;
@@ -621,17 +645,26 @@ void scale_vcores(struct vcores_data const *vcores)
 	do_scale_vcore(vcores->mpu.addr, val, vcores->mpu.pmic);
 
 	/* Configure MPU ABB LDO after scale */
-	abb_setup((*ctrl)->control_std_fuse_opp_vdd_mpu_2,
+	abb_setup(vcores->mpu.efuse.reg,
 		  (*ctrl)->control_wkup_ldovbb_mpu_voltage_ctrl,
 		  (*prcm)->prm_abbldo_mpu_setup,
 		  (*prcm)->prm_abbldo_mpu_ctrl,
 		  (*prcm)->prm_irqstatus_mpu_2,
-		  OMAP_ABB_MPU_TXDONE_MASK,
+		  vcores->mpu.abb_tx_done_mask,
 		  OMAP_ABB_FAST_OPP);
 
 	val = optimize_vcore_voltage(&vcores->mm);
 	do_scale_vcore(vcores->mm.addr, val, vcores->mm.pmic);
 
+	/* Configure MM ABB LDO after scale */
+	abb_setup(vcores->mm.efuse.reg,
+		  (*ctrl)->control_wkup_ldovbb_mm_voltage_ctrl,
+		  (*prcm)->prm_abbldo_mm_setup,
+		  (*prcm)->prm_abbldo_mm_ctrl,
+		  (*prcm)->prm_irqstatus_mpu,
+		  vcores->mm.abb_tx_done_mask,
+		  OMAP_ABB_FAST_OPP);
+
 	val = optimize_vcore_voltage(&vcores->gpu);
 	do_scale_vcore(vcores->gpu.addr, val, vcores->gpu.pmic);
 

arch/arm/cpu/armv7/omap5/hw_data.c

@@ -352,6 +352,7 @@ struct vcores_data omap5430_volts_es2 = {
 	.mpu.value = VDD_MPU_ES2,
 	.mpu.addr = SMPS_REG_ADDR_12_MPU,
 	.mpu.pmic = &palmas,
+	.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 
 	.core.value = VDD_CORE_ES2,
 	.core.addr = SMPS_REG_ADDR_8_CORE,
@@ -360,6 +361,7 @@ struct vcores_data omap5430_volts_es2 = {
 	.mm.value = VDD_MM_ES2,
 	.mm.addr = SMPS_REG_ADDR_45_IVA,
 	.mm.pmic = &palmas,
+	.mm.abb_tx_done_mask = OMAP_ABB_MM_TXDONE_MASK,
 };
 
 struct vcores_data dra752_volts = {
@@ -368,18 +370,21 @@ struct vcores_data dra752_volts = {
 	.mpu.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
 	.mpu.addr	= TPS659038_REG_ADDR_SMPS12,
 	.mpu.pmic	= &tps659038,
+	.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 
 	.eve.value	= VDD_EVE_DRA752,
 	.eve.efuse.reg	= STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 	.eve.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
 	.eve.addr	= TPS659038_REG_ADDR_SMPS45,
 	.eve.pmic	= &tps659038,
+	.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
 
 	.gpu.value	= VDD_GPU_DRA752,
 	.gpu.efuse.reg	= STD_FUSE_OPP_VMIN_GPU_NOM,
 	.gpu.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
 	.gpu.addr	= TPS659038_REG_ADDR_SMPS6,
 	.gpu.pmic	= &tps659038,
+	.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
 
 	.core.value	= VDD_CORE_DRA752,
 	.core.efuse.reg	= STD_FUSE_OPP_VMIN_CORE_NOM,
@@ -392,6 +397,7 @@ struct vcores_data dra752_volts = {
 	.iva.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
 	.iva.addr	= TPS659038_REG_ADDR_SMPS8,
 	.iva.pmic	= &tps659038,
+	.iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
 };
 
 struct vcores_data dra722_volts = {
@@ -400,6 +406,7 @@ struct vcores_data dra722_volts = {
 	.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 	.mpu.addr	= TPS65917_REG_ADDR_SMPS1,
 	.mpu.pmic	= &tps659038,
+	.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 
 	.core.value	= VDD_CORE_DRA72x,
 	.core.efuse.reg	= STD_FUSE_OPP_VMIN_CORE_NOM,
@@ -416,18 +423,21 @@ struct vcores_data dra722_volts = {
 	.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 	.gpu.addr	= TPS65917_REG_ADDR_SMPS3,
 	.gpu.pmic	= &tps659038,
+	.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
 
 	.eve.value	= VDD_EVE_DRA72x,
 	.eve.efuse.reg	= STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 	.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 	.eve.addr	= TPS65917_REG_ADDR_SMPS3,
 	.eve.pmic	= &tps659038,
+	.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
 
 	.iva.value	= VDD_IVA_DRA72x,
 	.iva.efuse.reg	= STD_FUSE_OPP_VMIN_IVA_NOM,
 	.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 	.iva.addr	= TPS65917_REG_ADDR_SMPS3,
 	.iva.pmic	= &tps659038,
+	.iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
 };
 
 /*

arch/arm/cpu/armv7/omap5/prcm-regs.c

@@ -297,7 +297,6 @@ struct prcm_regs const omap5_es1_prcm = {
 
 struct omap_sys_ctrl_regs const omap5_ctrl = {
 	.control_status				= 0x4A002134,
-	.control_std_fuse_opp_vdd_mpu_2		= 0x4A0021B4,
 	.control_std_fuse_die_id_0		= 0x4A002200,
 	.control_std_fuse_die_id_1		= 0x4A002208,
 	.control_std_fuse_die_id_2		= 0x4A00220C,
@@ -353,6 +352,7 @@ struct omap_sys_ctrl_regs const omap5_ctrl = {
 	.control_emif1_sdram_config_ext		= 0x4AE0C144,
 	.control_emif2_sdram_config_ext		= 0x4AE0C148,
 	.control_wkup_ldovbb_mpu_voltage_ctrl	= 0x4AE0C318,
+	.control_wkup_ldovbb_mm_voltage_ctrl	= 0x4AE0C314,
 	.control_padconf_wkup_base		= 0x4AE0C800,
 	.control_smart1nopmio_padconf_0		= 0x4AE0CDA0,
 	.control_smart1nopmio_padconf_1		= 0x4AE0CDA4,
@@ -440,13 +440,15 @@ struct omap_sys_ctrl_regs const dra7xx_ctrl = {
 	.control_srcomp_code_latch		= 0x4A002E84,
 	.control_ddr_control_ext_0		= 0x4A002E88,
 	.control_padconf_core_base		= 0x4A003400,
-	.control_std_fuse_opp_vdd_mpu_2		= 0x4A003B20,
 	.control_port_emif1_sdram_config	= 0x4AE0C110,
 	.control_port_emif1_lpddr2_nvm_config	= 0x4AE0C114,
 	.control_port_emif2_sdram_config	= 0x4AE0C118,
 	.control_emif1_sdram_config_ext		= 0x4AE0C144,
 	.control_emif2_sdram_config_ext		= 0x4AE0C148,
 	.control_wkup_ldovbb_mpu_voltage_ctrl	= 0x4AE0C158,
+	.control_wkup_ldovbb_iva_voltage_ctrl	= 0x4A002470,
+	.control_wkup_ldovbb_eve_voltage_ctrl	= 0x4A00246C,
+	.control_wkup_ldovbb_gpu_voltage_ctrl	= 0x4AE0C154,
 	.control_std_fuse_die_id_0		= 0x4AE0C200,
 	.control_std_fuse_die_id_1		= 0x4AE0C208,
 	.control_std_fuse_die_id_2		= 0x4AE0C20C,
@@ -724,6 +726,7 @@ struct prcm_regs const omap5_es2_prcm = {
 	.cm_l3init_usb_otg_ss1_clkctrl = 0x4a0096f0,
 
 	/* prm irqstatus regs */
+	.prm_irqstatus_mpu = 0x4ae06010,
 	.prm_irqstatus_mpu_2 = 0x4ae06014,
 
 	/* l4 wkup regs */
@@ -753,6 +756,8 @@ struct prcm_regs const omap5_es2_prcm = {
 
 	.prm_abbldo_mpu_setup = 0x4ae07cdc,
 	.prm_abbldo_mpu_ctrl = 0x4ae07ce0,
+	.prm_abbldo_mm_setup = 0x4ae07ce4,
+	.prm_abbldo_mm_ctrl = 0x4ae07ce8,
 
 	/* SCRM stuff, used by some boards */
 	.scrm_auxclk0 = 0x4ae0a310,
@@ -829,6 +834,7 @@ struct prcm_regs const dra7xx_prcm = {
 	.cm_ipu_i2c5_clkctrl			= 0x4a005578,
 
 	/* prm irqstatus regs */
+	.prm_irqstatus_mpu			= 0x4ae06010,
 	.prm_irqstatus_mpu_2			= 0x4ae06014,
 
 	/* cm2.ckgen */
@@ -997,6 +1003,12 @@ struct prcm_regs const dra7xx_prcm = {
 
 	.prm_abbldo_mpu_setup			= 0x4AE07DDC,
 	.prm_abbldo_mpu_ctrl			= 0x4AE07DE0,
+	.prm_abbldo_iva_setup			= 0x4AE07E34,
+	.prm_abbldo_iva_ctrl			= 0x4AE07E24,
+	.prm_abbldo_eve_setup			= 0x4AE07E30,
+	.prm_abbldo_eve_ctrl			= 0x4AE07E20,
+	.prm_abbldo_gpu_setup			= 0x4AE07DE4,
+	.prm_abbldo_gpu_ctrl			= 0x4AE07DE8,
 
 	/*l3main1 edma*/
 	.cm_l3main1_tptc1_clkctrl               = 0x4a008778,

arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c

@@ -180,7 +180,7 @@ ulong get_ddr_freq(ulong ctrl_num)
 
 	/*
 	 * DDR controller 0 & 1 are on memory complex 0
-	 * DDR controler 2 is on memory complext 1
+	 * DDR controller 2 is on memory complext 1
 	 */
 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 	if (ctrl_num >= 2)

arch/arm/cpu/armv8/start.S

@@ -214,7 +214,9 @@ WEAK(lowlevel_init)
 	ldr	x1, =GICC_BASE
 	bl	gic_init_secure_percpu
 #endif
+#endif
 
+#ifndef CONFIG_ARMV8_MULTIENTRY
 	branch_if_master x0, x1, 2f
 
 	/*

arch/arm/dts/Makefile

@@ -11,6 +11,8 @@ dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
 	exynos4412-trats2.dtb \
 	exynos4412-odroid.dtb
 
+dtb-$(CONFIG_TARGET_HIKEY) += hi6220-hikey.dtb
+
 dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
 	exynos5250-snow.dtb \
 	exynos5250-spring.dtb \

arch/arm/dts/hi6220-hikey.dts

@@ -0,0 +1,41 @@
+/*
+ * dts file for Hisilicon HiKey Development Board
+ *
+ * Copyright (C) 2015, Hisilicon Ltd.
+ *
+ */
+
+/dts-v1/;
+
+/*Reserved 1MB memory for MCU*/
+/memreserve/ 0x05e00000 0x00100000;
+
+#include "hi6220.dtsi"
+
+/ {
+	model = "HiKey Development Board";
+	compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220";
+
+	aliases {
+		serial0 = &uart0; /* On board UART0 */
+		serial1 = &uart1; /* BT UART */
+		serial2 = &uart2; /* LS Expansion UART0 */
+		serial3 = &uart3; /* LS Expansion UART1 */
+	};
+
+	chosen {
+		stdout-path = "serial3:115200n8";
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x40000000>;
+	};
+};
+
+&uart2 {
+	label = "LS-UART0";
+};
+&uart3 {
+	label = "LS-UART1";
+};

arch/arm/dts/hi6220.dtsi

@@ -0,0 +1,218 @@
+/*
+ * dts file for Hisilicon Hi6220 SoC
+ *
+ * Copyright (C) 2015, Hisilicon Ltd.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/hi6220-clock.h>
+
+/ {
+	compatible = "hisilicon,hi6220";
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+				core1 {
+					cpu = <&cpu1>;
+				};
+				core2 {
+					cpu = <&cpu2>;
+				};
+				core3 {
+					cpu = <&cpu3>;
+				};
+			};
+			cluster1 {
+				core0 {
+					cpu = <&cpu4>;
+				};
+				core1 {
+					cpu = <&cpu5>;
+				};
+				core2 {
+					cpu = <&cpu6>;
+				};
+				core3 {
+					cpu = <&cpu7>;
+				};
+			};
+		};
+
+		cpu0: cpu@0 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			reg = <0x0 0x0>;
+			enable-method = "psci";
+		};
+
+		cpu1: cpu@1 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			reg = <0x0 0x1>;
+			enable-method = "psci";
+		};
+
+		cpu2: cpu@2 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			reg = <0x0 0x2>;
+			enable-method = "psci";
+		};
+
+		cpu3: cpu@3 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			reg = <0x0 0x3>;
+			enable-method = "psci";
+		};
+
+		cpu4: cpu@100 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			reg = <0x0 0x100>;
+			enable-method = "psci";
+		};
+
+		cpu5: cpu@101 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			reg = <0x0 0x101>;
+			enable-method = "psci";
+		};
+
+		cpu6: cpu@102 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			reg = <0x0 0x102>;
+			enable-method = "psci";
+		};
+
+		cpu7: cpu@103 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			reg = <0x0 0x103>;
+			enable-method = "psci";
+		};
+	};
+
+	gic: interrupt-controller@f6801000 {
+		compatible = "arm,gic-400";
+		reg = <0x0 0xf6801000 0 0x1000>, /* GICD */
+		      <0x0 0xf6802000 0 0x2000>, /* GICC */
+		      <0x0 0xf6804000 0 0x2000>, /* GICH */
+		      <0x0 0xf6806000 0 0x2000>; /* GICV */
+		#address-cells = <0>;
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		ao_ctrl: ao_ctrl@f7800000 {
+			compatible = "hisilicon,hi6220-aoctrl", "syscon";
+			reg = <0x0 0xf7800000 0x0 0x2000>;
+			#clock-cells = <1>;
+		};
+
+		sys_ctrl: sys_ctrl@f7030000 {
+			compatible = "hisilicon,hi6220-sysctrl", "syscon";
+			reg = <0x0 0xf7030000 0x0 0x2000>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+
+		media_ctrl: media_ctrl@f4410000 {
+			compatible = "hisilicon,hi6220-mediactrl", "syscon";
+			reg = <0x0 0xf4410000 0x0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		pm_ctrl: pm_ctrl@f7032000 {
+			compatible = "hisilicon,hi6220-pmctrl", "syscon";
+			reg = <0x0 0xf7032000 0x0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		uart0: uart@f8015000 {	/* console */
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x0 0xf8015000 0x0 0x1000>;
+			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+			clock = <19200000>;
+			clocks = <&ao_ctrl HI6220_UART0_PCLK>,
+				 <&ao_ctrl HI6220_UART0_PCLK>;
+			clock-names = "uartclk", "apb_pclk";
+		};
+
+		uart1: uart@f7111000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x0 0xf7111000 0x0 0x1000>;
+			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+			clock = <19200000>;
+			clocks = <&sys_ctrl HI6220_UART1_PCLK>,
+				 <&sys_ctrl HI6220_UART1_PCLK>;
+			clock-names = "uartclk", "apb_pclk";
+			status = "disabled";
+		};
+
+		uart2: uart@f7112000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x0 0xf7112000 0x0 0x1000>;
+			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+			clock = <19200000>;
+			clocks = <&sys_ctrl HI6220_UART2_PCLK>,
+				 <&sys_ctrl HI6220_UART2_PCLK>;
+			clock-names = "uartclk", "apb_pclk";
+			status = "disabled";
+		};
+
+		uart3: uart@f7113000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x0 0xf7113000 0x0 0x1000>;
+			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+			clock = <19200000>;
+			clocks = <&sys_ctrl HI6220_UART3_PCLK>,
+				 <&sys_ctrl HI6220_UART3_PCLK>;
+			clock-names = "uartclk", "apb_pclk";
+		};
+
+		uart4: uart@f7114000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x0 0xf7114000 0x0 0x1000>;
+			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+			clock = <19200000>;
+			clocks = <&sys_ctrl HI6220_UART4_PCLK>,
+				 <&sys_ctrl HI6220_UART4_PCLK>;
+			clock-names = "uartclk", "apb_pclk";
+			status = "disabled";
+		};
+	};
+};

arch/arm/dts/socfpga_cyclone5_socrates.dts

@@ -83,5 +83,6 @@
 };
 
 &usb1 {
+	disable-over-current;
 	status = "okay";
 };

arch/arm/dts/uniphier-ph1-ld11-ref.dts

@@ -14,15 +14,6 @@
 	model = "UniPhier PH1-LD11 Reference Board";
 	compatible = "socionext,ph1-ld11-ref", "socionext,ph1-ld11";
 
-	memory {
-		device_type = "memory";
-		reg = <0 0x80000000 0 0x40000000>;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
 	aliases {
 		serial0 = &serial0;
 		serial1 = &serial1;
@@ -35,6 +26,15 @@
 		i2c4 = &i2c4;
 		i2c5 = &i2c5;
 	};
+
+	memory {
+		device_type = "memory";
+		reg = <0 0x80000000 0 0x40000000>;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
 };
 
 &ethsc {

arch/arm/dts/uniphier-ph1-ld20-ref.dts

@@ -8,21 +8,13 @@
 
 /dts-v1/;
 /include/ "uniphier-ph1-ld20.dtsi"
+/include/ "uniphier-ref-daughter.dtsi"
 /include/ "uniphier-support-card.dtsi"
 
 / {
 	model = "UniPhier PH1-LD20 Reference Board";
 	compatible = "socionext,ph1-ld20-ref", "socionext,ph1-ld20";
 
-	memory {
-		device_type = "memory";
-		reg = <0 0x80000000 0 0xc0000000>;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
 	aliases {
 		serial0 = &serial0;
 		serial1 = &serial1;
@@ -35,6 +27,15 @@
 		i2c4 = &i2c4;
 		i2c5 = &i2c5;
 	};
+
+	memory {
+		device_type = "memory";
+		reg = <0 0x80000000 0 0xc0000000>;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
 };
 
 &ethsc {

arch/arm/dts/uniphier-ph1-ld20.dtsi

@@ -226,6 +226,23 @@
 			reg = <0x59801000 0x400>;
 		};
 
+		mio: mioctrl@59810000 {
+			compatible = "socionext,ph1-ld20-mioctrl";
+			reg = <0x59810000 0x800>;
+			#clock-cells = <1>;
+		};
+
+		sd: sdhc@5a400000 {
+			compatible = "socionext,uniphier-sdhc";
+			status = "disabled";
+			reg = <0x5a400000 0x800>;
+			interrupts = <0 76 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_sd>;
+			clocks = <&mio 0>;
+			bus-width = <4>;
+		};
+
 		pinctrl: pinctrl@5f801000 {
 			compatible = "socionext,ph1-ld20-pinctrl", "syscon";
 			reg = <0x5f801000 0xe00>;

arch/arm/imx-common/Makefile

@@ -68,7 +68,7 @@ SPL: spl/u-boot-spl.bin $(IMX_CONFIG) FORCE
 	$(call if_changed,mkimage)
 
 MKIMAGEFLAGS_u-boot.uim = -A arm -O U-Boot -a $(CONFIG_SYS_TEXT_BASE) \
-		-e $(CONFIG_SYS_TEXT_BASE) -C none
+		-e $(CONFIG_SYS_TEXT_BASE) -C none -T firmware
 
 u-boot.uim: u-boot.bin FORCE
 	$(call if_changed,mkimage)
@@ -86,7 +86,7 @@ u-boot-with-nand-spl.imx: spl/u-boot-nand-spl.imx u-boot.uim FORCE
 	$(call if_changed,pad_cat)
 
 quiet_cmd_u-boot-nand-spl_imx = GEN     $@
-cmd_u-boot-nand-spl_imx = (echo -ne '\x00\x00\x00\x00\x46\x43\x42\x20\x01' && \
+cmd_u-boot-nand-spl_imx = (printf '\000\000\000\000\106\103\102\040\001' && \
 	dd bs=1015 count=1 if=/dev/zero 2>/dev/null) | cat - $< > $@
 
 spl/u-boot-nand-spl.imx: SPL FORCE

arch/arm/imx-common/cache.c

@@ -42,6 +42,12 @@ void v7_outer_cache_enable(void)
 	unsigned int val;
 
 
+	/*
+	 * Must disable the L2 before changing the latency parameters
+	 * and auxiliary control register.
+	 */
+	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+
 	/*
 	 * Set bit 22 in the auxiliary control register. If this bit
 	 * is cleared, PL310 treats Normal Shared Non-cacheable
@@ -59,9 +65,6 @@ void v7_outer_cache_enable(void)
 	}
 #endif
 
-	/* Must disable the L2 before changing the latency parameters */
-	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
-
 	writel(0x132, &pl310->pl310_tag_latency_ctrl);
 	writel(0x132, &pl310->pl310_data_latency_ctrl);
 

arch/arm/include/asm/arch-bcmcygnus/configs.h

@@ -30,7 +30,4 @@
 #define CONFIG_PHY_BROADCOM
 #define CONFIG_PHY_RESET_DELAY 10000 /* PHY reset delay in us*/
 
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_MII
-
 #endif /* __ARCH_CONFIGS_H */

arch/arm/include/asm/arch-ls102xa/config.h

@@ -90,7 +90,6 @@
 #define CONFIG_SYS_SCSI_MAX_LUN		1
 #define CONFIG_SYS_SCSI_MAX_DEVICE		(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
 						CONFIG_SYS_SCSI_MAX_LUN)
-#define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 #define CONFIG_SYS_FSL_ERRATUM_A008407
 

arch/arm/include/asm/arch-mx6/clock.h

@@ -42,6 +42,14 @@ enum mxc_clock {
 	MXC_I2C_CLK,
 };
 
+enum ldb_di_clock {
+	MXC_PLL5_CLK = 0,
+	MXC_PLL2_PFD0_CLK,
+	MXC_PLL2_PFD2_CLK,
+	MXC_MMDC_CH1_CLK,
+	MXC_PLL3_SW_CLK,
+};
+
 enum enet_freq {
 	ENET_25MHZ,
 	ENET_50MHZ,
@@ -70,4 +78,5 @@ int enable_lcdif_clock(u32 base_addr);
 void enable_qspi_clk(int qspi_num);
 void enable_thermal_clk(void);
 void mxs_set_lcdclk(u32 base_addr, u32 freq);
+void select_ldb_di_clock_source(enum ldb_di_clock clk);
 #endif /* __ASM_ARCH_CLOCK_H */

arch/arm/include/asm/arch-mx6/imx-regs.h

@@ -274,6 +274,7 @@
 #define IP2APB_TZASC1_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x50000)
 #ifdef CONFIG_MX6UL
 #define QSPI0_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x60000)
+#define UART6_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x7C000)
 #elif defined(CONFIG_MX6SX)
 #define SAI1_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x54000)
 #define AUDMUX_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x58000)

arch/arm/include/asm/arch-omap5/omap.h

@@ -215,6 +215,10 @@ struct s32ktimer {
 
 /* ABB tranxdone mask */
 #define OMAP_ABB_MPU_TXDONE_MASK		(0x1 << 7)
+#define OMAP_ABB_MM_TXDONE_MASK			(0x1 << 31)
+#define OMAP_ABB_IVA_TXDONE_MASK		(0x1 << 30)
+#define OMAP_ABB_EVE_TXDONE_MASK		(0x1 << 29)
+#define OMAP_ABB_GPU_TXDONE_MASK		(0x1 << 28)
 
 /* ABB efuse masks */
 #define OMAP5_ABB_FUSE_VSET_MASK		(0x1F << 24)

arch/arm/include/asm/arch-tegra/gpu.h

@@ -26,7 +26,7 @@ int tegra_gpu_enable_node(void *blob, const char *gpupath);
 
 #else /* CONFIG_OF_LIBFDT */
 
-static inline int tegra_gpu_enable_node(void *blob, const char *gpupath)
+static inline int tegra_gpu_enable_node(void *blob, const char *compat)
 {
 	return 0;
 }

arch/arm/include/asm/armv7.h

@@ -59,26 +59,7 @@
 #ifndef __ASSEMBLY__
 #include <linux/types.h>
 #include <asm/io.h>
-
-/*
- * CP15 Barrier instructions
- * Please note that we have separate barrier instructions in ARMv7
- * However, we use the CP15 based instructtions because we use
- * -march=armv5 in U-Boot
- */
-#define CP15ISB	asm volatile ("mcr     p15, 0, %0, c7, c5, 4" : : "r" (0))
-#define CP15DSB	asm volatile ("mcr     p15, 0, %0, c7, c10, 4" : : "r" (0))
-#define CP15DMB	asm volatile ("mcr     p15, 0, %0, c7, c10, 5" : : "r" (0))
-
-#ifdef __ARM_ARCH_7A__
-#define ISB	asm volatile ("isb" : : : "memory")
-#define DSB	asm volatile ("dsb" : : : "memory")
-#define DMB	asm volatile ("dmb" : : : "memory")
-#else
-#define ISB	CP15ISB
-#define DSB	CP15DSB
-#define DMB	CP15DMB
-#endif
+#include <asm/barriers.h>
 
 /*
  * Workaround for ARM errata # 798870

arch/arm/include/asm/barriers.h

@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2016 ARM Ltd.
+ *
+ * ARM and ARM64 barrier instructions
+ * split from armv7.h to allow sharing between ARM and ARM64
+ *
+ * Original copyright in armv7.h was:
+ * (C) Copyright 2010 Texas Instruments, <www.ti.com> Aneesh V <aneesh@ti.com>
+ *
+ * Much of the original barrier code was contributed by:
+ *   Valentine Barshak <valentine.barshak@cogentembedded.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __BARRIERS_H__
+#define __BARRIERS_H__
+
+#ifndef __ASSEMBLY__
+
+#ifndef CONFIG_ARM64
+/*
+ * CP15 Barrier instructions
+ * Please note that we have separate barrier instructions in ARMv7
+ * However, we use the CP15 based instructtions because we use
+ * -march=armv5 in U-Boot
+ */
+#define CP15ISB	asm volatile ("mcr     p15, 0, %0, c7, c5, 4" : : "r" (0))
+#define CP15DSB	asm volatile ("mcr     p15, 0, %0, c7, c10, 4" : : "r" (0))
+#define CP15DMB	asm volatile ("mcr     p15, 0, %0, c7, c10, 5" : : "r" (0))
+
+#endif /* !CONFIG_ARM64 */
+
+#if defined(__ARM_ARCH_7A__) || defined(CONFIG_ARM64)
+#define ISB	asm volatile ("isb sy" : : : "memory")
+#define DSB	asm volatile ("dsb sy" : : : "memory")
+#define DMB	asm volatile ("dmb sy" : : : "memory")
+#else
+#define ISB	CP15ISB
+#define DSB	CP15DSB
+#define DMB	CP15DMB
+#endif
+
+#endif	/* __ASSEMBLY__ */
+#endif	/* __BARRIERS_H__ */

arch/arm/include/asm/omap_common.h

@@ -234,6 +234,7 @@ struct prcm_regs {
 	u32 cm_l3init_usb_otg_ss1_clkctrl;
 	u32 cm_l3init_usb_otg_ss2_clkctrl;
 
+	u32 prm_irqstatus_mpu;
 	u32 prm_irqstatus_mpu_2;
 
 	/* cm2.l4per */
@@ -321,6 +322,14 @@ struct prcm_regs {
 	u32 prm_vc_cfg_i2c_clk;
 	u32 prm_abbldo_mpu_setup;
 	u32 prm_abbldo_mpu_ctrl;
+	u32 prm_abbldo_mm_setup;
+	u32 prm_abbldo_mm_ctrl;
+	u32 prm_abbldo_iva_setup;
+	u32 prm_abbldo_iva_ctrl;
+	u32 prm_abbldo_eve_setup;
+	u32 prm_abbldo_eve_ctrl;
+	u32 prm_abbldo_gpu_setup;
+	u32 prm_abbldo_gpu_ctrl;
 
 	u32 cm_div_m4_dpll_core;
 	u32 cm_div_m5_dpll_core;
@@ -363,7 +372,6 @@ struct omap_sys_ctrl_regs {
 	u32 control_core_mac_id_0_hi;
 	u32 control_core_mac_id_1_lo;
 	u32 control_core_mac_id_1_hi;
-	u32 control_std_fuse_opp_vdd_mpu_2;
 	u32 control_phy_power_usb;
 	u32 control_core_mmr_lock1;
 	u32 control_core_mmr_lock2;
@@ -442,6 +450,10 @@ struct omap_sys_ctrl_regs {
 	u32 control_emif1_sdram_config_ext;
 	u32 control_emif2_sdram_config_ext;
 	u32 control_wkup_ldovbb_mpu_voltage_ctrl;
+	u32 control_wkup_ldovbb_mm_voltage_ctrl;
+	u32 control_wkup_ldovbb_iva_voltage_ctrl;
+	u32 control_wkup_ldovbb_eve_voltage_ctrl;
+	u32 control_wkup_ldovbb_gpu_voltage_ctrl;
 	u32 control_smart1nopmio_padconf_0;
 	u32 control_smart1nopmio_padconf_1;
 	u32 control_padconf_mode;
@@ -541,6 +553,8 @@ struct volts {
 	u32 addr;
 	struct volts_efuse_data efuse;
 	struct pmic_data *pmic;
+
+	u32 abb_tx_done_mask;
 };
 
 struct vcores_data {

arch/arm/lib/stack.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015 Andreas Bießmann <andreas.devel@googlemail.com>
+ * Copyright (c) 2015 Andreas Bießmann <andreas@biessmann.org>
  *
  * Copyright (c) 2011 The Chromium OS Authors.
  * (C) Copyright 2002-2006

arch/arm/mach-at91/arm920t/at91rm9200_devices.c

@@ -2,7 +2,7 @@
  * [partely copied from arch/arm/cpu/arm926ejs/at91/arm9260_devices.c]
  *
  * (C) Copyright 2011
- * Andreas Bießmann <andreas.devel@googlemail.com>
+ * Andreas Bießmann <andreas@biessmann.org>
  *
  * (C) Copyright 2007-2008
  * Stelian Pop <stelian@popies.net>

arch/arm/mach-at91/arm920t/cpu.c

@@ -2,7 +2,7 @@
  * [origin: arch/arm/cpu/arm926ejs/at91/cpu.c]
  *
  * (C) Copyright 2011
- * Andreas Bießmann, andreas.devel@googlemail.com
+ * Andreas Bießmann, andreas@biessmann.org
  * (C) Copyright 2010
  * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
  * (C) Copyright 2009

arch/arm/mach-kirkwood/include/mach/config.h

@@ -80,7 +80,6 @@
  * Ethernet Driver configuration
  */
 #ifdef CONFIG_CMD_NET
-#define CONFIG_CMD_MII
 #define CONFIG_NETCONSOLE	/* include NetConsole support   */
 #define CONFIG_MII		/* expose smi ove miiphy interface */
 #define CONFIG_MVGBE		/* Enable Marvell Gbe Controller Driver */
@@ -102,7 +101,6 @@
  */
 #ifdef CONFIG_CMD_IDE
 #define __io
-#define CONFIG_CMD_EXT2
 #define CONFIG_MVSATA_IDE
 #define CONFIG_IDE_PREINIT
 #define CONFIG_MVSATA_IDE_USE_PORT1

arch/arm/mach-mvebu/include/mach/config.h

@@ -77,7 +77,6 @@
  * Ethernet Driver configuration
  */
 #ifdef CONFIG_CMD_NET
-#define CONFIG_CMD_MII
 #define CONFIG_MII		/* expose smi ove miiphy interface */
 #if !defined(CONFIG_ARMADA_375)
 #define CONFIG_MVNETA		/* Enable Marvell Gbe Controller Driver */

arch/arm/mach-rockchip/rk3288/sdram_rk3288.c

@@ -561,14 +561,14 @@ static void dram_all_config(const struct dram_info *dram,
 			&sdram_params->ch[chan];
 
 		sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan);
-		sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan);
+		sys_reg |= chan << SYS_REG_CHINFO_SHIFT(chan);
 		sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan);
 		sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan);
-		sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan);
+		sys_reg |= info->bk == 3 ? 1 << SYS_REG_BK_SHIFT(chan) : 0;
 		sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan);
 		sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan);
-		sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan);
-		sys_reg |= (2 >>info->dbw) << SYS_REG_DBW_SHIFT(chan);
+		sys_reg |= info->bw << SYS_REG_BW_SHIFT(chan);
+		sys_reg |= info->dbw << SYS_REG_DBW_SHIFT(chan);
 
 		dram_cfg_rbc(&dram->chan[chan], chan, sdram_params);
 	}
@@ -720,13 +720,13 @@ size_t sdram_size_mb(struct rk3288_pmu *pmu)
 		rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) &
 			SYS_REG_RANK_MASK);
 		col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK);
-		bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK) ;
+		bk = sys_reg & (1 << SYS_REG_BK_SHIFT(ch)) ? 3 : 0;
 		cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) &
 				SYS_REG_CS0_ROW_MASK);
 		cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) &
 				SYS_REG_CS1_ROW_MASK);
-		bw = (2 >> (sys_reg >> SYS_REG_BW_SHIFT(ch)) &
-			SYS_REG_BW_MASK);
+		bw = (sys_reg >> SYS_REG_BW_SHIFT(ch)) &
+			SYS_REG_BW_MASK;
 		row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) &
 			SYS_REG_ROW_3_4_MASK;
 

arch/arm/mach-socfpga/misc.c

@@ -172,7 +172,7 @@ static int socfpga_eth_reset(void)
 #else
 static int socfpga_eth_reset(void)
 {
-	return 0
+	return 0;
 };
 #endif
 

arch/arm/mach-sunxi/dram_helpers.c

@@ -7,6 +7,7 @@
  */
 
 #include <common.h>
+#include <asm/barriers.h>
 #include <asm/io.h>
 #include <asm/arch/dram.h>
 
@@ -31,6 +32,7 @@ bool mctl_mem_matches(u32 offset)
 	/* Try to write different values to RAM at two addresses */
 	writel(0, CONFIG_SYS_SDRAM_BASE);
 	writel(0xaa55aa55, (ulong)CONFIG_SYS_SDRAM_BASE + offset);
+	DSB;
 	/* Check if the same value is actually observed when reading back */
 	return readl(CONFIG_SYS_SDRAM_BASE) ==
 	       readl((ulong)CONFIG_SYS_SDRAM_BASE + offset);

arch/arm/mach-tegra/board2.c

@@ -404,16 +404,22 @@ ulong board_get_usable_ram_top(ulong total_size)
  */
 int ft_system_setup(void *blob, bd_t *bd)
 {
-	const char *gpu_path =
-#if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
-		"/gpu@0,57000000";
-#else
-		NULL;
+	const char *gpu_compats[] = {
+#if defined(CONFIG_TEGRA124)
+		"nvidia,gk20a",
 #endif
+#if defined(CONFIG_TEGRA210)
+		"nvidia,gm20b",
+#endif
+	};
+	int i, ret;
 
 	/* Enable GPU node if GPU setup has been performed */
-	if (gpu_path != NULL)
-		return tegra_gpu_enable_node(blob, gpu_path);
+	for (i = 0; i < ARRAY_SIZE(gpu_compats); i++) {
+		ret = tegra_gpu_enable_node(blob, gpu_compats[i]);
+		if (ret)
+			return ret;
+	}
 
 	return 0;
 }

arch/arm/mach-tegra/gpu.c

@@ -33,16 +33,17 @@ void tegra_gpu_config(void)
 
 #if defined(CONFIG_OF_LIBFDT)
 
-int tegra_gpu_enable_node(void *blob, const char *gpupath)
+int tegra_gpu_enable_node(void *blob, const char *compat)
 {
 	int offset;
 
-	if (_configured) {
-		offset = fdt_path_offset(blob, gpupath);
-		if (offset > 0) {
-			fdt_status_okay(blob, offset);
-			debug("enabled GPU node %s\n", gpupath);
-		}
+	if (!_configured)
+		return 0;
+
+	offset = fdt_node_offset_by_compatible(blob, -1, compat);
+	while (offset != -FDT_ERR_NOTFOUND) {
+		fdt_status_okay(blob, offset);
+		offset = fdt_node_offset_by_compatible(blob, offset, compat);
 	}
 
 	return 0;

arch/arm/mach-uniphier/Kconfig

@@ -23,6 +23,11 @@ config ARCH_UNIPHIER_PRO5_PXS2_LD6B
 	bool "UniPhier PH1-Pro5/ProXstream2/PH1-LD6b SoC"
 	select CPU_V7
 
+config ARCH_UNIPHIER_LD20
+	bool "UniPhier PH1-LD20 SoC"
+	select ARM64
+	select SPL_SEPARATE_BSS
+
 endchoice
 
 config ARCH_UNIPHIER_LD4

arch/arm/mach-uniphier/Makefile

@@ -31,3 +31,4 @@ obj-$(CONFIG_MICRO_SUPPORT_CARD) += micro-support-card.o
 obj-$(CONFIG_DEBUG_UART_UNIPHIER) += debug-uart/
 
 obj-$(CONFIG_CPU_V7) += arm32/
+obj-$(CONFIG_ARM64) += arm64/

arch/arm/mach-uniphier/arm64/Makefile

@@ -0,0 +1,10 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y += timer.o
+else
+obj-y += mem_map.o smp.o smp_kick_cpus.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD20) += arm-cci500.o
+endif

arch/arm/mach-uniphier/arm64/arm-cci500.c

@@ -0,0 +1,41 @@
+/*
+ * Initialization of ARM Corelink CCI-500 Cache Coherency Interconnect
+ *
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <mapmem.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+
+#define CCI500_BASE			0x5FD00000
+#define CCI500_SLAVE_OFFSET		0x1000
+
+#define CCI500_SNOOP_CTRL
+#define   CCI500_SNOOP_CTRL_EN_DVM	BIT(1)
+#define   CCI500_SNOOP_CTRL_EN_SNOOP	BIT(0)
+
+void cci500_init(unsigned int nr_slaves)
+{
+	unsigned long slave_base = CCI500_BASE + CCI500_SLAVE_OFFSET;
+	int i;
+
+	for (i = 0; i < nr_slaves; i++) {
+		void __iomem *base;
+		u32 tmp;
+
+		base = map_sysmem(slave_base, SZ_4K);
+
+		tmp = readl(base);
+		tmp |= CCI500_SNOOP_CTRL_EN_DVM | CCI500_SNOOP_CTRL_EN_SNOOP;
+		writel(tmp, base);
+
+		unmap_sysmem(base);
+
+		slave_base += CCI500_SLAVE_OFFSET;
+	}
+}

arch/arm/mach-uniphier/arm64/mem_map.c

@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/types.h>
+#include <asm/armv8/mmu.h>
+
+static struct mm_region uniphier_mem_map[] = {
+	{
+		.base = 0x00000000,
+		.size = 0x80000000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+	{
+		.base = 0x80000000,
+		.size = 0xc0000000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	},
+	{ /* sentinel */ }
+};
+
+struct mm_region *mem_map = uniphier_mem_map;

arch/arm/mach-uniphier/arm64/smp.S

@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <linux/linkage.h>
+
+ENTRY(uniphier_smp_setup)
+	mrs	x0, s3_1_c15_c2_1	/* CPUECTLR_EL1 */
+	orr	x0, x0, #(1 << 6)	/* SMPEN */
+	msr	s3_1_c15_c2_1, x0
+	ret
+ENDPROC(uniphier_smp_setup)
+
+ENTRY(uniphier_secondary_startup)
+	bl	uniphier_smp_setup
+	b	_start
+ENDPROC(uniphier_secondary_startup)

arch/arm/mach-uniphier/arm64/smp_kick_cpus.c

@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <mapmem.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+
+#define UNIPHIER_SMPCTRL_ROM_RSV0	0x59801200
+
+void uniphier_smp_setup(void);
+void uniphier_secondary_startup(void);
+
+void uniphier_smp_kick_all_cpus(void)
+{
+	void __iomem *rom_boot_rsv0;
+
+	rom_boot_rsv0 = map_sysmem(UNIPHIER_SMPCTRL_ROM_RSV0, SZ_8);
+
+	writeq((u64)uniphier_secondary_startup, rom_boot_rsv0);
+	readq(rom_boot_rsv0);	/* relax */
+
+	unmap_sysmem(rom_boot_rsv0);
+
+	uniphier_smp_setup();
+
+	asm("sev"); /* Bring up all secondary CPUs from Boot ROM into U-Boot */
+}

arch/arm/mach-uniphier/arm64/timer.c

@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <mapmem.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+
+#define CNT_CONTROL_BASE	0x60E00000
+
+#define CNTCR			0x000
+#define   CNTCR_EN			BIT(0)
+
+/* setup ARMv8 Generic Timer */
+int timer_init(void)
+{
+	void __iomem *base;
+	u32 tmp;
+
+	base = map_sysmem(CNT_CONTROL_BASE, SZ_4K);
+
+	/*
+	 * Note:
+	 * In a system that implements both Secure and Non-secure states,
+	 * this register is only writable in Secure state.
+	 */
+	tmp = readl(base + CNTCR);
+	tmp |= CNTCR_EN;
+	writel(tmp, base + CNTCR);
+
+	unmap_sysmem(base);
+
+	return 0;
+}

arch/arm/mach-uniphier/board_common.c

@@ -8,9 +8,13 @@
 
 #include "micro-support-card.h"
 
+void uniphier_smp_kick_all_cpus(void);
+
 int board_init(void)
 {
 	led_puts("Uboo");
-
+#ifdef CONFIG_ARM64
+	uniphier_smp_kick_all_cpus();
+#endif
 	return 0;
 }

arch/arm/mach-uniphier/board_early_init_f.c

@@ -61,6 +61,14 @@ int board_early_init_f(void)
 		led_puts("U1");
 		uniphier_pxs2_clk_init();
 		break;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD20)
+	case SOC_UNIPHIER_LD20:
+		uniphier_ld20_pin_init();
+		led_puts("U1");
+		uniphier_ld20_clk_init();
+		cci500_init(2);
+		break;
 #endif
 	default:
 		break;

arch/arm/mach-uniphier/board_late_init.c

@@ -28,38 +28,37 @@ static void nand_denali_wp_disable(void)
 #endif
 }
 
-struct uniphier_fdt_file {
-	const char *compatible;
-	const char *file_name;
-};
+#define VENDOR_PREFIX		"socionext,"
+#define DTB_FILE_PREFIX		"uniphier-"
 
-static const struct uniphier_fdt_file uniphier_fdt_files[] = {
-	{ "socionext,ph1-ld4-ref", "uniphier-ph1-ld4-ref.dtb", },
-	{ "socionext,ph1-ld6b-ref", "uniphier-ph1-ld6b-ref.dtb", },
-	{ "socionext,ph1-ld10-ref", "uniphier-ph1-ld10-ref.dtb", },
-	{ "socionext,ph1-pro4-ace", "uniphier-ph1-pro4-ace.dtb", },
-	{ "socionext,ph1-pro4-ref", "uniphier-ph1-pro4-ref.dtb", },
-	{ "socionext,ph1-pro4-sanji", "uniphier-ph1-pro4-sanji.dtb", },
-	{ "socionext,ph1-pro5-4kbox", "uniphier-ph1-pro5-4kbox.dtb", },
-	{ "socionext,ph1-sld3-ref", "uniphier-ph1-sld3-ref.dtb", },
-	{ "socionext,ph1-sld8-ref", "uniphier-ph1-sld8-ref.dtb", },
-	{ "socionext,proxstream2-gentil", "uniphier-proxstream2-gentil.dtb", },
-	{ "socionext,proxstream2-vodka", "uniphier-proxstream2-vodka.dtb", },
-};
-
-static void uniphier_set_fdt_file(void)
+static int uniphier_set_fdt_file(void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
-	int i;
+	const char *compat;
+	char dtb_name[256];
+	int buf_len = 256;
+	int ret;
 
-	/* lookup DTB file name based on the compatible string */
-	for (i = 0; i < ARRAY_SIZE(uniphier_fdt_files); i++) {
-		if (!fdt_node_check_compatible(gd->fdt_blob, 0,
-					uniphier_fdt_files[i].compatible)) {
-			setenv("fdt_file", uniphier_fdt_files[i].file_name);
-			return;
-		}
-	}
+	ret = fdt_get_string(gd->fdt_blob, 0, "compatible", &compat);
+	if (ret)
+		return -EINVAL;
+
+	if (strncmp(compat, VENDOR_PREFIX, strlen(VENDOR_PREFIX)))
+		return -EINVAL;
+
+	compat += strlen(VENDOR_PREFIX);
+
+	strncat(dtb_name, DTB_FILE_PREFIX, buf_len);
+	buf_len -= strlen(DTB_FILE_PREFIX);
+
+	strncat(dtb_name, compat, buf_len);
+	buf_len -= strlen(compat);
+
+	strncat(dtb_name, ".dtb", buf_len);
+
+	setenv("fdt_file", dtb_name);
+
+	return 0;
 }
 
 int board_late_init(void)
@@ -85,11 +84,12 @@ int board_late_init(void)
 		setenv("bootmode", "usbboot");
 		break;
 	default:
-		printf("Unsupported Boot Mode\n");
-		return -1;
+		printf("Unknown\n");
+		break;
 	}
 
-	uniphier_set_fdt_file();
+	if (uniphier_set_fdt_file())
+		printf("fdt_file environment was not set correctly\n");
 
 	return 0;
 }

arch/arm/mach-uniphier/boards.c

@@ -165,6 +165,28 @@ static const struct uniphier_board_data uniphier_ld6b_data = {
 };
 #endif
 
+#if defined(CONFIG_ARCH_UNIPHIER_LD20)
+static const struct uniphier_board_data uniphier_ld20_data = {
+	.dram_freq = 1866,
+	.dram_nr_ch = 3,
+	.dram_ch[0] = {
+		.base = 0x80000000,
+		.size = 0x40000000,
+		.width = 32,
+	},
+	.dram_ch[1] = {
+		.base = 0xc0000000,
+		.size = 0x40000000,
+		.width = 32,
+	},
+	.dram_ch[2] = {
+		.base = 0x100000000UL,
+		.size = 0x40000000,
+		.width = 32,
+	},
+};
+#endif
+
 struct uniphier_board_id {
 	const char *compatible;
 	const struct uniphier_board_data *param;
@@ -194,6 +216,9 @@ static const struct uniphier_board_id uniphier_boards[] = {
 #if defined(CONFIG_ARCH_UNIPHIER_LD6B)
 	{ "socionext,ph1-ld6b", &uniphier_ld6b_data, },
 #endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD20)
+	{ "socionext,ph1-ld20", &uniphier_ld20_data, },
+#endif
 };
 
 const struct uniphier_board_data *uniphier_get_board_param(void)

arch/arm/mach-uniphier/boot-mode/Makefile

@@ -11,5 +11,6 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= boot-mode-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PRO5)	+= boot-mode-pro5.o
 obj-$(CONFIG_ARCH_UNIPHIER_PXS2)	+= boot-mode-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD6B)	+= boot-mode-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= boot-mode-ld20.o
 
 obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o

arch/arm/mach-uniphier/boot-mode/boot-device.h

@@ -16,11 +16,13 @@ u32 uniphier_sld3_boot_device(void);
 u32 uniphier_ld4_boot_device(void);
 u32 uniphier_pro5_boot_device(void);
 u32 uniphier_pxs2_boot_device(void);
+u32 uniphier_ld20_boot_device(void);
 
 void uniphier_sld3_boot_mode_show(void);
 void uniphier_ld4_boot_mode_show(void);
 void uniphier_pro5_boot_mode_show(void);
 void uniphier_pxs2_boot_mode_show(void);
+void uniphier_ld20_boot_mode_show(void);
 
 u32 spl_boot_device_raw(void);
 

arch/arm/mach-uniphier/boot-mode/boot-mode-ld20.c

@@ -0,0 +1,77 @@
+/*
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/io.h>
+
+#include "../sg-regs.h"
+#include "boot-device.h"
+
+static struct boot_device_info boot_device_table[] = {
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, EraseSize 128KB, Addr 4)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 4)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, EraseSize 128KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, EraseSize 256KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, EraseSize 512KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC  8, EraseSize 128KB, Addr 4)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 4)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC  8, EraseSize 128KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC  8, EraseSize 256KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC  8, EraseSize 512KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, ONFI,            Addr 4)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI,            Addr 4)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, ONFI,            Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI,            Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC  8, ONFI             Addr 4)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI             Addr 4)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC  8, ONFI             Addr 5)"},
+	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI             Addr 5)"},
+	{BOOT_DEVICE_MMC1, "eMMC (Legacy,         4bit, 1.8V, Training Off)"},
+	{BOOT_DEVICE_MMC1, "eMMC (Legacy,         4bit, 1.8V, Training On)"},
+	{BOOT_DEVICE_MMC1, "eMMC (Legacy,         8bit, 1.8V, Training Off)"},
+	{BOOT_DEVICE_MMC1, "eMMC (Legacy,         8bit, 1.8V, Training On)"},
+	{BOOT_DEVICE_MMC1, "eMMC (High Speed SDR, 8bit, 1.8V, Training Off)"},
+	{BOOT_DEVICE_MMC1, "eMMC (High Speed SDR, 8bit, 1.8V, Training On)"},
+	{BOOT_DEVICE_MMC1, "eMMC (Legacy,         4bit, 1.8V, Training Off)"},
+	{BOOT_DEVICE_NOR,  "NOR Boot (XECS1)"},
+};
+
+static int get_boot_mode_sel(void)
+{
+	return (readl(SG_PINMON0) >> 1) & 0x1f;
+}
+
+u32 uniphier_ld20_boot_device(void)
+{
+	int boot_mode;
+
+	if (~readl(SG_PINMON0) & 0x00000780)
+		return BOOT_DEVICE_USB;
+
+	boot_mode = get_boot_mode_sel();
+
+	return boot_device_table[boot_mode].type;
+}
+
+void uniphier_ld20_boot_mode_show(void)
+{
+	int mode_sel, i;
+
+	mode_sel = get_boot_mode_sel();
+
+	puts("Boot Mode Pin:\n");
+
+	for (i = 0; i < ARRAY_SIZE(boot_device_table); i++)
+		printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i,
+		       boot_device_table[i].info);
+}

arch/arm/mach-uniphier/boot-mode/boot-mode.c

@@ -38,6 +38,10 @@ u32 spl_boot_device_raw(void)
 	case SOC_UNIPHIER_PXS2:
 	case SOC_UNIPHIER_LD6B:
 		return uniphier_pxs2_boot_device();
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD20)
+	case SOC_UNIPHIER_LD20:
+		return uniphier_ld20_boot_device();
 #endif
 	default:
 		return BOOT_DEVICE_NONE;
@@ -110,7 +114,7 @@ static int do_mmcsetn(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 U_BOOT_CMD(
 	   mmcsetn,	1,	1,	do_mmcsetn,
-	"Set the first MMC (not SD) dev number to \"mmc_first_dev\" enviroment",
+	"Set the first MMC (not SD) dev number to \"mmc_first_dev\" environment",
 	""
 );
 #endif

arch/arm/mach-uniphier/boot-mode/cmd_pinmon.c

@@ -38,6 +38,11 @@ static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	case SOC_UNIPHIER_LD6B:
 		uniphier_pxs2_boot_mode_show();
 		break;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD20)
+	case SOC_UNIPHIER_LD20:
+		uniphier_ld20_boot_mode_show();
+		break;
 #endif
 	default:
 		break;

arch/arm/mach-uniphier/clk/Makefile

@@ -9,3 +9,4 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= clk-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PRO5)	+= clk-pro5.o
 obj-$(CONFIG_ARCH_UNIPHIER_PXS2)	+= clk-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD6B)	+= clk-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= clk-ld20.o

arch/arm/mach-uniphier/clk/clk-ld20.c

@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sc64-regs.h"
+
+void uniphier_ld20_clk_init(void)
+{
+}

arch/arm/mach-uniphier/cpu_info.c

@@ -48,7 +48,7 @@ int print_cpuinfo(void)
 		puts("PH1-LD11 ()");
 		break;
 	case 0x32:
-		puts("PH1-LD20 ()");
+		puts("PH1-LD20 (SC1401AJ1)");
 		break;
 	default:
 		printf("Unknown Processor ID (0x%x)\n", revision);

arch/arm/mach-uniphier/dram/Makefile

@@ -12,6 +12,7 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= umc-sld8.o \
 					   ddrphy-training.o ddrphy-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PXS2)	+= umc-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD6B)	+= umc-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= umc-ld20.o
 
 else
 

arch/arm/mach-uniphier/dram/ddrphy-ld20-regs.h

@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ */
+
+#ifndef _DDRPHY_LD20_REGS_H
+#define _DDRPHY_LD20_REGS_H
+
+#define PHY_SCL_DATA_0			0x00000104
+#define PHY_SCL_DATA_1			0x00000108
+#define PHY_SCL_LATENCY			0x0000010C
+#define PHY_SCL_START			0x00000100
+#define PHY_SCL_CONFIG_1		0x00000118
+#define PHY_SCL_CONFIG_2		0x0000011C
+#define PHY_PAD_CTRL			0x00000120
+#define PHY_DLL_RECALIB			0x00000124
+#define PHY_DLL_ADRCTRL			0x00000128
+#define PHY_LANE_SEL			0x0000012C
+#define PHY_DLL_TRIM_1			0x00000130
+#define PHY_DLL_TRIM_2			0x00000134
+#define PHY_DLL_TRIM_3			0x00000138
+#define PHY_SCL_MAIN_CLK_DELTA		0x00000140
+#define PHY_WRLVL_AUTOINC_TRIM		0x0000014C
+#define PHY_WRLVL_DYN_ODT		0x00000150
+#define PHY_WRLVL_ON_OFF		0x00000154
+#define PHY_UNQ_ANALOG_DLL_1		0x0000015C
+#define PHY_DLL_INCR_TRIM_1		0x00000164
+#define PHY_DLL_INCR_TRIM_3		0x00000168
+#define PHY_SCL_CONFIG_3		0x0000016C
+#define PHY_UNIQUIFY_TSMC_IO_1		0x00000170
+#define PHY_SCL_START_ADDR		0x00000188
+#define PHY_DSCL_CNT		        0x0000019C
+#define PHY_DLL_TRIM_CLK		0x000001A4
+#define PHY_DYNAMIC_BIT_LVL		0x000001AC
+#define PHY_SCL_WINDOW_TRIM		0x000001B4
+#define PHY_DISABLE_GATING_FOR_SCL	0x000001B8
+#define PHY_SCL_CONFIG_4		0x000001BC
+#define PHY_DYNAMIC_WRITE_BIT_LVL	0x000001C0
+#define PHY_VREF_TRAINING		0x000001C8
+#define PHY_SCL_GATE_TIMING		0x000001E0
+
+#endif /* _DDRPHY_LD20_REGS_H */

arch/arm/mach-uniphier/dram/umc-ld20-regs.h

@@ -0,0 +1,73 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ */
+
+#ifndef UMC_LD20_REGS_H
+#define UMC_LD20_REGS_H
+
+#define UMC_CMDCTLA		0x00000000
+#define UMC_CMDCTLB		0x00000004
+#define UMC_CMDCTLC		0x00000008
+#define UMC_INITCTLA		0x00000020
+#define UMC_INITCTLB		0x00000024
+#define UMC_INITCTLC		0x00000028
+#define UMC_DRMMR0		0x00000030
+#define UMC_DRMMR1		0x00000034
+#define UMC_DRMMR2		0x00000038
+#define UMC_DRMMR3		0x0000003C
+#define UMC_INITSET		0x00000040
+#define UMC_INITSTAT		0x00000044
+#define UMC_CMDCTLE		0x00000050
+#define UMC_SPCSETB		0x00000084
+#define   UMC_SPCSETB_AREFMD_MASK	(0x3)	/* Auto Refresh Mode */
+#define   UMC_SPCSETB_AREFMD_ARB	(0x0)	/* control by arbitor */
+#define   UMC_SPCSETB_AREFMD_CONT	(0x1)	/* control by DRAMCONT */
+#define   UMC_SPCSETB_AREFMD_REG	(0x2)	/* control by register */
+#define UMC_ACSCTLA		0x000000C0
+#define UMC_ACSSETA		0x000000C4
+#define UMC_MEMCONF0A		0x00000200
+#define UMC_MEMCONF0B		0x00000204
+#define UMC_MEMCONFCH		0x00000240
+#define UMC_MEMMAPSET		0x00000250
+#define UMC_FLOWCTLA		0x00000400
+#define UMC_FLOWCTLB		0x00000404
+#define UMC_FLOWCTLC		0x00000408
+#define UMC_FLOWCTLG		0x00000508
+#define UMC_RDATACTL_D0		0x00000600
+#define UMC_WDATACTL_D0		0x00000604
+#define UMC_RDATACTL_D1		0x00000608
+#define UMC_WDATACTL_D1		0x0000060C
+#define UMC_DATASET		0x00000610
+#define UMC_ODTCTL_D0		0x00000618
+#define UMC_ODTCTL_D1		0x0000061C
+#define UMC_RESPCTL		0x00000624
+#define UMC_DIRECTBUSCTRLA	0x00000680
+#define UMC_DCCGCTL		0x00000720
+#define UMC_DICGCTLA		0x00000724
+#define UMC_DICGCTLB		0x00000728
+#define UMC_ERRMASKA		0x00000958
+#define UMC_ERRMASKB		0x0000095C
+#define UMC_BSICMAPSET		0x00000988
+#define UMC_DIOCTLA		0x00000C00
+#define   UMC_DIOCTLA_CTL_NRST		BIT(8)	/* ctl_rst_n */
+#define   UMC_DIOCTLA_CFG_NRST		BIT(0)	/* cfg_rst_n */
+#define UMC_DFISTCTLC		0x00000C18
+#define UMC_DFICUPDCTLA		0x00000C20
+#define UMC_DFIPUPDCTLA		0x00000C30
+#define UMC_DFICSOVRRD		0x00000C84
+#define UMC_DFITURNOFF          0x00000C88
+
+/* UM registers */
+#define UMC_MBUS0		0x00080004
+#define UMC_MBUS1		0x00081004
+#define UMC_MBUS2		0x00082004
+#define UMC_MBUS3		0x00000C78
+#define UMC_MBUS4		0x00000CF8
+#define UMC_MBUS5		0x00000E78
+#define UMC_MBUS6		0x00000EF8
+#define UMC_MBUS7		0x00001278
+#define UMC_MBUS8		0x000012F8
+#define UMC_MBUS9		0x00002478
+#define UMC_MBUS10		0x000024F8
+
+#endif /* UMC_LD20_REGS_H */

arch/arm/mach-uniphier/dram/umc-ld20.c

@@ -0,0 +1,306 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ *
+ * based on commit f7a4c9efe333fb1536efa86f9e96dc0ee109fedd of Diag
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/bitops.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+#include <asm/processor.h>
+
+#include "../init.h"
+#include "ddrphy-ld20-regs.h"
+#include "umc-ld20-regs.h"
+
+#define DRAM_CH_NR	3
+
+enum dram_freq {
+	DRAM_FREQ_1866M,
+	DRAM_FREQ_NR,
+};
+
+enum dram_size {
+	DRAM_SZ_256M,
+	DRAM_SZ_512M,
+	DRAM_SZ_NR,
+};
+
+/* umc */
+static u32 umc_initctla[DRAM_FREQ_NR] = {0x71016D11};
+static u32 umc_initctlb[DRAM_FREQ_NR] = {0x07E390AC};
+static u32 umc_initctlc[DRAM_FREQ_NR] = {0x00FF00FF};
+static u32 umc_drmmr0[DRAM_FREQ_NR] = {0x00000114};
+static u32 umc_drmmr2[DRAM_FREQ_NR] = {0x000002a0};
+
+static u32 umc_memconf0a[DRAM_FREQ_NR] = {0x00000801};
+static u32 umc_memconf0b[DRAM_FREQ_NR] = {0x00000130};
+static u32 umc_memconfch[DRAM_FREQ_NR] = {0x00033803};
+
+static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x060D0D20};
+static u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x2D211C08};
+static u32 umc_cmdctlc[DRAM_FREQ_NR] = {0x00150C04};
+static u32 umc_cmdctle[DRAM_FREQ_NR][DRAM_SZ_NR] = {
+	{0x0049071D, 0x0078071D},
+};
+
+static u32 umc_rdatactl_d0[DRAM_FREQ_NR] = {0x00000610};
+static u32 umc_rdatactl_d1[DRAM_FREQ_NR] = {0x00000610};
+static u32 umc_wdatactl_d0[DRAM_FREQ_NR] = {0x00000204};
+static u32 umc_wdatactl_d1[DRAM_FREQ_NR] = {0x00000204};
+static u32 umc_odtctl_d0[DRAM_FREQ_NR] = {0x02000002};
+static u32 umc_odtctl_d1[DRAM_FREQ_NR] = {0x02000002};
+static u32 umc_dataset[DRAM_FREQ_NR] = {0x04000000};
+
+static u32 umc_flowctla[DRAM_FREQ_NR] = {0x0081E01E};
+static u32 umc_directbusctrla[DRAM_CH_NR] = {
+	0x00000000, 0x00000001, 0x00000001
+};
+
+/* DDR PHY */
+static void ddrphy_init(void __iomem *phy_base, enum dram_freq freq)
+{
+	writel(0x00000001, phy_base + PHY_UNIQUIFY_TSMC_IO_1);
+	while ((readl(phy_base + PHY_UNIQUIFY_TSMC_IO_1) & BIT(1)))
+		cpu_relax();
+
+	writel(0x00000000, phy_base + PHY_DLL_INCR_TRIM_3);
+	writel(0x00000000, phy_base + PHY_DLL_INCR_TRIM_1);
+	writel(0x00000000, phy_base + PHY_LANE_SEL);
+	writel(0x00000005, phy_base + PHY_DLL_TRIM_1);
+	writel(0x0000000a, phy_base + PHY_DLL_TRIM_3);
+	writel(0x00000006, phy_base + PHY_LANE_SEL);
+	writel(0x00000005, phy_base + PHY_DLL_TRIM_1);
+	writel(0x0000000a, phy_base + PHY_DLL_TRIM_3);
+	writel(0x0000000c, phy_base + PHY_LANE_SEL);
+	writel(0x00000005, phy_base + PHY_DLL_TRIM_1);
+	writel(0x0000000a, phy_base + PHY_DLL_TRIM_3);
+	writel(0x00000012, phy_base + PHY_LANE_SEL);
+	writel(0x00000005, phy_base + PHY_DLL_TRIM_1);
+	writel(0x0000000a, phy_base + PHY_DLL_TRIM_3);
+	writel(0x00000001, phy_base + PHY_SCL_WINDOW_TRIM);
+	writel(0x00000000, phy_base + PHY_UNQ_ANALOG_DLL_1);
+	writel(0x50bb40b1, phy_base + PHY_PAD_CTRL);
+	writel(0x00000070, phy_base + PHY_VREF_TRAINING);
+	writel(0x01000075, phy_base + PHY_SCL_CONFIG_1);
+	writel(0x00000501, phy_base + PHY_SCL_CONFIG_2);
+	writel(0x00000000, phy_base + PHY_SCL_CONFIG_3);
+	writel(0x000261c0, phy_base + PHY_DYNAMIC_WRITE_BIT_LVL);
+	writel(0x00000000, phy_base + PHY_SCL_CONFIG_4);
+	writel(0x000000a0, phy_base + PHY_SCL_GATE_TIMING);
+	writel(0x02a000a0, phy_base + PHY_WRLVL_DYN_ODT);
+	writel(0x00840004, phy_base + PHY_WRLVL_ON_OFF);
+	writel(0x0000020d, phy_base + PHY_DLL_ADRCTRL);
+	writel(0x00000000, phy_base + PHY_LANE_SEL);
+	writel(0x0000008d, phy_base + PHY_DLL_TRIM_CLK);
+	writel(0xa800100d, phy_base + PHY_DLL_RECALIB);
+	writel(0x00005076, phy_base + PHY_SCL_LATENCY);
+}
+
+static int ddrphy_training(void __iomem *phy_base)
+{
+	writel(0x0000000f, phy_base + PHY_WRLVL_AUTOINC_TRIM);
+	writel(0x00010000, phy_base + PHY_DLL_TRIM_2);
+	writel(0x50000000, phy_base + PHY_SCL_START);
+
+	while ((readl(phy_base + PHY_SCL_START) & BIT(28)))
+		cpu_relax();
+
+	writel(0x00000000, phy_base + PHY_DISABLE_GATING_FOR_SCL);
+	writel(0xff00ff00, phy_base + PHY_SCL_DATA_0);
+	writel(0xff00ff00, phy_base + PHY_SCL_DATA_1);
+	writel(0x00080000, phy_base + PHY_SCL_START_ADDR);
+	writel(0x11000000, phy_base + PHY_SCL_START);
+
+	while ((readl(phy_base + PHY_SCL_START) & BIT(28)))
+		cpu_relax();
+
+	writel(0x00000000, phy_base + PHY_SCL_START_ADDR);
+	writel(0x30500000, phy_base + PHY_SCL_START);
+
+	while ((readl(phy_base + PHY_SCL_START) & BIT(28)))
+		cpu_relax();
+
+	writel(0x00000001, phy_base + PHY_DISABLE_GATING_FOR_SCL);
+	writel(0x00000010, phy_base + PHY_SCL_MAIN_CLK_DELTA);
+	writel(0x789b3de0, phy_base + PHY_SCL_DATA_0);
+	writel(0xf10e4a56, phy_base + PHY_SCL_DATA_1);
+	writel(0x11000000, phy_base + PHY_SCL_START);
+
+	while ((readl(phy_base + PHY_SCL_START) & BIT(28)))
+		cpu_relax();
+
+	writel(0x34000000, phy_base + PHY_SCL_START);
+
+	while ((readl(phy_base + PHY_SCL_START) & BIT(28)))
+		cpu_relax();
+
+	writel(0x00000003, phy_base + PHY_DISABLE_GATING_FOR_SCL);
+
+	return 0;
+}
+
+static int umc_dc_init(void __iomem *dc_base, enum dram_freq freq,
+		       unsigned long size, int ch)
+{
+	enum dram_size size_e;
+
+	switch (size) {
+	case 0:
+		return 0;
+	case SZ_256M:
+		size_e = DRAM_SZ_256M;
+		break;
+	case SZ_512M:
+		size_e = DRAM_SZ_512M;
+		break;
+	default:
+		pr_err("unsupported DRAM size 0x%08lx (per 16bit) for ch%d\n",
+		       size, ch);
+		return -EINVAL;
+	}
+
+	/* Wait for PHY Init Complete */
+	while (!(readl(dc_base + UMC_DFISTCTLC) & BIT(0)))
+		cpu_relax();
+
+	writel(0x00000001, dc_base + UMC_DFICSOVRRD);
+	writel(0x00000000, dc_base + UMC_DFITURNOFF);
+
+	writel(umc_initctla[freq], dc_base + UMC_INITCTLA);
+	writel(umc_initctlb[freq], dc_base + UMC_INITCTLB);
+	writel(umc_initctlc[freq], dc_base + UMC_INITCTLC);
+
+	writel(umc_drmmr0[freq], dc_base + UMC_DRMMR0);
+	writel(0x00000004, dc_base + UMC_DRMMR1);
+	writel(umc_drmmr2[freq], dc_base + UMC_DRMMR2);
+	writel(0x00000000, dc_base + UMC_DRMMR3);
+
+	writel(umc_memconf0a[freq], dc_base + UMC_MEMCONF0A);
+	writel(umc_memconf0b[freq], dc_base + UMC_MEMCONF0B);
+	writel(umc_memconfch[freq], dc_base + UMC_MEMCONFCH);
+	writel(0x00000008, dc_base + UMC_MEMMAPSET);
+
+	writel(umc_cmdctla[freq], dc_base + UMC_CMDCTLA);
+	writel(umc_cmdctlb[freq], dc_base + UMC_CMDCTLB);
+	writel(umc_cmdctlc[freq], dc_base + UMC_CMDCTLC);
+	writel(umc_cmdctle[freq][size_e], dc_base + UMC_CMDCTLE);
+
+	writel(umc_rdatactl_d0[freq], dc_base + UMC_RDATACTL_D0);
+	writel(umc_rdatactl_d1[freq], dc_base + UMC_RDATACTL_D1);
+
+	writel(umc_wdatactl_d0[freq], dc_base + UMC_WDATACTL_D0);
+	writel(umc_wdatactl_d1[freq], dc_base + UMC_WDATACTL_D1);
+	writel(umc_odtctl_d0[freq], dc_base + UMC_ODTCTL_D0);
+	writel(umc_odtctl_d1[freq], dc_base + UMC_ODTCTL_D1);
+	writel(umc_dataset[freq], dc_base + UMC_DATASET);
+
+	writel(0x00400020, dc_base + UMC_DCCGCTL);
+	writel(0x00000003, dc_base + UMC_ACSCTLA);
+	writel(0x00000103, dc_base + UMC_FLOWCTLG);
+	writel(0x00010200, dc_base + UMC_ACSSETA);
+
+	writel(umc_flowctla[freq], dc_base + UMC_FLOWCTLA);
+	writel(0x00004444, dc_base + UMC_FLOWCTLC);
+	writel(0x00000000, dc_base + UMC_DFICUPDCTLA);
+
+	writel(0x00202000, dc_base + UMC_FLOWCTLB);
+	writel(0x00000000, dc_base + UMC_BSICMAPSET);
+	writel(0x00000000, dc_base + UMC_ERRMASKA);
+	writel(0x00000000, dc_base + UMC_ERRMASKB);
+
+	writel(umc_directbusctrla[ch], dc_base + UMC_DIRECTBUSCTRLA);
+
+	writel(0x00000001, dc_base + UMC_INITSET);
+	/* Wait for PHY Init Complete */
+	while (readl(dc_base + UMC_INITSTAT) & BIT(0))
+		cpu_relax();
+
+	writel(0x2A0A0A00, dc_base + UMC_SPCSETB);
+	writel(0x00000000, dc_base + UMC_DFICSOVRRD);
+
+	return 0;
+}
+
+static int umc_ch_init(void __iomem *umc_ch_base, void __iomem *phy_ch_base,
+		       enum dram_freq freq, unsigned long size, int ch)
+{
+	void __iomem *dc_base = umc_ch_base + 0x00011000;
+	void __iomem *phy_base = phy_ch_base;
+	int ret;
+
+	/* PHY Update Mode (ON) */
+	writel(0x8000003f, dc_base + UMC_DFIPUPDCTLA);
+
+	/* deassert PHY reset signals */
+	writel(UMC_DIOCTLA_CTL_NRST | UMC_DIOCTLA_CFG_NRST,
+	       dc_base + UMC_DIOCTLA);
+
+	ddrphy_init(phy_base, freq);
+
+	ret = umc_dc_init(dc_base, freq, size, ch);
+	if (ret)
+		return ret;
+
+	ret = ddrphy_training(phy_base);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static void um_init(void __iomem *um_base)
+{
+	writel(0x000000ff, um_base + UMC_MBUS0);
+	writel(0x000000ff, um_base + UMC_MBUS1);
+	writel(0x000000ff, um_base + UMC_MBUS2);
+	writel(0x00000001, um_base + UMC_MBUS3);
+	writel(0x00000001, um_base + UMC_MBUS4);
+	writel(0x00000001, um_base + UMC_MBUS5);
+	writel(0x00000001, um_base + UMC_MBUS6);
+	writel(0x00000001, um_base + UMC_MBUS7);
+	writel(0x00000001, um_base + UMC_MBUS8);
+	writel(0x00000001, um_base + UMC_MBUS9);
+	writel(0x00000001, um_base + UMC_MBUS10);
+}
+
+int uniphier_ld20_umc_init(const struct uniphier_board_data *bd)
+{
+	void __iomem *um_base = (void __iomem *)0x5b600000;
+	void __iomem *umc_ch_base = (void __iomem *)0x5b800000;
+	void __iomem *phy_ch_base = (void __iomem *)0x6e200000;
+	enum dram_freq freq;
+	int ch, ret;
+
+	switch (bd->dram_freq) {
+	case 1866:
+		freq = DRAM_FREQ_1866M;
+		break;
+	default:
+		pr_err("unsupported DRAM frequency %d MHz\n", bd->dram_freq);
+		return -EINVAL;
+	}
+
+	for (ch = 0; ch < bd->dram_nr_ch; ch++) {
+		unsigned long size = bd->dram_ch[ch].size;
+		unsigned int width = bd->dram_ch[ch].width;
+
+		ret = umc_ch_init(umc_ch_base, phy_ch_base, freq,
+				  size / (width / 16), ch);
+		if (ret) {
+			pr_err("failed to initialize UMC ch%d\n", ch);
+			return ret;
+		}
+
+		umc_ch_base += 0x00200000;
+		phy_ch_base += 0x00004000;
+	}
+
+	um_init(um_base);
+
+	return 0;
+}

arch/arm/mach-uniphier/dram_init.c

@@ -6,6 +6,7 @@
 
 #include <common.h>
 #include <libfdt.h>
+#include <fdtdec.h>
 #include <linux/err.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -40,8 +41,7 @@ int dram_init(void)
 
 	val += ac;
 
-	gd->ram_size = sc == 2 ? fdt64_to_cpu(*(fdt64_t *)val) :
-							fdt32_to_cpu(*val);
+	gd->ram_size = fdtdec_get_number(val, sc);
 
 	debug("DRAM size = %08lx\n", (unsigned long)gd->ram_size);
 
@@ -71,11 +71,9 @@ void dram_init_banksize(void)
 
 	for (i = 0; i < CONFIG_NR_DRAM_BANKS && len >= cells;
 	     i++, len -= cells) {
-		gd->bd->bi_dram[i].start = ac == 2 ?
-			fdt64_to_cpu(*(fdt64_t *)val) : fdt32_to_cpu(*val);
+		gd->bd->bi_dram[i].start = fdtdec_get_number(val, ac);
 		val += ac;
-		gd->bd->bi_dram[i].size = sc == 2 ?
-			fdt64_to_cpu(*(fdt64_t *)val) : fdt32_to_cpu(*val);
+		gd->bd->bi_dram[i].size = fdtdec_get_number(val, sc);
 		val += sc;
 
 		debug("DRAM bank %d: start = %08lx, size = %08lx\n",

arch/arm/mach-uniphier/early-clk/Makefile

@@ -9,3 +9,4 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= early-clk-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PRO5)	+= early-clk-pro5.o
 obj-$(CONFIG_ARCH_UNIPHIER_PXS2)	+= early-clk-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD6B)	+= early-clk-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= early-clk-ld20.o

arch/arm/mach-uniphier/early-clk/early-clk-ld20.c

@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sc64-regs.h"
+
+int uniphier_ld20_early_clk_init(const struct uniphier_board_data *bd)
+{
+	u32 tmp;
+
+	/* deassert reset */
+	tmp = readl(SC_RSTCTRL7);
+	tmp |= SC_RSTCTRL7_UMCSB | SC_RSTCTRL7_UMCA2 | SC_RSTCTRL7_UMCA1 |
+		SC_RSTCTRL7_UMCA0 | SC_RSTCTRL7_UMC32 | SC_RSTCTRL7_UMC31 |
+		SC_RSTCTRL7_UMC30;
+	writel(tmp, SC_RSTCTRL7);
+
+	/* provide clocks */
+	tmp = readl(SC_CLKCTRL4);
+	tmp |= SC_CLKCTRL4_PERI;
+	writel(tmp, SC_CLKCTRL4);
+
+	tmp = readl(SC_CLKCTRL7);
+	tmp |= SC_CLKCTRL7_UMCSB | SC_CLKCTRL7_UMC32 | SC_CLKCTRL7_UMC31 |
+							SC_CLKCTRL7_UMC30;
+	writel(tmp, SC_CLKCTRL7);
+
+	return 0;
+}

arch/arm/mach-uniphier/early-pinctrl/Makefile

@@ -3,3 +3,4 @@
 #
 
 obj-$(CONFIG_ARCH_UNIPHIER_SLD3)	+= early-pinctrl-sld3.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= early-pinctrl-ld20.o

arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-ld20.c

@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include "../init.h"
+#include "../sg-regs.h"
+
+int uniphier_ld20_early_pin_init(const struct uniphier_board_data *bd)
+{
+	/* Comment format:    PAD Name -> Function Name */
+	sg_set_pinsel(0, 0, 8, 4);	/* XECS1  -> XECS1 */
+	sg_set_pinsel(1, 0, 8, 4);	/* ERXW   -> ERXW  */
+	sg_set_pinsel(2, 0, 8, 4);	/* XERWE1 -> XERWE1 */
+	sg_set_pinsel(6, 2, 8, 4);	/* XNFRE  -> XERWE0 */
+	sg_set_pinsel(7, 2, 8, 4);	/* XNFWE  -> ES0 */
+	sg_set_pinsel(8, 2, 8, 4);	/* NFALE  -> ES1 */
+	sg_set_pinsel(9, 2, 8, 4);	/* NFCLE  -> ES2 */
+	sg_set_pinsel(10, 2, 8, 4);	/* NFD0   -> ED0 */
+	sg_set_pinsel(11, 2, 8, 4);	/* NFD1   -> ED1 */
+	sg_set_pinsel(12, 2, 8, 4);	/* NFD2   -> ED2 */
+	sg_set_pinsel(13, 2, 8, 4);	/* NFD3   -> ED3 */
+	sg_set_pinsel(14, 2, 8, 4);	/* NFD4   -> ED4 */
+	sg_set_pinsel(15, 2, 8, 4);	/* NFD5   -> ED5 */
+	sg_set_pinsel(16, 2, 8, 4);	/* NFD6   -> ED6 */
+	sg_set_pinsel(17, 2, 8, 4);	/* NFD7   -> ED7 */
+	sg_set_iectrl_range(0, 2);
+	sg_set_iectrl_range(6, 17);
+
+	return 0;
+}

arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-sld3.c

@@ -22,5 +22,7 @@ int uniphier_sld3_early_pin_init(const struct uniphier_board_data *bd)
 	sg_set_pinsel(102, 2, 4, 4);	/* TXD2 */
 #endif
 
+	sg_set_pinsel(99, 1, 4, 4);	/* GPIO26 -> EA24 */
+
 	return 0;
 }

arch/arm/mach-uniphier/init.h

@@ -32,11 +32,11 @@ int uniphier_pro4_init(const struct uniphier_board_data *bd);
 int uniphier_sld8_init(const struct uniphier_board_data *bd);
 int uniphier_pro5_init(const struct uniphier_board_data *bd);
 int uniphier_pxs2_init(const struct uniphier_board_data *bd);
+int uniphier_ld20_init(const struct uniphier_board_data *bd);
 
 #if defined(CONFIG_MICRO_SUPPORT_CARD)
 int uniphier_sbc_init_admulti(const struct uniphier_board_data *bd);
 int uniphier_sbc_init_savepin(const struct uniphier_board_data *bd);
-int uniphier_sld3_sbc_init(const struct uniphier_board_data *bd);
 int uniphier_ld4_sbc_init(const struct uniphier_board_data *bd);
 int uniphier_pxs2_sbc_init(const struct uniphier_board_data *bd);
 #else
@@ -52,11 +52,6 @@ static inline int uniphier_sbc_init_savepin(
 	return 0;
 }
 
-static inline int uniphier_sld3_sbc_init(const struct uniphier_board_data *bd)
-{
-	return 0;
-}
-
 static inline int uniphier_ld4_sbc_init(const struct uniphier_board_data *bd)
 {
 	return 0;
@@ -86,13 +81,16 @@ int uniphier_ld4_enable_dpll_ssc(const struct uniphier_board_data *bd);
 int uniphier_ld4_early_clk_init(const struct uniphier_board_data *bd);
 int uniphier_pro5_early_clk_init(const struct uniphier_board_data *bd);
 int uniphier_pxs2_early_clk_init(const struct uniphier_board_data *bd);
+int uniphier_ld20_early_clk_init(const struct uniphier_board_data *bd);
 
 int uniphier_sld3_early_pin_init(const struct uniphier_board_data *bd);
+int uniphier_ld20_early_pin_init(const struct uniphier_board_data *bd);
 
 int uniphier_ld4_umc_init(const struct uniphier_board_data *bd);
 int uniphier_pro4_umc_init(const struct uniphier_board_data *bd);
 int uniphier_sld8_umc_init(const struct uniphier_board_data *bd);
 int uniphier_pxs2_umc_init(const struct uniphier_board_data *bd);
+int uniphier_ld20_umc_init(const struct uniphier_board_data *bd);
 
 void uniphier_sld3_pin_init(void);
 void uniphier_ld4_pin_init(void);
@@ -101,11 +99,15 @@ void uniphier_sld8_pin_init(void);
 void uniphier_pro5_pin_init(void);
 void uniphier_pxs2_pin_init(void);
 void uniphier_ld6b_pin_init(void);
+void uniphier_ld20_pin_init(void);
 
 void uniphier_ld4_clk_init(void);
 void uniphier_pro4_clk_init(void);
 void uniphier_pro5_clk_init(void);
 void uniphier_pxs2_clk_init(void);
+void uniphier_ld20_clk_init(void);
+
+void cci500_init(int nr_slaves);
 
 #define pr_err(fmt, args...)	printf(fmt, ##args)
 

arch/arm/mach-uniphier/init/Makefile

@@ -11,3 +11,4 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= init-sld8.o
 obj-$(CONFIG_ARCH_UNIPHIER_PRO5)	+= init-pro5.o
 obj-$(CONFIG_ARCH_UNIPHIER_PXS2)	+= init-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD6B)	+= init-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= init-ld20.o

arch/arm/mach-uniphier/init/init-ld20.c

@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+
+#include "../init.h"
+#include "../micro-support-card.h"
+
+int uniphier_ld20_init(const struct uniphier_board_data *bd)
+{
+	uniphier_sbc_init_savepin(bd);
+	uniphier_pxs2_sbc_init(bd);
+	uniphier_ld20_early_pin_init(bd);
+
+	support_card_reset();
+
+	support_card_init();
+
+	led_puts("L0");
+
+	memconf_init(bd);
+	uniphier_pxs2_memconf_init(bd);
+
+	led_puts("L1");
+
+	uniphier_ld20_early_clk_init(bd);
+
+	led_puts("L2");
+
+	led_puts("L3");
+
+#ifdef CONFIG_SPL_SERIAL_SUPPORT
+	preloader_console_init();
+#endif
+
+	led_puts("L4");
+
+	{
+		int res;
+
+		res = uniphier_ld20_umc_init(bd);
+		if (res < 0) {
+			while (1)
+				;
+		}
+	}
+
+	led_puts("L5");
+
+	return 0;
+}

arch/arm/mach-uniphier/init/init-sld3.c

@@ -15,7 +15,8 @@ int uniphier_sld3_init(const struct uniphier_board_data *bd)
 	uniphier_sld3_bcu_init(bd);
 
 	uniphier_sbc_init_admulti(bd);
-	uniphier_sld3_sbc_init(bd);
+
+	uniphier_sld3_early_pin_init(bd);
 
 	support_card_reset();
 
@@ -34,8 +35,6 @@ int uniphier_sld3_init(const struct uniphier_board_data *bd)
 
 	led_puts("L2");
 
-	uniphier_sld3_early_pin_init(bd);
-
 	led_puts("L3");
 
 #ifdef CONFIG_SPL_SERIAL_SUPPORT

arch/arm/mach-uniphier/init/init.c

@@ -54,6 +54,11 @@ void spl_board_init(void)
 	case SOC_UNIPHIER_LD6B:
 		uniphier_pxs2_init(param);
 		break;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD20)
+	case SOC_UNIPHIER_LD20:
+		uniphier_ld20_init(param);
+		break;
 #endif
 	default:
 		break;

arch/arm/mach-uniphier/memconf/Makefile

@@ -6,3 +6,4 @@ obj-y					+= memconf.o
 obj-$(CONFIG_ARCH_UNIPHIER_SLD3)	+= memconf-sld3.o
 obj-$(CONFIG_ARCH_UNIPHIER_PXS2)	+= memconf-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD6B)	+= memconf-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= memconf-pxs2.o

arch/arm/mach-uniphier/memconf/memconf-pxs2.c

@@ -49,6 +49,9 @@ int uniphier_pxs2_memconf_init(const struct uniphier_board_data *bd)
 	case SZ_512M:
 		tmp |= SG_MEMCONF_CH2_SZ_512M;
 		break;
+	case SZ_1G:
+		tmp |= SG_MEMCONF_CH2_SZ_1G;
+		break;
 	default:
 		pr_err("error: unsupported DRAM Ch2 size\n");
 		return -EINVAL;

arch/arm/mach-uniphier/pinctrl/Makefile

@@ -9,3 +9,4 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= pinctrl-sld8.o
 obj-$(CONFIG_ARCH_UNIPHIER_PRO5)	+= pinctrl-pro5.o
 obj-$(CONFIG_ARCH_UNIPHIER_PXS2)	+= pinctrl-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD6B)	+= pinctrl-ld6b.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= pinctrl-ld20.o

arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c

@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
+
+void uniphier_ld20_pin_init(void)
+{
+	/* Comment format:    PAD Name -> Function Name */
+
+#ifdef CONFIG_NAND_DENALI
+	sg_set_pinsel(3, 0, 8, 4);	/* XNFWP   -> XNFWP */
+	sg_set_pinsel(4, 0, 8, 4);	/* XNFCE0  -> XNFCE0 */
+	sg_set_pinsel(5, 0, 8, 4);	/* NFRYBY0 -> NFRYBY0 */
+	sg_set_pinsel(6, 0, 8, 4);	/* XNFRE   -> XNFRE */
+	sg_set_pinsel(7, 0, 8, 4);	/* XNFWE   -> XNFWE */
+	sg_set_pinsel(8, 0, 8, 4);	/* NFALE   -> NFALE */
+	sg_set_pinsel(9, 0, 8, 4);	/* NFCLE   -> NFCLE */
+	sg_set_pinsel(10, 0, 8, 4);	/* NFD0    -> NFD0 */
+	sg_set_pinsel(11, 0, 8, 4);	/* NFD1    -> NFD1 */
+	sg_set_pinsel(12, 0, 8, 4);	/* NFD2    -> NFD2 */
+	sg_set_pinsel(13, 0, 8, 4);	/* NFD3    -> NFD3 */
+	sg_set_pinsel(14, 0, 8, 4);	/* NFD4    -> NFD4 */
+	sg_set_pinsel(15, 0, 8, 4);	/* NFD5    -> NFD5 */
+	sg_set_pinsel(16, 0, 8, 4);	/* NFD6    -> NFD6 */
+	sg_set_pinsel(17, 0, 8, 4);	/* NFD7    -> NFD7 */
+	sg_set_iectrl_range(3, 17);
+#endif
+
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+	sg_set_pinsel(46, 0, 8, 4);	/* USB0VBUS -> USB0VBUS */
+	sg_set_pinsel(47, 0, 8, 4);	/* USB0OD   -> USB0OD */
+	sg_set_pinsel(48, 0, 8, 4);	/* USB1VBUS -> USB1VBUS */
+	sg_set_pinsel(49, 0, 8, 4);	/* USB1OD   -> USB1OD */
+	sg_set_pinsel(50, 0, 8, 4);	/* USB2VBUS -> USB2VBUS */
+	sg_set_pinsel(51, 0, 8, 4);	/* USB2OD   -> USB2OD */
+	sg_set_pinsel(52, 0, 8, 4);	/* USB3VBUS -> USB3VBUS */
+	sg_set_pinsel(53, 0, 8, 4);	/* USB3OD   -> USB3OD */
+	sg_set_iectrl_range(46, 53);
+#endif
+}

arch/arm/mach-uniphier/sbc/Makefile

@@ -2,10 +2,11 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-$(CONFIG_ARCH_UNIPHIER_SLD3)	+= sbc-admulti.o sbc-sld3.o
+obj-$(CONFIG_ARCH_UNIPHIER_SLD3)	+= sbc-admulti.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD4)		+= sbc-savepin.o sbc-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PRO4)	+= sbc-savepin.o
 obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= sbc-savepin.o sbc-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PRO5)	+= sbc-savepin.o
 obj-$(CONFIG_ARCH_UNIPHIER_PXS2)	+= sbc-savepin.o sbc-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD6B)	+= sbc-savepin.o sbc-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= sbc-savepin.o sbc-pxs2.o

arch/arm/mach-uniphier/sbc/sbc-sld3.c

@@ -1,17 +0,0 @@
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <linux/io.h>
-
-#include "../init.h"
-#include "../sg-regs.h"
-
-int uniphier_sld3_sbc_init(const struct uniphier_board_data *bd)
-{
-	sg_set_pinsel(99, 1, 4, 4);	/* GPIO26 -> EA24 */
-
-	return 0;
-}

arch/arm/mach-uniphier/sg-regs.h

@@ -50,10 +50,11 @@
 #define SG_MEMCONF_CH2_SZ_128M		((0x0 << 26) | (0x02 << 16))
 #define SG_MEMCONF_CH2_SZ_256M		((0x0 << 26) | (0x03 << 16))
 #define SG_MEMCONF_CH2_SZ_512M		((0x1 << 26) | (0x00 << 16))
+#define SG_MEMCONF_CH2_SZ_1G		((0x1 << 26) | (0x01 << 16))
 #define SG_MEMCONF_CH2_NUM_MASK		(0x1 << 24)
 #define SG_MEMCONF_CH2_NUM_1		(0x1 << 24)
 #define SG_MEMCONF_CH2_NUM_2		(0x0 << 24)
-/* PH1-LD6b, ProXstream2 only */
+/* PH1-LD6b, ProXstream2, PH1-LD20 only */
 #define SG_MEMCONF_CH2_DISABLE		(0x1 << 21)
 
 #define SG_MEMCONF_SPARSEMEM		(0x1 << 4)
@@ -126,6 +127,14 @@ static inline void sg_set_iectrl(unsigned pin)
 	writel(tmp, reg);
 }
 
+static inline void sg_set_iectrl_range(unsigned min, unsigned max)
+{
+	int i;
+
+	for (i = min; i <= max; i++)
+		sg_set_iectrl(i);
+}
+
 #endif /* __ASSEMBLY__ */
 
 #endif /* ARCH_SG_REGS_H */

arch/avr32/cpu/mmc.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (C) 2004-2006 Atmel Corporation
- * Copyright (C) 2015 Andreas Bießmann <andreas.devel@googlmail.com>
+ * Copyright (C) 2015 Andreas Bießmann <andreas@biessmann.org>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

arch/avr32/lib/bootm.c

@@ -174,7 +174,7 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima
 	/*
 	 * allow the PREP bootm subcommand, it is required for bootm to work
 	 *
-	 * TODO: Andreas Bießmann <andreas.devel@googlemail.com> refactor the
+	 * TODO: Andreas Bießmann <andreas@biessmann.org> refactor the
 	 * do_bootm_linux() for avr32
 	 */
 	if (flag & BOOTM_STATE_OS_PREP)

arch/avr32/lib/dram_init.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2015 Andreas Bießmann <andreas.devel@googlemail.com>
+ * Copyright (C) 2015 Andreas Bießmann <andreas@biessmann.org>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

arch/blackfin/include/asm/config.h

@@ -138,9 +138,6 @@
 #ifndef CONFIG_SYS_BOOTM_LEN
 # define CONFIG_SYS_BOOTM_LEN 0x4000000
 #endif
-#ifndef CONFIG_SYS_PROMPT
-# define CONFIG_SYS_PROMPT "bfin> "
-#endif
 #ifndef CONFIG_SYS_CBSIZE
 # define CONFIG_SYS_CBSIZE 1024
 #elif defined(CONFIG_CMD_KGDB) && CONFIG_SYS_CBSIZE < 1024

arch/mips/Kconfig

@@ -145,7 +145,7 @@ config MIPS_BOOT_ENV_LEGACY
 	  Enable this option if you want U-Boot to hand over the Yamon-style
 	  environment to the kernel. Information like memory size, initrd
 	  address and size will be prepared as zero-terminated key/value list.
-	  The address of the enviroment is stored in register $a2.
+	  The address of the environment is stored in register $a2.
 
 config MIPS_BOOT_FDT
 	bool "Hand over a flattened device tree to Linux kernel"

arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c

@@ -1151,7 +1151,7 @@ phys_size_t initdram(int board_type)
 	dram_size *= ranks;
 	debug("dram_size = %lu\n", dram_size);
 
-	/* Start the SDRAM controler */
+	/* Start the SDRAM controller */
 	mtsdram(DDR0_02, DDR0_02_START_ENCODE(1));
 	denali_wait_for_dlllock();
 

arch/powerpc/lib/stack.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015 Andreas Bießmann <andreas.devel@googlemail.com>
+ * Copyright (c) 2015 Andreas Bießmann <andreas@biessmann.org>
  *
  * Copyright (c) 2011 The Chromium OS Authors.
  * (C) Copyright 2002-2006

arch/x86/cpu/qemu/Makefile

@@ -8,6 +8,3 @@ ifndef CONFIG_EFI_STUB
 obj-y += car.o dram.o
 endif
 obj-y += cpu.o fw_cfg.o qemu.o
-ifndef CONFIG_QEMU_ACPI_TABLE
-obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o dsdt.o
-endif

arch/x86/cpu/qemu/acpi.c

@@ -1,176 +0,0 @@
-/*
- * Copyright (C) 2015, Saket Sinha <saket.sinha89@gmail.com>
- *
- * SPDX-License-Identifier:   GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/acpi_table.h>
-#include <asm/ioapic.h>
-#include <asm/tables.h>
-
-void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
-		      void *dsdt)
-{
-	acpi_header_t *header = &(fadt->header);
-	u16 pmbase;
-
-	pci_dev_t bdf = PCI_BDF(0, 0x1f, 0);
-	pci_read_config_word(bdf, 0x40, &pmbase);
-
-	/*
-	 * TODO(saket.sinha89@gmail.com): wrong value
-	 * of pmbase by above function. Hard-coding it to
-	 * correct value. Since no PCI register is
-	 * programmed Power Management Interface is
-	 * not working
-	 */
-	pmbase = 0x0600;
-
-	memset((void *)fadt, 0, sizeof(struct acpi_fadt));
-	memcpy(header->signature, "FACP", 4);
-	header->length = sizeof(struct acpi_fadt);
-	header->revision = 3;
-	memcpy(header->oem_id, OEM_ID, 6);
-	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
-	memcpy(header->asl_compiler_id, ASLC, 4);
-	header->asl_compiler_revision = 0;
-
-	fadt->firmware_ctrl = (unsigned long) facs;
-	fadt->dsdt = (unsigned long) dsdt;
-	fadt->model = 0x00;
-	fadt->preferred_pm_profile = PM_MOBILE;
-	fadt->sci_int = 0x9;
-	fadt->smi_cmd = 0;
-	fadt->acpi_enable = 0;
-	fadt->acpi_disable = 0;
-	fadt->s4bios_req = 0x0;
-	fadt->pstate_cnt = 0;
-	fadt->pm1a_evt_blk = pmbase;
-	fadt->pm1b_evt_blk = 0x0;
-	fadt->pm1a_cnt_blk = pmbase + 0x4;
-	fadt->pm1b_cnt_blk = 0x0;
-	fadt->pm2_cnt_blk = pmbase + 0x50;
-	fadt->pm_tmr_blk = pmbase + 0x8;
-	fadt->gpe0_blk = pmbase + 0x20;
-	fadt->gpe1_blk = 0;
-	fadt->pm1_evt_len = 4;
-	/*
-	 * Upper word is reserved and
-	 * Linux complains about 32 bit
-	 */
-	fadt->pm1_cnt_len = 2;
-	fadt->pm2_cnt_len = 1;
-	fadt->pm_tmr_len = 4;
-	fadt->gpe0_blk_len = 16;
-	fadt->gpe1_blk_len = 0;
-	fadt->gpe1_base = 0;
-	fadt->cst_cnt = 0;
-	fadt->p_lvl2_lat = 1;
-	fadt->p_lvl3_lat = 0x39;
-	fadt->flush_size = 0;
-	fadt->flush_stride = 0;
-	fadt->duty_offset = 1;
-	fadt->duty_width = 3;
-	fadt->day_alrm = 0xd;
-	fadt->mon_alrm = 0x00;
-	fadt->century = 0x32;
-	fadt->iapc_boot_arch = 0x00;
-	fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
-			ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE |
-			ACPI_FADT_DOCKING_SUPPORTED | ACPI_FADT_RESET_REGISTER |
-			ACPI_FADT_PLATFORM_CLOCK;
-	fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO;
-	fadt->reset_reg.bit_width = 8;
-	fadt->reset_reg.bit_offset = 0;
-	fadt->reset_reg.resv = 0;
-	fadt->reset_reg.addrl = 0xcf9;
-	fadt->reset_reg.addrh = 0;
-	fadt->reset_value = 0x06;
-	/*
-	 * Set X_FIRMWARE_CTRL only if FACS is
-	 * above 4GB. If X_FIRMWARE_CTRL is set,
-	 * then FIRMWARE_CTRL must be zero
-	 */
-	fadt->x_firmware_ctl_l = 0;
-	fadt->x_firmware_ctl_h = 0;
-	fadt->x_dsdt_l = (unsigned long)dsdt;
-	fadt->x_dsdt_h = 0;
-	fadt->x_pm1a_evt_blk.space_id = 1;
-	fadt->x_pm1a_evt_blk.bit_width = 32;
-	fadt->x_pm1a_evt_blk.bit_offset = 0;
-	fadt->x_pm1a_evt_blk.resv = 0;
-	fadt->x_pm1a_evt_blk.addrl = pmbase;
-	fadt->x_pm1a_evt_blk.addrh = 0x0;
-	fadt->x_pm1b_evt_blk.space_id = 0;
-	fadt->x_pm1b_evt_blk.bit_width = 0;
-	fadt->x_pm1b_evt_blk.bit_offset = 0;
-	fadt->x_pm1b_evt_blk.resv = 0;
-	fadt->x_pm1b_evt_blk.addrl = 0x0;
-	fadt->x_pm1b_evt_blk.addrh = 0x0;
-	fadt->x_pm1a_cnt_blk.space_id = 1;
-	/*
-	 * Upper word is reserved and
-	 * Linux complains about 32 bit
-	 */
-	fadt->x_pm1a_cnt_blk.bit_width = 16;
-	fadt->x_pm1a_cnt_blk.bit_offset = 0;
-	fadt->x_pm1a_cnt_blk.resv = 0;
-	fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
-	fadt->x_pm1a_cnt_blk.addrh = 0x0;
-	fadt->x_pm1b_cnt_blk.space_id = 0;
-	fadt->x_pm1b_cnt_blk.bit_width = 0;
-	fadt->x_pm1b_cnt_blk.bit_offset = 0;
-	fadt->x_pm1b_cnt_blk.resv = 0;
-	fadt->x_pm1b_cnt_blk.addrl = 0x0;
-	fadt->x_pm1b_cnt_blk.addrh = 0x0;
-	fadt->x_pm2_cnt_blk.space_id = 1;
-	fadt->x_pm2_cnt_blk.bit_width = 8;
-	fadt->x_pm2_cnt_blk.bit_offset = 0;
-	fadt->x_pm2_cnt_blk.resv = 0;
-	fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;
-	fadt->x_pm2_cnt_blk.addrh = 0x0;
-	fadt->x_pm_tmr_blk.space_id = 1;
-	fadt->x_pm_tmr_blk.bit_width = 32;
-	fadt->x_pm_tmr_blk.bit_offset = 0;
-	fadt->x_pm_tmr_blk.resv = 0;
-	fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
-	fadt->x_pm_tmr_blk.addrh = 0x0;
-	fadt->x_gpe0_blk.space_id = 1;
-	fadt->x_gpe0_blk.bit_width = 128;
-	fadt->x_gpe0_blk.bit_offset = 0;
-	fadt->x_gpe0_blk.resv = 0;
-	fadt->x_gpe0_blk.addrl = pmbase + 0x20;
-	fadt->x_gpe0_blk.addrh = 0x0;
-	fadt->x_gpe1_blk.space_id = 0;
-	fadt->x_gpe1_blk.bit_width = 0;
-	fadt->x_gpe1_blk.bit_offset = 0;
-	fadt->x_gpe1_blk.resv = 0;
-	fadt->x_gpe1_blk.addrl = 0x0;
-	fadt->x_gpe1_blk.addrh = 0x0;
-
-	header->checksum = table_compute_checksum((void *)fadt, header->length);
-}
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
-	/* create all subtables for processors */
-	current = acpi_create_madt_lapics(current);
-
-	/*
-	 * TODO(saket.sinha89@gmail.com): get these
-	 * IRQ values from device tree
-	 */
-	current += acpi_create_madt_ioapic((struct acpi_madt_ioapic *)current,
-					   2, IO_APIC_ADDR, 0);
-	current += acpi_create_madt_irqoverride(
-		(struct acpi_madt_irqoverride *)current, 0, 0, 2, 0);
-	current += acpi_create_madt_irqoverride(
-		(struct acpi_madt_irqoverride *)current, 0, 9, 9, 0xd);
-	current += acpi_create_madt_irqoverride(
-		(struct acpi_madt_irqoverride *)current, 0, 0xd, 0xd, 0xd);
-	acpi_create_madt_lapic_nmi(
-		(struct acpi_madt_lapic_nmi *)current, 0, 0, 0);
-
-	return current;
-}

arch/x86/cpu/qemu/acpi/cpu-hotplug.asl

@@ -1,80 +0,0 @@
-/* CPU hotplug */
-
-Scope(\_SB) {
-    /* Objects filled in by run-time generated SSDT */
-    External(NTFY, MethodObj)
-    External(CPON, PkgObj)
-
-    /* Methods called by run-time generated SSDT Processor objects */
-    Method(CPMA, 1, NotSerialized) {
-	    /*
-	     * _MAT method - create an madt apic buffer
-	     * Arg0 = Processor ID = Local APIC ID
-	     * Local0 = CPON flag for this cpu
-	     */
-        Store(DerefOf(Index(CPON, Arg0)), Local0)
-        /* Local1 = Buffer (in madt apic form) to return */
-        Store(Buffer(8) {0x00, 0x08, 0x00, 0x00, 0x00, 0, 0, 0}, Local1)
-        /* Update the processor id, lapic id, and enable/disable status */
-        Store(Arg0, Index(Local1, 2))
-        Store(Arg0, Index(Local1, 3))
-        Store(Local0, Index(Local1, 4))
-        Return (Local1)
-    }
-    Method(CPST, 1, NotSerialized) {
-	    /*
-	     * _STA method - return ON status of cpu
-	     * Arg0 = Processor ID = Local APIC ID
-	     * Local0 = CPON flag for this cpu
-	     */
-        Store(DerefOf(Index(CPON, Arg0)), Local0)
-        If (Local0) {
-            Return (0xf)
-        } Else {
-            Return (0x0)
-        }
-    }
-    Method(CPEJ, 2, NotSerialized) {
-        /* _EJ0 method - eject callback */
-        Sleep(200)
-    }
-
-    /* CPU hotplug notify method */
-    OperationRegion(PRST, SystemIO, 0xaf00, 32)
-    Field(PRST, ByteAcc, NoLock, Preserve) {
-        PRS, 256
-    }
-    Method(PRSC, 0) {
-        /* Local5 = active cpu bitmap */
-        Store(PRS, Local5)
-        /* Local2 = last read byte from bitmap */
-        Store(Zero, Local2)
-        /* Local0 = Processor ID / APIC ID iterator */
-        Store(Zero, Local0)
-        While (LLess(Local0, SizeOf(CPON))) {
-            /* Local1 = CPON flag for this cpu */
-            Store(DerefOf(Index(CPON, Local0)), Local1)
-            If (And(Local0, 0x07)) {
-                /* Shift down previously read bitmap byte */
-                ShiftRight(Local2, 1, Local2)
-            } Else {
-                /* Read next byte from cpu bitmap */
-                Store(DerefOf(Index(Local5, ShiftRight(Local0, 3))), Local2)
-            }
-            /* Local3 = active state for this cpu */
-            Store(And(Local2, 1), Local3)
-
-            If (LNotEqual(Local1, Local3)) {
-                /* State change - update CPON with new state */
-                Store(Local3, Index(CPON, Local0))
-                /* Do CPU notify */
-                If (LEqual(Local3, 1)) {
-                    NTFY(Local0, 1)
-                } Else {
-                    NTFY(Local0, 3)
-                }
-            }
-            Increment(Local0)
-        }
-    }
-}

arch/x86/cpu/qemu/acpi/dbug.asl

@@ -1,25 +0,0 @@
-/* Debugging */
-
-Scope(\) {
-    /* Debug Output */
-    OperationRegion(DBG, SystemIO, 0x0402, 0x01)
-    Field(DBG, ByteAcc, NoLock, Preserve) {
-        DBGB,   8,
-    }
-	/*
-	 * Debug method - use this method to send output to the QEMU
-	 * BIOS debug port.  This method handles strings, integers,
-	 * and buffers.  For example: DBUG("abc") DBUG(0x123)
-	 */
-    Method(DBUG, 1) {
-        ToHexString(Arg0, Local0)
-        ToBuffer(Local0, Local0)
-        Subtract(SizeOf(Local0), 1, Local1)
-        Store(Zero, Local2)
-        While (LLess(Local2, Local1)) {
-            Store(DerefOf(Index(Local0, Local2)), DBGB)
-            Increment(Local2)
-        }
-        Store(0x0a, dbgb)
-    }
-}

arch/x86/cpu/qemu/acpi/hpet.asl

@@ -1,31 +0,0 @@
-/* HPET */
-
-Scope(\_SB) {
-    Device(HPET) {
-        Name(_HID, EISAID("PNP0103"))
-        Name(_UID, 0)
-        OperationRegion(HPTM, SystemMemory, 0xfed00000, 0x400)
-        Field(HPTM, DWordAcc, Lock, Preserve) {
-            VEND, 32,
-            PRD, 32,
-        }
-        Method(_STA, 0, NotSerialized) {
-            Store(VEND, Local0)
-            Store(PRD, Local1)
-            ShiftRight(Local0, 16, Local0)
-            If (LOr(LEqual(Local0, 0), LEqual(Local0, 0xffff))) {
-                Return (0x0)
-            }
-            If (LOr(LEqual(Local1, 0), LGreater(Local1, 100000000))) {
-                Return (0x0)
-            }
-            Return (0x0f)
-        }
-        Name(_CRS, ResourceTemplate() {
-            Memory32Fixed(ReadOnly,
-                0xfed00000,         /* Address Base */
-                0x00000400,         /* Address Length */
-                )
-        })
-    }
-}

arch/x86/cpu/qemu/acpi/isa.asl

@@ -1,102 +0,0 @@
-/* Common legacy ISA style devices. */
-Scope(\_SB.PCI0.ISA) {
-
-    Device(RTC) {
-        Name(_HID, EisaId("PNP0B00"))
-        Name(_CRS, ResourceTemplate() {
-            IO(Decode16, 0x0070, 0x0070, 0x10, 0x02)
-            IRQNoFlags() { 8 }
-            IO(Decode16, 0x0072, 0x0072, 0x02, 0x06)
-        })
-    }
-
-    Device(KBD) {
-        Name(_HID, EisaId("PNP0303"))
-        Method(_STA, 0, NotSerialized) {
-            Return (0x0f)
-        }
-        Name(_CRS, ResourceTemplate() {
-            IO(Decode16, 0x0060, 0x0060, 0x01, 0x01)
-            IO(Decode16, 0x0064, 0x0064, 0x01, 0x01)
-            IRQNoFlags() { 1 }
-        })
-    }
-
-    Device(MOU) {
-        Name(_HID, EisaId("PNP0F13"))
-        Method(_STA, 0, NotSerialized) {
-            Return (0x0f)
-        }
-        Name(_CRS, ResourceTemplate() {
-            IRQNoFlags() { 12 }
-        })
-    }
-
-    Device(FDC0) {
-        Name(_HID, EisaId("PNP0700"))
-        Method(_STA, 0, NotSerialized) {
-            Store(FDEN, Local0)
-            If (LEqual(Local0, 0)) {
-                Return (0x00)
-            } Else {
-                Return (0x0f)
-            }
-        }
-        Name(_CRS, ResourceTemplate() {
-            IO(Decode16, 0x03f2, 0x03f2, 0x00, 0x04)
-            IO(Decode16, 0x03f7, 0x03f7, 0x00, 0x01)
-            IRQNoFlags() { 6 }
-            DMA(Compatibility, NotBusMaster, Transfer8) { 2 }
-        })
-    }
-
-    Device(LPT) {
-        Name(_HID, EisaId("PNP0400"))
-        Method(_STA, 0, NotSerialized) {
-            Store(LPEN, Local0)
-            If (LEqual(Local0, 0)) {
-                Return (0x00)
-            } Else {
-                Return (0x0f)
-            }
-        }
-        Name(_CRS, ResourceTemplate() {
-            IO(Decode16, 0x0378, 0x0378, 0x08, 0x08)
-            IRQNoFlags() { 7 }
-        })
-    }
-
-    Device(COM1) {
-        Name(_HID, EisaId("PNP0501"))
-        Name(_UID, 0x01)
-        Method(_STA, 0, NotSerialized) {
-            Store(CAEN, Local0)
-            If (LEqual(Local0, 0)) {
-                Return (0x00)
-            } Else {
-                Return (0x0f)
-            }
-        }
-        Name(_CRS, ResourceTemplate() {
-            IO(Decode16, 0x03f8, 0x03f8, 0x00, 0x08)
-            IRQNoFlags() { 4 }
-        })
-    }
-
-    Device(COM2) {
-        Name(_HID, EisaId("PNP0501"))
-        Name(_UID, 0x02)
-        Method(_STA, 0, NotSerialized) {
-            Store(CBEN, Local0)
-            If (LEqual(Local0, 0)) {
-                Return (0x00)
-            } Else {
-                Return (0x0f)
-            }
-        }
-        Name(_CRS, ResourceTemplate() {
-            IO(Decode16, 0x02f8, 0x02f8, 0x00, 0x08)
-            IRQNoFlags() { 3 }
-        })
-    }
-}

arch/x86/cpu/qemu/acpi/pci-crs.asl

@@ -1,61 +0,0 @@
-/* PCI CRS (current resources) definition. */
-Scope(\_SB.PCI0) {
-
-    Name(CRES, ResourceTemplate() {
-        WordBusNumber(ResourceProducer, MinFixed, MaxFixed, PosDecode,
-            0x0000,             /* Address Space Granularity */
-            0x0000,             /* Address Range Minimum */
-            0x00ff,             /* Address Range Maximum */
-            0x0000,             /* Address Translation Offset */
-            0x0100,             /* Address Length */
-            ,, )
-        IO(Decode16,
-            0x0cf8,             /* Address Range Minimum */
-            0x0cf8,             /* Address Range Maximum */
-            0x01,               /* Address Alignment */
-            0x08,               /* Address Length */
-            )
-        WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
-            0x0000,             /* Address Space Granularity */
-            0x0000,             /* Address Range Minimum */
-            0x0cf7,             /* Address Range Maximum */
-            0x0000,             /* Address Translation Offset */
-            0x0cf8,             /* Address Length */
-            ,, , TypeStatic)
-        WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
-            0x0000,             /* Address Space Granularity */
-            0x0d00,             /* Address Range Minimum */
-            0xffff,             /* Address Range Maximum */
-            0x0000,             /* Address Translation Offset */
-            0xf300,             /* Address Length */
-            ,, , TypeStatic)
-        DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
-            0x00000000,         /* Address Space Granularity */
-            0x000a0000,         /* Address Range Minimum */
-            0x000bffff,         /* Address Range Maximum */
-            0x00000000,         /* Address Translation Offset */
-            0x00020000,         /* Address Length */
-            ,, , AddressRangeMemory, TypeStatic)
-        DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
-            0x00000000,         /* Address Space Granularity */
-            0xe0000000,         /* Address Range Minimum */
-            0xfebfffff,         /* Address Range Maximum */
-            0x00000000,         /* Address Translation Offset */
-            0x1ec00000,         /* Address Length */
-            ,, PW32, AddressRangeMemory, TypeStatic)
-    })
-
-    Name(CR64, ResourceTemplate() {
-        QWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
-            0x00000000,          /* Address Space Granularity */
-            0x80000000,        /* Address Range Minimum */
-            0xffffffff,        /* Address Range Maximum */
-            0x00000000,          /* Address Translation Offset */
-            0x80000000,        /* Address Length */
-            ,, PW64, AddressRangeMemory, TypeStatic)
-    })
-
-    Method(_CRS, 0) {
-        Return (CRES)
-    }
-}

arch/x86/cpu/qemu/dsdt.asl

@@ -1,412 +0,0 @@
-/*
- * QEMU ACPI DSDT ASL definition
- *
- * Copyright (c) 2006 Fabrice Bellard
- *
- * Copyright (c) 2010 Isaku Yamahata
- *                    yamahata at valinux co jp
- * Based on acpi-dsdt.dsl, but heavily modified for q35 chipset.
- */
-
-DefinitionBlock (
-    "dsdt.aml",         /* Output Filename */
-    "DSDT",             /* Signature */
-    0x01,               /* DSDT Compliance Revision */
-    "UBOO",             /* OEMID */
-    "UBOOT   ",         /* TABLE ID */
-    0x2                 /* OEM Revision */
-    )
-{
-
-#include "acpi/dbug.asl"
-
-    Scope(\_SB) {
-        OperationRegion(PCST, SystemIO, 0xae00, 0x0c)
-        OperationRegion(PCSB, SystemIO, 0xae0c, 0x01)
-        Field(PCSB, AnyAcc, NoLock, WriteAsZeros) {
-            PCIB, 8,
-        }
-    }
-
-
-/* PCI Bus definition */
-
-    Scope(\_SB) {
-        Device(PCI0) {
-            Name(_HID, EisaId("PNP0A08"))
-            Name(_CID, EisaId("PNP0A03"))
-            Name(_ADR, 0x00)
-            Name(_UID, 1)
-
-            /* _OSC: based on sample of ACPI3.0b spec */
-            Name(SUPP, 0) /* PCI _OSC Support Field value */
-            Name(CTRL, 0) /* PCI _OSC Control Field value */
-            Method(_OSC, 4) {
-                /* Create DWORD-addressable fields from Capabilities Buffer */
-                CreateDWordField(Arg3, 0, CDW1)
-
-                /* Check for proper UUID */
-                If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")))
-			 {
-                /* Create DWORD-addressable fields from Capabilities Buffer */
-                    CreateDWordField(Arg3, 4, CDW2)
-                    CreateDWordField(Arg3, 8, CDW3)
-
-                    /* Save Capabilities DWORD2 & 3 */
-                    Store(CDW2, SUPP)
-                    Store(CDW3, CTRL)
-
-				/*
-				 * Always allow native PME, AER (no dependencies)
-				 * Never allow SHPC (no SHPC controller in this system)
-				 */
-                    And(CTRL, 0x1d, CTRL)
-
-                    If (LNotEqual(Arg1, One)) {
-                        /* Unknown revision */
-                        Or(CDW1, 0x08, CDW1)
-                    }
-                    If (LNotEqual(CDW3, CTRL)) {
-                        /* Capabilities bits were masked */
-                        Or(CDW1, 0x10, CDW1)
-                    }
-                    /* Update DWORD3 in the buffer */
-                    Store(CTRL, CDW3)
-                } Else {
-                    Or(CDW1, 4, CDW1) /* Unrecognized UUID */
-                }
-                Return (Arg3)
-            }
-        }
-    }
-
-#include "acpi/pci-crs.asl"
-#include "acpi/hpet.asl"
-
-
-/* VGA */
-
-    Scope(\_SB.PCI0) {
-        Device(VGA) {
-            Name(_ADR, 0x00010000)
-            Method(_S1D, 0, NotSerialized) {
-                Return (0x00)
-            }
-            Method(_S2D, 0, NotSerialized) {
-                Return (0x00)
-            }
-            Method(_S3D, 0, NotSerialized) {
-                Return (0x00)
-            }
-        }
-    }
-
-
-/* LPC ISA bridge */
-
-    Scope(\_SB.PCI0) {
-        /* PCI D31:f0 LPC ISA bridge */
-        Device(ISA) {
-            /* PCI D31:f0 */
-            Name(_ADR, 0x001f0000)
-
-            /* ICH9 PCI to ISA irq remapping */
-            OperationRegion(PIRQ, PCI_Config, 0x60, 0x0c)
-
-            OperationRegion(LPCD, PCI_Config, 0x80, 0x2)
-            Field(LPCD, AnyAcc, NoLock, Preserve) {
-                COMA,   3,
-                    ,   1,
-                COMB,   3,
-
-                Offset(0x01),
-                LPTD,   2,
-                    ,   2,
-                FDCD,   2
-            }
-            OperationRegion(LPCE, PCI_Config, 0x82, 0x2)
-            Field(LPCE, AnyAcc, NoLock, Preserve) {
-                CAEN,   1,
-                CBEN,   1,
-                LPEN,   1,
-                FDEN,   1
-            }
-        }
-    }
-
-#include "acpi/isa.asl"
-
-
-/* PCI IRQs */
-
-    /* Zero => PIC mode, One => APIC Mode */
-    Name(\PICF, Zero)
-    Method(\_PIC, 1, NotSerialized) {
-        Store(Arg0, \PICF)
-    }
-
-    Scope(\_SB) {
-        Scope(PCI0) {
-#define prt_slot_lnk(nr, lnk0, lnk1, lnk2, lnk3)  \
-    Package() { nr##ffff, 0, lnk0, 0 },           \
-    Package() { nr##ffff, 1, lnk1, 0 },           \
-    Package() { nr##ffff, 2, lnk2, 0 },           \
-    Package() { nr##ffff, 3, lnk3, 0 }
-
-#define prt_slot_lnkA(nr) prt_slot_lnk(nr, LNKA, LNKB, LNKC, LNKD)
-#define prt_slot_lnkB(nr) prt_slot_lnk(nr, LNKB, LNKC, LNKD, LNKA)
-#define prt_slot_lnkC(nr) prt_slot_lnk(nr, LNKC, LNKD, LNKA, LNKB)
-#define prt_slot_lnkD(nr) prt_slot_lnk(nr, LNKD, LNKA, LNKB, LNKC)
-
-#define prt_slot_lnkE(nr) prt_slot_lnk(nr, LNKE, LNKF, LNKG, LNKH)
-#define prt_slot_lnkF(nr) prt_slot_lnk(nr, LNKF, LNKG, LNKH, LNKE)
-#define prt_slot_lnkG(nr) prt_slot_lnk(nr, LNKG, LNKH, LNKE, LNKF)
-#define prt_slot_lnkH(nr) prt_slot_lnk(nr, LNKH, LNKE, LNKF, LNKG)
-
-            Name(PRTP, Package() {
-                prt_slot_lnkE(0x0000),
-                prt_slot_lnkF(0x0001),
-                prt_slot_lnkG(0x0002),
-                prt_slot_lnkH(0x0003),
-                prt_slot_lnkE(0x0004),
-                prt_slot_lnkF(0x0005),
-                prt_slot_lnkG(0x0006),
-                prt_slot_lnkH(0x0007),
-                prt_slot_lnkE(0x0008),
-                prt_slot_lnkF(0x0009),
-                prt_slot_lnkG(0x000a),
-                prt_slot_lnkH(0x000b),
-                prt_slot_lnkE(0x000c),
-                prt_slot_lnkF(0x000d),
-                prt_slot_lnkG(0x000e),
-                prt_slot_lnkH(0x000f),
-                prt_slot_lnkE(0x0010),
-                prt_slot_lnkF(0x0011),
-                prt_slot_lnkG(0x0012),
-                prt_slot_lnkH(0x0013),
-                prt_slot_lnkE(0x0014),
-                prt_slot_lnkF(0x0015),
-                prt_slot_lnkG(0x0016),
-                prt_slot_lnkH(0x0017),
-                prt_slot_lnkE(0x0018),
-
-                /* INTA -> PIRQA for slot 25 - 31
-                   see the default value of D<N>IR */
-                prt_slot_lnkA(0x0019),
-                prt_slot_lnkA(0x001a),
-                prt_slot_lnkA(0x001b),
-                prt_slot_lnkA(0x001c),
-                prt_slot_lnkA(0x001d),
-
-                /* PCIe->PCI bridge. use PIRQ[E-H] */
-                prt_slot_lnkE(0x001e),
-
-                prt_slot_lnkA(0x001f)
-            })
-
-#define prt_slot_gsi(nr, gsi0, gsi1, gsi2, gsi3)  \
-    Package() { nr##ffff, 0, gsi0, 0 },           \
-    Package() { nr##ffff, 1, gsi1, 0 },           \
-    Package() { nr##ffff, 2, gsi2, 0 },           \
-    Package() { nr##ffff, 3, gsi3, 0 }
-
-#define prt_slot_gsiA(nr) prt_slot_gsi(nr, GSIA, GSIB, GSIC, GSID)
-#define prt_slot_gsiB(nr) prt_slot_gsi(nr, GSIB, GSIC, GSID, GSIA)
-#define prt_slot_gsiC(nr) prt_slot_gsi(nr, GSIC, GSID, GSIA, GSIB)
-#define prt_slot_gsiD(nr) prt_slot_gsi(nr, GSID, GSIA, GSIB, GSIC)
-
-#define prt_slot_gsiE(nr) prt_slot_gsi(nr, GSIE, GSIF, GSIG, GSIH)
-#define prt_slot_gsiF(nr) prt_slot_gsi(nr, GSIF, GSIG, GSIH, GSIE)
-#define prt_slot_gsiG(nr) prt_slot_gsi(nr, GSIG, GSIH, GSIE, GSIF)
-#define prt_slot_gsiH(nr) prt_slot_gsi(nr, GSIH, GSIE, GSIF, GSIG)
-
-            Name(PRTA, Package() {
-                prt_slot_gsiE(0x0000),
-                prt_slot_gsiF(0x0001),
-                prt_slot_gsiG(0x0002),
-                prt_slot_gsiH(0x0003),
-                prt_slot_gsiE(0x0004),
-                prt_slot_gsiF(0x0005),
-                prt_slot_gsiG(0x0006),
-                prt_slot_gsiH(0x0007),
-                prt_slot_gsiE(0x0008),
-                prt_slot_gsiF(0x0009),
-                prt_slot_gsiG(0x000a),
-                prt_slot_gsiH(0x000b),
-                prt_slot_gsiE(0x000c),
-                prt_slot_gsiF(0x000d),
-                prt_slot_gsiG(0x000e),
-                prt_slot_gsiH(0x000f),
-                prt_slot_gsiE(0x0010),
-                prt_slot_gsiF(0x0011),
-                prt_slot_gsiG(0x0012),
-                prt_slot_gsiH(0x0013),
-                prt_slot_gsiE(0x0014),
-                prt_slot_gsiF(0x0015),
-                prt_slot_gsiG(0x0016),
-                prt_slot_gsiH(0x0017),
-                prt_slot_gsiE(0x0018),
-
-			/*
-			 * INTA -> PIRQA for slot 25 - 31, but 30
-			 * see the default value of D<N>IR
-			 */
-                prt_slot_gsiA(0x0019),
-                prt_slot_gsiA(0x001a),
-                prt_slot_gsiA(0x001b),
-                prt_slot_gsiA(0x001c),
-                prt_slot_gsiA(0x001d),
-
-                /* PCIe->PCI bridge. use PIRQ[E-H] */
-                prt_slot_gsiE(0x001e),
-
-                prt_slot_gsiA(0x001f)
-            })
-
-            Method(_PRT, 0, NotSerialized) {
-			  /*
-			   * PCI IRQ routing table,
-			   * example from ACPI 2.0a
-			   * specification, section 6.2.8.1
-			   * Note: we provide the same info
-			   * as the PCI routing table
-			   * of the Bochs BIOS
-			   */
-                If (LEqual(\PICF, Zero)) {
-                    Return (PRTP)
-                } Else {
-                    Return (PRTA)
-                }
-            }
-        }
-
-        Field(PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve) {
-            PRQA,   8,
-            PRQB,   8,
-            PRQC,   8,
-            PRQD,   8,
-
-            Offset(0x08),
-            PRQE,   8,
-            PRQF,   8,
-            PRQG,   8,
-            PRQH,   8
-        }
-
-        Method(IQST, 1, NotSerialized) {
-            /* _STA method - get status */
-            If (And(0x80, Arg0)) {
-                Return (0x09)
-            }
-            Return (0x0b)
-        }
-        Method(IQCR, 1, NotSerialized) {
-            /* _CRS method - get current settings */
-            Name(PRR0, ResourceTemplate() {
-                Interrupt(, Level, ActiveHigh, Shared) { 0 }
-            })
-            CreateDWordField(PRR0, 0x05, PRRI)
-            Store(And(Arg0, 0x0f), PRRI)
-            Return (PRR0)
-        }
-
-#define define_link(link, uid, reg)                             \
-        Device(link) {                                          \
-            Name(_HID, EISAID("PNP0C0F"))                       \
-            Name(_UID, uid)                                     \
-            Name(_PRS, ResourceTemplate() {                     \
-                Interrupt(, Level, ActiveHigh, Shared) {        \
-                    5, 10, 11                                   \
-                }                                               \
-            })                                                  \
-            Method(_STA, 0, NotSerialized) {                    \
-                Return (IQST(reg))                              \
-            }                                                   \
-            Method(_DIS, 0, NotSerialized) {                    \
-                Or(reg, 0x80, reg)                              \
-            }                                                   \
-            Method(_CRS, 0, NotSerialized) {                    \
-                Return (IQCR(reg))                              \
-            }                                                   \
-            Method(_SRS, 1, NotSerialized) {                    \
-                CreateDWordField(Arg0, 0x05, PRRI)              \
-                Store(PRRI, reg)                                \
-            }                                                   \
-        }
-
-        define_link(LNKA, 0, PRQA)
-        define_link(LNKB, 1, PRQB)
-        define_link(LNKC, 2, PRQC)
-        define_link(LNKD, 3, PRQD)
-        define_link(LNKE, 4, PRQE)
-        define_link(LNKF, 5, PRQF)
-        define_link(LNKG, 6, PRQG)
-        define_link(LNKH, 7, PRQH)
-
-#define define_gsi_link(link, uid, gsi)                         \
-        Device(link) {                                          \
-            Name(_HID, EISAID("PNP0C0F"))                       \
-            Name(_UID, uid)                                     \
-            Name(_PRS, ResourceTemplate() {                     \
-                Interrupt(, Level, ActiveHigh, Shared) {        \
-                    gsi                                         \
-                }                                               \
-            })                                                  \
-            Name(_CRS, ResourceTemplate() {                     \
-                Interrupt(, Level, ActiveHigh, Shared) {        \
-                    gsi                                         \
-                }                                               \
-            })                                                  \
-            Method(_SRS, 1, NotSerialized) {                    \
-            }                                                   \
-        }
-
-        define_gsi_link(GSIA, 0, 0x10)
-        define_gsi_link(GSIB, 0, 0x11)
-        define_gsi_link(GSIC, 0, 0x12)
-        define_gsi_link(GSID, 0, 0x13)
-        define_gsi_link(GSIE, 0, 0x14)
-        define_gsi_link(GSIF, 0, 0x15)
-        define_gsi_link(GSIG, 0, 0x16)
-        define_gsi_link(GSIH, 0, 0x17)
-    }
-
-/* General purpose events */
-
-    Scope(\_GPE) {
-        Name(_HID, "ACPI0006")
-
-        Method(_L00) {
-        }
-        Method(_L01) {
-        }
-        Method(_L02) {
-        }
-        Method(_L03) {
-        }
-        Method(_L04) {
-        }
-        Method(_L05) {
-        }
-        Method(_L06) {
-        }
-        Method(_L07) {
-        }
-        Method(_L08) {
-        }
-        Method(_L09) {
-        }
-        Method(_L0A) {
-        }
-        Method(_L0B) {
-        }
-        Method(_L0C) {
-        }
-        Method(_L0D) {
-        }
-        Method(_L0E) {
-        }
-        Method(_L0F) {
-        }
-    }
-}

arch/x86/cpu/qemu/fw_cfg.c

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2015 Miao Yan <yanmiaoebst@gmail.com>
+ * (C) Copyright 2015 Miao Yan <yanmiaobest@gmail.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */