Prepare v2016.11

Signed-off-by: Tom Rini <trini@konsulko.com>

.travis.yml

@@ -78,6 +78,7 @@ script:
      tools/buildman/buildman -P ${BUILDMAN};
      ret=$?;
      if [[ $ret -ne 0 && $ret -ne 129 ]]; then
+       tools/buildman/buildman -sdeP ${BUILDMAN};
        exit $ret;
      fi;
    fi
@@ -96,30 +97,53 @@ matrix:
   # we need to build by vendor due to 50min time limit for builds
   # each env setting here is a dedicated build
     - env:
-        - BUILDMAN="arm1136"
+        - BUILDMAN="arm11"
     - env:
-        - BUILDMAN="arm1176"
-    - env:
-        - BUILDMAN="arm720t"
+        - BUILDMAN="arm7"
     - env:
         - BUILDMAN="arm920t"
+    - env:
+        - JOB="arm926ejs"
+          BUILDMAN="arm926ejs -x mx,siemens,atmel"
+    - env:
+        - BUILDMAN="arm946es"
     - env:
         - BUILDMAN="atmel -x avr32"
     - env:
         - BUILDMAN="avr32"
           TOOLCHAIN="avr32"
-    - env:
-        - BUILDMAN="davinci"
     - env:
         - BUILDMAN="denx"
     - env:
         - JOB="Freescale ARM"
           BUILDMAN="freescale -x powerpc,m68k"
+    - env:
+        - JOB="i.MX (non-Freescale)"
+          BUILDMAN="mx -x freescale"
+    - env:
+        - BUILDMAN="sun4i"
+    - env:
+        - BUILDMAN="sun5i"
+    - env:
+        - BUILDMAN="sun6i"
+    - env:
+        - BUILDMAN="sun7i"
+    - env:
+        - BUILDMAN="sun8i"
+    - env:
+        - BUILDMAN="sun9i"
+    - env:
+        - BUILDMAN="sun50i"
+    - env:
+        - JOB="Catch-all ARM"
+          BUILDMAN="arm -x arm11,arm7,arm9,aarch64,atmel,denx,freescale,kirkwood,siemens,tegra,uniphier,mx,sunxi,am33xx,omap3,omap4,omap5,pxa"
     - env:
         - BUILDMAN="sandbox x86"
           TOOLCHAIN="x86_64"
     - env:
         - BUILDMAN="kirkwood"
+    - env:
+        - BUILDMAN="pxa"
     - env:
         - BUILDMAN="m68k"
           TOOLCHAIN="m68k"
@@ -158,11 +182,18 @@ matrix:
     - env:
         - BUILDMAN="tegra"
     - env:
-        - BUILDMAN="ti"
+        - JOB="am33xx"
+          BUILDMAN="am33xx -x siemens"
+    - env:
+        - BUILDMAN="omap3"
+    - env:
+        - BUILDMAN="omap4"
+    - env:
+        - BUILDMAN="omap5"
     - env:
         - BUILDMAN="uniphier"
     - env:
-        - BUILDMAN="aarch64 -x tegra,freescale,uniphier"
+        - BUILDMAN="aarch64 -x tegra,freescale,uniphier,sunxi"
           TOOLCHAIN="aarch64"
     - env:
         - BUILDMAN="sh4"

MAINTAINERS

@@ -167,9 +167,7 @@ F:	arch/arm/cpu/armv7/stv0991/
 F:	arch/arm/include/asm/arch-stv0991/
 
 ARM SUNXI
-M:	Ian Campbell <ijc@hellion.org.uk>
-M:	Hans De Goede <hdegoede@redhat.com>
-S:	Maintained
+S:	Orphan
 T:	git git://git.denx.de/u-boot-sunxi.git
 F:	arch/arm/cpu/armv7/sunxi/
 F:	arch/arm/include/asm/arch-sunxi/

Makefile

@@ -5,7 +5,7 @@
 VERSION = 2016
 PATCHLEVEL = 11
 SUBLEVEL =
-EXTRAVERSION = -rc3
+EXTRAVERSION =
 NAME =
 
 # *DOCUMENTATION*

arch/arm/cpu/armv8/cache.S

@@ -150,11 +150,23 @@ ENTRY(__asm_invalidate_icache_all)
 	ret
 ENDPROC(__asm_invalidate_icache_all)
 
-ENTRY(__asm_flush_l3_cache)
+ENTRY(__asm_invalidate_l3_dcache)
 	mov	x0, #0			/* return status as success */
 	ret
-ENDPROC(__asm_flush_l3_cache)
-	.weak	__asm_flush_l3_cache
+ENDPROC(__asm_invalidate_l3_dcache)
+	.weak	__asm_invalidate_l3_dcache
+
+ENTRY(__asm_flush_l3_dcache)
+	mov	x0, #0			/* return status as success */
+	ret
+ENDPROC(__asm_flush_l3_dcache)
+	.weak	__asm_flush_l3_dcache
+
+ENTRY(__asm_invalidate_l3_icache)
+	mov	x0, #0			/* return status as success */
+	ret
+ENDPROC(__asm_invalidate_l3_icache)
+	.weak	__asm_invalidate_l3_icache
 
 /*
  * void __asm_switch_ttbr(ulong new_ttbr)

arch/arm/cpu/armv8/cache_v8.c

@@ -421,19 +421,20 @@ __weak void mmu_setup(void)
 void invalidate_dcache_all(void)
 {
 	__asm_invalidate_dcache_all();
+	__asm_invalidate_l3_dcache();
 }
 
 /*
  * Performs a clean & invalidation of the entire data cache at all levels.
  * This function needs to be inline to avoid using stack.
- * __asm_flush_l3_cache return status of timeout
+ * __asm_flush_l3_dcache return status of timeout
  */
 inline void flush_dcache_all(void)
 {
 	int ret;
 
 	__asm_flush_dcache_all();
-	ret = __asm_flush_l3_cache();
+	ret = __asm_flush_l3_dcache();
 	if (ret)
 		debug("flushing dcache returns 0x%x\n", ret);
 	else
@@ -623,7 +624,7 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
 
 void icache_enable(void)
 {
-	__asm_invalidate_icache_all();
+	invalidate_icache_all();
 	set_sctlr(get_sctlr() | CR_I);
 }
 
@@ -640,6 +641,7 @@ int icache_status(void)
 void invalidate_icache_all(void)
 {
 	__asm_invalidate_icache_all();
+	__asm_invalidate_l3_icache();
 }
 
 #else	/* CONFIG_SYS_ICACHE_OFF */

arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S

@@ -245,7 +245,7 @@ hnf_set_pstate:
 
 	ret
 
-ENTRY(__asm_flush_l3_cache)
+ENTRY(__asm_flush_l3_dcache)
 	/*
 	 * Return status in x0
 	 *    success 0
@@ -275,7 +275,7 @@ ENTRY(__asm_flush_l3_cache)
 	mov	x0, x8
 	mov	lr, x29
 	ret
-ENDPROC(__asm_flush_l3_cache)
+ENDPROC(__asm_flush_l3_dcache)
 #endif
 
 #ifdef CONFIG_MP

arch/arm/cpu/armv8/generic_timer.c

@@ -9,6 +9,8 @@
 #include <command.h>
 #include <asm/system.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /*
  * Generic timer implementation of get_tbclk()
  */
@@ -41,6 +43,15 @@ unsigned long timer_read_counter(void)
 	return cntpct;
 }
 
+unsigned long long get_ticks(void)
+{
+	unsigned long ticks = timer_read_counter();
+
+	gd->arch.tbl = ticks;
+
+	return ticks;
+}
+
 unsigned long usec2ticks(unsigned long usec)
 {
 	ulong ticks;

arch/arm/dts/dra7-evm.dts

@@ -505,7 +505,7 @@
 	spi-max-frequency = <76800000>;
 	m25p80@0 {
 		compatible = "s25fl256s1","spi-flash";
-		spi-max-frequency = <64000000>;
+		spi-max-frequency = <76800000>;
 		reg = <0>;
 		spi-tx-bus-width = <1>;
 		spi-rx-bus-width = <4>;

arch/arm/dts/dra72-evm-common.dtsi

@@ -441,7 +441,7 @@
 	spi-max-frequency = <76800000>;
 	m25p80@0 {
 		compatible = "s25fl256s1", "spi-flash";
-		spi-max-frequency = <64000000>;
+		spi-max-frequency = <76800000>;
 		reg = <0>;
 		spi-tx-bus-width = <1>;
 		spi-rx-bus-width = <4>;

arch/arm/dts/rk3288-evb.dts

@@ -17,7 +17,6 @@
 };
 
 &dmc {
-	rockchip,num-channels = <2>;
 	rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
 		0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
 		0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0
@@ -25,8 +24,6 @@
 		0x8 0x1f4>;
 	rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
 		0x0 0xc3 0x6 0x2>;
-	/* Add a dummy value to cause of-platdata think this is bytes */
-	rockchip,sdram-channel = /bits/ 8 <0x2 0xa 0x3 0x2 0x2 0x0 0xe 0xe 0xff>;
 	rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 0>;
 };
 

arch/arm/dts/rk3288-fennec.dts

@@ -17,7 +17,6 @@
 };
 
 &dmc {
-	rockchip,num-channels = <2>;
 	rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
 		0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
 		0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0
@@ -25,8 +24,6 @@
 		0x8 0x1f4>;
 	rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
 		0x0 0xc3 0x6 0x2>;
-	/* Add a dummy value to cause of-platdata think this is bytes */
-	rockchip,sdram-channel = /bits/ 8 <0x2 0xa 0x3 0x2 0x2 0x0 0xe 0xe 0xff>;
 	rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 0>;
 };
 

arch/arm/dts/rk3288-firefly.dts

@@ -22,7 +22,6 @@
 };
 
 &dmc {
-	rockchip,num-channels = <2>;
 	rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
 		0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
 		0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
@@ -31,7 +30,6 @@
 	rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
 		0xa60 0x40 0x10 0x0>;
 	/* Add a dummy value to cause of-platdata think this is bytes */
-	rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf 0xff>;
 	rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
 };
 

arch/arm/dts/rk3288-miniarm.dts

@@ -17,7 +17,6 @@
 };
 
 &dmc {
-	rockchip,num-channels = <2>;
 	rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
 		0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
 		0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
@@ -25,8 +24,6 @@
 		0x5 0x0>;
 	rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
 		0xa60 0x40 0x10 0x0>;
-	/* Add a dummy value to cause of-platdata think this is bytes */
-	rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf 0xff>;
 	rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
 };
 

arch/arm/dts/rk3288-popmetal.dts

@@ -17,7 +17,6 @@
 };
 
 &dmc {
-	rockchip,num-channels = <2>;
 	rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
 		0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
 		0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
@@ -25,8 +24,6 @@
 		0x5 0x0>;
 	rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
 		0xa60 0x40 0x10 0x0>;
-	/* Add a dummy value to cause of-platdata think this is bytes */
-	rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf 0xff>;
 	rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
 };
 

arch/arm/dts/rk3288-rock2-square.dts

@@ -184,7 +184,6 @@
 };
 
 &dmc {
-	rockchip,num-channels = <2>;
 	rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
 		0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
 		0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
@@ -192,7 +191,6 @@
 		0x5 0x0>;
 	rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
 		0xa60 0x40 0x10 0x0>;
-	rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf 0xff>;
 	rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
 };
 

arch/arm/dts/rk3288-veyron.dtsi

@@ -245,7 +245,6 @@
 		533000 1150000
 		666000 1200000
 	>;
-	rockchip,num-channels = <2>;
 	rockchip,pctl-timing = <0x29a 0xc8 0x1f4 0x42 0x4e 0x4 0xea 0xa
 		0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
 		0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
@@ -253,7 +252,6 @@
 		0x5 0x0>;
 	rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
 		0xa60 0x40 0x10 0x0>;
-	rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf 0xff>;
 	rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
 };
 

arch/arm/dts/tegra186-p2771-0000.dtsi

@@ -25,6 +25,11 @@
 		reg = <0x0 0x80000000 0x0 0x60000000>;
 	};
 
+	ethernet@2490000 {
+		status = "okay";
+		phy-reset-gpios = <&gpio_main TEGRA_MAIN_GPIO(M, 4) GPIO_ACTIVE_LOW>;
+	};
+
 	i2c@3160000 {
 		status = "okay";
 	};

arch/arm/dts/tegra186.dtsi

@@ -31,6 +31,26 @@
 		#interrupt-cells = <2>;
 	};
 
+	ethernet@2490000 {
+		compatible = "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10";
+		reg = <0x0 0x02490000 0x0 0x10000>;
+		interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&bpmp TEGRA186_CLK_AXI_CBB>,
+			<&bpmp TEGRA186_CLK_EQOS_AXI>,
+			<&bpmp TEGRA186_CLK_EQOS_RX>,
+			<&bpmp TEGRA186_CLK_EQOS_PTP_REF>,
+			<&bpmp TEGRA186_CLK_EQOS_TX>;
+		clock-names = "slave_bus",
+			"master_bus",
+			"rx",
+			"ptp_ref",
+			"tx";
+		resets = <&bpmp TEGRA186_RESET_EQOS>;
+		reset-names = "eqos";
+		phy-mode = "rgmii";
+		status = "disabled";
+	};
+
 	uarta: serial@3100000 {
 		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
 		reg = <0x0 0x03100000 0x0 0x10000>;

arch/arm/include/asm/arch-rockchip/cru_rk3036.h

@@ -24,6 +24,12 @@
 #define PERI_HCLK_HZ	148500000
 #define PERI_PCLK_HZ	74250000
 
+/* Private data for the clock driver - used by rockchip_get_cru() */
+struct rk3036_clk_priv {
+	struct rk3036_cru *cru;
+	ulong rate;
+};
+
 struct rk3036_cru {
 	struct rk3036_pll {
 		unsigned int con0;

arch/arm/include/asm/arch-rockchip/cru_rk3288.h

@@ -25,6 +25,13 @@
 #define PERI_HCLK_HZ	148500000
 #define PERI_PCLK_HZ	74250000
 
+/* Private data for the clock driver - used by rockchip_get_cru() */
+struct rk3288_clk_priv {
+	struct rk3288_grf *grf;
+	struct rk3288_cru *cru;
+	ulong rate;
+};
+
 struct rk3288_cru {
 	struct rk3288_pll {
 		u32 con0;

arch/arm/include/asm/arch-rockchip/cru_rk3399.h

@@ -9,6 +9,12 @@
 
 #include <common.h>
 
+/* Private data for the clock driver - used by rockchip_get_cru() */
+struct rk3399_clk_priv {
+	struct rk3399_cru *cru;
+	ulong rate;
+};
+
 struct rk3399_pmucru {
 	u32 ppll_con[6];
 	u32 reserved[0x1a];

arch/arm/include/asm/arch-rockchip/sdram.h

@@ -16,6 +16,11 @@ enum {
 };
 
 struct rk3288_sdram_channel {
+	/*
+	 * bit width in address, eg:
+	 * 8 banks using 3 bit to address,
+	 * 2 cs using 1 bit to address.
+	 */
 	u8 rank;
 	u8 col;
 	u8 bk;
@@ -87,6 +92,16 @@ struct rk3288_base_params {
 	u32 ddrconfig;
 	u32 ddr_freq;
 	u32 dramtype;
+	/*
+	 * DDR Stride is address mapping for DRAM space
+	 * Stride	Ch 0 range	Ch1 range	Total
+	 * 0x00		0-256MB		256MB-512MB	512MB
+	 * 0x05		0-1GB		0-1GB		1GB
+	 * 0x09		0-2GB		0-2GB		2GB
+	 * 0x0d		0-4GB		0-4GB		4GB
+	 * 0x17		N/A		0-4GB		4GB
+	 * 0x1a		0-4GB		4GB-8GB		8GB
+	 */
 	u32 stride;
 	u32 odt;
 };

arch/arm/include/asm/system.h

@@ -93,7 +93,9 @@ void __asm_invalidate_dcache_all(void);
 void __asm_flush_dcache_range(u64 start, u64 end);
 void __asm_invalidate_tlb_all(void);
 void __asm_invalidate_icache_all(void);
-int __asm_flush_l3_cache(void);
+int __asm_invalidate_l3_dcache(void);
+int __asm_flush_l3_dcache(void);
+int __asm_invalidate_l3_icache(void);
 void __asm_switch_ttbr(u64 new_ttbr);
 
 void armv8_switch_to_el2(void);
@@ -329,7 +331,7 @@ static inline void set_dacr(unsigned int val)
 
 /* options available for data cache on each page */
 enum dcache_option {
-	DCACHE_OFF = TTB_SECT | TTB_SECT_MAIR(0),
+	DCACHE_OFF = TTB_SECT | TTB_SECT_MAIR(0) | TTB_SECT_XN_MASK,
 	DCACHE_WRITETHROUGH = TTB_SECT | TTB_SECT_MAIR(1),
 	DCACHE_WRITEBACK = TTB_SECT | TTB_SECT_MAIR(2),
 	DCACHE_WRITEALLOC = TTB_SECT | TTB_SECT_MAIR(3),

arch/arm/lib/cache-cp15.c

@@ -71,8 +71,13 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
 
 	end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
 	start = start >> MMU_SECTION_SHIFT;
-	debug("%s: start=%pa, size=%zu, option=%d\n", __func__, &start, size,
+#ifdef CONFIG_ARMV7_LPAE
+	debug("%s: start=%pa, size=%zu, option=%llx\n", __func__, &start, size,
 	      option);
+#else
+	debug("%s: start=%pa, size=%zu, option=0x%x\n", __func__, &start, size,
+	      option);
+#endif
 	for (upto = start; upto < end; upto++)
 		set_section_dcache(upto, option);
 

arch/arm/mach-keystone/clock.c

@@ -163,15 +163,15 @@ void configure_secondary_pll(const struct pll_init_data *data)
 {
 	int pllod = data->pll_od - 1;
 
+	/* Enable Glitch free bypass for ARM PLL */
+	if (cpu_is_k2hk() && data->pll == TETRIS_PLL)
+		clrbits_le32(KS2_MISC_CTRL, MISC_CTL1_ARM_PLL_EN);
+
 	/* Enable Bypass mode */
 	setbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_ENSAT_MASK);
 	setbits_le32(keystone_pll_regs[data->pll].reg0,
 		     CFG_PLLCTL0_BYPASS_MASK);
 
-	/* Enable Glitch free bypass for ARM PLL */
-	if (cpu_is_k2hk() && data->pll == TETRIS_PLL)
-		clrbits_le32(KS2_MISC_CTRL, MISC_CTL1_ARM_PLL_EN);
-
 	configure_mult_div(data);
 
 	/* Program Output Divider */
@@ -189,10 +189,6 @@ void configure_secondary_pll(const struct pll_init_data *data)
 	if (data->pll == PASS_PLL && cpu_is_k2hk())
 		pll_pa_clk_sel();
 
-	/* Select the Output of ARM PLL as input to ARM */
-	if (data->pll == TETRIS_PLL)
-		setbits_le32(KS2_MISC_CTRL, MISC_CTL1_ARM_PLL_EN);
-
 	clrbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_RST_MASK);
 	/* Wait for 500 * REFCLK cucles * (PLLD + 1) */
 	sdelay(105000);
@@ -200,6 +196,10 @@ void configure_secondary_pll(const struct pll_init_data *data)
 	/* Switch to PLL mode */
 	clrbits_le32(keystone_pll_regs[data->pll].reg0,
 		     CFG_PLLCTL0_BYPASS_MASK);
+
+	/* Select the Output of ARM PLL as input to ARM */
+	if (cpu_is_k2hk() && data->pll == TETRIS_PLL)
+		setbits_le32(KS2_MISC_CTRL, MISC_CTL1_ARM_PLL_EN);
 }
 
 void init_pll(const struct pll_init_data *data)

arch/arm/mach-rockchip/rk3036/Makefile

@@ -4,6 +4,8 @@
 # SPDX-License-Identifier:     GPL-2.0+
 #
 
+obj-y += clk_rk3036.o
+
 ifndef CONFIG_SPL_BUILD
 obj-y += syscon_rk3036.o
 endif

arch/arm/mach-rockchip/rk3036/clk_rk3036.c

@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2016 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk3036.h>
+
+int rockchip_get_clk(struct udevice **devp)
+{
+	return uclass_get_device_by_driver(UCLASS_CLK,
+			DM_GET_DRIVER(rockchip_rk3036_cru), devp);
+}
+
+void *rockchip_get_cru(void)
+{
+	struct rk3036_clk_priv *priv;
+	struct udevice *dev;
+	int ret;
+
+	ret = rockchip_get_clk(&dev);
+	if (ret)
+		return ERR_PTR(ret);
+
+	priv = dev_get_priv(dev);
+
+	return priv->cru;
+}

arch/arm/mach-rockchip/rk3288/Kconfig

@@ -81,9 +81,6 @@ config SPL_LIBCOMMON_SUPPORT
 config SPL_LIBGENERIC_SUPPORT
 	default y
 
-config SPL_MMC_SUPPORT
-	default y
-
 config SPL_SERIAL_SUPPORT
 	default y
 

arch/arm/mach-rockchip/rk3288/clk_rk3288.c

@@ -9,9 +9,25 @@
 #include <dm.h>
 #include <syscon.h>
 #include <asm/arch/clock.h>
+#include <asm/arch/cru_rk3288.h>
 
 int rockchip_get_clk(struct udevice **devp)
 {
 	return uclass_get_device_by_driver(UCLASS_CLK,
 			DM_GET_DRIVER(rockchip_rk3288_cru), devp);
 }
+
+void *rockchip_get_cru(void)
+{
+	struct rk3288_clk_priv *priv;
+	struct udevice *dev;
+	int ret;
+
+	ret = rockchip_get_clk(&dev);
+	if (ret)
+		return ERR_PTR(ret);
+
+	priv = dev_get_priv(dev);
+
+	return priv->cru;
+}

arch/arm/mach-rockchip/rk3288/rk3288.c

@@ -6,7 +6,7 @@
 #include <asm/io.h>
 #include <asm/arch/hardware.h>
 
-#define GRF_SOC_CON2 0x24c
+#define GRF_SOC_CON2 0xff77024c
 
 int arch_cpu_init(void)
 {

arch/arm/mach-rockchip/rk3288/sdram_rk3288.c

@@ -57,6 +57,10 @@ struct rk3288_sdram_params {
 	struct regmap *map;
 };
 
+#define TEST_PATTEN	0x5aa5f00f
+#define DQS_GATE_TRAINING_ERROR_RANK0	(1 << 4)
+#define DQS_GATE_TRAINING_ERROR_RANK1	(2 << 4)
+
 #ifdef CONFIG_SPL_BUILD
 static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
 {
@@ -214,7 +218,7 @@ static void ddr_set_en_bst_odt(struct rk3288_grf *grf, uint channel,
 }
 
 static void pctl_cfg(u32 channel, struct rk3288_ddr_pctl *pctl,
-		     const struct rk3288_sdram_params *sdram_params,
+		     struct rk3288_sdram_params *sdram_params,
 		     struct rk3288_grf *grf)
 {
 	unsigned int burstlen;
@@ -264,7 +268,7 @@ static void pctl_cfg(u32 channel, struct rk3288_ddr_pctl *pctl,
 }
 
 static void phy_cfg(const struct chan_info *chan, u32 channel,
-		    const struct rk3288_sdram_params *sdram_params)
+		    struct rk3288_sdram_params *sdram_params)
 {
 	struct rk3288_ddr_publ *publ = chan->publ;
 	struct rk3288_msch *msch = chan->msch;
@@ -446,7 +450,7 @@ static void set_bandwidth_ratio(const struct chan_info *chan, u32 channel,
 }
 
 static int data_training(const struct chan_info *chan, u32 channel,
-			 const struct rk3288_sdram_params *sdram_params)
+			 struct rk3288_sdram_params *sdram_params)
 {
 	unsigned int j;
 	int ret = 0;
@@ -549,7 +553,7 @@ static void move_to_access_state(const struct chan_info *chan)
 }
 
 static void dram_cfg_rbc(const struct chan_info *chan, u32 chnum,
-			 const struct rk3288_sdram_params *sdram_params)
+			 struct rk3288_sdram_params *sdram_params)
 {
 	struct rk3288_ddr_publ *publ = chan->publ;
 
@@ -563,7 +567,7 @@ static void dram_cfg_rbc(const struct chan_info *chan, u32 chnum,
 }
 
 static void dram_all_config(const struct dram_info *dram,
-			    const struct rk3288_sdram_params *sdram_params)
+			    struct rk3288_sdram_params *sdram_params)
 {
 	unsigned int chan;
 	u32 sys_reg = 0;
@@ -589,9 +593,191 @@ static void dram_all_config(const struct dram_info *dram,
 	writel(sys_reg, &dram->pmu->sys_reg[2]);
 	rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, sdram_params->base.stride);
 }
+const int ddrconf_table[] = {
+	/* row	    col,bw */
+	0,
+	((1 << 4) | 1),
+	((2 << 4) | 1),
+	((3 << 4) | 1),
+	((4 << 4) | 1),
+	((1 << 4) | 2),
+	((2 << 4) | 2),
+	((3 << 4) | 2),
+	((1 << 4) | 0),
+	((2 << 4) | 0),
+	((3 << 4) | 0),
+	0,
+	0,
+	0,
+	0,
+	((4 << 4) | 2),
+};
+
+static int sdram_rank_bw_detect(struct dram_info *dram, int channel,
+		struct rk3288_sdram_params *sdram_params)
+{
+	int reg;
+	int need_trainig = 0;
+	const struct chan_info *chan = &dram->chan[channel];
+	struct rk3288_ddr_publ *publ = chan->publ;
+
+	if (-1 == data_training(chan, channel, sdram_params)) {
+		reg = readl(&publ->datx8[0].dxgsr[0]);
+		/* Check the result for rank 0 */
+		if ((channel == 0) && (reg & DQS_GATE_TRAINING_ERROR_RANK0)) {
+			debug("data training fail!\n");
+				return -EIO;
+		} else if ((channel == 1) &&
+			   (reg & DQS_GATE_TRAINING_ERROR_RANK0)) {
+			sdram_params->num_channels = 1;
+		}
+
+		/* Check the result for rank 1 */
+		if (reg & DQS_GATE_TRAINING_ERROR_RANK1) {
+			sdram_params->ch[channel].rank = 1;
+			clrsetbits_le32(&publ->pgcr, 0xF << 18,
+					sdram_params->ch[channel].rank << 18);
+			need_trainig = 1;
+		}
+		reg = readl(&publ->datx8[2].dxgsr[0]);
+		if (reg & (1 << 4)) {
+			sdram_params->ch[channel].bw = 1;
+			set_bandwidth_ratio(chan, channel,
+					    sdram_params->ch[channel].bw,
+					    dram->grf);
+			need_trainig = 1;
+		}
+	}
+	/* Assume the Die bit width are the same with the chip bit width */
+	sdram_params->ch[channel].dbw = sdram_params->ch[channel].bw;
+
+	if (need_trainig &&
+	    (-1 == data_training(chan, channel, sdram_params))) {
+		if (sdram_params->base.dramtype == LPDDR3) {
+			ddr_phy_ctl_reset(dram->cru, channel, 1);
+			udelay(10);
+			ddr_phy_ctl_reset(dram->cru, channel, 0);
+			udelay(10);
+		}
+		debug("2nd data training failed!");
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int sdram_col_row_detect(struct dram_info *dram, int channel,
+		struct rk3288_sdram_params *sdram_params)
+{
+	int row, col;
+	unsigned int addr;
+	const struct chan_info *chan = &dram->chan[channel];
+	struct rk3288_ddr_pctl *pctl = chan->pctl;
+	struct rk3288_ddr_publ *publ = chan->publ;
+	int ret = 0;
+
+	/* Detect col */
+	for (col = 11; col >= 9; col--) {
+		writel(0, CONFIG_SYS_SDRAM_BASE);
+		addr = CONFIG_SYS_SDRAM_BASE +
+			(1 << (col + sdram_params->ch[channel].bw - 1));
+		writel(TEST_PATTEN, addr);
+		if ((readl(addr) == TEST_PATTEN) &&
+		    (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+			break;
+	}
+	if (col == 8) {
+		printf("Col detect error\n");
+		ret = -EINVAL;
+		goto out;
+	} else {
+		sdram_params->ch[channel].col = col;
+	}
+
+	move_to_config_state(publ, pctl);
+	writel(4, &chan->msch->ddrconf);
+	move_to_access_state(chan);
+	/* Detect row*/
+	for (row = 16; row >= 12; row--) {
+		writel(0, CONFIG_SYS_SDRAM_BASE);
+		addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
+		writel(TEST_PATTEN, addr);
+		if ((readl(addr) == TEST_PATTEN) &&
+		    (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+			break;
+	}
+	if (row == 11) {
+		printf("Row detect error\n");
+		ret = -EINVAL;
+	} else {
+		sdram_params->ch[channel].cs1_row = row;
+		sdram_params->ch[channel].row_3_4 = 0;
+		debug("chn %d col %d, row %d\n", channel, col, row);
+		sdram_params->ch[channel].cs0_row = row;
+	}
+
+out:
+	return ret;
+}
+
+static int sdram_get_niu_config(struct rk3288_sdram_params *sdram_params)
+{
+	int i, tmp, size, ret = 0;
+
+	tmp = sdram_params->ch[0].col - 9;
+	tmp -= (sdram_params->ch[0].bw == 2) ? 0 : 1;
+	tmp |= ((sdram_params->ch[0].cs0_row - 12) << 4);
+	size = sizeof(ddrconf_table)/sizeof(ddrconf_table[0]);
+	for (i = 0; i < size; i++)
+		if (tmp == ddrconf_table[i])
+			break;
+	if (i >= size) {
+		printf("niu config not found\n");
+		ret = -EINVAL;
+	} else {
+		sdram_params->base.ddrconfig = i;
+	}
+
+	return ret;
+}
+
+static int sdram_get_stride(struct rk3288_sdram_params *sdram_params)
+{
+	int stride = -1;
+	int ret = 0;
+	long cap = sdram_params->num_channels * (1u <<
+			(sdram_params->ch[0].cs0_row +
+			 sdram_params->ch[0].col +
+			 (sdram_params->ch[0].rank - 1) +
+			 sdram_params->ch[0].bw +
+			 3 - 20));
+
+	switch (cap) {
+	case 512:
+		stride = 0;
+		break;
+	case 1024:
+		stride = 5;
+		break;
+	case 2048:
+		stride = 9;
+		break;
+	case 4096:
+		stride = 0xd;
+		break;
+	default:
+		stride = -1;
+		printf("could not find correct stride, cap error!\n");
+		ret = -EINVAL;
+		break;
+	}
+	sdram_params->base.stride = stride;
+
+	return ret;
+}
 
 static int sdram_init(struct dram_info *dram,
-		      const struct rk3288_sdram_params *sdram_params)
+		      struct rk3288_sdram_params *sdram_params)
 {
 	int channel;
 	int zqcr;
@@ -619,12 +805,14 @@ static int sdram_init(struct dram_info *dram,
 		struct rk3288_ddr_pctl *pctl = chan->pctl;
 		struct rk3288_ddr_publ *publ = chan->publ;
 
+		/* map all the 4GB space to the current channel */
+		if (channel)
+			rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, 0x17);
+		else
+			rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, 0x1a);
 		phy_pctrl_reset(dram->cru, publ, channel);
 		phy_dll_bypass_set(publ, sdram_params->base.ddr_freq);
 
-		if (channel >= sdram_params->num_channels)
-			continue;
-
 		dfi_cfg(pctl, sdram_params->base.dramtype);
 
 		pctl_cfg(channel, pctl, sdram_params, dram->grf);
@@ -658,16 +846,20 @@ static int sdram_init(struct dram_info *dram,
 			udelay(1);
 		}
 
+		/* Using 32bit bus width for detect */
+		sdram_params->ch[channel].bw = 2;
 		set_bandwidth_ratio(chan, channel,
 				    sdram_params->ch[channel].bw, dram->grf);
 		/*
-		 * set cs
+		 * set cs, using n=3 for detect
 		 * CS0, n=1
 		 * CS1, n=2
 		 * CS0 & CS1, n = 3
 		 */
+		sdram_params->ch[channel].rank = 2,
 		clrsetbits_le32(&publ->pgcr, 0xF << 18,
 				(sdram_params->ch[channel].rank | 1) << 18);
+
 		/* DS=40ohm,ODT=155ohm */
 		zqcr = 1 << ZDEN_SHIFT | 2 << PU_ONDIE_SHIFT |
 			2 << PD_ONDIE_SHIFT | 0x19 << PU_OUTPUT_SHIFT |
@@ -693,16 +885,8 @@ static int sdram_init(struct dram_info *dram,
 			}
 		}
 
-		if (-1 == data_training(chan, channel, sdram_params)) {
-			if (sdram_params->base.dramtype == LPDDR3) {
-				ddr_phy_ctl_reset(dram->cru, channel, 1);
-				udelay(10);
-				ddr_phy_ctl_reset(dram->cru, channel, 0);
-				udelay(10);
-			}
-			debug("failed!");
-			return -EIO;
-		}
+		/* Detect the rank and bit-width with data-training */
+		sdram_rank_bw_detect(dram, channel, sdram_params);
 
 		if (sdram_params->base.dramtype == LPDDR3) {
 			u32 i;
@@ -710,12 +894,31 @@ static int sdram_init(struct dram_info *dram,
 			for (i = 0; i < 17; i++)
 				send_command_op(pctl, 1, MRR_CMD, i, 0);
 		}
+		writel(15, &chan->msch->ddrconf);
 		move_to_access_state(chan);
+		/* DDR3 and LPDDR3 are always 8 bank, no need detect */
+		sdram_params->ch[channel].bk = 3;
+		/* Detect Col and Row number*/
+		ret = sdram_col_row_detect(dram, channel, sdram_params);
+		if (ret)
+			goto error;
 	}
+	/* Find NIU DDR configuration */
+	ret = sdram_get_niu_config(sdram_params);
+	if (ret)
+		goto error;
+	/* Find stride setting */
+	ret = sdram_get_stride(sdram_params);
+	if (ret)
+		goto error;
+
 	dram_all_config(dram, sdram_params);
 	debug("%s done\n", __func__);
 
 	return 0;
+error:
+	printf("DRAM init failed!\n");
+	hang();
 }
 #endif /* CONFIG_SPL_BUILD */
 
@@ -743,7 +946,6 @@ size_t sdram_size_mb(struct rk3288_pmu *pmu)
 			SYS_REG_BW_MASK));
 		row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) &
 			SYS_REG_ROW_3_4_MASK;
-
 		chipsize_mb = (1 << (cs0_row + col + bk + bw - 20));
 
 		if (rank > 1)
@@ -815,21 +1017,10 @@ static int rk3288_dmc_ofdata_to_platdata(struct udevice *dev)
 	struct rk3288_sdram_params *params = dev_get_platdata(dev);
 	const void *blob = gd->fdt_blob;
 	int node = dev->of_offset;
-	int i, ret;
+	int ret;
 
-	params->num_channels = fdtdec_get_int(blob, node,
-					      "rockchip,num-channels", 1);
-	for (i = 0; i < params->num_channels; i++) {
-		ret = fdtdec_get_byte_array(blob, node,
-					    "rockchip,sdram-channel",
-					    (u8 *)&params->ch[i],
-					    sizeof(params->ch[i]));
-		if (ret) {
-			debug("%s: Cannot read rockchip,sdram-channel\n",
-			      __func__);
-			return -EINVAL;
-		}
-	}
+	/* Rk3288 supports dual-channel, set default channel num to 2 */
+	params->num_channels = 2;
 	ret = fdtdec_get_int_array(blob, node, "rockchip,pctl-timing",
 				   (u32 *)&params->pctl_timing,
 				   sizeof(params->pctl_timing) / sizeof(u32));
@@ -870,18 +1061,15 @@ static int conv_of_platdata(struct udevice *dev)
 {
 	struct rk3288_sdram_params *plat = dev_get_platdata(dev);
 	struct dtd_rockchip_rk3288_dmc *of_plat = &plat->of_plat;
-	int i, ret;
+	int ret;
 
-	for (i = 0; i < 2; i++) {
-		memcpy(&plat->ch[i], of_plat->rockchip_sdram_channel,
-		       sizeof(plat->ch[i]));
-	}
 	memcpy(&plat->pctl_timing, of_plat->rockchip_pctl_timing,
 	       sizeof(plat->pctl_timing));
 	memcpy(&plat->phy_timing, of_plat->rockchip_phy_timing,
 	       sizeof(plat->phy_timing));
 	memcpy(&plat->base, of_plat->rockchip_sdram_params, sizeof(plat->base));
-	plat->num_channels = of_plat->rockchip_num_channels;
+	/* Rk3288 supports dual-channel, set default channel num to 2 */
+	plat->num_channels = 2;
 	ret = regmap_init_mem_platdata(dev, of_plat->reg,
 				       ARRAY_SIZE(of_plat->reg) / 2,
 				       &plat->map);

arch/arm/mach-rockchip/rk3399/Makefile

@@ -4,5 +4,6 @@
 # SPDX-License-Identifier:     GPL-2.0+
 #
 
+obj-y += clk_rk3399.o
 obj-y += rk3399.o
 obj-y += syscon_rk3399.o

arch/arm/mach-rockchip/rk3399/clk_rk3399.c

@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2016 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk3399.h>
+
+int rockchip_get_clk(struct udevice **devp)
+{
+	return uclass_get_device_by_driver(UCLASS_CLK,
+			DM_GET_DRIVER(rockchip_rk3399_pmuclk), devp);
+}
+
+void *rockchip_get_cru(void)
+{
+	struct rk3399_clk_priv *priv;
+	struct udevice *dev;
+	int ret;
+
+	ret = rockchip_get_clk(&dev);
+	if (ret)
+		return ERR_PTR(ret);
+
+	priv = dev_get_priv(dev);
+
+	return priv->cru;
+}

arch/arm/mach-rockchip/rk3399/rk3399.c

@@ -6,6 +6,10 @@
 
 #include <common.h>
 #include <asm/armv8/mmu.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+
+#define GRF_EMMCCORE_CON11 0xff77f02c
 
 static struct mm_region rk3399_mem_map[] = {
 	{
@@ -28,3 +32,13 @@ static struct mm_region rk3399_mem_map[] = {
 };
 
 struct mm_region *mem_map = rk3399_mem_map;
+
+int arch_cpu_init(void)
+{
+	/* We do some SoC one time setting here. */
+
+	/* Emmc clock generator: disable the clock multipilier */
+	rk_clrreg(GRF_EMMCCORE_CON11, 0x0ff);
+
+	return 0;
+}

arch/arm/mach-tegra/board186.c

@@ -24,7 +24,12 @@ int board_init(void)
 	return tegra_board_init();
 }
 
-int board_late_init(void)
+__weak int tegra_soc_board_init_late(void)
 {
 	return 0;
 }
+
+int board_late_init(void)
+{
+	return tegra_soc_board_init_late();
+}

arch/arm/mach-tegra/tegra186/Makefile

@@ -4,5 +4,6 @@
 
 obj-y += ../board186.o
 obj-y += cache.o
+obj-y += nvtboot_board.o
 obj-y += nvtboot_ll.o
 obj-y += nvtboot_mem.o

arch/arm/mach-tegra/tegra186/cache.S

@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+
+#define SMC_SIP_INVOKE_MCE		0x82FFFF00
+#define MCE_SMC_ROC_FLUSH_CACHE		(SMC_SIP_INVOKE_MCE | 11)
+#define MCE_SMC_ROC_FLUSH_CACHE_ONLY	(SMC_SIP_INVOKE_MCE | 14)
+#define MCE_SMC_ROC_CLEAN_CACHE_ONLY	(SMC_SIP_INVOKE_MCE | 15)
+
+ENTRY(__asm_tegra_cache_smc)
+	mov	x1, #0
+	mov	x2, #0
+	mov	x3, #0
+	mov	x4, #0
+	mov	x5, #0
+	mov	x6, #0
+	smc	#0
+	mov	x0, #0
+	ret
+ENDPROC(__asm_invalidate_l3_dcache)
+
+ENTRY(__asm_invalidate_l3_dcache)
+	mov	x0, #(MCE_SMC_ROC_FLUSH_CACHE_ONLY & 0xffff)
+	movk	x0, #(MCE_SMC_ROC_FLUSH_CACHE_ONLY >> 16), lsl #16
+	b	__asm_tegra_cache_smc
+ENDPROC(__asm_invalidate_l3_dcache)
+
+ENTRY(__asm_flush_l3_dcache)
+	mov	x0, #(MCE_SMC_ROC_CLEAN_CACHE_ONLY & 0xffff)
+	movk	x0, #(MCE_SMC_ROC_CLEAN_CACHE_ONLY >> 16), lsl #16
+	b	__asm_tegra_cache_smc
+ENDPROC(__asm_flush_l3_dcache)
+
+ENTRY(__asm_invalidate_l3_icache)
+	mov	x0, #(MCE_SMC_ROC_FLUSH_CACHE & 0xffff)
+	movk	x0, #(MCE_SMC_ROC_FLUSH_CACHE >> 16), lsl #16
+	b	__asm_tegra_cache_smc
+ENDPROC(__asm_invalidate_l3_icache)

arch/arm/mach-tegra/tegra186/cache.c

@@ -1,23 +0,0 @@
-/*
- * Copyright (c) 2016, NVIDIA CORPORATION.
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-
-#include <common.h>
-#include <asm/system.h>
-
-#define SMC_SIP_INVOKE_MCE	0x82FFFF00
-#define MCE_SMC_ROC_FLUSH_CACHE	11
-
-int __asm_flush_l3_cache(void)
-{
-	struct pt_regs regs = {0};
-
-	isb();
-
-	regs.regs[0] = SMC_SIP_INVOKE_MCE | MCE_SMC_ROC_FLUSH_CACHE;
-	smc_call(&regs);
-
-	return 0;
-}

arch/arm/mach-tegra/tegra186/nvtboot_board.c

@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdt_support.h>
+#include <fdtdec.h>
+#include <asm/arch/tegra.h>
+
+extern unsigned long nvtboot_boot_x0;
+
+/*
+ * Attempt to use /chosen/nvidia,ether-mac in the nvtboot DTB to U-Boot's
+ * ethaddr environment variable if possible.
+ */
+static int set_ethaddr_from_nvtboot(void)
+{
+	const void *nvtboot_blob = (void *)nvtboot_boot_x0;
+	int ret, node, len;
+	const u32 *prop;
+
+	/* Already a valid address in the environment? If so, keep it */
+	if (getenv("ethaddr"))
+		return 0;
+
+	node = fdt_path_offset(nvtboot_blob, "/chosen");
+	if (node < 0) {
+		printf("Can't find /chosen node in nvtboot DTB\n");
+		return node;
+	}
+	prop = fdt_getprop(nvtboot_blob, node, "nvidia,ether-mac", &len);
+	if (!prop) {
+		printf("Can't find nvidia,ether-mac property in nvtboot DTB\n");
+		return -ENOENT;
+	}
+
+	ret = setenv("ethaddr", (void *)prop);
+	if (ret) {
+		printf("Failed to set ethaddr from nvtboot DTB: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+int tegra_soc_board_init_late(void)
+{
+	/* Ignore errors here; not all cases care about Ethernet addresses */
+	set_ethaddr_from_nvtboot();
+
+	return 0;
+}

arch/arm/mach-tegra/tegra186/nvtboot_ll.S

@@ -9,6 +9,7 @@
 #include <config.h>
 #include <linux/linkage.h>
 
+.align 8
 .globl	nvtboot_boot_x0
 nvtboot_boot_x0:
 	.dword 0

board/davinci/da8xxevm/omapl138_lcdk.c

@@ -333,15 +333,17 @@ int misc_init_r(void)
 			get_mac_addr(addr);
 		}
 
-		if (is_multicast_ethaddr(addr) || is_zero_ethaddr(addr)) {
-			printf("Invalid MAC address read.\n");
-			return -EINVAL;
-		}
-		sprintf((char *)tmp, "%02x:%02x:%02x:%02x:%02x:%02x", addr[0],
-				addr[1], addr[2], addr[3], addr[4], addr[5]);
+		if (!is_multicast_ethaddr(addr) && !is_zero_ethaddr(addr)) {
+			sprintf((char *)tmp, "%02x:%02x:%02x:%02x:%02x:%02x",
+				addr[0], addr[1], addr[2], addr[3], addr[4],
+				addr[5]);
 
-		setenv("ethaddr", (char *)tmp);
+			setenv("ethaddr", (char *)tmp);
+		} else {
+			printf("Invalid MAC address read.\n");
+		}
 	}
+
 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
 	/* Select RMII fucntion through the expander */
 	if (rmii_hw_init())

board/engicam/icorem6/MAINTAINERS

@@ -2,5 +2,6 @@ ICOREM6QDL BOARD
 M:	Jagan Teki <jagan@amarulasolutions.com>
 S:	Maintained
 F:	board/engicam/icorem6
-F:	include/configs/icorem6qdl.h
-F:	configs/icorem6qdl_defconfig
+F:	include/configs/imx6qdl_icore.h
+F:	configs/imx6qdl_icore_mmc_defconfig
+F:	configs/imx6qdl_icore_nand_defconfig

board/engicam/icorem6/README

@@ -4,7 +4,7 @@ How to use U-Boot on Engicam i.CoreM6 DualLite/Solo and Quad/Dual Starter Kit:
 - Configure U-Boot for Engicam i.CoreM6 QDL:
 
 $ make mrproper
-$ make icorem6qdl_mmc_defconfig
+$ make imx6qdl_icore_mmc_defconfig
 
 - Build for i.CoreM6 DualLite/Solo
 

board/freescale/mx6sabresd/mx6sabresd.c

@@ -362,6 +362,39 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
+static int ar8031_phy_fixup(struct phy_device *phydev)
+{
+	unsigned short val;
+
+	/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+	val &= 0xffe3;
+	val |= 0x18;
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+	/* introduce tx clock delay */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+	val |= 0x0100;
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	ar8031_phy_fixup(phydev);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
 #if defined(CONFIG_VIDEO_IPUV3)
 static void disable_lvds(struct display_info_t const *dev)
 {

board/freescale/mx6ullevk/README

@@ -0,0 +1,36 @@
+How to use U-Boot on Freescale MX6ULL 14x14 EVK
+----------------------------------------------
+
+- First make sure you have installed the dtc package (device tree compiler):
+
+$ sudo apt-get install device-tree-compiler
+
+- Build U-Boot for MX6ULL 14x14 EVK:
+
+$ make mrproper
+$ make mx6ull_14x14_evk_defconfig
+$ make
+
+This generates the u-boot-dtb.imx image in the current directory.
+
+- Flash the u-boot-dtb.imx image into the micro SD card:
+
+$ sudo dd if=u-boot-dtb.imx of=/dev/sdb bs=1K seek=1 && sync
+
+- Jumper settings:
+
+SW601: 0 0 1 0
+Sw602: 1 0
+
+Where 0 means bottom position and 1 means top position (from the switch label
+numbers reference).
+
+Connect the USB cable between the EVK and the PC for the console.
+(The USB console connector is the one close the push buttons)
+
+Insert the micro SD card in the board, power it up and U-Boot messages should
+come up.
+
+The link for the board: http://www.nxp.com/products/microcontrollers-and- \
+processors/arm-processors/i.mx-applications-processors/i.mx-6-processors/ \
+i.mx6qp/evaluation-kit-for-the-i.mx-6ull-applications-processor:MCIMX6ULL-EVK

board/isee/igep00x0/igep00x0.c

@@ -27,24 +27,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-const omap3_sysinfo sysinfo = {
-	DDR_STACKED,
-#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
-	"IGEPv2",
-#endif
-#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
-	"IGEP COM MODULE/ELECTRON",
-#endif
-#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0032)
-	"IGEP COM PROTON",
-#endif
-#if defined(CONFIG_ENV_IS_IN_ONENAND)
-	"ONENAND",
-#else
-	"NAND",
-#endif
-};
-
 static const struct ns16550_platdata igep_serial = {
 	.base = OMAP34XX_UART3,
 	.reg_shift = 2,
@@ -102,10 +84,22 @@ void get_board_mem_timings(struct board_sdrc_timings *timings)
 	int mfr, id, err = identify_nand_chip(&mfr, &id);
 
 	timings->mr = MICRON_V_MR_165;
-	if (!err && mfr == NAND_MFR_MICRON) {
-		timings->mcfg = MICRON_V_MCFG_200(256 << 20);
-		timings->ctrla = MICRON_V_ACTIMA_200;
-		timings->ctrlb = MICRON_V_ACTIMB_200;
+	if (!err) {
+		switch (mfr) {
+		case NAND_MFR_HYNIX:
+			timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
+			timings->ctrla = HYNIX_V_ACTIMA_200;
+			timings->ctrlb = HYNIX_V_ACTIMB_200;
+			break;
+		case NAND_MFR_MICRON:
+			timings->mcfg = MICRON_V_MCFG_200(256 << 20);
+			timings->ctrla = MICRON_V_ACTIMA_200;
+			timings->ctrlb = MICRON_V_ACTIMB_200;
+			break;
+		default:
+			/* Should not happen... */
+			break;
+		}
 		timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
 		gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
 	} else {

board/ti/am335x/mux.c

@@ -397,7 +397,7 @@ void enable_board_pin_mux(void)
 		configure_module_pin_mux(rmii1_pin_mux);
 		configure_module_pin_mux(spi0_pin_mux);
 	} else {
-		puts("Unknown board, cannot configure pinmux.");
-		hang();
+		/* Unknown board. We might still be able to boot. */
+		puts("Bad EEPROM or unknown board, cannot configure pinmux.");
 	}
 }

board/ti/ks2_evm/board_k2g.c

@@ -66,7 +66,7 @@ static struct pll_init_data tetris_pll_config[NUM_SPDS] = {
 
 static struct pll_init_data uart_pll_config = {UART_PLL, 64, 1, 4};
 static struct pll_init_data nss_pll_config = {NSS_PLL, 250, 3, 2};
-static struct pll_init_data ddr3_pll_config = {DDR3A_PLL, 250, 3, 10};
+static struct pll_init_data ddr3_pll_config = {DDR3A_PLL, 133, 1, 16};
 
 struct pll_init_data *get_pll_init_data(int pll)
 {

board/wandboard/wandboard.c

@@ -189,6 +189,39 @@ int board_mmc_init(bd_t *bis)
 	return 0;
 }
 
+static int ar8031_phy_fixup(struct phy_device *phydev)
+{
+	unsigned short val;
+
+	/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+	val &= 0xffe3;
+	val |= 0x18;
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+	/* introduce tx clock delay */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+	val |= 0x0100;
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	ar8031_phy_fixup(phydev);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
 #if defined(CONFIG_VIDEO_IPUV3)
 struct i2c_pads_info mx6q_i2c2_pad_info = {
 	.scl = {

common/dfu.c

@@ -24,7 +24,11 @@ int run_usb_dnl_gadget(int usbctrl_index, char *usb_dnl_gadget)
 	bool dfu_reset = false;
 	int ret, i = 0;
 
-	board_usb_init(usbctrl_index, USB_INIT_DEVICE);
+	ret = board_usb_init(usbctrl_index, USB_INIT_DEVICE);
+	if (ret) {
+		error("board usb init failed\n");
+		return CMD_RET_FAILURE;
+	}
 	g_dnl_clear_detach();
 	ret = g_dnl_register(usb_dnl_gadget);
 	if (ret) {

common/image.c

@@ -587,10 +587,12 @@ const table_entry_t *get_table_entry(const table_entry_t *table, int id)
 
 static const char *unknown_msg(enum ih_category category)
 {
+	static const char unknown_str[] = "Unknown ";
 	static char msg[30];
 
-	strcpy(msg, "Unknown ");
-	strcat(msg, table_info[category].desc);
+	strcpy(msg, unknown_str);
+	strncat(msg, table_info[category].desc,
+		sizeof(msg) - sizeof(unknown_str));
 
 	return msg;
 }

configs/evb-rk3288_defconfig

@@ -64,3 +64,4 @@ CONFIG_SYSRESET=y
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y
+CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y

configs/fennec-rk3288_defconfig

@@ -63,3 +63,4 @@ CONFIG_SYSRESET=y
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y
+CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y

configs/igep0020_defconfig

@@ -7,6 +7,7 @@ CONFIG_BOOTDELAY=3
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
 CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_SPL=y
 CONFIG_SPL_MTD_SUPPORT=y
 CONFIG_SPL_ONENAND_SUPPORT=y

configs/igep0030_defconfig

@@ -2,10 +2,12 @@ CONFIG_ARM=y
 CONFIG_OMAP34XX=y
 # CONFIG_SPL_EXT_SUPPORT is not set
 CONFIG_TARGET_OMAP3_IGEP00X0=y
-CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_ONENAND"
+CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0030"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
 CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_SPL=y
 CONFIG_SPL_MTD_SUPPORT=y
 CONFIG_SPL_ONENAND_SUPPORT=y
@@ -30,5 +32,6 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_CMD_UBI=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y

configs/igep0030_nand_defconfig

@@ -1,34 +0,0 @@
-CONFIG_ARM=y
-CONFIG_OMAP34XX=y
-# CONFIG_SPL_EXT_SUPPORT is not set
-CONFIG_TARGET_OMAP3_IGEP00X0=y
-CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_NAND"
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL=y
-CONFIG_SPL_MTD_SUPPORT=y
-CONFIG_SPL_ONENAND_SUPPORT=y
-CONFIG_SPL_OS_BOOT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_IMLS is not set
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_CMD_UBI=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y

configs/igep0032_defconfig

@@ -2,10 +2,12 @@ CONFIG_ARM=y
 CONFIG_OMAP34XX=y
 # CONFIG_SPL_EXT_SUPPORT is not set
 CONFIG_TARGET_OMAP3_IGEP00X0=y
-CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0032,BOOT_ONENAND"
+CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0032"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
 CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_SPL=y
 CONFIG_SPL_MTD_SUPPORT=y
 CONFIG_SPL_ONENAND_SUPPORT=y

configs/miniarm-rk3288_defconfig

@@ -62,3 +62,4 @@ CONFIG_SYSRESET=y
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y
+CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y

configs/p2771-0000-000_defconfig

@@ -30,6 +30,7 @@ CONFIG_CMD_FS_GENERIC=y
 # CONFIG_BLK is not set
 CONFIG_TEGRA186_BPMP_I2C=y
 # CONFIG_DM_MMC_OPS is not set
+CONFIG_DWC_ETH_QOS=y
 CONFIG_E1000=y
 CONFIG_RTL8169=y
 CONFIG_PCI=y

configs/p2771-0000-500_defconfig

@@ -30,6 +30,7 @@ CONFIG_CMD_FS_GENERIC=y
 # CONFIG_BLK is not set
 CONFIG_TEGRA186_BPMP_I2C=y
 # CONFIG_DM_MMC_OPS is not set
+CONFIG_DWC_ETH_QOS=y
 CONFIG_E1000=y
 CONFIG_RTL8169=y
 CONFIG_PCI=y

configs/popmetal-rk3288_defconfig

@@ -62,3 +62,4 @@ CONFIG_SYSRESET=y
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y
+CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y

doc/README.arm64

@@ -2,23 +2,31 @@ U-Boot for arm64
 
 Summary
 =======
-No hardware platform of arm64 is available now. The U-Boot is
-simulated on Foundation Model and Fast Model for ARMv8.
+The initial arm64 U-Boot port was developed before hardware was available,
+so the first supported platforms were the Foundation and Fast Model for ARMv8.
+These days U-Boot runs on a variety of 64-bit capable ARM hardware, from
+embedded development boards to servers.
 
 Notes
 =====
 
-1. Currenly, U-Boot run at the highest exception level processor
-   supported and jump to EL2 or optionally EL1 before enter OS.
+1. U-Boot can run at any exception level it is entered in, it is
+   recommened to enter it in EL3 if U-Boot takes some responsibilities of a
+   classical firmware (like initial hardware setup, CPU errata workarounds
+   or SMP bringup). U-Boot can be entered in EL2 when its main purpose is
+   that of a boot loader. It can drop to lower exception levels before
+   entering the OS.
 
 2. U-Boot for arm64 is compiled with AArch64-gcc. AArch64-gcc
    use rela relocation format, a tool(tools/relocate-rela) by Scott Wood
    is used to encode the initial addend of rela to u-boot.bin. After running,
    the U-Boot will be relocated to destination again.
 
-3. Fdt should be placed at a 2-megabyte boundary and within the first 512
-   megabytes from the start of the kernel image. So, fdt_high should be
-   defined specially.
+3. Earlier Linux kernel versions required the FDT to be placed at a
+   2 MB boundary and within the same 512 MB section as the kernel image,
+   resulting in fdt_high to be defined specially.
+   Since kernel version 4.2 Linux is more relaxed about the DT location, so it
+   can be placed anywhere in memory.
    Please reference linux/Documentation/arm64/booting.txt for detail.
 
 4. Spin-table is used to wake up secondary processors. One location
@@ -37,9 +45,8 @@ Notes
    aarch32 specific codes.
 
 
-
-Contributor
-===========
+Contributors
+============
    Tom Rini            <trini@ti.com>
    Scott Wood          <scottwood@freescale.com>
    York Sun            <yorksun@freescale.com>

doc/README.rockchip

@@ -149,7 +149,6 @@ Note: rk3036 SDMMC and debug uart use the same iomux, so if you boot from SD, th
 
 Using fastboot on rk3288
 ========================
-- Define GPT partition layout like kylin_rk3036(see include/configs/kylin_rk3036.h)
 - Write GPT partition layout to mmc device which fastboot want to use it to
 store the image
 
@@ -212,7 +211,6 @@ When booting you should see something like:
    Err:   serial@ff690000
    =>
 
-
 Future work
 ===========
 
@@ -298,6 +296,15 @@ overhead and in SPL with a 32KB size limit some shortcuts have been taken.
 In general all Rockchip drivers should use these features, with SPL-specific
 modifications where required.
 
+GPT partition layout
+----------------------------
+
+Rockchip use a unified GPT partition layout  in open source support.
+With this GPT partition layout, uboot can be compatilbe with other components,
+like miniloader, trusted-os, arm-trust-firmware.
+
+There are some documents about partitions in the links below.
+http://rockchip.wikidot.com/partitions
 
 --
 Simon Glass <sjg@chromium.org>

doc/device-tree-bindings/net/snps,dwc-qos-ethernet.txt

@@ -0,0 +1,166 @@
+* Synopsys DWC Ethernet QoS IP version 4.10 driver (GMAC)
+
+This binding supports the Synopsys Designware Ethernet QoS (Quality Of Service)
+IP block. The IP supports multiple options for bus type, clocking and reset
+structure, and feature list. Consequently, a number of properties and list
+entries in properties are marked as optional, or only required in specific HW
+configurations.
+
+Required properties:
+- compatible: One of:
+  - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
+    Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
+  - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
+    Represents the IP core when integrated into the NVIDIA Tegra186 SoC.
+  - "snps,dwc-qos-ethernet-4.10"
+    This combination is deprecated. It should be treated as equivalent to
+    "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
+    compatible with earlier revisions of this binding.
+- reg: Address and length of the register set for the device
+- clocks: Phandle and clock specifiers for each entry in clock-names, in the
+  same order. See ../clock/clock-bindings.txt.
+- clock-names: May contain any/all of the following depending on the IP
+  configuration, in any order:
+  - "tx"
+    The EQOS transmit path clock. The HW signal name is clk_tx_i.
+    In some configurations (e.g. GMII/RGMII), this clock also drives the PHY TX
+    path. In other configurations, other clocks (such as tx_125, rmii) may
+    drive the PHY TX path.
+  - "rx"
+    The EQOS receive path clock. The HW signal name is clk_rx_i.
+    In some configurations (e.g. GMII/RGMII), this clock is derived from the
+    PHY's RX clock output. In other configurations, other clocks (such as
+    rx_125, rmii) may drive the EQOS RX path.
+    In cases where the PHY clock is directly fed into the EQOS receive path
+    without intervening logic, the DT need not represent this clock, since it
+    is assumed to be fully under the control of the PHY device/driver. In
+    cases where SoC integration adds additional logic to this path, such as a
+    SW-controlled clock gate, this clock should be represented in DT.
+  - "slave_bus"
+    The CPU/slave-bus (CSR) interface clock. This applies to any bus type;
+    APB, AHB, AXI, etc. The HW signal name is hclk_i (AHB) or clk_csr_i (other
+    buses).
+  - "master_bus"
+    The master bus interface clock. Only required in configurations that use a
+    separate clock for the master and slave bus interfaces. The HW signal name
+    is hclk_i (AHB) or aclk_i (AXI).
+  - "ptp_ref"
+    The PTP reference clock. The HW signal name is clk_ptp_ref_i.
+  - "phy_ref_clk"
+    This clock is deprecated and should not be used by new compatible values.
+    It is equivalent to "tx".
+  - "apb_pclk"
+    This clock is deprecated and should not be used by new compatible values.
+    It is equivalent to "slave_bus".
+
+  Note: Support for additional IP configurations may require adding the
+  following clocks to this list in the future: clk_rx_125_i, clk_tx_125_i,
+  clk_pmarx_0_i, clk_pmarx1_i, clk_rmii_i, clk_revmii_rx_i, clk_revmii_tx_i.
+  Configurations exist where multiple similar clocks are used at once, e.g. all
+  of clk_rx_125_i, clk_pmarx_0_i, clk_pmarx1_i. For this reason it is best to
+  extend the binding with a separate clock-names entry for each of those RX
+  clocks, rather than repurposing the existing "rx" clock-names entry as a
+  generic/logical clock in a similar fashion to "master_bus" and "slave_bus".
+  This will allow easy support for configurations that support multiple PHY
+  interfaces using a mux, and hence need to have explicit control over
+  specific RX clocks.
+
+  The following compatible values require the following set of clocks:
+  - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10":
+    - "slave_bus"
+    - "master_bus"
+    - "rx"
+    - "tx"
+    - "ptp_ref"
+  - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10":
+    - "slave_bus"
+    - "master_bus"
+    - "tx"
+    - "ptp_ref"
+  - "snps,dwc-qos-ethernet-4.10" (deprecated):
+    - "phy_ref_clk"
+    - "apb_clk"
+- interrupt-parent: Should be the phandle for the interrupt controller
+  that services interrupts for this device
+- interrupts: Should contain the core's combined interrupt signal
+- phy-mode: See ethernet.txt file in the same directory
+- resets: Phandle and reset specifiers for each entry in reset-names, in the
+  same order. See ../reset/reset.txt.
+- reset-names: May contain any/all of the following depending on the IP
+  configuration, in any order:
+  - "eqos". The reset to the entire module. The HW signal name is hreset_n
+    (AHB) or aresetn_i (AXI).
+
+  The following compatible values require the following set of resets:
+  (the reset properties may be omitted if empty)
+  - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10":
+    - "eqos".
+  - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10":
+    - None.
+  - "snps,dwc-qos-ethernet-4.10" (deprecated):
+    - None.
+
+Optional properties:
+- dma-coherent: Present if dma operations are coherent
+- mac-address: See ethernet.txt in the same directory
+- local-mac-address: See ethernet.txt in the same directory
+- phy-reset-gpios: Phandle and specifier for any GPIO used to reset the PHY.
+  See ../gpio/gpio.txt.
+- snps,en-lpi: If present it enables use of the AXI low-power interface
+- snps,write-requests: Number of write requests that the AXI port can issue.
+  It depends on the SoC configuration.
+- snps,read-requests: Number of read requests that the AXI port can issue.
+  It depends on the SoC configuration.
+- snps,burst-map: Bitmap of allowed AXI burst lengts, with the LSB
+  representing 4, then 8 etc.
+- snps,txpbl: DMA Programmable burst length for the TX DMA
+- snps,rxpbl: DMA Programmable burst length for the RX DMA
+- snps,en-tx-lpi-clockgating: Enable gating of the MAC TX clock during
+  TX low-power mode.
+- phy-handle: See ethernet.txt file in the same directory
+- mdio device tree subnode: When the GMAC has a phy connected to its local
+    mdio, there must be device tree subnode with the following
+    required properties:
+    - compatible: Must be "snps,dwc-qos-ethernet-mdio".
+    - #address-cells: Must be <1>.
+    - #size-cells: Must be <0>.
+
+    For each phy on the mdio bus, there must be a node with the following
+    fields:
+
+    - reg: phy id used to communicate to phy.
+    - device_type: Must be "ethernet-phy".
+    - fixed-mode device tree subnode: see fixed-link.txt in the same directory
+
+Examples:
+ethernet2@40010000 {
+	clock-names = "phy_ref_clk", "apb_pclk";
+	clocks = <&clkc 17>, <&clkc 15>;
+	compatible = "snps,dwc-qos-ethernet-4.10";
+	interrupt-parent = <&intc>;
+	interrupts = <0x0 0x1e 0x4>;
+	reg = <0x40010000 0x4000>;
+	phy-handle = <&phy2>;
+	phy-mode = "gmii";
+	phy-reset-gpios = <&gpioctlr 43 GPIO_ACTIVE_LOW>;
+
+	snps,en-tx-lpi-clockgating;
+	snps,en-lpi;
+	snps,write-requests = <2>;
+	snps,read-requests = <16>;
+	snps,burst-map = <0x7>;
+	snps,txpbl = <8>;
+	snps,rxpbl = <2>;
+
+	dma-coherent;
+
+	mdio {
+		#address-cells = <0x1>;
+		#size-cells = <0x0>;
+		phy2: phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			device_type = "ethernet-phy";
+			reg = <0x1>;
+		};
+	};
+};

doc/mkimage.1

@@ -137,6 +137,10 @@ compilation is performed and the \-f flag should not be given.
 This can be used to sign images with additional keys after initial image
 creation.
 
+.TP
+.BI "\-i [" "ramdisk_file" "]"
+Appends the ramdisk file to the FIT.
+
 .TP
 .BI "\-k [" "key_directory" "]"
 Specifies the directory containing keys to use for signing. This directory

drivers/clk/rockchip/clk_rk3036.c

@@ -19,11 +19,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-struct rk3036_clk_priv {
-	struct rk3036_cru *cru;
-	ulong rate;
-};
-
 enum {
 	VCO_MAX_HZ	= 2400U * 1000000,
 	VCO_MIN_HZ	= 600 * 1000000,
@@ -49,23 +44,6 @@ enum {
 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
 
-void *rockchip_get_cru(void)
-{
-	struct udevice *dev;
-	fdt_addr_t addr;
-	int ret;
-
-	ret = uclass_get_device(UCLASS_CLK, 0, &dev);
-	if (ret)
-		return ERR_PTR(ret);
-
-	addr = dev_get_addr(dev);
-	if (addr == FDT_ADDR_T_NONE)
-		return ERR_PTR(-EINVAL);
-
-	return (void *)addr;
-}
-
 static int rkclk_set_pll(struct rk3036_cru *cru, enum rk_clk_id clk_id,
 			 const struct pll_div *div)
 {
@@ -371,7 +349,7 @@ static const struct udevice_id rk3036_clk_ids[] = {
 	{ }
 };
 
-U_BOOT_DRIVER(clk_rk3036) = {
+U_BOOT_DRIVER(rockchip_rk3036_cru) = {
 	.name		= "clk_rk3036",
 	.id		= UCLASS_CLK,
 	.of_match	= rk3036_clk_ids,

drivers/clk/rockchip/clk_rk3288.c

@@ -30,12 +30,6 @@ struct rk3288_clk_plat {
 #endif
 };
 
-struct rk3288_clk_priv {
-	struct rk3288_grf *grf;
-	struct rk3288_cru *cru;
-	ulong rate;
-};
-
 struct pll_div {
 	u32 nr;
 	u32 nf;
@@ -140,21 +134,6 @@ static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
 
-void *rockchip_get_cru(void)
-{
-	struct rk3288_clk_priv *priv;
-	struct udevice *dev;
-	int ret;
-
-	ret = rockchip_get_clk(&dev);
-	if (ret)
-		return ERR_PTR(ret);
-
-	priv = dev_get_priv(dev);
-
-	return priv->cru;
-}
-
 static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,
 			 const struct pll_div *div)
 {

drivers/clk/rockchip/clk_rk3399.c

@@ -18,11 +18,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-struct rk3399_clk_priv {
-	struct rk3399_cru *cru;
-	ulong rate;
-};
-
 struct rk3399_pmuclk_priv {
 	struct rk3399_pmucru *pmucru;
 };
@@ -780,23 +775,6 @@ static struct clk_ops rk3399_clk_ops = {
 	.set_rate = rk3399_clk_set_rate,
 };
 
-void *rockchip_get_cru(void)
-{
-	struct udevice *dev;
-	fdt_addr_t *addr;
-	int ret;
-
-	ret = uclass_get_device_by_name(UCLASS_CLK, "clk_rk3399", &dev);
-	if (ret)
-		return ERR_PTR(ret);
-
-	addr = dev_get_addr_ptr(dev);
-	if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
-		return ERR_PTR(-EINVAL);
-
-	return addr;
-}
-
 static int rk3399_clk_probe(struct udevice *dev)
 {
 	struct rk3399_clk_priv *priv = dev_get_priv(dev);
@@ -990,7 +968,7 @@ static const struct udevice_id rk3399_pmuclk_ids[] = {
 	{ }
 };
 
-U_BOOT_DRIVER(pmuclk_rk3399) = {
+U_BOOT_DRIVER(rockchip_rk3399_pmuclk) = {
 	.name		= "pmuclk_rk3399",
 	.id		= UCLASS_CLK,
 	.of_match	= rk3399_pmuclk_ids,

drivers/dfu/dfu.c

@@ -482,7 +482,7 @@ int dfu_config_entities(char *env, char *interface, char *devstr)
 
 const char *dfu_get_dev_type(enum dfu_device_type t)
 {
-	const char *dev_t[] = {NULL, "eMMC", "OneNAND", "NAND", "RAM" };
+	const char *dev_t[] = {NULL, "eMMC", "OneNAND", "NAND", "RAM", "SF" };
 	return dev_t[t];
 }
 

drivers/net/Kconfig

@@ -64,6 +64,17 @@ config ALTERA_TSE
 	  Please find details on the "Triple-Speed Ethernet MegaCore Function
 	  Resource Center" of Altera.
 
+config DWC_ETH_QOS
+	bool "Synopsys DWC Ethernet QOS device support"
+	depends on DM_ETH
+	select PHYLIB
+	help
+	  This driver supports the Synopsys Designware Ethernet QOS (Quality
+	  Of Service) IP block. The IP supports many options for bus type,
+	  clocking/reset structure, and feature list. This driver currently
+	  supports the specific configuration used in NVIDIA's Tegra186 chip,
+	  but should be extensible to other combinations quite easily.
+
 config E1000
 	bool "Intel PRO/1000 Gigabit Ethernet support"
 	help

drivers/net/Makefile

@@ -76,3 +76,4 @@ obj-$(CONFIG_FSL_MC_ENET) += ldpaa_eth/
 obj-$(CONFIG_FSL_MEMAC) += fm/memac_phy.o
 obj-$(CONFIG_VSC9953) += vsc9953.o
 obj-$(CONFIG_PIC32_ETH) += pic32_mdio.o pic32_eth.o
+obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o

drivers/net/mvgbe.c

@@ -177,25 +177,6 @@ static int smi_reg_write(struct mii_dev *bus, int phy_adr, int devad,
 }
 #endif
 
-#if defined(CONFIG_PHYLIB)
-int mvgbe_phy_read(struct mii_dev *bus, int phy_addr, int dev_addr,
-		   int reg_addr)
-{
-	u16 data;
-	int ret;
-	ret = smi_reg_read(bus->name, phy_addr, reg_addr, &data);
-	if (ret)
-		return ret;
-	return data;
-}
-
-int mvgbe_phy_write(struct mii_dev *bus, int phy_addr, int dev_addr,
-		    int reg_addr, u16 data)
-{
-	return smi_reg_write(bus->name, phy_addr, reg_addr, data);
-}
-#endif
-
 /* Stop and checks all queues */
 static void stop_queue(u32 * qreg)
 {
@@ -676,8 +657,8 @@ int mvgbe_phylib_init(struct eth_device *dev, int phyid)
 		printf("mdio_alloc failed\n");
 		return -ENOMEM;
 	}
-	bus->read = mvgbe_phy_read;
-	bus->write = mvgbe_phy_write;
+	bus->read = smi_reg_read;
+	bus->write = smi_reg_write;
 	strcpy(bus->name, dev->name);
 
 	ret = mdio_register(bus);
@@ -688,7 +669,7 @@ int mvgbe_phylib_init(struct eth_device *dev, int phyid)
 	}
 
 	/* Set phy address of the port */
-	mvgbe_phy_write(bus, MV_PHY_ADR_REQUEST, 0, MV_PHY_ADR_REQUEST, phyid);
+	smi_reg_write(bus, MV_PHY_ADR_REQUEST, 0, MV_PHY_ADR_REQUEST, phyid);
 
 	phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_RGMII);
 	if (!phydev) {

drivers/net/phy/micrel.c

@@ -415,11 +415,31 @@ static int ksz9031_of_config(struct phy_device *phydev)
 
 	return 0;
 }
+
+static int ksz9031_center_flp_timing(struct phy_device *phydev)
+{
+	struct phy_driver *drv = phydev->drv;
+	int ret = 0;
+
+	if (!drv || !drv->writeext)
+		return -EOPNOTSUPP;
+
+	ret = drv->writeext(phydev, 0, 0, MII_KSZ9031_FLP_BURST_TX_LO, 0x1A80);
+	if (ret)
+		return ret;
+
+	ret = drv->writeext(phydev, 0, 0, MII_KSZ9031_FLP_BURST_TX_HI, 0x6);
+	return ret;
+}
 #else
 static int ksz9031_of_config(struct phy_device *phydev)
 {
 	return 0;
 }
+static int ksz9031_center_flp_timing(struct phy_device *phydev)
+{
+	return 0;
+}
 #endif
 
 /* Accessors to extended registers*/
@@ -470,6 +490,9 @@ static int ksz9031_config(struct phy_device *phydev)
 {
 	int ret;
 	ret = ksz9031_of_config(phydev);
+	if (ret)
+		return ret;
+	ret = ksz9031_center_flp_timing(phydev);
 	if (ret)
 		return ret;
 	return genphy_config(phydev);

drivers/spi/ti_qspi.c

@@ -16,6 +16,7 @@
 #include <asm/omap_gpio.h>
 #include <asm/omap_common.h>
 #include <asm/ti-common/ti-edma3.h>
+#include <linux/kernel.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -118,21 +119,18 @@ static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz)
 	if (!hz)
 		clk_div = 0;
 	else
-		clk_div = (priv->fclk / hz) - 1;
+		clk_div = DIV_ROUND_UP(priv->fclk, hz) - 1;
+
+	/* truncate clk_div value to QSPI_CLK_DIV_MAX */
+	if (clk_div > QSPI_CLK_DIV_MAX)
+		clk_div = QSPI_CLK_DIV_MAX;
 
 	debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
 
 	/* disable SCLK */
 	writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,
 	       &priv->base->clk_ctrl);
-
-	/* assign clk_div values */
-	if (clk_div < 0)
-		clk_div = 0;
-	else if (clk_div > QSPI_CLK_DIV_MAX)
-		clk_div = QSPI_CLK_DIV_MAX;
-
-	/* enable SCLK */
+	/* enable SCLK and program the clk divider */
 	writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);
 }
 

drivers/video/video_bmp.c

@@ -312,7 +312,7 @@ int video_bmp_display(struct udevice *dev, ulong bmp_image, int x, int y,
 				fb_put_word(&fb, &bmap);
 
 			bmap += (padded_width - width) * 2;
-			fb -= width * 2 + lcd_line_length;
+			fb -= width * 2 + priv->line_length;
 		}
 		break;
 #endif /* CONFIG_BMP_16BPP */
@@ -325,7 +325,7 @@ int video_bmp_display(struct udevice *dev, ulong bmp_image, int x, int y,
 				*(fb++) = *(bmap++);
 				*(fb++) = 0;
 			}
-			fb -= lcd_line_length + width * (bpix / 8);
+			fb -= priv->line_length + width * (bpix / 8);
 		}
 		break;
 #endif /* CONFIG_BMP_24BMP */
@@ -338,7 +338,7 @@ int video_bmp_display(struct udevice *dev, ulong bmp_image, int x, int y,
 				*(fb++) = *(bmap++);
 				*(fb++) = *(bmap++);
 			}
-			fb -= lcd_line_length + width * (bpix / 8);
+			fb -= priv->line_length + width * (bpix / 8);
 		}
 		break;
 #endif /* CONFIG_BMP_32BPP */

include/configs/colibri_pxa270.h

@@ -39,7 +39,6 @@
 #define	CONFIG_TIMESTAMP
 #define	CONFIG_CMDLINE_TAG
 #define	CONFIG_SETUP_MEMORY_TAGS
-#define	CONFIG_LZMA			/* LZMA compression support */
 
 /*
  * Serial Console Configuration

include/configs/evb_rk3399.h

@@ -10,7 +10,7 @@
 #include <configs/rk3399_common.h>
 
 #define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_SYS_MMC_ENV_DEV 1
 /*
  * SPL @ 32k for ~36k
  * ENV @ 96k

include/configs/rk3036_common.h

@@ -7,6 +7,7 @@
 #define __CONFIG_RK3036_COMMON_H
 
 #include <asm/arch/hardware.h>
+#include "rockchip-common.h"
 
 #define CONFIG_SYS_NO_FLASH
 #define CONFIG_NR_DRAM_BANKS		1
@@ -78,11 +79,6 @@
 #define CONFIG_G_DNL_VENDOR_NUM		0x2207
 #define CONFIG_G_DNL_PRODUCT_NUM	0x310a
 
-/* Enable gpt partition table */
-#define CONFIG_CMD_GPT
-
-#include <config_distro_defaults.h>
-
 #define ENV_MEM_LAYOUT_SETTINGS \
 	"scriptaddr=0x60000000\0" \
 	"pxefile_addr_r=0x60100000\0" \
@@ -90,17 +86,6 @@
 	"kernel_addr_r=0x62000000\0" \
 	"ramdisk_addr_r=0x64000000\0"
 
-#define CONFIG_RANDOM_UUID
-#define PARTS_DEFAULT \
-	"uuid_disk=${uuid_gpt_disk};" \
-	"name=boot,start=8M,size=64M,bootable,uuid=${uuid_gpt_boot};" \
-	"name=rootfs,size=-,uuid=${uuid_gpt_rootfs};\0" \
-
-/* First try to boot from SD (index 0), then eMMC (index 1 */
-#define BOOT_TARGET_DEVICES(func) \
-	func(MMC, mmc, 0) \
-	func(MMC, mmc, 1)
-
 #include <config_distro_bootcmd.h>
 
 /* Linux fails to load the fdt if it's loaded above 512M on a evb-rk3036 board,

include/configs/rk3288_common.h

@@ -8,6 +8,7 @@
 #define __CONFIG_RK3288_COMMON_H
 
 #include <asm/arch/hardware.h>
+#include "rockchip-common.h"
 
 #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
 #define CONFIG_SYS_NO_FLASH
@@ -89,11 +90,6 @@
 #define CONFIG_G_DNL_VENDOR_NUM		0x2207
 #define CONFIG_G_DNL_PRODUCT_NUM	0x320a
 
-/* Enable gpt partition table */
-#define CONFIG_CMD_GPT
-
-#include <config_distro_defaults.h>
-
 #define ENV_MEM_LAYOUT_SETTINGS \
 	"scriptaddr=0x00000000\0" \
 	"pxefile_addr_r=0x00100000\0" \
@@ -101,24 +97,13 @@
 	"kernel_addr_r=0x02000000\0" \
 	"ramdisk_addr_r=0x04000000\0"
 
-#define CONFIG_RANDOM_UUID
-#define PARTS_DEFAULT \
-	"uuid_disk=${uuid_gpt_disk};" \
-	"name=boot,start=8M,size=64M,bootable,uuid=${uuid_gpt_boot};" \
-	"name=rootfs,size=-,uuid=${uuid_gpt_rootfs};\0" \
-
-/* First try to boot from SD (index 0), then eMMC (index 1 */
-#define BOOT_TARGET_DEVICES(func) \
-	func(MMC, mmc, 0) \
-	func(MMC, mmc, 1)
-
 #include <config_distro_bootcmd.h>
 
-/* Linux fails to load the fdt if it's loaded above 512M on a Rock 2 board, so
+/* Linux fails to load the fdt if it's loaded above 256M on a Rock 2 board, so
  * limit the fdt reallocation to that */
 #define CONFIG_EXTRA_ENV_SETTINGS \
-	"fdt_high=0x1fffffff\0" \
-	"initrd_high=0x1fffffff\0" \
+	"fdt_high=0x0fffffff\0" \
+	"initrd_high=0x0fffffff\0" \
 	"partitions=" PARTS_DEFAULT \
 	ENV_MEM_LAYOUT_SETTINGS \
 	ROCKCHIP_DEVICE_SETTINGS \

include/configs/rk3399_common.h

@@ -7,6 +7,8 @@
 #ifndef __CONFIG_RK3399_COMMON_H
 #define __CONFIG_RK3399_COMMON_H
 
+#include "rockchip-common.h"
+
 #define CONFIG_SYS_NO_FLASH
 #define CONFIG_NR_DRAM_BANKS		1
 #define CONFIG_ENV_SIZE			0x2000
@@ -52,7 +54,6 @@
 #define CONFIG_SF_DEFAULT_SPEED 20000000
 
 #ifndef CONFIG_SPL_BUILD
-#include <config_distro_defaults.h>
 
 #define ENV_MEM_LAYOUT_SETTINGS \
 	"scriptaddr=0x00000000\0" \
@@ -61,19 +62,6 @@
 	"kernel_addr_r=0x02000000\0" \
 	"ramdisk_addr_r=0x04000000\0"
 
-#define CONFIG_CMD_GPT
-#define CONFIG_RANDOM_UUID
-#define CONFIG_PARTITION_UUIDS
-#define PARTS_DEFAULT \
-	"uuid_disk=${uuid_gpt_disk};" \
-	"name=boot,start=16M,size=32M,bootable;" \
-	"name=rootfs,size=-,uuid=${uuid_gpt_rootfs};\0" \
-
-/* First try to boot from SD (index 0), then eMMC (index 1) */
-#define BOOT_TARGET_DEVICES(func) \
-	func(MMC, mmc, 0) \
-	func(MMC, mmc, 1)
-
 #include <config_distro_bootcmd.h>
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	ENV_MEM_LAYOUT_SETTINGS \

include/configs/rockchip-common.h

@@ -0,0 +1,35 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _ROCKCHIP_COMMON_H_
+#define _ROCKCHIP_COMMON_H_
+#include <linux/sizes.h>
+
+#ifndef CONFIG_SPL_BUILD
+#include <config_distro_defaults.h>
+
+/* First try to boot from SD (index 0), then eMMC (index 1 */
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(MMC, mmc, 1)
+
+ /* Enable gpt partition table */
+#define CONFIG_CMD_GPT
+#define CONFIG_RANDOM_UUID
+#define CONFIG_PARTITION_UUIDS
+#define PARTS_DEFAULT \
+	"uuid_disk=${uuid_gpt_disk};" \
+	"name=loader1,start=32K,size=4000K,uuid=${uuid_gpt_loader1};" \
+	"name=reserved1,size=64K,uuid=${uuid_gpt_reserved1};" \
+	"name=reserved2,size=4M,uuid=${uuid_gpt_reserved2};" \
+	"name=loader2,size=4MB,uuid=${uuid_gpt_loader2};" \
+	"name=atf,size=4M,uuid=${uuid_gpt_atf};" \
+	"name=boot,size=128M,bootable,uuid=${uuid_gpt_boot};" \
+	"name=rootfs,size=-,uuid=${uuid_gpt_rootfs};\0" \
+
+#endif
+
+#endif /* _ROCKCHIP_COMMON_H_ */

include/micrel.h

@@ -20,6 +20,9 @@
 #define MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW	0x6
 #define MII_KSZ9031_EXT_RGMII_CLOCK_SKEW	0x8
 
+#define MII_KSZ9031_FLP_BURST_TX_LO		0x3
+#define MII_KSZ9031_FLP_BURST_TX_HI		0x4
+
 /* Registers */
 #define MMD_ACCESS_CONTROL	0xd
 #define MMD_ACCESS_REG_DATA	0xe

net/eth-uclass.c

@@ -512,7 +512,8 @@ static int eth_post_probe(struct udevice *dev)
 		eth_setenv_enetaddr_by_index("eth", dev->seq, pdata->enetaddr);
 		printf("\nWarning: %s using MAC address from ROM\n",
 		       dev->name);
-	} else if (is_zero_ethaddr(pdata->enetaddr)) {
+	} else if (is_zero_ethaddr(pdata->enetaddr) ||
+		   !is_valid_ethaddr(pdata->enetaddr)) {
 #ifdef CONFIG_NET_RANDOM_ETHADDR
 		net_random_ethaddr(pdata->enetaddr);
 		printf("\nWarning: %s (eth%d) using random MAC address - %pM\n",

net/eth_legacy.c

@@ -118,6 +118,7 @@ static int on_ethaddr(const char *name, const char *value, enum env_op op,
 			case env_op_create:
 			case env_op_overwrite:
 				eth_parse_enetaddr(value, dev->enetaddr);
+				eth_write_hwaddr(dev, "eth", dev->index);
 				break;
 			case env_op_delete:
 				memset(dev->enetaddr, 0, 6);

tools/Makefile

@@ -13,7 +13,7 @@ CONFIG_CMD_NET = y
 CONFIG_XWAY_SWAP_BYTES = y
 CONFIG_NETCONSOLE = y
 CONFIG_SHA1_CHECK_UB_IMG = y
-CONFIG_SUNXI = y
+CONFIG_ARCH_SUNXI = y
 endif
 
 subdir-$(HOST_TOOLS_ALL) += easylogo

tools/buildman/board.py

@@ -92,9 +92,9 @@ class Board:
         self.board_name = board_name
         self.vendor = vendor
         self.soc = soc
-        self.props = [self.target, self.arch, self.cpu, self.board_name,
-                      self.vendor, self.soc]
         self.options = options
+        self.props = [self.target, self.arch, self.cpu, self.board_name,
+                      self.vendor, self.soc, self.options]
         self.build_it = False
 
 

tools/fit_image.c

@@ -85,8 +85,15 @@ static int fit_calc_size(struct image_tool_params *params)
 	size = imagetool_get_filesize(params, params->datafile);
 	if (size < 0)
 		return -1;
-
 	total_size = size;
+
+	if (params->fit_ramdisk) {
+		size = imagetool_get_filesize(params, params->fit_ramdisk);
+		if (size < 0)
+			return -1;
+		total_size += size;
+	}
+
 	for (cont = params->content_head; cont; cont = cont->next) {
 		size = imagetool_get_filesize(params, cont->fname);
 		if (size < 0)
@@ -233,6 +240,20 @@ static int fit_write_images(struct image_tool_params *params, char *fdt)
 		fdt_end_node(fdt);
 	}
 
+	/* And a ramdisk file if available */
+	if (params->fit_ramdisk) {
+		fdt_begin_node(fdt, FIT_RAMDISK_PROP "@1");
+
+		fdt_property_string(fdt, "type", FIT_RAMDISK_PROP);
+		fdt_property_string(fdt, "os", genimg_get_os_short_name(params->os));
+
+		ret = fdt_property_file(params, fdt, "data", params->fit_ramdisk);
+		if (ret)
+			return ret;
+
+		fdt_end_node(fdt);
+	}
+
 	fdt_end_node(fdt);
 
 	return 0;
@@ -272,15 +293,25 @@ static void fit_write_configs(struct image_tool_params *params, char *fdt)
 		snprintf(str, sizeof(str), "%s@1", typename);
 		fdt_property_string(fdt, typename, str);
 
+		if (params->fit_ramdisk)
+			fdt_property_string(fdt, FIT_RAMDISK_PROP,
+					    FIT_RAMDISK_PROP "@1");
+
 		snprintf(str, sizeof(str), FIT_FDT_PROP "@%d", upto);
 		fdt_property_string(fdt, FIT_FDT_PROP, str);
 		fdt_end_node(fdt);
 	}
+
 	if (!upto) {
 		fdt_begin_node(fdt, "conf@1");
 		typename = genimg_get_type_short_name(params->fit_image_type);
 		snprintf(str, sizeof(str), "%s@1", typename);
 		fdt_property_string(fdt, typename, str);
+
+		if (params->fit_ramdisk)
+			fdt_property_string(fdt, FIT_RAMDISK_PROP,
+					    FIT_RAMDISK_PROP "@1");
+
 		fdt_end_node(fdt);
 	}
 

tools/imagetool.h

@@ -70,6 +70,7 @@ struct image_tool_params {
 	int orig_file_size;	/* Original size for file before padding */
 	bool auto_its;		/* Automatically create the .its file */
 	int fit_image_type;	/* Image type to put into the FIT */
+	char *fit_ramdisk;	/* Ramdisk file to include */
 	struct content_info *content_head;	/* List of files to include */
 	struct content_info *content_tail;
 	bool external_data;	/* Store data outside the FIT */

tools/imximage.c

@@ -533,12 +533,19 @@ static void print_hdr_v2(struct imx_header *imx_hdr)
 
 static void copy_plugin_code(struct imx_header *imxhdr, char *plugin_file)
 {
-	int ifd = -1;
+	int ifd;
 	struct stat sbuf;
 	char *plugin_buf = imxhdr->header.hdr_v2.data.plugin_code;
 	char *ptr;
 
 	ifd = open(plugin_file, O_RDONLY|O_BINARY);
+	if (ifd < 0) {
+		fprintf(stderr, "Can't open %s: %s\n",
+			plugin_file,
+			strerror(errno));
+		exit(EXIT_FAILURE);
+	}
+
 	if (fstat(ifd, &sbuf) < 0) {
 		fprintf(stderr, "Can't stat %s: %s\n",
 			plugin_file,

tools/mkimage.c

@@ -88,12 +88,13 @@ static void usage(const char *msg)
 		"          -x ==> set XIP (execute in place)\n",
 		params.cmdname);
 	fprintf(stderr,
-		"       %s [-D dtc_options] [-f fit-image.its|-f auto|-F] [-b <dtb> [-b <dtb>]] fit-image\n"
+		"       %s [-D dtc_options] [-f fit-image.its|-f auto|-F] [-b <dtb> [-b <dtb>]] [-i <ramdisk.cpio.gz>] fit-image\n"
 		"           <dtb> file is used with -f auto, it may occur multiple times.\n",
 		params.cmdname);
 	fprintf(stderr,
 		"          -D => set all options for device tree compiler\n"
-		"          -f => input filename for FIT source\n");
+		"          -f => input filename for FIT source\n"
+		"          -i => input filename for ramdisk file\n");
 #ifdef CONFIG_FIT_SIGNATURE
 	fprintf(stderr,
 		"Signing / verified boot options: [-E] [-k keydir] [-K dtb] [ -c <comment>] [-p addr] [-r]\n"
@@ -141,7 +142,7 @@ static void process_args(int argc, char **argv)
 	int opt;
 
 	while ((opt = getopt(argc, argv,
-			     "a:A:b:c:C:d:D:e:Ef:Fk:K:ln:p:O:rR:qsT:vVx")) != -1) {
+			     "a:A:b:c:C:d:D:e:Ef:Fk:i:K:ln:p:O:rR:qsT:vVx")) != -1) {
 		switch (opt) {
 		case 'a':
 			params.addr = strtoull(optarg, &ptr, 16);
@@ -207,6 +208,9 @@ static void process_args(int argc, char **argv)
 			params.type = IH_TYPE_FLATDT;
 			params.fflag = 1;
 			break;
+		case 'i':
+			params.fit_ramdisk = optarg;
+			break;
 		case 'k':
 			params.keydir = optarg;
 			break;