Prepare v2016.09.01

Signed-off-by: Tom Rini <trini@konsulko.com>

.gitignore

@@ -31,7 +31,7 @@
 # Top-level generic files
 #
 /MLO*
-/SPL*
+/SPL
 /System.map
 /u-boot*
 /boards.cfg

.travis.yml

@@ -3,8 +3,7 @@
 
 # build U-Boot on Travis CI - https://travis-ci.org/
 
-sudo: required
-dist: trusty
+sudo: true
 
 language: c
 
@@ -19,90 +18,58 @@ addons:
     - libsdl1.2-dev
     - python
     - python-virtualenv
-    - gcc-powerpc-linux-gnu
-    - gcc-arm-linux-gnueabihf
-    - gcc-aarch64-linux-gnu
-    - iasl
-    - grub-efi-ia32-bin
-    - rpm2cpio
-    - wget
+
+cache:
+ - apt
 
 install:
  # install latest device tree compiler
- - git clone --depth=1 git://git.kernel.org/pub/scm/utils/dtc/dtc.git /tmp/dtc
+ - git clone --depth=1 https://git.kernel.org/pub/scm/utils/dtc/dtc.git /tmp/dtc
  - make -j4 -C /tmp/dtc
- # Clone uboot-test-hooks
- - git clone --depth=1 git://github.com/swarren/uboot-test-hooks.git /tmp/uboot-test-hooks
- - ln -s travis-ci /tmp/uboot-test-hooks/bin/`hostname`
- - ln -s travis-ci /tmp/uboot-test-hooks/py/`hostname`
  # prepare buildman environment
- - echo -e "[toolchain]\nroot = /usr" > ~/.buildman
- - echo -e "\n[toolchain-alias]\nblackfin = bfin\nsh = sh4\nopenrisc = or32" >> ~/.buildman
+ - export BUILDMAN_ROOT="root:"
+ - export BUILDMAN_PPC="ppc:"
+ - export BUILDMAN_ARM="arm:"
+ - export BUILDMAN_SANDBOX="sandbox:"
+ - echo -e "[toolchain]\n${BUILDMAN_ROOT} /\n" > ~/.buildman
+ - echo -e "${BUILDMAN_PPC} /opt/eldk-5.4/powerpc/sysroots/i686-eldk-linux/usr/bin/powerpc-linux/\n" >> ~/.buildman
+ - echo -e "${BUILDMAN_ARM} /opt/eldk-5.4/armv5te/sysroots/i686-eldk-linux/usr/bin/armv5te-linux-gnueabi/\n" >> ~/.buildman
+ - echo -e "${BUILDMAN_SANDBOX} /usr/bin/gcc\n" >> ~/.buildman
+ - export BUILDMAN_ALIAS="x86:"
+ - export BUILDMAN_ALIAS_ARM="arm:"
+ - echo -e "\n\n[toolchain-alias]\n${BUILDMAN_ALIAS} i386\n" >> ~/.buildman
+ - echo -e "${BUILDMAN_ALIAS_ARM} armv5te\n" >> ~/.buildman
  - cat ~/.buildman
  - virtualenv /tmp/venv
  - . /tmp/venv/bin/activate
  - pip install pytest
- - grub-mkimage -o ~/grub_x86.efi -O i386-efi normal  echo lsefimmap lsefi lsefisystab efinet tftp minicmd
- - mkdir ~/grub2-arm
- - ( cd ~/grub2-arm; wget -O - http://download.opensuse.org/ports/armv7hl/distribution/leap/42.2/repo/oss/suse/armv7hl/grub2-arm-efi-2.02~beta2-87.1.armv7hl.rpm | rpm2cpio | cpio -di )
 
 env:
   global:
-    - PATH=/tmp/dtc:/tmp/qemu-install/bin:/tmp/uboot-test-hooks/bin:$PATH
-    - PYTHONPATH=/tmp/uboot-test-hooks/py/travis-ci
+    - PATH=/tmp/dtc:$PATH
     - BUILD_DIR=build
     - HOSTCC="cc"
     - HOSTCXX="c++"
 
 before_script:
   # install toolchains based on TOOLCHAIN} variable
+  - if [[ "${TOOLCHAIN}" == *aarch64* ]]; then ./tools/buildman/buildman --fetch-arch aarch64 ; fi
+  - if [[ "${TOOLCHAIN}" == *arm* ]]; then wget ftp://ftp.denx.de/pub/eldk/5.4/targets/armv5te/eldk-eglibc-i686-arm-toolchain-gmae-5.4.sh ; fi
+  - if [[ "${TOOLCHAIN}" == *arm* ]]; then sh eldk-eglibc-i686-arm-toolchain-gmae-5.4.sh -y ; fi
   - if [[ "${TOOLCHAIN}" == *avr32* ]]; then ./tools/buildman/buildman --fetch-arch avr32 ; fi
-  - if [[ "${TOOLCHAIN}" == *bfin* ]]; then ./tools/buildman/buildman --fetch-arch bfin ; fi
+  - if [[ "${TOOLCHAIN}" == *i386* ]]; then ./tools/buildman/buildman sandbox --fetch-arch i386 ; fi
   - if [[ "${TOOLCHAIN}" == *m68k* ]]; then ./tools/buildman/buildman --fetch-arch m68k ; fi
-  - if [[ "${TOOLCHAIN}" == *microblaze* ]]; then ./tools/buildman/buildman --fetch-arch microblaze ; fi
   - if [[ "${TOOLCHAIN}" == *mips* ]]; then ./tools/buildman/buildman --fetch-arch mips ; fi
-  - if [[ "${TOOLCHAIN}" == *or32* ]]; then ./tools/buildman/buildman --fetch-arch or32 ; fi
-  - if [[ "${TOOLCHAIN}" == *sh4* ]]; then ./tools/buildman/buildman --fetch-arch sh4 ; fi
-  - if [[ "${TOOLCHAIN}" == *x86_64* ]]; then
-      ./tools/buildman/buildman --fetch-arch x86_64;
-      echo -e "\n[toolchain-prefix]\nx86 = ${HOME}/.buildman-toolchains/gcc-4.9.0-nolibc/x86_64-linux/bin/x86_64-linux-" >> ~/.buildman;
-    fi
-  - if [[ "${TOOLCHAIN}" == *xtensa* ]]; then ./tools/buildman/buildman --fetch-arch xtensa ; fi
-  - if [[ "${QEMU_TARGET}" != "" ]]; then
-       git clone git://git.qemu.org/qemu.git /tmp/qemu;
-       pushd /tmp/qemu;
-       git submodule update --init dtc &&
-       git checkout v2.8.0-rc3 &&
-       ./configure --prefix=/tmp/qemu-install --target-list=${QEMU_TARGET} &&
-       make -j4 all install;
-       popd;
-    fi
+  - if [[ "${TOOLCHAIN}" == *ppc* ]]; then wget ftp://ftp.denx.de/pub/eldk/5.4/targets/powerpc/eldk-eglibc-i686-powerpc-toolchain-gmae-5.4.sh ; fi
+  - if [[ "${TOOLCHAIN}" == *ppc* ]]; then sh eldk-eglibc-i686-powerpc-toolchain-gmae-5.4.sh -y ; fi
 
 script:
- # Comments must be outside the command strings below, or the Travis parser
- # will get confused.
- #
- # Exit code 129 means warnings only.
- - if [[ "${BUILDMAN}" != "" ]]; then
-     set +e;
-     tools/buildman/buildman -P ${BUILDMAN};
-     ret=$?;
-     if [[ $ret -ne 0 && $ret -ne 129 ]]; then
-       tools/buildman/buildman -sdeP ${BUILDMAN};
-       exit $ret;
-     fi;
+ # the execution sequence for each test
+ - if [[ "${TEST_CMD}" != "" ]]; then
+     ${TEST_CMD};
    fi
- # "not a_test_which_does_not_exist" is a dummy -k parameter which will
- # never prevent any test from running. That way, we can always pass
- # "-k something" even when $TEST_PY_TEST_SPEC doesnt need a custom
- # value.
- - export UBOOT_TRAVIS_BUILD_DIR=`cd .. && pwd`/.bm-work/${TEST_PY_BD};
-   cp ~/grub_x86.efi $UBOOT_TRAVIS_BUILD_DIR/;
-   cp ~/grub2-arm/usr/lib/grub2/arm-efi/grub.efi $UBOOT_TRAVIS_BUILD_DIR/grub_arm.efi;
-   if [[ "${TEST_PY_BD}" != "" ]]; then
-     ./test/py/test.py --bd ${TEST_PY_BD} ${TEST_PY_ID}
-       -k "${TEST_PY_TEST_SPEC:-not a_test_which_does_not_exist}"
-       --build-dir "$UBOOT_TRAVIS_BUILD_DIR";
+ - if [[ "${BUILDMAN}" != "" ]]; then
+     tools/buildman/buildman ${BUILDMAN};
    fi
 
 matrix:
@@ -110,207 +77,113 @@ matrix:
   # we need to build by vendor due to 50min time limit for builds
   # each env setting here is a dedicated build
     - env:
-        - BUILDMAN="arm11"
+        - BUILDMAN="arm1136"
+          TOOLCHAIN="arm"
     - env:
-        - BUILDMAN="arm7"
+        - BUILDMAN="arm1136"
+          TOOLCHAIN="arm"
+    - env:
+        - BUILDMAN="arm1176"
+          TOOLCHAIN="arm"
+    - env:
+        - BUILDMAN="arm720t"
+          TOOLCHAIN="arm"
     - env:
         - BUILDMAN="arm920t"
-    - env:
-        - JOB="arm926ejs"
-          BUILDMAN="arm926ejs -x mx,siemens,atmel"
-    - env:
-        - BUILDMAN="arm946es"
+          TOOLCHAIN="arm"
     - env:
         - BUILDMAN="atmel -x avr32"
+          TOOLCHAIN="arm"
     - env:
         - BUILDMAN="avr32"
           TOOLCHAIN="avr32"
+    - env:
+        - BUILDMAN="davinci"
+          TOOLCHAIN="arm"
     - env:
         - BUILDMAN="denx"
+          TOOLCHAIN="arm"
     - env:
-        - JOB="Freescale ARM32"
-          BUILDMAN="freescale -x powerpc,m68k,aarch64"
-    - env:
-        - JOB="Freescale AArch64"
-          BUILDMAN="freescale -x powerpc,m68k,armv7,arm9,arm11"
-    - env:
-        - JOB="i.MX (non-Freescale)"
-          BUILDMAN="mx -x freescale"
-    - env:
-        - BUILDMAN="samsung"
-    - env:
-        - BUILDMAN="sun4i"
-    - env:
-        - BUILDMAN="sun5i"
-    - env:
-        - BUILDMAN="sun6i"
-    - env:
-        - BUILDMAN="sun7i"
-    - env:
-        - BUILDMAN="sun8i"
-    - env:
-        - BUILDMAN="sun9i"
-    - env:
-        - BUILDMAN="sun50i"
-    - env:
-        - JOB="Catch-all ARM"
-          BUILDMAN="arm -x arm11,arm7,arm9,aarch64,atmel,denx,freescale,kirkwood,mvebu,siemens,tegra,uniphier,mx,samsung,sunxi,am33xx,omap3,omap4,omap5,pxa,rockchip"
+        - BUILDMAN="freescale -x powerpc,m68k,aarch64"
+          TOOLCHAIN="arm"
     - env:
         - BUILDMAN="sandbox x86"
-          TOOLCHAIN="x86_64"
+          TOOLCHAIN="i386"
     - env:
         - BUILDMAN="kirkwood"
-    - env:
-        - BUILDMAN="mvebu"
-    - env:
-        - BUILDMAN="pxa"
+          TOOLCHAIN="arm"
     - env:
         - BUILDMAN="m68k"
           TOOLCHAIN="m68k"
-    - env:
-        - BUILDMAN="microblaze"
-          TOOLCHAIN="microblaze"
     - env:
         - BUILDMAN="mips"
           TOOLCHAIN="mips"
     - env:
         - BUILDMAN="mpc512x"
+          TOOLCHAIN="ppc"
     - env:
         - BUILDMAN="mpc5xx"
+          TOOLCHAIN="ppc"
     - env:
         - BUILDMAN="mpc5xxx"
+          TOOLCHAIN="ppc"
     - env:
         - BUILDMAN="mpc8260"
+          TOOLCHAIN="ppc"
     - env:
         - BUILDMAN="mpc83xx"
+          TOOLCHAIN="ppc"
     - env:
         - BUILDMAN="mpc85xx -x freescale"
+          TOOLCHAIN="ppc"
     - env:
         - BUILDMAN="mpc85xx -x t208xrdb -x t4qds -x t102* -x p1_p2_rdb_pc -x p1010rdb -x corenet_ds -x b4860qds -x sbc8548 -x bsc91*"
+          TOOLCHAIN="ppc"
     - env:
         - BUILDMAN="t208xrdb t4qds t102*"
+          TOOLCHAIN="ppc"
     - env:
         - BUILDMAN="p1_p2_rdb_pc p1010rdb"
+          TOOLCHAIN="ppc"
     - env:
         - BUILDMAN="corenet_ds b4860qds sbc8548 bsc91*"
+          TOOLCHAIN="ppc"
     - env:
         - BUILDMAN="mpc86xx"
+          TOOLCHAIN="ppc"
     - env:
         - BUILDMAN="mpc8xx"
+          TOOLCHAIN="ppc"
     - env:
         - BUILDMAN="siemens"
+          TOOLCHAIN="arm"
     - env:
-        - BUILDMAN="tegra"
+        - BUILDMAN="ti"
+          TOOLCHAIN="arm"
     - env:
-        - JOB="am33xx"
-          BUILDMAN="am33xx -x siemens"
-    - env:
-        - BUILDMAN="omap3"
-    - env:
-        - BUILDMAN="omap4"
-    - env:
-        - BUILDMAN="omap5"
-    - env:
-        - BUILDMAN="uniphier"
-    - env:
-        - BUILDMAN="aarch64 -x tegra,freescale,mvebu,uniphier,sunxi,samsung,rockchip"
+        - BUILDMAN="aarch64"
           TOOLCHAIN="aarch64"
-    - env:
-        - BUILDMAN="rockchip"
-    - env:
-        - BUILDMAN="sh4"
-          TOOLCHAIN="sh4"
-    - env:
-        - BUILDMAN="xtensa"
-          TOOLCHAIN="xtensa"
 
     # QA jobs for code analytics
     # static code analysis with cppcheck (we can add --enable=all later)
     - env:
-        - JOB="cppcheck"
-      script:
-        - cppcheck --force --quiet --inline-suppr .
+        - TEST_CMD="cppcheck --force --quiet --inline-suppr ."
     # search for TODO within source tree
     - env:
-        - JOB="grep TODO"
-      script:
-        - grep -r TODO .
+        - TEST_CMD="grep -r TODO ."
     # search for FIXME within source tree
     - env:
-        - JOB="grep FIXME HACK"
-      script:
-        - grep -r FIXME .
+        - TEST_CMD="grep -r FIXME ."
     # search for HACK within source tree and ignore HACKKIT board
+    - env:
+        - TEST_CMD="grep -r HACK . | grep -v HACKKIT"
       script:
         - grep -r HACK . | grep -v HACKKIT
     # some statistics about the code base
     - env:
-        - JOB="sloccount"
-      script:
-        - sloccount .
-
+        - TEST_CMD="sloccount ."
     # test/py
     - env:
-        - TEST_PY_BD="sandbox"
-          BUILDMAN="^sandbox$"
-          TOOLCHAIN="x86_64"
-    - env:
-        - TEST_PY_BD="vexpress_ca15_tc2"
-          TEST_PY_ID="--id qemu"
-          QEMU_TARGET="arm-softmmu"
-          BUILDMAN="^vexpress_ca15_tc2$"
-    - env:
-        - TEST_PY_BD="vexpress_ca9x4"
-          TEST_PY_ID="--id qemu"
-          QEMU_TARGET="arm-softmmu"
-          BUILDMAN="^vexpress_ca9x4$"
-    - env:
-        - TEST_PY_BD="integratorcp_cm926ejs"
-          TEST_PY_TEST_SPEC="not sleep"
-          TEST_PY_ID="--id qemu"
-          QEMU_TARGET="arm-softmmu"
-          BUILDMAN="^integratorcp_cm926ejs$"
-    - env:
-        - TEST_PY_BD="qemu_mips"
-          TEST_PY_TEST_SPEC="not sleep"
-          QEMU_TARGET="mips-softmmu"
-          BUILDMAN="^qemu_mips$"
-          TOOLCHAIN="mips"
-    - env:
-        - TEST_PY_BD="qemu_mipsel"
-          TEST_PY_TEST_SPEC="not sleep"
-          QEMU_TARGET="mipsel-softmmu"
-          BUILDMAN="^qemu_mipsel$"
-          TOOLCHAIN="mips"
-    - env:
-        - TEST_PY_BD="qemu_mips64"
-          TEST_PY_TEST_SPEC="not sleep"
-          QEMU_TARGET="mips64-softmmu"
-          BUILDMAN="^qemu_mips64$"
-          TOOLCHAIN="mips"
-    - env:
-        - TEST_PY_BD="qemu_mips64el"
-          TEST_PY_TEST_SPEC="not sleep"
-          QEMU_TARGET="mips64el-softmmu"
-          BUILDMAN="^qemu_mips64el$"
-          TOOLCHAIN="mips"
-    - env:
-        - TEST_PY_BD="qemu-ppce500"
-          TEST_PY_TEST_SPEC="not sleep"
-          QEMU_TARGET="ppc-softmmu"
-          BUILDMAN="^qemu-ppce500$"
-    - env:
-        - TEST_PY_BD="qemu-x86"
-          TEST_PY_TEST_SPEC="not sleep"
-          QEMU_TARGET="i386-softmmu"
-          BUILDMAN="^qemu-x86$"
-          TOOLCHAIN="x86_64"
-          BUILD_ROM="yes"
-    - env:
-        - TEST_PY_BD="zynq_zc702"
-          TEST_PY_TEST_SPEC="not sleep"
-          QEMU_TARGET="arm-softmmu"
-          TEST_PY_ID="--id qemu"
-          BUILDMAN="^zynq_zc702$"
+        - TEST_CMD="./test/py/test.py --bd sandbox --build"
 
 # TODO make it perfect ;-r

Kconfig

@@ -55,13 +55,11 @@ config CC_OPTIMIZE_FOR_SIZE
 
 config DISTRO_DEFAULTS
 	bool "Select defaults suitable for booting general purpose Linux distributions"
-	default y if ARCH_SUNXI || TEGRA
-	default y if ARCH_LS2080A
+	default y if ARCH_SUNXI
 	default n
 	select CMD_BOOTZ if ARM && !ARM64
 	select CMD_BOOTI if ARM64
 	select CMD_DHCP
-	select CMD_PXE
 	select CMD_EXT2
 	select CMD_EXT4
 	select CMD_FAT
@@ -139,6 +137,74 @@ endmenu		# General setup
 
 menu "Boot images"
 
+config SUPPORT_SPL
+	bool
+
+config SUPPORT_TPL
+	bool
+
+config SPL
+	bool
+	depends on SUPPORT_SPL
+	prompt "Enable SPL"
+	help
+	  If you want to build SPL as well as the normal image, say Y.
+
+config SPL_SYS_MALLOC_SIMPLE
+	bool
+	depends on SPL
+	prompt "Only use malloc_simple functions in the SPL"
+	help
+	  Say Y here to only use the *_simple malloc functions from
+	  malloc_simple.c, rather then using the versions from dlmalloc.c;
+	  this will make the SPL binary smaller at the cost of more heap
+	  usage as the *_simple malloc functions do not re-use free-ed mem.
+
+config SPL_STACK_R
+	depends on SPL
+	bool "Enable SDRAM location for SPL stack"
+	help
+	  SPL starts off execution in SRAM and thus typically has only a small
+	  stack available. Since SPL sets up DRAM while in its board_init_f()
+	  function, it is possible for the stack to move there before
+	  board_init_r() is reached. This option enables a special SDRAM
+	  location for the SPL stack. U-Boot SPL switches to this after
+	  board_init_f() completes, and before board_init_r() starts.
+
+config SPL_STACK_R_ADDR
+	depends on SPL_STACK_R
+	hex "SDRAM location for SPL stack"
+	help
+	  Specify the address in SDRAM for the SPL stack. This will be set up
+	  before board_init_r() is called.
+
+config SPL_STACK_R_MALLOC_SIMPLE_LEN
+	depends on SPL_STACK_R && SPL_SYS_MALLOC_SIMPLE
+	hex "Size of malloc_simple heap after switching to DRAM SPL stack"
+	default 0x100000
+	help
+	  Specify the amount of the stack to use as memory pool for
+	  malloc_simple after switching the stack to DRAM. This may be set
+	  to give board_init_r() a larger heap then the initial heap in
+	  SRAM which is limited to SYS_MALLOC_F_LEN bytes.
+
+config SPL_SEPARATE_BSS
+	depends on SPL
+	bool "BSS section is in a different memory region from text"
+	help
+	  Some platforms need a large BSS region in SPL and can provide this
+	  because RAM is already set up. In this case BSS can be moved to RAM.
+	  This option should then be enabled so that the correct device tree
+	  location is used. Normally we put the device tree at the end of BSS
+	  but with this option enabled, it goes at _image_binary_end.
+
+config TPL
+	bool
+	depends on SPL && SUPPORT_TPL
+	prompt "Enable TPL"
+	help
+	  If you want to build TPL as well as the normal image and SPL, say Y.
+
 config FIT
 	bool "Support Flattened Image Tree"
 	help
@@ -299,8 +365,9 @@ config SYS_CLK_FREQ
 	help
 	  TODO: Move CONFIG_SYS_CLK_FREQ for all the architecture
 
-config ARCH_FIXUP_FDT_MEMORY
-	bool "Enable arch_fixup_memory_banks() call"
+config ARCH_FIXUP_FDT
+	bool "Enable arch_fixup_fdt() call"
+	depends on ARM || MIPS
 	default y
 	help
 	  Enable FDT memory map syncup before OS boot. This feature can be

MAINTAINERS

@@ -69,7 +69,8 @@ ARM ALTERA SOCFPGA
 M:	Marek Vasut <marex@denx.de>
 S:	Maintainted
 T:	git git://git.denx.de/u-boot-socfpga.git
-F:	arch/arm/mach-socfpga/
+F:	arch/arm/cpu/armv7/socfpga/
+F:	board/altera/socfpga/
 
 ARM ATMEL AT91
 M:	Andreas Bießmann <andreas@biessmann.org>
@@ -166,8 +167,9 @@ F:	arch/arm/cpu/armv7/stv0991/
 F:	arch/arm/include/asm/arch-stv0991/
 
 ARM SUNXI
-M:	Jagan Teki <jagan@openedev.com>
-M:	Maxime Ripard <maxime.ripard@free-electrons.com>
+M:	Ian Campbell <ijc@hellion.org.uk>
+M:	Hans De Goede <hdegoede@redhat.com>
+S:	Maintained
 T:	git git://git.denx.de/u-boot-sunxi.git
 F:	arch/arm/cpu/armv7/sunxi/
 F:	arch/arm/include/asm/arch-sunxi/
@@ -242,7 +244,7 @@ T:	git git://git.denx.de/u-boot-coldfire.git
 F:	arch/m68k/
 
 DFU
-M:	Lukasz Majewski <l.majewski@majess.pl>
+M:	Lukasz Majewski <l.majewski@samsung.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-dfu.git
 F:	drivers/dfu/
@@ -271,7 +273,7 @@ F:	lib/fdtdec*
 F:	lib/libfdt/
 F:	include/fdt*
 F:	include/libfdt*
-F:	cmd/fdt.c
+F.	common/cmd_fdt.c
 F:	common/fdt_support.c
 
 FREEBSD
@@ -366,12 +368,6 @@ S:	Maintained
 T:	git git://git.denx.de/u-boot-ppc4xx.git
 F:	arch/powerpc/cpu/ppc4xx/
 
-POWER
-M:	Jaehoon Chung <jh80.chung@samsung.com>
-S:	Maintained
-T:	git git://git.denx.de/u-boot-pmic.git
-F:	drivers/power/
-
 NETWORK
 M:	Joe Hershberger <joe.hershberger@ni.com>
 S:	Maintained
@@ -398,8 +394,8 @@ T:	git git://git.denx.de/u-boot-nios.git
 F:	arch/nios2/
 
 ONENAND
-#M:	Lukasz Majewski <l.majewski@majess.pl>
-S:	Orphaned (Since 2017-01)
+M:	Lukasz Majewski <l.majewski@samsung.com>
+S:	Maintained
 T:	git git://git.denx.de/u-boot-onenand.git
 F:	drivers/mtd/onenand/
 
@@ -421,7 +417,7 @@ T:	git git://git.denx.de/u-boot-sparc.git
 F:	arch/sparc/
 
 SPI
-M:	Jagan Teki <jagan@openedev.com>
+M:	Jagan Teki <jteki@openedev.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-spi.git
 F:	drivers/mtd/spi/

Makefile

@@ -2,9 +2,9 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-VERSION = 2017
-PATCHLEVEL = 01
-SUBLEVEL =
+VERSION = 2016
+PATCHLEVEL = 09
+SUBLEVEL = 01
 EXTRAVERSION =
 NAME =
 
@@ -527,15 +527,6 @@ endif
 endif
 endif
 
-# These are set by the arch-specific config.mk. Make sure they are exported
-# so they can be used when building an EFI application.
-export EFI_LDS		# Filename of EFI link script in arch/$(ARCH)/lib
-export EFI_CRT0		# Filename of EFI CRT0 in arch/$(ARCH)/lib
-export EFI_RELOC	# Filename of EFU relocation code in arch/$(ARCH)/lib
-export CFLAGS_EFI	# Compiler flags to add when building EFI app
-export CFLAGS_NON_EFI	# Compiler flags to remove when building EFI app
-export EFI_TARGET	# binutils target if EFI is natively supported
-
 # If board code explicitly specified LDSCRIPT or CONFIG_SYS_LDSCRIPT, use
 # that (or fail if absent).  Otherwise, search for a linker script in a
 # standard location.
@@ -664,7 +655,6 @@ libs-y += drivers/power/ \
 libs-y += drivers/spi/
 libs-$(CONFIG_FMAN_ENET) += drivers/net/fm/
 libs-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/
-libs-$(CONFIG_SYS_FSL_MMDC) += drivers/ddr/fsl/
 libs-$(CONFIG_ALTERA_SDRAM) += drivers/ddr/altera/
 libs-y += drivers/serial/
 libs-y += drivers/usb/dwc3/
@@ -750,7 +740,7 @@ DO_STATIC_RELA =
 endif
 
 # Always append ALL so that arch config.mk's can add custom ones
-ALL-y += u-boot.srec u-boot.bin u-boot.sym System.map binary_size_check
+ALL-y += u-boot.srec u-boot.bin u-boot.sym System.map u-boot.cfg binary_size_check
 
 ALL-$(CONFIG_ONENAND_U_BOOT) += u-boot-onenand.bin
 ifeq ($(CONFIG_SPL_FSL_PBL),y)
@@ -763,11 +753,7 @@ ALL-$(CONFIG_RAMBOOT_PBL) += u-boot.pbl
 endif
 endif
 ALL-$(CONFIG_SPL) += spl/u-boot-spl.bin
-ifeq ($(CONFIG_MX6)$(CONFIG_SECURE_BOOT), yy)
-ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot-ivt.img
-else
 ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.img
-endif
 ALL-$(CONFIG_TPL) += tpl/u-boot-tpl.bin
 ALL-$(CONFIG_OF_SEPARATE) += u-boot.dtb
 ifeq ($(CONFIG_SPL_FRAMEWORK),y)
@@ -813,11 +799,9 @@ cmd_zobjcopy = $(OBJCOPY) $(OBJCOPYFLAGS) $(OBJCOPYFLAGS_$(@F)) $< $@
 quiet_cmd_efipayload = OBJCOPY $@
 cmd_efipayload = $(OBJCOPY) -I binary -O $(EFIPAYLOAD_BFDTARGET) -B $(EFIPAYLOAD_BFDARCH) $< $@
 
-MKIMAGEOUTPUT ?= /dev/null
-
 quiet_cmd_mkimage = MKIMAGE $@
 cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
-	$(if $(KBUILD_VERBOSE:1=), >$(MKIMAGEOUTPUT))
+	$(if $(KBUILD_VERBOSE:1=), >/dev/null)
 
 quiet_cmd_cat = CAT     $@
 cmd_cat = cat $(filter-out $(PHONY), $^) > $@
@@ -827,8 +811,6 @@ append = cat $(filter-out $< $(PHONY), $^) >> $@
 quiet_cmd_pad_cat = CAT     $@
 cmd_pad_cat = $(cmd_objcopy) && $(append) || rm -f $@
 
-cfg: u-boot.cfg
-
 all:		$(ALL-y)
 ifeq ($(CONFIG_DM_I2C_COMPAT)$(CONFIG_SANDBOX),y)
 	@echo "===================== WARNING ======================"
@@ -837,11 +819,6 @@ ifeq ($(CONFIG_DM_I2C_COMPAT)$(CONFIG_SANDBOX),y)
 	@echo "before sending patches to the mailing list."
 	@echo "===================================================="
 endif
-	@# Check that this build does not use CONFIG options that we do not
-	@# know about unless they are in Kconfig. All the existing CONFIG
-	@# options are whitelisted, so new ones should not be added.
-	$(srctree)/scripts/check-config.sh u-boot.cfg \
-		$(srctree)/scripts/config_whitelist.txt ${srctree} 1>&2
 
 PHONY += dtbs
 dtbs: dts/dt.dtb
@@ -866,12 +843,6 @@ endif
 %.imx: %.bin
 	$(Q)$(MAKE) $(build)=arch/arm/imx-common $@
 
-%.vyb: %.imx
-	$(Q)$(MAKE) $(build)=arch/arm/cpu/armv7/vf610 $@
-
-quiet_cmd_copy = COPY    $@
-      cmd_copy = cp $< $@
-
 u-boot.dtb: dts/dt.dtb
 	$(call cmd,copy)
 
@@ -909,12 +880,6 @@ u-boot.ldr:	u-boot
 		$(LDR) -T $(CONFIG_CPU) -c $@ $< $(LDR_FLAGS)
 		$(BOARD_SIZE_CHECK)
 
-# binman
-# ---------------------------------------------------------------------------
-quiet_cmd_binman = BINMAN  $@
-cmd_binman = $(srctree)/tools/binman/binman -d u-boot.dtb -O . \
-		-I . -I $(srctree)/board/$(BOARDDIR) $<
-
 OBJCOPYFLAGS_u-boot.ldr.hex := -I binary -O ihex
 
 OBJCOPYFLAGS_u-boot.ldr.srec := -I binary -O srec
@@ -944,11 +909,6 @@ else
 MKIMAGEFLAGS_u-boot.img = -A $(ARCH) -T firmware -C none -O u-boot \
 	-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
 	-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board"
-MKIMAGEFLAGS_u-boot-ivt.img = -A $(ARCH) -T firmware_ivt -C none -O u-boot \
-	-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
-	-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board"
-u-boot-ivt.img: MKIMAGEOUTPUT = u-boot-ivt.img.log
-CLEAN_FILES += u-boot-ivt.img.log u-boot-dtb.imx.log SPL.log u-boot.imx.log
 endif
 
 MKIMAGEFLAGS_u-boot-dtb.img = $(MKIMAGEFLAGS_u-boot.img)
@@ -962,7 +922,7 @@ MKIMAGEFLAGS_u-boot-spl.kwb = -n $(srctree)/$(CONFIG_SYS_KWD_CONFIG:"%"=%) \
 MKIMAGEFLAGS_u-boot.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \
 		-R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage
 
-u-boot-dtb.img u-boot.img u-boot.kwb u-boot.pbl u-boot-ivt.img: \
+u-boot-dtb.img u-boot.img u-boot.kwb u-boot.pbl: \
 		$(if $(CONFIG_SPL_LOAD_FIT),u-boot-nodtb.bin dts/dt.dtb,u-boot.bin) FORCE
 	$(call if_changed,mkimage)
 
@@ -975,6 +935,9 @@ u-boot.sha1:	u-boot.bin
 u-boot.dis:	u-boot
 		$(OBJDUMP) -d $< > $@
 
+u-boot.cfg:	include/config.h FORCE
+	$(call if_changed,cpp_cfg)
+
 ifdef CONFIG_TPL
 SPL_PAYLOAD := tpl/u-boot-with-tpl.bin
 else
@@ -1064,11 +1027,50 @@ endif
 
 # x86 uses a large ROM. We fill it with 0xff, put the 16-bit stuff (including
 # reset vector) at the top, Intel ME descriptor at the bottom, and U-Boot in
-# the middle. This is handled by binman based on an image description in the
-# board's device tree.
+# the middle.
 ifneq ($(CONFIG_X86_RESET_VECTOR),)
 rom: u-boot.rom FORCE
 
+IFDTOOL=$(objtree)/tools/ifdtool
+IFDTOOL_FLAGS  = -f 0:$(objtree)/u-boot.dtb
+IFDTOOL_FLAGS += -m 0x$(shell $(NM) u-boot |grep _dt_ucode_base_size |cut -d' ' -f1)
+IFDTOOL_FLAGS += -U $(CONFIG_SYS_TEXT_BASE):$(objtree)/u-boot-nodtb.bin
+IFDTOOL_FLAGS += -w $(CONFIG_SYS_X86_START16):$(objtree)/u-boot-x86-16bit.bin
+IFDTOOL_FLAGS += -C
+
+ifneq ($(CONFIG_HAVE_INTEL_ME),)
+IFDTOOL_ME_FLAGS  = -D $(srctree)/board/$(BOARDDIR)/descriptor.bin
+IFDTOOL_ME_FLAGS += -i ME:$(srctree)/board/$(BOARDDIR)/me.bin
+endif
+
+ifneq ($(CONFIG_HAVE_MRC),)
+IFDTOOL_FLAGS += -w $(CONFIG_X86_MRC_ADDR):$(srctree)/board/$(BOARDDIR)/mrc.bin
+endif
+
+ifneq ($(CONFIG_HAVE_FSP),)
+IFDTOOL_FLAGS += -w $(CONFIG_FSP_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_FSP_FILE)
+endif
+
+ifneq ($(CONFIG_HAVE_CMC),)
+IFDTOOL_FLAGS += -w $(CONFIG_CMC_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_CMC_FILE)
+endif
+
+ifneq ($(CONFIG_HAVE_VGA_BIOS),)
+IFDTOOL_FLAGS += -w $(CONFIG_VGA_BIOS_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_VGA_BIOS_FILE)
+endif
+
+ifneq ($(CONFIG_HAVE_REFCODE),)
+IFDTOOL_FLAGS += -w $(CONFIG_X86_REFCODE_ADDR):refcode.bin
+endif
+
+quiet_cmd_ifdtool = IFDTOOL $@
+cmd_ifdtool  = $(IFDTOOL) -c -r $(CONFIG_ROM_SIZE) u-boot.tmp;
+ifneq ($(CONFIG_HAVE_INTEL_ME),)
+cmd_ifdtool += $(IFDTOOL) $(IFDTOOL_ME_FLAGS) u-boot.tmp;
+endif
+cmd_ifdtool += $(IFDTOOL) $(IFDTOOL_FLAGS) u-boot.tmp;
+cmd_ifdtool += mv u-boot.tmp $@
+
 refcode.bin: $(srctree)/board/$(BOARDDIR)/refcode.bin FORCE
 	$(call if_changed,copy)
 
@@ -1078,16 +1080,18 @@ cmd_ldr = $(LD) $(LDFLAGS_$(@F)) \
 
 u-boot.rom: u-boot-x86-16bit.bin u-boot.bin FORCE \
 		$(if $(CONFIG_HAVE_REFCODE),refcode.bin)
-	$(call if_changed,binman)
+	$(call if_changed,ifdtool)
 
 OBJCOPYFLAGS_u-boot-x86-16bit.bin := -O binary -j .start16 -j .resetvec
 u-boot-x86-16bit.bin: u-boot FORCE
 	$(call if_changed,objcopy)
 endif
 
-ifneq ($(CONFIG_ARCH_SUNXI),)
-u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.img u-boot.dtb FORCE
-	$(call if_changed,binman)
+ifneq ($(CONFIG_SUNXI),)
+OBJCOPYFLAGS_u-boot-sunxi-with-spl.bin = -I binary -O binary \
+				   --pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff
+u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.img FORCE
+	$(call if_changed,pad_cat)
 endif
 
 ifneq ($(CONFIG_TEGRA),)
@@ -1118,7 +1122,7 @@ quiet_cmd_u-boot_payload ?= LD      $@
       cmd_u-boot_payload ?= $(LD) $(LDFLAGS_EFI_PAYLOAD) -o $@ \
       -T u-boot-payload.lds arch/x86/cpu/call32.o \
       lib/efi/efi.o lib/efi/efi_stub.o u-boot.bin.o \
-      $(addprefix arch/$(ARCH)/lib/,$(EFISTUB))
+      $(addprefix arch/$(ARCH)/lib/efi/,$(EFISTUB))
 
 u-boot-payload: u-boot.bin.o u-boot-payload.lds FORCE
 	$(call if_changed,u-boot_payload)
@@ -1505,7 +1509,6 @@ help:
 	@echo  '  cscope	  - Generate cscope index'
 	@echo  '  ubootrelease	  - Output the release version string (use with make -s)'
 	@echo  '  ubootversion	  - Output the version stored in Makefile (use with make -s)'
-	@echo  "  cfg		  - Don't build, just create the .cfg files"
 	@echo  ''
 	@echo  'Static analysers'
 	@echo  '  checkstack      - Generate a list of stack hogs'

README

@@ -127,7 +127,7 @@ releases in "stable" maintenance trees.
 Examples:
 	U-Boot v2009.11	    - Release November 2009
 	U-Boot v2009.11.1   - Release 1 in version November 2009 stable tree
-	U-Boot v2010.09-rc1 - Release candidate 1 for September 2010 release
+	U-Boot v2010.09-rc1 - Release candiate 1 for September 2010 release
 
 
 Directory Hierarchy:
@@ -325,6 +325,27 @@ The following options need to be configured:
 - CPU Daughterboard Type: (if CONFIG_ATSTK1000 is defined)
 		Define exactly one, e.g. CONFIG_ATSTK1002
 
+- CPU Module Type: (if CONFIG_COGENT is defined)
+		Define exactly one of
+		CONFIG_CMA286_60_OLD
+--- FIXME --- not tested yet:
+		CONFIG_CMA286_60, CONFIG_CMA286_21, CONFIG_CMA286_60P,
+		CONFIG_CMA287_23, CONFIG_CMA287_50
+
+- Motherboard Type: (if CONFIG_COGENT is defined)
+		Define exactly one of
+		CONFIG_CMA101, CONFIG_CMA102
+
+- Motherboard I/O Modules: (if CONFIG_COGENT is defined)
+		Define one or more of
+		CONFIG_CMA302
+
+- Motherboard Options: (if CONFIG_CMA101 or CONFIG_CMA102 are defined)
+		Define one or more of
+		CONFIG_LCD_HEARTBEAT	- update a character position on
+					  the LCD display every second with
+					  a "rotator" |\-/|\-/
+
 - Marvell Family Member
 		CONFIG_SYS_MVFS		- define it if you want to enable
 					  multiple fs option at one time
@@ -376,6 +397,15 @@ The following options need to be configured:
 		Defines the string to utilize when trying to match PCIe device
 		tree nodes for the given platform.
 
+		CONFIG_SYS_PPC_E500_DEBUG_TLB
+
+		Enables a temporary TLB entry to be used during boot to work
+		around limitations in e500v1 and e500v2 external debugger
+		support. This reduces the portions of the boot code where
+		breakpoints and single stepping do not work.  The value of this
+		symbol should be set to the TLB1 entry to be used for this
+		purpose.
+
 		CONFIG_SYS_FSL_ERRATUM_A004510
 
 		Enables a workaround for erratum A004510.  If set,
@@ -548,6 +578,20 @@ The following options need to be configured:
 		CONFIG_SYS_FSL_SEC_LE
 		Defines the SEC controller register space as Little Endian
 
+- Intel Monahans options:
+		CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
+
+		Defines the Monahans run mode to oscillator
+		ratio. Valid values are 8, 16, 24, 31. The core
+		frequency is this value multiplied by 13 MHz.
+
+		CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO
+
+		Defines the Monahans turbo mode to oscillator
+		ratio. Valid values are 1 (default if undefined) and
+		2. The core frequency as calculated above is multiplied
+		by this value.
+
 - MIPS CPU options:
 		CONFIG_SYS_INIT_SP_OFFSET
 
@@ -686,6 +730,11 @@ The following options need to be configured:
 		This causes ft_system_setup() to be called before booting
 		the kernel.
 
+		CONFIG_OF_BOOT_CPU
+
+		This define fills in the correct boot CPU in the boot
+		param header, the default value is zero if undefined.
+
 		CONFIG_OF_IDE_FIXUP
 
 		U-Boot can detect if an IDE device is present or not.
@@ -761,6 +810,59 @@ The following options need to be configured:
 		port routines must be defined elsewhere
 		(i.e. serial_init(), serial_getc(), ...)
 
+		CONFIG_CFB_CONSOLE
+		Enables console device for a color framebuffer. Needs following
+		defines (cf. smiLynxEM, i8042)
+			VIDEO_FB_LITTLE_ENDIAN	graphic memory organisation
+						(default big endian)
+			VIDEO_HW_RECTFILL	graphic chip supports
+						rectangle fill
+						(cf. smiLynxEM)
+			VIDEO_HW_BITBLT		graphic chip supports
+						bit-blit (cf. smiLynxEM)
+			VIDEO_VISIBLE_COLS	visible pixel columns
+						(cols=pitch)
+			VIDEO_VISIBLE_ROWS	visible pixel rows
+			VIDEO_PIXEL_SIZE	bytes per pixel
+			VIDEO_DATA_FORMAT	graphic data format
+						(0-5, cf. cfb_console.c)
+			VIDEO_FB_ADRS		framebuffer address
+			VIDEO_KBD_INIT_FCT	keyboard int fct
+						(i.e. rx51_kp_init())
+			VIDEO_TSTC_FCT		test char fct
+						(i.e. rx51_kp_tstc)
+			VIDEO_GETC_FCT		get char fct
+						(i.e. rx51_kp_getc)
+			CONFIG_VIDEO_LOGO	display Linux logo in
+						upper left corner
+			CONFIG_VIDEO_BMP_LOGO	use bmp_logo.h instead of
+						linux_logo.h for logo.
+						Requires CONFIG_VIDEO_LOGO
+			CONFIG_CONSOLE_EXTRA_INFO
+						additional board info beside
+						the logo
+			CONFIG_HIDE_LOGO_VERSION
+						do not display bootloader
+						version string
+
+		When CONFIG_CFB_CONSOLE_ANSI is defined, console will support
+		a limited number of ANSI escape sequences (cursor control,
+		erase functions and limited graphics rendition control).
+
+		When CONFIG_CFB_CONSOLE is defined, video console is
+		default i/o. Serial console can be forced with
+		environment 'console=serial'.
+
+		When CONFIG_SILENT_CONSOLE is defined, all console
+		messages (by U-Boot and Linux!) can be silenced with
+		the "silent" environment variable. See
+		doc/README.silent for more information.
+
+		CONFIG_SYS_CONSOLE_BG_COL: define the backgroundcolor, default
+			is 0x00.
+		CONFIG_SYS_CONSOLE_FG_COL: define the foregroundcolor, default
+			is 0xa0.
+
 - Console Baudrate:
 		CONFIG_BAUDRATE - in bps
 		Select one of the baudrates listed in
@@ -775,6 +877,23 @@ The following options need to be configured:
 		must be defined, to setup the maximum idle timeout for
 		the SMC.
 
+- Pre-Console Buffer:
+		Prior to the console being initialised (i.e. serial UART
+		initialised etc) all console output is silently discarded.
+		Defining CONFIG_PRE_CONSOLE_BUFFER will cause U-Boot to
+		buffer any console messages prior to the console being
+		initialised to a buffer of size CONFIG_PRE_CON_BUF_SZ
+		bytes located at CONFIG_PRE_CON_BUF_ADDR. The buffer is
+		a circular buffer, so if more than CONFIG_PRE_CON_BUF_SZ
+		bytes are output before the console is initialised, the
+		earlier bytes are discarded.
+
+		Note that when printing the buffer a copy is made on the
+		stack so CONFIG_PRE_CON_BUF_SZ must fit on the stack.
+
+		'Sane' compilers will generate smaller code if
+		CONFIG_PRE_CON_BUF_SZ is a power of 2
+
 - Autoboot Command:
 		CONFIG_BOOTCOMMAND
 		Only needed when CONFIG_BOOTDELAY is enabled;
@@ -1218,6 +1337,10 @@ The following options need to be configured:
 		CONFIG_LAN91C96
 		Support for SMSC's LAN91C96 chips.
 
+			CONFIG_LAN91C96_BASE
+			Define this to hold the physical address
+			of the LAN91C96's I/O space
+
 			CONFIG_LAN91C96_USE_32_BIT
 			Define this to enable 32 bit addressing
 
@@ -1282,7 +1405,7 @@ The following options need to be configured:
 
 - PWM Support:
 		CONFIG_PWM_IMX
-		Support for PWM module on the imx6.
+		Support for PWM modul on the imx6.
 
 - TPM Support:
 		CONFIG_TPM
@@ -1402,6 +1525,10 @@ The following options need to be configured:
 				Derive USB clock from external clock "blah"
 				- CONFIG_SYS_USB_EXTC_CLK 0x02
 
+				CONFIG_SYS_USB_BRG_CLK 0xBLAH
+				Derive USB clock from brgclk
+				- CONFIG_SYS_USB_BRG_CLK 0x04
+
 		If you have a USB-IF assigned VendorID then you may wish to
 		define your own vendor specific values either in BoardName.h
 		or directly in usbd_vendor_info.h. If you don't define
@@ -1554,23 +1681,26 @@ The following options need to be configured:
 		to generate and write the Backup GUID Partition Table.)
 		This occurs when the specified "partition name" on the
 		"fastboot flash" command line matches this value.
-		The default is "gpt" if undefined.
-
-		CONFIG_FASTBOOT_MBR_NAME
-		The fastboot "flash" command supports writing the downloaded
-		image to DOS MBR.
-		This occurs when the "partition name" specified on the
-		"fastboot flash" command line matches this value.
-		If not defined the default value "mbr" is used.
+		Default is GPT_ENTRY_NAME (currently "gpt") if undefined.
 
 - Journaling Flash filesystem support:
-		CONFIG_JFFS2_NAND
+		CONFIG_JFFS2_NAND, CONFIG_JFFS2_NAND_OFF, CONFIG_JFFS2_NAND_SIZE,
+		CONFIG_JFFS2_NAND_DEV
 		Define these for a default partition on a NAND device
 
 		CONFIG_SYS_JFFS2_FIRST_SECTOR,
 		CONFIG_SYS_JFFS2_FIRST_BANK, CONFIG_SYS_JFFS2_NUM_BANKS
 		Define these for a default partition on a NOR device
 
+		CONFIG_SYS_JFFS_CUSTOM_PART
+		Define this to create an own partition. You have to provide a
+		function struct part_info* jffs2_part_info(int part_num)
+
+		If you define only one JFFS2 partition you may also want to
+		#define CONFIG_SYS_JFFS_SINGLE_PART	1
+		to disable the command chpart. This is the default when you
+		have not defined a custom partition
+
 - FAT(File Allocation Table) filesystem write function support:
 		CONFIG_FAT_WRITE
 
@@ -1580,7 +1710,7 @@ The following options need to be configured:
 		This will also enable the command "fatwrite" enabling the
 		user to write files to FAT.
 
-- CBFS (Coreboot Filesystem) support:
+CBFS (Coreboot Filesystem) support
 		CONFIG_CMD_CBFS
 
 		Define this to enable support for reading from a Coreboot
@@ -1605,6 +1735,45 @@ The following options need to be configured:
 		instead.
 
 - Video support:
+		CONFIG_VIDEO
+
+		Define this to enable video support (for output to
+		video).
+
+		CONFIG_VIDEO_CT69000
+
+		Enable Chips & Technologies 69000 Video chip
+
+		CONFIG_VIDEO_SMI_LYNXEM
+		Enable Silicon Motion SMI 712/710/810 Video chip. The
+		video output is selected via environment 'videoout'
+		(1 = LCD and 2 = CRT). If videoout is undefined, CRT is
+		assumed.
+
+		For the CT69000 and SMI_LYNXEM drivers, videomode is
+		selected via environment 'videomode'. Two different ways
+		are possible:
+		- "videomode=num"   'num' is a standard LiLo mode numbers.
+		Following standard modes are supported	(* is default):
+
+		      Colors	640x480 800x600 1024x768 1152x864 1280x1024
+		-------------+---------------------------------------------
+		      8 bits |	0x301*	0x303	 0x305	  0x161	    0x307
+		     15 bits |	0x310	0x313	 0x316	  0x162	    0x319
+		     16 bits |	0x311	0x314	 0x317	  0x163	    0x31A
+		     24 bits |	0x312	0x315	 0x318	    ?	    0x31B
+		-------------+---------------------------------------------
+		(i.e. setenv videomode 317; saveenv; reset;)
+
+		- "videomode=bootargs" all the video parameters are parsed
+		from the bootargs. (See drivers/video/videomodes.c)
+
+
+		CONFIG_VIDEO_SED13806
+		Enable Epson SED13806 driver. This driver supports 8bpp
+		and 16bpp modes defined by CONFIG_VIDEO_SED13806_8BPP
+		or CONFIG_VIDEO_SED13806_16BPP
+
 		CONFIG_FSL_DIU_FB
 		Enable the Freescale DIU video driver.	Reference boards for
 		SOCs that have a DIU should define this macro to enable DIU
@@ -1684,6 +1853,12 @@ The following options need to be configured:
 		here, since it is cheaper to change data cache settings on
 		a per-section basis.
 
+		CONFIG_CONSOLE_SCROLL_LINES
+
+		When the console need to be scrolled, this is the number of
+		lines to scroll by. It defaults to 1. Increasing this makes
+		the console jump but can help speed up operation when scrolling
+		is slow.
 
 		CONFIG_LCD_ROTATION
 
@@ -2156,6 +2331,8 @@ The following options need to be configured:
 		  - CONFIG_SYS_I2C_SH_SPEED3 for for the speed channel 3
 		  - CONFIG_SYS_I2C_SH_BASE4 for setting the register channel 4
 		  - CONFIG_SYS_I2C_SH_SPEED4 for for the speed channel 4
+		  - CONFIG_SYS_I2C_SH_BASE5 for setting the register channel 5
+		  - CONFIG_SYS_I2C_SH_SPEED5 for for the speed channel 5
 		  - CONFIG_SYS_I2C_SH_NUM_CONTROLLERS for number of i2c buses
 
 		- drivers/i2c/omap24xx_i2c.c
@@ -2209,7 +2386,10 @@ The following options need to be configured:
 		additional defines:
 
 		CONFIG_SYS_NUM_I2C_BUSES
-		Hold the number of i2c buses you want to use.
+		Hold the number of i2c buses you want to use. If you
+		don't use/have i2c muxes on your i2c bus, this
+		is equal to CONFIG_SYS_NUM_I2C_ADAPTERS, and you can
+		omit this define.
 
 		CONFIG_SYS_I2C_DIRECT_BUS
 		define this, if you don't use i2c muxes on your hardware.
@@ -2423,7 +2603,7 @@ The following options need to be configured:
 		will skip addresses 0x50 and 0x68 on a board with one I2C bus
 
 			#define CONFIG_I2C_MULTI_BUS
-			#define CONFIG_SYS_I2C_NOPROBES	{{0,0x50},{0,0x68},{1,0x54}}
+			#define CONFIG_SYS_I2C_MULTI_NOPROBES	{{0,0x50},{0,0x68},{1,0x54}}
 
 		will skip addresses 0x50 and 0x68 on bus 0 and address 0x54 on bus 1
 
@@ -3329,6 +3509,26 @@ FIT uImage format:
 		CONFIG_SPL_INIT_MINIMAL
 		Arch init code should be built for a very small image
 
+		CONFIG_SPL_LIBCOMMON_SUPPORT
+		Support for common/libcommon.o in SPL binary
+
+		CONFIG_SPL_LIBDISK_SUPPORT
+		Support for disk/libdisk.o in SPL binary
+
+		CONFIG_SPL_I2C_SUPPORT
+		Support for drivers/i2c/libi2c.o in SPL binary
+
+		CONFIG_SPL_GPIO_SUPPORT
+		Support for drivers/gpio/libgpio.o in SPL binary
+
+		CONFIG_SPL_MMC_SUPPORT
+		Support for drivers/mmc/libmmc.o in SPL binary
+
+		CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR,
+		CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS,
+		Address and partition on the MMC to load U-Boot from
+		when the MMC is being used in raw mode.
+
 		CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
 		Partition on the MMC to load U-Boot from when the MMC is being
 		used in raw mode
@@ -3347,6 +3547,12 @@ FIT uImage format:
 		Partition on the MMC to load U-Boot from when the MMC is being
 		used in fs mode
 
+		CONFIG_SPL_FAT_SUPPORT
+		Support for fs/fat/libfat.o in SPL binary
+
+		CONFIG_SPL_EXT_SUPPORT
+		Support for EXT filesystem in SPL binary
+
 		CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
 		Filename to read to load U-Boot when reading from filesystem
 
@@ -3385,10 +3591,18 @@ FIT uImage format:
 		Support for a lightweight UBI (fastmap) scanner and
 		loader
 
+		CONFIG_SPL_MTD_SUPPORT
+		Support for the MTD subsystem within SPL.  Useful for
+		environment on NAND support within SPL.
+
 		CONFIG_SPL_NAND_RAW_ONLY
 		Support to boot only raw u-boot.bin images. Use this only
 		if you need to save space.
 
+		CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+		Set for the SPL on PPC mpc8xxx targets, support for
+		drivers/ddr/fsl/libddr.o in SPL binary.
+
 		CONFIG_SPL_COMMON_INIT_DDR
 		Set for common ddr init with serial presence detect in
 		SPL binary.
@@ -3424,9 +3638,29 @@ FIT uImage format:
 		Support for an OMAP3-specific set of functions to return the
 		ID and MFR of the first attached NAND chip, if present.
 
+		CONFIG_SPL_SERIAL_SUPPORT
+		Support for drivers/serial/libserial.o in SPL binary
+
+		CONFIG_SPL_SPI_FLASH_SUPPORT
+		Support for drivers/mtd/spi/libspi_flash.o in SPL binary
+
+		CONFIG_SPL_SPI_SUPPORT
+		Support for drivers/spi/libspi.o in SPL binary
+
 		CONFIG_SPL_RAM_DEVICE
 		Support for running image already present in ram, in SPL binary
 
+		CONFIG_SPL_LIBGENERIC_SUPPORT
+		Support for lib/libgeneric.o in SPL binary
+
+		CONFIG_SPL_ENV_SUPPORT
+		Support for the environment operating in SPL binary
+
+		CONFIG_SPL_NET_SUPPORT
+		Support for the net/libnet.o in SPL binary.
+		It conflicts with SPL env from storage medium specified by
+		CONFIG_ENV_IS_xxx but CONFIG_ENV_IS_NOWHERE
+
 		CONFIG_SPL_PAD_TO
 		Image offset to which the SPL should be padded before appending
 		the SPL payload. By default, this is defined as
@@ -3513,6 +3747,21 @@ Configuration Settings:
 - CONFIG_SYS_BAUDRATE_TABLE:
 		List of legal baudrate settings for this board.
 
+- CONFIG_SYS_CONSOLE_INFO_QUIET
+		Suppress display of console information at boot.
+
+- CONFIG_SYS_CONSOLE_IS_IN_ENV
+		If the board specific function
+			extern int overwrite_console (void);
+		returns 1, the stdin, stderr and stdout are switched to the
+		serial port, else the settings in the environment are used.
+
+- CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+		Enable the call to overwrite_console().
+
+- CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+		Enable overwrite of previous console environment settings.
+
 - CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END:
 		Begin and End addresses of the area used by the
 		simple memory test.
@@ -3560,6 +3809,10 @@ Configuration Settings:
 - CONFIG_SYS_SDRAM_BASE:
 		Physical start address of SDRAM. _Must_ be 0 here.
 
+- CONFIG_SYS_MBIO_BASE:
+		Physical start address of Motherboard I/O (if using a
+		Cogent motherboard)
+
 - CONFIG_SYS_FLASH_BASE:
 		Physical start address of Flash memory.
 
@@ -3991,7 +4244,7 @@ to save the current settings.
 	  This setting describes a second storage area of CONFIG_ENV_SIZE
 	  size used to hold a redundant copy of the environment data, so
 	  that there is a valid backup copy in case there is a power failure
-	  during a "saveenv" operation. CONFIG_ENV_OFFSET_REDUND must be
+	  during a "saveenv" operation. CONFIG_ENV_OFFSET_RENDUND must be
 	  aligned to an erase sector boundary.
 
 	- CONFIG_ENV_SPI_BUS (optional):
@@ -4042,7 +4295,7 @@ but it can not erase, write this NOR flash by SRIO or PCIE interface.
 	  This setting describes a second storage area of CONFIG_ENV_SIZE
 	  size used to hold a redundant copy of the environment data, so
 	  that there is a valid backup copy in case there is a power failure
-	  during a "saveenv" operation.	 CONFIG_ENV_OFFSET_REDUND must be
+	  during a "saveenv" operation.	 CONFIG_ENV_OFFSET_RENDUND must be
 	  aligned to an erase block boundary.
 
 	- CONFIG_ENV_RANGE (optional):
@@ -4101,7 +4354,7 @@ but it can not erase, write this NOR flash by SRIO or PCIE interface.
 
          Define this to a string that is the name of the block device.
 
-       - FAT_ENV_DEVICE_AND_PART:
+       - FAT_ENV_DEV_AND_PART:
 
          Define this to a string to specify the partition of the device. It can
          be as following:
@@ -4343,7 +4596,7 @@ Low Level (hardware related) configuration options:
 		CONFIG_SYS_GBL_DATA_OFFSET is chosen such that the initial
 		data is located at the end of the available space
 		(sometimes written as (CONFIG_SYS_INIT_RAM_SIZE -
-		GENERATED_GBL_DATA_SIZE), and the initial stack is just
+		CONFIG_SYS_INIT_DATA_SIZE), and the initial stack is just
 		below that area (growing from (CONFIG_SYS_INIT_RAM_ADDR +
 		CONFIG_SYS_GBL_DATA_OFFSET) downward.
 
@@ -4402,6 +4655,11 @@ Low Level (hardware related) configuration options:
 		enable SPI microcode relocation patch (MPC8xx);
 		define relocation offset in DPRAM [SCC4]
 
+- CONFIG_SYS_USE_OSCCLK:
+		Use OSCM clock mode on MBX8xx board. Be careful,
+		wrong setting might damage your board. Read
+		doc/README.MBX before setting this variable!
+
 - CONFIG_SYS_CPM_POST_WORD_ADDR: (MPC8xx, MPC8260 only)
 		Offset of the bootmode word in DPRAM used by post
 		(Power On Self Tests). This definition overrides
@@ -4584,6 +4842,12 @@ Low Level (hardware related) configuration options:
 		addressable memory. This option causes some memory accesses
 		to be mapped through map_sysmem() / unmap_sysmem().
 
+- CONFIG_USE_ARCH_MEMCPY
+  CONFIG_USE_ARCH_MEMSET
+		If these options are used a optimized version of memcpy/memset will
+		be used if available. These functions may be faster under some
+		conditions but may increase the binary size.
+
 - CONFIG_X86_RESET_VECTOR
 		If defined, the x86 reset vector code is included. This is not
 		needed when U-Boot is running from Coreboot.
@@ -4639,6 +4903,10 @@ within that device.
 	Specifies that QE/FMAN firmware is located on the primary SD/MMC
 	device.  CONFIG_SYS_FMAN_FW_ADDR is the byte offset on that device.
 
+- CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH
+	Specifies that QE/FMAN firmware is located on the primary SPI
+	device.  CONFIG_SYS_FMAN_FW_ADDR is the byte offset on that device.
+
 - CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 	Specifies that QE/FMAN firmware is located in the remote (master)
 	memory space.	CONFIG_SYS_FMAN_FW_ADDR is a virtual address which
@@ -4657,12 +4925,34 @@ within that device.
 - CONFIG_FSL_MC_ENET
 	Enable the MC driver for Layerscape SoCs.
 
+- CONFIG_SYS_LS_MC_FW_ADDR
+	The address in the storage device where the firmware is located.  The
+	meaning of this address depends on which CONFIG_SYS_LS_MC_FW_IN_xxx macro
+	is also specified.
+
+- CONFIG_SYS_LS_MC_FW_LENGTH
+	The maximum possible size of the firmware.  The firmware binary format
+	has a field that specifies the actual size of the firmware, but it
+	might not be possible to read any part of the firmware unless some
+	local storage is allocated to hold the entire firmware first.
+
+- CONFIG_SYS_LS_MC_FW_IN_NOR
+	Specifies that MC firmware is located in NOR flash, mapped as
+	normal addressable memory via the LBC. CONFIG_SYS_LS_MC_FW_ADDR is the
+	virtual address in NOR flash.
+
 Freescale Layerscape Debug Server Support:
 -------------------------------------------
 The Freescale Layerscape Debug Server Support supports the loading of
 "Debug Server firmware" and triggering SP boot-rom.
 This firmware often needs to be loaded during U-Boot booting.
 
+- CONFIG_FSL_DEBUG_SERVER
+	Enable the Debug Server for Layerscape SoCs.
+
+- CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE
+	Define minimum DDR size required for debug server image
+
 - CONFIG_SYS_MC_RSV_MEM_ALIGN
 	Define alignment of reserved memory MC requires
 

api/api_storage.c

@@ -37,11 +37,11 @@ struct stor_spec {
 	int		max_dev;
 	int		enum_started;
 	int		enum_ended;
-	int		type;	/* "external" type: DT_STOR_{IDE,USB,etc} */
+	int		type;		/* "external" type: DT_STOR_{IDE,USB,etc} */
 	char		*name;
 };
 
-static struct stor_spec specs[ENUM_MAX] = { { 0, 0, 0, 0, NULL }, };
+static struct stor_spec specs[ENUM_MAX] = { { 0, 0, 0, 0, "" }, };
 
 
 void dev_stor_init(void)
@@ -105,10 +105,6 @@ static int dev_stor_get(int type, int first, int *more, struct device_info *di)
 
 	struct blk_desc *dd;
 
-	/* Wasn't configured for this type, return 0 directly */
-	if (specs[type].name == NULL)
-		return 0;
-
 	if (first) {
 		di->cookie = (void *)blk_get_dev(specs[type].name, 0);
 		if (di->cookie == NULL)
@@ -116,10 +112,8 @@ static int dev_stor_get(int type, int first, int *more, struct device_info *di)
 		else
 			found = 1;
 
-		/*
-		 * provide hint if there are more devices in
-		 * this group to enumerate
-		 */
+		/* provide hint if there are more devices in
+		 * this group to enumerate */
 		if (1 < specs[type].max_dev)
 			*more = 1;
 
@@ -127,10 +121,8 @@ static int dev_stor_get(int type, int first, int *more, struct device_info *di)
 		for (i = 0; i < specs[type].max_dev; i++)
 			if (di->cookie ==
 			    (void *)blk_get_dev(specs[type].name, i)) {
-				/*
-				 * previous cookie found -- advance to the
-				 * next device, if possible
-				 */
+				/* previous cookie found -- advance to the
+				 * next device, if possible */
 
 				if (++i >= specs[type].max_dev) {
 					/* out of range, no more to enum */
@@ -145,10 +137,8 @@ static int dev_stor_get(int type, int first, int *more, struct device_info *di)
 				else
 					found = 1;
 
-				/*
-				 * provide hint if there are more devices in
-				 * this group to enumerate
-				 */
+				/* provide hint if there are more devices in
+				 * this group to enumerate */
 				if ((i + 1) < specs[type].max_dev)
 					*more = 1;
 
@@ -177,8 +167,9 @@ static int dev_stor_get(int type, int first, int *more, struct device_info *di)
 }
 
 
-/* returns: ENUM_IDE, ENUM_USB etc. based on struct blk_desc */
-
+/*
+ * returns:	ENUM_IDE, ENUM_USB etc. based on struct blk_desc
+ */
 static int dev_stor_type(struct blk_desc *dd)
 {
 	int i, j;
@@ -192,8 +183,9 @@ static int dev_stor_type(struct blk_desc *dd)
 }
 
 
-/* returns: 0/1 whether cookie points to some device in this group */
-
+/*
+ * returns:	0/1 whether cookie points to some device in this group
+ */
 static int dev_is_stor(int type, struct device_info *di)
 {
 	return (dev_stor_type(di->cookie) == type) ? 1 : 0;
@@ -224,6 +216,7 @@ static int dev_enum_stor(int type, struct device_info *di)
 	 */
 
 	if (di->cookie == NULL) {
+
 		debugf("group%d - enum restart\n", type);
 
 		/*
@@ -234,6 +227,7 @@ static int dev_enum_stor(int type, struct device_info *di)
 		specs[type].enum_started = 1;
 
 	} else if (dev_is_stor(type, di)) {
+
 		debugf("group%d - enum continued for the next device\n", type);
 
 		if (specs[type].enum_ended) {
@@ -245,6 +239,7 @@ static int dev_enum_stor(int type, struct device_info *di)
 		found = dev_stor_get(type, 0, &more, di);
 
 	} else {
+
 		if (specs[type].enum_ended) {
 			debugf("group %d - already enumerated, skipping\n", type);
 			return 0;
@@ -256,7 +251,7 @@ static int dev_enum_stor(int type, struct device_info *di)
 			/*
 			 * 2b.  If enumerating devices in this group did not
 			 * happen before, it means the cookie pointed to a
-			 * device from some other group (another storage
+			 * device frome some other group (another storage
 			 * group, or network); in this case try to take the
 			 * first available device from our group
 			 */
@@ -283,7 +278,7 @@ static int dev_enum_stor(int type, struct device_info *di)
 
 	if (found)
 		debugf("device found, returning cookie 0x%08x\n",
-		       (u_int32_t)di->cookie);
+			(u_int32_t)di->cookie);
 	else
 		debugf("no device found\n");
 
@@ -304,7 +299,9 @@ int dev_enum_storage(struct device_info *di)
 {
 	int i;
 
-	/* check: ide, usb, scsi, mmc */
+	/*
+	 * check: ide, usb, scsi, mmc
+	 */
 	for (i = ENUM_IDE; i < ENUM_MAX; i ++) {
 		if (dev_enum_stor(i, di))
 			return 1;

arch/Kconfig

@@ -62,7 +62,6 @@ config SANDBOX
 	bool "Sandbox"
 	select SUPPORT_OF_CONTROL
 	select DM
-	select DM_KEYBOARD
 	select DM_SPI_FLASH
 	select DM_SERIAL
 	select DM_I2C
@@ -84,7 +83,6 @@ config X86
 	select HAVE_PRIVATE_LIBGCC
 	select SUPPORT_OF_CONTROL
 	select DM
-	select DM_KEYBOARD
 	select DM_SERIAL
 	select DM_GPIO
 	select DM_SPI

arch/arc/config.mk

@@ -31,15 +31,15 @@ CONFIG_MMU = 1
 endif
 
 ifdef CONFIG_CPU_ARC750D
-PLATFORM_CPPFLAGS += -mcpu=arc700
+PLATFORM_CPPFLAGS += -marc700
 endif
 
 ifdef CONFIG_CPU_ARC770D
-PLATFORM_CPPFLAGS += -mcpu=arc700 -mlock -mswape
+PLATFORM_CPPFLAGS += -marc700 -mlock -mswape
 endif
 
 ifdef CONFIG_CPU_ARCEM6
-PLATFORM_CPPFLAGS += -mcpu=arcem
+PLATFORM_CPPFLAGS += -marcem
 endif
 
 ifdef CONFIG_CPU_ARCHS34

arch/arc/include/asm/errno.h

@@ -0,0 +1 @@
+#include <asm-generic/errno.h>

arch/arc/lib/bootm.c

@@ -37,11 +37,6 @@ void arch_lmb_reserve(struct lmb *lmb)
 	lmb_reserve(lmb, sp, (CONFIG_SYS_SDRAM_BASE + gd->ram_size - sp));
 }
 
-int arch_fixup_fdt(void *blob)
-{
-	return 0;
-}
-
 static int cleanup_before_linux(void)
 {
 	disable_interrupts();

arch/arm/Kconfig

@@ -126,35 +126,6 @@ config ENABLE_ARM_SOC_BOOT0_HOOK
 	  ARM_SOC_BOOT0_HOOK which contains the required assembler
 	  preprocessor code.
 
-config USE_ARCH_MEMCPY
-	bool "Use an assembly optimized implementation of memcpy"
-	default y if CPU_V7
-	depends on !ARM64
-	help
-	  Enable the generation of an optimized version of memcpy.
-	  Such implementation may be faster under some conditions
-	  but may increase the binary size.
-
-config USE_ARCH_MEMSET
-	bool "Use an assembly optimized implementation of memset"
-	default y if CPU_V7
-	depends on !ARM64
-	help
-	  Enable the generation of an optimized version of memset.
-	  Such implementation may be faster under some conditions
-	  but may increase the binary size.
-
-config ARCH_OMAP2
-	bool
-	select CPU_V7
-	select SUPPORT_SPL
-
-config ARM64_SUPPORT_AARCH32
-	bool "ARM64 system support AArch32 execution state"
-	default y if ARM64 && !TARGET_THUNDERX_88XX
-	help
-	  This ARM64 system supports AArch32 execution state.
-
 choice
 	prompt "Target select"
 	default TARGET_HIKEY
@@ -166,6 +137,14 @@ config TARGET_EDB93XX
 	bool "Support edb93xx"
 	select CPU_ARM920T
 
+config TARGET_VCMA9
+	bool "Support VCMA9"
+	select CPU_ARM920T
+
+config TARGET_SMDK2410
+	bool "Support smdk2410"
+	select CPU_ARM920T
+
 config TARGET_ASPENITE
 	bool "Support aspenite"
 	select CPU_ARM926EJS
@@ -185,7 +164,9 @@ config KIRKWOOD
 	select CPU_ARM926EJS
 
 config ARCH_MVEBU
-	bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)"
+	bool "Marvell MVEBU family (Armada XP/375/38x)"
+	select CPU_V7
+	select SUPPORT_SPL
 	select OF_CONTROL
 	select OF_SEPARATE
 	select DM
@@ -193,6 +174,10 @@ config ARCH_MVEBU
 	select DM_SERIAL
 	select DM_SPI
 	select DM_SPI_FLASH
+	select SPL_DM
+	select SPL_DM_SEQ_ALIAS
+	select SPL_OF_CONTROL
+	select SPL_SIMPLE_BUS
 
 config TARGET_DEVKIT3250
 	bool "Support devkit3250"
@@ -331,7 +316,6 @@ config ARCH_BCM283X
 	select DM
 	select DM_SERIAL
 	select DM_GPIO
-	select OF_CONTROL
 
 config TARGET_VEXPRESS_CA15_TC2
 	bool "Support vexpress_ca15_tc2"
@@ -349,61 +333,159 @@ config TARGET_VEXPRESS_CA9X4
 
 config TARGET_BRXRE1
 	bool "Support BRXRE1"
-	select ARCH_OMAP2
+	select CPU_V7
+	select SUPPORT_SPL
 
 config TARGET_BRPPT1
 	bool "Support BRPPT1"
-	select ARCH_OMAP2
+	select CPU_V7
+	select SUPPORT_SPL
+
+config TARGET_CM_T335
+	bool "Support cm_t335"
+	select CPU_V7
+	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
+
+config TARGET_PEPPER
+	bool "Support pepper"
+	select CPU_V7
+	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
+
+config TARGET_AM335X_IGEP0033
+	bool "Support am335x_igep0033"
+	select CPU_V7
+	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
+
+config TARGET_PCM051
+	bool "Support pcm051"
+	select CPU_V7
+	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
 
 config TARGET_DRACO
 	bool "Support draco"
-	select ARCH_OMAP2
+	select CPU_V7
+	select SUPPORT_SPL
 	select DM
 	select DM_SERIAL
 	select DM_GPIO
 
 config TARGET_THUBAN
 	bool "Support thuban"
-	select ARCH_OMAP2
+	select CPU_V7
+	select SUPPORT_SPL
 	select DM
 	select DM_SERIAL
 	select DM_GPIO
 
 config TARGET_RASTABAN
 	bool "Support rastaban"
-	select ARCH_OMAP2
+	select CPU_V7
+	select SUPPORT_SPL
 	select DM
 	select DM_SERIAL
 	select DM_GPIO
 
 config TARGET_ETAMIN
 	bool "Support etamin"
-	select ARCH_OMAP2
+	select CPU_V7
+	select SUPPORT_SPL
 	select DM
 	select DM_SERIAL
 	select DM_GPIO
 
 config TARGET_PXM2
 	bool "Support pxm2"
-	select ARCH_OMAP2
+	select CPU_V7
+	select SUPPORT_SPL
 	select DM
 	select DM_SERIAL
 	select DM_GPIO
 
 config TARGET_RUT
 	bool "Support rut"
-	select ARCH_OMAP2
+	select CPU_V7
+	select SUPPORT_SPL
 	select DM
 	select DM_SERIAL
 	select DM_GPIO
 
+config TARGET_PENGWYN
+	bool "Support pengwyn"
+	select CPU_V7
+	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
+
+config TARGET_AM335X_BALTOS
+	bool "Support am335x_baltos"
+	select CPU_V7
+	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
+
+config TARGET_AM335X_EVM
+	bool "Support am335x_evm"
+	select CPU_V7
+	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
+	select TI_I2C_BOARD_DETECT
+
+config TARGET_AM335X_SHC
+	bool "Support am335x based shc board from bosch"
+	select CPU_V7
+	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
+
+config TARGET_AM335X_SL50
+	bool "Support am335x_sl50"
+	select CPU_V7
+	select SUPPORT_SPL
+	select DM
+	select DM_GPIO
+	select DM_SERIAL
+
+config TARGET_BAV335X
+	bool "Support bav335x"
+	select CPU_V7
+	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	help
+	  The BAV335x OEM Network Processor integrates all the functions of an
+	  embedded network computer in a small, easy to use SODIMM module which
+	  incorporates the popular Texas Instruments Sitara 32bit ARM Coretex-A8
+	  processor, with fast DDR3 512MB SDRAM, 4GB of embedded MMC and a Gigabit
+	  ethernet with simple connection to external connectors.
+
+	  For more information, visit: http://birdland.com/oem
+
 config TARGET_TI814X_EVM
 	bool "Support ti814x_evm"
-	select ARCH_OMAP2
+	select CPU_V7
+	select SUPPORT_SPL
 
 config TARGET_TI816X_EVM
 	bool "Support ti816x_evm"
-	select ARCH_OMAP2
+	select CPU_V7
+	select SUPPORT_SPL
 
 config TARGET_BCM23550_W1D
 	bool "Support bcm23550_w1d"
@@ -424,7 +506,6 @@ config TARGET_BCMNSP
 config ARCH_EXYNOS
 	bool "Samsung EXYNOS"
 	select DM
-	select DM_I2C
 	select DM_SPI_FLASH
 	select DM_SERIAL
 	select DM_SPI
@@ -437,7 +518,6 @@ config ARCH_S5PC1XX
 	select DM
 	select DM_SERIAL
 	select DM_GPIO
-	select DM_I2C
 
 config ARCH_HIGHBANK
 	bool "Calxeda Highbank"
@@ -464,16 +544,10 @@ config ARCH_MESON
 config ARCH_MX7
 	bool "Freescale MX7"
 	select CPU_V7
-	select SYS_FSL_HAS_SEC if SECURE_BOOT
-	select SYS_FSL_SEC_COMPAT_4
-	select SYS_FSL_SEC_LE
 
 config ARCH_MX6
 	bool "Freescale MX6"
 	select CPU_V7
-	select SYS_FSL_HAS_SEC if SECURE_BOOT
-	select SYS_FSL_SEC_COMPAT_4
-	select SYS_FSL_SEC_LE
 
 config ARCH_MX5
 	bool "Freescale MX5"
@@ -506,21 +580,25 @@ config TARGET_MX53SMD
 
 config OMAP34XX
 	bool "OMAP34XX SoC"
-	select ARCH_OMAP2
+	select CPU_V7
+	select SUPPORT_SPL
 	select USE_TINY_PRINTF
 
 config OMAP44XX
 	bool "OMAP44XX SoC"
-	select ARCH_OMAP2
+	select CPU_V7
+	select SUPPORT_SPL
 	select USE_TINY_PRINTF
 
 config OMAP54XX
 	bool "OMAP54XX SoC"
-	select ARCH_OMAP2
+	select CPU_V7
+	select SUPPORT_SPL
 
 config AM43XX
 	bool "AM43XX SoC"
-	select ARCH_OMAP2
+	select CPU_V7
+	select SUPPORT_SPL
 	help
 	  Support for AM43xx SOC from Texas Instruments.
 	  The AM43xx high performance SOC features a Cortex-A9
@@ -528,16 +606,6 @@ config AM43XX
 	  protocols, dual camera support, optional 3D graphics
 	  and an optional customer programmable secure boot.
 
-config AM33XX
-	bool "AM33XX SoC"
-	select ARCH_OMAP2
-	help
-	  Support for AM335x SOC from Texas Instruments.
-	  The AM335x high performance SOC features a Cortex-A8
-	  ARM core, a dual core PRU-ICSS for industrial Ethernet
-	  protocols, optional 3D graphics and an optional customer
-	  programmable secure boot.
-
 config ARCH_RMOBILE
 	bool "Renesas ARM SoCs"
 	select DM
@@ -546,7 +614,6 @@ config ARCH_RMOBILE
 config TARGET_S32V234EVB
 	bool "Support s32v234evb"
 	select ARM64
-	select SYS_FSL_ERRATUM_ESDHC111
 
 config ARCH_SNAPDRAGON
 	bool "Qualcomm Snapdragon SoCs"
@@ -567,67 +634,49 @@ config ARCH_SOCFPGA
 	select DM
 	select DM_SPI_FLASH
 	select DM_SPI
-	select ENABLE_ARM_SOC_BOOT0_HOOK
 
 config TARGET_CM_T43
 	bool "Support cm_t43"
-	select ARCH_OMAP2
+	select CPU_V7
+	select SUPPORT_SPL
 
 config ARCH_SUNXI
 	bool "Support sunxi (Allwinner) SoCs"
 	select CMD_GPIO
 	select CMD_MMC if MMC
-	select CMD_USB if DISTRO_DEFAULTS
+	select CMD_USB
 	select DM
 	select DM_ETH
 	select DM_GPIO
 	select DM_KEYBOARD
 	select DM_SERIAL
-	select DM_USB if DISTRO_DEFAULTS
+	select DM_USB
 	select OF_BOARD_SETUP
 	select OF_CONTROL
 	select OF_SEPARATE
 	select SPL_STACK_R if SUPPORT_SPL
 	select SPL_SYS_MALLOC_SIMPLE if SUPPORT_SPL
 	select SYS_NS16550
-	select USB if DISTRO_DEFAULTS
-	select USB_STORAGE if DISTRO_DEFAULTS
-	select USB_KEYBOARD if DISTRO_DEFAULTS
+	select USB
+	select USB_STORAGE
+	select USB_KEYBOARD
 	select USE_TINY_PRINTF
 
-config TARGET_TS4600
-	bool "Support TS4600"
-	select CPU_ARM926EJS
-	select SUPPORT_SPL
-
 config TARGET_TS4800
 	bool "Support TS4800"
 	select CPU_V7
-	select SYS_FSL_ERRATUM_ESDHC_A001
 
 config TARGET_VF610TWR
 	bool "Support vf610twr"
 	select CPU_V7
-	select SYS_FSL_ERRATUM_ESDHC111
 
 config TARGET_COLIBRI_VF
 	bool "Support Colibri VF50/61"
 	select CPU_V7
-	select SYS_FSL_ERRATUM_ESDHC111
 
 config TARGET_PCM052
 	bool "Support pcm-052"
 	select CPU_V7
-	select SYS_FSL_ERRATUM_ESDHC111
-	select SYS_FSL_ERRATUM_ESDHC135
-	select SYS_FSL_ERRATUM_ESDHC_A001
-
-config TARGET_BK4R1
-	bool "Support BK4r1"
-	select CPU_V7
-	select SYS_FSL_ERRATUM_ESDHC111
-	select SYS_FSL_ERRATUM_ESDHC135
-	select SYS_FSL_ERRATUM_ESDHC_A001
 
 config ARCH_ZYNQ
 	bool "Xilinx Zynq Platform"
@@ -686,7 +735,6 @@ config TARGET_VEXPRESS64_JUNO
 
 config TARGET_LS2080A_EMU
 	bool "Support ls2080a_emu"
-	select ARCH_LS2080A
 	select ARM64
 	select ARMV8_MULTIENTRY
 	help
@@ -697,7 +745,6 @@ config TARGET_LS2080A_EMU
 
 config TARGET_LS2080A_SIMU
 	bool "Support ls2080a_simu"
-	select ARCH_LS2080A
 	select ARM64
 	select ARMV8_MULTIENTRY
 	help
@@ -708,7 +755,6 @@ config TARGET_LS2080A_SIMU
 
 config TARGET_LS2080AQDS
 	bool "Support ls2080aqds"
-	select ARCH_LS2080A
 	select ARM64
 	select ARMV8_MULTIENTRY
 	select SUPPORT_SPL
@@ -720,7 +766,6 @@ config TARGET_LS2080AQDS
 
 config TARGET_LS2080ARDB
 	bool "Support ls2080ardb"
-	select ARCH_LS2080A
 	select ARM64
 	select ARMV8_MULTIENTRY
 	select SUPPORT_SPL
@@ -743,7 +788,6 @@ config TARGET_HIKEY
 
 config TARGET_LS1012AQDS
 	bool "Support ls1012aqds"
-	select ARCH_LS1012A
 	select ARM64
 	help
 	  Support for Freescale LS1012AQDS platform.
@@ -753,7 +797,6 @@ config TARGET_LS1012AQDS
 
 config TARGET_LS1012ARDB
 	bool "Support ls1012ardb"
-	select ARCH_LS1012A
 	select ARM64
 	help
 	  Support for Freescale LS1012ARDB platform.
@@ -763,7 +806,6 @@ config TARGET_LS1012ARDB
 
 config TARGET_LS1012AFRDM
 	bool "Support ls1012afrdm"
-	select ARCH_LS1012A
 	select ARM64
 	help
 	  Support for Freescale LS1012AFRDM platform.
@@ -774,41 +816,17 @@ config TARGET_LS1012AFRDM
 config TARGET_LS1021AQDS
 	bool "Support ls1021aqds"
 	select CPU_V7
-	select CPU_V7_HAS_NONSEC
-	select CPU_V7_HAS_VIRT
 	select SUPPORT_SPL
-	select ARCH_LS1021A
 	select ARCH_SUPPORT_PSCI
-	select LS1_DEEP_SLEEP
-	select SYS_FSL_DDR
 
 config TARGET_LS1021ATWR
 	bool "Support ls1021atwr"
 	select CPU_V7
-	select CPU_V7_HAS_NONSEC
-	select CPU_V7_HAS_VIRT
 	select SUPPORT_SPL
-	select ARCH_LS1021A
 	select ARCH_SUPPORT_PSCI
-	select LS1_DEEP_SLEEP
-
-config TARGET_LS1021AIOT
-	bool "Support ls1021aiot"
-	select CPU_V7
-	select CPU_V7_HAS_NONSEC
-	select CPU_V7_HAS_VIRT
-	select SUPPORT_SPL
-	select ARCH_LS1021A
-	select ARCH_SUPPORT_PSCI
-	help
-	  Support for Freescale LS1021AIOT platform.
-	  The LS1021A Freescale board (IOT) is a high-performance
-	  development platform that supports the QorIQ LS1021A
-	  Layerscape Architecture processor.
 
 config TARGET_LS1043AQDS
 	bool "Support ls1043aqds"
-	select ARCH_LS1043A
 	select ARM64
 	select ARMV8_MULTIENTRY
 	select SUPPORT_SPL
@@ -817,39 +835,12 @@ config TARGET_LS1043AQDS
 
 config TARGET_LS1043ARDB
 	bool "Support ls1043ardb"
-	select ARCH_LS1043A
 	select ARM64
 	select ARMV8_MULTIENTRY
 	select SUPPORT_SPL
 	help
 	  Support for Freescale LS1043ARDB platform.
 
-config TARGET_LS1046AQDS
-	bool "Support ls1046aqds"
-	select ARCH_LS1046A
-	select ARM64
-	select ARMV8_MULTIENTRY
-	select SUPPORT_SPL
-	select DM_SPI_FLASH if DM_SPI
-	help
-	  Support for Freescale LS1046AQDS platform.
-	  The LS1046A Development System (QDS) is a high-performance
-	  development platform that supports the QorIQ LS1046A
-	  Layerscape Architecture processor.
-
-config TARGET_LS1046ARDB
-	bool "Support ls1046ardb"
-	select ARCH_LS1046A
-	select ARM64
-	select ARMV8_MULTIENTRY
-	select SUPPORT_SPL
-	select DM_SPI_FLASH if DM_SPI
-	help
-	  Support for Freescale LS1046ARDB platform.
-	  The LS1046A Reference Design Board (RDB) is a high-performance
-	  development platform that supports the QorIQ LS1046A
-	  Layerscape Architecture processor.
-
 config TARGET_H2200
 	bool "Support h2200"
 	select CPU_PXA
@@ -865,23 +856,17 @@ config TARGET_COLIBRI_PXA270
 config ARCH_UNIPHIER
 	bool "Socionext UniPhier SoCs"
 	select CLK_UNIPHIER
+	select SUPPORT_SPL
+	select SPL
+	select OF_CONTROL
+	select SPL_OF_CONTROL
+	select OF_LIBFDT
 	select DM
+	select SPL_DM
 	select DM_GPIO
+	select DM_SERIAL
 	select DM_I2C
 	select DM_MMC
-	select DM_RESET
-	select DM_SERIAL
-	select DM_USB
-	select OF_CONTROL
-	select OF_LIBFDT
-	select PINCTRL
-	select SPL
-	select SPL_DM
-	select SPL_LIBCOMMON_SUPPORT
-	select SPL_LIBGENERIC_SUPPORT
-	select SPL_OF_CONTROL
-	select SPL_PINCTRL
-	select SUPPORT_SPL
 	help
 	  Support for UniPhier SoC family developed by Socionext Inc.
 	  (formerly, System LSI Business Division of Panasonic Corporation)
@@ -907,9 +892,6 @@ config ARCH_ROCKCHIP
 	select DM_SERIAL
 	select DM_SPI
 	select DM_SPI_FLASH
-	select DM_USB if USB
-	select DM_PWM
-	select DM_REGULATOR
 
 config TARGET_THUNDERX_88XX
 	bool "Support ThunderX 88xx"
@@ -935,21 +917,15 @@ source "arch/arm/mach-keystone/Kconfig"
 
 source "arch/arm/mach-kirkwood/Kconfig"
 
-source "arch/arm/mach-litesom/Kconfig"
-
 source "arch/arm/mach-mvebu/Kconfig"
 
-source "arch/arm/cpu/armv7/ls102xa/Kconfig"
-
 source "arch/arm/cpu/armv7/mx7/Kconfig"
 
 source "arch/arm/cpu/armv7/mx6/Kconfig"
 
 source "arch/arm/cpu/armv7/mx5/Kconfig"
 
-source "arch/arm/mach-omap2/Kconfig"
-
-source "arch/arm/cpu/armv8/fsl-layerscape/Kconfig"
+source "arch/arm/cpu/armv7/omap-common/Kconfig"
 
 source "arch/arm/mach-orion5x/Kconfig"
 
@@ -1008,10 +984,7 @@ source "board/freescale/ls2080ardb/Kconfig"
 source "board/freescale/ls1021aqds/Kconfig"
 source "board/freescale/ls1043aqds/Kconfig"
 source "board/freescale/ls1021atwr/Kconfig"
-source "board/freescale/ls1021aiot/Kconfig"
-source "board/freescale/ls1046aqds/Kconfig"
 source "board/freescale/ls1043ardb/Kconfig"
-source "board/freescale/ls1046ardb/Kconfig"
 source "board/freescale/ls1012aqds/Kconfig"
 source "board/freescale/ls1012ardb/Kconfig"
 source "board/freescale/ls1012afrdm/Kconfig"
@@ -1033,10 +1006,12 @@ source "board/h2200/Kconfig"
 source "board/hisilicon/hikey/Kconfig"
 source "board/imx31_phycore/Kconfig"
 source "board/isee/igep0033/Kconfig"
+source "board/mpl/vcma9/Kconfig"
 source "board/olimex/mx23_olinuxino/Kconfig"
 source "board/phytec/pcm051/Kconfig"
 source "board/phytec/pcm052/Kconfig"
 source "board/ppcag/bg0900/Kconfig"
+source "board/samsung/smdk2410/Kconfig"
 source "board/sandisk/sansa_fuze_plus/Kconfig"
 source "board/schulercontrol/sc_sps_1/Kconfig"
 source "board/siemens/draco/Kconfig"
@@ -1060,7 +1035,6 @@ source "board/ti/ti816x/Kconfig"
 source "board/timll/devkit3250/Kconfig"
 source "board/toradex/colibri_pxa270/Kconfig"
 source "board/toradex/colibri_vf/Kconfig"
-source "board/technologic/ts4600/Kconfig"
 source "board/technologic/ts4800/Kconfig"
 source "board/vscom/baltos/Kconfig"
 source "board/woodburn/Kconfig"

arch/arm/Makefile

@@ -58,13 +58,11 @@ machine-$(CONFIG_ARCH_HIGHBANK)		+= highbank
 machine-$(CONFIG_ARCH_KEYSTONE)		+= keystone
 # TODO: rename CONFIG_KIRKWOOD -> CONFIG_ARCH_KIRKWOOD
 machine-$(CONFIG_KIRKWOOD)		+= kirkwood
-machine-$(CONFIG_LITESOM)		+= litesom
 machine-$(CONFIG_ARCH_MESON)		+= meson
 machine-$(CONFIG_ARCH_MVEBU)		+= mvebu
 # TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA
 # TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X
 machine-$(CONFIG_ORION5X)		+= orion5x
-machine-$(CONFIG_ARCH_OMAP2)		+= omap2
 machine-$(CONFIG_ARCH_S5PC1XX)		+= s5pc1xx
 machine-$(CONFIG_ARCH_SUNXI)		+= sunxi
 machine-$(CONFIG_ARCH_SNAPDRAGON)	+= snapdragon
@@ -95,7 +93,7 @@ libs-y += arch/arm/cpu/
 libs-y += arch/arm/lib/
 
 ifeq ($(CONFIG_SPL_BUILD),y)
-ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35))
+ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx31 mx35))
 libs-y += arch/arm/imx-common/
 endif
 else

arch/arm/config.mk

@@ -6,16 +6,13 @@
 #
 
 ifndef CONFIG_STANDALONE_LOAD_ADDR
-ifneq ($(CONFIG_ARCH_OMAP2),)
+ifneq ($(CONFIG_OMAP_COMMON),)
 CONFIG_STANDALONE_LOAD_ADDR = 0x80300000
 else
 CONFIG_STANDALONE_LOAD_ADDR = 0xc100000
 endif
 endif
 
-CFLAGS_NON_EFI := -fno-pic -ffixed-r9 -ffunction-sections -fdata-sections
-CFLAGS_EFI := -fpic -fshort-wchar
-
 LDFLAGS_FINAL += --gc-sections
 PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections \
 		     -fno-common -ffixed-r9
@@ -121,8 +118,7 @@ endif
 
 # limit ourselves to the sections we want in the .bin.
 ifdef CONFIG_ARM64
-OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .data \
-		-j .u_boot_list -j .rela.dyn
+OBJCOPYFLAGS += -j .text -j .rodata -j .data -j .u_boot_list -j .rela.dyn
 else
 OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .hash \
 		-j .data -j .got -j .got.plt -j .u_boot_list -j .rel.dyn
@@ -148,11 +144,4 @@ else
 ALL-y += u-boot.imx
 endif
 endif
-ifneq ($(CONFIG_VF610),)
-ALL-y += u-boot.vyb
 endif
-endif
-
-EFI_LDS := elf_arm_efi.lds
-EFI_CRT0 := crt0_arm_efi.o
-EFI_RELOC := reloc_arm_efi.o

arch/arm/cpu/arm1136/mx35/generic.c

@@ -10,7 +10,7 @@
 #include <common.h>
 #include <div64.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>

arch/arm/cpu/arm1136/mx35/mx35_sdram.c

@@ -5,7 +5,7 @@
  */
 
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/imx-regs.h>
 #include <linux/types.h>
 #include <asm/arch/sys_proto.h>

arch/arm/cpu/arm1176/start.S

@@ -16,7 +16,6 @@
 
 #include <asm-offsets.h>
 #include <config.h>
-#include <linux/linkage.h>
 
 #ifndef CONFIG_SYS_PHY_UBOOT_BASE
 #define CONFIG_SYS_PHY_UBOOT_BASE	CONFIG_SYS_UBOOT_BASE
@@ -38,11 +37,6 @@
 	.globl reset
 
 reset:
-	/* Allow the board to save important registers */
-	b	save_boot_params
-.globl	save_boot_params_ret
-save_boot_params_ret:
-
 	/*
 	 * set the cpu to SVC32 mode
 	 */
@@ -116,7 +110,3 @@ mmu_disable_phys:
 c_runtime_cpu_setup:
 
 	mov	pc, lr
-
-WEAK(save_boot_params)
-	b	save_boot_params_ret	/* back to my caller */
-ENDPROC(save_boot_params)

arch/arm/cpu/arm920t/imx/timer.c

@@ -78,7 +78,11 @@ unsigned long long get_ticks(void)
  */
 ulong get_tbclk (void)
 {
-	return CONFIG_SYS_HZ;
+	ulong tbclk;
+
+	tbclk = CONFIG_SYS_HZ;
+
+	return tbclk;
 }
 
 /*

arch/arm/cpu/arm926ejs/mxs/clock.c

@@ -11,7 +11,7 @@
  */
 
 #include <common.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/imx-regs.h>

arch/arm/cpu/arm926ejs/mxs/iomux.c

@@ -8,7 +8,7 @@
  */
 
 #include <common.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/iomux.h>

arch/arm/cpu/arm926ejs/mxs/mxs.c

@@ -11,7 +11,7 @@
  */
 
 #include <common.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/imx-common/dma.h>

arch/arm/cpu/arm926ejs/mxs/spl_boot.c

@@ -40,17 +40,17 @@ void early_delay(int delay)
 		;
 }
 
-#if defined(CONFIG_MX23)
 #define	MUX_CONFIG_BOOTMODE_PAD	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
 static const iomux_cfg_t iomux_boot[] = {
+#if defined(CONFIG_MX23)
 	MX23_PAD_LCD_D00__GPIO_1_0 | MUX_CONFIG_BOOTMODE_PAD,
 	MX23_PAD_LCD_D01__GPIO_1_1 | MUX_CONFIG_BOOTMODE_PAD,
 	MX23_PAD_LCD_D02__GPIO_1_2 | MUX_CONFIG_BOOTMODE_PAD,
 	MX23_PAD_LCD_D03__GPIO_1_3 | MUX_CONFIG_BOOTMODE_PAD,
 	MX23_PAD_LCD_D04__GPIO_1_4 | MUX_CONFIG_BOOTMODE_PAD,
 	MX23_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_BOOTMODE_PAD,
-};
 #endif
+};
 
 static uint8_t mxs_get_bootmode_index(void)
 {

arch/arm/cpu/arm926ejs/spear/timer.c

@@ -37,7 +37,7 @@ int timer_init(void)
 	writel(MISC_PRSC_CFG, &misc_regs_p->prsc1_clk_cfg);
 	synth = MISC_GPT3SYNTH;
 #else
-# error Incorrect config. Can only be SPEAR{600|300|310|320}
+# error Incorrect config. Can only be spear{600|300|310|320}
 #endif
 
 	writel(readl(&misc_regs_p->periph_clk_cfg) | synth,

arch/arm/cpu/armv7/Makefile

@@ -12,7 +12,7 @@ obj-y	+= cache_v7.o cache_v7_asm.o
 obj-y	+= cpu.o cp15.o
 obj-y	+= syslib.o
 
-ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_MX7)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_ARCH_SUNXI)$(CONFIG_ARCH_SOCFPGA)$(CONFIG_LS102XA),)
+ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_MX7)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI)$(CONFIG_ARCH_SOCFPGA),)
 ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y)
 obj-y	+= lowlevel_init.o
 endif
@@ -23,12 +23,14 @@ obj-$(CONFIG_ARMV7_PSCI)	+= psci.o psci-common.o
 
 obj-$(CONFIG_IPROC) += iproc-common/
 obj-$(CONFIG_KONA) += kona-common/
+obj-$(CONFIG_OMAP_COMMON) += omap-common/
 obj-$(CONFIG_SYS_ARCH_TIMER) += arch_timer.o
 
 ifneq (,$(filter s5pc1xx exynos,$(SOC)))
 obj-y += s5p-common/
 endif
 
+obj-$(if $(filter am33xx,$(SOC)),y) += am33xx/
 obj-$(if $(filter bcm235xx,$(SOC)),y) += bcm235xx/
 obj-$(if $(filter bcm281xx,$(SOC)),y) += bcm281xx/
 obj-$(if $(filter bcmcygnus,$(SOC)),y) += bcmcygnus/
@@ -37,6 +39,9 @@ obj-$(if $(filter ls102xa,$(SOC)),y) += ls102xa/
 obj-$(if $(filter mx5,$(SOC)),y) += mx5/
 obj-$(CONFIG_MX6) += mx6/
 obj-$(CONFIG_MX7) += mx7/
+obj-$(CONFIG_OMAP34XX) += omap3/
+obj-$(CONFIG_OMAP44XX) += omap4/
+obj-$(CONFIG_OMAP54XX) += omap5/
 obj-$(CONFIG_RMOBILE) += rmobile/
 obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/
 obj-$(CONFIG_ARCH_SUNXI) += sunxi/

arch/arm/cpu/armv7/am33xx/Kconfig

@@ -0,0 +1,40 @@
+if AM43XX
+config TARGET_AM43XX_EVM
+	bool "Support am43xx_evm"
+	select TI_I2C_BOARD_DETECT
+	help
+	  This option specifies support for the AM43xx
+	  GP and HS EVM development platforms.The AM437x
+	  GP EVM is a standalone test, development, and
+	  evaluation module system that enables developers
+	  to write software and develop hardware around
+	  an AM43xx processor subsystem.
+
+config ISW_ENTRY_ADDR
+	hex "Address in memory or XIP flash of bootloader entry point"
+	help
+	  After any reset, the boot ROM on the AM43XX SOC
+	  searches the boot media for a valid boot image.
+	  For non-XIP devices, the ROM then copies the
+	  image into internal memory.
+	  For all boot modes, after the ROM processes the
+	  boot image it eventually computes the entry
+	  point address depending on the device type
+	  (secure/non-secure), boot media (xip/non-xip) and
+	  image headers.
+	default 0x402F4000
+
+config PUB_ROM_DATA_SIZE
+	hex "Size in bytes of the L3 SRAM reserved by ROM to store data"
+	help
+	  During the device boot, the public ROM uses the top of
+	  the public L3 OCMC RAM to store r/w data like stack,
+	  heap, globals etc. When the ROM is copying the boot
+	  image from the boot media into memory, the image must
+	  not spill over into this area. This value can be used
+	  during compile time to determine the maximum size of a
+	  boot image. Once the ROM transfers control to the boot
+	  image, this area is no longer used, and can be reclaimed
+	  for run time use by the boot image.
+	default 0x8400
+endif

arch/arm/cpu/armv7/am33xx/board.c

@@ -28,7 +28,7 @@
 #include <i2c.h>
 #include <miiphy.h>
 #include <cpsw.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <linux/compiler.h>
 #include <linux/usb/ch9.h>
 #include <linux/usb/gadget.h>
@@ -120,8 +120,7 @@ int cpu_mmc_init(bd_t *bis)
 
 /* AM33XX has two MUSB controllers which can be host or gadget */
 #if (defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)) && \
-	(defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) && \
-	(!defined(CONFIG_DM_USB))
+	(defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1))
 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 
 /* USB 2.0 PHY Control */
@@ -148,7 +147,7 @@ static struct musb_hdrc_config musb_config = {
 };
 
 #ifdef CONFIG_AM335X_USB0
-static void am33xx_otg0_set_phy_power(struct udevice *dev, u8 on)
+static void am33xx_otg0_set_phy_power(u8 on)
 {
 	am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0);
 }
@@ -167,7 +166,7 @@ static struct musb_hdrc_platform_data otg0_plat = {
 #endif
 
 #ifdef CONFIG_AM335X_USB1
-static void am33xx_otg1_set_phy_power(struct udevice *dev, u8 on)
+static void am33xx_otg1_set_phy_power(u8 on)
 {
 	am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1);
 }
@@ -188,7 +187,6 @@ static struct musb_hdrc_platform_data otg1_plat = {
 
 int arch_misc_init(void)
 {
-#ifndef CONFIG_DM_USB
 #ifdef CONFIG_AM335X_USB0
 	musb_register(&otg0_plat, &otg0_board_data,
 		(void *)USB0_OTG_BASE);
@@ -196,14 +194,6 @@ int arch_misc_init(void)
 #ifdef CONFIG_AM335X_USB1
 	musb_register(&otg1_plat, &otg1_board_data,
 		(void *)USB1_OTG_BASE);
-#endif
-#else
-	struct udevice *dev;
-	int ret;
-
-	ret = uclass_first_device(UCLASS_MISC, &dev);
-	if (ret || !dev)
-		return ret;
 #endif
 	return 0;
 }
@@ -280,11 +270,15 @@ static void watchdog_disable(void)
 		;
 }
 
-void s_init(void)
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong dummy)
 {
+	board_early_init_f();
+	sdram_init();
 }
+#endif
 
-void early_system_init(void)
+void s_init(void)
 {
 	/*
 	 * The ROM will only have set up sufficient pinmux to allow for the
@@ -296,32 +290,11 @@ void early_system_init(void)
 #endif
 	watchdog_disable();
 	set_uart_mux_conf();
-	setup_early_clocks();
+	setup_clocks_for_console();
 	uart_soft_reset();
-#ifdef CONFIG_TI_I2C_BOARD_DETECT
-	do_board_detect();
-#endif
 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
 	/* Enable RTC32K clock */
 	rtc32k_enable();
 #endif
 }
-
-#ifdef CONFIG_SPL_BUILD
-void board_init_f(ulong dummy)
-{
-	early_system_init();
-	board_early_init_f();
-	sdram_init();
-}
 #endif
-
-#endif
-
-int arch_cpu_init_dm(void)
-{
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-	early_system_init();
-#endif
-	return 0;
-}

arch/arm/cpu/armv7/am33xx/clock.c

@@ -232,15 +232,10 @@ __weak void scale_vcores(void)
 {
 }
 
-void setup_early_clocks(void)
+void prcm_init()
 {
-	setup_clocks_for_console();
 	enable_basic_clocks();
-	timer_init();
-}
-
-void prcm_init(void)
-{
 	scale_vcores();
 	setup_dplls();
+	timer_init();
 }

arch/arm/cpu/armv7/am33xx/clock_ti814x.c

@@ -386,12 +386,6 @@ void setup_clocks_for_console(void)
 	while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN)
 		;
 }
-
-void setup_early_clocks(void)
-{
-	setup_clocks_for_console();
-}
-
 /*
  * Configure the PLL/PRCM for necessary peripherals
  */

arch/arm/cpu/armv7/am33xx/clock_ti816x.c

@@ -429,11 +429,6 @@ void setup_clocks_for_console(void)
 		;
 }
 
-void setup_early_clocks(void)
-{
-	setup_clocks_for_console();
-}
-
 void prcm_init(void)
 {
 	/* Enable the control */

arch/arm/cpu/armv7/am33xx/config.mk

@@ -0,0 +1,32 @@
+#
+# Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+include  $(srctree)/$(CPUDIR)/omap-common/config_secure.mk
+
+ifdef CONFIG_SPL_BUILD
+ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
+#
+# For booting from SPI use
+# u-boot-spl_HS_SPI_X-LOADER to program flash
+#
+# For booting spl from all other  media
+# use u-boot-spl_HS_ISSW
+#
+# Refer to README.ti-secure for more info
+#
+ALL-y	+= u-boot-spl_HS_ISSW
+ALL-$(CONFIG_SPL_SPI_SUPPORT) += u-boot-spl_HS_SPI_X-LOADER
+else
+ALL-y	+= MLO
+ALL-$(CONFIG_SPL_SPI_SUPPORT) += MLO.byteswap
+endif
+else
+ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
+ALL-$(CONFIG_QSPI_BOOT) += u-boot_HS_XIP_X-LOADER
+ALL-$(CONFIG_SPL_LOAD_FIT) += u-boot_HS.img
+endif
+ALL-y	+= u-boot.img
+endif

arch/arm/cpu/armv7/am33xx/ddr.c

@@ -180,10 +180,6 @@ void config_sdram(const struct emif_regs *regs, int nr)
 	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
 	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
 	writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
-
-	/* Write REG_COS_COUNT_1, REG_COS_COUNT_2, and REG_PR_OLD_COUNT. */
-	if (regs->ocp_config)
-		writel(regs->ocp_config, &emif_reg[nr]->emif_l3_config);
 }
 
 /**

arch/arm/cpu/armv7/am33xx/sys_info.c

@@ -65,7 +65,9 @@ u32 get_device_type(void)
  */
 u32 get_sysboot_value(void)
 {
-	return readl(&cstat->statusreg) & SYSBOOT_MASK;
+	int mode;
+	mode = readl(&cstat->statusreg) & (SYSBOOT_MASK);
+	return mode;
 }
 
 #ifdef CONFIG_DISPLAY_CPUINFO
@@ -95,9 +97,6 @@ int print_cpuinfo(void)
 	case TI81XX:
 		cpu_s = "TI81XX";
 		break;
-	case AM437X:
-		cpu_s = "AM437X";
-		break;
 	default:
 		cpu_s = "Unknown CPU type";
 		break;
@@ -113,7 +112,7 @@ int print_cpuinfo(void)
 	else
 		sec_s = "?";
 
-	printf("CPU  : %s-%s rev %s\n", cpu_s, sec_s, rev_s);
+	printf("%s-%s rev %s\n", cpu_s, sec_s, rev_s);
 
 	return 0;
 }

arch/arm/cpu/armv7/arch_timer.c

@@ -8,7 +8,6 @@
 #include <common.h>
 #include <asm/io.h>
 #include <div64.h>
-#include <bootstage.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -18,6 +17,7 @@ int timer_init(void)
 	gd->arch.tbu = 0;
 
 	gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ;
+
 	return 0;
 }
 
@@ -39,11 +39,6 @@ ulong get_timer(ulong base)
 	return lldiv(get_ticks(), gd->arch.timer_rate_hz) - base;
 }
 
-ulong timer_get_boot_us(void)
-{
-	return lldiv(get_ticks(), CONFIG_SYS_HZ_CLOCK / (CONFIG_SYS_HZ * 1000));
-}
-
 void __udelay(unsigned long usec)
 {
 	unsigned long long endtime;

arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c

@@ -12,7 +12,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/sysmap.h>
 #include <asm/kona-common/clk.h>
 #include "clk-core.h"

arch/arm/cpu/armv7/bcm235xx/clk-bsc.c

@@ -6,7 +6,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/sysmap.h>
 #include <asm/kona-common/clk.h>
 #include "clk-core.h"

arch/arm/cpu/armv7/bcm235xx/clk-core.c

@@ -12,7 +12,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <bitfield.h>
 #include <asm/arch/sysmap.h>
 #include <asm/kona-common/clk.h>

arch/arm/cpu/armv7/bcm235xx/clk-eth.c

@@ -6,7 +6,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/sysmap.h>
 #include <asm/kona-common/clk.h>
 #include "clk-core.h"

arch/arm/cpu/armv7/bcm235xx/clk-sdio.c

@@ -6,7 +6,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/sysmap.h>
 #include <asm/kona-common/clk.h>
 #include "clk-core.h"

arch/arm/cpu/armv7/bcm235xx/clk-usb-otg.c

@@ -5,7 +5,7 @@
  */
 
 #include <common.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/sysmap.h>
 #include "clk-core.h"
 

arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c

@@ -12,7 +12,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/sysmap.h>
 #include <asm/kona-common/clk.h>
 #include "clk-core.h"

arch/arm/cpu/armv7/bcm281xx/clk-bsc.c

@@ -6,7 +6,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/sysmap.h>
 #include <asm/kona-common/clk.h>
 #include "clk-core.h"

arch/arm/cpu/armv7/bcm281xx/clk-core.c

@@ -12,7 +12,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <bitfield.h>
 #include <asm/arch/sysmap.h>
 #include <asm/kona-common/clk.h>

arch/arm/cpu/armv7/bcm281xx/clk-eth.c

@@ -6,7 +6,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/sysmap.h>
 #include <asm/kona-common/clk.h>
 #include "clk-core.h"

arch/arm/cpu/armv7/bcm281xx/clk-sdio.c

@@ -6,7 +6,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/sysmap.h>
 #include <asm/kona-common/clk.h>
 #include "clk-core.h"

arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c

@@ -5,7 +5,7 @@
  */
 
 #include <common.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/sysmap.h>
 #include "clk-core.h"
 

arch/arm/cpu/armv7/lowlevel_init.S

@@ -19,11 +19,7 @@ ENTRY(lowlevel_init)
 	/*
 	 * Setup a temporary stack. Global data is not available yet.
 	 */
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
-	ldr	sp, =CONFIG_SPL_STACK
-#else
 	ldr	sp, =CONFIG_SYS_INIT_SP_ADDR
-#endif
 	bic	sp, sp, #7 /* 8-byte alignment for ABI compliance */
 #ifdef CONFIG_SPL_DM
 	mov	r9, #0

arch/arm/cpu/armv7/ls102xa/Kconfig

@@ -1,62 +0,0 @@
-config ARCH_LS1021A
-	bool
-	select SYS_FSL_ERRATUM_A008378
-	select SYS_FSL_ERRATUM_A008407
-	select SYS_FSL_ERRATUM_A009663
-	select SYS_FSL_ERRATUM_A009942
-	select SYS_FSL_ERRATUM_A010315
-	select SYS_FSL_SRDS_1
-	select SYS_HAS_SERDES
-	select SYS_FSL_DDR_BE if SYS_FSL_DDR
-	select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
-	select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR
-	select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR
-	select SYS_FSL_HAS_SEC
-	select SYS_FSL_SEC_COMPAT_5
-	select SYS_FSL_SEC_LE
-
-menu "LS102xA architecture"
-	depends on ARCH_LS1021A
-
-config LS1_DEEP_SLEEP
-	bool "Deep sleep"
-	depends on ARCH_LS1021A
-
-config MAX_CPUS
-	int "Maximum number of CPUs permitted for LS102xA"
-	depends on ARCH_LS1021A
-	default 2
-	help
-	  Set this number to the maximum number of possible CPUs in the SoC.
-	  SoCs may have multiple clusters with each cluster may have multiple
-	  ports. If some ports are reserved but higher ports are used for
-	  cores, count the reserved ports. This will allocate enough memory
-	  in spin table to properly handle all cores.
-
-config SECURE_BOOT
-	bool	"Secure Boot"
-	help
-		Enable Freescale Secure Boot feature. Normally selected
-		by defconfig. If unsure, do not change.
-
-config SYS_FSL_ERRATUM_A010315
-	bool "Workaround for PCIe erratum A010315"
-
-config SYS_FSL_SRDS_1
-	bool
-
-config SYS_FSL_SRDS_2
-	bool
-
-config SYS_HAS_SERDES
-	bool
-
-config SYS_FSL_IFC_BANK_COUNT
-	int "Maximum banks of Integrated flash controller"
-	depends on ARCH_LS1021A
-	default 8
-
-config SYS_FSL_ERRATUM_A008407
-	bool
-
-endmenu

arch/arm/cpu/armv7/ls102xa/Makefile

@@ -16,5 +16,5 @@ obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o
 obj-$(CONFIG_SPL) += spl.o
 
 ifdef CONFIG_ARMV7_PSCI
-obj-y  += psci.o ls102xa_psci.o
+obj-y  += psci.o
 endif

arch/arm/cpu/armv7/ls102xa/fsl_epu.c

@@ -9,163 +9,6 @@
 
 #include "fsl_epu.h"
 
-struct fsm_reg_vals epu_default_val[] = {
-	/* EPGCR (Event Processor Global Control Register) */
-	{EPGCR, 0},
-	/* EPECR (Event Processor Event Control Registers) */
-	{EPECR0 + EPECR_STRIDE * 0, 0},
-	{EPECR0 + EPECR_STRIDE * 1, 0},
-	{EPECR0 + EPECR_STRIDE * 2, 0xF0004004},
-	{EPECR0 + EPECR_STRIDE * 3, 0x80000084},
-	{EPECR0 + EPECR_STRIDE * 4, 0x20000084},
-	{EPECR0 + EPECR_STRIDE * 5, 0x08000004},
-	{EPECR0 + EPECR_STRIDE * 6, 0x80000084},
-	{EPECR0 + EPECR_STRIDE * 7, 0x80000084},
-	{EPECR0 + EPECR_STRIDE * 8, 0x60000084},
-	{EPECR0 + EPECR_STRIDE * 9, 0x08000084},
-	{EPECR0 + EPECR_STRIDE * 10, 0x42000084},
-	{EPECR0 + EPECR_STRIDE * 11, 0x90000084},
-	{EPECR0 + EPECR_STRIDE * 12, 0x80000084},
-	{EPECR0 + EPECR_STRIDE * 13, 0x08000084},
-	{EPECR0 + EPECR_STRIDE * 14, 0x02000084},
-	{EPECR0 + EPECR_STRIDE * 15, 0x00000004},
-	/*
-	 * EPEVTCR (Event Processor EVT Pin Control Registers)
-	 * SCU8 triger EVT2, and SCU11 triger EVT9
-	 */
-	{EPEVTCR0 + EPEVTCR_STRIDE * 0, 0},
-	{EPEVTCR0 + EPEVTCR_STRIDE * 1, 0},
-	{EPEVTCR0 + EPEVTCR_STRIDE * 2, 0x80000001},
-	{EPEVTCR0 + EPEVTCR_STRIDE * 3, 0},
-	{EPEVTCR0 + EPEVTCR_STRIDE * 4, 0},
-	{EPEVTCR0 + EPEVTCR_STRIDE * 5, 0},
-	{EPEVTCR0 + EPEVTCR_STRIDE * 6, 0},
-	{EPEVTCR0 + EPEVTCR_STRIDE * 7, 0},
-	{EPEVTCR0 + EPEVTCR_STRIDE * 8, 0},
-	{EPEVTCR0 + EPEVTCR_STRIDE * 9, 0xB0000001},
-	/* EPCMPR (Event Processor Counter Compare Registers) */
-	{EPCMPR0 + EPCMPR_STRIDE * 0, 0},
-	{EPCMPR0 + EPCMPR_STRIDE * 1, 0},
-	{EPCMPR0 + EPCMPR_STRIDE * 2, 0x000000FF},
-	{EPCMPR0 + EPCMPR_STRIDE * 3, 0},
-	{EPCMPR0 + EPCMPR_STRIDE * 4, 0x000000FF},
-	{EPCMPR0 + EPCMPR_STRIDE * 5, 0x00000020},
-	{EPCMPR0 + EPCMPR_STRIDE * 6, 0},
-	{EPCMPR0 + EPCMPR_STRIDE * 7, 0},
-	{EPCMPR0 + EPCMPR_STRIDE * 8, 0x000000FF},
-	{EPCMPR0 + EPCMPR_STRIDE * 9, 0x000000FF},
-	{EPCMPR0 + EPCMPR_STRIDE * 10, 0x000000FF},
-	{EPCMPR0 + EPCMPR_STRIDE * 11, 0x000000FF},
-	{EPCMPR0 + EPCMPR_STRIDE * 12, 0x000000FF},
-	{EPCMPR0 + EPCMPR_STRIDE * 13, 0},
-	{EPCMPR0 + EPCMPR_STRIDE * 14, 0x000000FF},
-	{EPCMPR0 + EPCMPR_STRIDE * 15, 0x000000FF},
-	/* EPCCR (Event Processor Counter Control Registers) */
-	{EPCCR0 + EPCCR_STRIDE * 0, 0},
-	{EPCCR0 + EPCCR_STRIDE * 1, 0},
-	{EPCCR0 + EPCCR_STRIDE * 2, 0x92840000},
-	{EPCCR0 + EPCCR_STRIDE * 3, 0},
-	{EPCCR0 + EPCCR_STRIDE * 4, 0x92840000},
-	{EPCCR0 + EPCCR_STRIDE * 5, 0x92840000},
-	{EPCCR0 + EPCCR_STRIDE * 6, 0},
-	{EPCCR0 + EPCCR_STRIDE * 7, 0},
-	{EPCCR0 + EPCCR_STRIDE * 8, 0x92840000},
-	{EPCCR0 + EPCCR_STRIDE * 9, 0x92840000},
-	{EPCCR0 + EPCCR_STRIDE * 10, 0x92840000},
-	{EPCCR0 + EPCCR_STRIDE * 11, 0x92840000},
-	{EPCCR0 + EPCCR_STRIDE * 12, 0x92840000},
-	{EPCCR0 + EPCCR_STRIDE * 13, 0},
-	{EPCCR0 + EPCCR_STRIDE * 14, 0x92840000},
-	{EPCCR0 + EPCCR_STRIDE * 15, 0x92840000},
-	/* EPSMCR (Event Processor SCU Mux Control Registers) */
-	{EPSMCR0 + EPSMCR_STRIDE * 0, 0},
-	{EPSMCR0 + EPSMCR_STRIDE * 1, 0},
-	{EPSMCR0 + EPSMCR_STRIDE * 2, 0x6C700000},
-	{EPSMCR0 + EPSMCR_STRIDE * 3, 0x2F000000},
-	{EPSMCR0 + EPSMCR_STRIDE * 4, 0x002F0000},
-	{EPSMCR0 + EPSMCR_STRIDE * 5, 0x00002E00},
-	{EPSMCR0 + EPSMCR_STRIDE * 6, 0x7C000000},
-	{EPSMCR0 + EPSMCR_STRIDE * 7, 0x30000000},
-	{EPSMCR0 + EPSMCR_STRIDE * 8, 0x64300000},
-	{EPSMCR0 + EPSMCR_STRIDE * 9, 0x00003000},
-	{EPSMCR0 + EPSMCR_STRIDE * 10, 0x65000030},
-	{EPSMCR0 + EPSMCR_STRIDE * 11, 0x31740000},
-	{EPSMCR0 + EPSMCR_STRIDE * 12, 0x7F000000},
-	{EPSMCR0 + EPSMCR_STRIDE * 13, 0x00003100},
-	{EPSMCR0 + EPSMCR_STRIDE * 14, 0x00000031},
-	{EPSMCR0 + EPSMCR_STRIDE * 15, 0x76000000},
-	/* EPACR (Event Processor Action Control Registers) */
-	{EPACR0 + EPACR_STRIDE * 0, 0},
-	{EPACR0 + EPACR_STRIDE * 1, 0},
-	{EPACR0 + EPACR_STRIDE * 2, 0},
-	{EPACR0 + EPACR_STRIDE * 3, 0x00000080},
-	{EPACR0 + EPACR_STRIDE * 4, 0},
-	{EPACR0 + EPACR_STRIDE * 5, 0x00000040},
-	{EPACR0 + EPACR_STRIDE * 6, 0},
-	{EPACR0 + EPACR_STRIDE * 7, 0},
-	{EPACR0 + EPACR_STRIDE * 8, 0},
-	{EPACR0 + EPACR_STRIDE * 9, 0x0000001C},
-	{EPACR0 + EPACR_STRIDE * 10, 0x00000020},
-	{EPACR0 + EPACR_STRIDE * 11, 0},
-	{EPACR0 + EPACR_STRIDE * 12, 0x00000003},
-	{EPACR0 + EPACR_STRIDE * 13, 0x06000000},
-	{EPACR0 + EPACR_STRIDE * 14, 0x04000000},
-	{EPACR0 + EPACR_STRIDE * 15, 0x02000000},
-	/* EPIMCR (Event Processor Input Mux Control Registers) */
-	{EPIMCR0 + EPIMCR_STRIDE * 0, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 1, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 2, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 3, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 4, 0x44000000},
-	{EPIMCR0 + EPIMCR_STRIDE * 5, 0x40000000},
-	{EPIMCR0 + EPIMCR_STRIDE * 6, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 7, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 8, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 9, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 10, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 11, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 12, 0x44000000},
-	{EPIMCR0 + EPIMCR_STRIDE * 13, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 14, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 15, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 16, 0x6A000000},
-	{EPIMCR0 + EPIMCR_STRIDE * 17, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 18, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 19, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 20, 0x48000000},
-	{EPIMCR0 + EPIMCR_STRIDE * 21, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 22, 0x6C000000},
-	{EPIMCR0 + EPIMCR_STRIDE * 23, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 24, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 25, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 26, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 27, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 28, 0x76000000},
-	{EPIMCR0 + EPIMCR_STRIDE * 29, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 30, 0},
-	{EPIMCR0 + EPIMCR_STRIDE * 31, 0x76000000},
-	/* EPXTRIGCR (Event Processor Crosstrigger Control Register) */
-	{EPXTRIGCR, 0x0000FFDF},
-	/* end */
-	{FSM_END_FLAG, 0},
-};
-
-/**
- * fsl_epu_setup - Setup EPU registers to default values
- */
-void fsl_epu_setup(void *epu_base)
-{
-	struct fsm_reg_vals *data = epu_default_val;
-
-	if (!epu_base || !data)
-		return;
-
-	while (data->offset != FSM_END_FLAG) {
-		out_be32(epu_base + data->offset, data->value);
-		data++;
-	}
-}
-
 /**
  * fsl_epu_clean - Clear EPU registers
  */

arch/arm/cpu/armv7/ls102xa/fsl_epu.h

@@ -63,14 +63,6 @@
 #define EPCTR31		0xA7C
 #define EPCTR_STRIDE	FSL_STRIDE_4B
 
-#define FSM_END_FLAG	0xFFFFFFFFUL
-
-struct fsm_reg_vals {
-	u32 offset;
-	u32 value;
-};
-
-void fsl_epu_setup(void *epu_base);
 void fsl_epu_clean(void *epu_base);
 
 #endif

arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c

@@ -7,7 +7,7 @@
 #include <common.h>
 #include <asm/arch/fsl_serdes.h>
 #include <asm/arch/immap_ls102xa.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/io.h>
 #include "fsl_ls1_serdes.h"
 
@@ -23,15 +23,9 @@ int is_serdes_configured(enum srds_prtcl device)
 	u64 ret = 0;
 
 #ifdef CONFIG_SYS_FSL_SRDS_1
-	if (!(serdes1_prtcl_map & (1ULL << NONE)))
-		fsl_serdes_init();
-
 	ret |= (1ULL << device) & serdes1_prtcl_map;
 #endif
 #ifdef CONFIG_SYS_FSL_SRDS_2
-	if (!(serdes2_prtcl_map & (1ULL << NONE)))
-		fsl_serdes_init();
-
 	ret |= (1ULL << device) & serdes2_prtcl_map;
 #endif
 
@@ -93,24 +87,19 @@ u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
 		serdes_prtcl_map |= (1ULL << lane_prtcl);
 	}
 
-	/* Set the first bit to indicate serdes has been initialized */
-	serdes_prtcl_map |= (1ULL << NONE);
-
 	return serdes_prtcl_map;
 }
 
 void fsl_serdes_init(void)
 {
 #ifdef CONFIG_SYS_FSL_SRDS_1
-	if (!(serdes1_prtcl_map & (1ULL << NONE)))
-		serdes1_prtcl_map = serdes_init(FSL_SRDS_1,
+	serdes1_prtcl_map = serdes_init(FSL_SRDS_1,
 					CONFIG_SYS_FSL_SERDES_ADDR,
 					RCWSR4_SRDS1_PRTCL_MASK,
 					RCWSR4_SRDS1_PRTCL_SHIFT);
 #endif
 #ifdef CONFIG_SYS_FSL_SRDS_2
-	if (!(serdes2_prtcl_map & (1ULL << NONE)))
-		serdes2_prtcl_map = serdes_init(FSL_SRDS_2,
+	serdes2_prtcl_map = serdes_init(FSL_SRDS_2,
 					CONFIG_SYS_FSL_SERDES_ADDR +
 					FSL_SRDS_2 * 0x1000,
 					RCWSR4_SRDS2_PRTCL_MASK,

arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c

@@ -1,236 +0,0 @@
-/*
- * Copyright 2016 Freescale Semiconductor, Inc.
- * Author: Hongbo Zhang <hongbo.zhang@nxp.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- * This file implements LS102X platform PSCI SYSTEM-SUSPEND function
- */
-
-#include <config.h>
-#include <asm/io.h>
-#include <asm/psci.h>
-#include <asm/arch/immap_ls102xa.h>
-#include <fsl_immap.h>
-#include "fsl_epu.h"
-
-#define __secure __attribute__((section("._secure.text")))
-
-#define CCSR_GICD_CTLR			0x1000
-#define CCSR_GICC_CTLR			0x2000
-#define DCSR_RCPM_CG1CR0		0x31c
-#define DCSR_RCPM_CSTTACR0		0xb00
-#define DCFG_CRSTSR_WDRFR		0x8
-#define DDR_RESV_LEN			128
-
-#ifdef CONFIG_LS1_DEEP_SLEEP
-/*
- * DDR controller initialization training breaks the first 128 bytes of DDR,
- * save them so that the bootloader can restore them while resuming.
- */
-static void __secure ls1_save_ddr_head(void)
-{
-	const char *src = (const char *)CONFIG_SYS_SDRAM_BASE;
-	char *dest = (char *)(OCRAM_BASE_S_ADDR + OCRAM_S_SIZE - DDR_RESV_LEN);
-	struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
-	int i;
-
-	out_le32(&scfg->sparecr[2], dest);
-
-	for (i = 0; i < DDR_RESV_LEN; i++)
-		*dest++ = *src++;
-}
-
-static void __secure ls1_fsm_setup(void)
-{
-	void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
-	void *dcsr_rcpm_base = (void *)SYS_FSL_DCSR_RCPM_ADDR;
-
-	out_be32(dcsr_rcpm_base + DCSR_RCPM_CSTTACR0, 0x00001001);
-	out_be32(dcsr_rcpm_base + DCSR_RCPM_CG1CR0, 0x00000001);
-
-	fsl_epu_setup((void *)dcsr_epu_base);
-
-	/* Pull MCKE signal low before enabling deep sleep signal in FPGA */
-	out_be32(dcsr_epu_base + EPECR0, 0x5);
-	out_be32(dcsr_epu_base + EPSMCR15, 0x76300000);
-}
-
-static void __secure ls1_deepsleep_irq_cfg(void)
-{
-	struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
-	struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
-	u32 ippdexpcr0, ippdexpcr1, pmcintecr = 0;
-
-	/* Mask interrupts from GIC */
-	out_be32(&rcpm->nfiqoutr, 0x0ffffffff);
-	out_be32(&rcpm->nirqoutr, 0x0ffffffff);
-	/* Mask deep sleep wake-up interrupts while entering deep sleep */
-	out_be32(&rcpm->dsimskr, 0x0ffffffff);
-
-	ippdexpcr0 = in_be32(&rcpm->ippdexpcr0);
-	/*
-	 * Workaround: There is bug of register ippdexpcr1, when read it always
-	 * returns zero, so its value is saved to a scrachpad register to be
-	 * read, that is why we don't read it from register ippdexpcr1 itself.
-	 */
-	ippdexpcr1 = in_le32(&scfg->sparecr[7]);
-
-	if (ippdexpcr0 & RCPM_IPPDEXPCR0_ETSEC)
-		pmcintecr |= SCFG_PMCINTECR_ETSECRXG0 |
-			     SCFG_PMCINTECR_ETSECRXG1 |
-			     SCFG_PMCINTECR_ETSECERRG0 |
-			     SCFG_PMCINTECR_ETSECERRG1;
-
-	if (ippdexpcr0 & RCPM_IPPDEXPCR0_GPIO)
-		pmcintecr |= SCFG_PMCINTECR_GPIO;
-
-	if (ippdexpcr1 & RCPM_IPPDEXPCR1_LPUART)
-		pmcintecr |= SCFG_PMCINTECR_LPUART;
-
-	if (ippdexpcr1 & RCPM_IPPDEXPCR1_FLEXTIMER)
-		pmcintecr |= SCFG_PMCINTECR_FTM;
-
-	/* Always set external IRQ pins as wakeup source */
-	pmcintecr |= SCFG_PMCINTECR_IRQ0 | SCFG_PMCINTECR_IRQ1;
-
-	out_be32(&scfg->pmcintlecr, 0);
-	/* Clear PMC interrupt status */
-	out_be32(&scfg->pmcintsr, 0xffffffff);
-	/* Enable wakeup interrupt during deep sleep */
-	out_be32(&scfg->pmcintecr, pmcintecr);
-}
-
-static void __secure ls1_delay(unsigned int loop)
-{
-	while (loop--) {
-		int i = 1000;
-		while (i--)
-			;
-	}
-}
-
-static void __secure ls1_start_fsm(void)
-{
-	void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
-	void *ccsr_gic_base = (void *)SYS_FSL_GIC_ADDR;
-	struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
-	struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
-
-	/* Set HRSTCR */
-	setbits_be32(&scfg->hrstcr, 0x80000000);
-
-	/* Place DDR controller in self refresh mode */
-	setbits_be32(&ddr->sdram_cfg_2, 0x80000000);
-
-	ls1_delay(2000);
-
-	/* Set EVT4_B to lock the signal MCKE down */
-	out_be32(dcsr_epu_base + EPECR0, 0x0);
-
-	ls1_delay(2000);
-
-	out_be32(ccsr_gic_base + CCSR_GICD_CTLR, 0x0);
-	out_be32(ccsr_gic_base + CCSR_GICC_CTLR, 0x0);
-
-	/* Enable all EPU Counters */
-	setbits_be32(dcsr_epu_base + EPGCR, 0x80000000);
-
-	/* Enable SCU15 */
-	setbits_be32(dcsr_epu_base + EPECR15, 0x90000004);
-
-	/* Enter WFI mode, and EPU FSM will start */
-	__asm__ __volatile__ ("wfi" : : : "memory");
-
-	/* NEVER ENTER HERE */
-	while (1)
-		;
-}
-
-static void __secure ls1_deep_sleep(u32 entry_point)
-{
-	struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
-	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
-	struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
-#ifdef QIXIS_BASE
-	u32 tmp;
-	void *qixis_base = (void *)QIXIS_BASE;
-#endif
-
-	/* Enable cluster to enter the PCL10 state */
-	out_be32(&scfg->clusterpmcr, SCFG_CLUSTERPMCR_WFIL2EN);
-
-	/* Save the first 128 bytes of DDR data */
-	ls1_save_ddr_head();
-
-	/* Save the kernel resume entry */
-	out_le32(&scfg->sparecr[3], entry_point);
-
-	/* Request to put cluster 0 in PCL10 state */
-	setbits_be32(&rcpm->clpcl10setr, RCPM_CLPCL10SETR_C0);
-
-	/* Setup the registers of the EPU FSM for deep sleep */
-	ls1_fsm_setup();
-
-#ifdef QIXIS_BASE
-	/* Connect the EVENT button to IRQ in FPGA */
-	tmp = in_8(qixis_base + QIXIS_CTL_SYS);
-	tmp &= ~QIXIS_CTL_SYS_EVTSW_MASK;
-	tmp |= QIXIS_CTL_SYS_EVTSW_IRQ;
-	out_8(qixis_base + QIXIS_CTL_SYS, tmp);
-
-	/* Enable deep sleep signals in FPGA */
-	tmp = in_8(qixis_base + QIXIS_PWR_CTL2);
-	tmp |= QIXIS_PWR_CTL2_PCTL;
-	out_8(qixis_base + QIXIS_PWR_CTL2, tmp);
-
-	/* Pull down PCIe RST# */
-	tmp = in_8(qixis_base + QIXIS_RST_FORCE_3);
-	tmp |= QIXIS_RST_FORCE_3_PCIESLOT1;
-	out_8(qixis_base + QIXIS_RST_FORCE_3, tmp);
-#endif
-
-	/* Enable Warm Device Reset */
-	setbits_be32(&scfg->dpslpcr, SCFG_DPSLPCR_WDRR_EN);
-	setbits_be32(&gur->crstsr, DCFG_CRSTSR_WDRFR);
-
-	ls1_deepsleep_irq_cfg();
-
-	psci_v7_flush_dcache_all();
-
-	ls1_start_fsm();
-}
-
-#else
-static void __secure ls1_sleep(void)
-{
-	struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
-	struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
-
-#ifdef QIXIS_BASE
-	u32 tmp;
-	void *qixis_base = (void *)QIXIS_BASE;
-
-	/* Connect the EVENT button to IRQ in FPGA */
-	tmp = in_8(qixis_base + QIXIS_CTL_SYS);
-	tmp &= ~QIXIS_CTL_SYS_EVTSW_MASK;
-	tmp |= QIXIS_CTL_SYS_EVTSW_IRQ;
-	out_8(qixis_base + QIXIS_CTL_SYS, tmp);
-#endif
-
-	/* Enable cluster to enter the PCL10 state */
-	out_be32(&scfg->clusterpmcr, SCFG_CLUSTERPMCR_WFIL2EN);
-
-	setbits_be32(&rcpm->powmgtcsr, RCPM_POWMGTCSR_LPM20_REQ);
-
-	__asm__ __volatile__ ("wfi" : : : "memory");
-}
-#endif
-
-void __secure ls1_system_suspend(u32 fn, u32 entry_point, u32 context_id)
-{
-#ifdef CONFIG_LS1_DEEP_SLEEP
-	ls1_deep_sleep(entry_point);
-#else
-	ls1_sleep();
-#endif
-}

arch/arm/cpu/armv7/ls102xa/psci.S

@@ -29,7 +29,6 @@
 #define PSCI_FN_AFFINITY_INFO_FEATURE_MASK	0x0
 #define PSCI_FN_SYSTEM_OFF_FEATURE_MASK		0x0
 #define PSCI_FN_SYSTEM_RESET_FEATURE_MASK	0x0
-#define PSCI_FN_SYSTEM_SUSPEND_FEATURE_MASK	0x0
 
 	.pushsection ._secure.text, "ax"
 
@@ -62,8 +61,6 @@ _ls102x_psci_supported_table:
 	.word	PSCI_FN_SYSTEM_OFF_FEATURE_MASK
 	.word	ARM_PSCI_0_2_FN_SYSTEM_RESET
 	.word	PSCI_FN_SYSTEM_RESET_FEATURE_MASK
-	.word	ARM_PSCI_1_0_FN_SYSTEM_SUSPEND
-	.word	PSCI_FN_SYSTEM_SUSPEND_FEATURE_MASK
 	.word	0
 	.word	ARM_PSCI_RET_NI
 
@@ -246,12 +243,4 @@ psci_system_reset:
 1:	wfi
 	b	1b
 
-.globl	psci_system_suspend
-psci_system_suspend:
-	push	{lr}
-
-	bl	ls1_system_suspend
-
-	pop	{pc}
-
 	.popsection

arch/arm/cpu/armv7/ls102xa/soc.c

@@ -7,11 +7,9 @@
 #include <common.h>
 #include <asm/arch/clock.h>
 #include <asm/io.h>
-#include <asm/arch/fsl_serdes.h>
 #include <asm/arch/immap_ls102xa.h>
 #include <asm/arch/ls102xa_soc.h>
 #include <asm/arch/ls102xa_stream_id.h>
-#include <fsl_csu.h>
 
 struct liodn_id_table sec_liodn_tbl[] = {
 	SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),
@@ -60,33 +58,12 @@ unsigned int get_soc_major_rev(void)
 	return major;
 }
 
-void s_init(void)
-{
-}
-
-#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
-void erratum_a010315(void)
-{
-	int i;
-
-	for (i = PCIE1; i <= PCIE2; i++)
-		if (!is_serdes_configured(i)) {
-			debug("PCIe%d: disabled all R/W permission!\n", i);
-			set_pcie_ns_access(i, 0);
-		}
-}
-#endif
-
 int arch_soc_init(void)
 {
 	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
 	unsigned int major;
 
-#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
-	enable_layerscape_ns_access();
-#endif
-
 #ifdef CONFIG_FSL_QSPI
 	out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
 #endif

arch/arm/cpu/armv7/mx5/Kconfig

@@ -18,19 +18,11 @@ config TARGET_USBARMORY
 	bool "Support USB armory"
 	select CPU_V7
 
-config TARGET_MX53CX9020
-	bool "Support CX9020"
-	select CPU_V7
-	select MX53
-	select DM
-	select DM_SERIAL
-
 endchoice
 
 config SYS_SOC
 	default "mx5"
 
-source "board/beckhoff/mx53cx9020/Kconfig"
 source "board/inversepath/usbarmory/Kconfig"
 
 endif

arch/arm/cpu/armv7/mx5/clock.c

@@ -9,7 +9,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>

arch/arm/cpu/armv7/mx5/soc.c

@@ -12,7 +12,7 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
 
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/io.h>
 #include <asm/imx-common/boot_mode.h>
 

arch/arm/cpu/armv7/mx6/Kconfig

@@ -26,27 +26,11 @@ config MX6SX
 	select ROM_UNIFIED_SECTIONS
 	bool
 
-config MX6SLL
-	select ROM_UNIFIED_SECTIONS
-	bool
-
 config MX6UL
 	select SYS_L2CACHE_OFF
 	select ROM_UNIFIED_SECTIONS
 	bool
 
-config MX6ULL
-	bool
-	select MX6UL
-
-config MX6_DDRCAL
-	bool "Include dynamic DDR calibration routines"
-	depends on SPL
-	default n
-	help
-	  Say "Y" if your board uses dynamic (per-boot) DDR calibration.
-	  If unsure, say N.
-
 choice
 	prompt "MX6 board select"
 	optional
@@ -55,13 +39,6 @@ config TARGET_ADVANTECH_DMS_BA16
 	bool "Advantech dms-ba16"
 	select MX6Q
 
-config TARGET_APALIS_IMX6
-	bool "Toradex Apalis iMX6 board"
-	select SUPPORT_SPL
-	select DM
-	select DM_SERIAL
-	select DM_THERMAL
-
 config TARGET_ARISTAINETOS
 	bool "aristainetos"
 
@@ -84,13 +61,6 @@ config TARGET_CM_FX6
 	select DM_SERIAL
 	select DM_GPIO
 
-config TARGET_COLIBRI_IMX6
-	bool "Toradex Colibri iMX6 board"
-	select SUPPORT_SPL
-	select DM
-	select DM_SERIAL
-	select DM_THERMAL
-
 config TARGET_EMBESTMX6BOARDS
 	bool "embestmx6boards"
 
@@ -121,30 +91,6 @@ config TARGET_MX6CUBOXI
 config TARGET_MX6QARM2
 	bool "mx6qarm2"
 
-config TARGET_MX6Q_ICORE
-	bool "Support Engicam i.Core"
-	select MX6QDL
-	select OF_CONTROL
-	select DM
-	select DM_ETH
-	select DM_GPIO
-	select DM_I2C
-	select DM_MMC
-	select DM_THERMAL
-	select SUPPORT_SPL
-
-config TARGET_MX6Q_ICORE_RQS
-	bool "Support Engicam i.Core RQS"
-	select MX6QDL
-	select OF_CONTROL
-	select DM
-	select DM_ETH
-	select DM_GPIO
-	select DM_I2C
-	select DM_MMC
-	select DM_THERMAL
-	select SUPPORT_SPL
-
 config TARGET_MX6QSABREAUTO
 	bool "mx6qsabreauto"
 	select DM
@@ -160,12 +106,6 @@ config TARGET_MX6SLEVK
 	bool "mx6slevk"
 	select SUPPORT_SPL
 
-config TARGET_MX6SLLEVK
-        bool "mx6sll evk"
-        select MX6SLL
-        select DM
-        select DM_THERMAL
-
 config TARGET_MX6SXSABRESD
 	bool "mx6sxsabresd"
 	select MX6SX
@@ -193,24 +133,6 @@ config TARGET_MX6UL_14X14_EVK
 	select DM_THERMAL
 	select SUPPORT_SPL
 
-config TARGET_MX6UL_GEAM
-	bool "Support Engicam GEAM6UL"
-	select MX6UL
-	select OF_CONTROL
-	select DM
-	select DM_ETH
-	select DM_GPIO
-	select DM_I2C
-	select DM_MMC
-	select DM_THERMAL
-	select SUPPORT_SPL
-
-config TARGET_MX6ULL_14X14_EVK
-	bool "Support mx6ull_14x14_evk"
-	select MX6ULL
-	select DM
-	select DM_THERMAL
-
 config TARGET_NITROGEN6X
 	bool "nitrogen6x"
 
@@ -222,10 +144,6 @@ config TARGET_PICO_IMX6UL
 	bool "PICO-IMX6UL-EMMC"
 	select MX6UL
 
-config TARGET_LITEBOARD
-	bool "Grinn liteBoard (i.MX6UL)"
-	select LITESOM
-
 config TARGET_PLATINUM_PICON
 	bool "platinum-picon"
 	select SUPPORT_SPL
@@ -254,19 +172,6 @@ config TARGET_UDOO
 	bool "udoo"
 	select SUPPORT_SPL
 
-config TARGET_UDOO_NEO
-	bool "UDOO Neo"
-	select SUPPORT_SPL
-	select MX6SX
-	select DM
-	select DM_THERMAL
-
-config TARGET_SAMTEC_VINING_2000
-	bool "samtec VIN|ING 2000"
-	select MX6SX
-	select DM
-	select DM_THERMAL
-
 config TARGET_WANDBOARD
 	bool "wandboard"
 	select SUPPORT_SPL
@@ -310,32 +215,22 @@ source "board/compulab/cm_fx6/Kconfig"
 source "board/congatec/cgtqmx6eval/Kconfig"
 source "board/el/el6x/Kconfig"
 source "board/embest/mx6boards/Kconfig"
-source "board/engicam/geam6ul/Kconfig"
-source "board/engicam/icorem6/Kconfig"
-source "board/engicam/icorem6_rqs/Kconfig"
 source "board/freescale/mx6qarm2/Kconfig"
 source "board/freescale/mx6qsabreauto/Kconfig"
 source "board/freescale/mx6sabresd/Kconfig"
 source "board/freescale/mx6slevk/Kconfig"
-source "board/freescale/mx6sllevk/Kconfig"
 source "board/freescale/mx6sxsabresd/Kconfig"
 source "board/freescale/mx6sxsabreauto/Kconfig"
 source "board/freescale/mx6ul_14x14_evk/Kconfig"
-source "board/freescale/mx6ullevk/Kconfig"
-source "board/grinn/liteboard/Kconfig"
 source "board/phytec/pcm058/Kconfig"
 source "board/gateworks/gw_ventana/Kconfig"
 source "board/kosagi/novena/Kconfig"
-source "board/samtec/vining_2000/Kconfig"
 source "board/seco/Kconfig"
 source "board/solidrun/mx6cuboxi/Kconfig"
 source "board/technexion/pico-imx6ul/Kconfig"
 source "board/tbs/tbs2910/Kconfig"
 source "board/tqc/tqma6/Kconfig"
-source "board/toradex/apalis_imx6/Kconfig"
-source "board/toradex/colibri_imx6/Kconfig"
 source "board/udoo/Kconfig"
-source "board/udoo/neo/Kconfig"
 source "board/wandboard/Kconfig"
 source "board/warp/Kconfig"
 

arch/arm/cpu/armv7/mx6/clock.c

@@ -7,7 +7,7 @@
 #include <common.h>
 #include <div64.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>
@@ -97,10 +97,7 @@ void enable_enet_clk(unsigned char enable)
 {
 	u32 mask, *addr;
 
-	if (is_mx6ull()) {
-		mask = MXC_CCM_CCGR0_ENET_CLK_ENABLE_MASK;
-		addr = &imx_ccm->CCGR0;
-	} else if (is_mx6ul()) {
+	if (is_mx6ul()) {
 		mask = MXC_CCM_CCGR3_ENET_MASK;
 		addr = &imx_ccm->CCGR3;
 	} else {
@@ -120,7 +117,7 @@ void enable_uart_clk(unsigned char enable)
 {
 	u32 mask;
 
-	if (is_mx6ul() || is_mx6ull())
+	if (is_mx6ul())
 		mask = MXC_CCM_CCGR5_UART_MASK;
 	else
 		mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
@@ -171,9 +168,7 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 			reg &= ~mask;
 		__raw_writel(reg, &imx_ccm->CCGR2);
 	} else {
-		if (is_mx6sll())
-			return -EINVAL;
-		if (is_mx6sx() || is_mx6ul() || is_mx6ull()) {
+		if (is_mx6sx() || is_mx6ul()) {
 			mask = MXC_CCM_CCGR6_I2C4_MASK;
 			addr = &imx_ccm->CCGR6;
 		} else {
@@ -284,7 +279,7 @@ static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
 
 	switch (pll) {
 	case PLL_BUS:
-		if (!is_mx6ul() && !is_mx6ull()) {
+		if (!is_mx6ul()) {
 			if (pfd_num == 3) {
 				/* No PFD3 on PLL2 */
 				return 0;
@@ -384,8 +379,8 @@ static u32 get_ipg_per_clk(void)
 	u32 reg, perclk_podf;
 
 	reg = __raw_readl(&imx_ccm->cscmr1);
-	if (is_mx6sll() || is_mx6sl() || is_mx6sx() ||
-	    is_mx6dqp() || is_mx6ul() || is_mx6ull()) {
+	if (is_mx6sl() || is_mx6sx() ||
+	    is_mx6dqp() || is_mx6ul()) {
 		if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
 			return MXC_HCLK; /* OSC 24Mhz */
 	}
@@ -401,8 +396,7 @@ static u32 get_uart_clk(void)
 	u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
 	reg = __raw_readl(&imx_ccm->cscdr1);
 
-	if (is_mx6sl() || is_mx6sx() || is_mx6dqp() || is_mx6ul() ||
-	    is_mx6sll() || is_mx6ull()) {
+	if (is_mx6sl() || is_mx6sx() || is_mx6dqp() || is_mx6ul()) {
 		if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
 			freq = MXC_HCLK;
 	}
@@ -421,8 +415,7 @@ static u32 get_cspi_clk(void)
 	cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
 		     MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
 
-	if (is_mx6dqp() || is_mx6sl() || is_mx6sx() || is_mx6ul() ||
-	    is_mx6sll() || is_mx6ull()) {
+	if (is_mx6dqp() || is_mx6sl() || is_mx6sx() || is_mx6ul()) {
 		if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
 			return MXC_HCLK / (cspi_podf + 1);
 	}
@@ -484,8 +477,7 @@ static u32 get_mmdc_ch0_clk(void)
 
 	u32 freq, podf, per2_clk2_podf, pmu_misc2_audio_div;
 
-	if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl() ||
-	    is_mx6sll()) {
+	if (is_mx6sx() || is_mx6ul() || is_mx6sl()) {
 		podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
 			MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
 		if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
@@ -517,11 +509,6 @@ static u32 get_mmdc_ch0_clk(void)
 				freq = mxc_get_pll_pfd(PLL_BUS, 0);
 				break;
 			case 3:
-				if (is_mx6sl()) {
-					freq = mxc_get_pll_pfd(PLL_BUS, 2) >> 1;
-					break;
-				}
-
 				pmu_misc2_audio_div = PMU_MISC2_AUDIO_DIV(__raw_readl(&imx_ccm->pmu_misc2));
 				switch (pmu_misc2_audio_div) {
 				case 0:
@@ -628,19 +615,16 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq)
 
 	debug("mxs_set_lcdclk, freq = %dKHz\n", freq);
 
-	if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl() &&
-	    !is_mx6sll()) {
+	if (!is_mx6sx() && !is_mx6ul()) {
 		debug("This chip not support lcd!\n");
 		return;
 	}
 
-	if (!is_mx6sl()) {
-		if (base_addr == LCDIF1_BASE_ADDR) {
-			reg = readl(&imx_ccm->cscdr2);
-			/* Can't change clocks when clock not from pre-mux */
-			if ((reg & MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK) != 0)
-				return;
-		}
+	if (base_addr == LCDIF1_BASE_ADDR) {
+		reg = readl(&imx_ccm->cscdr2);
+		/* Can't change clocks when clock not from pre-mux */
+		if ((reg & MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK) != 0)
+			return;
 	}
 
 	if (is_mx6sx()) {
@@ -711,44 +695,24 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq)
 		if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
 			return;
 
-		enable_lcdif_clock(base_addr, 0);
-		if (!is_mx6sl()) {
-			/* Select pre-lcd clock to PLL5 and set pre divider */
-			clrsetbits_le32(&imx_ccm->cscdr2,
-					MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK |
-					MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK,
-					(0x2 << MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET) |
-					((pred - 1) <<
-					 MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET));
+		/* Select pre-lcd clock to PLL5 and set pre divider */
+		clrsetbits_le32(&imx_ccm->cscdr2,
+				MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK |
+				MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK,
+				(0x2 << MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET) |
+				((pred - 1) <<
+				 MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET));
 
-			/* Set the post divider */
-			clrsetbits_le32(&imx_ccm->cbcmr,
-					MXC_CCM_CBCMR_LCDIF1_PODF_MASK,
-					((postd - 1) <<
-					MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET));
-		} else {
-			/* Select pre-lcd clock to PLL5 and set pre divider */
-			clrsetbits_le32(&imx_ccm->cscdr2,
-					MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_MASK |
-					MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_MASK,
-					(0x2 << MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_OFFSET) |
-					((pred - 1) <<
-					 MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_OFFSET));
-
-			/* Set the post divider */
-			clrsetbits_le32(&imx_ccm->cscmr1,
-					MXC_CCM_CSCMR1_LCDIF_PIX_PODF_MASK,
-					(((postd - 1)^0x6) <<
-					 MXC_CCM_CSCMR1_LCDIF_PIX_PODF_OFFSET));
-		}
-
-		enable_lcdif_clock(base_addr, 1);
+		/* Set the post divider */
+		clrsetbits_le32(&imx_ccm->cbcmr,
+				MXC_CCM_CBCMR_LCDIF1_PODF_MASK,
+				((postd - 1) <<
+				 MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET));
 	} else if (is_mx6sx()) {
 		/* Setting LCDIF2 for i.MX6SX */
 		if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
 			return;
 
-		enable_lcdif_clock(base_addr, 0);
 		/* Select pre-lcd clock to PLL5 and set pre divider */
 		clrsetbits_le32(&imx_ccm->cscdr2,
 				MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK |
@@ -762,12 +726,10 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq)
 				MXC_CCM_CSCMR1_LCDIF2_PODF_MASK,
 				((postd - 1) <<
 				 MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET));
-
-		enable_lcdif_clock(base_addr, 1);
 	}
 }
 
-int enable_lcdif_clock(u32 base_addr, bool enable)
+int enable_lcdif_clock(u32 base_addr)
 {
 	u32 reg = 0;
 	u32 lcdif_clk_sel_mask, lcdif_ccgr3_mask;
@@ -787,7 +749,7 @@ int enable_lcdif_clock(u32 base_addr, bool enable)
 			 MXC_CCM_CCGR3_DISP_AXI_MASK) :
 			(MXC_CCM_CCGR3_LCDIF1_PIX_MASK |
 			 MXC_CCM_CCGR3_DISP_AXI_MASK);
-	} else if (is_mx6ul() || is_mx6ull() || is_mx6sll()) {
+	} else if (is_mx6ul()) {
 		if (base_addr != LCDIF1_BASE_ADDR) {
 			puts("Wrong LCD interface!\n");
 			return -EINVAL;
@@ -795,59 +757,23 @@ int enable_lcdif_clock(u32 base_addr, bool enable)
 		/* Set to pre-mux clock at default */
 		lcdif_clk_sel_mask = MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK;
 		lcdif_ccgr3_mask =  MXC_CCM_CCGR3_LCDIF1_PIX_MASK;
-	} else if (is_mx6sl()) {
-		if (base_addr != LCDIF1_BASE_ADDR) {
-			puts("Wrong LCD interface!\n");
-			return -EINVAL;
-		}
-
-		reg = readl(&imx_ccm->CCGR3);
-		reg &= ~(MXC_CCM_CCGR3_LCDIF_AXI_MASK |
-			 MXC_CCM_CCGR3_LCDIF_PIX_MASK);
-		writel(reg, &imx_ccm->CCGR3);
-
-		if (enable) {
-			reg = readl(&imx_ccm->cscdr3);
-			reg &= ~MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_MASK;
-			reg |= 1 << MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_OFFSET;
-			writel(reg, &imx_ccm->cscdr3);
-
-			reg = readl(&imx_ccm->CCGR3);
-			reg |= MXC_CCM_CCGR3_LCDIF_AXI_MASK |
-				MXC_CCM_CCGR3_LCDIF_PIX_MASK;
-			writel(reg, &imx_ccm->CCGR3);
-		}
-
-		return 0;
 	} else {
 		return 0;
 	}
 
-	/* Gate LCDIF clock first */
+	reg = readl(&imx_ccm->cscdr2);
+	reg &= ~lcdif_clk_sel_mask;
+	writel(reg, &imx_ccm->cscdr2);
+
+	/* Enable the LCDIF pix clock */
 	reg = readl(&imx_ccm->CCGR3);
-	reg &= ~lcdif_ccgr3_mask;
+	reg |= lcdif_ccgr3_mask;
 	writel(reg, &imx_ccm->CCGR3);
 
 	reg = readl(&imx_ccm->CCGR2);
-	reg &= ~MXC_CCM_CCGR2_LCD_MASK;
+	reg |= MXC_CCM_CCGR2_LCD_MASK;
 	writel(reg, &imx_ccm->CCGR2);
 
-	if (enable) {
-		/* Select pre-mux */
-		reg = readl(&imx_ccm->cscdr2);
-		reg &= ~lcdif_clk_sel_mask;
-		writel(reg, &imx_ccm->cscdr2);
-
-		/* Enable the LCDIF pix clock */
-		reg = readl(&imx_ccm->CCGR3);
-		reg |= lcdif_ccgr3_mask;
-		writel(reg, &imx_ccm->CCGR3);
-
-		reg = readl(&imx_ccm->CCGR2);
-		reg |= MXC_CCM_CCGR2_LCD_MASK;
-		writel(reg, &imx_ccm->CCGR2);
-	}
-
 	return 0;
 }
 #endif
@@ -921,7 +847,7 @@ int enable_fec_anatop_clock(int fec_id, enum enet_freq freq)
 		reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq);
 	} else if (fec_id == 1) {
 		/* Only i.MX6SX/UL support ENET2 */
-		if (!(is_mx6sx() || is_mx6ul() || is_mx6ull()))
+		if (!(is_mx6sx() || is_mx6ul()))
 			return -EINVAL;
 		reg &= ~BM_ANADIG_PLL_ENET2_DIV_SELECT;
 		reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq);
@@ -950,11 +876,6 @@ int enable_fec_anatop_clock(int fec_id, enum enet_freq freq)
 	writel(reg, &anatop->pll_enet);
 
 #ifdef CONFIG_MX6SX
-	/* Disable enet system clcok before switching clock parent */
-	reg = readl(&imx_ccm->CCGR3);
-	reg &= ~MXC_CCM_CCGR3_ENET_MASK;
-	writel(reg, &imx_ccm->CCGR3);
-
 	/*
 	 * Set enet ahb clock to 200MHz
 	 * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
@@ -985,16 +906,6 @@ static u32 get_usdhc_clk(u32 port)
 	u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
 	u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
 
-	if (is_mx6ul() || is_mx6ull()) {
-		if (port > 1)
-			return 0;
-	}
-
-	if (is_mx6sll()) {
-		if (port > 2)
-			return 0;
-	}
-
 	switch (port) {
 	case 0:
 		usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
@@ -1158,27 +1069,17 @@ void hab_caam_clock_enable(unsigned char enable)
 {
 	u32 reg;
 
-	if (is_mx6ull() || is_mx6sll()) {
-		/* CG5, DCP clock */
-		reg = __raw_readl(&imx_ccm->CCGR0);
-		if (enable)
-			reg |= MXC_CCM_CCGR0_DCP_CLK_MASK;
-		else
-			reg &= ~MXC_CCM_CCGR0_DCP_CLK_MASK;
-		__raw_writel(reg, &imx_ccm->CCGR0);
-	} else {
-		/* CG4 ~ CG6, CAAM clocks */
-		reg = __raw_readl(&imx_ccm->CCGR0);
-		if (enable)
-			reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
-				MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
-				MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
-		else
-			reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
-				MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
-				MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
-		__raw_writel(reg, &imx_ccm->CCGR0);
-	}
+	/* CG4 ~ CG6, CAAM clocks */
+	reg = __raw_readl(&imx_ccm->CCGR0);
+	if (enable)
+		reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
+			MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
+			MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
+	else
+		reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
+			MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
+			MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
+	__raw_writel(reg, &imx_ccm->CCGR0);
 
 	/* EMI slow clk */
 	reg = __raw_readl(&imx_ccm->CCGR6);
@@ -1463,20 +1364,6 @@ void select_ldb_di_clock_source(enum ldb_di_clock clk)
 }
 #endif
 
-#ifndef CONFIG_SYS_NO_FLASH
-void enable_eim_clk(unsigned char enable)
-{
-	u32 reg;
-
-	reg = __raw_readl(&imx_ccm->CCGR6);
-	if (enable)
-		reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
-	else
-		reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
-	__raw_writel(reg, &imx_ccm->CCGR6);
-}
-#endif
-
 /***************************************************/
 
 U_BOOT_CMD(

arch/arm/cpu/armv7/mx6/ddr.c

@@ -14,7 +14,8 @@
 #include <asm/types.h>
 #include <wait_bit.h>
 
-#if defined(CONFIG_MX6_DDRCAL)
+#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
+
 static void reset_read_data_fifos(void)
 {
 	struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
@@ -85,15 +86,14 @@ static void modify_dg_result(u32 *reg_st0, u32 *reg_st1, u32 *reg_ctrl)
 	writel(val_ctrl, reg_ctrl);
 }
 
-int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo)
+int mmdc_do_write_level_calibration(void)
 {
 	struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
 	struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
 	u32 esdmisc_val, zq_val;
 	u32 errors = 0;
-	u32 ldectrl[4] = {0};
+	u32 ldectrl[4];
 	u32 ddr_mr1 = 0x4;
-	u32 rwalat_max;
 
 	/*
 	 * Stash old values in case calibration fails,
@@ -101,10 +101,8 @@ int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo)
 	 */
 	ldectrl[0] = readl(&mmdc0->mpwldectrl0);
 	ldectrl[1] = readl(&mmdc0->mpwldectrl1);
-	if (sysinfo->dsize == 2) {
-		ldectrl[2] = readl(&mmdc1->mpwldectrl0);
-		ldectrl[3] = readl(&mmdc1->mpwldectrl1);
-	}
+	ldectrl[2] = readl(&mmdc1->mpwldectrl0);
+	ldectrl[3] = readl(&mmdc1->mpwldectrl1);
 
 	/* disable DDR logic power down timer */
 	clrbits_le32(&mmdc0->mdpdc, 0xff00);
@@ -124,10 +122,10 @@ int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo)
 	writel(zq_val & ~0x3, &mmdc0->mpzqhwctrl);
 
 	/* 3. increase walat and ralat to maximum */
-	rwalat_max = (1 << 6) | (1 << 7) | (1 << 8) | (1 << 16) | (1 << 17);
-	setbits_le32(&mmdc0->mdmisc, rwalat_max);
-	if (sysinfo->dsize == 2)
-		setbits_le32(&mmdc1->mdmisc, rwalat_max);
+	setbits_le32(&mmdc0->mdmisc,
+		     (1 << 6) | (1 << 7) | (1 << 8) | (1 << 16) | (1 << 17));
+	setbits_le32(&mmdc1->mdmisc,
+		     (1 << 6) | (1 << 7) | (1 << 8) | (1 << 16) | (1 << 17));
 	/*
 	 * 4 & 5. Configure the external DDR device to enter write-leveling
 	 * mode through Load Mode Register command.
@@ -154,25 +152,21 @@ int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo)
 	 */
 	if (readl(&mmdc0->mpwlgcr) & 0x00000F00)
 		errors |= 1;
-	if (sysinfo->dsize == 2)
-		if (readl(&mmdc1->mpwlgcr) & 0x00000F00)
-			errors |= 2;
+	if (readl(&mmdc1->mpwlgcr) & 0x00000F00)
+		errors |= 2;
 
 	debug("Ending write leveling calibration. Error mask: 0x%x\n", errors);
 
 	/* check to see if cal failed */
 	if ((readl(&mmdc0->mpwldectrl0) == 0x001F001F) &&
 	    (readl(&mmdc0->mpwldectrl1) == 0x001F001F) &&
-	    ((sysinfo->dsize < 2) ||
-	     ((readl(&mmdc1->mpwldectrl0) == 0x001F001F) &&
-	      (readl(&mmdc1->mpwldectrl1) == 0x001F001F)))) {
+	    (readl(&mmdc1->mpwldectrl0) == 0x001F001F) &&
+	    (readl(&mmdc1->mpwldectrl1) == 0x001F001F)) {
 		debug("Cal seems to have soft-failed due to memory not supporting write leveling on all channels. Restoring original write leveling values.\n");
 		writel(ldectrl[0], &mmdc0->mpwldectrl0);
 		writel(ldectrl[1], &mmdc0->mpwldectrl1);
-		if (sysinfo->dsize == 2) {
-			writel(ldectrl[2], &mmdc1->mpwldectrl0);
-			writel(ldectrl[3], &mmdc1->mpwldectrl1);
-		}
+		writel(ldectrl[2], &mmdc1->mpwldectrl0);
+		writel(ldectrl[3], &mmdc1->mpwldectrl1);
 		errors |= 4;
 	}
 
@@ -195,20 +189,16 @@ int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo)
 	      readl(&mmdc0->mpwldectrl0));
 	debug("\tMMDC_MPWLDECTRL1 after write level cal: 0x%08X\n",
 	      readl(&mmdc0->mpwldectrl1));
-	if (sysinfo->dsize == 2) {
-		debug("\tMMDC_MPWLDECTRL0 after write level cal: 0x%08X\n",
-		      readl(&mmdc1->mpwldectrl0));
-		debug("\tMMDC_MPWLDECTRL1 after write level cal: 0x%08X\n",
-		      readl(&mmdc1->mpwldectrl1));
-	}
+	debug("\tMMDC_MPWLDECTRL0 after write level cal: 0x%08X\n",
+	      readl(&mmdc1->mpwldectrl0));
+	debug("\tMMDC_MPWLDECTRL1 after write level cal: 0x%08X\n",
+	      readl(&mmdc1->mpwldectrl1));
 
 	/* We must force a readback of these values, to get them to stick */
 	readl(&mmdc0->mpwldectrl0);
 	readl(&mmdc0->mpwldectrl1);
-	if (sysinfo->dsize == 2) {
-		readl(&mmdc1->mpwldectrl0);
-		readl(&mmdc1->mpwldectrl1);
-	}
+	readl(&mmdc1->mpwldectrl0);
+	readl(&mmdc1->mpwldectrl1);
 
 	/* enable DDR logic power down timer: */
 	setbits_le32(&mmdc0->mdpdc, 0x00005500);
@@ -222,7 +212,7 @@ int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo)
 	return errors;
 }
 
-int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo)
+int mmdc_do_dqs_calibration(void)
 {
 	struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
 	struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
@@ -233,6 +223,7 @@ int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo)
 	bool cs0_enable_initial;
 	bool cs1_enable_initial;
 	u32 esdmisc_val;
+	u32 bus_size;
 	u32 temp_ref;
 	u32 pddword = 0x00ffff00; /* best so far, place into MPPDCMPR1 */
 	u32 errors = 0;
@@ -301,6 +292,10 @@ int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo)
 	cs0_enable = readl(&mmdc0->mdctl) & 0x80000000;
 	cs1_enable = readl(&mmdc0->mdctl) & 0x40000000;
 
+	/* Check to see what the data bus size is */
+	bus_size = (readl(&mmdc0->mdctl) & 0x30000) >> 16;
+	debug("Data bus size: %d (%d bits)\n", bus_size, 1 << (bus_size + 4));
+
 	precharge_all(cs0_enable, cs1_enable);
 
 	/* Write the pre-defined value into MPPDCMPR1 */
@@ -319,11 +314,11 @@ int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo)
 	 * Both PHYs for x64 configuration, if x32, do only PHY0.
 	 */
 	writel(initdelay, &mmdc0->mprddlctl);
-	if (sysinfo->dsize == 0x2)
+	if (bus_size == 0x2)
 		writel(initdelay, &mmdc1->mprddlctl);
 
 	/* Force a measurment, for previous delay setup to take effect. */
-	force_delay_measurement(sysinfo->dsize);
+	force_delay_measurement(bus_size);
 
 	/*
 	 * ***************************
@@ -352,8 +347,6 @@ int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo)
 	 * 16 before comparing read data.
 	 */
 	setbits_le32(&mmdc0->mpdgctrl0, 1 << 30);
-	if (sysinfo->dsize == 2)
-		setbits_le32(&mmdc1->mpdgctrl0, 1 << 30);
 
 	/* Set bit 28 to start automatic read DQS gating calibration */
 	setbits_le32(&mmdc0->mpdgctrl0, 5 << 28);
@@ -369,14 +362,9 @@ int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo)
 	if (readl(&mmdc0->mpdgctrl0) & 0x00001000)
 		errors |= 1;
 
-	if ((sysinfo->dsize == 0x2) && (readl(&mmdc1->mpdgctrl0) & 0x00001000))
+	if ((bus_size == 0x2) && (readl(&mmdc1->mpdgctrl0) & 0x00001000))
 		errors |= 2;
 
-	/* now disable mpdgctrl0[DG_CMP_CYC] */
-	clrbits_le32(&mmdc0->mpdgctrl0, 1 << 30);
-	if (sysinfo->dsize == 2)
-		clrbits_le32(&mmdc1->mpdgctrl0, 1 << 30);
-
 	/*
 	 * DQS gating absolute offset should be modified from
 	 * reflecting (HW_DG_LOWx + HW_DG_UPx)/2 to
@@ -386,7 +374,7 @@ int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo)
 			 &mmdc0->mpdgctrl0);
 	modify_dg_result(&mmdc0->mpdghwst2, &mmdc0->mpdghwst3,
 			 &mmdc0->mpdgctrl1);
-	if (sysinfo->dsize == 0x2) {
+	if (bus_size == 0x2) {
 		modify_dg_result(&mmdc1->mpdghwst0, &mmdc1->mpdghwst1,
 				 &mmdc1->mpdgctrl0);
 		modify_dg_result(&mmdc1->mpdghwst2, &mmdc1->mpdghwst3,
@@ -429,8 +417,7 @@ int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo)
 	if (readl(&mmdc0->mprddlhwctl) & 0x0000000f)
 		errors |= 4;
 
-	if ((sysinfo->dsize == 0x2) &&
-	    (readl(&mmdc1->mprddlhwctl) & 0x0000000f))
+	if ((bus_size == 0x2) && (readl(&mmdc1->mprddlhwctl) & 0x0000000f))
 		errors |= 8;
 
 	debug("Ending Read Delay calibration. Error mask: 0x%x\n", errors);
@@ -456,14 +443,14 @@ int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo)
 	 * Both PHYs for x64 configuration, if x32, do only PHY0.
 	 */
 	writel(initdelay, &mmdc0->mpwrdlctl);
-	if (sysinfo->dsize == 0x2)
+	if (bus_size == 0x2)
 		writel(initdelay, &mmdc1->mpwrdlctl);
 
 	/*
 	 * XXX This isn't in the manual. Force a measurement,
 	 * for previous delay setup to effect.
 	 */
-	force_delay_measurement(sysinfo->dsize);
+	force_delay_measurement(bus_size);
 
 	/*
 	 * 9. 10. Start the automatic write calibration process
@@ -483,8 +470,7 @@ int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo)
 	if (readl(&mmdc0->mpwrdlhwctl) & 0x0000000f)
 		errors |= 16;
 
-	if ((sysinfo->dsize == 0x2) &&
-	    (readl(&mmdc1->mpwrdlhwctl) & 0x0000000f))
+	if ((bus_size == 0x2) && (readl(&mmdc1->mpwrdlhwctl) & 0x0000000f))
 		errors |= 32;
 
 	debug("Ending Write Delay calibration. Error mask: 0x%x\n", errors);
@@ -536,18 +522,14 @@ int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo)
 	debug("Read DQS gating calibration:\n");
 	debug("\tMPDGCTRL0 PHY0 = 0x%08X\n", readl(&mmdc0->mpdgctrl0));
 	debug("\tMPDGCTRL1 PHY0 = 0x%08X\n", readl(&mmdc0->mpdgctrl1));
-	if (sysinfo->dsize == 2) {
-		debug("\tMPDGCTRL0 PHY1 = 0x%08X\n", readl(&mmdc1->mpdgctrl0));
-		debug("\tMPDGCTRL1 PHY1 = 0x%08X\n", readl(&mmdc1->mpdgctrl1));
-	}
+	debug("\tMPDGCTRL0 PHY1 = 0x%08X\n", readl(&mmdc1->mpdgctrl0));
+	debug("\tMPDGCTRL1 PHY1 = 0x%08X\n", readl(&mmdc1->mpdgctrl1));
 	debug("Read calibration:\n");
 	debug("\tMPRDDLCTL PHY0 = 0x%08X\n", readl(&mmdc0->mprddlctl));
-	if (sysinfo->dsize == 2)
-		debug("\tMPRDDLCTL PHY1 = 0x%08X\n", readl(&mmdc1->mprddlctl));
+	debug("\tMPRDDLCTL PHY1 = 0x%08X\n", readl(&mmdc1->mprddlctl));
 	debug("Write calibration:\n");
 	debug("\tMPWRDLCTL PHY0 = 0x%08X\n", readl(&mmdc0->mpwrdlctl));
-	if (sysinfo->dsize == 2)
-		debug("\tMPWRDLCTL PHY1 = 0x%08X\n", readl(&mmdc1->mpwrdlctl));
+	debug("\tMPWRDLCTL PHY1 = 0x%08X\n", readl(&mmdc1->mpwrdlctl));
 
 	/*
 	 * Registers below are for debugging purposes.  These print out
@@ -559,12 +541,10 @@ int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo)
 	debug("\tMPDGHWST1 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst1));
 	debug("\tMPDGHWST2 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst2));
 	debug("\tMPDGHWST3 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst3));
-	if (sysinfo->dsize == 2) {
-		debug("\tMPDGHWST0 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst0));
-		debug("\tMPDGHWST1 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst1));
-		debug("\tMPDGHWST2 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst2));
-		debug("\tMPDGHWST3 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst3));
-	}
+	debug("\tMPDGHWST0 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst0));
+	debug("\tMPDGHWST1 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst1));
+	debug("\tMPDGHWST2 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst2));
+	debug("\tMPDGHWST3 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst3));
 
 	debug("Final do_dqs_calibration error mask: 0x%x\n", errors);
 
@@ -1500,29 +1480,6 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
 	mdelay(1);
 }
 
-void mmdc_read_calibration(struct mx6_ddr_sysinfo const *sysinfo,
-                           struct mx6_mmdc_calibration *calib)
-{
-	struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
-	struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
-
-	calib->p0_mpwldectrl0 = readl(&mmdc0->mpwldectrl0);
-	calib->p0_mpwldectrl1 = readl(&mmdc0->mpwldectrl1);
-	calib->p0_mpdgctrl0 = readl(&mmdc0->mpdgctrl0);
-	calib->p0_mpdgctrl1 = readl(&mmdc0->mpdgctrl1);
-	calib->p0_mprddlctl = readl(&mmdc0->mprddlctl);
-	calib->p0_mpwrdlctl = readl(&mmdc0->mpwrdlctl);
-
-	if (sysinfo->dsize == 2) {
-		calib->p1_mpwldectrl0 = readl(&mmdc1->mpwldectrl0);
-		calib->p1_mpwldectrl1 = readl(&mmdc1->mpwldectrl1);
-		calib->p1_mpdgctrl0 = readl(&mmdc1->mpdgctrl0);
-		calib->p1_mpdgctrl1 = readl(&mmdc1->mpdgctrl1);
-		calib->p1_mprddlctl = readl(&mmdc1->mprddlctl);
-		calib->p1_mpwrdlctl = readl(&mmdc1->mpwrdlctl);
-	}
-}
-
 void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
 		  const struct mx6_mmdc_calibration *calib,
 		  const void *ddr_cfg)

arch/arm/cpu/armv7/mx6/mp.c

@@ -9,7 +9,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/imx-regs.h>
 

arch/arm/cpu/armv7/mx6/soc.c

@@ -8,7 +8,7 @@
  */
 
 #include <common.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/clock.h>
@@ -126,7 +126,7 @@ u32 get_cpu_speed_grade_hz(void)
 	val >>= OCOTP_CFG3_SPEED_SHIFT;
 	val &= 0x3;
 
-	if (is_mx6ul() || is_mx6ull()) {
+	if (is_mx6ul()) {
 		if (val == OCOTP_CFG3_SPEED_528MHZ)
 			return 528000000;
 		else if (val == OCOTP_CFG3_SPEED_696MHZ)
@@ -293,24 +293,16 @@ static void clear_mmdc_ch_mask(void)
 	reg = readl(&mxc_ccm->ccdr);
 
 	/* Clear MMDC channel mask */
-	if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl())
+	if (is_mx6sx() || is_mx6ul() || is_mx6sl())
 		reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK);
 	else
 		reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
 	writel(reg, &mxc_ccm->ccdr);
 }
 
-#define OCOTP_MEM0_REFTOP_TRIM_SHIFT          8
-
 static void init_bandgap(void)
 {
 	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
-	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
-	struct fuse_bank *bank = &ocotp->bank[1];
-	struct fuse_bank1_regs *fuse =
-		(struct fuse_bank1_regs *)bank->fuse_regs;
-	uint32_t val;
-
 	/*
 	 * Ensure the bandgap has stabilized.
 	 */
@@ -322,28 +314,9 @@ static void init_bandgap(void)
 	 * be set.
 	 */
 	writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
-	/*
-	 * On i.MX6ULL,we need to set VBGADJ bits according to the
-	 * REFTOP_TRIM[3:0] in fuse table
-	 *	000 - set REFTOP_VBGADJ[2:0] to 3b'110,
-	 *	110 - set REFTOP_VBGADJ[2:0] to 3b'000,
-	 *	001 - set REFTOP_VBGADJ[2:0] to 3b'001,
-	 *	010 - set REFTOP_VBGADJ[2:0] to 3b'010,
-	 *	011 - set REFTOP_VBGADJ[2:0] to 3b'011,
-	 *	100 - set REFTOP_VBGADJ[2:0] to 3b'100,
-	 *	101 - set REFTOP_VBGADJ[2:0] to 3b'101,
-	 *	111 - set REFTOP_VBGADJ[2:0] to 3b'111,
-	 */
-	if (is_mx6ull()) {
-		val = readl(&fuse->mem0);
-		val >>= OCOTP_MEM0_REFTOP_TRIM_SHIFT;
-		val &= 0x7;
-
-		writel(val << BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT,
-		       &anatop->ana_misc0_set);
-	}
 }
 
+
 #ifdef CONFIG_MX6SL
 static void set_preclk_from_osc(void)
 {
@@ -370,7 +343,7 @@ int arch_cpu_init(void)
 	 */
 	init_bandgap();
 
-	if (!is_mx6ul() && !is_mx6ull()) {
+	if (!IS_ENABLED(CONFIG_MX6UL)) {
 		/*
 		 * When low freq boot is enabled, ROM will not set AHB
 		 * freq, so we need to ensure AHB freq is 132MHz in such
@@ -383,41 +356,14 @@ int arch_cpu_init(void)
 			set_ahb_rate(132000000);
 	}
 
-	if (is_mx6ul()) {
-		if (is_soc_rev(CHIP_REV_1_0) == 0) {
-			/*
-			 * According to the design team's requirement on
-			 * i.MX6UL,the PMIC_STBY_REQ PAD should be configured
-			 * as open drain 100K (0x0000b8a0).
-			 * Only exists on TO1.0
-			 */
-			writel(0x0000b8a0, IOMUXC_BASE_ADDR + 0x29c);
-		} else {
-			/*
-			 * From TO1.1, SNVS adds internal pull up control
-			 * for POR_B, the register filed is GPBIT[1:0],
-			 * after system boot up, it can be set to 2b'01
-			 * to disable internal pull up.It can save about
-			 * 30uA power in SNVS mode.
-			 */
-			writel((readl(MX6UL_SNVS_LP_BASE_ADDR + 0x10) &
-			       (~0x1400)) | 0x400,
-			       MX6UL_SNVS_LP_BASE_ADDR + 0x10);
-		}
-	}
-
-	if (is_mx6ull()) {
+	if (IS_ENABLED(CONFIG_MX6UL) && is_soc_rev(CHIP_REV_1_0) == 0) {
 		/*
-		 * GPBIT[1:0] is suggested to set to 2'b11:
-		 * 2'b00 : always PUP100K
-		 * 2'b01 : PUP100K when PMIC_ON_REQ or SOC_NOT_FAIL
-		 * 2'b10 : always disable PUP100K
-		 * 2'b11 : PDN100K when SOC_FAIL, PUP100K when SOC_NOT_FAIL
-		 * register offset is different from i.MX6UL, since
-		 * i.MX6UL is fixed by ECO.
+		 * According to the design team's requirement on i.MX6UL,
+		 * the PMIC_STBY_REQ PAD should be configured as open
+		 * drain 100K (0x0000b8a0).
+		 * Only exists on TO1.0
 		 */
-		writel(readl(MX6UL_SNVS_LP_BASE_ADDR) |
-			0x3, MX6UL_SNVS_LP_BASE_ADDR);
+		writel(0x0000b8a0, IOMUXC_BASE_ADDR + 0x29c);
 	}
 
 	/* Set perclk to source from OSC 24MHz */
@@ -513,7 +459,7 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 	struct fuse_bank4_regs *fuse =
 			(struct fuse_bank4_regs *)bank->fuse_regs;
 
-	if ((is_mx6sx() || is_mx6ul() || is_mx6ull()) && dev_id == 1) {
+	if ((is_mx6sx() || is_mx6ul()) && dev_id == 1) {
 		u32 value = readl(&fuse->mac_addr2);
 		mac[0] = value >> 24 ;
 		mac[1] = value >> 16 ;
@@ -548,7 +494,7 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 const struct boot_mode soc_boot_modes[] = {
 	{"normal",	MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
 	/* reserved value should start rom usb */
-	{"usb",		MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
+	{"usb",		MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
 	{"sata",	MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
 	{"ecspi1:0",	MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
 	{"ecspi1:1",	MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
@@ -577,7 +523,7 @@ void s_init(void)
 	u32 mask528;
 	u32 reg, periph1, periph2;
 
-	if (is_mx6sx() || is_mx6ul() || is_mx6ull())
+	if (is_mx6sx() || is_mx6ul())
 		return;
 
 	/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs

arch/arm/cpu/armv7/mx7/clock.c

@@ -10,7 +10,7 @@
 #include <common.h>
 #include <div64.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>

arch/arm/cpu/armv7/mx7/clock_slice.c

@@ -10,7 +10,7 @@
 #include <common.h>
 #include <div64.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>

arch/arm/cpu/armv7/omap-common/Kconfig

@@ -1,6 +1,6 @@
 config TI_SECURE_DEVICE
 	bool "HS Device Type Support"
-	depends on OMAP54XX || AM43XX || AM33XX
+	depends on OMAP54XX || AM43XX
 	help
 	  If a high secure (HS) device type is being used, this config
 	  must be set. This option impacts various aspects of the
@@ -8,10 +8,10 @@ config TI_SECURE_DEVICE
 	  authenticated) and the code. See the doc/README.ti-secure
 	  file for further details.
 
-source "arch/arm/mach-omap2/omap3/Kconfig"
+source "arch/arm/cpu/armv7/omap3/Kconfig"
 
-source "arch/arm/mach-omap2/omap4/Kconfig"
+source "arch/arm/cpu/armv7/omap4/Kconfig"
 
-source "arch/arm/mach-omap2/omap5/Kconfig"
+source "arch/arm/cpu/armv7/omap5/Kconfig"
 
-source "arch/arm/mach-omap2/am33xx/Kconfig"
+source "arch/arm/cpu/armv7/am33xx/Kconfig"

arch/arm/cpu/armv7/omap-common/Makefile

@@ -5,12 +5,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-$(if $(filter am33xx,$(SOC)),y) += am33xx/
-obj-$(CONFIG_OMAP34XX) += omap3/
-obj-$(CONFIG_OMAP44XX) += omap4/
-obj-$(CONFIG_OMAP54XX) += omap5/
-
-obj-y	+= reset.o
+obj-y	:= reset.o
 ifeq ($(CONFIG_TIMER),)
 obj-y	+= timer.o
 else

arch/arm/cpu/armv7/omap-common/boot-common.c

@@ -90,11 +90,6 @@ void save_omap_boot_params(void)
 		case BOOT_DEVICE_CPGMAC:
 			sys_boot_device = 1;
 			break;
-#endif
-#if defined(BOOT_DEVICE_DFU) && !defined(CONFIG_SPL_DFU_SUPPORT)
-		case BOOT_DEVICE_DFU:
-			sys_boot_device = 1;
-			break;
 #endif
 	}
 

arch/arm/cpu/armv7/omap-common/clocks-common.c

@@ -477,45 +477,35 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic)
 		gpio_direction_output(pmic->gpio, 1);
 }
 
-int __weak get_voltrail_opp(int rail_offset)
-{
-	/*
-	 * By default return OPP_NOM for all voltage rails.
-	 */
-	return OPP_NOM;
-}
-
-static u32 optimize_vcore_voltage(struct volts const *v, int opp)
+static u32 optimize_vcore_voltage(struct volts const *v)
 {
 	u32 val;
-
-	if (!v->value[opp])
+	if (!v->value)
 		return 0;
-	if (!v->efuse.reg[opp])
-		return v->value[opp];
+	if (!v->efuse.reg)
+		return v->value;
 
 	switch (v->efuse.reg_bits) {
 	case 16:
-		val = readw(v->efuse.reg[opp]);
+		val = readw(v->efuse.reg);
 		break;
 	case 32:
-		val = readl(v->efuse.reg[opp]);
+		val = readl(v->efuse.reg);
 		break;
 	default:
 		printf("Error: efuse 0x%08x bits=%d unknown\n",
-		       v->efuse.reg[opp], v->efuse.reg_bits);
-		return v->value[opp];
+		       v->efuse.reg, v->efuse.reg_bits);
+		return v->value;
 	}
 
 	if (!val) {
 		printf("Error: efuse 0x%08x bits=%d val=0, using %d\n",
-		       v->efuse.reg[opp], v->efuse.reg_bits, v->value[opp]);
-		return v->value[opp];
+		       v->efuse.reg, v->efuse.reg_bits, v->value);
+		return v->value;
 	}
 
 	debug("%s:efuse 0x%08x bits=%d Vnom=%d, using efuse value %d\n",
-	      __func__, v->efuse.reg[opp], v->efuse.reg_bits, v->value[opp],
-	      val);
+	      __func__, v->efuse.reg, v->efuse.reg_bits, v->value, val);
 	return val;
 }
 
@@ -539,19 +529,16 @@ void __weak recalibrate_iodelay(void)
  */
 void scale_vcores(struct vcores_data const *vcores)
 {
-	int i, opp, j, ol;
+	int i;
 	struct volts *pv = (struct volts *)vcores;
 	struct volts *px;
 
 	for (i=0; i<(sizeof(struct vcores_data)/sizeof(struct volts)); i++) {
-		opp = get_voltrail_opp(i);
-		debug("%d -> ", pv->value[opp]);
-
-		if (pv->value[opp]) {
+		debug("%d -> ", pv->value);
+		if (pv->value) {
 			/* Handle non-empty members only */
-			pv->value[opp] = optimize_vcore_voltage(pv, opp);
+			pv->value = optimize_vcore_voltage(pv);
      			px = (struct volts *)vcores;
-			j = 0;
 			while (px < pv) {
 				/*
 				 * Scan already handled non-empty members to see
@@ -560,29 +547,26 @@ void scale_vcores(struct vcores_data const *vcores)
 				 * particular SMPS; the other group voltages are
 				 * zeroed.
 				 */
-				ol = get_voltrail_opp(j);
-				if (px->value[ol] &&
-				    (pv->pmic->i2c_slave_addr ==
-				     px->pmic->i2c_slave_addr) &&
-				    (pv->addr == px->addr)) {
-					/* Same PMIC, same SMPS */
-					if (pv->value[opp] > px->value[ol])
-						px->value[ol] = pv->value[opp];
+				if (px->value) {
+					if ((pv->pmic->i2c_slave_addr ==
+					     px->pmic->i2c_slave_addr) &&
+					    (pv->addr == px->addr)) {
+					    	/* Same PMIC, same SMPS */
+						if (pv->value > px->value)
+							px->value = pv->value;
 
-					pv->value[opp] = 0;
-				}
+						pv->value = 0;
+					}
+		     		}
 				px++;
-				j++;
 			}
 		}
-		debug("%d\n", pv->value[opp]);
+	     	debug("%d\n", pv->value);
 		pv++;
 	}
 
-	opp = get_voltrail_opp(VOLT_CORE);
-	debug("cor: %d\n", vcores->core.value[opp]);
-	do_scale_vcore(vcores->core.addr, vcores->core.value[opp],
-		       vcores->core.pmic);
+	debug("cor: %d\n", vcores->core.value);
+	do_scale_vcore(vcores->core.addr, vcores->core.value, vcores->core.pmic);
 	/*
 	 * IO delay recalibration should be done immediately after
 	 * adjusting AVS voltages for VDD_CORE_L.
@@ -593,12 +577,10 @@ void scale_vcores(struct vcores_data const *vcores)
 	recalibrate_iodelay();
 #endif
 
-	opp = get_voltrail_opp(VOLT_MPU);
-	debug("mpu: %d\n", vcores->mpu.value[opp]);
-	do_scale_vcore(vcores->mpu.addr, vcores->mpu.value[opp],
-		       vcores->mpu.pmic);
+	debug("mpu: %d\n", vcores->mpu.value);
+	do_scale_vcore(vcores->mpu.addr, vcores->mpu.value, vcores->mpu.pmic);
 	/* Configure MPU ABB LDO after scale */
-	abb_setup(vcores->mpu.efuse.reg[opp],
+	abb_setup(vcores->mpu.efuse.reg,
 		  (*ctrl)->control_wkup_ldovbb_mpu_voltage_ctrl,
 		  (*prcm)->prm_abbldo_mpu_setup,
 		  (*prcm)->prm_abbldo_mpu_ctrl,
@@ -606,12 +588,10 @@ void scale_vcores(struct vcores_data const *vcores)
 		  vcores->mpu.abb_tx_done_mask,
 		  OMAP_ABB_FAST_OPP);
 
-	opp = get_voltrail_opp(VOLT_MM);
-	debug("mm: %d\n", vcores->mm.value[opp]);
-	do_scale_vcore(vcores->mm.addr, vcores->mm.value[opp],
-		       vcores->mm.pmic);
+	debug("mm: %d\n", vcores->mm.value);
+	do_scale_vcore(vcores->mm.addr, vcores->mm.value, vcores->mm.pmic);
 	/* Configure MM ABB LDO after scale */
-	abb_setup(vcores->mm.efuse.reg[opp],
+	abb_setup(vcores->mm.efuse.reg,
 		  (*ctrl)->control_wkup_ldovbb_mm_voltage_ctrl,
 		  (*prcm)->prm_abbldo_mm_setup,
 		  (*prcm)->prm_abbldo_mm_ctrl,
@@ -619,38 +599,30 @@ void scale_vcores(struct vcores_data const *vcores)
 		  vcores->mm.abb_tx_done_mask,
 		  OMAP_ABB_FAST_OPP);
 
-	opp = get_voltrail_opp(VOLT_GPU);
-	debug("gpu: %d\n", vcores->gpu.value[opp]);
-	do_scale_vcore(vcores->gpu.addr, vcores->gpu.value[opp],
-		       vcores->gpu.pmic);
+	debug("gpu: %d\n", vcores->gpu.value);
+	do_scale_vcore(vcores->gpu.addr, vcores->gpu.value, vcores->gpu.pmic);
 	/* Configure GPU ABB LDO after scale */
-	abb_setup(vcores->gpu.efuse.reg[opp],
+	abb_setup(vcores->gpu.efuse.reg,
 		  (*ctrl)->control_wkup_ldovbb_gpu_voltage_ctrl,
 		  (*prcm)->prm_abbldo_gpu_setup,
 		  (*prcm)->prm_abbldo_gpu_ctrl,
 		  (*prcm)->prm_irqstatus_mpu,
 		  vcores->gpu.abb_tx_done_mask,
 		  OMAP_ABB_FAST_OPP);
-
-	opp = get_voltrail_opp(VOLT_EVE);
-	debug("eve: %d\n", vcores->eve.value[opp]);
-	do_scale_vcore(vcores->eve.addr, vcores->eve.value[opp],
-		       vcores->eve.pmic);
+	debug("eve: %d\n", vcores->eve.value);
+	do_scale_vcore(vcores->eve.addr, vcores->eve.value, vcores->eve.pmic);
 	/* Configure EVE ABB LDO after scale */
-	abb_setup(vcores->eve.efuse.reg[opp],
+	abb_setup(vcores->eve.efuse.reg,
 		  (*ctrl)->control_wkup_ldovbb_eve_voltage_ctrl,
 		  (*prcm)->prm_abbldo_eve_setup,
 		  (*prcm)->prm_abbldo_eve_ctrl,
 		  (*prcm)->prm_irqstatus_mpu,
 		  vcores->eve.abb_tx_done_mask,
 		  OMAP_ABB_FAST_OPP);
-
-	opp = get_voltrail_opp(VOLT_IVA);
-	debug("iva: %d\n", vcores->iva.value[opp]);
-	do_scale_vcore(vcores->iva.addr, vcores->iva.value[opp],
-		       vcores->iva.pmic);
+	debug("iva: %d\n", vcores->iva.value);
+	do_scale_vcore(vcores->iva.addr, vcores->iva.value, vcores->iva.pmic);
 	/* Configure IVA ABB LDO after scale */
-	abb_setup(vcores->iva.efuse.reg[opp],
+	abb_setup(vcores->iva.efuse.reg,
 		  (*ctrl)->control_wkup_ldovbb_iva_voltage_ctrl,
 		  (*prcm)->prm_abbldo_iva_setup,
 		  (*prcm)->prm_abbldo_iva_ctrl,

arch/arm/cpu/armv7/omap-common/config_secure.mk

@@ -3,7 +3,7 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 #
-quiet_cmd_mkomapsecimg = SECURE  $@
+quiet_cmd_mkomapsecimg = MKIMAGE $@
 ifneq ($(TI_SECURE_DEV_PKG),)
 ifneq ($(wildcard $(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh),)
 ifneq ($(CONFIG_SPL_BUILD),)
@@ -18,12 +18,11 @@ endif
 else
 cmd_mkomapsecimg = echo "WARNING:" \
 	"$(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh not found." \
-	"$@ was NOT secured!"; cp $< $@
+	"$@ was NOT created!"
 endif
 else
 cmd_mkomapsecimg = echo "WARNING: TI_SECURE_DEV_PKG environment" \
-	"variable must be defined for TI secure devices. \
-	$@ was NOT secured!"; cp $< $@
+	"variable must be defined for TI secure devices. $@ was NOT created!"
 endif
 
 ifdef CONFIG_SPL_LOAD_FIT
@@ -36,51 +35,51 @@ cmd_omapsecureimg = $(TI_SECURE_DEV_PKG)/scripts/secure-binary-image.sh \
 else
 cmd_omapsecureimg = echo "WARNING:" \
 	"$(TI_SECURE_DEV_PKG)/scripts/secure-binary-image.sh not found." \
-	"$@ was NOT secured!"; cp $< $@
+	"$@ was NOT created!"; cp $< $@
 endif
 else
 cmd_omapsecureimg = echo "WARNING: TI_SECURE_DEV_PKG environment" \
 	"variable must be defined for TI secure devices." \
-	"$@ was NOT secured!"; cp $< $@
+	"$@ was NOT created!"; cp $< $@
 endif
 endif
 
 
 # Standard X-LOADER target (QPSI, NOR flash)
-u-boot-spl_HS_X-LOADER: $(obj)/u-boot-spl.bin FORCE
+u-boot-spl_HS_X-LOADER: $(obj)/u-boot-spl.bin
 	$(call if_changed,mkomapsecimg)
 
 # For MLO targets (SD card boot) the final file name that is copied to the SD
 # card FAT partition must be MLO, so we make a copy of the output file to a new
 # file with that name
-u-boot-spl_HS_MLO: $(obj)/u-boot-spl.bin FORCE
+u-boot-spl_HS_MLO: $(obj)/u-boot-spl.bin
 	$(call if_changed,mkomapsecimg)
 	@if [ -f $@ ]; then \
 		cp -f $@ MLO; \
 	fi
 
 # Standard 2ND target (certain peripheral boot modes)
-u-boot-spl_HS_2ND: $(obj)/u-boot-spl.bin FORCE
+u-boot-spl_HS_2ND: $(obj)/u-boot-spl.bin
 	$(call if_changed,mkomapsecimg)
 
 # Standard ULO target (certain peripheral boot modes)
-u-boot-spl_HS_ULO: $(obj)/u-boot-spl.bin FORCE
+u-boot-spl_HS_ULO: $(obj)/u-boot-spl.bin
 	$(call if_changed,mkomapsecimg)
 
 # Standard ISSW target (certain devices, various boot modes)
-u-boot-spl_HS_ISSW: $(obj)/u-boot-spl.bin FORCE
+u-boot-spl_HS_ISSW: $(obj)/u-boot-spl.bin
 	$(call if_changed,mkomapsecimg)
 
 # For SPI flash on AM335x and AM43xx, these require special byte swap handling
 # so we use the SPI_X-LOADER target instead of X-LOADER and let the
 # create-boot-image.sh script handle that
-u-boot-spl_HS_SPI_X-LOADER: $(obj)/u-boot-spl.bin FORCE
+u-boot-spl_HS_SPI_X-LOADER: $(obj)/u-boot-spl.bin
 	$(call if_changed,mkomapsecimg)
 
 # For supporting single stage XiP QSPI on AM43xx, the image is a full u-boot
 # file, not an SPL. In this case the mkomapsecimg command looks for a
 # u-boot-HS_* prefix
-u-boot_HS_XIP_X-LOADER: $(obj)/u-boot.bin FORCE
+u-boot_HS_XIP_X-LOADER: $(obj)/u-boot.bin
 	$(call if_changed,mkomapsecimg)
 
 # For supporting the SPL loading and interpreting of FIT images whose
@@ -91,18 +90,21 @@ ifdef CONFIG_SPL_LOAD_FIT
 MKIMAGEFLAGS_u-boot_HS.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
 	-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
 	-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \
-	$(patsubst %,-b arch/$(ARCH)/dts/%.dtb_HS,$(subst ",,$(CONFIG_OF_LIST)))
+	$(patsubst %,-b arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST)))
 
 OF_LIST_TARGETS = $(patsubst %,arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST)))
 $(OF_LIST_TARGETS): dtbs
 
-%.dtb_HS: %.dtb FORCE
+%_HS.dtb: %.dtb
+	$(call if_changed,omapsecureimg)
+	$(Q)if [ -f $@ ]; then \
+		cp -f $@ $<; \
+	fi
+
+u-boot-nodtb_HS.bin: u-boot-nodtb.bin
 	$(call if_changed,omapsecureimg)
 
-u-boot-nodtb_HS.bin: u-boot-nodtb.bin FORCE
-	$(call if_changed,omapsecureimg)
-
-u-boot_HS.img: u-boot-nodtb_HS.bin u-boot.img $(patsubst %.dtb,%.dtb_HS,$(OF_LIST_TARGETS)) FORCE
+u-boot_HS.img: u-boot-nodtb_HS.bin u-boot.img $(patsubst %.dtb,%_HS.dtb,$(OF_LIST_TARGETS))
 	$(call if_changed,mkimage)
 	$(Q)if [ -f $@ ]; then \
 		cp -f $@ u-boot.img; \

arch/arm/cpu/armv7/omap-common/emif-common.c

@@ -14,7 +14,6 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/omap_common.h>
-#include <asm/omap_sec_common.h>
 #include <asm/utils.h>
 #include <linux/compiler.h>
 
@@ -1478,20 +1477,6 @@ void sdram_init(void)
 			debug("get_ram_size() successful");
 	}
 
-#if defined(CONFIG_TI_SECURE_DEVICE)
-	/*
-	 * On HS devices, do static EMIF firewall configuration
-	 * but only do it if not already running in SDRAM
-	 */
-	if (!in_sdram)
-		if (0 != secure_emif_reserve())
-			hang();
-
-	/* On HS devices, ensure static EMIF firewall APIs are locked */
-	if (0 != secure_emif_firewall_lock())
-		hang();
-#endif
-
 	if (sdram_type == EMIF_SDRAM_TYPE_DDR3 &&
 	    (!in_sdram && !warm_reset()) && (!is_dra7xx())) {
 		if (emif1_enabled)

arch/arm/cpu/armv7/omap-common/lowlevel_init.S

@@ -24,30 +24,6 @@ ENTRY(save_boot_params)
 	str	r0, [r1]
 	b	save_boot_params_ret
 ENDPROC(save_boot_params)
-
-#if !defined(CONFIG_TI_SECURE_DEVICE) && defined(CONFIG_ARMV7_LPAE)
-ENTRY(switch_to_hypervisor)
-
-/*
- * Switch to hypervisor mode
- */
-	adr	r0, save_sp
-	str	sp, [r0]
-	adr	r1, restore_from_hyp
-	ldr	r0, =0x102
-	b	omap_smc1
-restore_from_hyp:
-	adr	r0, save_sp
-	ldr	sp, [r0]
-	MRC p15, 4, R0, c1, c0, 0
-	ldr     r1, =0X1004	@Set cache enable bits for hypervisor mode
-	orr     r0, r0, r1
-	MCR p15, 4, R0, c1, c0, 0
-	b	switch_to_hypervisor_ret
-save_sp:
-	.word	0x0
-ENDPROC(switch_to_hypervisor)
-#endif
 #endif
 
 ENTRY(omap_smc1)

arch/arm/cpu/armv7/omap-common/omap-cache.c

@@ -17,28 +17,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-/*
- * Without LPAE short descriptors are used
- * Set C - Cache Bit3
- * Set B - Buffer Bit2
- * The last 2 bits set to 0b10
- * Do Not set XN bit4
- * So value is 0xe
- *
- * With LPAE cache configuration happens via MAIR0 register
- * AttrIndx value is 0x3 for picking byte3 for MAIR0 which has 0xFF.
- * 0xFF maps to Cache writeback with Read and Write Allocate set
- * The bits[1:0] should have the value 0b01 for the first level
- * descriptor.
- * So the value is 0xd
- */
-
-#ifdef CONFIG_ARMV7_LPAE
-#define ARMV7_DCACHE_POLICY	DCACHE_WRITEALLOC
-#else
-#define ARMV7_DCACHE_POLICY	DCACHE_WRITEBACK & ~TTB_SECT_XN_MASK
-#endif
-
+#define ARMV7_DCACHE_WRITEBACK  0xe
 #define ARMV7_DOMAIN_CLIENT	1
 #define ARMV7_DOMAIN_MASK	(0x3 << 0)
 
@@ -53,13 +32,13 @@ void dram_bank_mmu_setup(int bank)
 	bd_t *bd = gd->bd;
 	int	i;
 
-	u32 start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
-	u32 size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT;
+	u32 start = bd->bi_dram[bank].start >> 20;
+	u32 size = bd->bi_dram[bank].size >> 20;
 	u32 end = start + size;
 
 	debug("%s: bank: %d\n", __func__, bank);
 	for (i = start; i < end; i++)
-		set_section_dcache(i, ARMV7_DCACHE_POLICY);
+		set_section_dcache(i, ARMV7_DCACHE_WRITEBACK);
 }
 
 void arm_init_domains(void)

arch/arm/cpu/armv7/omap-common/pipe3-phy.c

@@ -12,7 +12,7 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/io.h>
-#include <linux/errno.h>
+#include <asm/errno.h>
 #include "pipe3-phy.h"
 
 /* PLLCTRL Registers */

arch/arm/cpu/armv7/omap3/Kconfig

@@ -1,38 +1,5 @@
 if OMAP34XX
 
-config SPL_EXT_SUPPORT
-	default y
-
-config SPL_FAT_SUPPORT
-	default y
-
-config SPL_GPIO_SUPPORT
-	default y
-
-config SPL_I2C_SUPPORT
-	default y
-
-config SPL_LIBCOMMON_SUPPORT
-	default y
-
-config SPL_LIBDISK_SUPPORT
-	default y
-
-config SPL_LIBGENERIC_SUPPORT
-	default y
-
-config SPL_MMC_SUPPORT
-	default y
-
-config SPL_NAND_SUPPORT
-	default y
-
-config SPL_POWER_SUPPORT
-	default y
-
-config SPL_SERIAL_SUPPORT
-	default y
-
 choice
 	prompt "OMAP3 board select"
 	optional

arch/arm/cpu/armv7/omap3/am35x_musb.c

@@ -13,7 +13,7 @@
 #include <asm/io.h>
 #include <asm/arch/am35x_def.h>
 
-void am35x_musb_reset(struct udevice *dev)
+void am35x_musb_reset(void)
 {
 	/* Reset the musb interface */
 	clrsetbits_le32(&am35x_scm_general_regs->ip_sw_reset,
@@ -22,7 +22,7 @@ void am35x_musb_reset(struct udevice *dev)
 			USBOTGSS_SW_RST, 0);
 }
 
-void am35x_musb_phy_power(struct udevice *dev, u8 on)
+void am35x_musb_phy_power(u8 on)
 {
 	unsigned long start = get_timer(0);
 
@@ -53,7 +53,7 @@ void am35x_musb_phy_power(struct udevice *dev, u8 on)
 	}
 }
 
-void am35x_musb_clear_irq(struct udevice *dev)
+void am35x_musb_clear_irq(void)
 {
 	clrsetbits_le32(&am35x_scm_general_regs->lvl_intr_clr,
 			0, USBOTGSS_INT_CLR);

arch/arm/cpu/armv7/omap3/config.mk

@@ -0,0 +1,15 @@
+#
+# Copyright 2011 Linaro Limited
+#
+# (C) Copyright 2010
+# Texas Instruments, <www.ti.com>
+#
+# Aneesh V <aneesh@ti.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+ifdef CONFIG_SPL_BUILD
+ALL-y	+= MLO
+else
+ALL-y	+= u-boot.img
+endif