Prepare v2017.07

Signed-off-by: Tom Rini <trini@konsulko.com>

.travis.yml

@@ -60,7 +60,6 @@ env:
 
 before_script:
   # install toolchains based on TOOLCHAIN} variable
-  - if [[ "${TOOLCHAIN}" == *avr32* ]]; then ./tools/buildman/buildman --fetch-arch avr32 ; fi
   - if [[ "${TOOLCHAIN}" == *m68k* ]]; then ./tools/buildman/buildman --fetch-arch m68k ; fi
   - if [[ "${TOOLCHAIN}" == *microblaze* ]]; then ./tools/buildman/buildman --fetch-arch microblaze ; fi
   - if [[ "${TOOLCHAIN}" == *mips* ]]; then ./tools/buildman/buildman --fetch-arch mips ; fi
@@ -138,12 +137,9 @@ matrix:
     - env:
         - BUILDMAN="arm946es"
     - env:
-        - BUILDMAN="atmel -x avr32"
+        - BUILDMAN="atmel"
     - env:
-        - BUILDMAN="avr32"
-          TOOLCHAIN="avr32"
-    - env:
-        - BUILDMAN="denx"
+        - BUILDMAN="aries"
     - env:
         - JOB="Freescale ARM32"
           BUILDMAN="freescale -x powerpc,m68k,aarch64"
@@ -174,7 +170,7 @@ matrix:
         - BUILDMAN="sun50i"
     - env:
         - JOB="Catch-all ARM"
-          BUILDMAN="arm -x arm11,arm7,arm9,aarch64,atmel,denx,freescale,kirkwood,mvebu,siemens,tegra,uniphier,mx,samsung,sunxi,am33xx,omap3,omap4,omap5,pxa,rockchip"
+          BUILDMAN="arm -x arm11,arm7,arm9,aarch64,atmel,aries,freescale,kirkwood,mvebu,siemens,tegra,uniphier,mx,samsung,sunxi,am33xx,omap3,omap4,omap5,pxa,rockchip"
     - env:
         - BUILDMAN="sandbox x86"
           TOOLCHAIN="x86_64"
@@ -209,6 +205,8 @@ matrix:
         - BUILDMAN="corenet_ds b4860qds sbc8548 bsc91*"
     - env:
         - BUILDMAN="mpc86xx"
+    - env:
+        - BUILDMAN="mpc8xx"
     - env:
         - BUILDMAN="siemens"
     - env:

MAINTAINERS

@@ -78,8 +78,8 @@ T:	git git://git.denx.de/u-boot-atmel.git
 F:	arch/arm/mach-at91/
 
 ARM BROADCOM BCM283X
-M:	Stephen Warren <swarren@wwwdotorg.org>
-S:	Maintained
+#M:	Stephen Warren <swarren@wwwdotorg.org>
+S:	Orphaned (Since 2017-07)
 F:	arch/arm/mach-bcm283x/
 F:	drivers/gpio/bcm2835_gpio.c
 F:	drivers/mmc/bcm2835_sdhci.c
@@ -89,6 +89,7 @@ F:	include/dm/platform_data/serial_bcm283x_mu.h
 
 ARM FREESCALE IMX
 M:	Stefano Babic <sbabic@denx.de>
+M:	Fabio Estevam <fabio.estevam@nxp.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-imx.git
 F:	arch/arm/cpu/arm1136/mx*/
@@ -132,6 +133,7 @@ F:	arch/arm/mach-rmobile/
 
 ARM ROCKCHIP
 M:	Simon Glass <sjg@chromium.org>
+M:	Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-rockchip.git
 F:	arch/arm/mach-rockchip/
@@ -219,12 +221,6 @@ S:	Maintained
 F:	arch/arm/cpu/armv8/zynqmp/
 F:	arch/arm/include/asm/arch-zynqmp/
 
-AVR32
-M:	Andreas Bießmann <andreas@biessmann.org>
-S:	Maintained
-T:	git git://git.denx.de/u-boot-avr32.git
-F:	arch/avr32/
-
 BUILDMAN
 M:	Simon Glass <sjg@chromium.org>
 S:	Maintained
@@ -262,6 +258,7 @@ F:	test/dm/
 EFI PAYLOAD
 M:	Alexander Graf <agraf@suse.de>
 S:	Maintained
+T:	git git://github.com/agraf/u-boot.git
 F:	include/efi_loader.h
 F:	lib/efi_loader/
 F:	cmd/bootefi.c
@@ -322,7 +319,7 @@ S:	Maintained
 F:	arch/powerpc/
 
 POWERPC MPC8XX
-M:	Wolfgang Denk <wd@denx.de>
+M:	Christophe Leroy <christophe.leroy@c-s.fr>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-mpc8xx.git
 F:	arch/powerpc/cpu/mpc8xx/

Makefile

@@ -5,7 +5,7 @@
 VERSION = 2017
 PATCHLEVEL = 07
 SUBLEVEL =
-EXTRAVERSION = -rc2
+EXTRAVERSION =
 NAME =
 
 # *DOCUMENTATION*

README

@@ -136,7 +136,6 @@ Directory Hierarchy:
 /arch			Architecture specific files
   /arc			Files generic to ARC architecture
   /arm			Files generic to ARM architecture
-  /avr32		Files generic to AVR32 architecture
   /m68k			Files generic to m68k architecture
   /microblaze		Files generic to microblaze architecture
   /mips			Files generic to MIPS architecture
@@ -320,9 +319,6 @@ The following options need to be configured:
 
 - Board Type:	Define exactly one, e.g. CONFIG_MPC8540ADS.
 
-- CPU Daughterboard Type: (if CONFIG_ATSTK1000 is defined)
-		Define exactly one, e.g. CONFIG_ATSTK1002
-
 - Marvell Family Member
 		CONFIG_SYS_MVFS		- define it if you want to enable
 					  multiple fs option at one time
@@ -833,8 +829,6 @@ The following options need to be configured:
 		CONFIG_SCSI		* SCSI Support
 		CONFIG_CMD_SDRAM	* print SDRAM configuration information
 					  (requires CONFIG_CMD_I2C)
-		CONFIG_CMD_SETGETDCR	  Support for DCR Register access
-					  (4xx only)
 		CONFIG_CMD_SF		* Read/write/erase SPI NOR flash
 		CONFIG_CMD_SOFTSWITCH	* Soft switch setting command for BF60x
 		CONFIG_CMD_SOURCE	  "source" command Support
@@ -862,7 +856,7 @@ The following options need to be configured:
 		(configuration option CONFIG_CMD_CACHE) unless you know
 		what you (and your U-Boot users) are doing. Data
 		cache cannot be enabled on systems like the
-		8260 (where accesses to the IMMR region must be
+		8xx (where accesses to the IMMR region must be
 		uncached), and it cannot be disabled on all other
 		systems where we (mis-) use the data cache to hold an
 		initial stack and some data.
@@ -925,9 +919,11 @@ The following options need to be configured:
 		CONFIG_WATCHDOG
 		If this variable is defined, it enables watchdog
 		support for the SoC. There must be support in the SoC
-		specific code for a watchdog. When supported for a
-		specific SoC is available, then no further board specific
-		code should be needed to use it.
+		specific code for a watchdog. For the 8xx
+		CPUs, the SIU Watchdog feature is enabled in the SYPCR
+		register.  When supported for a specific SoC is
+		available, then no further board specific code should
+		be needed to use it.
 
 		CONFIG_HW_WATCHDOG
 		When using a watchdog circuitry external to the used
@@ -2534,12 +2530,6 @@ The following options need to be configured:
 		Define this option to include a destructive SPI flash
 		test ('sf test').
 
-		CONFIG_SF_DUAL_FLASH		Dual flash memories
-
-		Define this option to use dual flash support where two flash
-		memories can be connected with a given cs line.
-		Currently Xilinx Zynq qspi supports these type of connections.
-
 - SystemACE Support:
 		CONFIG_SYSTEMACE
 
@@ -3944,7 +3934,7 @@ Low Level (hardware related) configuration options:
 
 - CONFIG_SYS_IMMR:	Physical address of the Internal Memory.
 		DO NOT CHANGE unless you know exactly what you're
-		doing! (11-4) [82xx systems only]
+		doing! (11-4) [MPC8xx systems only]
 
 - CONFIG_SYS_INIT_RAM_ADDR:
 
@@ -3957,7 +3947,7 @@ Low Level (hardware related) configuration options:
 		sequences.
 
 		U-Boot uses the following memory types:
-		- PPC4xx:  data cache
+		- MPC8xx: IMMR (internal memory of the CPU)
 
 - CONFIG_SYS_GBL_DATA_OFFSET:
 
@@ -3996,10 +3986,6 @@ Low Level (hardware related) configuration options:
   CONFIG_SYS_OR3_PRELIM, CONFIG_SYS_BR3_PRELIM:
 		Memory Controller Definitions: BR2/3 and OR2/3 (SDRAM)
 
-- CONFIG_PCI_DISABLE_PCIE:
-		Disable PCI-Express on systems where it is supported but not
-		required.
-
 - CONFIG_PCI_ENUM_ONLY
 		Only scan through and get the devices on the buses.
 		Don't do any setup work, presumably because someone or
@@ -4823,9 +4809,9 @@ details; basically, the header defines the following image properties:
   LynxOS, pSOS, QNX, RTEMS, INTEGRITY;
   Currently supported: Linux, NetBSD, VxWorks, QNX, RTEMS, LynxOS,
   INTEGRITY).
-* Target CPU Architecture (Provisions for Alpha, ARM, AVR32, Intel x86,
+* Target CPU Architecture (Provisions for Alpha, ARM, Intel x86,
   IA64, MIPS, NDS32, Nios II, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit;
-  Currently supported: ARM, AVR32, Intel x86, MIPS, NDS32, Nios II, PowerPC).
+  Currently supported: ARM, Intel x86, MIPS, NDS32, Nios II, PowerPC).
 * Compression Type (uncompressed, gzip, bzip2)
 * Load Address
 * Entry Point

api/api_platform-powerpc.c

@@ -30,7 +30,7 @@ int platform_sys_info(struct sys_info *si)
 	si->clk_bus = gd->bus_clk;
 	si->clk_cpu = gd->cpu_clk;
 
-#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
+#if defined(CONFIG_8xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
 #define bi_bar	bi_immr_base
 #elif defined(CONFIG_MPC83xx)
 #define bi_bar	bi_immrbar

api/api_storage.c

@@ -43,6 +43,9 @@ struct stor_spec {
 
 static struct stor_spec specs[ENUM_MAX] = { { 0, 0, 0, 0, NULL }, };
 
+#ifndef CONFIG_SYS_MMC_MAX_DEVICE
+#define CONFIG_SYS_MMC_MAX_DEVICE	1
+#endif
 
 void dev_stor_init(void)
 {

arch/Kconfig

@@ -23,10 +23,6 @@ config ARM
 	select HAVE_PRIVATE_LIBGCC if !ARM64
 	select SUPPORT_OF_CONTROL
 
-config AVR32
-	bool "AVR32 architecture"
-	select CREATE_ARCH_SYMLINK
-
 config M68K
 	bool "M68000 architecture"
 	select HAVE_PRIVATE_LIBGCC
@@ -96,7 +92,6 @@ config X86
 	select DM_SPI
 	select DM_SPI_FLASH
 	select USB_EHCI_HCD
-	select DM_MMC if MMC
 	imply CMD_FPGA_LOADMK
 	imply CMD_GETTIME
 	imply CMD_IO
@@ -167,7 +162,6 @@ config SYS_CONFIG_NAME
 
 source "arch/arc/Kconfig"
 source "arch/arm/Kconfig"
-source "arch/avr32/Kconfig"
 source "arch/m68k/Kconfig"
 source "arch/microblaze/Kconfig"
 source "arch/mips/Kconfig"

arch/arc/Kconfig

@@ -132,10 +132,14 @@ config TARGET_AXS101
 config TARGET_AXS103
 	bool "Support Synopsys Designware SDP board AXS103"
 
+config TARGET_HSDK
+	bool "Support Synpsys HS DevelopmentKit board"
+
 endchoice
 
 source "board/abilis/tb100/Kconfig"
 source "board/synopsys/Kconfig"
 source "board/synopsys/axs10x/Kconfig"
+source "board/synopsys/hsdk/Kconfig"
 
 endmenu

arch/arc/dts/Makefile

@@ -6,6 +6,7 @@ dtb-$(CONFIG_TARGET_AXS101) +=  axs101.dtb
 dtb-$(CONFIG_TARGET_AXS103) +=  axs103.dtb
 dtb-$(CONFIG_TARGET_NSIM) +=  nsim.dtb
 dtb-$(CONFIG_TARGET_TB100) +=  abilis_tb100.dtb
+dtb-$(CONFIG_TARGET_HSDK) +=  hsdk.dtb
 
 targets += $(dtb-y)
 

arch/arc/dts/hsdk.dts

@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/dts-v1/;
+
+#include "skeleton.dtsi"
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	aliases {
+		console = &uart0;
+	};
+
+	cpu_card {
+		core_clk: core_clk {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <1000000000>;
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	uart0: serial0@f0005000 {
+		compatible = "snps,dw-apb-uart";
+		reg = <0xf0005000 0x1000>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+	};
+
+	ethernet@f0008000 {
+		#interrupt-cells = <1>;
+		compatible = "altr,socfpga-stmmac";
+		reg = <0xf0008000 0x2000>;
+		phy-mode = "gmii";
+	};
+
+	ehci@0xf0040000 {
+		compatible = "generic-ehci";
+		reg = <0xf0040000 0x100>;
+	};
+
+	ohci@0xf0060000 {
+		compatible = "generic-ohci";
+		reg = <0xf0060000 0x100>;
+	};
+};

arch/arc/lib/cache.c

@@ -8,6 +8,7 @@
 #include <common.h>
 #include <linux/compiler.h>
 #include <linux/kernel.h>
+#include <linux/log2.h>
 #include <asm/arcregs.h>
 #include <asm/cache.h>
 
@@ -215,17 +216,33 @@ void cache_init(void)
 	read_decode_cache_bcr_arcv2();
 
 	if (ioc_exists) {
+		/* IOC Aperture start is equal to DDR start */
+		unsigned int ap_base = CONFIG_SYS_SDRAM_BASE;
+		/* IOC Aperture size is equal to DDR size */
+		long ap_size = CONFIG_SYS_SDRAM_SIZE;
+
 		flush_dcache_all();
 		invalidate_dcache_all();
 
-		/* IO coherency base - 0x8z */
-		write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, 0x80000);
-		/* IO coherency aperture size - 512Mb: 0x8z-0xAz */
-		write_aux_reg(ARC_AUX_IO_COH_AP0_SIZE, 0x11);
-		/* Enable partial writes */
+		if (!is_power_of_2(ap_size) || ap_size < 4096)
+			panic("IOC Aperture size must be power of 2 and bigger 4Kib");
+
+		/*
+		 * IOC Aperture size decoded as 2 ^ (SIZE + 2) KB,
+		 * so setting 0x11 implies 512M, 0x12 implies 1G...
+		 */
+		write_aux_reg(ARC_AUX_IO_COH_AP0_SIZE,
+			      order_base_2(ap_size/1024) - 2);
+
+
+		/* IOC Aperture start must be aligned to the size of the aperture */
+		if (ap_base % ap_size != 0)
+			panic("IOC Aperture start must be aligned to the size of the aperture");
+
+		write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, ap_base >> 12);
 		write_aux_reg(ARC_AUX_IO_COH_PARTIAL, 1);
-		/* Enable IO coherency */
 		write_aux_reg(ARC_AUX_IO_COH_ENABLE, 1);
+
 	}
 #endif
 }

arch/arc/lib/start.S

@@ -10,6 +10,9 @@
 #include <asm/arcregs.h>
 
 ENTRY(_start)
+; ARCompact devices are not supposed to be SMP so master/slave check
+; makes no sense.
+#ifdef CONFIG_ISA_ARCV2
 	; Non-masters will be halted immediately, they might be kicked later
 	; by platform code right before passing control to the Linux kernel
 	; in bootm.c:boot_jump_linux().
@@ -25,6 +28,7 @@ ENTRY(_start)
 	nop
 
 .Lmaster_proceed:
+#endif
 
 	/* Setup interrupt vector base that matches "__text_start" */
 	sr	__ivt_start, [ARC_AUX_INTR_VEC_BASE]

arch/arm/Kconfig

@@ -253,7 +253,7 @@ config USE_ARCH_MEMCPY
 	  but may increase the binary size.
 
 config SPL_USE_ARCH_MEMCPY
-	bool "Use an assembly optimized implementation of memcpy"
+	bool "Use an assembly optimized implementation of memcpy for SPL"
 	default y if USE_ARCH_MEMCPY
 	depends on !ARM64
 	help
@@ -271,7 +271,7 @@ config USE_ARCH_MEMSET
 	  but may increase the binary size.
 
 config SPL_USE_ARCH_MEMSET
-	bool "Use an assembly optimized implementation of memset"
+	bool "Use an assembly optimized implementation of memset for SPL"
 	default y if USE_ARCH_MEMSET
 	depends on !ARM64
 	help
@@ -666,8 +666,8 @@ config ARCH_SUNXI
 	select OF_BOARD_SETUP
 	select OF_CONTROL
 	select OF_SEPARATE
-	select SPL_STACK_R if SUPPORT_SPL
-	select SPL_SYS_MALLOC_SIMPLE if SUPPORT_SPL
+	select SPL_STACK_R if SPL
+	select SPL_SYS_MALLOC_SIMPLE if SPL
 	select SYS_NS16550
 	select SPL_SYS_THUMB_BUILD if !ARM64
 	select USB if DISTRO_DEFAULTS

arch/arm/cpu/arm926ejs/mx25/generic.c

@@ -58,6 +58,14 @@ static ulong imx_get_mpllclk(void)
 	return imx_decode_pll(readl(&ccm->mpctl), fref);
 }
 
+static ulong imx_get_upllclk(void)
+{
+	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
+	ulong fref = MXC_HCLK;
+
+	return imx_decode_pll(readl(&ccm->upctl), fref);
+}
+
 static ulong imx_get_armclk(void)
 {
 	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
@@ -95,7 +103,8 @@ static ulong imx_get_ipgclk(void)
 static ulong imx_get_perclk(int clk)
 {
 	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
-	ulong fref = imx_get_ahbclk();
+	ulong fref = readl(&ccm->mcr) & (1 << clk) ? imx_get_upllclk() :
+						     imx_get_ahbclk();
 	ulong div;
 
 	div = readl(&ccm->pcdr[CCM_PERCLK_REG(clk)]);
@@ -104,6 +113,25 @@ static ulong imx_get_perclk(int clk)
 	return fref / div;
 }
 
+int imx_set_perclk(enum mxc_clock clk, bool from_upll, unsigned int freq)
+{
+	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
+	ulong fref = from_upll ? imx_get_upllclk() : imx_get_ahbclk();
+	ulong div = (fref + freq - 1) / freq;
+
+	if (clk > MXC_UART_CLK || !div || --div > CCM_PERCLK_MASK)
+		return -EINVAL;
+
+	clrsetbits_le32(&ccm->pcdr[CCM_PERCLK_REG(clk)],
+			CCM_PERCLK_MASK << CCM_PERCLK_SHIFT(clk),
+			div << CCM_PERCLK_SHIFT(clk));
+	if (from_upll)
+		setbits_le32(&ccm->mcr, 1 << clk);
+	else
+		clrbits_le32(&ccm->mcr, 1 << clk);
+	return 0;
+}
+
 unsigned int mxc_get_clock(enum mxc_clock clk)
 {
 	if (clk >= MXC_CLK_NUM)

arch/arm/cpu/armv7/mx6/soc.c

@@ -158,7 +158,7 @@ u32 get_cpu_speed_grade_hz(void)
  * OCOTP_MEM0[7:6] (see Fusemap Description Table offset 0x480)
  * defines a 2-bit Temperature Grade
  *
- * return temperature grade and min/max temperature in celcius
+ * return temperature grade and min/max temperature in Celsius
  */
 #define OCOTP_MEM0_TEMP_SHIFT          6
 

arch/arm/cpu/armv7/mx7/Kconfig

@@ -25,6 +25,13 @@ config TARGET_MX7DSABRESD
 	select DM
 	select DM_THERMAL
 
+config TARGET_PICO_IMX7D
+	bool "pico-imx7d"
+	select BOARD_LATE_INIT
+	select MX7D
+	select DM
+	select DM_THERMAL
+
 config TARGET_WARP7
 	bool "warp7"
 	select BOARD_LATE_INIT
@@ -45,6 +52,7 @@ config SYS_SOC
 	default "mx7"
 
 source "board/freescale/mx7dsabresd/Kconfig"
+source "board/technexion/pico-imx7d/Kconfig"
 source "board/toradex/colibri_imx7/Kconfig"
 source "board/warp7/Kconfig"
 

arch/arm/cpu/armv8/Kconfig

@@ -92,7 +92,7 @@ config PSCI_RESET
 		   !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
 		   !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
 		   !TARGET_LS2081ARDB && \
-		   !ARCH_UNIPHIER && !ARCH_SNAPDRAGON && !TARGET_S32V234EVB
+		   !ARCH_UNIPHIER && !TARGET_S32V234EVB
 	help
 	  Most armv8 systems have PSCI support enabled in EL3, either through
 	  ARM Trusted Firmware or other firmware.

arch/arm/cpu/armv8/zynqmp/cpu.c

@@ -37,12 +37,6 @@ static struct mm_region zynqmp_mem_map[] = {
 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 			 PTE_BLOCK_NON_SHARE |
 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	}, {
-		.virt = 0xffe00000UL,
-		.phys = 0xffe00000UL,
-		.size = 0x00200000UL,
-		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-			 PTE_BLOCK_INNER_SHARE
 	}, {
 		.virt = 0x400000000UL,
 		.phys = 0x400000000UL,
@@ -104,3 +98,111 @@ unsigned int zynqmp_get_silicon_version(void)
 
 	return ZYNQMP_CSU_VERSION_SILICON;
 }
+
+#define ZYNQMP_MMIO_READ	0xC2000014
+#define ZYNQMP_MMIO_WRITE	0xC2000013
+
+#ifndef CONFIG_SPL_BUILD
+int invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, u32 arg3,
+	       u32 *ret_payload)
+{
+	/*
+	 * Added SIP service call Function Identifier
+	 * Make sure to stay in x0 register
+	 */
+	struct pt_regs regs;
+
+	regs.regs[0] = pm_api_id;
+	regs.regs[1] = ((u64)arg1 << 32) | arg0;
+	regs.regs[2] = ((u64)arg3 << 32) | arg2;
+
+	smc_call(&regs);
+
+	if (ret_payload != NULL) {
+		ret_payload[0] = (u32)regs.regs[0];
+		ret_payload[1] = upper_32_bits(regs.regs[0]);
+		ret_payload[2] = (u32)regs.regs[1];
+		ret_payload[3] = upper_32_bits(regs.regs[1]);
+		ret_payload[4] = (u32)regs.regs[2];
+	}
+
+	return regs.regs[0];
+}
+
+#define ZYNQMP_SIP_SVC_GET_API_VERSION		0xC2000001
+
+#define ZYNQMP_PM_VERSION_MAJOR		0
+#define ZYNQMP_PM_VERSION_MINOR		3
+#define ZYNQMP_PM_VERSION_MAJOR_SHIFT	16
+#define ZYNQMP_PM_VERSION_MINOR_MASK	0xFFFF
+
+#define ZYNQMP_PM_VERSION	\
+	((ZYNQMP_PM_VERSION_MAJOR << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | \
+				 ZYNQMP_PM_VERSION_MINOR)
+
+#if defined(CONFIG_CLK_ZYNQMP)
+void zynqmp_pmufw_version(void)
+{
+	int ret;
+	u32 ret_payload[PAYLOAD_ARG_CNT];
+	u32 pm_api_version;
+
+	ret = invoke_smc(ZYNQMP_SIP_SVC_GET_API_VERSION, 0, 0, 0, 0,
+			 ret_payload);
+	pm_api_version = ret_payload[1];
+
+	if (ret)
+		panic("PMUFW is not found - Please load it!\n");
+
+	printf("PMUFW:\tv%d.%d\n",
+	       pm_api_version >> ZYNQMP_PM_VERSION_MAJOR_SHIFT,
+	       pm_api_version & ZYNQMP_PM_VERSION_MINOR_MASK);
+
+	if (pm_api_version != ZYNQMP_PM_VERSION)
+		panic("PMUFW version error. Expected: v%d.%d\n",
+		      ZYNQMP_PM_VERSION_MAJOR, ZYNQMP_PM_VERSION_MINOR);
+}
+#endif
+
+int zynqmp_mmio_write(const u32 address,
+		      const u32 mask,
+		      const u32 value)
+{
+	return invoke_smc(ZYNQMP_MMIO_WRITE, address, mask, value, 0, NULL);
+}
+
+int zynqmp_mmio_read(const u32 address, u32 *value)
+{
+	u32 ret_payload[PAYLOAD_ARG_CNT];
+	u32 ret;
+
+	if (!value)
+		return -EINVAL;
+
+	ret = invoke_smc(ZYNQMP_MMIO_READ, address, 0, 0, 0, ret_payload);
+	*value = ret_payload[1];
+
+	return ret;
+}
+#else
+int zynqmp_mmio_write(const u32 address,
+		      const u32 mask,
+		      const u32 value)
+{
+	u32 data;
+	u32 value_local = value;
+
+	zynqmp_mmio_read(address, &data);
+	data &= ~mask;
+	value_local &= mask;
+	value_local |= data;
+	writel(value_local, (ulong)address);
+	return 0;
+}
+
+int zynqmp_mmio_read(const u32 address, u32 *value)
+{
+	*value = readl((ulong)address);
+	return 0;
+}
+#endif

arch/arm/cpu/armv8/zynqmp/spl.c

@@ -83,9 +83,15 @@ u32 spl_boot_device(void)
 	case JTAG_MODE:
 		return BOOT_DEVICE_RAM;
 #ifdef CONFIG_SPL_MMC_SUPPORT
-	case EMMC_MODE:
-	case SD_MODE:
 	case SD_MODE1:
+	case SD1_LSHFT_MODE: /* not working on silicon v1 */
+/* if both controllers enabled, then these two are the second controller */
+#if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1)
+		return BOOT_DEVICE_MMC2;
+/* else, fall through, the one SDHCI controller that is enabled is number 1 */
+#endif
+	case SD_MODE:
+	case EMMC_MODE:
 		return BOOT_DEVICE_MMC1;
 #endif
 #ifdef CONFIG_SPL_DFU_SUPPORT
@@ -106,10 +112,11 @@ u32 spl_boot_device(void)
 
 u32 spl_boot_mode(const u32 boot_device)
 {
-	switch (spl_boot_device()) {
+	switch (boot_device) {
 	case BOOT_DEVICE_RAM:
 		return 0;
 	case BOOT_DEVICE_MMC1:
+	case BOOT_DEVICE_MMC2:
 		return MMCSD_MODE_FS;
 	default:
 		puts("spl: error: unsupported device\n");

arch/arm/dts/Makefile

@@ -97,8 +97,10 @@ dtb-$(CONFIG_ARCH_MVEBU) +=			\
 	armada-38x-controlcenterdc.dtb
 
 dtb-$(CONFIG_ARCH_UNIPHIER_LD11) += \
+	uniphier-ld11-global.dtb \
 	uniphier-ld11-ref.dtb
 dtb-$(CONFIG_ARCH_UNIPHIER_LD20) += \
+	uniphier-ld20-global.dtb \
 	uniphier-ld20-ref.dtb
 dtb-$(CONFIG_ARCH_UNIPHIER_LD4) += \
 	uniphier-ld4-ref.dtb
@@ -127,6 +129,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
 	zynq-microzed.dtb \
 	zynq-picozed.dtb \
 	zynq-topic-miami.dtb \
+	zynq-topic-miamilite.dtb \
 	zynq-topic-miamiplus.dtb \
 	zynq-zc770-xm010.dtb \
 	zynq-zc770-xm011.dtb \
@@ -393,7 +396,7 @@ dtb-$(CONFIG_TARGET_AT91SAM9N12EK) += at91sam9n12ek.dtb
 
 dtb-$(CONFIG_TARGET_OMAP3_LOGIC) += \
 	logicpd-torpedo-37xx-devkit.dtb \
-	logicpd-som-lv-37xx-devkit.dts
+	logicpd-som-lv-37xx-devkit.dtb
 
 dtb-$(CONFIG_TARGET_SAMA5D2_XPLAINED) += \
 	at91-sama5d2_xplained.dtb

arch/arm/dts/am437x-gp-evm-u-boot.dtsi

@@ -9,30 +9,30 @@
 
 /{
 	ocp {
-		u-boot,dm-pre-reloc;
+		u-boot,dm-spl;
 	};
 };
 
 &uart0 {
-	u-boot,dm-pre-reloc;
+	u-boot,dm-spl;
 };
 
 &mmc1 {
-	u-boot,dm-pre-reloc;
+	u-boot,dm-spl;
 };
 
 &mac {
-	u-boot,dm-pre-reloc;
+	u-boot,dm-spl;
 };
 
 &davinci_mdio {
-	u-boot,dm-pre-reloc;
+	u-boot,dm-spl;
 };
 
 &cpsw_emac0 {
-	u-boot,dm-pre-reloc;
+	u-boot,dm-spl;
 };
 
 &phy_sel {
-	u-boot,dm-pre-reloc;
+	u-boot,dm-spl;
 };

arch/arm/dts/at91sam9260-smartweb.dts

@@ -18,6 +18,7 @@
 	compatible = "atmel,at91sam9260", "atmel,at91sam9";
 
 	chosen {
+		u-boot,dm-pre-reloc;
 		stdout-path = &dbgu;
 	};
 
@@ -48,6 +49,7 @@
 			};
 
 			dbgu: serial@fffff200 {
+				u-boot,dm-pre-reloc;
 				status = "okay";
 			};
 

arch/arm/dts/at91sam9g20-taurus.dts

@@ -18,6 +18,7 @@
 	compatible = "atmel,at91sam9g20ek", "atmel,at91sam9g20", "atmel,at91sam9";
 
 	chosen {
+		u-boot,dm-pre-reloc;
 		stdout-path = &dbgu;
 	};
 
@@ -48,6 +49,7 @@
 			};
 
 			dbgu: serial@fffff200 {
+				u-boot,dm-pre-reloc;
 				status = "okay";
 			};
 

arch/arm/dts/at91sam9g45-corvus.dts

@@ -18,6 +18,7 @@
 	compatible = "atmel,at91sam9m10g45ek", "atmel,at91sam9g45", "atmel,at91sam9";
 
 	chosen {
+		u-boot,dm-pre-reloc;
 		stdout-path = &dbgu;
 	};
 
@@ -38,6 +39,7 @@
 	ahb {
 		apb {
 			dbgu: serial@ffffee00 {
+				u-boot,dm-pre-reloc;
 				status = "okay";
 			};
 

arch/arm/dts/exynos4.dtsi

@@ -122,44 +122,49 @@
 		interrupts = <7 63 0>;
 	};
 
-	sdhci@12510000 {
+	sdhci0: sdhci@12510000 {
 		#address-cells = <1>;
 		#size-cells = <0>;
-		compatible = "samsung,exynos-mmc";
+		compatible = "samsung,exynos4412-sdhci";
 		reg = <0x12510000 0x1000>;
 		interrupts = <0 75 0>;
+		status = "disabled";
 	};
 
-	sdhci@12520000 {
+	sdhci1: sdhci@12520000 {
 		#address-cells = <1>;
 		#size-cells = <0>;
-		compatible = "samsung,exynos-mmc";
+		compatible = "samsung,exynos4412-sdhci";
 		reg = <0x12520000 0x1000>;
 		interrupts = <0 76 0>;
+		status = "disabled";
 	};
 
-	sdhci@12530000 {
+	sdhci2: sdhci@12530000 {
 		#address-cells = <1>;
 		#size-cells = <0>;
-		compatible = "samsung,exynos-mmc";
+		compatible = "samsung,exynos4412-sdhci";
 		reg = <0x12530000 0x1000>;
 		interrupts = <0 77 0>;
+		status = "disabled";
 	};
 
-	sdhci@12540000 {
+	sdhci3: sdhci@12540000 {
 		#address-cells = <1>;
 		#size-cells = <0>;
-		compatible = "samsung,exynos-mmc";
+		compatible = "samsung,exynos4412-sdhci";
 		reg = <0x12540000 0x1000>;
 		interrupts = <0 78 0>;
+		status = "disabled";
 	};
 
-	dwmmc@12550000 {
+	mshc_0: dwmmc@12550000 {
 		#address-cells = <1>;
 		#size-cells = <0>;
-		compatible = "samsung,exynos-dwmmc";
+		compatible = "samsung,exynos4412-dw-mshc";
 		reg = <0x12550000 0x1000>;
 		interrupts = <0 131 0>;
+		status = "disabled";
 	};
 
 };

arch/arm/dts/exynos4210-origen.dts

@@ -22,24 +22,12 @@
 	aliases {
 		serial0 = "/serial@13800000";
 		console = "/serial@13820000";
-		mmc2 = "/sdhci@12530000";
-	};
-
-	sdhci@12510000 {
-		status = "disabled";
-	};
-
-	sdhci@12520000 {
-		status = "disabled";
-	};
-
-	sdhci@12530000 {
-		samsung,bus-width = <4>;
-		samsung,timing = <1 2 3>;
-		cd-gpios = <&gpk2 2 0>;
-	};
-
-	sdhci@12540000 {
-		status = "disabled";
 	};
 };
+
+&sdhci2 {
+	samsung,bus-width = <4>;
+	samsung,timing = <1 2 3>;
+	cd-gpios = <&gpk2 2 0>;
+	status = "okay";
+};

arch/arm/dts/exynos4210-trats.dts

@@ -21,8 +21,6 @@
 	aliases {
 		serial0 = "/serial@13800000";
 		console = "/serial@13820000";
-		mmc0 = "/sdhci@12510000";
-		mmc2 = "/sdhci@12530000";
 		i2c8 = &i2c_fg;
 	};
 
@@ -91,30 +89,6 @@
 		samsung,dsim-device-reverse-panel = <1>;
 	};
 
-	sdhci@12510000 {
-		samsung,bus-width = <8>;
-		samsung,timing = <1 3 3>;
-		pwr-gpios = <&gpk0 2 0>;
-	};
-
-	sdhci@12520000 {
-		status = "disabled";
-	};
-
-	sdhci@12530000 {
-		samsung,bus-width = <4>;
-		samsung,timing = <1 2 3>;
-		cd-gpios = <&gpx3 4 0>;
-	};
-
-	sdhci@12540000 {
-		status = "disabled";
-	};
-
-	dwmmc@12550000 {
-		status = "disabled";
-	};
-
 	i2c_fg: fuel-gauge {
 		compatible = "i2c-gpio";
 		gpios = <&gpy4 1 0>,	/* sda */
@@ -265,3 +239,17 @@
 		};
 	};
 };
+
+&sdhci0 {
+	samsung,bus-width = <8>;
+	samsung,timing = <1 3 3>;
+	pwr-gpios = <&gpk0 2 0>;
+	status = "okay";
+};
+
+&sdhci2 {
+	samsung,bus-width = <4>;
+	samsung,timing = <1 2 3>;
+	cd-gpios = <&gpx3 4 0>;
+	status = "okay";
+};

arch/arm/dts/exynos4210-universal_c210.dts

@@ -17,28 +17,6 @@
 	aliases {
 		serial0 = "/serial@13800000";
 		console = "/serial@13820000";
-		mmc0 = "/sdhci@12510000";
-		mmc2 = "/sdhci@12530000";
-	};
-
-	sdhci@12510000 {
-		samsung,bus-width = <8>;
-		samsung,timing = <1 3 3>;
-		pwr-gpios = <&gpk0 2 0>;
-	};
-
-	sdhci@12520000 {
-		status = "disabled";
-	};
-
-	sdhci@12530000 {
-		samsung,bus-width = <4>;
-		samsung,timing = <1 2 3>;
-		cd-gpios = <&gpx3 4 0>;
-	};
-
-	sdhci@12540000 {
-		status = "disabled";
 	};
 
 	soft-spi {
@@ -258,3 +236,17 @@
 		};
 	};
 };
+
+&sdhci0 {
+	samsung,bus-width = <8>;
+	samsung,timing = <1 3 3>;
+	pwr-gpios = <&gpk0 2 0>;
+	status = "okay";
+};
+
+&sdhci2 {
+	samsung,bus-width = <4>;
+	samsung,timing = <1 2 3>;
+	cd-gpios = <&gpx3 4 0>;
+	status = "okay";
+};

arch/arm/dts/exynos4412-odroid.dts

@@ -25,8 +25,8 @@
 		i2c7 = "/i2c@138d0000";
 		serial0 = "/serial@13800000";
 		console = "/serial@13810000";
-		mmc2 = "/sdhci@12530000";
-		mmc4 = "/dwmmc@12550000";
+		mmc0 = &mshc_0;
+		mmc1 = &sdhci2;
 	};
 
 	i2c@13860000 {
@@ -224,34 +224,6 @@
 		status = "okay";
 	};
 
-	sdhci@12510000 {
-		status = "disabled";
-	};
-
-	sdhci@12520000 {
-		status = "disabled";
-	};
-
-	sdhci@12530000 {
-		samsung,bus-width = <4>;
-		samsung,timing = <1 2 3>;
-		cd-gpios = <&gpk2 2 0>;
-	};
-
-	sdhci@12540000 {
-		status = "disabled";
-	};
-
-	dwmmc@12550000 {
-		samsung,bus-width = <8>;
-		samsung,timing = <2 1 0>;
-		samsung,removable = <0>;
-		fifoth_val = <0x203f0040>;
-		bus_hz = <400000000>;
-		div = <0x3>;
-		index = <4>;
-	};
-
 	ehci@12580000 {
 		compatible = "samsung,exynos-ehci";
 		reg = <0x12580000 0x100>;
@@ -268,3 +240,21 @@
 		reset-gpio = <&gpk1 2 0>;
 	};
 };
+
+&sdhci2 {
+	samsung,bus-width = <4>;
+	samsung,timing = <1 2 3>;
+	cd-gpios = <&gpk2 2 0>;
+	status = "okay";
+};
+
+&mshc_0 {
+	samsung,bus-width = <8>;
+	samsung,timing = <2 1 0>;
+	samsung,removable = <0>;
+	fifoth_val = <0x203f0040>;
+	bus_hz = <400000000>;
+	div = <0x3>;
+	index = <4>;
+	status = "okay";
+};

arch/arm/dts/exynos4412-trats2.dts

@@ -31,9 +31,8 @@
 		i2c9 = &i2c_max77693;
 		serial0 = "/serial@13800000";
 		console = "/serial@13820000";
-		mmc0 = "/sdhci@12510000";
-		mmc2 = "/sdhci@12530000";
-		mshc0 = "/dwmmc@12550000";
+		mmc0 = &mshc_0;
+		mmc1 = &sdhci2;
 	};
 
 	i2c_fg: fuel-gauge {
@@ -437,28 +436,30 @@
 		pwr-gpios = <&gpk0 4 0>;
 		status = "disabled";
 	};
-
-	sdhci@12520000 {
-		status = "disabled";
-	};
-
-	sdhci@12530000 {
-		samsung,bus-width = <4>;
-		samsung,timing = <1 2 3>;
-		cd-gpios = <&gpk2 2 0>;
-	};
-
-	sdhci@12540000 {
-		status = "disabled";
-	};
-
-	dwmmc@12550000 {
-		samsung,bus-width = <8>;
-		samsung,timing = <2 1 0>;
-		pwr-gpios = <&gpk0 4 0>;
-		fifoth_val = <0x203f0040>;
-		bus_hz = <400000000>;
-		div = <0x3>;
-		index = <4>;
-	};
+};
+
+&sdhci0 {
+	samsung,bus-width = <8>;
+	samsung,timing = <1 3 3>;
+	pwr-gpios = <&gpk0 4 0>;
+	status = "disabled";
+};
+
+&sdhci2 {
+	samsung,bus-width = <4>;
+	samsung,timing = <1 2 3>;
+	cd-gpios = <&gpk2 2 0>;
+	status = "okay";
+};
+
+&mshc_0 {
+	samsung,bus-width = <8>;
+	samsung,timing = <2 1 0>;
+	samsung,removable = <0>;
+	fifoth_val = <0x203f0040>;
+	bus_hz = <400000000>;
+	div = <0x3>;
+	index = <4>;
+	fifo-depth = <0x80>;
+	status = "okay";
 };

arch/arm/dts/exynos4x12.dtsi

@@ -27,7 +27,6 @@
 		pinctrl1 = &pinctrl_1;
 		pinctrl2 = &pinctrl_2;
 		pinctrl3 = &pinctrl_3;
-		mshc0 = &mshc_0;
 	};
 
 	pd_isp: isp-power-domain@10023CA0 {
@@ -100,16 +99,4 @@
 		clock-names = "sclk_fimg2d", "fimg2d";
 		status = "disabled";
 	};
-
-	mshc_0: mmc@12550000 {
-		compatible = "samsung,exynos4412-dw-mshc";
-		reg = <0x12550000 0x1000>;
-		interrupts = <0 77 0>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		fifo-depth = <0x80>;
-		clocks = <&clock 301>, <&clock 149>;
-		clock-names = "biu", "ciu";
-		status = "disabled";
-	};
 };

arch/arm/dts/exynos5422-odroidxu3.dts

@@ -40,6 +40,215 @@
 		s2mps11_pmic@66 {
 			compatible = "samsung,s2mps11-pmic";
 			reg = <0x66>;
+			voltage-regulators {
+				ldo1_reg: LDO1 {
+					regulator-name = "vdd_ldo1";
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1000000>;
+					regulator-always-on;
+				};
+
+				ldo3_reg: LDO3 {
+					regulator-name = "vddq_mmc0";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+				};
+
+				ldo4_reg: LDO4 {
+					regulator-name = "vdd_adc";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+				};
+
+				ldo5_reg: LDO5 {
+					regulator-name = "vdd_ldo5";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+				};
+
+				ldo6_reg: LDO6 {
+					regulator-name = "vdd_ldo6";
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1000000>;
+					regulator-always-on;
+				};
+
+				ldo7_reg: LDO7 {
+					regulator-name = "vdd_ldo7";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+				};
+
+				ldo8_reg: LDO8 {
+					regulator-name = "vdd_ldo8";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+				};
+
+				ldo9_reg: LDO9 {
+					regulator-name = "vdd_ldo9";
+					regulator-min-microvolt = <3000000>;
+					regulator-max-microvolt = <3000000>;
+					regulator-always-on;
+				};
+
+				ldo10_reg: LDO10 {
+					regulator-name = "vdd_ldo10";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+				};
+
+				ldo11_reg: LDO11 {
+					regulator-name = "vdd_ldo11";
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1000000>;
+					regulator-always-on;
+				};
+
+				ldo12_reg: LDO12 {
+					regulator-name = "vdd_ldo12";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+				};
+
+				ldo13_reg: LDO13 {
+					regulator-name = "vddq_mmc2";
+					regulator-min-microvolt = <2800000>;
+					regulator-max-microvolt = <2800000>;
+				};
+
+				ldo15_reg: LDO15 {
+					regulator-name = "vdd_ldo15";
+					regulator-min-microvolt = <3100000>;
+					regulator-max-microvolt = <3100000>;
+					regulator-always-on;
+				};
+
+				ldo16_reg: LDO16 {
+					regulator-name = "vdd_ldo16";
+					regulator-min-microvolt = <2200000>;
+					regulator-max-microvolt = <2200000>;
+					regulator-always-on;
+				};
+
+				ldo17_reg: LDO17 {
+					regulator-name = "tsp_avdd";
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-always-on;
+				};
+
+				ldo18_reg: LDO18 {
+					regulator-name = "vdd_emmc_1V8";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+				};
+
+				ldo19_reg: LDO19 {
+					regulator-name = "vdd_sd";
+					regulator-min-microvolt = <2800000>;
+					regulator-max-microvolt = <2800000>;
+				};
+
+				ldo24_reg: LDO24 {
+					regulator-name = "tsp_io";
+					regulator-min-microvolt = <2800000>;
+					regulator-max-microvolt = <2800000>;
+					regulator-always-on;
+				};
+
+				ldo26_reg: LDO26 {
+					regulator-name = "vdd_ldo26";
+					regulator-min-microvolt = <3000000>;
+					regulator-max-microvolt = <3000000>;
+					regulator-always-on;
+				};
+
+				buck1_reg: BUCK1 {
+					regulator-name = "vdd_mif";
+					regulator-min-microvolt = <800000>;
+					regulator-max-microvolt = <1300000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				buck2_reg: BUCK2 {
+					regulator-name = "vdd_arm";
+					regulator-min-microvolt = <800000>;
+					regulator-max-microvolt = <1500000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				buck3_reg: BUCK3 {
+					regulator-name = "vdd_int";
+					regulator-min-microvolt = <800000>;
+					regulator-max-microvolt = <1400000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				buck4_reg: BUCK4 {
+					regulator-name = "vdd_g3d";
+					regulator-min-microvolt = <800000>;
+					regulator-max-microvolt = <1400000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				buck5_reg: BUCK5 {
+					regulator-name = "vdd_mem";
+					regulator-min-microvolt = <800000>;
+					regulator-max-microvolt = <1400000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				buck6_reg: BUCK6 {
+					regulator-name = "vdd_kfc";
+					regulator-min-microvolt = <800000>;
+					regulator-max-microvolt = <1500000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				buck7_reg: BUCK7 {
+					regulator-name = "vdd_1.0v_ldo";
+					regulator-min-microvolt = <800000>;
+					regulator-max-microvolt = <1500000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				buck8_reg: BUCK8 {
+					regulator-name = "vdd_1.8v_ldo";
+					regulator-min-microvolt = <800000>;
+					regulator-max-microvolt = <1500000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				buck9_reg: BUCK9 {
+					regulator-name = "vdd_2.8v_ldo";
+					regulator-min-microvolt = <3000000>;
+					regulator-max-microvolt = <3750000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				buck10_reg: BUCK10 {
+					regulator-name = "vdd_vmem";
+					regulator-min-microvolt = <2850000>;
+					regulator-max-microvolt = <2850000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+			};
 		};
 	};
 

arch/arm/dts/omap5-u-boot.dtsi

@@ -9,7 +9,7 @@
 
 /{
 	ocp {
-		u-boot,dm-pre-reloc;
+		u-boot,dm-spl;
 
 		ocp2scp@4a090000 {
 			compatible = "ti,omap-ocp2scp", "simple-bus";
@@ -18,37 +18,37 @@
 };
 
 &uart1 {
-	u-boot,dm-pre-reloc;
+	u-boot,dm-spl;
 };
 
 &uart3 {
-	u-boot,dm-pre-reloc;
+	u-boot,dm-spl;
 };
 
 &mmc1 {
-	u-boot,dm-pre-reloc;
+	u-boot,dm-spl;
 };
 
 &mmc2 {
-	u-boot,dm-pre-reloc;
+	u-boot,dm-spl;
 };
 
 &l4_cfg {
-	u-boot,dm-pre-reloc;
+	u-boot,dm-spl;
 };
 
 &scm {
-	u-boot,dm-pre-reloc;
+	u-boot,dm-spl;
 };
 
 &scm_conf {
-	u-boot,dm-pre-reloc;
+	u-boot,dm-spl;
 };
 
 &qspi {
-	u-boot,dm-pre-reloc;
+	u-boot,dm-spl;
 
 	m25p80@0 {
-		u-boot,dm-pre-reloc;
+		u-boot,dm-spl;
 	};
 };

arch/arm/dts/uniphier-ld11-global.dts

@@ -0,0 +1,79 @@
+/*
+ * Device Tree Source for UniPhier LD11 Global Board
+ *
+ * Copyright (C) 2016-2017 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *           Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+/dts-v1/;
+/include/ "uniphier-ld11.dtsi"
+
+/ {
+	model = "UniPhier LD11 Global Board (REF_LD11_GP)";
+	compatible = "socionext,uniphier-ld11-global",
+		     "socionext,uniphier-ld11";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	aliases {
+		serial0 = &serial0;
+		serial1 = &serial1;
+		serial2 = &serial2;
+		serial3 = &serial3;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		i2c2 = &i2c2;
+		i2c3 = &i2c3;
+		i2c4 = &i2c4;
+		i2c5 = &i2c5;
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0 0x80000000 0 0x40000000>;
+	};
+};
+
+&serial0 {
+	status = "okay";
+};
+
+&serial1 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	eeprom@50 {
+		compatible = "st,24c64", "atmel,24c64", "i2c-eeprom";
+		reg = <0x50>;
+		pagesize = <32>;
+	};
+};
+
+&usb0 {
+	status = "okay";
+};
+
+&usb1 {
+	status = "okay";
+};
+
+&usb2 {
+	status = "okay";
+};
+
+/* for U-Boot only */
+&serial0 {
+	u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart0 {
+	u-boot,dm-pre-reloc;
+};

arch/arm/dts/uniphier-ld11-ref.dts

@@ -4,7 +4,7 @@
  * Copyright (C) 2016 Socionext Inc.
  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
- * SPDX-License-Identifier:	GPL-2.0+	X11
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  */
 
 /dts-v1/;

arch/arm/dts/uniphier-ld11.dtsi

@@ -4,46 +4,10 @@
  * Copyright (C) 2016 Socionext Inc.
  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  */
 
-/memreserve/ 0x80000000 0x00080000;
+/memreserve/ 0x80000000 0x02000000;
 
 / {
 	compatible = "socionext,uniphier-ld11";

arch/arm/dts/uniphier-ld20-global.dts

@@ -0,0 +1,61 @@
+/*
+ * Device Tree Source for UniPhier LD20 Global Board
+ *
+ * Copyright (C) 2015-2017 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *           Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+/dts-v1/;
+/include/ "uniphier-ld20.dtsi"
+
+/ {
+	model = "UniPhier LD20 Global Board (REF_LD20_GP)";
+	compatible = "socionext,uniphier-ld20-global",
+		     "socionext,uniphier-ld20";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	aliases {
+		serial0 = &serial0;
+		serial1 = &serial1;
+		serial2 = &serial2;
+		serial3 = &serial3;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		i2c2 = &i2c2;
+		i2c3 = &i2c3;
+		i2c4 = &i2c4;
+		i2c5 = &i2c5;
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0 0x80000000 0 0xc0000000>;
+	};
+};
+
+&serial0 {
+	status = "okay";
+};
+
+&serial1 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+};
+
+/* for U-Boot only */
+&serial0 {
+	u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart0 {
+	u-boot,dm-pre-reloc;
+};

arch/arm/dts/uniphier-ld20-ref.dts

@@ -4,7 +4,7 @@
  * Copyright (C) 2015-2016 Socionext Inc.
  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
- * SPDX-License-Identifier:	GPL-2.0+	X11
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  */
 
 /dts-v1/;

arch/arm/dts/uniphier-ld20.dtsi

@@ -4,46 +4,10 @@
  * Copyright (C) 2015-2016 Socionext Inc.
  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  */
 
-/memreserve/ 0x80000000 0x00080000;
+/memreserve/ 0x80000000 0x02000000;
 
 / {
 	compatible = "socionext,uniphier-ld20";

arch/arm/dts/uniphier-ld4-ref.dts

@@ -4,7 +4,7 @@
  * Copyright (C) 2015-2016 Socionext Inc.
  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
- * SPDX-License-Identifier:	GPL-2.0+	X11
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  */
 
 /dts-v1/;

arch/arm/dts/uniphier-ld4.dtsi

@@ -4,43 +4,7 @@
  * Copyright (C) 2015-2016 Socionext Inc.
  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  */
 
 / {

arch/arm/dts/uniphier-ld6b-ref.dts

@@ -4,7 +4,7 @@
  * Copyright (C) 2015-2016 Socionext Inc.
  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
- * SPDX-License-Identifier:	GPL-2.0+
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  */
 
 /dts-v1/;

arch/arm/dts/uniphier-ld6b.dtsi

@@ -4,7 +4,7 @@
  * Copyright (C) 2015-2016 Socionext Inc.
  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
- * SPDX-License-Identifier:	GPL-2.0+	X11
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  */
 
 /*

arch/arm/dts/uniphier-pinctrl.dtsi

@@ -4,7 +4,7 @@
  * Copyright (C) 2015-2017 Socionext Inc.
  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
- * SPDX-License-Identifier:	GPL-2.0+	X11
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  */
 
 &pinctrl {

arch/arm/dts/uniphier-pro4-ace.dts

@@ -4,7 +4,7 @@
  * Copyright (C) 2016 Socionext Inc.
  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
- * SPDX-License-Identifier:	GPL-2.0+	X11
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  */
 
 /dts-v1/;
@@ -52,7 +52,7 @@
 	status = "okay";
 
 	eeprom@54 {
-		compatible = "st,24c64", "i2c-eeprom";
+		compatible = "st,24c64", "atmel,24c64", "i2c-eeprom";
 		reg = <0x54>;
 		pagesize = <32>;
 		u-boot,i2c-offset-len = <2>;

arch/arm/dts/uniphier-pro4-ref.dts

@@ -4,7 +4,7 @@
  * Copyright (C) 2015-2016 Socionext Inc.
  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
- * SPDX-License-Identifier:	GPL-2.0+	X11
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  */
 
 /dts-v1/;

arch/arm/dts/uniphier-pro4-sanji.dts

@@ -4,7 +4,7 @@
  * Copyright (C) 2016 Socionext Inc.
  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
- * SPDX-License-Identifier:	GPL-2.0+	X11
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  */
 
 /dts-v1/;
@@ -47,7 +47,7 @@
 	status = "okay";
 
 	eeprom@54 {
-		compatible = "st,24c64", "i2c-eeprom";
+		compatible = "st,24c64", "atmel,24c64", "i2c-eeprom";
 		reg = <0x54>;
 		pagesize = <32>;
 		u-boot,i2c-offset-len = <2>;

arch/arm/dts/uniphier-pro4.dtsi

@@ -4,43 +4,7 @@
  * Copyright (C) 2015-2016 Socionext Inc.
  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  */
 
 / {

arch/arm/dts/uniphier-pro5-4kbox.dts

@@ -4,7 +4,7 @@
  * Copyright (C) 2015-2016 Socionext Inc.
  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
- * SPDX-License-Identifier:	GPL-2.0+
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  */
 
 /dts-v1/;

arch/arm/dts/uniphier-pro5.dtsi

@@ -4,43 +4,7 @@
  * Copyright (C) 2015-2016 Socionext Inc.
  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  */
 
 / {

arch/arm/dts/uniphier-pxs2-gentil.dts

@@ -4,7 +4,7 @@
  * Copyright (C) 2015-2016 Socionext Inc.
  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
- * SPDX-License-Identifier:	GPL-2.0+
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  */
 
 /dts-v1/;
@@ -44,7 +44,7 @@
 	status = "okay";
 
 	eeprom@54 {
-		compatible = "st,24c64", "i2c-eeprom";
+		compatible = "st,24c64", "atmel,24c64", "i2c-eeprom";
 		reg = <0x54>;
 		pagesize = <32>;
 		u-boot,i2c-offset-len = <2>;

arch/arm/dts/uniphier-pxs2-vodka.dts

@@ -4,7 +4,7 @@
  * Copyright (C) 2015-2016 Socionext Inc.
  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
- * SPDX-License-Identifier:	GPL-2.0+
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  */
 
 /dts-v1/;

arch/arm/dts/uniphier-pxs2.dtsi

@@ -4,43 +4,7 @@
  * Copyright (C) 2015-2016 Socionext Inc.
  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  */
 
 / {

arch/arm/dts/uniphier-ref-daughter.dtsi

@@ -4,7 +4,7 @@
  * Copyright (C) 2015-2017 Socionext Inc.
  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
- * SPDX-License-Identifier:	GPL-2.0+	X11
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  */
 
 &i2c0 {

arch/arm/dts/uniphier-sld3-ref.dts

@@ -4,7 +4,7 @@
  * Copyright (C) 2015-2016 Socionext Inc.
  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
- * SPDX-License-Identifier:	GPL-2.0+	X11
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  */
 
 /dts-v1/;

arch/arm/dts/uniphier-sld3.dtsi

@@ -4,43 +4,7 @@
  * Copyright (C) 2015-2016 Socionext Inc.
  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  */
 
 / {

arch/arm/dts/uniphier-sld8-ref.dts

@@ -4,7 +4,7 @@
  * Copyright (C) 2015-2016 Socionext Inc.
  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
- * SPDX-License-Identifier:	GPL-2.0+	X11
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  */
 
 /dts-v1/;

arch/arm/dts/uniphier-sld8.dtsi

@@ -4,43 +4,7 @@
  * Copyright (C) 2015-2016 Socionext Inc.
  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  */
 
 / {

arch/arm/dts/uniphier-support-card.dtsi

@@ -4,43 +4,7 @@
  * Copyright (C) 2015-2017 Socionext Inc.
  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  */
 
 &system_bus {

arch/arm/dts/zynq-topic-miamilite.dts

@@ -0,0 +1,17 @@
+/*
+ * Topic Miami Lite board DTS
+ *
+ * Copyright (C) 2017 Topic Embedded Products
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include "zynq-topic-miami.dts"
+
+/ {
+	model = "Topic Miami Lite Zynq Board";
+	compatible = "topic,miamilite", "xlnx,zynq-7000";
+};
+
+&qspi {
+	is-dual = <1>;
+};

arch/arm/imx-common/cpu.c

@@ -275,6 +275,9 @@ u32 get_ahb_clk(void)
 
 void arch_preboot_os(void)
 {
+#if defined(CONFIG_PCIE_IMX)
+	imx_pcie_remove();
+#endif
 #if defined(CONFIG_CMD_SATA)
 	sata_stop();
 #if defined(CONFIG_MX6)

arch/arm/include/asm/arch-am33xx/emac_defs.h

@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2010 Texas Instruments
+ *
+ * Based on:
+ *
+ * ----------------------------------------------------------------------------
+ *
+ * dm644x_emac.h
+ *
+ * TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM
+ *
+ * Copyright (C) 2005 Texas Instruments.
+ *
+ * ----------------------------------------------------------------------------
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ */
+
+#ifndef _EMAC_DEFS_H_
+#define _EMAC_DEFS_H_
+
+#ifdef CONFIG_TI816X
+#define EMAC_BASE_ADDR			(0x4A100000)
+#define EMAC_WRAPPER_BASE_ADDR		(0x4A100900)
+#define EMAC_WRAPPER_RAM_ADDR		(0x4A102000)
+#define EMAC_MDIO_BASE_ADDR		(0x4A100800)
+#define EMAC_MDIO_BUS_FREQ		(250000000UL)
+#define EMAC_MDIO_CLOCK_FREQ		(2000000UL)
+
+typedef volatile unsigned int	dv_reg;
+typedef volatile unsigned int	*dv_reg_p;
+
+#define DAVINCI_EMAC_VERSION2
+#define DAVINCI_EMAC_GIG_ENABLE
+#endif
+
+#endif  /* _EMAC_DEFS_H_ */

arch/arm/include/asm/arch-am33xx/hardware_ti816x.h

@@ -31,6 +31,7 @@
 
 /* Control Module Base Address */
 #define CTRL_BASE		0x48140000
+#define CTRL_DEVICE_BASE	0x48140600
 
 /* PRCM Base Address */
 #define PRCM_BASE		0x48180000

arch/arm/include/asm/arch-mx25/clock.h

@@ -51,6 +51,7 @@ enum mxc_clock {
 	MXC_CLK_NUM
 };
 
+int imx_set_perclk(enum mxc_clock clk, bool from_upll, unsigned int freq);
 unsigned int mxc_get_clock(enum mxc_clock clk);
 
 #define imx_get_uartclk()	mxc_get_clock(MXC_UART_CLK)

arch/arm/include/asm/arch-zynqmp/sys_proto.h

@@ -8,6 +8,8 @@
 #ifndef _ASM_ARCH_SYS_PROTO_H
 #define _ASM_ARCH_SYS_PROTO_H
 
+#define PAYLOAD_ARG_CNT		5
+
 int zynq_slcr_get_mio_pin_status(const char *periph);
 
 unsigned int zynqmp_get_silicon_version(void);
@@ -16,4 +18,10 @@ void psu_init(void);
 
 void handoff_setup(void);
 
+void zynqmp_pmufw_version(void);
+int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value);
+int zynqmp_mmio_read(const u32 address, u32 *value);
+int invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, u32 arg3,
+	       u32 *ret_payload);
+
 #endif /* _ASM_ARCH_SYS_PROTO_H */

arch/arm/lib/bootm.c

@@ -360,7 +360,6 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
 #ifdef CONFIG_CPU_V7M
 	ulong addr = (ulong)kernel_entry | 1;
 	kernel_entry = (void *)addr;
-	dcache_disable();
 #endif
 	s = getenv("machid");
 	if (s) {

arch/arm/mach-at91/Kconfig

@@ -124,7 +124,7 @@ config TARGET_SAMA5D4EK
 	select BOARD_EARLY_INIT_F
 
 config TARGET_MA5D4EVK
-	bool "DENX MA5D4EVK Evaluation Kit"
+	bool "Aries MA5D4EVK Evaluation Kit"
 	select CPU_V7
 	select SUPPORT_SPL
 
@@ -169,6 +169,7 @@ endchoice
 config SYS_SOC
 	default "at91"
 
+source "board/aries/ma5d4evk/Kconfig"
 source "board/atmel/at91rm9200ek/Kconfig"
 source "board/atmel/at91sam9260ek/Kconfig"
 source "board/atmel/at91sam9261ek/Kconfig"
@@ -186,7 +187,6 @@ source "board/atmel/sama5d4ek/Kconfig"
 source "board/bluewater/gurnard/Kconfig"
 source "board/bluewater/snapper9260/Kconfig"
 source "board/calao/usb_a9263/Kconfig"
-source "board/denx/ma5d4evk/Kconfig"
 source "board/egnite/ethernut5/Kconfig"
 source "board/esd/meesc/Kconfig"
 source "board/l+g/vinco/Kconfig"

arch/arm/mach-omap2/boot-common.c

@@ -64,6 +64,23 @@ void save_omap_boot_params(void)
 	 */
 	if (boot_device == BOOT_DEVICE_QSPI_4)
 		boot_device = BOOT_DEVICE_SPI;
+#endif
+#ifdef CONFIG_TI816X
+	/*
+	 * On PG2.0 and later TI816x the values we get when booting are not the
+	 * same as on PG1.0, which is what the defines are based on.  Update
+	 * them as needed.
+	 */
+	if (get_cpu_rev() != 1) {
+		if (boot_device == 0x05) {
+			omap_boot_params->boot_device = BOOT_DEVICE_NAND;
+			boot_device = BOOT_DEVICE_NAND;
+		}
+		if (boot_device == 0x08) {
+			omap_boot_params->boot_device = BOOT_DEVICE_MMC1;
+			boot_device = BOOT_DEVICE_MMC1;
+		}
+	}
 #endif
 	/*
 	 * When booting from peripheral booting, the boot device is not usable

arch/arm/mach-stm32/stm32f7/soc.c

@@ -17,6 +17,8 @@ u32 get_cpu_rev(void)
 
 int arch_cpu_init(void)
 {
+	int i;
+
 	struct mpu_region_config stm32_region_config[] = {
 		{ 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW,
 		O_I_WB_RD_WR_ALLOC, REGION_4GB },
@@ -35,7 +37,7 @@ int arch_cpu_init(void)
 	};
 
 	disable_mpu();
-	for (int i = 0; i < ARRAY_SIZE(stm32_region_config); i++)
+	for (i = 0; i < ARRAY_SIZE(stm32_region_config); i++)
 		mpu_config(&stm32_region_config[i]);
 	enable_mpu();
 

arch/arm/mach-uniphier/arm64/arm-cci500.c

@@ -11,6 +11,8 @@
 #include <linux/io.h>
 #include <linux/sizes.h>
 
+#include "../init.h"
+
 #define CCI500_BASE			0x5FD00000
 #define CCI500_SLAVE_OFFSET		0x1000
 

arch/arm/mach-uniphier/arm64/smp_kick_cpus.c

@@ -8,6 +8,8 @@
 #include <linux/io.h>
 #include <linux/sizes.h>
 
+#include "../init.h"
+
 #define UNIPHIER_SMPCTRL_ROM_RSV0	0x59801200
 
 void uniphier_smp_setup(void);

arch/arm/mach-uniphier/board_init.c

@@ -21,7 +21,7 @@ static void uniphier_setup_xirq(void)
 {
 	const void *fdt = gd->fdt_blob;
 	int soc_node, aidet_node;
-	const u32 *val;
+	const fdt32_t *val;
 	unsigned long aidet_base;
 	u32 tmp;
 

arch/arm/mach-uniphier/clk/pll-pxs3.c

@@ -2,6 +2,8 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
+#include "../init.h"
+
 void uniphier_pxs3_pll_init(void)
 {
 }

arch/arm/mach-uniphier/dram/umc-ld11.c

@@ -28,11 +28,11 @@ enum dram_size {
 };
 
 /* PHY */
-const int rof_pos_shift_pre[RANK_BLOCKS_TR][2] = { {0, 0}, {0, 0} };
-const int rof_neg_shift_pre[RANK_BLOCKS_TR][2] = { {0, 0}, {0, 0} };
-const int rof_pos_shift[RANK_BLOCKS_TR][2] = { {-35, -35}, {-35, -35} };
-const int rof_neg_shift[RANK_BLOCKS_TR][2] = { {-17, -17}, {-17, -17} };
-const int tof_shift[RANK_BLOCKS_TR][2] = { {-50, -50}, {-50, -50} };
+static const int rof_pos_shift_pre[RANK_BLOCKS_TR][2] = { {0, 0}, {0, 0} };
+static const int rof_neg_shift_pre[RANK_BLOCKS_TR][2] = { {0, 0}, {0, 0} };
+static const int rof_pos_shift[RANK_BLOCKS_TR][2] = { {-35, -35}, {-35, -35} };
+static const int rof_neg_shift[RANK_BLOCKS_TR][2] = { {-17, -17}, {-17, -17} };
+static const int tof_shift[RANK_BLOCKS_TR][2] = { {-50, -50}, {-50, -50} };
 
 /* Register address */
 #define PHY_ZQ0CR1	0x00000184
@@ -65,7 +65,7 @@ const int tof_shift[RANK_BLOCKS_TR][2] = { {-50, -50}, {-50, -50} };
 #define PHY_DSWBD_MASK		0x3F000000	/* bit[29:24] */
 #define PHY_DSDQOE_MASK		0x00000FFF
 
-static void ddrphy_maskwritel(u32 data, u32 mask, void *addr)
+static void ddrphy_maskwritel(u32 data, u32 mask, void __iomem *addr)
 {
 	u32 value;
 
@@ -73,7 +73,7 @@ static void ddrphy_maskwritel(u32 data, u32 mask, void *addr)
 	writel(value, addr);
 }
 
-static u32 ddrphy_maskreadl(u32 mask, void *addr)
+static u32 ddrphy_maskreadl(u32 mask, void __iomem *addr)
 {
 	return readl(addr) & mask;
 }

arch/arm/mach-uniphier/dram/umc-pxs2.c

@@ -436,7 +436,7 @@ static void umc_set_system_latency(void __iomem *dc_base, int phy_latency)
 }
 
 /* enable/disable auto refresh */
-void umc_refresh_ctrl(void __iomem *dc_base, int enable)
+static void umc_refresh_ctrl(void __iomem *dc_base, int enable)
 {
 	u32 tmp;
 

arch/arm/mach-uniphier/dram_init.c

@@ -7,6 +7,7 @@
  */
 
 #include <common.h>
+#include <fdt_support.h>
 #include <fdtdec.h>
 #include <linux/errno.h>
 #include <linux/sizes.h>

arch/arm/mach-uniphier/init.h

@@ -126,7 +126,7 @@ int uniphier_have_internal_stm(void);
 int uniphier_boot_from_backend(void);
 int uniphier_pin_init(const char *pinconfig_name);
 void uniphier_smp_kick_all_cpus(void);
-void cci500_init(int nr_slaves);
+void cci500_init(unsigned int nr_slaves);
 
 #undef pr_warn
 #define pr_warn(fmt, args...)	printf(fmt, ##args)

arch/arm/mach-zynq/Kconfig

@@ -24,6 +24,14 @@ config SPL_SPI_FLASH_SUPPORT
 config SPL_SPI_SUPPORT
 	default y if ZYNQ_QSPI
 
+config ZYNQ_DDRC_INIT
+	bool "Zynq DDRC initialization"
+	default y
+	help
+	  This option used to perform DDR specific initialization
+	  if required. There might be cases like ddr less where we
+	  want to skip ddr init and this option is useful for it.
+
 config SYS_BOARD
 	default "zynq"
 

arch/arm/mach-zynq/ddrc.c

@@ -12,6 +12,9 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifndef CONFIG_ZYNQ_DDRC_INIT
+void zynq_ddrc_init(void) {}
+#else
 /* Control regsiter bitfield definitions */
 #define ZYNQ_DDRC_CTRLREG_BUSWIDTH_MASK		0xC
 #define ZYNQ_DDRC_CTRLREG_BUSWIDTH_SHIFT	2
@@ -46,3 +49,4 @@ void zynq_ddrc_init(void)
 		puts("ECC disabled ");
 	}
 }
+#endif

arch/avr32/Kconfig

@@ -1,30 +0,0 @@
-menu "AVR32 architecture"
-	depends on AVR32
-
-config SYS_ARCH
-	default "avr32"
-
-choice
-	prompt "Target select"
-	optional
-
-config TARGET_ATNGW100
-	bool "Support atngw100"
-
-config TARGET_ATNGW100MKII
-	bool "Support atngw100mkii"
-
-config TARGET_ATSTK1002
-	bool "Support atstk1002"
-
-config TARGET_GRASSHOPPER
-	bool "Support grasshopper"
-
-endchoice
-
-source "board/atmel/atngw100/Kconfig"
-source "board/atmel/atngw100mkii/Kconfig"
-source "board/atmel/atstk1000/Kconfig"
-source "board/in-circuit/grasshopper/Kconfig"
-
-endmenu

arch/avr32/Makefile

@@ -1,8 +0,0 @@
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-head-y := arch/avr32/cpu/start.o
-
-libs-y += arch/avr32/cpu/
-libs-y += arch/avr32/lib/

arch/avr32/config.mk

@@ -1,17 +0,0 @@
-#
-# (C) Copyright 2000-2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-ifeq ($(CROSS_COMPILE),)
-CROSS_COMPILE := avr32-linux-
-endif
-
-CONFIG_STANDALONE_LOAD_ADDR ?= 0x00000000
-
-PLATFORM_RELFLAGS	+= -ffixed-r5 -fPIC -mno-init-got -mrelax
-PLATFORM_RELFLAGS	+= -ffunction-sections -fdata-sections
-
-LDFLAGS_u-boot		= --gc-sections --relax

arch/avr32/cpu/Makefile

@@ -1,21 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Copyright (C) 2005-2006 Atmel Corporation.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-extra-y			+= start.o
-
-obj-y			+= cpu.o
-obj-$(CONFIG_SYS_HSDRAMC) += hsdramc.o
-obj-y			+= exception.o
-obj-y			+= cache.o
-obj-y			+= interrupts.o
-obj-$(CONFIG_PORTMUX_PIO) += portmux-pio.o
-obj-$(CONFIG_PORTMUX_GPIO) += portmux-gpio.o
-obj-y += mmc.o
-
-obj-$(if $(filter at32ap700x,$(SOC)),y) += at32ap700x/

arch/avr32/cpu/at32ap700x/Makefile

@@ -1,7 +0,0 @@
-#
-# Copyright (C) 2005-2006 Atmel Corporation
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= portmux.o clk.o mmu.o

arch/avr32/cpu/at32ap700x/clk.c

@@ -1,82 +0,0 @@
-/*
- * Copyright (C) 2005-2008 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-
-#include <asm/io.h>
-
-#include <asm/arch/clk.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/portmux.h>
-
-#include "sm.h"
-
-void clk_init(void)
-{
-	uint32_t cksel;
-
-	/* in case of soft resets, disable watchdog */
-	sm_writel(WDT_CTRL, SM_BF(KEY, 0x55));
-	sm_writel(WDT_CTRL, SM_BF(KEY, 0xaa));
-
-#ifdef CONFIG_PLL
-	/* Initialize the PLL */
-	sm_writel(PM_PLL0, (SM_BF(PLLCOUNT, CONFIG_SYS_PLL0_SUPPRESS_CYCLES)
-			    | SM_BF(PLLMUL, CONFIG_SYS_PLL0_MUL - 1)
-			    | SM_BF(PLLDIV, CONFIG_SYS_PLL0_DIV - 1)
-			    | SM_BF(PLLOPT, CONFIG_SYS_PLL0_OPT)
-			    | SM_BF(PLLOSC, 0)
-			    | SM_BIT(PLLEN)));
-
-	/* Wait for lock */
-	while (!(sm_readl(PM_ISR) & SM_BIT(LOCK0))) ;
-#endif
-
-	/* Set up clocks for the CPU and all peripheral buses */
-	cksel = 0;
-	if (CONFIG_SYS_CLKDIV_CPU)
-		cksel |= SM_BIT(CPUDIV) | SM_BF(CPUSEL, CONFIG_SYS_CLKDIV_CPU - 1);
-	if (CONFIG_SYS_CLKDIV_HSB)
-		cksel |= SM_BIT(HSBDIV) | SM_BF(HSBSEL, CONFIG_SYS_CLKDIV_HSB - 1);
-	if (CONFIG_SYS_CLKDIV_PBA)
-		cksel |= SM_BIT(PBADIV) | SM_BF(PBASEL, CONFIG_SYS_CLKDIV_PBA - 1);
-	if (CONFIG_SYS_CLKDIV_PBB)
-		cksel |= SM_BIT(PBBDIV) | SM_BF(PBBSEL, CONFIG_SYS_CLKDIV_PBB - 1);
-	sm_writel(PM_CKSEL, cksel);
-
-#ifdef CONFIG_PLL
-	/* Use PLL0 as main clock */
-	sm_writel(PM_MCCTRL, SM_BIT(PLLSEL));
-
-#ifdef CONFIG_LCD
-	/* Set up pixel clock for the LCDC */
-	sm_writel(PM_GCCTRL(7), SM_BIT(PLLSEL) | SM_BIT(CEN));
-#endif
-#endif
-}
-
-unsigned long __gclk_set_rate(unsigned int id, enum gclk_parent parent,
-		unsigned long rate, unsigned long parent_rate)
-{
-	unsigned long divider;
-
-	if (rate == 0 || parent_rate == 0) {
-		sm_writel(PM_GCCTRL(id), 0);
-		return 0;
-	}
-
-	divider = (parent_rate + rate / 2) / rate;
-	if (divider <= 1) {
-		sm_writel(PM_GCCTRL(id), parent | SM_BIT(CEN));
-		rate = parent_rate;
-	} else {
-		divider = min(255UL, divider / 2 - 1);
-		sm_writel(PM_GCCTRL(id), parent | SM_BIT(CEN) | SM_BIT(DIVEN)
-				| SM_BF(DIV, divider));
-		rate = parent_rate / (2 * (divider + 1));
-	}
-
-	return rate;
-}

arch/avr32/cpu/at32ap700x/mmu.c

@@ -1,78 +0,0 @@
-#include <common.h>
-#include <asm/arch/mmu.h>
-#include <asm/sysreg.h>
-
-void mmu_init_r(unsigned long dest_addr)
-{
-	uintptr_t	vmr_table_addr;
-
-	/* Round monitor address down to the nearest page boundary */
-	dest_addr &= MMU_PAGE_ADDR_MASK;
-
-	/* Initialize TLB entry 0 to cover the monitor, and lock it */
-	sysreg_write(TLBEHI, dest_addr | SYSREG_BIT(TLBEHI_V));
-	sysreg_write(TLBELO, dest_addr | MMU_VMR_CACHE_WRBACK);
-	sysreg_write(MMUCR, SYSREG_BF(DRP, 0) | SYSREG_BF(DLA, 1)
-			| SYSREG_BIT(MMUCR_S) | SYSREG_BIT(M));
-	__builtin_tlbw();
-
-	/*
-	 * Calculate the address of the VM range table in a PC-relative
-	 * manner to make sure we hit the SDRAM and not the flash.
-	 */
-	vmr_table_addr = (uintptr_t)&mmu_vmr_table;
-	sysreg_write(PTBR, vmr_table_addr);
-	printf("VMR table @ 0x%08lx\n", vmr_table_addr);
-
-	/* Enable paging */
-	sysreg_write(MMUCR, SYSREG_BF(DRP, 1) | SYSREG_BF(DLA, 1)
-			| SYSREG_BIT(MMUCR_S) | SYSREG_BIT(M) | SYSREG_BIT(E));
-}
-
-int mmu_handle_tlb_miss(void)
-{
-	const struct mmu_vm_range *vmr_table;
-	const struct mmu_vm_range *vmr;
-	unsigned int fault_pgno;
-	int first, last;
-
-	fault_pgno = sysreg_read(TLBEAR) >> MMU_PAGE_SHIFT;
-	vmr_table = (const struct mmu_vm_range *)sysreg_read(PTBR);
-
-	/* Do a binary search through the VM ranges */
-	first = 0;
-	last = CONFIG_SYS_NR_VM_REGIONS;
-	while (first < last) {
-		unsigned int start;
-		int middle;
-
-		/* Pick the entry in the middle of the remaining range */
-		middle = (first + last) >> 1;
-		vmr = &vmr_table[middle];
-		start = vmr->virt_pgno;
-
-		/* Do the bisection thing */
-		if (fault_pgno < start) {
-			last = middle;
-		} else if (fault_pgno >= (start + vmr->nr_pages)) {
-			first = middle + 1;
-		} else {
-			/* Got it; let's slam it into the TLB */
-			uint32_t tlbelo;
-
-			tlbelo = vmr->phys & ~MMU_PAGE_ADDR_MASK;
-			tlbelo |= fault_pgno << MMU_PAGE_SHIFT;
-			sysreg_write(TLBELO, tlbelo);
-			__builtin_tlbw();
-
-			/* Zero means success */
-			return 0;
-		}
-	}
-
-	/*
-	 * Didn't find any matching entries. Return a nonzero value to
-	 * indicate that this should be treated as a fatal exception.
-	 */
-	return -1;
-}

arch/avr32/cpu/at32ap700x/portmux.c

@@ -1,278 +0,0 @@
-/*
- * Copyright (C) 2006, 2008 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-
-#include <asm/io.h>
-
-#include <asm/arch/chip-features.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/portmux.h>
-
-/*
- * Lots of small functions here. We depend on --gc-sections getting
- * rid of the ones we don't need.
- */
-void portmux_enable_ebi(unsigned int bus_width, unsigned int addr_width,
-		unsigned long flags, unsigned long drive_strength)
-{
-	unsigned long porte_mask = 0;
-
-	if (bus_width > 16)
-		portmux_select_peripheral(PORTMUX_PORT_E, 0xffff,
-				PORTMUX_FUNC_A, PORTMUX_BUSKEEPER);
-	if (addr_width > 23)
-		porte_mask |= (((1 << (addr_width - 23)) - 1) & 7) << 16;
-	if (flags & PORTMUX_EBI_CS(2))
-		porte_mask |= 1 << 25;
-	if (flags & PORTMUX_EBI_CS(4))
-		porte_mask |= 1 << 21;
-	if (flags & PORTMUX_EBI_CS(5))
-		porte_mask |= 1 << 22;
-	if (flags & (PORTMUX_EBI_CF(0) | PORTMUX_EBI_CF(1)))
-		porte_mask |= (1 << 19) | (1 << 20) | (1 << 23);
-
-	portmux_select_peripheral(PORTMUX_PORT_E, porte_mask,
-			PORTMUX_FUNC_A, 0);
-
-	if (flags & PORTMUX_EBI_NWAIT)
-		portmux_select_peripheral(PORTMUX_PORT_E, 1 << 24,
-				PORTMUX_FUNC_A, PORTMUX_PULL_UP);
-}
-
-#ifdef AT32AP700x_CHIP_HAS_MACB
-void portmux_enable_macb0(unsigned long flags, unsigned long drive_strength)
-{
-	unsigned long portc_mask;
-
-	portc_mask = (1 << 3)	/* TXD0	*/
-		| (1 << 4)	/* TXD1	*/
-		| (1 << 7)	/* TXEN	*/
-		| (1 << 8)	/* TXCK */
-		| (1 << 9)	/* RXD0	*/
-		| (1 << 10)	/* RXD1	*/
-		| (1 << 13)	/* RXER	*/
-		| (1 << 15)	/* RXDV	*/
-		| (1 << 16)	/* MDC	*/
-		| (1 << 17);	/* MDIO	*/
-
-	if (flags & PORTMUX_MACB_MII)
-		portc_mask |= (1 << 0)	/* COL	*/
-			| (1 << 1)	/* CRS	*/
-			| (1 << 2)	/* TXER	*/
-			| (1 << 5)	/* TXD2	*/
-			| (1 << 6)	/* TXD3 */
-			| (1 << 11)	/* RXD2	*/
-			| (1 << 12)	/* RXD3	*/
-			| (1 << 14);	/* RXCK	*/
-
-	if (flags & PORTMUX_MACB_SPEED)
-		portc_mask |= (1 << 18);/* SPD	*/
-
-	/* REVISIT: Some pins are probably pure outputs */
-	portmux_select_peripheral(PORTMUX_PORT_C, portc_mask,
-			PORTMUX_FUNC_A, PORTMUX_BUSKEEPER);
-}
-
-void portmux_enable_macb1(unsigned long flags, unsigned long drive_strength)
-{
-	unsigned long portc_mask = 0;
-	unsigned long portd_mask;
-
-	portd_mask = (1 << 13)	/* TXD0	*/
-		| (1 << 14)	/* TXD1	*/
-		| (1 << 11)	/* TXEN	*/
-		| (1 << 12)	/* TXCK */
-		| (1 << 10)	/* RXD0	*/
-		| (1 << 6)	/* RXD1	*/
-		| (1 << 5)	/* RXER	*/
-		| (1 << 4)	/* RXDV	*/
-		| (1 << 3)	/* MDC	*/
-		| (1 << 2);	/* MDIO	*/
-
-	if (flags & PORTMUX_MACB_MII)
-		portc_mask = (1 << 19)	/* COL	*/
-			| (1 << 23)	/* CRS	*/
-			| (1 << 26)	/* TXER	*/
-			| (1 << 27)	/* TXD2	*/
-			| (1 << 28)	/* TXD3 */
-			| (1 << 29)	/* RXD2	*/
-			| (1 << 30)	/* RXD3	*/
-			| (1 << 24);	/* RXCK	*/
-
-	if (flags & PORTMUX_MACB_SPEED)
-		portd_mask |= (1 << 15);/* SPD	*/
-
-	/* REVISIT: Some pins are probably pure outputs */
-	portmux_select_peripheral(PORTMUX_PORT_D, portd_mask,
-			PORTMUX_FUNC_B, PORTMUX_BUSKEEPER);
-	portmux_select_peripheral(PORTMUX_PORT_C, portc_mask,
-			PORTMUX_FUNC_B, PORTMUX_BUSKEEPER);
-}
-#endif
-
-#ifdef AT32AP700x_CHIP_HAS_MMCI
-void portmux_enable_mmci(unsigned int slot, unsigned long flags,
-		unsigned long drive_strength)
-{
-	unsigned long mask;
-	unsigned long portmux_flags = PORTMUX_PULL_UP;
-
-	/* First, the common CLK signal. It doesn't need a pull-up */
-	portmux_select_peripheral(PORTMUX_PORT_A, 1 << 10,
-			PORTMUX_FUNC_A, 0);
-
-	if (flags & PORTMUX_MMCI_EXT_PULLUP)
-		portmux_flags = 0;
-
-	/* Then, the per-slot signals */
-	switch (slot) {
-	case 0:
-		mask = (1 << 11) | (1 << 12);	/* CMD and DATA0 */
-		if (flags & PORTMUX_MMCI_4BIT)
-			/* DATA1..DATA3 */
-			mask |= (1 << 13) | (1 << 14) | (1 << 15);
-		portmux_select_peripheral(PORTMUX_PORT_A, mask,
-				PORTMUX_FUNC_A, portmux_flags);
-		break;
-	case 1:
-		mask = (1 << 6) | (1 << 7);	/* CMD and DATA0 */
-		if (flags & PORTMUX_MMCI_4BIT)
-			/* DATA1..DATA3 */
-			mask |= (1 << 8) | (1 << 9) | (1 << 10);
-		portmux_select_peripheral(PORTMUX_PORT_B, mask,
-				PORTMUX_FUNC_B, portmux_flags);
-		break;
-	}
-}
-#endif
-
-#ifdef AT32AP700x_CHIP_HAS_SPI
-void portmux_enable_spi0(unsigned long cs_mask, unsigned long drive_strength)
-{
-	unsigned long pin_mask;
-
-	/* MOSI and SCK */
-	portmux_select_peripheral(PORTMUX_PORT_A, (1 << 1) | (1 << 2),
-			PORTMUX_FUNC_A, 0);
-	/* MISO may float */
-	portmux_select_peripheral(PORTMUX_PORT_A, 1 << 0,
-			PORTMUX_FUNC_A, PORTMUX_BUSKEEPER);
-
-	/* Set up NPCSx as GPIO outputs, initially high */
-	pin_mask = (cs_mask & 7) << 3;
-	if (cs_mask & (1 << 3))
-		pin_mask |= 1 << 20;
-
-	portmux_select_gpio(PORTMUX_PORT_A, pin_mask,
-			PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH);
-}
-
-void portmux_enable_spi1(unsigned long cs_mask, unsigned long drive_strength)
-{
-	/* MOSI and SCK */
-	portmux_select_peripheral(PORTMUX_PORT_B, (1 << 1) | (1 << 5),
-			PORTMUX_FUNC_B, 0);
-	/* MISO may float */
-	portmux_select_peripheral(PORTMUX_PORT_B, 1 << 0,
-			PORTMUX_FUNC_B, PORTMUX_BUSKEEPER);
-
-	/* Set up NPCSx as GPIO outputs, initially high */
-	portmux_select_gpio(PORTMUX_PORT_B, (cs_mask & 7) << 2,
-			PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH);
-	portmux_select_gpio(PORTMUX_PORT_A, (cs_mask & 8) << (27 - 3),
-			PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH);
-}
-#endif
-
-#ifdef AT32AP700x_CHIP_HAS_LCDC
-void portmux_enable_lcdc(int pin_config)
-{
-	unsigned long portc_mask = 0;
-	unsigned long portd_mask = 0;
-	unsigned long porte_mask = 0;
-
-	switch (pin_config) {
-	case 0:
-		portc_mask = (1 << 19)	/* CC     */
-			| (1 << 20)	/* HSYNC  */
-			| (1 << 21)	/* PCLK   */
-			| (1 << 22)	/* VSYNC  */
-			| (1 << 23)	/* DVAL   */
-			| (1 << 24)	/* MODE   */
-			| (1 << 25)	/* PWR    */
-			| (1 << 26)	/* DATA0  */
-			| (1 << 27)	/* DATA1  */
-			| (1 << 28)	/* DATA2  */
-			| (1 << 29)	/* DATA3  */
-			| (1 << 30)	/* DATA4  */
-			| (1 << 31);	/* DATA5  */
-
-		portd_mask = (1 << 0)	/* DATA6  */
-			| (1 << 1)	/* DATA7  */
-			| (1 << 2)	/* DATA8  */
-			| (1 << 3)	/* DATA9  */
-			| (1 << 4)	/* DATA10 */
-			| (1 << 5)	/* DATA11 */
-			| (1 << 6)	/* DATA12 */
-			| (1 << 7)	/* DATA13 */
-			| (1 << 8)	/* DATA14 */
-			| (1 << 9)	/* DATA15 */
-			| (1 << 10)	/* DATA16 */
-			| (1 << 11)	/* DATA17 */
-			| (1 << 12)	/* DATA18 */
-			| (1 << 13)	/* DATA19 */
-			| (1 << 14)	/* DATA20 */
-			| (1 << 15)	/* DATA21 */
-			| (1 << 16)	/* DATA22 */
-			| (1 << 17);	/* DATA23 */
-		break;
-
-	case 1:
-		portc_mask = (1 << 20)	/* HSYNC  */
-			| (1 << 21)	/* PCLK   */
-			| (1 << 22)	/* VSYNC  */
-			| (1 << 25)	/* PWR    */
-			| (1 << 31);	/* DATA5  */
-
-		portd_mask = (1 << 0)	/* DATA6  */
-			| (1 << 1)	/* DATA7  */
-			| (1 << 7)	/* DATA13 */
-			| (1 << 8)	/* DATA14 */
-			| (1 << 9)	/* DATA15 */
-			| (1 << 16)	/* DATA22 */
-			| (1 << 17);	/* DATA23 */
-
-		porte_mask = (1 << 0)	/* CC     */
-			| (1 << 1)	/* DVAL   */
-			| (1 << 2)	/* MODE   */
-			| (1 << 3)	/* DATA0  */
-			| (1 << 4)	/* DATA1  */
-			| (1 << 5)	/* DATA2  */
-			| (1 << 6)	/* DATA3  */
-			| (1 << 7)	/* DATA4  */
-			| (1 << 8)	/* DATA8  */
-			| (1 << 9)	/* DATA9  */
-			| (1 << 10)	/* DATA10 */
-			| (1 << 11)	/* DATA11 */
-			| (1 << 12)	/* DATA12 */
-			| (1 << 13)	/* DATA16 */
-			| (1 << 14)	/* DATA17 */
-			| (1 << 15)	/* DATA18 */
-			| (1 << 16)	/* DATA19 */
-			| (1 << 17)	/* DATA20 */
-			| (1 << 18);	/* DATA21 */
-		break;
-	}
-
-	/* REVISIT: Some pins are probably pure outputs */
-	portmux_select_peripheral(PORTMUX_PORT_C, portc_mask,
-			PORTMUX_FUNC_A, PORTMUX_BUSKEEPER);
-	portmux_select_peripheral(PORTMUX_PORT_D, portd_mask,
-			PORTMUX_FUNC_A, PORTMUX_BUSKEEPER);
-	portmux_select_peripheral(PORTMUX_PORT_E, porte_mask,
-			PORTMUX_FUNC_B, PORTMUX_BUSKEEPER);
-}
-#endif

arch/avr32/cpu/at32ap700x/sm.h

@@ -1,204 +0,0 @@
-/*
- * Register definitions for System Manager
- */
-#ifndef __CPU_AT32AP_SM_H__
-#define __CPU_AT32AP_SM_H__
-
-/* SM register offsets */
-#define SM_PM_MCCTRL				0x0000
-#define SM_PM_CKSEL				0x0004
-#define SM_PM_CPU_MASK				0x0008
-#define SM_PM_HSB_MASK				0x000c
-#define SM_PM_PBA_MASK				0x0010
-#define SM_PM_PBB_MASK				0x0014
-#define SM_PM_PLL0				0x0020
-#define SM_PM_PLL1				0x0024
-#define SM_PM_VCTRL				0x0030
-#define SM_PM_VMREF				0x0034
-#define SM_PM_VMV				0x0038
-#define SM_PM_IER				0x0040
-#define SM_PM_IDR				0x0044
-#define SM_PM_IMR				0x0048
-#define SM_PM_ISR				0x004c
-#define SM_PM_ICR				0x0050
-#define SM_PM_GCCTRL(x)				(0x0060 + 4 * x)
-#define SM_RTC_CTRL				0x0080
-#define SM_RTC_VAL				0x0084
-#define SM_RTC_TOP				0x0088
-#define SM_RTC_IER				0x0090
-#define SM_RTC_IDR				0x0094
-#define SM_RTC_IMR				0x0098
-#define SM_RTC_ISR				0x009c
-#define SM_RTC_ICR				0x00a0
-#define SM_WDT_CTRL				0x00b0
-#define SM_WDT_CLR				0x00b4
-#define SM_WDT_EXT				0x00b8
-#define SM_RC_RCAUSE				0x00c0
-#define SM_EIM_IER				0x0100
-#define SM_EIM_IDR				0x0104
-#define SM_EIM_IMR				0x0108
-#define SM_EIM_ISR				0x010c
-#define SM_EIM_ICR				0x0110
-#define SM_EIM_MODE				0x0114
-#define SM_EIM_EDGE				0x0118
-#define SM_EIM_LEVEL				0x011c
-#define SM_EIM_TEST				0x0120
-#define SM_EIM_NMIC				0x0124
-
-/* Bitfields in PM_CKSEL */
-#define SM_CPUSEL_OFFSET			0
-#define SM_CPUSEL_SIZE				3
-#define SM_CPUDIV_OFFSET			7
-#define SM_CPUDIV_SIZE				1
-#define SM_HSBSEL_OFFSET			8
-#define SM_HSBSEL_SIZE				3
-#define SM_HSBDIV_OFFSET			15
-#define SM_HSBDIV_SIZE				1
-#define SM_PBASEL_OFFSET			16
-#define SM_PBASEL_SIZE				3
-#define SM_PBADIV_OFFSET			23
-#define SM_PBADIV_SIZE				1
-#define SM_PBBSEL_OFFSET			24
-#define SM_PBBSEL_SIZE				3
-#define SM_PBBDIV_OFFSET			31
-#define SM_PBBDIV_SIZE				1
-
-/* Bitfields in PM_PLL0 */
-#define SM_PLLEN_OFFSET				0
-#define SM_PLLEN_SIZE				1
-#define SM_PLLOSC_OFFSET			1
-#define SM_PLLOSC_SIZE				1
-#define SM_PLLOPT_OFFSET			2
-#define SM_PLLOPT_SIZE				3
-#define SM_PLLDIV_OFFSET			8
-#define SM_PLLDIV_SIZE				8
-#define SM_PLLMUL_OFFSET			16
-#define SM_PLLMUL_SIZE				8
-#define SM_PLLCOUNT_OFFSET			24
-#define SM_PLLCOUNT_SIZE			6
-#define SM_PLLTEST_OFFSET			31
-#define SM_PLLTEST_SIZE				1
-
-/* Bitfields in PM_VCTRL */
-#define SM_VAUTO_OFFSET				0
-#define SM_VAUTO_SIZE				1
-#define SM_PM_VCTRL_VAL_OFFSET			8
-#define SM_PM_VCTRL_VAL_SIZE			7
-
-/* Bitfields in PM_VMREF */
-#define SM_REFSEL_OFFSET			0
-#define SM_REFSEL_SIZE				4
-
-/* Bitfields in PM_VMV */
-#define SM_PM_VMV_VAL_OFFSET			0
-#define SM_PM_VMV_VAL_SIZE			8
-
-/* Bitfields in PM_ICR */
-#define SM_LOCK0_OFFSET				0
-#define SM_LOCK0_SIZE				1
-#define SM_LOCK1_OFFSET				1
-#define SM_LOCK1_SIZE				1
-#define SM_WAKE_OFFSET				2
-#define SM_WAKE_SIZE				1
-#define SM_VOK_OFFSET				3
-#define SM_VOK_SIZE				1
-#define SM_VMRDY_OFFSET				4
-#define SM_VMRDY_SIZE				1
-#define SM_CKRDY_OFFSET				5
-#define SM_CKRDY_SIZE				1
-
-/* Bitfields in PM_GCCTRL */
-#define SM_OSCSEL_OFFSET			0
-#define SM_OSCSEL_SIZE				1
-#define SM_PLLSEL_OFFSET			1
-#define SM_PLLSEL_SIZE				1
-#define SM_CEN_OFFSET				2
-#define SM_CEN_SIZE				1
-#define SM_CPC_OFFSET				3
-#define SM_CPC_SIZE				1
-#define SM_DIVEN_OFFSET				4
-#define SM_DIVEN_SIZE				1
-#define SM_DIV_OFFSET				8
-#define SM_DIV_SIZE				8
-
-/* Bitfields in RTC_CTRL */
-#define SM_PCLR_OFFSET				1
-#define SM_PCLR_SIZE				1
-#define SM_TOPEN_OFFSET				2
-#define SM_TOPEN_SIZE				1
-#define SM_CLKEN_OFFSET				3
-#define SM_CLKEN_SIZE				1
-#define SM_PSEL_OFFSET				8
-#define SM_PSEL_SIZE				16
-
-/* Bitfields in RTC_VAL */
-#define SM_RTC_VAL_VAL_OFFSET			0
-#define SM_RTC_VAL_VAL_SIZE			31
-
-/* Bitfields in RTC_TOP */
-#define SM_RTC_TOP_VAL_OFFSET			0
-#define SM_RTC_TOP_VAL_SIZE			32
-
-/* Bitfields in RTC_ICR */
-#define SM_TOPI_OFFSET				0
-#define SM_TOPI_SIZE				1
-
-/* Bitfields in WDT_CTRL */
-#define SM_KEY_OFFSET				24
-#define SM_KEY_SIZE				8
-
-/* Bitfields in RC_RCAUSE */
-#define SM_POR_OFFSET				0
-#define SM_POR_SIZE				1
-#define SM_BOD_OFFSET				1
-#define SM_BOD_SIZE				1
-#define SM_EXT_OFFSET				2
-#define SM_EXT_SIZE				1
-#define SM_WDT_OFFSET				3
-#define SM_WDT_SIZE				1
-#define SM_NTAE_OFFSET				4
-#define SM_NTAE_SIZE				1
-#define SM_SERP_OFFSET				5
-#define SM_SERP_SIZE				1
-
-/* Bitfields in EIM_EDGE */
-#define SM_INT0_OFFSET				0
-#define SM_INT0_SIZE				1
-#define SM_INT1_OFFSET				1
-#define SM_INT1_SIZE				1
-#define SM_INT2_OFFSET				2
-#define SM_INT2_SIZE				1
-#define SM_INT3_OFFSET				3
-#define SM_INT3_SIZE				1
-
-/* Bitfields in EIM_LEVEL */
-
-/* Bitfields in EIM_TEST */
-#define SM_TESTEN_OFFSET			31
-#define SM_TESTEN_SIZE				1
-
-/* Bitfields in EIM_NMIC */
-#define SM_EN_OFFSET				0
-#define SM_EN_SIZE				1
-
-/* Bit manipulation macros */
-#define SM_BIT(name)					\
-	(1 << SM_##name##_OFFSET)
-#define SM_BF(name,value)				\
-	(((value) & ((1 << SM_##name##_SIZE) - 1))	\
-	 << SM_##name##_OFFSET)
-#define SM_BFEXT(name,value)				\
-	(((value) >> SM_##name##_OFFSET)		\
-	 & ((1 << SM_##name##_SIZE) - 1))
-#define SM_BFINS(name,value,old)			\
-	(((old) & ~(((1 << SM_##name##_SIZE) - 1)	\
-		    << SM_##name##_OFFSET))		\
-	 | SM_BF(name,value))
-
-/* Register access macros */
-#define sm_readl(reg)					\
-	readl((void *)ATMEL_BASE_SM + SM_##reg)
-#define sm_writel(reg,value)				\
-	writel((value), (void *)ATMEL_BASE_SM + SM_##reg)
-
-#endif /* __CPU_AT32AP_SM_H__ */

arch/avr32/cpu/cache.c

@@ -1,81 +0,0 @@
-/*
- * Copyright (C) 2004-2006 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-
-#include <asm/arch/cacheflush.h>
-
-void dcache_clean_range(volatile void *start, size_t size)
-{
-	unsigned long v, begin, end, linesz;
-
-	linesz = CONFIG_SYS_DCACHE_LINESZ;
-
-	/* You asked for it, you got it */
-	begin = (unsigned long)start & ~(linesz - 1);
-	end = ((unsigned long)start + size + linesz - 1) & ~(linesz - 1);
-
-	for (v = begin; v < end; v += linesz)
-		dcache_clean_line((void *)v);
-
-	sync_write_buffer();
-}
-
-void invalidate_dcache_range(unsigned long start, unsigned long stop)
-{
-	unsigned long v, linesz;
-
-	linesz = CONFIG_SYS_DCACHE_LINESZ;
-
-	/* You asked for it, you got it */
-	start = start & ~(linesz - 1);
-	stop = (stop + linesz - 1) & ~(linesz - 1);
-
-	for (v = start; v < stop; v += linesz)
-		dcache_invalidate_line((void *)v);
-}
-
-void flush_dcache_range(unsigned long start, unsigned long stop)
-{
-	unsigned long v, linesz;
-
-	linesz = CONFIG_SYS_DCACHE_LINESZ;
-
-	/* You asked for it, you got it */
-	start = start & ~(linesz - 1);
-	stop = (stop + linesz - 1) & ~(linesz - 1);
-
-	for (v = start; v < stop; v += linesz)
-		dcache_flush_line((void *)v);
-
-	sync_write_buffer();
-}
-
-void icache_invalidate_range(volatile void *start, size_t size)
-{
-	unsigned long v, begin, end, linesz;
-
-	linesz = CONFIG_SYS_ICACHE_LINESZ;
-
-	/* You asked for it, you got it */
-	begin = (unsigned long)start & ~(linesz - 1);
-	end = ((unsigned long)start + size + linesz - 1) & ~(linesz - 1);
-
-	for (v = begin; v < end; v += linesz)
-		icache_invalidate_line((void *)v);
-}
-
-/*
- * This is called after loading something into memory.  We need to
- * make sure that everything that was loaded is actually written to
- * RAM, and that the icache will look for it. Cleaning the dcache and
- * invalidating the icache will do the trick.
- */
-void  flush_cache (unsigned long start_addr, unsigned long size)
-{
-	dcache_clean_range((void *)start_addr, size);
-	icache_invalidate_range((void *)start_addr, size);
-}

arch/avr32/cpu/config.mk

@@ -1,6 +0,0 @@
-#
-# Copyright (C) 2005-2006 Atmel Corporation
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-PLATFORM_RELFLAGS       += -mcpu=ap7000

arch/avr32/cpu/cpu.c

@@ -1,73 +0,0 @@
-/*
- * Copyright (C) 2005-2006 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-#include <command.h>
-
-#include <asm/io.h>
-#include <asm/sections.h>
-#include <asm/sysreg.h>
-
-#include <asm/arch/clk.h>
-#include <asm/arch/hardware.h>
-
-#include "hsmc3.h"
-
-/* Sanity checks */
-#if (CONFIG_SYS_CLKDIV_CPU > CONFIG_SYS_CLKDIV_HSB)		\
-	|| (CONFIG_SYS_CLKDIV_HSB > CONFIG_SYS_CLKDIV_PBA)	\
-	|| (CONFIG_SYS_CLKDIV_HSB > CONFIG_SYS_CLKDIV_PBB)
-# error Constraint fCPU >= fHSB >= fPB{A,B} violated
-#endif
-#if defined(CONFIG_PLL) && ((CONFIG_SYS_PLL0_MUL < 1) || (CONFIG_SYS_PLL0_DIV < 1))
-# error Invalid PLL multiplier and/or divider
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int arch_cpu_init(void)
-{
-	extern void _evba(void);
-
-	gd->arch.cpu_hz = CONFIG_SYS_OSC0_HZ;
-
-	/* TODO: Move somewhere else, but needs to be run before we
-	 * increase the clock frequency. */
-	hsmc3_writel(MODE0, 0x00031103);
-	hsmc3_writel(CYCLE0, 0x000c000d);
-	hsmc3_writel(PULSE0, 0x0b0a0906);
-	hsmc3_writel(SETUP0, 0x00010002);
-
-	clk_init();
-
-	/* Update the CPU speed according to the PLL configuration */
-	gd->arch.cpu_hz = get_cpu_clk_rate();
-
-	/* Set up the exception handler table and enable exceptions */
-	sysreg_write(EVBA, (unsigned long)&_evba);
-	asm volatile("csrf	%0" : : "i"(SYSREG_EM_OFFSET));
-
-	return 0;
-}
-
-void prepare_to_boot(void)
-{
-	/* Flush both caches and the write buffer */
-	asm volatile("cache  %0[4], 010\n\t"
-		     "cache  %0[0], 000\n\t"
-		     "sync   0" : : "r"(0) : "memory");
-}
-
-int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	/* This will reset the CPU core, caches, MMU and all internal busses */
-	__builtin_mtdr(8, 1 << 13);	/* set DC:DBE */
-	__builtin_mtdr(8, 1 << 30);	/* set DC:RES */
-
-	/* Flush the pipeline before we declare it a failure */
-	asm volatile("sub   pc, pc, -4");
-
-	return -1;
-}

arch/avr32/cpu/exception.c

@@ -1,108 +0,0 @@
-/*
- * Copyright (C) 2005-2006 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-
-#include <asm/sysreg.h>
-#include <asm/ptrace.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define STACKSIZE	2048
-
-static const char * const cpu_modes[8] = {
-	"Application", "Supervisor", "Interrupt level 0", "Interrupt level 1",
-	"Interrupt level 2", "Interrupt level 3", "Exception", "NMI"
-};
-
-static void dump_mem(const char *str, unsigned long bottom, unsigned long top)
-{
-	unsigned long p;
-	int i;
-
-	printf("%s(0x%08lx to 0x%08lx)\n", str, bottom, top);
-
-	for (p = bottom & ~31; p < top; ) {
-		printf("%04lx: ", p & 0xffff);
-
-		for (i = 0; i < 8; i++, p += 4) {
-			unsigned int val;
-
-			if (p < bottom || p >= top)
-				printf("         ");
-			else {
-				val = *(unsigned long *)p;
-				printf("%08x ", val);
-			}
-		}
-		printf("\n");
-	}
-}
-
-void do_unknown_exception(unsigned int ecr, struct pt_regs *regs)
-{
-	unsigned int mode;
-
-	printf("\n *** Unhandled exception %u at PC=0x%08lx [%08lx]\n",
-			ecr, regs->pc, regs->pc - gd->reloc_off);
-
-	switch (ecr) {
-	case ECR_BUS_ERROR_WRITE:
-	case ECR_BUS_ERROR_READ:
-		printf("Bus error at address 0x%08lx\n",
-		       sysreg_read(BEAR));
-		break;
-	case ECR_TLB_MULTIPLE:
-	case ECR_ADDR_ALIGN_X:
-	case ECR_PROTECTION_X:
-	case ECR_ADDR_ALIGN_R:
-	case ECR_ADDR_ALIGN_W:
-	case ECR_PROTECTION_R:
-	case ECR_PROTECTION_W:
-	case ECR_DTLB_MODIFIED:
-	case ECR_TLB_MISS_X:
-	case ECR_TLB_MISS_R:
-	case ECR_TLB_MISS_W:
-		printf("MMU exception at address 0x%08lx\n",
-		       sysreg_read(TLBEAR));
-		break;
-	}
-
-	printf("   pc: %08lx    lr: %08lx    sp: %08lx   r12: %08lx\n",
-	       regs->pc, regs->lr, regs->sp, regs->r12);
-	printf("  r11: %08lx   r10: %08lx    r9: %08lx    r8: %08lx\n",
-	       regs->r11, regs->r10, regs->r9, regs->r8);
-	printf("   r7: %08lx    r6: %08lx    r5: %08lx    r4: %08lx\n",
-	       regs->r7, regs->r6, regs->r5, regs->r4);
-	printf("   r3: %08lx    r2: %08lx    r1: %08lx    r0: %08lx\n",
-	       regs->r3, regs->r2, regs->r1, regs->r0);
-	printf("Flags: %c%c%c%c%c\n",
-	       regs->sr & SR_Q ? 'Q' : 'q',
-	       regs->sr & SR_V ? 'V' : 'v',
-	       regs->sr & SR_N ? 'N' : 'n',
-	       regs->sr & SR_Z ? 'Z' : 'z',
-	       regs->sr & SR_C ? 'C' : 'c');
-	printf("Mode bits: %c%c%c%c%c%c%c%c%c\n",
-	       regs->sr & SR_H ? 'H' : 'h',
-	       regs->sr & SR_R ? 'R' : 'r',
-	       regs->sr & SR_J ? 'J' : 'j',
-	       regs->sr & SR_EM ? 'E' : 'e',
-	       regs->sr & SR_I3M ? '3' : '.',
-	       regs->sr & SR_I2M ? '2' : '.',
-	       regs->sr & SR_I1M ? '1' : '.',
-	       regs->sr & SR_I0M ? '0' : '.',
-	       regs->sr & SR_GM ? 'G' : 'g');
-	mode = (regs->sr >> SYSREG_M0_OFFSET) & 7;
-	printf("CPU Mode: %s\n", cpu_modes[mode]);
-
-	/* Avoid exception loops */
-	if (regs->sp < (gd->start_addr_sp - STACKSIZE) ||
-	    regs->sp >= gd->start_addr_sp)
-		printf("\nStack pointer seems bogus, won't do stack dump\n");
-	else
-		dump_mem("\nStack: ", regs->sp, gd->start_addr_sp);
-
-	panic("Unhandled exception\n");
-}

arch/avr32/cpu/hsdramc.c

@@ -1,101 +0,0 @@
-/*
- * Copyright (C) 2005-2006 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-
-#include <asm/io.h>
-#include <asm/sdram.h>
-
-#include <asm/arch/clk.h>
-#include <asm/arch/hardware.h>
-
-#include "hsdramc1.h"
-
-unsigned long sdram_init(void *sdram_base, const struct sdram_config *config)
-{
-	unsigned long sdram_size;
-	uint32_t cfgreg;
-	unsigned int i;
-
-	cfgreg = (HSDRAMC1_BF(NC, config->col_bits - 8)
-		       | HSDRAMC1_BF(NR, config->row_bits - 11)
-		       | HSDRAMC1_BF(NB, config->bank_bits - 1)
-		       | HSDRAMC1_BF(CAS, config->cas)
-		       | HSDRAMC1_BF(TWR, config->twr)
-		       | HSDRAMC1_BF(TRC, config->trc)
-		       | HSDRAMC1_BF(TRP, config->trp)
-		       | HSDRAMC1_BF(TRCD, config->trcd)
-		       | HSDRAMC1_BF(TRAS, config->tras)
-		       | HSDRAMC1_BF(TXSR, config->txsr));
-
-	if (config->data_bits == SDRAM_DATA_16BIT)
-		cfgreg |= HSDRAMC1_BIT(DBW);
-
-	hsdramc1_writel(CR, cfgreg);
-
-	/* Send a NOP to turn on the clock (necessary on some chips) */
-	hsdramc1_writel(MR, HSDRAMC1_MODE_NOP);
-	hsdramc1_readl(MR);
-	writel(0, sdram_base);
-
-	/*
-	 * Initialization sequence for SDRAM, from the data sheet:
-	 *
-	 * 1. A minimum pause of 200 us is provided to precede any
-	 *    signal toggle.
-	 */
-	udelay(200);
-
-	/*
-	 * 2. A Precharge All command is issued to the SDRAM
-	 */
-	hsdramc1_writel(MR, HSDRAMC1_MODE_BANKS_PRECHARGE);
-	hsdramc1_readl(MR);
-	writel(0, sdram_base);
-
-	/*
-	 * 3. Eight auto-refresh (CBR) cycles are provided
-	 */
-	hsdramc1_writel(MR, HSDRAMC1_MODE_AUTO_REFRESH);
-	hsdramc1_readl(MR);
-	for (i = 0; i < 8; i++)
-		writel(0, sdram_base);
-
-	/*
-	 * 4. A mode register set (MRS) cycle is issued to program
-	 *    SDRAM parameters, in particular CAS latency and burst
-	 *    length.
-	 *
-	 * The address will be chosen by the SDRAMC automatically; we
-	 * just have to make sure BA[1:0] are set to 0.
-	 */
-	hsdramc1_writel(MR, HSDRAMC1_MODE_LOAD_MODE);
-	hsdramc1_readl(MR);
-	writel(0, sdram_base);
-
-	/*
-	 * 5. The application must go into Normal Mode, setting Mode
-	 *    to 0 in the Mode Register and performing a write access
-	 *    at any location in the SDRAM.
-	 */
-	hsdramc1_writel(MR, HSDRAMC1_MODE_NORMAL);
-	hsdramc1_readl(MR);
-	writel(0, sdram_base);
-
-	/*
-	 * 6. Write refresh rate into SDRAMC refresh timer count
-	 *    register (refresh rate = timing between refresh cycles).
-	 */
-	hsdramc1_writel(TR, config->refresh_period);
-
-	if (config->data_bits == SDRAM_DATA_16BIT)
-		sdram_size = 1 << (config->row_bits + config->col_bits
-				   + config->bank_bits + 1);
-	else
-		sdram_size = 1 << (config->row_bits + config->col_bits
-				   + config->bank_bits + 2);
-
-	return sdram_size;
-}

arch/avr32/cpu/hsdramc1.h

@@ -1,143 +0,0 @@
-/*
- * Register definitions for SDRAM Controller
- */
-#ifndef __ASM_AVR32_HSDRAMC1_H__
-#define __ASM_AVR32_HSDRAMC1_H__
-
-/* HSDRAMC1 register offsets */
-#define HSDRAMC1_MR				0x0000
-#define HSDRAMC1_TR				0x0004
-#define HSDRAMC1_CR				0x0008
-#define HSDRAMC1_HSR				0x000c
-#define HSDRAMC1_LPR				0x0010
-#define HSDRAMC1_IER				0x0014
-#define HSDRAMC1_IDR				0x0018
-#define HSDRAMC1_IMR				0x001c
-#define HSDRAMC1_ISR				0x0020
-#define HSDRAMC1_MDR				0x0024
-#define HSDRAMC1_VERSION			0x00fc
-
-/* Bitfields in MR */
-#define HSDRAMC1_MODE_OFFSET			0
-#define HSDRAMC1_MODE_SIZE			3
-
-/* Bitfields in TR */
-#define HSDRAMC1_COUNT_OFFSET			0
-#define HSDRAMC1_COUNT_SIZE			12
-
-/* Bitfields in CR */
-#define HSDRAMC1_NC_OFFSET			0
-#define HSDRAMC1_NC_SIZE			2
-#define HSDRAMC1_NR_OFFSET			2
-#define HSDRAMC1_NR_SIZE			2
-#define HSDRAMC1_NB_OFFSET			4
-#define HSDRAMC1_NB_SIZE			1
-#define HSDRAMC1_CAS_OFFSET			5
-#define HSDRAMC1_CAS_SIZE			2
-#define HSDRAMC1_DBW_OFFSET			7
-#define HSDRAMC1_DBW_SIZE			1
-#define HSDRAMC1_TWR_OFFSET			8
-#define HSDRAMC1_TWR_SIZE			4
-#define HSDRAMC1_TRC_OFFSET			12
-#define HSDRAMC1_TRC_SIZE			4
-#define HSDRAMC1_TRP_OFFSET			16
-#define HSDRAMC1_TRP_SIZE			4
-#define HSDRAMC1_TRCD_OFFSET			20
-#define HSDRAMC1_TRCD_SIZE			4
-#define HSDRAMC1_TRAS_OFFSET			24
-#define HSDRAMC1_TRAS_SIZE			4
-#define HSDRAMC1_TXSR_OFFSET			28
-#define HSDRAMC1_TXSR_SIZE			4
-
-/* Bitfields in HSR */
-#define HSDRAMC1_DA_OFFSET			0
-#define HSDRAMC1_DA_SIZE			1
-
-/* Bitfields in LPR */
-#define HSDRAMC1_LPCB_OFFSET			0
-#define HSDRAMC1_LPCB_SIZE			2
-#define HSDRAMC1_PASR_OFFSET			4
-#define HSDRAMC1_PASR_SIZE			3
-#define HSDRAMC1_TCSR_OFFSET			8
-#define HSDRAMC1_TCSR_SIZE			2
-#define HSDRAMC1_DS_OFFSET			10
-#define HSDRAMC1_DS_SIZE			2
-#define HSDRAMC1_TIMEOUT_OFFSET			12
-#define HSDRAMC1_TIMEOUT_SIZE			2
-
-/* Bitfields in IDR */
-#define HSDRAMC1_RES_OFFSET			0
-#define HSDRAMC1_RES_SIZE			1
-
-/* Bitfields in MDR */
-#define HSDRAMC1_MD_OFFSET			0
-#define HSDRAMC1_MD_SIZE			2
-
-/* Bitfields in VERSION */
-#define HSDRAMC1_VERSION_OFFSET			0
-#define HSDRAMC1_VERSION_SIZE			12
-#define HSDRAMC1_MFN_OFFSET			16
-#define HSDRAMC1_MFN_SIZE			3
-
-/* Constants for MODE */
-#define HSDRAMC1_MODE_NORMAL			0
-#define HSDRAMC1_MODE_NOP			1
-#define HSDRAMC1_MODE_BANKS_PRECHARGE		2
-#define HSDRAMC1_MODE_LOAD_MODE			3
-#define HSDRAMC1_MODE_AUTO_REFRESH		4
-#define HSDRAMC1_MODE_EXT_LOAD_MODE		5
-#define HSDRAMC1_MODE_POWER_DOWN		6
-
-/* Constants for NC */
-#define HSDRAMC1_NC_8_COLUMN_BITS		0
-#define HSDRAMC1_NC_9_COLUMN_BITS		1
-#define HSDRAMC1_NC_10_COLUMN_BITS		2
-#define HSDRAMC1_NC_11_COLUMN_BITS		3
-
-/* Constants for NR */
-#define HSDRAMC1_NR_11_ROW_BITS			0
-#define HSDRAMC1_NR_12_ROW_BITS			1
-#define HSDRAMC1_NR_13_ROW_BITS			2
-
-/* Constants for NB */
-#define HSDRAMC1_NB_TWO_BANKS			0
-#define HSDRAMC1_NB_FOUR_BANKS			1
-
-/* Constants for CAS */
-#define HSDRAMC1_CAS_ONE_CYCLE			1
-#define HSDRAMC1_CAS_TWO_CYCLES			2
-
-/* Constants for DBW */
-#define HSDRAMC1_DBW_32_BITS			0
-#define HSDRAMC1_DBW_16_BITS			1
-
-/* Constants for TIMEOUT */
-#define HSDRAMC1_TIMEOUT_AFTER_END		0
-#define HSDRAMC1_TIMEOUT_64_CYC_AFTER_END	1
-#define HSDRAMC1_TIMEOUT_128_CYC_AFTER_END	2
-
-/* Constants for MD */
-#define HSDRAMC1_MD_SDRAM			0
-#define HSDRAMC1_MD_LOW_POWER_SDRAM		1
-
-/* Bit manipulation macros */
-#define HSDRAMC1_BIT(name)					\
-	(1 << HSDRAMC1_##name##_OFFSET)
-#define HSDRAMC1_BF(name,value)					\
-	(((value) & ((1 << HSDRAMC1_##name##_SIZE) - 1))	\
-	 << HSDRAMC1_##name##_OFFSET)
-#define HSDRAMC1_BFEXT(name,value)				\
-	(((value) >> HSDRAMC1_##name##_OFFSET)			\
-	 & ((1 << HSDRAMC1_##name##_SIZE) - 1))
-#define HSDRAMC1_BFINS(name,value,old)				\
-	(((old) & ~(((1 << HSDRAMC1_##name##_SIZE) - 1)		\
-		    << HSDRAMC1_##name##_OFFSET))		\
-	 | HSDRAMC1_BF(name,value))
-
-/* Register access macros */
-#define hsdramc1_readl(reg)					\
-	readl((void *)ATMEL_BASE_HSDRAMC + HSDRAMC1_##reg)
-#define hsdramc1_writel(reg,value)				\
-	writel((value), (void *)ATMEL_BASE_HSDRAMC + HSDRAMC1_##reg)
-
-#endif /* __ASM_AVR32_HSDRAMC1_H__ */

arch/avr32/cpu/hsmc3.h

@@ -1,126 +0,0 @@
-/*
- * Register definitions for Static Memory Controller
- */
-#ifndef __CPU_AT32AP_HSMC3_H__
-#define __CPU_AT32AP_HSMC3_H__
-
-/* HSMC3 register offsets */
-#define HSMC3_SETUP0				0x0000
-#define HSMC3_PULSE0				0x0004
-#define HSMC3_CYCLE0				0x0008
-#define HSMC3_MODE0				0x000c
-#define HSMC3_SETUP1				0x0010
-#define HSMC3_PULSE1				0x0014
-#define HSMC3_CYCLE1				0x0018
-#define HSMC3_MODE1				0x001c
-#define HSMC3_SETUP2				0x0020
-#define HSMC3_PULSE2				0x0024
-#define HSMC3_CYCLE2				0x0028
-#define HSMC3_MODE2				0x002c
-#define HSMC3_SETUP3				0x0030
-#define HSMC3_PULSE3				0x0034
-#define HSMC3_CYCLE3				0x0038
-#define HSMC3_MODE3				0x003c
-#define HSMC3_SETUP4				0x0040
-#define HSMC3_PULSE4				0x0044
-#define HSMC3_CYCLE4				0x0048
-#define HSMC3_MODE4				0x004c
-#define HSMC3_SETUP5				0x0050
-#define HSMC3_PULSE5				0x0054
-#define HSMC3_CYCLE5				0x0058
-#define HSMC3_MODE5				0x005c
-
-/* Bitfields in SETUP0 */
-#define HSMC3_NWE_SETUP_OFFSET			0
-#define HSMC3_NWE_SETUP_SIZE			6
-#define HSMC3_NCS_WR_SETUP_OFFSET		8
-#define HSMC3_NCS_WR_SETUP_SIZE			6
-#define HSMC3_NRD_SETUP_OFFSET			16
-#define HSMC3_NRD_SETUP_SIZE			6
-#define HSMC3_NCS_RD_SETUP_OFFSET		24
-#define HSMC3_NCS_RD_SETUP_SIZE			6
-
-/* Bitfields in PULSE0 */
-#define HSMC3_NWE_PULSE_OFFSET			0
-#define HSMC3_NWE_PULSE_SIZE			7
-#define HSMC3_NCS_WR_PULSE_OFFSET		8
-#define HSMC3_NCS_WR_PULSE_SIZE			7
-#define HSMC3_NRD_PULSE_OFFSET			16
-#define HSMC3_NRD_PULSE_SIZE			7
-#define HSMC3_NCS_RD_PULSE_OFFSET		24
-#define HSMC3_NCS_RD_PULSE_SIZE			7
-
-/* Bitfields in CYCLE0 */
-#define HSMC3_NWE_CYCLE_OFFSET			0
-#define HSMC3_NWE_CYCLE_SIZE			9
-#define HSMC3_NRD_CYCLE_OFFSET			16
-#define HSMC3_NRD_CYCLE_SIZE			9
-
-/* Bitfields in MODE0 */
-#define HSMC3_READ_MODE_OFFSET			0
-#define HSMC3_READ_MODE_SIZE			1
-#define HSMC3_WRITE_MODE_OFFSET			1
-#define HSMC3_WRITE_MODE_SIZE			1
-#define HSMC3_EXNW_MODE_OFFSET			4
-#define HSMC3_EXNW_MODE_SIZE			2
-#define HSMC3_BAT_OFFSET			8
-#define HSMC3_BAT_SIZE				1
-#define HSMC3_DBW_OFFSET			12
-#define HSMC3_DBW_SIZE				2
-#define HSMC3_TDF_CYCLES_OFFSET			16
-#define HSMC3_TDF_CYCLES_SIZE			4
-#define HSMC3_TDF_MODE_OFFSET			20
-#define HSMC3_TDF_MODE_SIZE			1
-#define HSMC3_PMEN_OFFSET			24
-#define HSMC3_PMEN_SIZE				1
-#define HSMC3_PS_OFFSET				28
-#define HSMC3_PS_SIZE				2
-
-/* Bitfields in MODE1 */
-#define HSMC3_PD_OFFSET				28
-#define HSMC3_PD_SIZE				2
-
-/* Constants for READ_MODE */
-#define HSMC3_READ_MODE_NCS_CONTROLLED		0
-#define HSMC3_READ_MODE_NRD_CONTROLLED		1
-
-/* Constants for WRITE_MODE */
-#define HSMC3_WRITE_MODE_NCS_CONTROLLED		0
-#define HSMC3_WRITE_MODE_NWE_CONTROLLED		1
-
-/* Constants for EXNW_MODE */
-#define HSMC3_EXNW_MODE_DISABLED		0
-#define HSMC3_EXNW_MODE_RESERVED		1
-#define HSMC3_EXNW_MODE_FROZEN			2
-#define HSMC3_EXNW_MODE_READY			3
-
-/* Constants for BAT */
-#define HSMC3_BAT_BYTE_SELECT			0
-#define HSMC3_BAT_BYTE_WRITE			1
-
-/* Constants for DBW */
-#define HSMC3_DBW_8_BITS			0
-#define HSMC3_DBW_16_BITS			1
-#define HSMC3_DBW_32_BITS			2
-
-/* Bit manipulation macros */
-#define HSMC3_BIT(name)						\
-	(1 << HSMC3_##name##_OFFSET)
-#define HSMC3_BF(name,value)					\
-	(((value) & ((1 << HSMC3_##name##_SIZE) - 1))		\
-	 << HSMC3_##name##_OFFSET)
-#define HSMC3_BFEXT(name,value)					\
-	(((value) >> HSMC3_##name##_OFFSET)			\
-	 & ((1 << HSMC3_##name##_SIZE) - 1))
-#define HSMC3_BFINS(name,value,old)\
-	(((old) & ~(((1 << HSMC3_##name##_SIZE) - 1)		\
-		    << HSMC3_##name##_OFFSET))			\
-	 | HSMC3_BF(name,value))
-
-/* Register access macros */
-#define hsmc3_readl(reg)					\
-	readl((void *)ATMEL_BASE_HSMC + HSMC3_##reg)
-#define hsmc3_writel(reg,value)					\
-	writel((value), (void *)ATMEL_BASE_HSMC + HSMC3_##reg)
-
-#endif /* __CPU_AT32AP_HSMC3_H__ */

arch/avr32/cpu/interrupts.c

@@ -1,112 +0,0 @@
-/*
- * Copyright (C) 2004-2006 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-#include <div64.h>
-
-#include <linux/errno.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <asm/sysreg.h>
-
-#include <asm/arch/hardware.h>
-
-#define HANDLER_MASK	0x00ffffff
-#define INTLEV_SHIFT	30
-#define INTLEV_MASK	0x00000003
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* Incremented whenever COUNT reaches 0xffffffff by timer_interrupt_handler */
-volatile unsigned long timer_overflow;
-
-/*
- * Instead of dividing by get_tbclk(), multiply by this constant and
- * right-shift the result by 32 bits.
- */
-static unsigned long tb_factor;
-
-unsigned long get_tbclk(void)
-{
-	return gd->arch.cpu_hz;
-}
-
-unsigned long long get_ticks(void)
-{
-	unsigned long lo, hi_now, hi_prev;
-
-	do {
-		hi_prev = timer_overflow;
-		lo = sysreg_read(COUNT);
-		hi_now = timer_overflow;
-	} while (hi_prev != hi_now);
-
-	return ((unsigned long long)hi_now << 32) | lo;
-}
-
-unsigned long get_timer(unsigned long base)
-{
-	u64 now = get_ticks();
-
-	now *= tb_factor;
-	return (unsigned long)(now >> 32) - base;
-}
-
-/*
- * For short delays only. It will overflow after a few seconds.
- */
-void __udelay(unsigned long usec)
-{
-	unsigned long cycles;
-	unsigned long base;
-	unsigned long now;
-
-	base = sysreg_read(COUNT);
-	cycles = ((usec * (get_tbclk() / 10000)) + 50) / 100;
-
-	do {
-		now = sysreg_read(COUNT);
-	} while ((now - base) < cycles);
-}
-
-static int set_interrupt_handler(unsigned int nr, void (*handler)(void),
-				 unsigned int priority)
-{
-	extern void _evba(void);
-	unsigned long intpr;
-	unsigned long handler_addr = (unsigned long)handler;
-
-	handler_addr -= (unsigned long)&_evba;
-
-	if ((handler_addr & HANDLER_MASK) != handler_addr
-	    || (priority & INTLEV_MASK) != priority)
-		return -EINVAL;
-
-	intpr = (handler_addr & HANDLER_MASK);
-	intpr |= (priority & INTLEV_MASK) << INTLEV_SHIFT;
-	writel(intpr, (void *)ATMEL_BASE_INTC + 4 * nr);
-
-	return 0;
-}
-
-int timer_init(void)
-{
-	extern void timer_interrupt_handler(void);
-	u64 tmp;
-
-	sysreg_write(COUNT, 0);
-
-	tmp = (u64)CONFIG_SYS_HZ << 32;
-	tmp += gd->arch.cpu_hz / 2;
-	do_div(tmp, gd->arch.cpu_hz);
-	tb_factor = (u32)tmp;
-
-	if (set_interrupt_handler(0, &timer_interrupt_handler, 3))
-		return -EINVAL;
-
-	/* For all practical purposes, this gives us an overflow interrupt */
-	sysreg_write(COMPARE, 0xffffffff);
-	return 0;
-}

arch/avr32/cpu/mmc.c

@@ -1,16 +0,0 @@
-/*
- * Copyright (C) 2004-2006 Atmel Corporation
- * Copyright (C) 2015 Andreas Bießmann <andreas@biessmann.org>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-#include <atmel_mci.h>
-#include <asm/arch/hardware.h>
-
-/* provide cpu_mmc_init, to overwrite provide board_mmc_init */
-int cpu_mmc_init(bd_t *bd)
-{
-	/* This calls the atmel_mci_init in gen_atmel_mci.c */
-	return atmel_mci_init((void *)ATMEL_BASE_MMCI);
-}

arch/avr32/cpu/portmux-gpio.c

@@ -1,91 +0,0 @@
-/*
- * Copyright (C) 2008 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/gpio.h>
-
-void portmux_select_peripheral(void *port, unsigned long pin_mask,
-		enum portmux_function func, unsigned long flags)
-{
-	/* Both pull-up and pull-down set means buskeeper */
-	if (flags & PORTMUX_PULL_DOWN)
-		gpio_writel(port, PDERS, pin_mask);
-	else
-		gpio_writel(port, PDERC, pin_mask);
-	if (flags & PORTMUX_PULL_UP)
-		gpio_writel(port, PUERS, pin_mask);
-	else
-		gpio_writel(port, PUERC, pin_mask);
-
-	/* Select drive strength */
-	if (flags & PORTMUX_DRIVE_LOW)
-		gpio_writel(port, ODCR0S, pin_mask);
-	else
-		gpio_writel(port, ODCR0C, pin_mask);
-	if (flags & PORTMUX_DRIVE_HIGH)
-		gpio_writel(port, ODCR1S, pin_mask);
-	else
-		gpio_writel(port, ODCR1C, pin_mask);
-
-	/* Select function */
-	if (func & PORTMUX_FUNC_B)
-		gpio_writel(port, PMR0S, pin_mask);
-	else
-		gpio_writel(port, PMR0C, pin_mask);
-	if (func & PORTMUX_FUNC_C)
-		gpio_writel(port, PMR1S, pin_mask);
-	else
-		gpio_writel(port, PMR1C, pin_mask);
-
-	/* Disable GPIO (i.e. enable peripheral) */
-	gpio_writel(port, GPERC, pin_mask);
-}
-
-void portmux_select_gpio(void *port, unsigned long pin_mask,
-		unsigned long flags)
-{
-	/* Both pull-up and pull-down set means buskeeper */
-	if (flags & PORTMUX_PULL_DOWN)
-		gpio_writel(port, PDERS, pin_mask);
-	else
-		gpio_writel(port, PDERC, pin_mask);
-	if (flags & PORTMUX_PULL_UP)
-		gpio_writel(port, PUERS, pin_mask);
-	else
-		gpio_writel(port, PUERC, pin_mask);
-
-	/* Enable open-drain mode if requested */
-	if (flags & PORTMUX_OPEN_DRAIN)
-		gpio_writel(port, ODMERS, pin_mask);
-	else
-		gpio_writel(port, ODMERC, pin_mask);
-
-	/* Select drive strength */
-	if (flags & PORTMUX_DRIVE_LOW)
-		gpio_writel(port, ODCR0S, pin_mask);
-	else
-		gpio_writel(port, ODCR0C, pin_mask);
-	if (flags & PORTMUX_DRIVE_HIGH)
-		gpio_writel(port, ODCR1S, pin_mask);
-	else
-		gpio_writel(port, ODCR1C, pin_mask);
-
-	/* Select direction and initial pin state */
-	if (flags & PORTMUX_DIR_OUTPUT) {
-		if (flags & PORTMUX_INIT_HIGH)
-			gpio_writel(port, OVRS, pin_mask);
-		else
-			gpio_writel(port, OVRC, pin_mask);
-		gpio_writel(port, ODERS, pin_mask);
-	} else {
-		gpio_writel(port, ODERC, pin_mask);
-	}
-
-	/* Enable GPIO */
-	gpio_writel(port, GPERS, pin_mask);
-}

arch/avr32/cpu/portmux-pio.c

@@ -1,76 +0,0 @@
-/*
- * Copyright (C) 2006, 2008 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/gpio.h>
-
-void portmux_select_peripheral(void *port, unsigned long pin_mask,
-		enum portmux_function func, unsigned long flags)
-{
-	if (flags & PORTMUX_PULL_UP)
-		pio_writel(port, PUER, pin_mask);
-	else
-		pio_writel(port, PUDR, pin_mask);
-
-	switch (func) {
-	case PORTMUX_FUNC_A:
-		pio_writel(port, ASR, pin_mask);
-		break;
-	case PORTMUX_FUNC_B:
-		pio_writel(port, BSR, pin_mask);
-		break;
-	}
-
-	pio_writel(port, PDR, pin_mask);
-}
-
-void portmux_select_gpio(void *port, unsigned long pin_mask,
-		unsigned long flags)
-{
-	if (flags & PORTMUX_PULL_UP)
-		pio_writel(port, PUER, pin_mask);
-	else
-		pio_writel(port, PUDR, pin_mask);
-
-	if (flags & PORTMUX_OPEN_DRAIN)
-		pio_writel(port, MDER, pin_mask);
-	else
-		pio_writel(port, MDDR, pin_mask);
-
-	if (flags & PORTMUX_DIR_OUTPUT) {
-		if (flags & PORTMUX_INIT_HIGH)
-			pio_writel(port, SODR, pin_mask);
-		else
-			pio_writel(port, CODR, pin_mask);
-		pio_writel(port, OER, pin_mask);
-	} else {
-		pio_writel(port, ODR, pin_mask);
-	}
-
-	pio_writel(port, PER, pin_mask);
-}
-
-void pio_set_output_value(unsigned int pin, int value)
-{
-	void *port = pio_pin_to_port(pin);
-
-	if (!port)
-		panic("Invalid GPIO pin %u\n", pin);
-
-	__pio_set_output_value(port, pin & 0x1f, value);
-}
-
-int pio_get_input_value(unsigned int pin)
-{
-	void *port = pio_pin_to_port(pin);
-
-	if (!port)
-		panic("Invalid GPIO pin %u\n", pin);
-
-	return __pio_get_input_value(port, pin & 0x1f);
-}

arch/avr32/cpu/start.S

@@ -1,268 +0,0 @@
-/*
- * Copyright (C) 2005-2008 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <asm-offsets.h>
-#include <config.h>
-#include <asm/ptrace.h>
-#include <asm/sysreg.h>
-
-#define SYSREG_MMUCR_I_OFFSET	2
-#define SYSREG_MMUCR_S_OFFSET	4
-
-#define SR_INIT (SYSREG_BIT(GM) | SYSREG_BIT(EM) | SYSREG_BIT(M0))
-/* due to errata (unreliable branch folding) clear FE bit explicitly */
-#define CPUCR_INIT ((SYSREG_BIT(BI) | SYSREG_BIT(BE)	\
-		    | SYSREG_BIT(RE)   |  SYSREG_BIT(IBE)		\
-		    | SYSREG_BIT(IEE)) & ~SYSREG_BIT(FE))
-
-	/*
-	 * To save some space, we use the same entry point for
-	 * exceptions and reset. This avoids lots of alignment padding
-	 * since the reset vector is always suitably aligned.
-	 */
-	.section .exception.text, "ax", @progbits
-	.global	_start
-	.global	_evba
-	.type	_start, @function
-	.type	_evba, @function
-_start:
-	.size	_start, 0
-_evba:
-	.org	0x00
-	rjmp	unknown_exception	/* Unrecoverable exception */
-	.org	0x04
-	rjmp	unknown_exception	/* TLB multiple hit */
-	.org	0x08
-	rjmp	unknown_exception	/* Bus error data fetch */
-	.org	0x0c
-	rjmp	unknown_exception	/* Bus error instruction fetch */
-	.org	0x10
-	rjmp	unknown_exception	/* NMI */
-	.org	0x14
-	rjmp	unknown_exception	/* Instruction address */
-	.org	0x18
-	rjmp	unknown_exception	/* ITLB protection */
-	.org	0x1c
-	rjmp	unknown_exception	/* Breakpoint */
-	.org	0x20
-	rjmp	unknown_exception	/* Illegal opcode */
-	.org	0x24
-	rjmp	unknown_exception	/* Unimplemented instruction */
-	.org	0x28
-	rjmp	unknown_exception	/* Privilege violation */
-	.org	0x2c
-	rjmp	unknown_exception	/* Floating-point */
-	.org	0x30
-	rjmp	unknown_exception	/* Coprocessor absent */
-	.org	0x34
-	rjmp	unknown_exception	/* Data Address (read) */
-	.org	0x38
-	rjmp	unknown_exception	/* Data Address (write) */
-	.org	0x3c
-	rjmp	unknown_exception	/* DTLB Protection (read) */
-	.org	0x40
-	rjmp	unknown_exception	/* DTLB Protection (write) */
-	.org	0x44
-	rjmp	unknown_exception	/* DTLB Modified */
-
-	.org	0x50			/* ITLB Miss */
-	pushm   r8-r12,lr
-	rjmp	1f
-	.org	0x60			/* DTLB Miss (read) */
-	pushm   r8-r12,lr
-	rjmp	1f
-	.org	0x70			/* DTLB Miss (write) */
-	pushm   r8-r12,lr
-1:	mov	r12, sp
-	rcall	mmu_handle_tlb_miss
-	popm	r8-r12,lr
-	brne	unknown_exception
-	rete
-
-	.size	_evba, . - _evba
-
-	.align	2
-	.type	unknown_exception, @function
-unknown_exception:
-	/* Figure out whether we're handling an exception (Exception
-	 * mode) or just booting (Supervisor mode). */
-	csrfcz	SYSREG_M1_OFFSET
-	brcc	at32ap_cpu_bootstrap
-
-	/* This is an exception. Complain. */
-	pushm	r0-r12
-	sub	r8, sp, REG_R12 - REG_R0 - 4
-	mov	r9, lr
-	mfsr	r10, SYSREG_RAR_EX
-	mfsr	r11, SYSREG_RSR_EX
-	pushm	r8-r11
-	mfsr	r12, SYSREG_ECR
-	mov	r11, sp
-	rcall	do_unknown_exception
-1:	rjmp	1b
-
-	/* The COUNT/COMPARE timer interrupt handler */
-	.global	timer_interrupt_handler
-	.type	timer_interrupt_handler,@function
-	.align	2
-timer_interrupt_handler:
-	/*
-	 * Increment timer_overflow and re-write COMPARE with 0xffffffff.
-	 *
-	 * We're running at interrupt level 3, so we don't need to save
-	 * r8-r12 or lr to the stack.
-	 */
-	lda.w	r8, timer_overflow
-	ld.w	r9, r8[0]
-	mov	r10, -1
-	mtsr	SYSREG_COMPARE, r10
-	sub	r9, -1
-	st.w	r8[0], r9
-	rete
-
-	/*
-	 * CPU bootstrap after reset is handled here. SoC code may
-	 * override this in case they need to initialize oscillators,
-	 * etc.
-	 */
-	.section .text.at32ap_cpu_bootstrap, "ax", @progbits
-	.global	at32ap_cpu_bootstrap
-	.weak	at32ap_cpu_bootstrap
-	.type	at32ap_cpu_bootstrap, @function
-	.align	2
-at32ap_cpu_bootstrap:
-	/* Reset the Status Register */
-	mov	r0, lo(SR_INIT)
-	orh	r0, hi(SR_INIT)
-	mtsr	SYSREG_SR, r0
-
-	/* Reset CPUCR and invalidate the BTB */
-	mov	r2, CPUCR_INIT
-	mtsr	SYSREG_CPUCR, r2
-
-	/* Flush the caches */
-	mov	r1, 0
-	cache	r1[4], 8
-	cache	r1[0], 0
-	sync	0
-
-	/* Reset the MMU to default settings */
-	mov	r0, SYSREG_BIT(MMUCR_S) | SYSREG_BIT(MMUCR_I)
-	mtsr	SYSREG_MMUCR, r0
-
-	/* Internal RAM should not need any initialization.  We might
-	   have to initialize external RAM here if the part doesn't
-	   have internal RAM (or we may use the data cache) */
-
-	/* Jump to cacheable segment */
-	lddpc	pc, 1f
-
-	.align	2
-1:	.long	at32ap_low_level_init
-	.size	_start, . - _start
-
-	/* Common CPU bootstrap code after oscillator/cache/etc. init */
-	.section .text.avr32ap_low_level_init, "ax", @progbits
-	.global	at32ap_low_level_init
-	.type	at32ap_low_level_init, @function
-	.align	2
-at32ap_low_level_init:
-	lddpc	sp, sp_init
-
-	/* Initialize the GOT pointer */
-	lddpc	r6, got_init
-3:	rsub	r6, pc
-
-	/* Let's go */
-	rjmp	board_init_f
-
-	.align	2
-	.type	sp_init,@object
-sp_init:
-	.long	CONFIG_SYS_INIT_SP_ADDR
-got_init:
-	.long	3b - _GLOBAL_OFFSET_TABLE_
-
-	/*
-	 * void	relocate_code(new_sp, new_gd, monitor_addr)
-	 *
-	 * Relocate the u-boot image into RAM and continue from there.
-	 * Does not return.
-	 */
-	.section .text.relocate_code,"ax",@progbits
-	.global	relocate_code
-	.type	relocate_code,@function
-relocate_code:
-	mov	sp, r12		/* use new stack */
-	mov	r12, r11	/* save new_gd */
-	mov	r11, r10	/* save destination address */
-
-	/* copy .text section and flush the cache along the way */
-	lda.w	r8, _text
-	lda.w	r9, _etext
-	sub	lr, r10, r8	/* relocation offset */
-
-1:	ldm	r8++, r0-r3
-	stm	r10, r0-r3
-	sub	r10, -16
-	ldm	r8++, r0-r3
-	stm	r10, r0-r3
-	sub	r10, -16
-	cp.w	r8, r9
-	cache	r10[-4], 0x0d	/* dcache clean/invalidate */
-	cache	r10[-4], 0x01	/* icache invalidate */
-	brlt	1b
-
-	/* flush write buffer */
-	sync	0
-
-	/* copy data sections */
-	lda.w	r9, _edata
-1:	ld.d	r0, r8++
-	st.d	r10++, r0
-	cp.w	r8, r9
-	brlt	1b
-
-	/* zero out .bss */
-	mov	r0, 0
-	mov	r1, 0
-	lda.w	r9, __bss_end
-	sub	r9, r8
-1:	st.d	r10++, r0
-	sub	r9, 8
-	brgt	1b
-
-	/* jump to RAM */
-	sub	r0, pc, . - in_ram
-	add	pc, r0, lr
-
-	.align	2
-in_ram:
-	/* find the new GOT and relocate it */
-	lddpc	r6, got_init_reloc
-3:	rsub	r6, pc
-	mov	r8, r6
-	lda.w	r9, _egot
-	lda.w	r10, _got
-	sub	r9, r10
-1:	ld.w	r0, r8[0]
-	add	r0, lr
-	st.w	r8++, r0
-	sub	r9, 4
-	brgt	1b
-
-	/* Move the exception handlers */
-	mfsr	r2, SYSREG_EVBA
-	add	r2, lr
-	mtsr	SYSREG_EVBA, r2
-
-	/* Do the rest of the initialization sequence */
-	call	board_init_r
-
-	.align	2
-got_init_reloc:
-	.long	3b - _GLOBAL_OFFSET_TABLE_
-
-	.size	relocate_code, . - relocate_code