Prepare v2017.11-rc3

Signed-off-by: Tom Rini <trini@konsulko.com>

Kconfig

@@ -14,6 +14,12 @@ source "arch/Kconfig"
 
 menu "General setup"
 
+config BROKEN
+	bool
+	help
+	  This option cannot be enabled. It is used as dependency
+	  for broken and incomplete features.
+
 config LOCALVERSION
 	string "Local version - append to U-Boot release"
 	help
@@ -158,6 +164,15 @@ config PHYS_64BIT
 	  This can be used not only for 64bit SoCs, but also for
 	  large physical address extention on 32bit SoCs.
 
+config BUILD_ROM
+	bool "Build U-Boot as BIOS replacement"
+	depends on X86
+	help
+	  This option allows to build a ROM version of U-Boot.
+	  The build process generally requires several binary blobs
+	  which are not shipped in the U-Boot source tree.
+	  Please, see doc/README.x86 for details.
+
 endmenu		# General setup
 
 menu "Boot images"

Makefile

@@ -5,7 +5,7 @@
 VERSION = 2017
 PATCHLEVEL = 11
 SUBLEVEL =
-EXTRAVERSION = -rc2
+EXTRAVERSION = -rc3
 NAME =
 
 # *DOCUMENTATION*
@@ -796,7 +796,7 @@ ALL-$(CONFIG_REMAKE_ELF) += u-boot.elf
 ALL-$(CONFIG_EFI_APP) += u-boot-app.efi
 ALL-$(CONFIG_EFI_STUB) += u-boot-payload.efi
 
-ifneq ($(BUILD_ROM),)
+ifneq ($(BUILD_ROM)$(CONFIG_BUILD_ROM),)
 ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom
 endif
 

README

@@ -1028,21 +1028,6 @@ The following options need to be configured:
 			control registers. This behavior won't affect the
 			correctnessof 10/100 link speed update.
 
-		CONFIG_SMC911X
-		Support for SMSC's LAN911x and LAN921x chips
-
-			CONFIG_SMC911X_BASE
-			Define this to hold the physical address
-			of the device (I/O space)
-
-			CONFIG_SMC911X_32_BIT
-			Define this if data bus is 32 bits
-
-			CONFIG_SMC911X_16_BIT
-			Define this if data bus is 16 bits. If your processor
-			automatically converts one 32 bit word to two 16 bit
-			words you may also try CONFIG_SMC911X_32_BIT.
-
 		CONFIG_SH_ETHER
 		Support for Renesas on-chip Ethernet controller
 

arch/arm/Kconfig

@@ -698,6 +698,7 @@ config ARCH_SUNXI
 	select SPL_SYS_MALLOC_SIMPLE if SPL
 	select SYS_NS16550
 	select SPL_SYS_THUMB_BUILD if !ARM64
+	select SYS_THUMB_BUILD if !ARM64
 	select USB if DISTRO_DEFAULTS
 	select USB_STORAGE if DISTRO_DEFAULTS
 	select USB_KEYBOARD if DISTRO_DEFAULTS

arch/arm/cpu/armv8/fsl-layerscape/Kconfig

@@ -490,3 +490,10 @@ config SYS_MC_RSV_MEM_ALIGN
 
 config SPL_LDSCRIPT
 	default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
+
+config HAS_FSL_XHCI_USB
+	bool
+	default y if ARCH_LS1043A || ARCH_LS1046A
+	help
+	  For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
+	  pins, select it when the pins are assigned to USB.

arch/arm/cpu/armv8/fsl-layerscape/ppa.c

@@ -35,6 +35,7 @@ int ppa_init(void)
 	unsigned int el = current_el();
 	void *ppa_fit_addr;
 	u32 *boot_loc_ptr_l, *boot_loc_ptr_h;
+	u32 *loadable_l, *loadable_h;
 	int ret;
 
 #ifdef CONFIG_CHAIN_OF_TRUST
@@ -240,9 +241,9 @@ int ppa_init(void)
 					   PPA_KEY_HASH,
 					   &ppa_img_addr);
 		if (ret != 0)
-			printf("PPA validation failed\n");
+			printf("SEC firmware(s) validation failed\n");
 		else
-			printf("PPA validation Successful\n");
+			printf("SEC firmware(s) validation Successful\n");
 	}
 #if defined(CONFIG_SYS_LS_PPA_FW_IN_MMC) || \
 	defined(CONFIG_SYS_LS_PPA_FW_IN_NAND)
@@ -254,15 +255,24 @@ int ppa_init(void)
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	boot_loc_ptr_l = &gur->bootlocptrl;
 	boot_loc_ptr_h = &gur->bootlocptrh;
+
+	/* Assign addresses to loadable ptrs */
+	loadable_l = &gur->scratchrw[4];
+	loadable_h = &gur->scratchrw[5];
 #elif defined(CONFIG_FSL_LSCH2)
 	struct ccsr_scfg __iomem *scfg = (void *)(CONFIG_SYS_FSL_SCFG_ADDR);
 	boot_loc_ptr_l = &scfg->scratchrw[1];
 	boot_loc_ptr_h = &scfg->scratchrw[0];
+
+	/* Assign addresses to loadable ptrs */
+	loadable_l = &scfg->scratchrw[2];
+	loadable_h = &scfg->scratchrw[3];
 #endif
 
 	debug("fsl-ppa: boot_loc_ptr_l = 0x%p, boot_loc_ptr_h =0x%p\n",
 	      boot_loc_ptr_l, boot_loc_ptr_h);
-	ret = sec_firmware_init(ppa_fit_addr, boot_loc_ptr_l, boot_loc_ptr_h);
+	ret = sec_firmware_init(ppa_fit_addr, boot_loc_ptr_l, boot_loc_ptr_h,
+				loadable_l, loadable_h);
 
 #if defined(CONFIG_SYS_LS_PPA_FW_IN_MMC) || \
 	defined(CONFIG_SYS_LS_PPA_FW_IN_NAND)

arch/arm/cpu/armv8/sec_firmware.c

@@ -105,6 +105,74 @@ static int sec_firmware_parse_image(const void *sec_firmware_img,
 	return 0;
 }
 
+/*
+ * SEC Firmware FIT image parser to check if any loadable is
+ * present. If present, verify integrity of the loadable and
+ * copy loadable to address provided in (loadable_h, loadable_l).
+ *
+ * Returns 0 on success and a negative errno on error task fail.
+ */
+static int sec_firmware_check_copy_loadable(const void *sec_firmware_img,
+					    u32 *loadable_l, u32 *loadable_h)
+{
+	phys_addr_t sec_firmware_loadable_addr = 0;
+	int conf_node_off, ld_node_off;
+	char *conf_node_name = NULL;
+	const void *data;
+	size_t size;
+	ulong load;
+
+	conf_node_name = SEC_FIRMEWARE_FIT_CNF_NAME;
+
+	conf_node_off = fit_conf_get_node(sec_firmware_img, conf_node_name);
+	if (conf_node_off < 0) {
+		printf("SEC Firmware: %s: no such config\n", conf_node_name);
+	return -ENOENT;
+	}
+
+	ld_node_off = fit_conf_get_prop_node(sec_firmware_img, conf_node_off,
+					     FIT_LOADABLE_PROP);
+	if (ld_node_off >= 0) {
+		printf("SEC Firmware: '%s' present in config\n",
+		       FIT_LOADABLE_PROP);
+
+		/* Verify secure firmware image */
+		if (!(fit_image_verify(sec_firmware_img, ld_node_off))) {
+			printf("SEC Loadable: Bad loadable image (bad CRC)\n");
+			return -EINVAL;
+		}
+
+		if (fit_image_get_data(sec_firmware_img, ld_node_off,
+				       &data, &size)) {
+			printf("SEC Loadable: Can't get subimage data/size");
+			return -ENOENT;
+		}
+
+		/* Get load address, treated as load offset to secure memory */
+		if (fit_image_get_load(sec_firmware_img, ld_node_off, &load)) {
+			printf("SEC Loadable: Can't get subimage load");
+			return -ENOENT;
+		}
+
+		/* Compute load address for loadable in secure memory */
+		sec_firmware_loadable_addr = (sec_firmware_addr -
+						gd->arch.tlb_size) + load;
+
+		/* Copy loadable to secure memory and flush dcache */
+		debug("%s copied to address 0x%p\n",
+		      FIT_LOADABLE_PROP, (void *)sec_firmware_loadable_addr);
+		memcpy((void *)sec_firmware_loadable_addr, data, size);
+		flush_dcache_range(sec_firmware_loadable_addr,
+				   sec_firmware_loadable_addr + size);
+	}
+
+	/* Populate address ptrs for loadable image with loadbale addr */
+	out_le32(loadable_l, (sec_firmware_loadable_addr & WORD_MASK));
+	out_le32(loadable_h, (sec_firmware_loadable_addr >> WORD_SHIFT));
+
+	return 0;
+}
+
 static int sec_firmware_copy_image(const char *title,
 			 u64 image_addr, u32 image_size, u64 sec_firmware)
 {
@@ -117,9 +185,11 @@ static int sec_firmware_copy_image(const char *title,
 
 /*
  * This function will parse the SEC Firmware image, and then load it
- * to secure memory.
+ * to secure memory. Also load any loadable if present along with SEC
+ * Firmware image.
  */
-static int sec_firmware_load_image(const void *sec_firmware_img)
+static int sec_firmware_load_image(const void *sec_firmware_img,
+				   u32 *loadable_l, u32 *loadable_h)
 {
 	const void *raw_image_addr;
 	size_t raw_image_size = 0;
@@ -172,6 +242,15 @@ static int sec_firmware_load_image(const void *sec_firmware_img)
 	if (ret)
 		goto out;
 
+	/*
+	 * Check if any loadable are present along with firmware image, if
+	 * present load them.
+	 */
+	ret = sec_firmware_check_copy_loadable(sec_firmware_img, loadable_l,
+					       loadable_h);
+	if (ret)
+		goto out;
+
 	sec_firmware_addr |= SEC_FIRMWARE_LOADED;
 	debug("SEC Firmware: Entry point: 0x%llx\n",
 	      sec_firmware_addr & SEC_FIRMWARE_ADDR_MASK);
@@ -289,17 +368,22 @@ int sec_firmware_get_random(uint8_t *rand, int bytes)
  * @sec_firmware_img:	the SEC Firmware image address
  * @eret_hold_l:	the address to hold exception return address low
  * @eret_hold_h:	the address to hold exception return address high
+ * @loadable_l:		the address to hold loadable address low
+ * @loadable_h:		the address to hold loadable address high
  */
 int sec_firmware_init(const void *sec_firmware_img,
 			u32 *eret_hold_l,
-			u32 *eret_hold_h)
+			u32 *eret_hold_h,
+			u32 *loadable_l,
+			u32 *loadable_h)
 {
 	int ret;
 
 	if (!sec_firmware_is_valid(sec_firmware_img))
 		return -EINVAL;
 
-	ret = sec_firmware_load_image(sec_firmware_img);
+	ret = sec_firmware_load_image(sec_firmware_img, loadable_l,
+				      loadable_h);
 	if (ret) {
 		printf("SEC Firmware: Failed to load image\n");
 		return ret;

arch/arm/dts/Makefile

@@ -309,6 +309,7 @@ dtb-$(CONFIG_MACH_SUN8I_A33) += \
 	sun8i-a33-olinuxino.dtb \
 	sun8i-a33-q8-tablet.dtb \
 	sun8i-a33-sinlinx-sina33.dtb \
+	sun8i-r16-bananapi-m2m.dtb \
 	sun8i-r16-nintendo-nes-classic-edition.dtb \
 	sun8i-r16-parrot.dtb
 dtb-$(CONFIG_MACH_SUN8I_A83T) += \

arch/arm/dts/fsl-ls1088a.dtsi

@@ -76,6 +76,20 @@
 		num-cs = <4>;
 	};
 
+	usb0: usb3@3100000 {
+		compatible = "fsl,layerscape-dwc3";
+		reg = <0x0 0x3100000 0x0 0x10000>;
+		interrupts = <0 80 0x4>; /* Level high type */
+		dr_mode = "host";
+	};
+
+	usb1: usb3@3110000 {
+		compatible = "fsl,layerscape-dwc3";
+		reg = <0x0 0x3110000 0x0 0x10000>;
+		interrupts = <0 81 0x4>; /* Level high type */
+		dr_mode = "host";
+	};
+
 	pcie@3400000 {
 		compatible = "fsl,ls-pcie", "snps,dw-pcie";
 		reg = <0x00 0x03400000 0x0 0x80000   /* dbi registers */

arch/arm/dts/sun8i-r16-bananapi-m2m.dts

@@ -0,0 +1,321 @@
+/*
+ * Copyright (c) 2017 Free Electrons <maxime.ripard@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-a33.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "BananaPi M2 Magic";
+	compatible = "sinovoip,bananapi-m2m", "allwinner,sun8i-a33";
+
+	aliases {
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		i2c2 = &i2c2;
+		serial0 = &uart0;
+		serial1 = &uart1;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		blue {
+			label = "bpi-m2m:blue:usr";
+			gpios = <&pio 2 7 GPIO_ACTIVE_LOW>;
+		};
+
+		green {
+			label = "bpi-m2m:green:usr";
+			gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>;
+		};
+
+		red {
+			label = "bpi-m2m:red:power";
+			gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
+			default-state = "on";
+		};
+	};
+
+	reg_vcc5v0: vcc5v0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	wifi_pwrseq: wifi_pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL06 */
+	};
+};
+
+&codec {
+	status = "okay";
+};
+
+&cpu0 {
+	cpu-supply = <&reg_dcdc3>;
+};
+
+&cpu0_opp_table {
+	opp@1104000000 {
+		opp-hz = /bits/ 64 <1104000000>;
+		opp-microvolt = <1320000>;
+		clock-latency-ns = <244144>; /* 8 32k periods */
+	};
+
+	opp@1200000000 {
+		opp-hz = /bits/ 64 <1200000000>;
+		opp-microvolt = <1320000>;
+		clock-latency-ns = <244144>; /* 8 32k periods */
+	};
+};
+
+&dai {
+	status = "okay";
+};
+
+&ehci0 {
+	status = "okay";
+};
+
+/* This is the i2c bus exposed on the DSI connector for the touch panel */
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0_pins_a>;
+	status = "disabled";
+};
+
+/* This is the i2c bus exposed on the GPIO header */
+&i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1_pins_a>;
+	status = "disabled";
+};
+
+/* This is the i2c bus exposed on the CSI connector to control the sensor */
+&i2c2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c2_pins_a>;
+	status = "disabled";
+};
+
+&mmc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins_a>;
+	vmmc-supply = <&reg_dcdc1>;
+	bus-width = <4>;
+	cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
+	cd-inverted;
+	status = "okay";
+};
+
+&mmc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc1_pins_a>;
+	vmmc-supply = <&reg_aldo1>;
+	mmc-pwrseq = <&wifi_pwrseq>;
+	bus-width = <4>;
+	non-removable;
+	status = "okay";
+};
+
+&mmc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc2_8bit_pins>;
+	vmmc-supply = <&reg_dcdc1>;
+	bus-width = <8>;
+	non-removable;
+	cap-mmc-hw-reset;
+	status = "okay";
+};
+
+&ohci0 {
+	status = "okay";
+};
+
+&r_rsb {
+	status = "okay";
+
+	axp22x: pmic@3a3 {
+		compatible = "x-powers,axp223";
+		reg = <0x3a3>;
+		interrupt-parent = <&nmi_intc>;
+		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+		eldoin-supply = <&reg_dcdc1>;
+		x-powers,drive-vbus-en;
+	};
+};
+
+#include "axp223.dtsi"
+
+&ac_power_supply {
+	status = "okay";
+};
+
+&reg_aldo1 {
+	regulator-always-on;
+	regulator-min-microvolt = <3000000>;
+	regulator-max-microvolt = <3000000>;
+	regulator-name = "vcc-io";
+};
+
+&reg_aldo2 {
+	regulator-always-on;
+	regulator-min-microvolt = <2500000>;
+	regulator-max-microvolt = <2500000>;
+	regulator-name = "vdd-dll";
+};
+
+&reg_aldo3 {
+	regulator-always-on;
+	regulator-min-microvolt = <3000000>;
+	regulator-max-microvolt = <3000000>;
+	regulator-name = "avcc";
+};
+
+&reg_dc1sw {
+	regulator-name = "vcc-lcd";
+};
+
+&reg_dc5ldo {
+	regulator-always-on;
+	regulator-min-microvolt = <900000>;
+	regulator-max-microvolt = <1400000>;
+	regulator-name = "vdd-cpus";
+};
+
+&reg_dcdc1 {
+	regulator-always-on;
+	regulator-min-microvolt = <3000000>;
+	regulator-max-microvolt = <3000000>;
+	regulator-name = "vcc-3v0";
+};
+
+&reg_dcdc2 {
+	regulator-always-on;
+	regulator-min-microvolt = <900000>;
+	regulator-max-microvolt = <1400000>;
+	regulator-name = "vdd-sys";
+};
+
+&reg_dcdc3 {
+	regulator-always-on;
+	regulator-min-microvolt = <900000>;
+	regulator-max-microvolt = <1400000>;
+	regulator-name = "vdd-cpu";
+};
+
+&reg_dcdc5 {
+	regulator-always-on;
+	regulator-min-microvolt = <1500000>;
+	regulator-max-microvolt = <1500000>;
+	regulator-name = "vcc-dram";
+};
+
+/*
+ * Our WiFi chip needs both DLDO1 and DLDO2 to be powered at the same
+ * time, with the two being in sync. Since this is not really
+ * supported right now, just use the two as always on, and we will fix
+ * it later.
+ */
+&reg_dldo1 {
+	regulator-always-on;
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-wifi0";
+};
+
+&reg_dldo2 {
+	regulator-always-on;
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-wifi1";
+};
+
+&reg_drivevbus {
+	regulator-name = "usb0-vbus";
+	status = "okay";
+};
+
+&reg_rtc_ldo {
+	regulator-name = "vcc-rtc";
+};
+
+&sound {
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins_b>;
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1_pins_a>, <&uart1_pins_cts_rts_a>;
+	status = "okay";
+};
+
+&usb_otg {
+	dr_mode = "otg";
+	status = "okay";
+};
+
+&usb_power_supply {
+	status = "okay";
+};
+
+&usbphy {
+	usb0_id_det-gpios = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */
+	usb0_vbus_power-supply = <&usb_power_supply>;
+	usb0_vbus-supply = <&reg_drivevbus>;
+	usb1_vbus-supply = <&reg_vcc5v0>;
+	status = "okay";
+};

arch/arm/dts/sunxi-u-boot.dtsi

@@ -1,5 +1,14 @@
 #include <config.h>
 
+/*
+ * This is the maximum size the U-Boot binary can be, which is basically
+ * the start of the environment, minus the start of the U-Boot binary in
+ * the MMC. This makes the assumption that the MMC is using 512-bytes
+ * blocks, but devices using something other than that remains to be
+ * seen.
+ */
+#define UBOOT_MMC_MAX_SIZE	(CONFIG_ENV_OFFSET - (CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512))
+
 / {
 	binman {
 		filename = "u-boot-sunxi-with-spl.bin";
@@ -8,6 +17,9 @@
 			filename = "spl/sunxi-spl.bin";
 		};
 		u-boot-img {
+#ifdef CONFIG_MMC
+			size = <UBOOT_MMC_MAX_SIZE>;
+#endif
 			pos = <CONFIG_SPL_PAD_TO>;
 		};
 	};

arch/arm/dts/uniphier-ld11.dtsi

@@ -175,6 +175,19 @@
 						  "gpio_range4",
 						  "gpio_range5";
 			ngpios = <200>;
+			socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
+						     <21 217 3>;
+		};
+
+		adamv@57920000 {
+			compatible = "socionext,uniphier-ld11-adamv",
+				     "simple-mfd", "syscon";
+			reg = <0x57920000 0x1000>;
+
+			adamv_rst: reset {
+				compatible = "socionext,uniphier-ld11-adamv-reset";
+				#reset-cells = <1>;
+			};
 		};
 
 		i2c0: i2c@58780000 {

arch/arm/dts/uniphier-ld20.dtsi

@@ -223,6 +223,36 @@
 			clock-frequency = <58820000>;
 		};
 
+		gpio: gpio@55000000 {
+			compatible = "socionext,uniphier-gpio";
+			reg = <0x55000000 0x200>;
+			interrupt-parent = <&aidet>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pinctrl 0 0 0>,
+				      <&pinctrl 96 0 0>,
+				      <&pinctrl 160 0 0>;
+			gpio-ranges-group-names = "gpio_range0",
+						  "gpio_range1",
+						  "gpio_range2";
+			ngpios = <205>;
+			socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
+						     <21 217 3>;
+		};
+
+		adamv@57920000 {
+			compatible = "socionext,uniphier-ld20-adamv",
+				     "simple-mfd", "syscon";
+			reg = <0x57920000 0x1000>;
+
+			adamv_rst: reset {
+				compatible = "socionext,uniphier-ld20-adamv-reset";
+				#reset-cells = <1>;
+			};
+		};
+
 		i2c0: i2c@58780000 {
 			compatible = "socionext,uniphier-fi2c";
 			status = "disabled";

arch/arm/dts/uniphier-ld4-ref.dts

@@ -69,11 +69,6 @@
 	status = "okay";
 };
 
-/* for U-Boot only */
-&serial0 {
-	u-boot,dm-pre-reloc;
-};
-
-&pinctrl_uart0 {
-	u-boot,dm-pre-reloc;
+&nand {
+	status = "okay";
 };

arch/arm/dts/uniphier-ld4.dtsi

@@ -50,7 +50,6 @@
 		#size-cells = <1>;
 		ranges;
 		interrupt-parent = <&intc>;
-		u-boot,dm-pre-reloc;
 
 		l2: l2-cache@500c0000 {
 			compatible = "socionext,uniphier-system-cache";
@@ -295,11 +294,9 @@
 			compatible = "socionext,uniphier-ld4-soc-glue",
 				     "simple-mfd", "syscon";
 			reg = <0x5f800000 0x2000>;
-			u-boot,dm-pre-reloc;
 
 			pinctrl: pinctrl {
 				compatible = "socionext,uniphier-ld4-pinctrl";
-				u-boot,dm-pre-reloc;
 			};
 		};
 

arch/arm/dts/uniphier-ld6b-ref.dts

@@ -71,11 +71,6 @@
 	status = "okay";
 };
 
-/* for U-Boot only */
-&serial0 {
-	u-boot,dm-pre-reloc;
-};
-
-&pinctrl_uart0 {
-	u-boot,dm-pre-reloc;
+&nand {
+	status = "okay";
 };

arch/arm/dts/uniphier-pinctrl.dtsi

@@ -23,6 +23,21 @@
 		function = "emmc";
 	};
 
+	pinctrl_ether_mii: ether_mii_grp {
+		groups = "ether_mii";
+		function = "ether_mii";
+	};
+
+	pinctrl_ether_rgmii: ether_rgmii_grp {
+		groups = "ether_rgmii";
+		function = "ether_rgmii";
+	};
+
+	pinctrl_ether_rmii: ether_rmii_grp {
+		groups = "ether_rmii";
+		function = "ether_rmii";
+	};
+
 	pinctrl_i2c0: i2c0_grp {
 		groups = "i2c0";
 		function = "i2c0";

arch/arm/dts/uniphier-pro4-ace.dts

@@ -90,12 +90,3 @@
 &usb3 {
 	status = "okay";
 };
-
-/* for U-Boot only */
-&serial0 {
-	u-boot,dm-pre-reloc;
-};
-
-&pinctrl_uart0 {
-	u-boot,dm-pre-reloc;
-};

arch/arm/dts/uniphier-pro4-ref.dts

@@ -83,12 +83,3 @@
 &usb1 {
 	status = "okay";
 };
-
-/* for U-Boot only */
-&serial0 {
-	u-boot,dm-pre-reloc;
-};
-
-&pinctrl_uart0 {
-	u-boot,dm-pre-reloc;
-};

arch/arm/dts/uniphier-pro4-sanji.dts

@@ -85,24 +85,3 @@
 &usb3 {
 	status = "okay";
 };
-
-/* for U-Boot only */
-&serial0 {
-	u-boot,dm-pre-reloc;
-};
-
-&mio_clk {
-	u-boot,dm-pre-reloc;
-};
-
-&emmc {
-	u-boot,dm-pre-reloc;
-};
-
-&pinctrl_uart0 {
-	u-boot,dm-pre-reloc;
-};
-
-&pinctrl_emmc {
-	u-boot,dm-pre-reloc;
-};

arch/arm/dts/uniphier-pro4.dtsi

@@ -58,7 +58,6 @@
 		#size-cells = <1>;
 		ranges;
 		interrupt-parent = <&intc>;
-		u-boot,dm-pre-reloc;
 
 		l2: l2-cache@500c0000 {
 			compatible = "socionext,uniphier-system-cache";
@@ -224,7 +223,6 @@
 			compatible = "socionext,uniphier-pro4-mioctrl",
 				     "simple-mfd", "syscon";
 			reg = <0x59810000 0x800>;
-			u-boot,dm-pre-reloc;
 
 			mio_clk: clock {
 				compatible = "socionext,uniphier-pro4-mio-clock";
@@ -333,11 +331,9 @@
 			compatible = "socionext,uniphier-pro4-soc-glue",
 				     "simple-mfd", "syscon";
 			reg = <0x5f800000 0x2000>;
-			u-boot,dm-pre-reloc;
 
 			pinctrl: pinctrl {
 				compatible = "socionext,uniphier-pro4-pinctrl";
-				u-boot,dm-pre-reloc;
 			};
 		};
 

arch/arm/dts/uniphier-pro5-4kbox.dts

@@ -55,12 +55,3 @@
 &sd {
 	status = "okay";
 };
-
-/* for U-Boot only */
-&serial1 {
-	u-boot,dm-pre-reloc;
-};
-
-&pinctrl_uart1 {
-	u-boot,dm-pre-reloc;
-};

arch/arm/dts/uniphier-pro5.dtsi

@@ -132,7 +132,6 @@
 		#size-cells = <1>;
 		ranges;
 		interrupt-parent = <&intc>;
-		u-boot,dm-pre-reloc;
 
 		l2: l2-cache@500c0000 {
 			compatible = "socionext,uniphier-system-cache";
@@ -311,7 +310,6 @@
 			compatible = "socionext,uniphier-pro5-sdctrl",
 				     "simple-mfd", "syscon";
 			reg = <0x59810000 0x400>;
-			u-boot,dm-pre-reloc;
 
 			sd_clk: clock {
 				compatible = "socionext,uniphier-pro5-sd-clock";
@@ -344,11 +342,9 @@
 			compatible = "socionext,uniphier-pro5-soc-glue",
 				     "simple-mfd", "syscon";
 			reg = <0x5f800000 0x2000>;
-			u-boot,dm-pre-reloc;
 
 			pinctrl: pinctrl {
 				compatible = "socionext,uniphier-pro5-pinctrl";
-				u-boot,dm-pre-reloc;
 			};
 		};
 

arch/arm/dts/uniphier-pxs2-gentil.dts

@@ -66,24 +66,3 @@
 &usb1 {
 	status = "okay";
 };
-
-/* for U-Boot only */
-&serial2 {
-	u-boot,dm-pre-reloc;
-};
-
-&sd_clk {
-	u-boot,dm-pre-reloc;
-};
-
-&emmc {
-	u-boot,dm-pre-reloc;
-};
-
-&pinctrl_uart2 {
-	u-boot,dm-pre-reloc;
-};
-
-&pinctrl_emmc {
-	u-boot,dm-pre-reloc;
-};

arch/arm/dts/uniphier-pxs2-vodka.dts

@@ -49,24 +49,3 @@
 &usb0 {
 	status = "okay";
 };
-
-/* for U-Boot only */
-&serial2 {
-	u-boot,dm-pre-reloc;
-};
-
-&sd_clk {
-	u-boot,dm-pre-reloc;
-};
-
-&emmc {
-	u-boot,dm-pre-reloc;
-};
-
-&pinctrl_uart2 {
-	u-boot,dm-pre-reloc;
-};
-
-&pinctrl_emmc {
-	u-boot,dm-pre-reloc;
-};

arch/arm/dts/uniphier-pxs2.dtsi

@@ -120,7 +120,6 @@
 		#size-cells = <1>;
 		ranges;
 		interrupt-parent = <&intc>;
-		u-boot,dm-pre-reloc;
 
 		l2: l2-cache@500c0000 {
 			compatible = "socionext,uniphier-system-cache";
@@ -297,7 +296,6 @@
 			compatible = "socionext,uniphier-pxs2-sdctrl",
 				     "simple-mfd", "syscon";
 			reg = <0x59810000 0x400>;
-			u-boot,dm-pre-reloc;
 
 			sd_clk: clock {
 				compatible = "socionext,uniphier-pxs2-sd-clock";
@@ -365,11 +363,9 @@
 			compatible = "socionext,uniphier-pxs2-soc-glue",
 				     "simple-mfd", "syscon";
 			reg = <0x5f800000 0x2000>;
-			u-boot,dm-pre-reloc;
 
 			pinctrl: pinctrl {
 				compatible = "socionext,uniphier-pxs2-pinctrl";
-				u-boot,dm-pre-reloc;
 			};
 		};
 

arch/arm/dts/uniphier-pxs3-ref.dts

@@ -68,3 +68,7 @@
 &usb1 {
 	status = "okay";
 };
+
+&nand {
+	status = "okay";
+};

arch/arm/dts/uniphier-sld8-ref.dts

@@ -73,11 +73,6 @@
 	status = "okay";
 };
 
-/* for U-Boot only */
-&serial0 {
-	u-boot,dm-pre-reloc;
-};
-
-&pinctrl_uart0 {
-	u-boot,dm-pre-reloc;
+&nand {
+	status = "okay";
 };

arch/arm/dts/uniphier-sld8.dtsi

@@ -50,7 +50,6 @@
 		#size-cells = <1>;
 		ranges;
 		interrupt-parent = <&intc>;
-		u-boot,dm-pre-reloc;
 
 		l2: l2-cache@500c0000 {
 			compatible = "socionext,uniphier-system-cache";
@@ -299,11 +298,9 @@
 			compatible = "socionext,uniphier-sld8-soc-glue",
 				     "simple-mfd", "syscon";
 			reg = <0x5f800000 0x2000>;
-			u-boot,dm-pre-reloc;
 
 			pinctrl: pinctrl {
 				compatible = "socionext,uniphier-sld8-pinctrl";
-				u-boot,dm-pre-reloc;
 			};
 		};
 

arch/arm/dts/uniphier-v7-u-boot.dtsi

@@ -0,0 +1,61 @@
+/ {
+	soc {
+		u-boot,dm-pre-reloc;
+
+		serial@54006800 {
+			u-boot,dm-pre-reloc;
+		};
+
+		serial@54006900 {
+			u-boot,dm-pre-reloc;
+		};
+
+		serial@54006a00 {
+			u-boot,dm-pre-reloc;
+		};
+
+		mioctrl@59810000 {
+			u-boot,dm-pre-reloc;
+
+			clock {
+				u-boot,dm-pre-reloc;
+			};
+		};
+
+		sdctrl@59810000 {
+			u-boot,dm-pre-reloc;
+
+			clock {
+				u-boot,dm-pre-reloc;
+			};
+		};
+
+		soc-glue@5f800000 {
+			u-boot,dm-pre-reloc;
+
+			pinctrl {
+				u-boot,dm-pre-reloc;
+
+				emmc_grp {
+					u-boot,dm-pre-reloc;
+				};
+
+				uart0_grp {
+					u-boot,dm-pre-reloc;
+				};
+
+				uart1_grp {
+					u-boot,dm-pre-reloc;
+				};
+
+				uart2_grp {
+					u-boot,dm-pre-reloc;
+				};
+			};
+		};
+	};
+};
+
+&emmc {
+	u-boot,dm-pre-reloc;
+};

arch/arm/include/asm/arch-fsl-layerscape/config.h

@@ -16,7 +16,7 @@
  * Reserve secure memory
  * To be aligned with MMU block size
  */
-#define CONFIG_SYS_MEM_RESERVE_SECURE	(2048 * 1024)	/* 2MB */
+#define CONFIG_SYS_MEM_RESERVE_SECURE	(66 * 1024 * 1024)	/* 66MB */
 #define SPL_TLB_SETBACK	0x1000000	/* 16MB under effective memory top */
 
 #ifdef CONFIG_ARCH_LS2080A

arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h

@@ -158,7 +158,7 @@ struct sunxi_ccm_reg {
 #define CPU_CLK_SRC_OSC24M		0
 #define CPU_CLK_SRC_PLL1		1
 
-#define CCM_PLL1_CTRL_N(n)		((((n) - 1) & 0xff) << 8)
+#define CCM_PLL1_CTRL_N(n)		(((n) & 0xff) << 8)
 #define CCM_PLL1_CTRL_P(n)		(((n) & 0x1) << 16)
 #define CCM_PLL1_CTRL_EN		(0x1 << 31)
 #define CMM_PLL1_CLOCK_TIME_2		(0x2 << 24)

arch/arm/include/asm/arch-sunxi/lcdc.h

@@ -124,5 +124,8 @@ void lcdc_tcon0_mode_set(struct sunxi_lcdc_reg * const lcdc,
 void lcdc_tcon1_mode_set(struct sunxi_lcdc_reg * const lcdc,
 			 const struct display_timing *mode,
 			 bool ext_hvsync, bool is_composite);
+void lcdc_pll_set(struct sunxi_ccm_reg * const ccm, int tcon,
+		  int dotclock, int *clk_div, int *clk_double,
+		  bool is_composite);
 
 #endif /* _LCDC_H */

arch/arm/include/asm/armv8/sec_firmware.h

@@ -9,8 +9,10 @@
 
 #define PSCI_INVALID_VER		0xffffffff
 #define SEC_JR3_OFFSET			0x40000
+#define WORD_MASK			0xffffffff
+#define WORD_SHIFT			32
 
-int sec_firmware_init(const void *, u32 *, u32 *);
+int sec_firmware_init(const void *, u32 *, u32 *, u32 *, u32 *);
 int _sec_firmware_entry(const void *, u32 *, u32 *);
 bool sec_firmware_is_valid(const void *);
 bool sec_firmware_support_hwrng(void);

arch/arm/mach-omap2/Kconfig

@@ -11,6 +11,7 @@ config OMAP34XX
 	select ARM_ERRATA_621766
 	select ARM_ERRATA_725233
 	select USE_TINY_PRINTF
+	imply NAND_OMAP_GPMC
 	imply SPL_EXT_SUPPORT
 	imply SPL_FAT_SUPPORT
 	imply SPL_GPIO_SUPPORT
@@ -30,6 +31,8 @@ config OMAP34XX
 config OMAP44XX
 	bool "OMAP44XX SoC"
 	select USE_TINY_PRINTF
+	imply NAND_OMAP_ELM
+	imply NAND_OMAP_GPMC
 	imply SPL_DISPLAY_PRINT
 	imply SPL_EXT_SUPPORT
 	imply SPL_FAT_SUPPORT
@@ -39,6 +42,7 @@ config OMAP44XX
 	imply SPL_LIBDISK_SUPPORT
 	imply SPL_LIBGENERIC_SUPPORT
 	imply SPL_MMC_SUPPORT
+	imply SPL_NAND_SIMPLE
 	imply SPL_NAND_SUPPORT
 	imply SPL_POWER_SUPPORT
 	imply SPL_SERIAL_SUPPORT
@@ -49,6 +53,8 @@ config OMAP54XX
 	bool "OMAP54XX SoC"
 	select ARM_ERRATA_798870
 	select SYS_THUMB_BUILD
+	imply NAND_OMAP_ELM
+	imply NAND_OMAP_GPMC
 	imply SPL_DISPLAY_PRINT
 	imply SPL_ENV_SUPPORT
 	imply SPL_EXT_SUPPORT
@@ -59,6 +65,8 @@ config OMAP54XX
 	imply SPL_LIBDISK_SUPPORT
 	imply SPL_LIBGENERIC_SUPPORT
 	imply SPL_MMC_SUPPORT
+	imply SPL_NAND_AM33XX_BCH
+	imply SPL_NAND_AM33XX_BCH
 	imply SPL_NAND_SUPPORT
 	imply SPL_POWER_SUPPORT
 	imply SPL_SERIAL_SUPPORT
@@ -73,6 +81,8 @@ config TI814X
 
 config TI816X
 	bool "TI816X SoC"
+	imply NAND_OMAP_ELM
+	imply NAND_OMAP_GPMC
 	help
 	  Support for AM335x SOC from Texas Instruments.
 	  The AM335x high performance SOC features a Cortex-A8
@@ -80,8 +90,12 @@ config TI816X
 
 config AM43XX
 	bool "AM43XX SoC"
+	imply NAND_OMAP_ELM
+	imply NAND_OMAP_GPMC
 	imply SPL_DM
 	imply SPL_DM_SEQ_ALIAS
+	imply SPL_NAND_AM33XX_BCH
+	imply SPL_NAND_SUPPORT
 	imply SPL_OF_CONTROL
 	imply SPL_OF_TRANSLATE
 	imply SPL_SEPARATE_BSS
@@ -97,6 +111,10 @@ config AM43XX
 
 config AM33XX
 	bool "AM33XX SoC"
+	imply NAND_OMAP_ELM
+	imply NAND_OMAP_GPMC
+	imply SPL_NAND_AM33XX_BCH
+	imply SPL_NAND_SUPPORT
 	imply SYS_I2C_OMAP24XX
 	imply SYS_THUMB_BUILD
 	imply USE_TINY_PRINTF

arch/arm/mach-sunxi/Kconfig

@@ -606,7 +606,7 @@ config AXP_GPIO
 	---help---
 	Say Y here to enable support for the gpio pins of the axp PMIC ICs.
 
-config VIDEO
+config VIDEO_SUNXI
 	bool "Enable graphical uboot console on HDMI, LCD or VGA"
 	depends on !MACH_SUN8I_A83T
 	depends on !MACH_SUNXI_H3_H5
@@ -614,6 +614,8 @@ config VIDEO
 	depends on !MACH_SUN8I_V3S
 	depends on !MACH_SUN9I
 	depends on !MACH_SUN50I
+	select VIDEO
+	imply VIDEO_DT_SIMPLEFB
 	default y
 	---help---
 	Say Y here to add support for using a cfb console on the HDMI, LCD
@@ -622,21 +624,21 @@ config VIDEO
 
 config VIDEO_HDMI
 	bool "HDMI output support"
-	depends on VIDEO && !MACH_SUN8I
+	depends on VIDEO_SUNXI && !MACH_SUN8I
 	default y
 	---help---
 	Say Y here to add support for outputting video over HDMI.
 
 config VIDEO_VGA
 	bool "VGA output support"
-	depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
+	depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN7I)
 	default n
 	---help---
 	Say Y here to add support for outputting video over VGA.
 
 config VIDEO_VGA_VIA_LCD
 	bool "VGA via LCD controller support"
-	depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
+	depends on VIDEO_SUNXI && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
 	default n
 	---help---
 	Say Y here to add support for external DACs connected to the parallel
@@ -663,14 +665,14 @@ config VIDEO_VGA_EXTERNAL_DAC_EN
 
 config VIDEO_COMPOSITE
 	bool "Composite video output support"
-	depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
+	depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
 	default n
 	---help---
 	Say Y here to add support for outputting composite video.
 
 config VIDEO_LCD_MODE
 	string "LCD panel timing details"
-	depends on VIDEO
+	depends on VIDEO_SUNXI
 	default ""
 	---help---
 	LCD panel timing details string, leave empty if there is no LCD panel.
@@ -680,14 +682,14 @@ config VIDEO_LCD_MODE
 
 config VIDEO_LCD_DCLK_PHASE
 	int "LCD panel display clock phase"
-	depends on VIDEO
+	depends on VIDEO_SUNXI || DM_VIDEO
 	default 1
 	---help---
 	Select LCD panel display clock phase shift, range 0-3.
 
 config VIDEO_LCD_POWER
 	string "LCD panel power enable pin"
-	depends on VIDEO
+	depends on VIDEO_SUNXI
 	default ""
 	---help---
 	Set the power enable pin for the LCD panel. This takes a string in the
@@ -695,7 +697,7 @@ config VIDEO_LCD_POWER
 
 config VIDEO_LCD_RESET
 	string "LCD panel reset pin"
-	depends on VIDEO
+	depends on VIDEO_SUNXI
 	default ""
 	---help---
 	Set the reset pin for the LCD panel. This takes a string in the format
@@ -703,7 +705,7 @@ config VIDEO_LCD_RESET
 
 config VIDEO_LCD_BL_EN
 	string "LCD panel backlight enable pin"
-	depends on VIDEO
+	depends on VIDEO_SUNXI
 	default ""
 	---help---
 	Set the backlight enable pin for the LCD panel. This takes a string in the
@@ -712,7 +714,7 @@ config VIDEO_LCD_BL_EN
 
 config VIDEO_LCD_BL_PWM
 	string "LCD panel backlight pwm pin"
-	depends on VIDEO
+	depends on VIDEO_SUNXI
 	default ""
 	---help---
 	Set the backlight pwm pin for the LCD panel. This takes a string in the
@@ -720,14 +722,14 @@ config VIDEO_LCD_BL_PWM
 
 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
 	bool "LCD panel backlight pwm is inverted"
-	depends on VIDEO
+	depends on VIDEO_SUNXI
 	default y
 	---help---
 	Set this if the backlight pwm output is active low.
 
 config VIDEO_LCD_PANEL_I2C
 	bool "LCD panel needs to be configured via i2c"
-	depends on VIDEO
+	depends on VIDEO_SUNXI
 	default n
 	select CMD_I2C
 	---help---
@@ -768,6 +770,7 @@ config VIDEO_DE2
 	depends on SUNXI_DE2
 	select DM_VIDEO
 	select DISPLAY
+	imply VIDEO_DT_SIMPLEFB
 	default y
 	---help---
 	Say y here if you want to build DE2 video driver which is present on
@@ -776,7 +779,7 @@ config VIDEO_DE2
 
 choice
 	prompt "LCD panel support"
-	depends on VIDEO
+	depends on VIDEO_SUNXI
 	---help---
 	Select which type of LCD panel to support.
 

arch/arm/mach-uniphier/Kconfig

@@ -117,4 +117,6 @@ config CMD_DDRMPHY_DUMP
 	  The command "ddrmphy" shows the resulting parameters of DDR Multi PHY
 	  training; it is useful for the evaluation of DDR Multi PHY training.
 
+config SYS_SOC
+	default "uniphier-v7" if ARCH_UNIPHIER_LD4_SLD8 || ARCH_UNIPHIER_V7_MULTI
 endif

arch/arm/mach-uniphier/clk/clk-ld4.c

@@ -17,9 +17,6 @@ void uniphier_ld4_clk_init(void)
 
 	/* deassert reset */
 	tmp = readl(SC_RSTCTRL);
-#ifdef CONFIG_UNIPHIER_ETH
-	tmp |= SC_RSTCTRL_NRST_ETHER;
-#endif
 #ifdef CONFIG_NAND_DENALI
 	tmp |= SC_RSTCTRL_NRST_NAND;
 #endif
@@ -28,9 +25,6 @@ void uniphier_ld4_clk_init(void)
 
 	/* provide clocks */
 	tmp = readl(SC_CLKCTRL);
-#ifdef CONFIG_UNIPHIER_ETH
-	tmp |= SC_CLKCTRL_CEN_ETHER;
-#endif
 #ifdef CONFIG_USB_EHCI_HCD
 	tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC;
 #endif

arch/arm/mach-uniphier/clk/clk-pro4.c

@@ -21,9 +21,6 @@ void uniphier_pro4_clk_init(void)
 	tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_USB3C0 |
 		SC_RSTCTRL_NRST_GIO;
 #endif
-#ifdef CONFIG_UNIPHIER_ETH
-	tmp |= SC_RSTCTRL_NRST_ETHER;
-#endif
 #ifdef CONFIG_NAND_DENALI
 	tmp |= SC_RSTCTRL_NRST_NAND;
 #endif
@@ -43,9 +40,6 @@ void uniphier_pro4_clk_init(void)
 	tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
 		SC_CLKCTRL_CEN_GIO;
 #endif
-#ifdef CONFIG_UNIPHIER_ETH
-	tmp |= SC_CLKCTRL_CEN_ETHER;
-#endif
 #ifdef CONFIG_USB_EHCI_HCD
 	tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC;
 #endif

arch/arm/mach-uniphier/clk/clk-pxs2.c

@@ -19,9 +19,6 @@ void uniphier_pxs2_clk_init(void)
 #ifdef CONFIG_USB_DWC3_UNIPHIER
 	tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_GIO;
 #endif
-#ifdef CONFIG_UNIPHIER_ETH
-	tmp |= SC_RSTCTRL_NRST_ETHER;
-#endif
 #ifdef CONFIG_NAND_DENALI
 	tmp |= SC_RSTCTRL_NRST_NAND;
 #endif
@@ -45,9 +42,6 @@ void uniphier_pxs2_clk_init(void)
 	tmp |= BIT(20) | BIT(19) | SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
 		SC_CLKCTRL_CEN_GIO;
 #endif
-#ifdef CONFIG_UNIPHIER_ETH
-	tmp |= SC_CLKCTRL_CEN_ETHER;
-#endif
 #ifdef CONFIG_NAND_DENALI
 	tmp |= SC_CLKCTRL_CEN_NAND;
 #endif

arch/arm/mach-uniphier/dram/ddrphy-training.c

@@ -5,9 +5,13 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#include <common.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
 #include <linux/errno.h>
 #include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/printk.h>
+#include <time.h>
 
 #include "ddrphy-init.h"
 #include "ddrphy-regs.h"
@@ -108,7 +112,7 @@ int ddrphy_training(void __iomem *phy_base)
 	u32 init_flag = PHY_PIR_INIT;
 	u32 done_flag = PHY_PGSR0_IDONE;
 	int timeout = 50000; /* 50 msec is long enough */
-#ifdef DISPLAY_ELAPSED_TIME
+#ifdef DEBUG
 	ulong start = get_timer(0);
 #endif
 
@@ -121,8 +125,7 @@ int ddrphy_training(void __iomem *phy_base)
 
 	do {
 		if (--timeout < 0) {
-			printf("%s: error: timeout during DDR training\n",
-								__func__);
+			pr_err("timeout during DDR training\n");
 			return -ETIMEDOUT;
 		}
 		udelay(1);
@@ -131,14 +134,13 @@ int ddrphy_training(void __iomem *phy_base)
 
 	for (i = 0; i < ARRAY_SIZE(init_sequence); i++) {
 		if (pgsr0 & init_sequence[i].err_flag) {
-			printf("%s: error: %s failed\n", __func__,
-						init_sequence[i].description);
+			pr_err("%s failed\n", init_sequence[i].description);
 			return -EIO;
 		}
 	}
 
-#ifdef DISPLAY_ELAPSED_TIME
-	printf("%s: info: elapsed time %ld msec\n", get_timer(start));
+#ifdef DEBUG
+	pr_debug("DDR training: elapsed time %ld msec\n", get_timer(start));
 #endif
 
 	return 0;

arch/powerpc/cpu/mpc85xx/release.S

@@ -184,12 +184,18 @@ __secondary_start_page:
 
 	mtspr	SPRN_PIR,r4	/* write to PIR register */
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007907
+	mfspr	r8, L1CSR2
+	clrrwi	r8, r8, 10	/* clear bit [54-63] DCSTASHID */
+	mtspr	L1CSR2, r8
+#else
 #ifdef CONFIG_SYS_CACHE_STASHING
 	/* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
 	slwi	r8,r4,1
 	addi	r8,r8,32
 	mtspr	L1CSR2,r8
 #endif
+#endif	/* CONFIG_SYS_FSL_ERRATUM_A007907 */
 
 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
 	defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)

arch/x86/Kconfig

@@ -402,15 +402,6 @@ config FSP_BROKEN_HOB
 	  do not overwrite the important boot service data which is used by
 	  FSP, otherwise the subsequent call to fsp_notify() will fail.
 
-config FSP_LOCKDOWN_SPI
-	bool
-	depends on HAVE_FSP
-	help
-	  Some Intel FSP (like Braswell) does SPI lock-down during the call
-	  to fsp_notify(INIT_PHASE_BOOT). This option should be turned on
-	  for such FSP and U-Boot will configure the SPI opcode registers
-	  before the lock-down.
-
 config ENABLE_MRC_CACHE
 	bool "Enable MRC cache"
 	depends on !EFI && !SYS_COREBOOT
@@ -664,6 +655,7 @@ endmenu
 
 config HAVE_ACPI_RESUME
 	bool "Enable ACPI S3 resume"
+	select ENABLE_MRC_CACHE
 	help
 	  Select this to enable ACPI S3 resume. S3 is an ACPI-defined sleeping
 	  state where all system context is lost except system memory. U-Boot
@@ -677,7 +669,6 @@ config HAVE_ACPI_RESUME
 config S3_VGA_ROM_RUN
 	bool "Re-run VGA option ROMs on S3 resume"
 	depends on HAVE_ACPI_RESUME
-	default y if HAVE_ACPI_RESUME
 	help
 	  Execute VGA option ROMs in U-Boot when resuming from S3. Normally
 	  this is needed when graphics console is being used in the kernel.

arch/x86/cpu/baytrail/fsp_configs.c

@@ -8,117 +8,20 @@
 
 #include <common.h>
 #include <fdtdec.h>
-#include <asm/arch/fsp/azalia.h>
 #include <asm/fsp/fsp_support.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-/* ALC262 Verb Table - 10EC0262 */
-static const uint32_t verb_table_data13[] = {
-	/* Pin Complex (NID 0x11) */
-	0x01171cf0,
-	0x01171d11,
-	0x01171e11,
-	0x01171f41,
-	/* Pin Complex (NID 0x12) */
-	0x01271cf0,
-	0x01271d11,
-	0x01271e11,
-	0x01271f41,
-	/* Pin Complex (NID 0x14) */
-	0x01471c10,
-	0x01471d40,
-	0x01471e01,
-	0x01471f01,
-	/* Pin Complex (NID 0x15) */
-	0x01571cf0,
-	0x01571d11,
-	0x01571e11,
-	0x01571f41,
-	/* Pin Complex (NID 0x16) */
-	0x01671cf0,
-	0x01671d11,
-	0x01671e11,
-	0x01671f41,
-	/* Pin Complex (NID 0x18) */
-	0x01871c20,
-	0x01871d98,
-	0x01871ea1,
-	0x01871f01,
-	/* Pin Complex (NID 0x19) */
-	0x01971c21,
-	0x01971d98,
-	0x01971ea1,
-	0x01971f02,
-	/* Pin Complex (NID 0x1A) */
-	0x01a71c2f,
-	0x01a71d30,
-	0x01a71e81,
-	0x01a71f01,
-	/* Pin Complex */
-	0x01b71c1f,
-	0x01b71d40,
-	0x01b71e21,
-	0x01b71f02,
-	/* Pin Complex */
-	0x01c71cf0,
-	0x01c71d11,
-	0x01c71e11,
-	0x01c71f41,
-	/* Pin Complex */
-	0x01d71c01,
-	0x01d71dc6,
-	0x01d71e14,
-	0x01d71f40,
-	/* Pin Complex */
-	0x01e71cf0,
-	0x01e71d11,
-	0x01e71e11,
-	0x01e71f41,
-	/* Pin Complex */
-	0x01f71cf0,
-	0x01f71d11,
-	0x01f71e11,
-	0x01f71f41,
-};
-
-/*
- * This needs to be in ROM since if we put it in CAR, FSP init loses it when
- * it drops CAR.
+/**
+ * Override the FSP's Azalia configuration data
  *
- * TODO(sjg@chromium.org): Move to device tree when FSP allows it
- *
- * VerbTable: (RealTek ALC262)
- * Revision ID = 0xFF, support all steps
- * Codec Verb Table For AZALIA
- * Codec Address: CAd value (0/1/2)
- * Codec Vendor: 0x10EC0262
+ * @azalia:	pointer to be updated to point to a ROM address where Azalia
+ *		configuration data is stored
  */
-static const struct pch_azalia_verb_table azalia_verb_table[] = {
-	{
-		{
-			0x10ec0262,
-			0x0000,
-			0xff,
-			0x01,
-			0x000b,
-			0x0002,
-		},
-		verb_table_data13
-	}
-};
-
-const struct pch_azalia_config azalia_config = {
-	.pme_enable = 1,
-	.docking_supported = 1,
-	.docking_attached = 0,
-	.hdmi_codec_enable = 1,
-	.azalia_v_ci_enable = 1,
-	.rsvdbits = 0,
-	.azalia_verb_table_num = 1,
-	.azalia_verb_table = azalia_verb_table,
-	.reset_wait_timer_us = 300
-};
+__weak void update_fsp_azalia_configs(struct azalia_config **azalia)
+{
+	*azalia = NULL;
+}
 
 /**
  * Override the FSP's configuration data.
@@ -138,8 +41,6 @@ void update_fsp_configs(struct fsp_config_data *config,
 	rt_buf->common.boot_mode = config->common.boot_mode;
 	rt_buf->common.upd_data = &config->fsp_upd;
 
-	fsp_upd->azalia_config_ptr = (uint32_t)&azalia_config;
-
 	node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_BAYTRAIL_FSP);
 	if (node < 0) {
 		debug("%s: Cannot find FSP node\n", __func__);
@@ -174,6 +75,8 @@ void update_fsp_configs(struct fsp_config_data *config,
 					    SATA_MODE_AHCI);
 	fsp_upd->enable_azalia = fdtdec_get_bool(blob, node,
 						 "fsp,enable-azalia");
+	if (fsp_upd->enable_azalia)
+		update_fsp_azalia_configs(&fsp_upd->azalia_cfg_ptr);
 	fsp_upd->enable_xhci = fdtdec_get_bool(blob, node, "fsp,enable-xhci");
 	fsp_upd->lpe_mode = fdtdec_get_int(blob, node, "fsp,lpe-mode",
 					   LPE_MODE_PCI);

arch/x86/cpu/baytrail/valleyview.c

@@ -10,6 +10,13 @@
 #include <asm/irq.h>
 #include <asm/mrccache.h>
 #include <asm/post.h>
+#include <asm/arch/iomap.h>
+
+/* GPIO SUS */
+#define GPIO_SUS_PAD_BASE	(IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSSUS)
+#define GPIO_SUS_DFX5_CONF0	0x150
+#define BYT_TRIG_LVL		BIT(24)
+#define BYT_TRIG_POS		BIT(25)
 
 #ifndef CONFIG_EFI_APP
 int arch_cpu_init(void)
@@ -33,6 +40,21 @@ int arch_misc_init(void)
 	mrccache_save();
 #endif
 
+	/*
+	 * For some unknown reason, FSP (gold4) for BayTrail configures
+	 * the GPIO DFX5 PAD to enable level interrupt (bit 24 and 25).
+	 * This does not cause any issue when Linux kernel runs w/ or w/o
+	 * the pinctrl driver for BayTrail. However this causes unstable
+	 * S3 resume if the pinctrl driver is included in the kernel build.
+	 * As this pin keeps generating interrupts during an S3 resume,
+	 * and there is no IRQ requester in the kernel to handle it, the
+	 * kernel seems to hang and does not continue resuming.
+	 *
+	 * Clear the mysterious interrupt bits for this pin.
+	 */
+	clrbits_le32(GPIO_SUS_PAD_BASE + GPIO_SUS_DFX5_CONF0,
+		     BYT_TRIG_LVL | BYT_TRIG_POS);
+
 	return 0;
 }
 

arch/x86/cpu/braswell/Kconfig

@@ -12,7 +12,6 @@ config INTEL_BRASWELL
 	imply HAVE_INTEL_ME
 	imply HAVE_VBT
 	imply ENABLE_MRC_CACHE
-	imply ENV_IS_IN_SPI_FLASH
 	imply AHCI_PCI
 	imply ICH_SPI
 	imply MMC
@@ -32,8 +31,4 @@ config FSP_ADDR
 	hex
 	default 0xfff20000
 
-config FSP_LOCKDOWN_SPI
-	bool
-	default y
-
 endif

arch/x86/cpu/braswell/Makefile

@@ -4,4 +4,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-y += braswell.o cpu.o early_uart.o fsp_configs.o
+obj-y += braswell.o early_uart.o fsp_configs.o

arch/x86/cpu/braswell/cpu.c

@@ -1,170 +0,0 @@
-/*
- * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * Derived from arch/x86/cpu/baytrail/cpu.c
- */
-
-#include <common.h>
-#include <cpu.h>
-#include <dm.h>
-#include <asm/cpu.h>
-#include <asm/cpu_x86.h>
-#include <asm/io.h>
-#include <asm/lapic.h>
-#include <asm/msr.h>
-#include <asm/turbo.h>
-
-static const unsigned int braswell_bus_freq_table[] = {
-	83333333,
-	100000000,
-	133333333,
-	116666666,
-	80000000,
-	93333333,
-	90000000,
-	88900000,
-	87500000
-};
-
-static unsigned int braswell_bus_freq(void)
-{
-	msr_t clk_info = msr_read(MSR_BSEL_CR_OVERCLOCK_CONTROL);
-
-	if ((clk_info.lo & 0xf) < (ARRAY_SIZE(braswell_bus_freq_table)))
-		return braswell_bus_freq_table[clk_info.lo & 0xf];
-
-	return 0;
-}
-
-static unsigned long braswell_tsc_freq(void)
-{
-	msr_t platform_info;
-	ulong bclk = braswell_bus_freq();
-
-	if (!bclk)
-		return 0;
-
-	platform_info = msr_read(MSR_PLATFORM_INFO);
-
-	return bclk * ((platform_info.lo >> 8) & 0xff);
-}
-
-static int braswell_get_info(struct udevice *dev, struct cpu_info *info)
-{
-	info->cpu_freq = braswell_tsc_freq();
-	info->features = (1 << CPU_FEAT_L1_CACHE) | (1 << CPU_FEAT_MMU);
-
-	return 0;
-}
-
-static int braswell_get_count(struct udevice *dev)
-{
-	int ecx = 0;
-
-	/*
-	 * Use the algorithm described in Intel 64 and IA-32 Architectures
-	 * Software Developer's Manual Volume 3 (3A, 3B & 3C): System
-	 * Programming Guide, Jan-2015. Section 8.9.2: Hierarchical Mapping
-	 * of CPUID Extended Topology Leaf.
-	 */
-	while (1) {
-		struct cpuid_result leaf_b;
-
-		leaf_b = cpuid_ext(0xb, ecx);
-
-		/*
-		 * Braswell doesn't have hyperthreading so just determine the
-		 * number of cores by from level type (ecx[15:8] == * 2)
-		 */
-		if ((leaf_b.ecx & 0xff00) == 0x0200)
-			return leaf_b.ebx & 0xffff;
-
-		ecx++;
-	}
-
-	return 0;
-}
-
-static void braswell_set_max_freq(void)
-{
-	msr_t perf_ctl;
-	msr_t msr;
-
-	/* Enable speed step */
-	msr = msr_read(MSR_IA32_MISC_ENABLES);
-	msr.lo |= (1 << 16);
-	msr_write(MSR_IA32_MISC_ENABLES, msr);
-
-	/* Enable Burst Mode */
-	msr = msr_read(MSR_IA32_MISC_ENABLES);
-	msr.hi = 0;
-	msr_write(MSR_IA32_MISC_ENABLES, msr);
-
-	/*
-	 * Set guaranteed ratio [21:16] from IACORE_TURBO_RATIOS to
-	 * bits [15:8] of the PERF_CTL
-	 */
-	msr = msr_read(MSR_IACORE_TURBO_RATIOS);
-	perf_ctl.lo = (msr.lo & 0x3f0000) >> 8;
-
-	/*
-	 * Set guaranteed vid [22:16] from IACORE_TURBO_VIDS to
-	 * bits [7:0] of the PERF_CTL
-	 */
-	msr = msr_read(MSR_IACORE_TURBO_VIDS);
-	perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16;
-
-	perf_ctl.hi = 0;
-	msr_write(MSR_IA32_PERF_CTL, perf_ctl);
-}
-
-static int braswell_probe(struct udevice *dev)
-{
-	debug("Init Braswell core\n");
-
-	/*
-	 * On Braswell the turbo disable bit is actually scoped at the
-	 * building-block level, not package. For non-BSP cores that are
-	 * within a building block, enable turbo. The cores within the BSP's
-	 * building block will just see it already enabled and move on.
-	 */
-	if (lapicid())
-		turbo_enable();
-
-	/* Dynamic L2 shrink enable and threshold, clear SINGLE_PCTL bit 11 */
-	msr_clrsetbits_64(MSR_PMG_CST_CONFIG_CONTROL, 0x3f080f, 0xe0008),
-	msr_clrsetbits_64(MSR_POWER_MISC,
-			  ENABLE_ULFM_AUTOCM_MASK | ENABLE_INDP_AUTOCM_MASK, 0);
-
-	/* Disable C1E */
-	msr_clrsetbits_64(MSR_POWER_CTL, 2, 0);
-	msr_setbits_64(MSR_POWER_MISC, 0x44);
-
-	/* Set this core to max frequency ratio */
-	braswell_set_max_freq();
-
-	return 0;
-}
-
-static const struct udevice_id braswell_ids[] = {
-	{ .compatible = "intel,braswell-cpu" },
-	{ }
-};
-
-static const struct cpu_ops braswell_ops = {
-	.get_desc	= cpu_x86_get_desc,
-	.get_info	= braswell_get_info,
-	.get_count	= braswell_get_count,
-	.get_vendor	= cpu_x86_get_vendor,
-};
-
-U_BOOT_DRIVER(cpu_x86_braswell_drv) = {
-	.name		= "cpu_x86_braswell",
-	.id		= UCLASS_CPU,
-	.of_match	= braswell_ids,
-	.bind		= cpu_x86_bind,
-	.probe		= braswell_probe,
-	.ops		= &braswell_ops,
-};

arch/x86/dts/cherryhill.dts

@@ -37,28 +37,28 @@
 
 		cpu@0 {
 			device_type = "cpu";
-			compatible = "intel,braswell-cpu";
+			compatible = "cpu-x86";
 			reg = <0>;
 			intel,apic-id = <0>;
 		};
 
 		cpu@1 {
 			device_type = "cpu";
-			compatible = "intel,braswell-cpu";
+			compatible = "cpu-x86";
 			reg = <1>;
 			intel,apic-id = <2>;
 		};
 
 		cpu@2 {
 			device_type = "cpu";
-			compatible = "intel,braswell-cpu";
+			compatible = "cpu-x86";
 			reg = <2>;
 			intel,apic-id = <4>;
 		};
 
 		cpu@3 {
 			device_type = "cpu";
-			compatible = "intel,braswell-cpu";
+			compatible = "cpu-x86";
 			reg = <3>;
 			intel,apic-id = <6>;
 		};
@@ -143,6 +143,7 @@
 				#address-cells = <1>;
 				#size-cells = <0>;
 				compatible = "intel,ich9-spi";
+				intel,spi-lock-down;
 
 				spi-flash@0 {
 					#address-cells = <1>;
@@ -194,7 +195,6 @@
 			fsp,pmic-i2c-bus = <0>;
 			fsp,enable-isp;
 			fsp,isp-pci-dev-config = <ISP_PCI_DEV_CONFIG_2>;
-			fsp,turbo-mode;
 			fsp,pnp-settings = <PNP_SETTING_POWER_AND_PERF>;
 			fsp,sd-detect-chk;
 		};

arch/x86/include/asm/arch-baytrail/acpi/platform.asl

@@ -36,4 +36,4 @@ Scope (\_SB)
 }
 
 /* Chipset specific sleep states */
-#include "sleepstates.asl"
+#include <asm/acpi/sleepstates.asl>

arch/x86/include/asm/arch-baytrail/fsp/azalia.h

@@ -1,39 +0,0 @@
-/*
- * Copyright (C) 2013, Intel Corporation
- * Copyright (C) 2015 Google, Inc
- *
- * SPDX-License-Identifier:	Intel
- */
-
-#ifndef _FSP_AZALIA_H_
-#define _FSP_AZALIA_H_
-
-struct __packed pch_azalia_verb_table_header {
-	uint32_t vendor_device_id;
-	uint16_t sub_system_id;
-	uint8_t revision_id;		/* 0xff applies to all steppings */
-	uint8_t front_panel_support;
-	uint16_t number_of_rear_jacks;
-	uint16_t number_of_front_jacks;
-};
-
-struct __packed pch_azalia_verb_table {
-	struct pch_azalia_verb_table_header verb_table_header;
-	const uint32_t *verb_table_data;
-};
-
-struct __packed pch_azalia_config {
-	uint8_t pme_enable:1;
-	uint8_t docking_supported:1;
-	uint8_t docking_attached:1;
-	uint8_t hdmi_codec_enable:1;
-	uint8_t azalia_v_ci_enable:1;
-	uint8_t rsvdbits:3;
-	/* number of verb tables provided by platform */
-	uint8_t azalia_verb_table_num;
-	const struct pch_azalia_verb_table *azalia_verb_table;
-	/* delay timer after azalia reset */
-	uint16_t reset_wait_timer_us;
-};
-
-#endif

arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h

@@ -45,7 +45,7 @@ struct __packed upd_region {
 	uint8_t enable_sata;			/* Offset 0x002d */
 	uint8_t sata_mode;			/* Offset 0x002e */
 	uint8_t enable_azalia;			/* Offset 0x002f */
-	uint32_t azalia_config_ptr;		/* Offset 0x0030 */
+	struct azalia_config *azalia_cfg_ptr;	/* Offset 0x0030 */
 	uint8_t enable_xhci;			/* Offset 0x0034 */
 	uint8_t lpe_mode;			/* Offset 0x0035 */
 	uint8_t lpss_sio_mode;			/* Offset 0x0036 */

arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h

@@ -29,32 +29,6 @@ struct __packed memory_upd {
 	u8 reserved[189];			/* Offset 0x0043 */
 };
 
-struct __packed azalia_verb_table_header {
-	u32 vendor_device_id;
-	u16 sub_system_id;
-	u8 revision_id;
-	u8 front_panel_support;
-	u16 number_of_rear_jacks;
-	u16 number_of_front_jacks;
-};
-
-struct __packed azalia_verb_table {
-	struct azalia_verb_table_header header;
-	u32 *data;
-};
-
-struct __packed azalia_config {
-	u8 pme_enable:1;
-	u8 docking_supported:1;
-	u8 docking_attached:1;
-	u8 hdmi_codec_enable:1;
-	u8 azalia_v_ci_enable:1;
-	u8 reserved:3;
-	u8 verb_table_num;
-	struct azalia_verb_table *verb_table;
-	u16 reset_wait_timer_ms;
-};
-
 struct gpio_family {
 	u32 confg;
 	u32 confg_changes;

arch/x86/include/asm/arch-quark/acpi/platform.asl

@@ -33,4 +33,4 @@ Scope (\_SB)
 }
 
 /* Chipset specific sleep states */
-#include "sleepstates.asl"
+#include <asm/acpi/sleepstates.asl>

arch/x86/include/asm/arch-quark/acpi/sleepstates.asl

@@ -1,10 +0,0 @@
-/*
- * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-Name(\_S0, Package() {0x0, 0x0, 0x0, 0x0})
-Name(\_S3, Package() {0x5, 0x0, 0x0, 0x0})
-Name(\_S4, Package() {0x6, 0x0, 0x0, 0x0})
-Name(\_S5, Package() {0x7, 0x0, 0x0, 0x0})

arch/x86/include/asm/fsp/fsp_azalia.h

@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2015, Google, Inc
+ *
+ * SPDX-License-Identifier:	Intel
+ */
+
+#ifndef _FSP_AZALIA_H_
+#define _FSP_AZALIA_H_
+
+struct __packed azalia_verb_table_header {
+	u32 vendor_device_id;
+	u16 sub_system_id;
+	u8 revision_id;		/* 0xff applies to all steppings */
+	u8 front_panel_support;
+	u16 number_of_rear_jacks;
+	u16 number_of_front_jacks;
+};
+
+struct __packed azalia_verb_table {
+	struct azalia_verb_table_header header;
+	const u32 *data;
+};
+
+struct __packed azalia_config {
+	u8 pme_enable:1;
+	u8 docking_supported:1;
+	u8 docking_attached:1;
+	u8 hdmi_codec_enable:1;
+	u8 azalia_v_ci_enable:1;
+	u8 rsvdbits:3;
+	/* number of verb tables provided by platform */
+	u8 verb_table_num;
+	const struct azalia_verb_table *verb_table;
+	/* delay timer after azalia reset */
+	u16 reset_wait_timer_ms;
+};
+
+#endif

arch/x86/include/asm/fsp/fsp_support.h

@@ -15,6 +15,7 @@
 #include "fsp_hob.h"
 #include "fsp_infoheader.h"
 #include "fsp_bootmode.h"
+#include "fsp_azalia.h"
 #include <asm/arch/fsp/fsp_vpd.h>
 #include <asm/arch/fsp/fsp_configs.h>
 

arch/x86/lib/fsp/fsp_common.c

@@ -19,8 +19,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-extern void ich_spi_config_opcode(struct udevice *dev);
-
 int checkcpu(void)
 {
 	return 0;
@@ -51,28 +49,6 @@ void board_final_cleanup(void)
 {
 	u32 status;
 
-#ifdef CONFIG_FSP_LOCKDOWN_SPI
-	struct udevice *dev;
-
-	/*
-	 * Some Intel FSP (like Braswell) does SPI lock-down during the call
-	 * to fsp_notify(INIT_PHASE_BOOT). But before SPI lock-down is done,
-	 * it's bootloader's responsibility to configure the SPI controller's
-	 * opcode registers properly otherwise SPI controller driver doesn't
-	 * know how to communicate with the SPI flash device.
-	 *
-	 * Note we cannot do such configuration elsewhere (eg: during the SPI
-	 * controller driver's probe() routine), because:
-	 *
-	 * 1). U-Boot SPI controller driver does not set the lock-down bit
-	 * 2). Any SPI transfer will corrupt the contents of these registers
-	 *
-	 * Hence we have to do it right here before SPI lock-down bit is set.
-	 */
-	if (!uclass_first_device_err(UCLASS_SPI, &dev))
-		ich_spi_config_opcode(dev);
-#endif
-
 	/* call into FspNotify */
 	debug("Calling into FSP (notify phase INIT_PHASE_BOOT): ");
 	status = fsp_notify(NULL, INIT_PHASE_BOOT);

arch/x86/lib/fsp/fsp_graphics.c

@@ -37,6 +37,10 @@ static int save_vesa_mode(struct vesa_mode_info *vesa)
 	/*
 	 * If there is no graphics info structure, bail out and keep
 	 * running on the serial console.
+	 *
+	 * Note: on some platforms (eg: Braswell), the FSP will not produce
+	 * the graphics info HOB unless you plug some cables to the display
+	 * interface (eg: HDMI) on the board.
 	 */
 	if (!ginfo) {
 		debug("FSP graphics hand-off block not found\n");

board/advantech/som-db5800-som-6867/som-db5800-som-6867.c

@@ -6,6 +6,117 @@
  */
 
 #include <common.h>
+#include <asm/fsp/fsp_support.h>
+
+/* ALC262 Verb Table - 10EC0262 */
+static const u32 verb_table_data13[] = {
+	/* Pin Complex (NID 0x11) */
+	0x01171cf0,
+	0x01171d11,
+	0x01171e11,
+	0x01171f41,
+	/* Pin Complex (NID 0x12) */
+	0x01271cf0,
+	0x01271d11,
+	0x01271e11,
+	0x01271f41,
+	/* Pin Complex (NID 0x14) */
+	0x01471c10,
+	0x01471d40,
+	0x01471e01,
+	0x01471f01,
+	/* Pin Complex (NID 0x15) */
+	0x01571cf0,
+	0x01571d11,
+	0x01571e11,
+	0x01571f41,
+	/* Pin Complex (NID 0x16) */
+	0x01671cf0,
+	0x01671d11,
+	0x01671e11,
+	0x01671f41,
+	/* Pin Complex (NID 0x18) */
+	0x01871c20,
+	0x01871d98,
+	0x01871ea1,
+	0x01871f01,
+	/* Pin Complex (NID 0x19) */
+	0x01971c21,
+	0x01971d98,
+	0x01971ea1,
+	0x01971f02,
+	/* Pin Complex (NID 0x1A) */
+	0x01a71c2f,
+	0x01a71d30,
+	0x01a71e81,
+	0x01a71f01,
+	/* Pin Complex */
+	0x01b71c1f,
+	0x01b71d40,
+	0x01b71e21,
+	0x01b71f02,
+	/* Pin Complex */
+	0x01c71cf0,
+	0x01c71d11,
+	0x01c71e11,
+	0x01c71f41,
+	/* Pin Complex */
+	0x01d71c01,
+	0x01d71dc6,
+	0x01d71e14,
+	0x01d71f40,
+	/* Pin Complex */
+	0x01e71cf0,
+	0x01e71d11,
+	0x01e71e11,
+	0x01e71f41,
+	/* Pin Complex */
+	0x01f71cf0,
+	0x01f71d11,
+	0x01f71e11,
+	0x01f71f41,
+};
+
+/*
+ * This needs to be in ROM since if we put it in CAR, FSP init loses it when
+ * it drops CAR.
+ *
+ * VerbTable: (RealTek ALC262)
+ * Revision ID = 0xFF, support all steps
+ * Codec Verb Table For AZALIA
+ * Codec Address: CAd value (0/1/2)
+ * Codec Vendor: 0x10EC0262
+ */
+static const struct azalia_verb_table azalia_verb_table[] = {
+	{
+		{
+			0x10ec0262,
+			0x0000,
+			0xff,
+			0x01,
+			0x000b,
+			0x0002,
+		},
+		verb_table_data13
+	}
+};
+
+static const struct azalia_config azalia_config = {
+	.pme_enable = 1,
+	.docking_supported = 1,
+	.docking_attached = 0,
+	.hdmi_codec_enable = 1,
+	.azalia_v_ci_enable = 1,
+	.rsvdbits = 0,
+	.verb_table_num = 1,
+	.verb_table = azalia_verb_table,
+	.reset_wait_timer_ms = 300
+};
+
+void update_fsp_azalia_configs(const struct azalia_config **azalia)
+{
+	*azalia = &azalia_config;
+}
 
 int board_early_init_f(void)
 {

board/compulab/cm_t35/cm_t35.c

@@ -452,6 +452,7 @@ static int handle_mac_address(void)
  * Routine: board_eth_init
  * Description: initialize module and base-board Ethernet chips
  */
+#define SB_T35_SMC911X_BASE	(CONFIG_SMC911X_BASE + SZ_16M)
 int board_eth_init(bd_t *bis)
 {
 	int rc = 0, rc1 = 0;
@@ -460,7 +461,7 @@ int board_eth_init(bd_t *bis)
 	if (rc1)
 		printf("No MAC address found! ");
 
-	rc1 = cl_omap3_smc911x_init(0, 5, CM_T3X_SMC911X_BASE,
+	rc1 = cl_omap3_smc911x_init(0, 5, CONFIG_SMC911X_BASE,
 				    cm_t3x_reset_net_chip, -EINVAL);
 	if (rc1 > 0)
 		rc++;

board/freescale/ls1088a/eth_ls1088aqds.c

@@ -634,6 +634,7 @@ int board_eth_init(bd_t *bis)
 	for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
 		switch (wriop_get_enet_if(i)) {
 		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_ID:
 			ls1088a_handle_phy_interface_rgmii(i);
 			break;
 		case PHY_INTERFACE_MODE_QSGMII:

board/ti/sdp4430/cmd_bat.c

@@ -39,4 +39,4 @@ U_BOOT_CMD(
 	"bat startcharge - start charging via USB\n"
 	"bat stopcharge - stop charging\n"
 );
-#endif /* CONFIG_BAT_CMD */
+#endif /* CONFIG_CMD_BAT */

cmd/fastboot/Kconfig

@@ -81,6 +81,16 @@ config FASTBOOT_FLASH_MMC_DEV
 	  regarding the non-volatile storage device. Define this to
 	  the eMMC device that fastboot should use to store the image.
 
+config FASTBOOT_FLASH_NAND_DEV
+	int "Define FASTBOOT NAND FLASH default device"
+	depends on FASTBOOT_FLASH && NAND
+	depends on CMD_MTDPARTS
+	default 0 if ARCH_SUNXI && NAND_SUNXI
+	help
+	  The fastboot "flash" command requires additional information
+	  regarding the non-volatile storage device. Define this to
+	  the NAND device that fastboot should use to store the image.
+
 config FASTBOOT_GPT_NAME
 	string "Target name for updating GPT"
 	depends on FASTBOOT_FLASH

cmd/gpt.c

@@ -282,14 +282,14 @@ static int create_gpt_partitions_list(int numparts, const char *guid,
 		strcat(partitions_list, "name=");
 		strncat(partitions_list, (const char *)curr->gpt_part_info.name,
 			PART_NAME_LEN + 1);
-		strcat(partitions_list, ",start=");
-		prettyprint_part_size(partstr, (unsigned long)curr->gpt_part_info.start,
-				      (unsigned long) curr->gpt_part_info.blksz);
+		sprintf(partstr, ",start=0x%llx",
+			(unsigned long long)curr->gpt_part_info.start *
+					    curr->gpt_part_info.blksz);
 		/* one extra byte for NULL */
 		strncat(partitions_list, partstr, PART_NAME_LEN + 1);
-		strcat(partitions_list, ",size=");
-		prettyprint_part_size(partstr, curr->gpt_part_info.size,
-				      curr->gpt_part_info.blksz);
+		sprintf(partstr, ",size=0x%llx",
+			(unsigned long long)curr->gpt_part_info.size *
+					    curr->gpt_part_info.blksz);
 		strncat(partitions_list, partstr, PART_NAME_LEN + 1);
 
 		strcat(partitions_list, ",uuid=");

configs/Bananapi_m2m_defconfig

@@ -0,0 +1,20 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_CONS_INDEX=1
+CONFIG_MACH_SUN8I_A33=y
+CONFIG_DRAM_CLK=600
+CONFIG_DRAM_ZQ=15291
+CONFIG_DRAM_ODT_EN=y
+CONFIG_MMC0_CD_PIN="PB4"
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_USB0_ID_DET="PH8"
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-r16-bananapi-m2m"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_PARTITION_UUIDS is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_MUSB_GADGET=y

configs/MPC8536DS_36BIT_defconfig

@@ -1,5 +1,4 @@
 CONFIG_PPC=y
-CONFIG_VIDEO=y
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_MPC8536DS=y
@@ -35,4 +34,5 @@ CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
+CONFIG_VIDEO=y
 CONFIG_OF_LIBFDT=y

configs/MPC8536DS_SDCARD_defconfig

@@ -1,5 +1,4 @@
 CONFIG_PPC=y
-CONFIG_VIDEO=y
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_MPC8536DS=y
@@ -34,4 +33,5 @@ CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
+CONFIG_VIDEO=y
 CONFIG_OF_LIBFDT=y

configs/MPC8536DS_SPIFLASH_defconfig

@@ -1,5 +1,4 @@
 CONFIG_PPC=y
-CONFIG_VIDEO=y
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_MPC8536DS=y
@@ -34,4 +33,5 @@ CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
+CONFIG_VIDEO=y
 CONFIG_OF_LIBFDT=y

configs/MPC8536DS_defconfig

@@ -1,5 +1,4 @@
 CONFIG_PPC=y
-CONFIG_VIDEO=y
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_MPC8536DS=y
@@ -34,4 +33,5 @@ CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
+CONFIG_VIDEO=y
 CONFIG_OF_LIBFDT=y

configs/MPC8544DS_defconfig

@@ -1,5 +1,4 @@
 CONFIG_PPC=y
-CONFIG_VIDEO=y
 CONFIG_MPC85xx=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_MPC8544DS=y
@@ -31,4 +30,5 @@ CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_PCI=y
 CONFIG_USB_STORAGE=y
+CONFIG_VIDEO=y
 CONFIG_OF_LIBFDT=y

configs/MPC8572DS_36BIT_defconfig

@@ -1,5 +1,4 @@
 CONFIG_PPC=y
-CONFIG_VIDEO=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_MPC8572DS=y
 CONFIG_PHYS_64BIT=y
@@ -30,4 +29,5 @@ CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_PCI=y
 CONFIG_USB_STORAGE=y
+CONFIG_VIDEO=y
 CONFIG_OF_LIBFDT=y

configs/MPC8572DS_defconfig

@@ -1,5 +1,4 @@
 CONFIG_PPC=y
-CONFIG_VIDEO=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_MPC8572DS=y
 CONFIG_FIT=y
@@ -29,4 +28,5 @@ CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_PCI=y
 CONFIG_USB_STORAGE=y
+CONFIG_VIDEO=y
 CONFIG_OF_LIBFDT=y

configs/MPC8610HPCD_defconfig

@@ -1,5 +1,4 @@
 CONFIG_PPC=y
-CONFIG_VIDEO=y
 CONFIG_MPC86xx=y
 CONFIG_TARGET_MPC8610HPCD=y
 CONFIG_OF_BOARD_SETUP=y
@@ -23,4 +22,5 @@ CONFIG_SCSI=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_KEYBOARD=y
+CONFIG_VIDEO=y
 CONFIG_OF_LIBFDT=y

configs/MPC8641HPCN_36BIT_defconfig

@@ -1,5 +1,4 @@
 CONFIG_PPC=y
-CONFIG_VIDEO=y
 CONFIG_MPC86xx=y
 CONFIG_TARGET_MPC8641HPCN=y
 CONFIG_PHYS_64BIT=y
@@ -22,4 +21,5 @@ CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_KEYBOARD=y
+CONFIG_VIDEO=y
 CONFIG_OF_LIBFDT=y

configs/MPC8641HPCN_defconfig

@@ -1,5 +1,4 @@
 CONFIG_PPC=y
-CONFIG_VIDEO=y
 CONFIG_MPC86xx=y
 CONFIG_TARGET_MPC8641HPCN=y
 CONFIG_OF_BOARD_SETUP=y
@@ -22,4 +21,5 @@ CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_KEYBOARD=y
+CONFIG_VIDEO=y
 CONFIG_OF_LIBFDT=y

configs/T1024QDS_DDR4_SECURE_BOOT_defconfig

@@ -1,6 +1,5 @@
 CONFIG_PPC=y
 CONFIG_SECURE_BOOT=y
-CONFIG_VIDEO=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1024QDS=y
 # CONFIG_SYS_MALLOC_F is not set
@@ -41,6 +40,7 @@ CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
+CONFIG_VIDEO=y
 CONFIG_RSA=y
 CONFIG_SPL_RSA=y
 CONFIG_RSA_SOFTWARE_EXP=y

configs/T1024QDS_DDR4_defconfig

@@ -1,5 +1,4 @@
 CONFIG_PPC=y
-CONFIG_VIDEO=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1024QDS=y
 CONFIG_FIT=y
@@ -37,4 +36,5 @@ CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
+CONFIG_VIDEO=y
 CONFIG_OF_LIBFDT=y

configs/T1024QDS_NAND_defconfig

@@ -4,7 +4,6 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_VIDEO=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1024QDS=y
 CONFIG_FIT=y
@@ -52,4 +51,5 @@ CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
+CONFIG_VIDEO=y
 CONFIG_OF_LIBFDT=y

configs/T1024QDS_SDCARD_defconfig

@@ -4,7 +4,6 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_VIDEO=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1024QDS=y
 CONFIG_FIT=y
@@ -51,4 +50,5 @@ CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
+CONFIG_VIDEO=y
 CONFIG_OF_LIBFDT=y

configs/T1024QDS_SECURE_BOOT_defconfig

@@ -1,6 +1,5 @@
 CONFIG_PPC=y
 CONFIG_SECURE_BOOT=y
-CONFIG_VIDEO=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1024QDS=y
 # CONFIG_SYS_MALLOC_F is not set
@@ -42,6 +41,7 @@ CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
+CONFIG_VIDEO=y
 CONFIG_RSA=y
 CONFIG_SPL_RSA=y
 CONFIG_RSA_SOFTWARE_EXP=y

configs/T1024QDS_SPIFLASH_defconfig

@@ -5,7 +5,6 @@ CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_VIDEO=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1024QDS=y
 CONFIG_FIT=y
@@ -52,4 +51,5 @@ CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
+CONFIG_VIDEO=y
 CONFIG_OF_LIBFDT=y

configs/T1024QDS_defconfig

@@ -1,5 +1,4 @@
 CONFIG_PPC=y
-CONFIG_VIDEO=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1024QDS=y
 CONFIG_FIT=y
@@ -41,4 +40,5 @@ CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
+CONFIG_VIDEO=y
 CONFIG_OF_LIBFDT=y

configs/T1040QDS_DDR4_defconfig

@@ -1,5 +1,4 @@
 CONFIG_PPC=y
-CONFIG_VIDEO=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1040QDS=y
 CONFIG_FIT=y
@@ -41,4 +40,5 @@ CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
+CONFIG_VIDEO=y
 CONFIG_OF_LIBFDT=y

configs/T1040QDS_SECURE_BOOT_defconfig

@@ -1,6 +1,5 @@
 CONFIG_PPC=y
 CONFIG_SECURE_BOOT=y
-CONFIG_VIDEO=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1040QDS=y
 # CONFIG_SYS_MALLOC_F is not set
@@ -43,6 +42,7 @@ CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
+CONFIG_VIDEO=y
 CONFIG_RSA=y
 CONFIG_SPL_RSA=y
 CONFIG_RSA_SOFTWARE_EXP=y

configs/T1040QDS_defconfig

@@ -1,5 +1,4 @@
 CONFIG_PPC=y
-CONFIG_VIDEO=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1040QDS=y
 CONFIG_FIT=y
@@ -42,4 +41,5 @@ CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
+CONFIG_VIDEO=y
 CONFIG_OF_LIBFDT=y

configs/T1042D4RDB_NAND_defconfig

@@ -4,7 +4,6 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_VIDEO=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1042D4RDB=y
 CONFIG_FIT=y
@@ -48,5 +47,6 @@ CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
+CONFIG_VIDEO=y
 CONFIG_CFB_CONSOLE_ANSI=y
 CONFIG_OF_LIBFDT=y

configs/T1042D4RDB_SDCARD_defconfig

@@ -4,7 +4,6 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_VIDEO=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1042D4RDB=y
 CONFIG_FIT=y
@@ -47,5 +46,6 @@ CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
+CONFIG_VIDEO=y
 CONFIG_CFB_CONSOLE_ANSI=y
 CONFIG_OF_LIBFDT=y

configs/T1042D4RDB_SECURE_BOOT_defconfig

@@ -1,6 +1,5 @@
 CONFIG_PPC=y
 CONFIG_SECURE_BOOT=y
-CONFIG_VIDEO=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1042D4RDB=y
 # CONFIG_SYS_MALLOC_F is not set
@@ -38,6 +37,7 @@ CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
+CONFIG_VIDEO=y
 CONFIG_CFB_CONSOLE_ANSI=y
 CONFIG_RSA=y
 CONFIG_SPL_RSA=y

configs/T1042D4RDB_SPIFLASH_defconfig

@@ -5,7 +5,6 @@ CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_VIDEO=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1042D4RDB=y
 CONFIG_FIT=y
@@ -48,5 +47,6 @@ CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
+CONFIG_VIDEO=y
 CONFIG_CFB_CONSOLE_ANSI=y
 CONFIG_OF_LIBFDT=y

configs/T1042D4RDB_defconfig

@@ -1,5 +1,4 @@
 CONFIG_PPC=y
-CONFIG_VIDEO=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1042D4RDB=y
 CONFIG_FIT=y
@@ -37,5 +36,6 @@ CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
+CONFIG_VIDEO=y
 CONFIG_CFB_CONSOLE_ANSI=y
 CONFIG_OF_LIBFDT=y

configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig

@@ -5,7 +5,6 @@ CONFIG_SECURE_BOOT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_VIDEO=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1042RDB_PI=y
 CONFIG_FIT=y
@@ -53,6 +52,7 @@ CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
+CONFIG_VIDEO=y
 CONFIG_CFB_CONSOLE_ANSI=y
 CONFIG_RSA=y
 CONFIG_SPL_RSA=y

configs/T1042RDB_PI_NAND_defconfig

@@ -4,7 +4,6 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_VIDEO=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1042RDB_PI=y
 CONFIG_FIT=y
@@ -50,5 +49,6 @@ CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
+CONFIG_VIDEO=y
 CONFIG_CFB_CONSOLE_ANSI=y
 CONFIG_OF_LIBFDT=y

configs/T1042RDB_PI_SDCARD_defconfig

@@ -4,7 +4,6 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_VIDEO=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1042RDB_PI=y
 CONFIG_FIT=y
@@ -49,5 +48,6 @@ CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
+CONFIG_VIDEO=y
 CONFIG_CFB_CONSOLE_ANSI=y
 CONFIG_OF_LIBFDT=y

configs/T1042RDB_PI_SPIFLASH_defconfig

@@ -5,7 +5,6 @@ CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_VIDEO=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1042RDB_PI=y
 CONFIG_FIT=y
@@ -50,5 +49,6 @@ CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
+CONFIG_VIDEO=y
 CONFIG_CFB_CONSOLE_ANSI=y
 CONFIG_OF_LIBFDT=y

configs/T1042RDB_PI_defconfig

@@ -1,5 +1,4 @@
 CONFIG_PPC=y
-CONFIG_VIDEO=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1042RDB_PI=y
 CONFIG_FIT=y
@@ -39,5 +38,6 @@ CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
+CONFIG_VIDEO=y
 CONFIG_CFB_CONSOLE_ANSI=y
 CONFIG_OF_LIBFDT=y

configs/am335x_baltos_defconfig

@@ -8,7 +8,6 @@ CONFIG_TARGET_AM335X_BALTOS=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
 CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_SPL_FAT_SUPPORT=y
 CONFIG_FIT_VERBOSE=y
@@ -48,6 +47,7 @@ CONFIG_CMD_UBI=y
 CONFIG_ISO_PARTITION=y
 CONFIG_MMC_OMAP_HS=y
 CONFIG_NAND=y
+CONFIG_NAND_OMAP_GPMC_PREFETCH=y
 CONFIG_PHYLIB=y
 CONFIG_SYS_NS16550=y
 CONFIG_OMAP3_SPI=y

configs/am335x_evm_defconfig

@@ -30,6 +30,7 @@ CONFIG_MISC=y
 CONFIG_DM_MMC=y
 CONFIG_MMC_OMAP_HS=y
 CONFIG_NAND=y
+CONFIG_NAND_OMAP_GPMC_PREFETCH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_PHYLIB=y

configs/am335x_evm_nor_defconfig

@@ -23,6 +23,7 @@ CONFIG_DFU_RAM=y
 CONFIG_MMC_OMAP_HS=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_NAND=y
+CONFIG_NAND_OMAP_GPMC_PREFETCH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_PHYLIB=y