Prepare v2018.01

Signed-off-by: Tom Rini <trini@konsulko.com>

MAINTAINERS

@@ -65,6 +65,14 @@ S:	Maintained
 L:	uboot-snps-arc@synopsys.com
 F:	drivers/gpio/hsdk-creg-gpio.c
 
+ARC HSDK CGU CLOCK
+M:	Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
+S:	Maintained
+L:	uboot-snps-arc@synopsys.com
+F:	drivers/clk/clk-hsdk-cgu.c
+F:	include/dt-bindings/clock/snps,hsdk-cgu.h
+F:	doc/device-tree-bindings/clock/snps,hsdk-cgu.txt
+
 ARM
 M:	Albert Aribaud <albert.u.boot@aribaud.net>
 S:	Maintained
@@ -310,6 +318,15 @@ S:	Maintained
 T:	git git://git.denx.de/u-boot-i2c.git
 F:	drivers/i2c/
 
+LOGGING
+M:	Simon Glass <sjg@chromium.org>
+S:	Maintained
+T:	git git://git.denx.de/u-boot.git
+F:	common/log.c
+F:	cmd/log.c
+F:	test/log/log_test.c
+F:	test/py/tests/test_log.py
+
 MICROBLAZE
 M:	Michal Simek <monstr@monstr.eu>
 S:	Maintained

Makefile

@@ -5,7 +5,7 @@
 VERSION = 2018
 PATCHLEVEL = 01
 SUBLEVEL =
-EXTRAVERSION = -rc1
+EXTRAVERSION =
 NAME =
 
 # *DOCUMENTATION*
@@ -1149,6 +1149,11 @@ u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.img u-boot.dtb FORCE
 endif
 
 ifneq ($(CONFIG_TEGRA),)
+ifneq ($(CONFIG_BINMAN),)
+u-boot-dtb-tegra.bin u-boot-tegra.bin u-boot-nodtb-tegra.bin: \
+		spl/u-boot-spl u-boot.bin FORCE
+	$(call if_changed,binman)
+else
 OBJCOPYFLAGS_u-boot-nodtb-tegra.bin = -O binary --pad-to=$(CONFIG_SYS_TEXT_BASE)
 u-boot-nodtb-tegra.bin: spl/u-boot-spl u-boot-nodtb.bin FORCE
 	$(call if_changed,pad_cat)
@@ -1159,6 +1164,7 @@ u-boot-tegra.bin: spl/u-boot-spl u-boot.bin FORCE
 
 u-boot-dtb-tegra.bin: u-boot-tegra.bin FORCE
 	$(call if_changed,copy)
+endif  # binman
 endif
 
 OBJCOPYFLAGS_u-boot-app.efi := $(OBJCOPYFLAGS_EFI)

README

@@ -1603,6 +1603,15 @@ The following options need to be configured:
 
 		See doc/README.link-local for more information.
 
+ - MAC address from environment variables
+
+		FDT_SEQ_MACADDR_FROM_ENV
+
+		Fix-up device tree with MAC addresses fetched sequentially from
+		environment variables. This config work on assumption that
+		non-usable ethernet node of device-tree are either not present
+		or their status has been marked as "disabled".
+
  - CDP Options:
 		CONFIG_CDP_DEVICE_ID
 
@@ -2168,16 +2177,6 @@ The following options need to be configured:
 		currently only supports clearing the memory.
 
 - Error Recovery:
-		CONFIG_PANIC_HANG
-
-		Define this variable to stop the system in case of a
-		fatal error, so that you have to reset it manually.
-		This is probably NOT a good idea for an embedded
-		system where you want the system to reboot
-		automatically as fast as possible, but it may be
-		useful during development since you can try to debug
-		the conditions that lead to the situation.
-
 		CONFIG_NET_RETRY_COUNT
 
 		This variable defines the number of retries for
@@ -5126,8 +5125,9 @@ Coding Standards:
 -----------------
 
 All contributions to U-Boot should conform to the Linux kernel
-coding style; see the file "Documentation/CodingStyle" and the script
-"scripts/Lindent" in your Linux kernel source directory.
+coding style; see the kernel coding style guide at
+https://www.kernel.org/doc/html/latest/process/coding-style.html, and the
+script "scripts/Lindent" in your Linux kernel source directory.
 
 Source files originating from a different project (for example the
 MTD subsystem) are generally exempt from these guidelines and are not

arch/arc/include/asm/arcregs.h

@@ -27,6 +27,12 @@
 #define ARC_AUX_IC_PTAG		0x1E
 #endif
 #define ARC_BCR_IC_BUILD	0x77
+#define AUX_AUX_CACHE_LIMIT		0x5D
+#define ARC_AUX_NON_VOLATILE_LIMIT	0x5E
+
+/* ICCM and DCCM auxiliary registers */
+#define ARC_AUX_DCCM_BASE	0x18	/* DCCM Base Addr ARCv2 */
+#define ARC_AUX_ICCM_BASE	0x208	/* ICCM Base Addr ARCv2 */
 
 /* Timer related auxiliary registers */
 #define ARC_AUX_TIMER0_CNT	0x21	/* Timer 0 count */
@@ -72,6 +78,9 @@
 /* gcc builtin sr needs reg param to be long immediate */
 #define write_aux_reg(reg_immed, val)		\
 		__builtin_arc_sr((unsigned int)val, reg_immed)
+
+/* ARCNUM [15:8] - field to identify each core in a multi-core system */
+#define CPU_ID_GET()	((read_aux_reg(ARC_AUX_IDENTITY) & 0xFF00) >> 8)
 #endif /* __ASSEMBLY__ */
 
 #endif /* _ASM_ARC_ARCREGS_H */

arch/arc/include/asm/gpio.h

@@ -0,0 +1 @@
+#include <asm-generic/gpio.h>

arch/arc/lib/cache.c

@@ -32,15 +32,15 @@
  * relocation but will be used after being zeroed.
  */
 int l1_line_sz __section(".data");
-int dcache_exists __section(".data");
-int icache_exists __section(".data");
+bool dcache_exists __section(".data") = false;
+bool icache_exists __section(".data") = false;
 
 #define CACHE_LINE_MASK		(~(l1_line_sz - 1))
 
 #ifdef CONFIG_ISA_ARCV2
 int slc_line_sz __section(".data");
-int slc_exists __section(".data");
-int ioc_exists __section(".data");
+bool slc_exists __section(".data") = false;
+bool ioc_exists __section(".data") = false;
 
 static unsigned int __before_slc_op(const int op)
 {
@@ -152,7 +152,7 @@ static void read_decode_cache_bcr_arcv2(void)
 	sbcr.word = read_aux_reg(ARC_BCR_SLC);
 	if (sbcr.fields.ver) {
 		slc_cfg.word = read_aux_reg(ARC_AUX_SLC_CONFIG);
-		slc_exists = 1;
+		slc_exists = true;
 		slc_line_sz = (slc_cfg.fields.lsz == 0) ? 128 : 64;
 	}
 
@@ -169,7 +169,7 @@ static void read_decode_cache_bcr_arcv2(void)
 
 	cbcr.word = read_aux_reg(ARC_BCR_CLUSTER);
 	if (cbcr.fields.c)
-		ioc_exists = 1;
+		ioc_exists = true;
 }
 #endif
 
@@ -190,7 +190,7 @@ void read_decode_cache_bcr(void)
 
 	ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD);
 	if (ibcr.fields.ver) {
-		icache_exists = 1;
+		icache_exists = true;
 		l1_line_sz = ic_line_sz = 8 << ibcr.fields.line_len;
 		if (!ic_line_sz)
 			panic("Instruction exists but line length is 0\n");
@@ -198,7 +198,7 @@ void read_decode_cache_bcr(void)
 
 	dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD);
 	if (dbcr.fields.ver){
-		dcache_exists = 1;
+		dcache_exists = true;
 		l1_line_sz = dc_line_sz = 16 << dbcr.fields.line_len;
 		if (!dc_line_sz)
 			panic("Data cache exists but line length is 0\n");

arch/arm/Kconfig

@@ -773,7 +773,7 @@ config ARCH_ZYNQMP
 	select SUPPORT_SPL
 	select CLK
 	select SPL_BOARD_INIT if SPL
-	select SPL_CLK
+	select SPL_CLK if SPL
 	select DM_USB if USB
 	imply FAT_WRITE
 
@@ -850,6 +850,7 @@ config TARGET_LS2080AQDS
 	select SUPPORT_SPL
 	select ARCH_MISC_INIT
 	imply SCSI
+	imply SCSI_AHCI
 	help
 	  Support for Freescale LS2080AQDS platform
 	  The LS2080A Development System (QDS) is a high-performance
@@ -865,6 +866,7 @@ config TARGET_LS2080ARDB
 	select SUPPORT_SPL
 	select ARCH_MISC_INIT
 	imply SCSI
+	imply SCSI_AHCI
 	help
 	  Support for Freescale LS2080ARDB platform.
 	  The LS2080A Reference design board (RDB) is a high-performance
@@ -926,6 +928,7 @@ config TARGET_LS1012ARDB
 	select ARM64
 	select BOARD_LATE_INIT
 	imply SCSI
+	imply SCSI_AHCI
 	help
 	  Support for Freescale LS1012ARDB platform.
 	  The LS1012A Reference design board (RDB) is a high-performance

arch/arm/config.mk

@@ -136,10 +136,12 @@ endif
 # limit ourselves to the sections we want in the .bin.
 ifdef CONFIG_ARM64
 OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .data \
-		-j .u_boot_list -j .rela.dyn -j .got -j .got.plt
+		-j .u_boot_list -j .rela.dyn -j .got -j .got.plt \
+		-j .binman_sym_table
 else
 OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .hash \
-		-j .data -j .got -j .got.plt -j .u_boot_list -j .rel.dyn
+		-j .data -j .got -j .got.plt -j .u_boot_list -j .rel.dyn \
+		-j .binman_sym_table
 endif
 
 # if a dtb section exists we always have to include it

arch/arm/cpu/armv7/ls102xa/Kconfig

@@ -20,6 +20,7 @@ config ARCH_LS1021A
 	select SYS_FSL_SEC_COMPAT_5
 	select SYS_FSL_SEC_LE
 	imply SCSI
+	imply SCSI_AHCI
 	imply CMD_PCI
 
 menu "LS102xA architecture"

arch/arm/cpu/armv8/fsl-layerscape/Kconfig

@@ -5,8 +5,13 @@ config ARCH_LS1012A
 	select SYS_FSL_DDR_BE
 	select SYS_FSL_MMDC
 	select SYS_FSL_ERRATUM_A010315
+	select SYS_FSL_ERRATUM_A009798
+	select SYS_FSL_ERRATUM_A008997
+	select SYS_FSL_ERRATUM_A009007
+	select SYS_FSL_ERRATUM_A009008
 	select ARCH_EARLY_INIT_R
 	select BOARD_EARLY_INIT_F
+	imply PANIC_HANG
 
 config ARCH_LS1043A
 	bool
@@ -31,6 +36,7 @@ config ARCH_LS1043A
 	select ARCH_EARLY_INIT_R
 	select BOARD_EARLY_INIT_F
 	imply SCSI
+	imply SCSI_AHCI
 	imply CMD_PCI
 
 config ARCH_LS1046A
@@ -57,6 +63,7 @@ config ARCH_LS1046A
 	select ARCH_EARLY_INIT_R
 	select BOARD_EARLY_INIT_F
 	imply SCSI
+	imply SCSI_AHCI
 
 config ARCH_LS1088A
 	bool
@@ -85,6 +92,7 @@ config ARCH_LS1088A
 	select ARCH_EARLY_INIT_R
 	select BOARD_EARLY_INIT_F
 	imply SCSI
+	imply PANIC_HANG
 
 config ARCH_LS2080A
 	bool
@@ -123,6 +131,7 @@ config ARCH_LS2080A
 	select SYS_FSL_ERRATUM_A009203
 	select ARCH_EARLY_INIT_R
 	select BOARD_EARLY_INIT_F
+	imply PANIC_HANG
 
 config FSL_LSCH2
 	bool
@@ -244,6 +253,7 @@ config SYS_LS_PPA_ESBC_ADDR
 	default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A
 	default 0x20680000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A
 	default 0x580680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
+	default 0x20680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1088A
 	default 0x680000 if SYS_LS_PPA_FW_IN_MMC
 	default 0x680000 if SYS_LS_PPA_FW_IN_NAND
 	help

arch/arm/cpu/armv8/fsl-layerscape/cpu.c

@@ -29,6 +29,7 @@
 #include <fsl_ddr.h>
 #endif
 #include <asm/arch/clock.h>
+#include <hwconfig.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -494,6 +495,41 @@ static inline int check_psci(void)
 	return 0;
 }
 
+static void config_core_prefetch(void)
+{
+	char *buf = NULL;
+	char buffer[HWCONFIG_BUFFER_SIZE];
+	const char *prefetch_arg = NULL;
+	size_t arglen;
+	unsigned int mask;
+	struct pt_regs regs;
+
+	if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
+		buf = buffer;
+
+	prefetch_arg = hwconfig_subarg_f("core_prefetch", "disable",
+					 &arglen, buf);
+
+	if (prefetch_arg) {
+		mask = simple_strtoul(prefetch_arg, NULL, 0) & 0xff;
+		if (mask & 0x1) {
+			printf("Core0 prefetch can't be disabled\n");
+			return;
+		}
+
+#define SIP_PREFETCH_DISABLE_64 0xC200FF13
+		regs.regs[0] = SIP_PREFETCH_DISABLE_64;
+		regs.regs[1] = mask;
+		smc_call(&regs);
+
+		if (regs.regs[0])
+			printf("Prefetch disable config failed for mask ");
+		else
+			printf("Prefetch disable config passed for mask ");
+		printf("0x%x\n", mask);
+	}
+}
+
 int arch_early_init_r(void)
 {
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
@@ -502,8 +538,8 @@ int arch_early_init_r(void)
 	 * erratum A009635 is valid only for LS2080A SoC and
 	 * its personalitiesi
 	 */
-	svr_dev_id = get_svr() >> 16;
-	if (svr_dev_id == SVR_DEV_LS2080A)
+	svr_dev_id = get_svr();
+	if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
 		erratum_a009635();
 #endif
 #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR)
@@ -521,6 +557,8 @@ int arch_early_init_r(void)
 	fsl_rgmii_init();
 #endif
 
+	config_core_prefetch();
+
 #ifdef CONFIG_SYS_HAS_SERDES
 	fsl_serdes_init();
 #endif
@@ -566,8 +604,8 @@ int timer_init(void)
 	 * For LS2080A SoC and its personalities, timer controller
 	 * offset is different
 	 */
-	svr_dev_id = get_svr() >> 16;
-	if (svr_dev_id == SVR_DEV_LS2080A)
+	svr_dev_id = get_svr();
+	if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
 		cntcr = (u32 *)SYS_FSL_LS2080A_LS2085A_TIMER_ADDR;
 
 #endif

arch/arm/cpu/armv8/fsl-layerscape/doc/README.core_prefetch

@@ -0,0 +1,20 @@
+Core instruction prefetch disable
+---------------------------------
+To disable instruction prefetch of core; hwconfig needs to be updated.
+for e.g.
+setenv hwconfig 'fsl_ddr:bank_intlv=auto;core_prefetch:disable=0x02'
+
+Here 0x02 can be replaced with any valid value except Mask[0] bit. It
+represents 64 bit mask. The 64-bit Mask has one bit for each core.
+Mask[0] = core0
+Mask[1] = core1
+Mask[2] = core2
+etc
+If the bit is set ('b1) in the mask, then prefetch is disabled for
+that core when it is released from reset.
+
+core0 prefetch should not be disabled i.e. Mask[0] should never be set.
+Setting Mask[0] may lead to undefined behavior.
+
+Once disabled, prefetch remains disabled until the next reset.
+There is no function to re-enable prefetch.

arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3

@@ -154,8 +154,8 @@ Booting from NAND
 -------------------
 Booting from NAND requires two images, RCW and u-boot-with-spl.bin.
 The difference between NAND boot RCW image and NOR boot image is the PBI
-command sequence. Below is one example for PBI commands for QDS which uses
-NAND device with 2KB/page, block size 128KB.
+command sequence. Below is one example for PBI commands for LS2085AQDS which
+uses NAND device with 2KB/page, block size 128KB.
 
 1) CCSR 4-byte write to 0x00e00404, data=0x00000000
 2) CCSR 4-byte write to 0x00e00400, data=0x1800a000
@@ -188,7 +188,7 @@ nand write <u-boot image in memory> 200000 <size of u-boot image>
 
 With these two images in NAND device, the board can boot from NAND.
 
-Another example for RDB boards,
+Another example for LS2085ARDB boards,
 
 1) CCSR 4-byte write to 0x00e00404, data=0x00000000
 2) CCSR 4-byte write to 0x00e00400, data=0x1800a000
@@ -201,6 +201,8 @@ nand write <u-boot image in memory> 80000 <size of u-boot image>
 Notice the difference from QDS is SRC, SRC_ADDR and the offset of u-boot image
 to match board NAND device with 4KB/page, block size 512KB.
 
+Note, LS2088A and LS1088A don't support booting from NAND.
+
 Booting from SD/eMMC
 -------------------
 Booting from SD/eMMC requires two images, RCW and u-boot-with-spl.bin.

arch/arm/cpu/armv8/fsl-layerscape/fdt.c

@@ -42,6 +42,33 @@ void ft_fixup_cpu(void *blob)
 	int addr_cells;
 	u64 val, core_id;
 	size_t *boot_code_size = &(__secondary_boot_code_size);
+	u32 mask = cpu_pos_mask();
+	int off_prev = -1;
+
+	off = fdt_path_offset(blob, "/cpus");
+	if (off < 0) {
+		puts("couldn't find /cpus node\n");
+		return;
+	}
+
+	fdt_support_default_count_cells(blob, off, &addr_cells, NULL);
+
+	off = fdt_node_offset_by_prop_value(blob, off_prev, "device_type",
+					    "cpu", 4);
+	while (off != -FDT_ERR_NOTFOUND) {
+		reg = (fdt32_t *)fdt_getprop(blob, off, "reg", 0);
+		if (reg) {
+			core_id = fdt_read_number(reg, addr_cells);
+			if (!test_bit(id_to_core(core_id), &mask)) {
+				fdt_del_node(blob, off);
+				off = off_prev;
+			}
+		}
+		off_prev = off;
+		off = fdt_node_offset_by_prop_value(blob, off_prev,
+						    "device_type", "cpu", 4);
+	}
+
 #if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && \
 	defined(CONFIG_SEC_FIRMWARE_ARMV8_PSCI)
 	int node;
@@ -145,7 +172,7 @@ static void fdt_fixup_gic(void *blob)
 
 	val = gur_in32(&gur->svr);
 
-	if (SVR_SOC_VER(val) != SVR_LS1043A) {
+	if (!IS_SVR_DEV(val, SVR_DEV(SVR_LS1043A))) {
 		align_64k = 1;
 	} else if (SVR_REV(val) != REV1_0) {
 		val = scfg_in32(&scfg->gic_align) & (0x01 << GIC_ADDR_BIT);
@@ -327,7 +354,7 @@ static void fdt_fixup_msi(void *blob)
 
 	rev = gur_in32(&gur->svr);
 
-	if (SVR_SOC_VER(rev) != SVR_LS1043A)
+	if (!IS_SVR_DEV(rev, SVR_DEV(SVR_LS1043A)))
 		return;
 
 	rev = SVR_REV(rev);

arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S

@@ -37,9 +37,8 @@ ENTRY(get_gic_offset)
 	ldr     x2, =DCFG_CCSR_SVR
 	ldr	w2, [x2]
 	rev	w2, w2
-	mov	w3, w2
-	ands	w3, w3, #SVR_WO_E << 8
-	mov	w4, #SVR_LS1043A << 8
+	lsr	w3, w2, #16
+	ldr	w4, =SVR_DEV(SVR_LS1043A)
 	cmp	w3, w4
 	b.ne	1f
 	ands	w2, w2, #0xff
@@ -92,7 +91,7 @@ ENTRY(lowlevel_init)
 	 */
 	bl	get_svr
 	lsr	w0, w0, #16
-	ldr	w1, =SVR_DEV_LS2080A
+	ldr	w1, =SVR_DEV(SVR_LS2080A)
 	cmp	w0, w1
 	b.eq	1f
 
@@ -224,7 +223,7 @@ ENTRY(lowlevel_init)
 	 */
 	bl	get_svr
 	lsr	w0, w0, #16
-	ldr	w1, =SVR_DEV_LS2080A
+	ldr	w1, =SVR_DEV(SVR_LS2080A)
 	cmp	w0, w1
 	b.eq	1f
 

arch/arm/cpu/armv8/fsl-layerscape/soc.c

@@ -66,10 +66,13 @@ static void erratum_a009008(void)
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009008
 	u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
 
-#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
+	defined(CONFIG_ARCH_LS1012A)
 	set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB1);
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
 	set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB2);
 	set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB3);
+#endif
 #elif defined(CONFIG_ARCH_LS2080A)
 	set_usb_txvreftune(scfg, SCFG_USB3PRM1CR);
 #endif
@@ -87,17 +90,21 @@ static void erratum_a009798(void)
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009798
 	u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
 
-#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
+	defined(CONFIG_ARCH_LS1012A)
 	set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB1);
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
 	set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB2);
 	set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB3);
+#endif
 #elif defined(CONFIG_ARCH_LS2080A)
 	set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR);
 #endif
 #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
 }
 
-#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
+	defined(CONFIG_ARCH_LS1012A)
 static inline void set_usb_pcstxswingfull(u32 __iomem *scfg, u32 offset)
 {
 	scfg_clrsetbits32(scfg + offset / 4,
@@ -109,17 +116,21 @@ static inline void set_usb_pcstxswingfull(u32 __iomem *scfg, u32 offset)
 static void erratum_a008997(void)
 {
 #ifdef CONFIG_SYS_FSL_ERRATUM_A008997
-#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
+	defined(CONFIG_ARCH_LS1012A)
 	u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
 
 	set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB1);
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
 	set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB2);
 	set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB3);
 #endif
+#endif
 #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
 }
 
-#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
+	defined(CONFIG_ARCH_LS1012A)
 
 #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy)	\
 	out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1);	\
@@ -139,16 +150,18 @@ static void erratum_a008997(void)
 
 static void erratum_a009007(void)
 {
-#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
+	defined(CONFIG_ARCH_LS1012A)
 	void __iomem *usb_phy = (void __iomem *)SCFG_USB_PHY1;
 
 	PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
-
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
 	usb_phy = (void __iomem *)SCFG_USB_PHY2;
 	PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
 
 	usb_phy = (void __iomem *)SCFG_USB_PHY3;
 	PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
+#endif
 #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
 	void __iomem *dcsr = (void __iomem *)DCSR_BASE;
 

arch/arm/cpu/u-boot-spl.lds

@@ -36,6 +36,13 @@ SECTIONS
 		KEEP(*(SORT(.u_boot_list*)));
 	}
 
+	. = ALIGN(4);
+	.binman_sym_table : {
+		__binman_sym_start = .;
+		KEEP(*(SORT(.binman_sym*)));
+		__binman_sym_end = .;
+	}
+
 	. = ALIGN(4);
 
 	__image_copy_end = .;

arch/arm/dts/Makefile

@@ -324,7 +324,8 @@ dtb-$(CONFIG_MACH_SUN8I_A33) += \
 dtb-$(CONFIG_MACH_SUN8I_A83T) += \
 	sun8i-a83t-allwinner-h8homlet-v2.dtb \
 	sun8i-a83t-bananapi-m3.dtb \
-	sun8i-a83t-cubietruck-plus.dtb
+	sun8i-a83t-cubietruck-plus.dtb \
+	sun8i-a83t-tbs-a711.dts
 dtb-$(CONFIG_MACH_SUN8I_H3) += \
 	sun8i-h2-plus-orangepi-zero.dtb \
 	sun8i-h3-bananapi-m2-plus.dtb \
@@ -345,6 +346,7 @@ dtb-$(CONFIG_MACH_SUN8I_V3S) += \
 	sun8i-v3s-licheepi-zero.dtb
 dtb-$(CONFIG_MACH_SUN50I_H5) += \
 	sun50i-h5-nanopi-neo2.dtb \
+	sun50i-h5-nanopi-neo-plus2.dtb \
 	sun50i-h5-orangepi-pc2.dtb \
 	sun50i-h5-orangepi-prime.dtb \
 	sun50i-h5-orangepi-zero-plus2.dtb
@@ -393,7 +395,9 @@ dtb-$(CONFIG_RCAR_GEN3) += \
 	r8a7795-h3ulcb.dtb \
 	r8a7795-salvator-x.dtb \
 	r8a7796-m3ulcb.dtb \
-	r8a7796-salvator-x.dtb
+	r8a7796-salvator-x.dtb \
+	r8a77970-eagle.dtb \
+	r8a77995-draak.dtb
 
 dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \
 	keystone-k2l-evm.dtb \
@@ -430,6 +434,10 @@ dtb-$(CONFIG_TARGET_OMAP3_LOGIC) += \
 	logicpd-torpedo-37xx-devkit.dtb \
 	logicpd-som-lv-37xx-devkit.dtb
 
+dtb-$(CONFIG_TARGET_OMAP3_EVM) += \
+	omap3-evm-37xx.dtb \
+	omap3-evm.dtb
+
 dtb-$(CONFIG_TARGET_SAMA5D2_PTC_EK) += \
 	at91-sama5d2_ptc_ek.dtb
 

arch/arm/dts/exynos4.dtsi

@@ -28,31 +28,39 @@
 		reg = <0x10440000 0x1000>;
 	};
 
-	serial@13800000 {
+	gic: interrupt-controller@10490000 {
+		compatible = "arm,cortex-a9-gic";
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		cpu-offset = <0x4000>;
+		reg = <0x10490000 0x10000>, <0x10480000 0x10000>;
+	};
+
+	serial_0: serial@13800000 {
 		compatible = "samsung,exynos4210-uart";
 		reg = <0x13800000 0x3c>;
 		id = <0>;
 	};
 
-	serial@13810000 {
+	serail_1: serial@13810000 {
 		compatible = "samsung,exynos4210-uart";
 		reg = <0x13810000 0x3c>;
 		id = <1>;
 	};
 
-	serial@13820000 {
+	serial_2: serial@13820000 {
 		compatible = "samsung,exynos4210-uart";
 		reg = <0x13820000 0x3c>;
 		id = <2>;
 	};
 
-	serial@13830000 {
+	serial_3: serial@13830000 {
 		compatible = "samsung,exynos4210-uart";
 		reg = <0x13830000 0x3c>;
 		id = <3>;
 	};
 
-	serial@13840000 {
+	serial_4: serial@13840000 {
 		compatible = "samsung,exynos4210-uart";
 		reg = <0x13840000 0x3c>;
 		id = <4>;
@@ -63,6 +71,7 @@
 		#size-cells = <0>;
 		compatible = "samsung,s3c2440-i2c";
 		reg = <0x13860000 0x100>;
+		interrupt-parent = <&gic>;
 		interrupts = <0 56 0>;
 	};
 
@@ -71,6 +80,7 @@
 		#size-cells = <0>;
 		compatible = "samsung,s3c2440-i2c";
 		reg = <0x13870000 0x100>;
+		interrupt-parent = <&gic>;
 		interrupts = <1 57 0>;
 	};
 
@@ -79,6 +89,7 @@
 		#size-cells = <0>;
 		compatible = "samsung,s3c2440-i2c";
 		reg = <0x13880000 0x100>;
+		interrupt-parent = <&gic>;
 		interrupts = <2 58 0>;
 	};
 
@@ -87,6 +98,7 @@
 		#size-cells = <0>;
 		compatible = "samsung,s3c2440-i2c";
 		reg = <0x13890000 0x100>;
+		interrupt-parent = <&gic>;
 		interrupts = <3 59 0>;
 	};
 
@@ -95,6 +107,7 @@
 		#size-cells = <0>;
 		compatible = "samsung,s3c2440-i2c";
 		reg = <0x138a0000 0x100>;
+		interrupt-parent = <&gic>;
 		interrupts = <4 60 0>;
 	};
 
@@ -103,6 +116,7 @@
 		#size-cells = <0>;
 		compatible = "samsung,s3c2440-i2c";
 		reg = <0x138b0000 0x100>;
+		interrupt-parent = <&gic>;
 		interrupts = <5 61 0>;
 	};
 
@@ -111,6 +125,7 @@
 		#size-cells = <0>;
 		compatible = "samsung,s3c2440-i2c";
 		reg = <0x138c0000 0x100>;
+		interrupt-parent = <&gic>;
 		interrupts = <6 62 0>;
 	};
 
@@ -119,6 +134,7 @@
 		#size-cells = <0>;
 		compatible = "samsung,s3c2440-i2c";
 		reg = <0x138d0000 0x100>;
+		interrupt-parent = <&gic>;
 		interrupts = <7 63 0>;
 	};
 
@@ -127,6 +143,7 @@
 		#size-cells = <0>;
 		compatible = "samsung,exynos4412-sdhci";
 		reg = <0x12510000 0x1000>;
+		interrupt-parent = <&gic>;
 		interrupts = <0 75 0>;
 		status = "disabled";
 	};
@@ -136,6 +153,7 @@
 		#size-cells = <0>;
 		compatible = "samsung,exynos4412-sdhci";
 		reg = <0x12520000 0x1000>;
+		interrupt-parent = <&gic>;
 		interrupts = <0 76 0>;
 		status = "disabled";
 	};
@@ -145,6 +163,7 @@
 		#size-cells = <0>;
 		compatible = "samsung,exynos4412-sdhci";
 		reg = <0x12530000 0x1000>;
+		interrupt-parent = <&gic>;
 		interrupts = <0 77 0>;
 		status = "disabled";
 	};
@@ -154,6 +173,7 @@
 		#size-cells = <0>;
 		compatible = "samsung,exynos4412-sdhci";
 		reg = <0x12540000 0x1000>;
+		interrupt-parent = <&gic>;
 		interrupts = <0 78 0>;
 		status = "disabled";
 	};
@@ -163,6 +183,7 @@
 		#size-cells = <0>;
 		compatible = "samsung,exynos4412-dw-mshc";
 		reg = <0x12550000 0x1000>;
+		interrupt-parent = <&gic>;
 		interrupts = <0 131 0>;
 		status = "disabled";
 	};

arch/arm/dts/exynos4210.dtsi

@@ -41,14 +41,6 @@
 		cpu-offset = <0x8000>;
 	};
 
-	combiner: interrupt-controller@10440000 {
-		samsung,combiner-nr = <16>;
-		interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
-			     <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
-			     <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
-			     <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
-	};
-
 	mct@10050000 {
 		compatible = "samsung,exynos4210-mct";
 		reg = <0x10050000 0x800>;
@@ -85,12 +77,14 @@
 	pinctrl_0: pinctrl@11400000 {
 		compatible = "samsung,exynos4210-pinctrl";
 		reg = <0x11400000 0x1000>;
+		interrupt-parent = <&gic>;
 		interrupts = <0 47 0>;
 	};
 
 	pinctrl_1: pinctrl@11000000 {
 		compatible = "samsung,exynos4210-pinctrl";
 		reg = <0x11000000 0x1000>;
+		interrupt-parent = <&gic>;
 		interrupts = <0 46 0>;
 
 		wakup_eint: wakeup-interrupt-controller {
@@ -118,6 +112,7 @@
 	g2d@12800000 {
 		compatible = "samsung,s5pv210-g2d";
 		reg = <0x12800000 0x1000>;
+		interrupt-parent = <&gic>;
 		interrupts = <0 89 0>;
 		clocks = <&clock 177>, <&clock 277>;
 		clock-names = "sclk_fimg2d", "fimg2d";
@@ -154,3 +149,12 @@
 		};
 	};
 };
+
+&combiner {
+	samsung,combiner-nr = <16>;
+	interrupt-parent = <&gic>;
+	interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
+		     <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
+		     <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
+		     <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
+};

arch/arm/dts/exynos4412-odroid.dts

@@ -15,211 +15,12 @@
 	compatible = "samsung,odroid", "samsung,exynos4412";
 
 	aliases {
-		i2c0 = "/i2c@13860000";
-		i2c1 = "/i2c@13870000";
-		i2c2 = "/i2c@13880000";
-		i2c3 = "/i2c@13890000";
-		i2c4 = "/i2c@138a0000";
-		i2c5 = "/i2c@138b0000";
-		i2c6 = "/i2c@138c0000";
-		i2c7 = "/i2c@138d0000";
 		serial0 = "/serial@13800000";
 		console = "/serial@13810000";
 		mmc0 = &mshc_0;
 		mmc1 = &sdhci2;
 	};
 
-	i2c@13860000 {
-		samsung,i2c-sda-delay = <100>;
-		samsung,i2c-slave-addr = <0x10>;
-		samsung,i2c-max-bus-freq = <100000>;
-		status = "okay";
-
-		max77686_pmic@09 {
-			compatible = "maxim,max77686";
-			interrupts = <7 0>;
-			reg = <0x09 0 0>;
-			#clock-cells = <1>;
-
-			voltage-regulators {
-				ldo1_reg: LDO1 {
-					regulator-name = "VDD_ALIVE_1.0V";
-					regulator-min-microvolt = <1000000>;
-					regulator-max-microvolt = <1000000>;
-				};
-
-				ldo2_reg: LDO2 {
-					regulator-name = "VDDQ_VM1M2_1.2V";
-					regulator-min-microvolt = <1200000>;
-					regulator-max-microvolt = <1200000>;
-				};
-
-				ldo3_reg: LDO3 {
-					regulator-name = "VCC_1.8V_AP";
-					regulator-min-microvolt = <1800000>;
-					regulator-max-microvolt = <1800000>;
-				};
-
-				ldo4_reg: LDO4 {
-					regulator-name = "VDDQ_MMC2_2.8V";
-					regulator-min-microvolt = <2800000>;
-					regulator-max-microvolt = <2800000>;
-				};
-
-				ldo5_reg: LDO5 {
-					regulator-name = "VDDQ_MMC0/1/3_1.8V";
-					regulator-min-microvolt = <1800000>;
-					regulator-max-microvolt = <1800000>;
-				};
-
-				ldo6_reg: LDO6 {
-					regulator-name = "VMPLL_1.0V";
-					regulator-min-microvolt = <1100000>;
-					regulator-max-microvolt = <1100000>;
-				};
-
-				ldo7_reg: LDO7 {
-					regulator-name = "VPLL_1.1V";
-					regulator-min-microvolt = <1100000>;
-					regulator-max-microvolt = <1100000>;
-				};
-
-				ldo8_reg: LDO8 {
-					regulator-name = "VDD_MIPI/HDMI_1.0V";
-					regulator-min-microvolt = <1000000>;
-					regulator-max-microvolt = <1000000>;
-				};
-
-				ldo10_reg: LDO10 {
-					regulator-name = "VDD_MIPI/HDMI_1.8V";
-					regulator-min-microvolt = <1800000>;
-					regulator-max-microvolt = <1800000>;
-				};
-
-				ldo11_reg: LDO11 {
-					regulator-name = "VDD_ABB1_1.8V";
-					regulator-min-microvolt = <1800000>;
-					regulator-max-microvolt = <1800000>;
-				};
-
-				ldo12_reg: LDO12 {
-					regulator-name = "VDD_UOTG_3.0V";
-					regulator-min-microvolt = <3000000>;
-					regulator-max-microvolt = <3000000>;
-				};
-
-				ldo13_reg: LDO13 {
-					regulator-name = "VDD_C2C_1.8V";
-					regulator-min-microvolt = <1800000>;
-					regulator-max-microvolt = <1800000>;
-				};
-
-				ldo14_reg: LDO14 {
-					regulator-name = "VDD_ABB02_1.8V";
-					regulator-min-microvolt = <1800000>;
-					regulator-max-microvolt = <1800000>;
-				};
-
-				ldo15_reg: LDO15 {
-					regulator-name = "VDD_HSIC/OTG_1.0V";
-					regulator-min-microvolt = <1000000>;
-					regulator-max-microvolt = <1000000>;
-				};
-
-				ldo16_reg: LDO16 {
-					regulator-name = "VDD_HSIC_1.8V";
-					regulator-min-microvolt = <1800000>;
-					regulator-max-microvolt = <1800000>;
-				};
-
-				ldo17_reg: LDO17 {
-					regulator-name = "VDDQ_CAM_1.2V";
-					regulator-min-microvolt = <1200000>;
-					regulator-max-microvolt = <1200000>;
-				};
-
-				ldo20_reg: LDO20 {
-					regulator-name = "VDDQ_EMMC_1.8V";
-					regulator-min-microvolt = <1800000>;
-					regulator-max-microvolt = <1800000>;
-					regulator-always-on;
-					regulator-boot-on;
-				};
-
-				ldo21_reg: LDO21 {
-					regulator-name = "TFLASH_2.8V";
-					regulator-min-microvolt = <2800000>;
-					regulator-max-microvolt = <2800000>;
-					regulator-always-on;
-					regulator-boot-on;
-				};
-
-				ldo22_reg: LDO22 {
-					regulator-name = "VDDQ_EMMC_2.8V";
-					regulator-min-microvolt = <2800000>;
-					regulator-max-microvolt = <2800000>;
-					regulator-always-on;
-					regulator-boot-on;
-				};
-
-				ldo25_reg: LDO25 {
-					regulator-compatible = "LDO25";
-					regulator-name = "VDDQ_LCD_3.0V";
-					regulator-min-microvolt = <3000000>;
-					regulator-max-microvolt = <3000000>;
-				};
-
-				buck1_reg: BUCK1 {
-					regulator-name = "VDD_MIF_1.0V";
-					regulator-min-microvolt = <8500000>;
-					regulator-max-microvolt = <1100000>;
-				};
-
-				buck2_reg: BUCK2 {
-					regulator-name = "VDD_ARM_1.0V";
-					regulator-min-microvolt = <850000>;
-					regulator-max-microvolt = <1500000>;
-				};
-
-				buck3_reg: BUCK3 {
-					regulator-name = "VDD_INT_1.1V";
-					regulator-min-microvolt = <850000>;
-					regulator-max-microvolt = <1150000>;
-				};
-
-				buck4_reg: BUCK4 {
-					regulator-name = "VDD_G3D_1.0V";
-					regulator-min-microvolt = <850000>;
-					regulator-max-microvolt = <1150000>;
-				};
-
-				buck5_reg: BUCK5 {
-					regulator-name = "VDDQ_AP_1.2V";
-					regulator-min-microvolt = <1200000>;
-					regulator-max-microvolt = <1200000>;
-				};
-
-				buck6_reg: BUCK6 {
-					regulator-name = "VCC_INL1/7_1.35V";
-					regulator-min-microvolt = <1350000>;
-					regulator-max-microvolt = <1350000>;
-				};
-
-				buck7_reg: BUCK7 {
-					regulator-name = "VCC_INL2/3/5_2.0V";
-					regulator-min-microvolt = <2000000>;
-					regulator-max-microvolt = <2000000>;
-				};
-
-				buck8_reg: BUCK8 {
-					regulator-name = "VCC_P3V3_2.85V";
-					regulator-min-microvolt = <750000>;
-					regulator-max-microvolt = <3300000>;
-				};
-			};
-		};
-	};
-
 	serial@13810000 {
 		status = "okay";
 	};
@@ -241,6 +42,198 @@
 	};
 };
 
+&i2c_0 {
+	samsung,i2c-sda-delay = <100>;
+	samsung,i2c-slave-addr = <0x10>;
+	samsung,i2c-max-bus-freq = <100000>;
+	status = "okay";
+
+	max77686: max77686_pmic@09 {
+		compatible = "maxim,max77686";
+		interrupt-parent = <&gpx3>;
+		interrupts = <7 0>;
+		reg = <0x09 0 0>;
+		#clock-cells = <1>;
+
+		voltage-regulators {
+			ldo1_reg: LDO1 {
+				regulator-name = "VDD_ALIVE_1.0V";
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+			};
+
+			ldo2_reg: LDO2 {
+				regulator-name = "VDDQ_VM1M2_1.2V";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+			};
+
+			ldo3_reg: LDO3 {
+				regulator-name = "VCC_1.8V_AP";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+			};
+
+			ldo4_reg: LDO4 {
+				regulator-name = "VDDQ_MMC2_2.8V";
+				regulator-min-microvolt = <2800000>;
+				regulator-max-microvolt = <2800000>;
+			};
+
+			ldo5_reg: LDO5 {
+				regulator-name = "VDDQ_MMC0/1/3_1.8V";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+			};
+
+			ldo6_reg: LDO6 {
+				regulator-name = "VMPLL_1.0V";
+				regulator-min-microvolt = <1100000>;
+				regulator-max-microvolt = <1100000>;
+			};
+
+			ldo7_reg: LDO7 {
+				regulator-name = "VPLL_1.1V";
+				regulator-min-microvolt = <1100000>;
+				regulator-max-microvolt = <1100000>;
+			};
+
+			ldo8_reg: LDO8 {
+				regulator-name = "VDD_MIPI/HDMI_1.0V";
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+			};
+
+			ldo10_reg: LDO10 {
+				regulator-name = "VDD_MIPI/HDMI_1.8V";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+			};
+
+			ldo11_reg: LDO11 {
+				regulator-name = "VDD_ABB1_1.8V";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+			};
+
+			ldo12_reg: LDO12 {
+				regulator-name = "VDD_UOTG_3.0V";
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+			};
+
+			ldo13_reg: LDO13 {
+				regulator-name = "VDD_C2C_1.8V";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+			};
+
+			ldo14_reg: LDO14 {
+				regulator-name = "VDD_ABB02_1.8V";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+			};
+
+			ldo15_reg: LDO15 {
+				regulator-name = "VDD_HSIC/OTG_1.0V";
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+			};
+
+			ldo16_reg: LDO16 {
+				regulator-name = "VDD_HSIC_1.8V";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+			};
+
+			ldo17_reg: LDO17 {
+				regulator-name = "VDDQ_CAM_1.2V";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+			};
+
+			ldo20_reg: LDO20 {
+				regulator-name = "VDDQ_EMMC_1.8V";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			ldo21_reg: LDO21 {
+				regulator-name = "TFLASH_2.8V";
+				regulator-min-microvolt = <2800000>;
+				regulator-max-microvolt = <2800000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			ldo22_reg: LDO22 {
+				regulator-name = "VDDQ_EMMC_2.8V";
+				regulator-min-microvolt = <2800000>;
+				regulator-max-microvolt = <2800000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			ldo25_reg: LDO25 {
+				regulator-compatible = "LDO25";
+				regulator-name = "VDDQ_LCD_3.0V";
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+			};
+
+			buck1_reg: BUCK1 {
+				regulator-name = "VDD_MIF_1.0V";
+				regulator-min-microvolt = <8500000>;
+				regulator-max-microvolt = <1100000>;
+			};
+
+			buck2_reg: BUCK2 {
+				regulator-name = "VDD_ARM_1.0V";
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <1500000>;
+			};
+
+			buck3_reg: BUCK3 {
+				regulator-name = "VDD_INT_1.1V";
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <1150000>;
+			};
+
+			buck4_reg: BUCK4 {
+				regulator-name = "VDD_G3D_1.0V";
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <1150000>;
+			};
+
+			buck5_reg: BUCK5 {
+				regulator-name = "VDDQ_AP_1.2V";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+			};
+
+			buck6_reg: BUCK6 {
+				regulator-name = "VCC_INL1/7_1.35V";
+				regulator-min-microvolt = <1350000>;
+				regulator-max-microvolt = <1350000>;
+			};
+
+			buck7_reg: BUCK7 {
+				regulator-name = "VCC_INL2/3/5_2.0V";
+				regulator-min-microvolt = <2000000>;
+				regulator-max-microvolt = <2000000>;
+			};
+
+			buck8_reg: BUCK8 {
+				regulator-name = "VCC_P3V3_2.85V";
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <3300000>;
+			};
+		};
+	};
+};
+
 &sdhci2 {
 	samsung,bus-width = <4>;
 	samsung,timing = <1 2 3>;

arch/arm/dts/exynos4412-trats2.dts

@@ -19,14 +19,6 @@
 	};
 
 	aliases {
-		i2c0 = "/i2c@13860000";
-		i2c1 = "/i2c@13870000";
-		i2c2 = "/i2c@13880000";
-		i2c3 = "/i2c@13890000";
-		i2c4 = "/i2c@138a0000";
-		i2c5 = "/i2c@138b0000";
-		i2c6 = "/i2c@138c0000";
-		i2c7 = "/i2c@138d0000";
 		i2c8 = &i2c_fg;
 		i2c9 = &i2c_max77693;
 		serial0 = "/serial@13800000";
@@ -51,320 +43,6 @@
 		status = "okay";
 	};
 
-	i2c@138d0000 {
-		samsung,i2c-sda-delay = <100>;
-		samsung,i2c-slave-addr = <0x10>;
-		samsung,i2c-max-bus-freq = <100000>;
-		status = "okay";
-
-		max77686_pmic@09 {
-			compatible = "maxim,max77686";
-			interrupts = <7 0>;
-			reg = <0x09 0 0>;
-			#clock-cells = <1>;
-
-			voltage-regulators {
-				ldo1_reg: LDO1 {
-					regulator-compatible = "LDO1";
-					regulator-name = "VALIVE_1.0V_AP";
-					regulator-min-microvolt = <1000000>;
-					regulator-max-microvolt = <1000000>;
-					regulator-always-on;
-					regulator-mem-on;
-				};
-
-				ldo2_reg: LDO2 {
-					regulator-compatible = "LDO2";
-					regulator-name = "VM1M2_1.2V_AP";
-					regulator-min-microvolt = <1200000>;
-					regulator-max-microvolt = <1200000>;
-					regulator-always-on;
-					regulator-mem-on;
-				};
-
-				ldo3_reg: LDO3 {
-					regulator-compatible = "LDO3";
-					regulator-name = "VCC_1.8V_AP";
-					regulator-min-microvolt = <1800000>;
-					regulator-max-microvolt = <1800000>;
-					regulator-always-on;
-					regulator-mem-on;
-				};
-
-				ldo4_reg: LDO4 {
-					regulator-compatible = "LDO4";
-					regulator-name = "VCC_2.8V_AP";
-					regulator-min-microvolt = <2800000>;
-					regulator-max-microvolt = <2800000>;
-					regulator-always-on;
-					regulator-mem-on;
-				};
-
-				ldo5_reg: LDO5 {
-					regulator-compatible = "LDO5";
-					regulator-name = "VCC_1.8V_IO";
-					regulator-min-microvolt = <1800000>;
-					regulator-max-microvolt = <1800000>;
-					regulator-always-on;
-					regulator-mem-on;
-				};
-
-				ldo6_reg: LDO6 {
-					regulator-compatible = "LDO6";
-					regulator-name = "VMPLL_1.0V_AP";
-					regulator-min-microvolt = <1000000>;
-					regulator-max-microvolt = <1000000>;
-					regulator-always-on;
-					regulator-mem-on;
-				};
-
-				ldo7_reg: LDO7 {
-					regulator-compatible = "LDO7";
-					regulator-name = "VPLL_1.0V_AP";
-					regulator-min-microvolt = <1000000>;
-					regulator-max-microvolt = <1000000>;
-					regulator-always-on;
-					regulator-mem-on;
-				};
-
-				ldo8_reg: LDO8 {
-					regulator-compatible = "LDO8";
-					regulator-name = "VMIPI_1.0V";
-					regulator-min-microvolt = <1000000>;
-					regulator-max-microvolt = <1000000>;
-					regulator-mem-off;
-				};
-
-				ldo9_reg: LDO9 {
-					regulator-compatible = "LDO9";
-					regulator-name = "CAM_ISP_MIPI_1.2V";
-					regulator-min-microvolt = <1200000>;
-					regulator-max-microvolt = <1200000>;
-					regulator-mem-idle;
-				};
-
-				ldo10_reg: LDO10 {
-					regulator-compatible = "LDO10";
-					regulator-name = "VMIPI_1.8V";
-					regulator-min-microvolt = <1800000>;
-					regulator-max-microvolt = <1800000>;
-					regulator-mem-off;
-				};
-
-				ldo11_reg: LDO11 {
-					regulator-compatible = "LDO11";
-					regulator-name = "VABB1_1.95V";
-					regulator-min-microvolt = <1950000>;
-					regulator-max-microvolt = <1950000>;
-					regulator-always-on;
-					regulator-mem-off;
-				};
-
-				ldo12_reg: LDO12 {
-					regulator-compatible = "LDO12";
-					regulator-name = "VUOTG_3.0V";
-					regulator-min-microvolt = <3000000>;
-					regulator-max-microvolt = <3000000>;
-					regulator-mem-off;
-				};
-
-				ldo13_reg: LDO13 {
-					regulator-compatible = "LDO13";
-					regulator-name = "NFC_AVDD_1.8V";
-					regulator-min-microvolt = <1800000>;
-					regulator-max-microvolt = <1800000>;
-					regulator-mem-idle;
-				};
-
-				ldo14_reg: LDO14 {
-					regulator-compatible = "LDO14";
-					regulator-name = "VABB2_1.95V";
-					regulator-min-microvolt = <1950000>;
-					regulator-max-microvolt = <1950000>;
-					regulator-always-on;
-					regulator-mem-off;
-				};
-
-				ldo15_reg: LDO15 {
-					regulator-compatible = "LDO15";
-					regulator-name = "VHSIC_1.0V";
-					regulator-min-microvolt = <1000000>;
-					regulator-max-microvolt = <1000000>;
-					regulator-mem-off;
-				};
-
-				ldo16_reg: LDO16 {
-					regulator-compatible = "LDO16";
-					regulator-name = "VHSIC_1.8V";
-					regulator-min-microvolt = <1800000>;
-					regulator-max-microvolt = <1800000>;
-					regulator-mem-off;
-				};
-
-				ldo17_reg: LDO17 {
-					regulator-compatible = "LDO17";
-					regulator-name = "CAM_SENSOR_CORE_1.2V";
-					regulator-min-microvolt = <1200000>;
-					regulator-max-microvolt = <1200000>;
-					regulator-mem-idle;
-				};
-
-				ldo18_reg: LDO18 {
-					regulator-compatible = "LDO18";
-					regulator-name = "CAM_ISP_SEN_IO_1.8V";
-					regulator-min-microvolt = <1800000>;
-					regulator-max-microvolt = <1800000>;
-					regulator-mem-idle;
-				};
-
-				ldo19_reg: LDO19 {
-					regulator-compatible = "LDO19";
-					regulator-name = "VT_CAM_1.8V";
-					regulator-min-microvolt = <1800000>;
-					regulator-max-microvolt = <1800000>;
-					regulator-mem-idle;
-				};
-
-				ldo20_reg: LDO20 {
-					regulator-compatible = "LDO20";
-					regulator-name = "VDDQ_PRE_1.8V";
-					regulator-min-microvolt = <1800000>;
-					regulator-max-microvolt = <1800000>;
-					regulator-mem-idle;
-				};
-
-				ldo21_reg: LDO21 {
-					regulator-compatible = "LDO21";
-					regulator-name = "VTF_2.8V";
-					regulator-min-microvolt = <2800000>;
-					regulator-max-microvolt = <2800000>;
-					regulator-mem-idle;
-				};
-
-				ldo22_reg: LDO22 {
-					regulator-compatible = "LDO22";
-					regulator-name = "VMEM_VDD_2.8V";
-					regulator-min-microvolt = <2800000>;
-					regulator-max-microvolt = <2800000>;
-					regulator-always-on;
-					regulator-mem-off;
-				};
-
-				ldo23_reg: LDO23 {
-					regulator-compatible = "LDO23";
-					regulator-name = "TSP_AVDD_3.3V";
-					regulator-min-microvolt = <3300000>;
-					regulator-max-microvolt = <3300000>;
-					regulator-mem-idle;
-				};
-
-				ldo24_reg: LDO24 {
-					regulator-compatible = "LDO24";
-					regulator-name = "TSP_VDD_1.8V";
-					regulator-min-microvolt = <1800000>;
-					regulator-max-microvolt = <1800000>;
-					regulator-mem-idle;
-				};
-
-				ldo25_reg: LDO25 {
-					regulator-compatible = "LDO25";
-					regulator-name = "LCD_VCC_3.3V";
-					regulator-min-microvolt = <2800000>;
-					regulator-max-microvolt = <2800000>;
-					regulator-mem-idle;
-				};
-
-				ldo26_reg: LDO26 {
-					regulator-compatible = "LDO26";
-					regulator-name = "MOTOR_VCC_3.0V";
-					regulator-min-microvolt = <3000000>;
-					regulator-max-microvolt = <3000000>;
-					regulator-mem-idle;
-				};
-
-				buck1_reg: BUCK1 {
-					regulator-compatible = "BUCK1";
-					regulator-name = "vdd_mif";
-					regulator-min-microvolt = <850000>;
-					regulator-max-microvolt = <1100000>;
-					regulator-always-on;
-					regulator-boot-on;
-					regulator-mem-off;
-				};
-
-				buck2_reg: BUCK2 {
-					regulator-compatible = "BUCK2";
-					regulator-name = "vdd_arm";
-					regulator-min-microvolt = <850000>;
-					regulator-max-microvolt = <1500000>;
-					regulator-always-on;
-					regulator-boot-on;
-					regulator-mem-off;
-				};
-
-				buck3_reg: BUCK3 {
-					regulator-compatible = "BUCK3";
-					regulator-name = "vdd_int";
-					regulator-min-microvolt = <850000>;
-					regulator-max-microvolt = <1150000>;
-					regulator-always-on;
-					regulator-boot-on;
-					regulator-mem-off;
-				};
-
-				buck4_reg: BUCK4 {
-					regulator-compatible = "BUCK4";
-					regulator-name = "vdd_g3d";
-					regulator-min-microvolt = <850000>;
-					regulator-max-microvolt = <1150000>;
-					regulator-boot-on;
-					regulator-mem-off;
-				};
-
-				buck5_reg: BUCK5 {
-					regulator-compatible = "BUCK5";
-					regulator-name = "VMEM_1.2V_AP";
-					regulator-min-microvolt = <1200000>;
-					regulator-max-microvolt = <1200000>;
-					regulator-always-on;
-				};
-
-				buck6_reg: BUCK6 {
-					regulator-compatible = "BUCK6";
-					regulator-name = "VCC_SUB_1.35V";
-					regulator-min-microvolt = <1350000>;
-					regulator-max-microvolt = <1350000>;
-					regulator-always-on;
-				};
-
-				buck7_reg: BUCK7 {
-					regulator-compatible = "BUCK7";
-					regulator-name = "VCC_SUB_2.0V";
-					regulator-min-microvolt = <2000000>;
-					regulator-max-microvolt = <2000000>;
-					regulator-always-on;
-				};
-
-				buck8_reg: BUCK8 {
-					regulator-compatible = "BUCK8";
-					regulator-name = "VMEM_VDDF_3.0V";
-					regulator-min-microvolt = <2850000>;
-					regulator-max-microvolt = <2850000>;
-					regulator-always-on;
-					regulator-mem-off;
-				};
-
-				buck9_reg: BUCK9 {
-					regulator-compatible = "BUCK9";
-					regulator-name = "CAM_ISP_CORE_1.2V";
-					regulator-min-microvolt = <1000000>;
-					regulator-max-microvolt = <1200000>;
-					regulator-mem-off;
-				};
-			};
-		};
-	};
-
 	fimd@11c00000 {
 		compatible = "samsung,exynos-fimd";
 		reg = <0x11c00000 0xa4>;
@@ -438,6 +116,321 @@
 	};
 };
 
+&i2c_7 {
+	samsung,i2c-sda-delay = <100>;
+	samsung,i2c-slave-addr = <0x10>;
+	samsung,i2c-max-bus-freq = <100000>;
+	status = "okay";
+
+	max77686: max77686_pmic@09 {
+		compatible = "maxim,max77686";
+		interrupt-parent = <&gpx0>;
+		interrupts = <7 0>;
+		reg = <0x09 0 0>;
+		#clock-cells = <1>;
+
+		voltage-regulators {
+			ldo1_reg: LDO1 {
+				regulator-compatible = "LDO1";
+				regulator-name = "VALIVE_1.0V_AP";
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-always-on;
+				regulator-mem-on;
+			};
+
+			ldo2_reg: LDO2 {
+				regulator-compatible = "LDO2";
+				regulator-name = "VM1M2_1.2V_AP";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-always-on;
+				regulator-mem-on;
+			};
+
+			ldo3_reg: LDO3 {
+				regulator-compatible = "LDO3";
+				regulator-name = "VCC_1.8V_AP";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+				regulator-mem-on;
+			};
+
+			ldo4_reg: LDO4 {
+				regulator-compatible = "LDO4";
+				regulator-name = "VCC_2.8V_AP";
+				regulator-min-microvolt = <2800000>;
+				regulator-max-microvolt = <2800000>;
+				regulator-always-on;
+				regulator-mem-on;
+			};
+
+			ldo5_reg: LDO5 {
+				regulator-compatible = "LDO5";
+				regulator-name = "VCC_1.8V_IO";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+				regulator-mem-on;
+			};
+
+			ldo6_reg: LDO6 {
+				regulator-compatible = "LDO6";
+				regulator-name = "VMPLL_1.0V_AP";
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-always-on;
+				regulator-mem-on;
+			};
+
+			ldo7_reg: LDO7 {
+				regulator-compatible = "LDO7";
+				regulator-name = "VPLL_1.0V_AP";
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-always-on;
+				regulator-mem-on;
+			};
+
+			ldo8_reg: LDO8 {
+				regulator-compatible = "LDO8";
+				regulator-name = "VMIPI_1.0V";
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-mem-off;
+			};
+
+			ldo9_reg: LDO9 {
+				regulator-compatible = "LDO9";
+				regulator-name = "CAM_ISP_MIPI_1.2V";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-mem-idle;
+			};
+
+			ldo10_reg: LDO10 {
+				regulator-compatible = "LDO10";
+				regulator-name = "VMIPI_1.8V";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-mem-off;
+			};
+
+			ldo11_reg: LDO11 {
+				regulator-compatible = "LDO11";
+				regulator-name = "VABB1_1.95V";
+				regulator-min-microvolt = <1950000>;
+				regulator-max-microvolt = <1950000>;
+				regulator-always-on;
+				regulator-mem-off;
+			};
+
+			ldo12_reg: LDO12 {
+				regulator-compatible = "LDO12";
+				regulator-name = "VUOTG_3.0V";
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-mem-off;
+			};
+
+			ldo13_reg: LDO13 {
+				regulator-compatible = "LDO13";
+				regulator-name = "NFC_AVDD_1.8V";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-mem-idle;
+			};
+
+			ldo14_reg: LDO14 {
+				regulator-compatible = "LDO14";
+				regulator-name = "VABB2_1.95V";
+				regulator-min-microvolt = <1950000>;
+				regulator-max-microvolt = <1950000>;
+				regulator-always-on;
+				regulator-mem-off;
+			};
+
+			ldo15_reg: LDO15 {
+				regulator-compatible = "LDO15";
+				regulator-name = "VHSIC_1.0V";
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-mem-off;
+			};
+
+			ldo16_reg: LDO16 {
+				regulator-compatible = "LDO16";
+				regulator-name = "VHSIC_1.8V";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-mem-off;
+			};
+
+			ldo17_reg: LDO17 {
+				regulator-compatible = "LDO17";
+				regulator-name = "CAM_SENSOR_CORE_1.2V";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-mem-idle;
+			};
+
+			ldo18_reg: LDO18 {
+				regulator-compatible = "LDO18";
+				regulator-name = "CAM_ISP_SEN_IO_1.8V";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-mem-idle;
+			};
+
+			ldo19_reg: LDO19 {
+				regulator-compatible = "LDO19";
+				regulator-name = "VT_CAM_1.8V";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-mem-idle;
+			};
+
+			ldo20_reg: LDO20 {
+				regulator-compatible = "LDO20";
+				regulator-name = "VDDQ_PRE_1.8V";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-mem-idle;
+			};
+
+			ldo21_reg: LDO21 {
+				regulator-compatible = "LDO21";
+				regulator-name = "VTF_2.8V";
+				regulator-min-microvolt = <2800000>;
+				regulator-max-microvolt = <2800000>;
+				regulator-mem-idle;
+			};
+
+			ldo22_reg: LDO22 {
+				regulator-compatible = "LDO22";
+				regulator-name = "VMEM_VDD_2.8V";
+				regulator-min-microvolt = <2800000>;
+				regulator-max-microvolt = <2800000>;
+				regulator-always-on;
+				regulator-mem-off;
+			};
+
+			ldo23_reg: LDO23 {
+				regulator-compatible = "LDO23";
+				regulator-name = "TSP_AVDD_3.3V";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-mem-idle;
+			};
+
+			ldo24_reg: LDO24 {
+				regulator-compatible = "LDO24";
+				regulator-name = "TSP_VDD_1.8V";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-mem-idle;
+			};
+
+			ldo25_reg: LDO25 {
+				regulator-compatible = "LDO25";
+				regulator-name = "LCD_VCC_3.3V";
+				regulator-min-microvolt = <2800000>;
+				regulator-max-microvolt = <2800000>;
+				regulator-mem-idle;
+			};
+
+			ldo26_reg: LDO26 {
+				regulator-compatible = "LDO26";
+				regulator-name = "MOTOR_VCC_3.0V";
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-mem-idle;
+			};
+
+			buck1_reg: BUCK1 {
+				regulator-compatible = "BUCK1";
+				regulator-name = "vdd_mif";
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <1100000>;
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-mem-off;
+			};
+
+			buck2_reg: BUCK2 {
+				regulator-compatible = "BUCK2";
+				regulator-name = "vdd_arm";
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <1500000>;
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-mem-off;
+			};
+
+			buck3_reg: BUCK3 {
+				regulator-compatible = "BUCK3";
+				regulator-name = "vdd_int";
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <1150000>;
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-mem-off;
+			};
+
+			buck4_reg: BUCK4 {
+				regulator-compatible = "BUCK4";
+				regulator-name = "vdd_g3d";
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <1150000>;
+				regulator-boot-on;
+				regulator-mem-off;
+			};
+
+			buck5_reg: BUCK5 {
+				regulator-compatible = "BUCK5";
+				regulator-name = "VMEM_1.2V_AP";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-always-on;
+			};
+
+			buck6_reg: BUCK6 {
+				regulator-compatible = "BUCK6";
+				regulator-name = "VCC_SUB_1.35V";
+				regulator-min-microvolt = <1350000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-always-on;
+			};
+
+			buck7_reg: BUCK7 {
+				regulator-compatible = "BUCK7";
+				regulator-name = "VCC_SUB_2.0V";
+				regulator-min-microvolt = <2000000>;
+				regulator-max-microvolt = <2000000>;
+				regulator-always-on;
+			};
+
+			buck8_reg: BUCK8 {
+				regulator-compatible = "BUCK8";
+				regulator-name = "VMEM_VDDF_3.0V";
+				regulator-min-microvolt = <2850000>;
+				regulator-max-microvolt = <2850000>;
+				regulator-always-on;
+				regulator-mem-off;
+			};
+
+			buck9_reg: BUCK9 {
+				regulator-compatible = "BUCK9";
+				regulator-name = "CAM_ISP_CORE_1.2V";
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-mem-off;
+			};
+		};
+	};
+};
+
 &sdhci0 {
 	samsung,bus-width = <8>;
 	samsung,timing = <1 3 3>;

arch/arm/dts/exynos4412.dtsi

@@ -21,18 +21,14 @@
 
 / {
 	compatible = "samsung,exynos4412";
-
-	gic: interrupt-controller@10490000 {
-		cpu-offset = <0x4000>;
-	};
-
-	interrupt-controller@10440000 {
-		samsung,combiner-nr = <20>;
-		interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
-			     <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
-			     <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
-			     <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
-			     <0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>;
-	};
-
+};
+
+&combiner {
+	samsung,combiner-nr = <20>;
+	interrupt-parent = <&gic>;
+	interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
+		     <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
+		     <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
+		     <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
+		     <0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>;
 };

arch/arm/dts/exynos4x12.dtsi

@@ -63,12 +63,14 @@
 	pinctrl_0: pinctrl@11400000 {
 		compatible = "samsung,exynos4x12-pinctrl";
 		reg = <0x11400000 0x1000>;
+		interrupt-parent = <&gic>;
 		interrupts = <0 47 0>;
 	};
 
 	pinctrl_1: pinctrl@11000000 {
 		compatible = "samsung,exynos4x12-pinctrl";
 		reg = <0x11000000 0x1000>;
+		interrupt-parent = <&gic>;
 		interrupts = <0 46 0>;
 
 		wakup_eint: wakeup-interrupt-controller {
@@ -88,12 +90,14 @@
 	pinctrl_3: pinctrl@106E0000 {
 		compatible = "samsung,exynos4x12-pinctrl";
 		reg = <0x106E0000 0x1000>;
+		interrupt-parent = <&gic>;
 		interrupts = <0 72 0>;
 	};
 
 	g2d@10800000 {
 		compatible = "samsung,exynos4212-g2d";
 		reg = <0x10800000 0x1000>;
+		interrupt-parent = <&gic>;
 		interrupts = <0 89 0>;
 		clocks = <&clock 177>, <&clock 277>;
 		clock-names = "sclk_fimg2d", "fimg2d";

arch/arm/dts/imx53.dtsi

@@ -23,10 +23,18 @@
 		serial1 = &uart2;
 	};
 
+	tzic: tz-interrupt-controller@fffc000 {
+		compatible = "fsl,imx53-tzic", "fsl,tzic";
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		reg = <0x0fffc000 0x4000>;
+	};
+
 	soc {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "simple-bus";
+		interrupt-parent = <&tzic>;
 		ranges;
 
 		aips@50000000 { /* AIPS1 */

arch/arm/dts/imx6q-cm-fx6.dts

@@ -3,15 +3,46 @@
  *
  * Author: Valentin Raevsky <valentin@compulab.co.il>
  *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
  *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
 #include "imx6q.dtsi"
 
 / {
@@ -31,6 +62,118 @@
 			linux,default-trigger = "heartbeat";
 		};
 	};
+
+	awnh387_pwrseq: pwrseq {
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_pwrseq>;
+		compatible = "mmc-pwrseq-sd8787";
+		powerdown-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>;
+		reset-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
+	};
+
+	reg_pcie_power_on_gpio: regulator-pcie-power-on-gpio {
+		compatible = "regulator-fixed";
+		regulator-name = "regulator-pcie-power-on-gpio";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio2 24 GPIO_ACTIVE_LOW>;
+	};
+
+	reg_usb_h1_vbus: usb_h1_vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "usb_h1_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	reg_usb_otg_vbus: usb_otg_vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "usb_otg_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	sound-analog {
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "On-board analog audio";
+		simple-audio-card,widgets =
+			"Headphone", "Headphone Jack",
+			"Line", "Line Out",
+			"Microphone", "Mic Jack",
+			"Line", "Line In";
+		simple-audio-card,routing =
+			"Headphone Jack", "RHPOUT",
+			"Headphone Jack", "LHPOUT",
+			"MICIN", "Mic Bias",
+			"Mic Bias", "Mic Jack";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,bitclock-master = <&sound_master>;
+		simple-audio-card,frame-master = <&sound_master>;
+		simple-audio-card,bitclock-inversion;
+
+		sound_master: simple-audio-card,cpu {
+			sound-dai = <&ssi2>;
+			system-clock-frequency = <2822400>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <&wm8731>;
+		};
+	};
+
+	sound-spdif {
+		compatible = "fsl,imx-audio-spdif";
+		model = "imx-spdif";
+		spdif-controller = <&spdif>;
+		spdif-out;
+		spdif-in;
+	};
+};
+
+/*
+ * The U-Boot: audio mux node has been removed because the required dt-bindings
+ * header file is not present in the U-Boot.
+ */
+
+&cpu0 {
+	/*
+	 * Although the imx6q fuse indicates that 1.2GHz operation is possible,
+	 * the module behaves unstable at this frequency. Hence, remove the
+	 * 1.2GHz operation point here.
+	 */
+	operating-points = <
+		/* kHz	uV */
+		996000	1250000
+		852000	1250000
+		792000	1175000
+		396000	975000
+	>;
+	fsl,soc-operating-points = <
+		/* ARM kHz	SOC-PU uV */
+		996000		1250000
+		852000		1250000
+		792000		1175000
+		396000		1175000
+	>;
+};
+
+&ecspi1 {
+	cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>, <&gpio3 19 GPIO_ACTIVE_HIGH>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi1>;
+	status = "okay";
+
+	m25p80@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "st,m25p", "jedec,spi-nor";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+	};
 };
 
 &fec {
@@ -46,58 +189,176 @@
 	status = "okay";
 };
 
-&iomuxc {
-	imx6q-cm-fx6 {
-		pinctrl_enet: enetgrp {
-			fsl,pins = <
-				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
-				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0
-				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0
-				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0
-				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0
-				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0
-				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b0b0
-				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b0b0
-				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b0b0
-				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b0b0
-				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b0b0
-				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b0b0
-				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
-				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
-				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
-				MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
-			>;
-		};
+&i2c3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	status = "okay";
+	clock-frequency = <100000>;
 
-		pinctrl_gpmi_nand: gpminandgrp {
-			fsl,pins = <
-				MX6QDL_PAD_NANDF_CLE__NAND_CLE		0xb0b1
-				MX6QDL_PAD_NANDF_ALE__NAND_ALE		0xb0b1
-				MX6QDL_PAD_NANDF_WP_B__NAND_WP_B	0xb0b1
-				MX6QDL_PAD_NANDF_RB0__NAND_READY_B	0xb000
-				MX6QDL_PAD_NANDF_CS0__NAND_CE0_B	0xb0b1
-				MX6QDL_PAD_NANDF_CS1__NAND_CE1_B	0xb0b1
-				MX6QDL_PAD_SD4_CMD__NAND_RE_B		0xb0b1
-				MX6QDL_PAD_SD4_CLK__NAND_WE_B		0xb0b1
-				MX6QDL_PAD_NANDF_D0__NAND_DATA00	0xb0b1
-				MX6QDL_PAD_NANDF_D1__NAND_DATA01	0xb0b1
-				MX6QDL_PAD_NANDF_D2__NAND_DATA02	0xb0b1
-				MX6QDL_PAD_NANDF_D3__NAND_DATA03	0xb0b1
-				MX6QDL_PAD_NANDF_D4__NAND_DATA04	0xb0b1
-				MX6QDL_PAD_NANDF_D5__NAND_DATA05	0xb0b1
-				MX6QDL_PAD_NANDF_D6__NAND_DATA06	0xb0b1
-				MX6QDL_PAD_NANDF_D7__NAND_DATA07	0xb0b1
-				MX6QDL_PAD_SD4_DAT0__NAND_DQS		0x00b1
-			>;
-		};
-
-		pinctrl_uart4: uart4grp {
-			fsl,pins = <
-				MX6QDL_PAD_KEY_COL0__UART4_TX_DATA	0x1b0b1
-				MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA	0x1b0b1
-			>;
-		};
+	eeprom@50 {
+		compatible = "atmel,24c02";
+		reg = <0x50>;
+		pagesize = <16>;
 	};
+
+	wm8731: codec@1a {
+		#sound-dai-cells = <0>;
+		compatible = "wlf,wm8731";
+		reg = <0x1a>;
+	};
+};
+
+&iomuxc {
+	pinctrl_audmux: audmuxgrp {
+		fsl,pins = <
+			MX6QDL_PAD_SD2_CMD__AUD4_RXC   0x17059
+			MX6QDL_PAD_SD2_DAT0__AUD4_RXD  0x17059
+			MX6QDL_PAD_SD2_DAT3__AUD4_TXC  0x17059
+			MX6QDL_PAD_SD2_DAT2__AUD4_TXD  0x17059
+			MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x17059
+		>;
+	};
+
+	pinctrl_ecspi1: ecspi1grp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D16__ECSPI1_SCLK	0x100b1
+			MX6QDL_PAD_EIM_D17__ECSPI1_MISO	0x100b1
+			MX6QDL_PAD_EIM_D18__ECSPI1_MOSI	0x100b1
+			MX6QDL_PAD_EIM_EB2__GPIO2_IO30	0x100b1
+			MX6QDL_PAD_EIM_D19__GPIO3_IO19	0x100b1
+		>;
+	};
+
+	pinctrl_enet: enetgrp {
+		fsl,pins = <
+			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
+			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
+			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
+			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
+			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
+			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
+			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
+			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
+			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
+			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
+			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
+			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
+			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
+			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
+			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
+		>;
+	};
+
+	pinctrl_gpmi_nand: gpminandgrp {
+		fsl,pins = <
+			MX6QDL_PAD_NANDF_CLE__NAND_CLE		0xb0b1
+			MX6QDL_PAD_NANDF_ALE__NAND_ALE		0xb0b1
+			MX6QDL_PAD_NANDF_WP_B__NAND_WP_B	0xb0b1
+			MX6QDL_PAD_NANDF_RB0__NAND_READY_B	0xb000
+			MX6QDL_PAD_NANDF_CS0__NAND_CE0_B	0xb0b1
+			MX6QDL_PAD_NANDF_CS1__NAND_CE1_B	0xb0b1
+			MX6QDL_PAD_SD4_CMD__NAND_RE_B		0xb0b1
+			MX6QDL_PAD_SD4_CLK__NAND_WE_B		0xb0b1
+			MX6QDL_PAD_NANDF_D0__NAND_DATA00	0xb0b1
+			MX6QDL_PAD_NANDF_D1__NAND_DATA01	0xb0b1
+			MX6QDL_PAD_NANDF_D2__NAND_DATA02	0xb0b1
+			MX6QDL_PAD_NANDF_D3__NAND_DATA03	0xb0b1
+			MX6QDL_PAD_NANDF_D4__NAND_DATA04	0xb0b1
+			MX6QDL_PAD_NANDF_D5__NAND_DATA05	0xb0b1
+			MX6QDL_PAD_NANDF_D6__NAND_DATA06	0xb0b1
+			MX6QDL_PAD_NANDF_D7__NAND_DATA07	0xb0b1
+			MX6QDL_PAD_SD4_DAT0__NAND_DQS		0x00b1
+		>;
+	};
+
+	pinctrl_i2c3: i2c3grp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_3__I2C3_SCL	0x4001b8b1
+			MX6QDL_PAD_GPIO_6__I2C3_SDA	0x4001b8b1
+		>;
+	};
+
+	pinctrl_pcie: pciegrp {
+		fsl,pins = <
+			MX6QDL_PAD_ENET_RXD1__GPIO1_IO26	0x1b0b1
+			MX6QDL_PAD_EIM_CS1__GPIO2_IO24	0x1b0b1
+		>;
+	};
+
+	pinctrl_pwrseq: pwrseqgrp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_17__GPIO7_IO12		0x1b0b0
+			MX6QDL_PAD_NANDF_CS3__GPIO6_IO16	0x1b0b0
+		>;
+	};
+
+	pinctrl_spdif: spdifgrp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_16__SPDIF_IN  0x1b0b0
+			MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x1b0b0
+		>;
+	};
+
+	pinctrl_uart4: uart4grp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_COL0__UART4_TX_DATA	0x1b0b1
+			MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA	0x1b0b1
+		>;
+	};
+
+	pinctrl_usbh1: usbh1grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD3_RST__GPIO7_IO08	0x1b0b1
+		>;
+	};
+
+	pinctrl_usbotg: usbotggrp {
+		fsl,pins = <
+			MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID	0x17059
+			MX6QDL_PAD_EIM_D22__GPIO3_IO22	0x130b0
+		>;
+	};
+
+	pinctrl_usdhc1: usdhc1grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD1_CMD__SD1_CMD	0x17071
+			MX6QDL_PAD_SD1_CLK__SD1_CLK	0x10071
+			MX6QDL_PAD_SD1_DAT0__SD1_DATA0	0x17071
+			MX6QDL_PAD_SD1_DAT1__SD1_DATA1	0x17071
+			MX6QDL_PAD_SD1_DAT2__SD1_DATA2	0x17071
+			MX6QDL_PAD_SD1_DAT3__SD1_DATA3	0x17071
+		>;
+	};
+};
+
+&pcie {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pcie>;
+	reset-gpio = <&gpio1 26 GPIO_ACTIVE_LOW>;
+	vpcie-supply = <&reg_pcie_power_on_gpio>;
+	status = "okay";
+};
+
+&sata {
+	status = "okay";
+};
+
+&snvs_poweroff {
+	status = "okay";
+};
+
+&spdif {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_spdif>;
+	status = "okay";
+};
+
+&ssi2 {
+	assigned-clocks = <&clks IMX6QDL_CLK_SSI2_SEL>,
+			<&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
+	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
+	assigned-clock-rates = <0>, <786432000>;
+	status = "okay";
 };
 
 &uart4 {
@@ -106,10 +367,37 @@
 	status = "okay";
 };
 
-&sata {
+&usbh1 {
+	vbus-supply = <&reg_usb_h1_vbus>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usbh1>;
 	status = "okay";
 };
 
+&usbotg {
+	vbus-supply = <&reg_usb_otg_vbus>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usbotg>;
+	dr_mode = "otg";
+	status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	mmc-pwrseq = <&awnh387_pwrseq>;
+	non-removable;
+	/*
+	 * If the OS probes the Bluetooth AMP function advertised on this bus
+	 * but the firmware in place does not support it, the WiFi/BT module
+	 * gets unresponsive.
+	 * Users who configured their OS properly can enable this node to gain
+	 * WiFi and/or plain Bluetooth support.
+	 */
+	status = "disabled";
+};
+
+/* The U-Boot: enable usdhc3 for mmc boot */
 &usdhc3 {
 	status = "okay";
 };

arch/arm/dts/omap-gpmc-smsc911x.dtsi

@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Common file for GPMC connected smsc911x on omaps
+ *
+ * Note that the board specifc DTS file needs to specify
+ * ranges, pinctrl, reg, interrupt parent and interrupts.
+ */
+
+/ {
+	vddvario: regulator-vddvario {
+		  compatible = "regulator-fixed";
+		  regulator-name = "vddvario";
+		  regulator-always-on;
+	};
+
+	vdd33a: regulator-vdd33a {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd33a";
+		regulator-always-on;
+	};
+};
+
+&gpmc {
+	ethernet@gpmc {
+		compatible = "smsc,lan9221", "smsc,lan9115";
+		bank-width = <2>;
+		gpmc,device-width = <1>;
+		gpmc,cycle2cycle-samecsen = <1>;
+		gpmc,cycle2cycle-diffcsen = <1>;
+		gpmc,cs-on-ns = <5>;
+		gpmc,cs-rd-off-ns = <150>;
+		gpmc,cs-wr-off-ns = <150>;
+		gpmc,adv-on-ns = <0>;
+		gpmc,adv-rd-off-ns = <15>;
+		gpmc,adv-wr-off-ns = <40>;
+		gpmc,oe-on-ns = <45>;
+		gpmc,oe-off-ns = <140>;
+		gpmc,we-on-ns = <45>;
+		gpmc,we-off-ns = <140>;
+		gpmc,rd-cycle-ns = <155>;
+		gpmc,wr-cycle-ns = <155>;
+		gpmc,access-ns = <120>;
+		gpmc,page-burst-access-ns = <20>;
+		gpmc,bus-turnaround-ns = <75>;
+		gpmc,cycle2cycle-delay-ns = <75>;
+		gpmc,wait-monitoring-ns = <0>;
+		gpmc,clk-activation-ns = <0>;
+		gpmc,wr-data-mux-bus-ns = <0>;
+		gpmc,wr-access-ns = <0>;
+		vddvario-supply = <&vddvario>;
+		vdd33a-supply = <&vdd33a>;
+		reg-io-width = <4>;
+		smsc,save-mac-address;
+	};
+};

arch/arm/dts/omap3-evm-37xx-u-boot.dtsi

@@ -0,0 +1,29 @@
+/*
+ * U-Boot additions
+ *
+ * (C) Copyright 2017 Derald D. Woods <woods.technical@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/ {
+	chosen {
+		stdout-path = &uart1;
+	};
+};
+
+&mmc1 {
+	cd-inverted;
+};
+
+&uart1 {
+	reg-shift = <2>;
+};
+
+&uart2 {
+	reg-shift = <2>;
+};
+
+&uart3 {
+	reg-shift = <2>;
+};

arch/arm/dts/omap3-evm-37xx.dts

@@ -0,0 +1,110 @@
+/*
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "omap36xx.dtsi"
+#include "omap3-evm-common.dtsi"
+#include "omap3-evm-processor-common.dtsi"
+
+/ {
+	model = "TI OMAP37XX EVM (TMDSEVM3730)";
+	compatible = "ti,omap3-evm-37xx", "ti,omap3630", "ti,omap3";
+};
+
+&omap3_pmx_core2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&hsusb2_2_pins>;
+
+	ehci_phy_pins: pinmux_ehci_phy_pins {
+		pinctrl-single,pins = <
+
+		/* EHCI PHY reset GPIO etk_d7.gpio_21 */
+		OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4)
+
+		/* EHCI VBUS etk_d8.gpio_22 */
+		OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4)
+		>;
+	};
+
+	/* Used by OHCI and EHCI. OHCI won't work without external phy */
+	hsusb2_2_pins: pinmux_hsusb2_2_pins {
+		pinctrl-single,pins = <
+
+		/* etk_d10.hsusb2_clk */
+		OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3)
+
+		/* etk_d11.hsusb2_stp */
+		OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3)
+
+		/* etk_d12.hsusb2_dir */
+		OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3)
+
+		/* etk_d13.hsusb2_nxt */
+		OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3)
+
+		/* etk_d14.hsusb2_data0 */
+		OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3)
+
+		/* etk_d15.hsusb2_data1 */
+		OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3)
+		>;
+	};
+};
+
+&gpmc {
+	nand@0,0 {
+		compatible = "ti,omap2-nand";
+		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+		interrupt-parent = <&gpmc>;
+		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+			     <1 IRQ_TYPE_NONE>;	/* termcount */
+		linux,mtd-name= "hynix,h8kds0un0mer-4em";
+		nand-bus-width = <16>;
+		gpmc,device-width = <2>;
+		ti,nand-ecc-opt = "bch8";
+
+		gpmc,sync-clk-ps = <0>;
+		gpmc,cs-on-ns = <0>;
+		gpmc,cs-rd-off-ns = <44>;
+		gpmc,cs-wr-off-ns = <44>;
+		gpmc,adv-on-ns = <6>;
+		gpmc,adv-rd-off-ns = <34>;
+		gpmc,adv-wr-off-ns = <44>;
+		gpmc,we-off-ns = <40>;
+		gpmc,oe-off-ns = <54>;
+		gpmc,access-ns = <64>;
+		gpmc,rd-cycle-ns = <82>;
+		gpmc,wr-cycle-ns = <82>;
+		gpmc,wr-access-ns = <40>;
+		gpmc,wr-data-mux-bus-ns = <0>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@0 {
+			label = "X-Loader";
+			reg = <0 0x80000>;
+		};
+		partition@0x80000 {
+			label = "U-Boot";
+			reg = <0x80000 0x1c0000>;
+		};
+		partition@0x1c0000 {
+			label = "Environment";
+			reg = <0x240000 0x40000>;
+		};
+		partition@0x280000 {
+			label = "Kernel";
+			reg = <0x280000 0x500000>;
+		};
+		partition@0x780000 {
+			label = "Filesystem";
+			reg = <0x780000 0x1f880000>;
+		};
+	};
+};

arch/arm/dts/omap3-evm-common.dtsi

@@ -0,0 +1,195 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Common support for omap3 EVM boards
+ */
+
+#include <dt-bindings/input/input.h>
+#include "omap-gpmc-smsc911x.dtsi"
+
+/ {
+	cpus {
+		cpu@0 {
+			cpu0-supply = <&vcc>;
+		};
+	};
+
+	/* HS USB Port 2 Power */
+	hsusb2_power: hsusb2_power_reg {
+		compatible = "regulator-fixed";
+		regulator-name = "hsusb2_vbus";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; /* gpio_22 */
+		startup-delay-us = <70000>;
+		enable-active-high;
+	};
+
+	/* HS USB Host PHY on PORT 2 */
+	hsusb2_phy: hsusb2_phy {
+		compatible = "usb-nop-xceiv";
+		reset-gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */
+		vcc-supply = <&hsusb2_power>;
+		#phy-cells = <0>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		ledb {
+			label = "omap3evm::ledb";
+			gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */
+			linux,default-trigger = "default-on";
+		};
+	};
+
+	wl12xx_vmmc: wl12xx_vmmc {
+		compatible = "regulator-fixed";
+		regulator-name = "vwl1271";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		gpio = <&gpio5 22 GPIO_ACTIVE_HIGH>;	/* gpio150 */
+		startup-delay-us = <70000>;
+		enable-active-high;
+		vin-supply = <&vmmc2>;
+	};
+};
+
+&i2c1 {
+	clock-frequency = <2600000>;
+
+	twl: twl@48 {
+		reg = <0x48>;
+		interrupts = <7>; /* SYS_NIRQ cascaded to intc */
+		interrupt-parent = <&intc>;
+	};
+};
+
+#include "twl4030.dtsi"
+#include "twl4030_omap3.dtsi"
+#include "omap3-panel-sharp-ls037v7dw01.dtsi"
+
+&backlight0 {
+	gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>;
+};
+
+&twl {
+	twl_power: power {
+		compatible = "ti,twl4030-power-omap3-evm", "ti,twl4030-power-idle";
+		ti,use_poweroff;
+	};
+};
+
+&i2c2 {
+	clock-frequency = <400000>;
+};
+
+&i2c3 {
+	clock-frequency = <400000>;
+
+	/*
+	 * TVP5146 Video decoder-in for analog input support.
+	 */
+	tvp5146@5c {
+		compatible = "ti,tvp5146m2";
+		reg = <0x5c>;
+	};
+};
+
+&lcd_3v3 {
+	gpio = <&gpio5 25 GPIO_ACTIVE_LOW>;	/* gpio153 */
+};
+
+&lcd0 {
+	enable-gpios = <&gpio5 24 GPIO_ACTIVE_HIGH>;	/* gpio152, lcd INI */
+	reset-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>;	/* gpio155, lcd RESB */
+	mode-gpios = <&gpio5 26 GPIO_ACTIVE_HIGH	/* gpio154, lcd MO */
+		      &gpio1 2 GPIO_ACTIVE_HIGH		/* gpio2, lcd LR */
+		      &gpio1 3 GPIO_ACTIVE_HIGH>;	/* gpio3, lcd UD */
+};
+
+&mcspi1 {
+	tsc2046@0 {
+		interrupt-parent = <&gpio6>;
+		interrupts = <15 0>;		/* gpio175 */
+		pendown-gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&mmc1 {
+	interrupts-extended = <&intc 83 &omap3_pmx_core 0x11a>;
+	vmmc-supply = <&vmmc1>;
+	vqmmc-supply = <&vsim>;
+	bus-width = <8>;
+};
+
+&mmc2 {
+	vmmc-supply = <&wl12xx_vmmc>;
+	non-removable;
+	bus-width = <4>;
+	cap-power-off-card;
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+	wlcore: wlcore@2 {
+		compatible = "ti,wl1271";
+		reg = <2>;
+		interrupt-parent = <&gpio5>;
+		interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; /* gpio 149 */
+		ref-clock-frequency = <38400000>;
+	};
+};
+
+&twl_gpio {
+	ti,use-leds;
+};
+
+&twl_keypad {
+	linux,keymap = <
+			MATRIX_KEY(2, 2, KEY_1)
+			MATRIX_KEY(1, 1, KEY_2)
+			MATRIX_KEY(0, 0, KEY_3)
+			MATRIX_KEY(3, 2, KEY_4)
+			MATRIX_KEY(2, 1, KEY_5)
+			MATRIX_KEY(1, 0, KEY_6)
+			MATRIX_KEY(1, 3, KEY_7)
+			MATRIX_KEY(3, 1, KEY_8)
+			MATRIX_KEY(2, 0, KEY_9)
+			MATRIX_KEY(2, 3, KEY_KPASTERISK)
+			MATRIX_KEY(0, 2, KEY_0)
+			MATRIX_KEY(3, 0, KEY_KPDOT)
+			/* s4 not wired */
+			MATRIX_KEY(1, 2, KEY_BACKSPACE)
+			MATRIX_KEY(0, 1, KEY_ENTER)
+			>;
+};
+
+&usbhshost {
+	port2-mode = "ehci-phy";
+};
+
+&usbhsehci {
+	phys = <0 &hsusb2_phy>;
+};
+
+&usb_otg_hs {
+	interface-type = <0>;
+	usb-phy = <&usb2_phy>;
+	phys = <&usb2_phy>;
+	phy-names = "usb2-phy";
+	mode = <3>;
+	power = <50>;
+};
+
+&gpmc {
+	ethernet@gpmc {
+		interrupt-parent = <&gpio6>;
+		interrupts = <16 8>;
+		reg = <5 0 0xff>;
+	};
+};
+
+&vaux2 {
+	regulator-name = "usb_1v8";
+	regulator-min-microvolt = <1800000>;
+	regulator-max-microvolt = <1800000>;
+	regulator-always-on;
+};

arch/arm/dts/omap3-evm-processor-common.dtsi

@@ -0,0 +1,216 @@
+/*
+ * Common support for omap3 EVM 35xx/37xx processor modules
+ */
+
+/ {
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x80000000 0x10000000>; /* 256 MB */
+	};
+
+	wl12xx_vmmc: wl12xx_vmmc {
+		pinctrl-names = "default";
+		pinctrl-0 = <&wl12xx_gpio>;
+	};
+};
+
+&dss {
+	vdds_dsi-supply = <&vpll2>;
+	vdda_video-supply = <&lcd_3v3>;
+	pinctrl-names = "default";
+	pinctrl-0 = <
+		&dss_dpi_pins1
+		&dss_dpi_pins2
+	>;
+};
+
+&hsusb2_phy {
+	pinctrl-names = "default";
+	pinctrl-0 = <&ehci_phy_pins>;
+};
+
+&omap3_pmx_core {
+	pinctrl-names = "default";
+	pinctrl-0 = <&on_board_gpio_61 &hsusb2_pins>;
+
+	dss_dpi_pins1: pinmux_dss_dpi_pins2 {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0)   /* dss_pclk.dss_pclk */
+			OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0)   /* dss_hsync.dss_hsync */
+			OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0)   /* dss_vsync.dss_vsync */
+			OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0)   /* dss_acbias.dss_acbias */
+
+			OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0)   /* dss_data6.dss_data6 */
+			OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0)   /* dss_data7.dss_data7 */
+			OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0)   /* dss_data8.dss_data8 */
+			OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0)   /* dss_data9.dss_data9 */
+			OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0)   /* dss_data10.dss_data10 */
+			OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0)   /* dss_data11.dss_data11 */
+			OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0)   /* dss_data12.dss_data12 */
+			OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0)   /* dss_data13.dss_data13 */
+			OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0)   /* dss_data14.dss_data14 */
+			OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0)   /* dss_data15.dss_data15 */
+			OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0)   /* dss_data16.dss_data16 */
+			OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0)   /* dss_data17.dss_data17 */
+
+			OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE3)   /* dss_data18.dss_data0 */
+			OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE3)   /* dss_data19.dss_data1 */
+			OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE3)   /* dss_data20.dss_data2 */
+			OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE3)   /* dss_data21.dss_data3 */
+			OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE3)   /* dss_data22.dss_data4 */
+			OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE3)   /* dss_data23.dss_data5 */
+		>;
+	};
+
+	mmc1_pins: pinmux_mmc1_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT_PULLUP | MUX_MODE0)	/* sdmmc1_clk.sdmmc1_clk */
+			OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0)		/* sdmmc1_cmd.sdmmc1_cmd */
+			OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) 	/* sdmmc1_dat0.sdmmc1_dat0 */
+			OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) 	/* sdmmc1_dat1.sdmmc1_dat1 */
+			OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) 	/* sdmmc1_dat2.sdmmc1_dat2 */
+			OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) 	/* sdmmc1_dat3.sdmmc1_dat3 */
+			OMAP3_CORE1_IOPAD(0x2150, PIN_INPUT_PULLUP | MUX_MODE0) 	/* sdmmc1_dat4.sdmmc1_dat4 */
+			OMAP3_CORE1_IOPAD(0x2152, PIN_INPUT_PULLUP | MUX_MODE0) 	/* sdmmc1_dat5.sdmmc1_dat5 */
+			OMAP3_CORE1_IOPAD(0x2154, PIN_INPUT_PULLUP | MUX_MODE0) 	/* sdmmc1_dat6.sdmmc1_dat6 */
+			OMAP3_CORE1_IOPAD(0x2156, PIN_INPUT_PULLUP | MUX_MODE0) 	/* sdmmc1_dat7.sdmmc1_dat7 */
+		>;
+	};
+
+	/* NOTE: Clocked externally, needs INPUT also for sdmmc2_clk.sdmmc2_clk */
+	mmc2_pins: pinmux_mmc2_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc2_clk.sdmmc2_clk */
+			OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc2_cmd.sdmmc2_cmd */
+			OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc2_dat0.sdmmc2_dat0 */
+			OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */
+			OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc2_dat2.sdmmc2_dat2 */
+			OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc2_dat3.sdmmc2_dat3 */
+		>;
+	};
+
+	uart3_pins: pinmux_uart3_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x219e, WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
+			OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0)		/* uart3_tx_irtx.uart3_tx_irtx */
+		>;
+	};
+
+	/* Devices are routed with gpmc_nbe1.gpio_61 to on-board devices */
+	on_board_gpio_61: pinmux_ehci_port_select_pins {
+		pinctrl-single,pins = <
+		OMAP3_CORE1_IOPAD(0x20c8, PIN_OUTPUT | MUX_MODE4)
+		>;
+	};
+
+	/* Used by OHCI and EHCI. OHCI won't work without external phy */
+	hsusb2_pins: pinmux_hsusb2_pins {
+		pinctrl-single,pins = <
+
+		/* mcspi1_cs3.hsusb2_data2 */
+		OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3)
+
+		/* mcspi2_clk.hsusb2_data7 */
+		OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3)
+
+		/* mcspi2_simo.hsusb2_data4 */
+		OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3)
+
+		/* mcspi2_somi.hsusb2_data5 */
+		OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3)
+
+		/* mcspi2_cs0.hsusb2_data6 */
+		OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3)
+
+		/* mcspi2_cs1.hsusb2_data3 */
+		OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3)
+		>;
+	};
+
+	wl12xx_gpio: pinmux_wl12xx_gpio {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x2180, PIN_OUTPUT | MUX_MODE4)		/* uart1_cts.gpio_150 */
+			OMAP3_CORE1_IOPAD(0x217e, PIN_INPUT | MUX_MODE4)		/* uart1_rts.gpio_149 */
+		>;
+	};
+
+	smsc911x_pins: pinmux_smsc911x_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT | MUX_MODE4)		/* mcspi1_cs2.gpio_176 */
+		>;
+	};
+};
+
+&omap3_pmx_wkup {
+	dss_dpi_pins2: pinmux_dss_dpi_pins1 {
+		pinctrl-single,pins = <
+			OMAP3_WKUP_IOPAD(0x2a0a, PIN_OUTPUT | MUX_MODE3)   /* sys_boot0.dss_data18 */
+			OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE3)   /* sys_boot1.dss_data19 */
+			OMAP3_WKUP_IOPAD(0x2a10, PIN_OUTPUT | MUX_MODE3)   /* sys_boot3.dss_data20 */
+			OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE3)   /* sys_boot4.dss_data21 */
+			OMAP3_WKUP_IOPAD(0x2a14, PIN_OUTPUT | MUX_MODE3)   /* sys_boot5.dss_data22 */
+			OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | MUX_MODE3)   /* sys_boot6.dss_data23 */
+		>;
+	};
+};
+
+&mmc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc1_pins>;
+};
+
+&mmc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc2_pins>;
+};
+
+&mmc3 {
+	status = "disabled";
+};
+
+&uart1 {
+	interrupts-extended = <&intc 72 &omap3_pmx_core OMAP3_UART1_RX>;
+};
+
+&uart2 {
+	interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>;
+};
+
+&uart3 {
+	interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart3_pins>;
+};
+
+/*
+ * GPIO_61 (nUSB2_EN_1V8) must be low to enable on-board EHCI USB2 interface
+ * for bus switch SN74CB3Q3384A, level-shifter SN74AVC16T245DGGR, and 1.8V.
+ */
+&gpio2 {
+	en_usb2_port {
+		gpio-hog;
+		gpios = <29 GPIO_ACTIVE_HIGH>;	/* gpio_61 */
+		output-low;
+		line-name = "enable usb2 port";
+	};
+};
+
+/* T2_GPIO_2 low to route GPIO_61 to on-board devices */
+&twl_gpio {
+	en_on_board_gpio_61 {
+		gpio-hog;
+		gpios = <2 GPIO_ACTIVE_HIGH>;
+		output-low;
+		line-name = "en_hsusb2_clk";
+	};
+};
+
+&gpmc {
+	ranges = <0 0 0x30000000 0x1000000>,	/* CS0: 16MB for NAND */
+		 <5 0 0x2c000000 0x01000000>;	/* CS5: 16MB for LAN9220 */
+
+	ethernet@gpmc {
+		pinctrl-names = "default";
+		pinctrl-0 = <&smsc911x_pins>;
+	};
+};

arch/arm/dts/omap3-evm-u-boot.dtsi

@@ -0,0 +1,29 @@
+/*
+ * U-Boot additions
+ *
+ * (C) Copyright 2017 Derald D. Woods <woods.technical@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/ {
+	chosen {
+		stdout-path = &uart1;
+	};
+};
+
+&mmc1 {
+	cd-inverted;
+};
+
+&uart1 {
+	reg-shift = <2>;
+};
+
+&uart2 {
+	reg-shift = <2>;
+};
+
+&uart3 {
+	reg-shift = <2>;
+};

arch/arm/dts/omap3-evm.dts

@@ -0,0 +1,89 @@
+/*
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "omap34xx.dtsi"
+#include "omap3-evm-common.dtsi"
+#include "omap3-evm-processor-common.dtsi"
+
+/ {
+	model = "TI OMAP35XX EVM (TMDSEVM3530)";
+	compatible = "ti,omap3-evm", "ti,omap3430", "ti,omap3";
+};
+
+&omap3_pmx_core2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&hsusb2_2_pins>;
+
+	ehci_phy_pins: pinmux_ehci_phy_pins {
+		pinctrl-single,pins = <
+
+		/* EHCI PHY reset GPIO etk_d7.gpio_21 */
+		OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4)
+
+		/* EHCI VBUS etk_d8.gpio_22 */
+		OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4)
+		>;
+	};
+
+	/* Used by OHCI and EHCI. OHCI won't work without external phy */
+	hsusb2_2_pins: pinmux_hsusb2_2_pins {
+		pinctrl-single,pins = <
+
+		/* etk_d10.hsusb2_clk */
+		OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3)
+
+		/* etk_d11.hsusb2_stp */
+		OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3)
+
+		/* etk_d12.hsusb2_dir */
+		OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3)
+
+		/* etk_d13.hsusb2_nxt */
+		OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3)
+
+		/* etk_d14.hsusb2_data0 */
+		OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3)
+
+		/* etk_d15.hsusb2_data1 */
+		OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3)
+		>;
+	};
+};
+
+&gpmc {
+	nand@0,0 {
+		compatible = "ti,omap2-nand";
+		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+		interrupt-parent = <&gpmc>;
+		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+			     <1 IRQ_TYPE_NONE>;	/* termcount */
+		linux,mtd-name= "micron,mt29f2g16abdhc";
+		nand-bus-width = <16>;
+		gpmc,device-width = <2>;
+		ti,nand-ecc-opt = "bch8";
+
+		gpmc,sync-clk-ps = <0>;
+		gpmc,cs-on-ns = <0>;
+		gpmc,cs-rd-off-ns = <44>;
+		gpmc,cs-wr-off-ns = <44>;
+		gpmc,adv-on-ns = <6>;
+		gpmc,adv-rd-off-ns = <34>;
+		gpmc,adv-wr-off-ns = <44>;
+		gpmc,we-off-ns = <40>;
+		gpmc,oe-off-ns = <54>;
+		gpmc,access-ns = <64>;
+		gpmc,rd-cycle-ns = <82>;
+		gpmc,wr-cycle-ns = <82>;
+		gpmc,wr-access-ns = <40>;
+		gpmc,wr-data-mux-bus-ns = <0>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+	};
+};

arch/arm/dts/omap3-panel-sharp-ls037v7dw01.dtsi

@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Common file for omap dpi panels with QVGA and reset pins
+ *
+ * Note that the board specifc DTS file needs to specify
+ * at minimum the GPIO enable-gpios for display, and
+ * gpios for gpio-backlight.
+ */
+
+/ {
+	aliases {
+		display0 = &lcd0;
+	};
+
+	backlight0: backlight {
+		compatible = "gpio-backlight";
+		default-on;
+	};
+
+	/* 3.3V GPIO controlled regulator for LCD_ENVDD */
+	lcd_3v3: regulator-lcd-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "lcd_3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		startup-delay-us = <70000>;
+	};
+
+	lcd0: display {
+		compatible = "sharp,ls037v7dw01";
+		label = "lcd";
+		power-supply = <&lcd_3v3>;
+		envdd-supply = <&lcd_3v3>;
+
+		port {
+			lcd_in: endpoint {
+				remote-endpoint = <&dpi_out>;
+			};
+		};
+	};
+};
+
+/* Needed to power the DPI pins */
+&vpll2 {
+	regulator-always-on;
+};
+
+&dss {
+	status = "ok";
+	port {
+		dpi_out: endpoint {
+			remote-endpoint = <&lcd_in>;
+			data-lines = <18>;
+		};
+	};
+};
+
+&mcspi1 {
+	tsc2046@0 {
+		reg = <0>;			/* CS0 */
+		compatible = "ti,tsc2046";
+		spi-max-frequency = <1000000>;
+		vcc-supply = <&lcd_3v3>;
+		ti,x-min = /bits/ 16 <0>;
+		ti,x-max = /bits/ 16 <8000>;
+		ti,y-min = /bits/ 16 <0>;
+		ti,y-max = /bits/ 16 <4800>;
+		ti,x-plate-ohms = /bits/ 16 <40>;
+		ti,pressure-max = /bits/ 16 <255>;
+		ti,swap-xy;
+		wakeup-source;
+	};
+};

arch/arm/dts/omap34xx.dtsi

@@ -0,0 +1,84 @@
+/*
+ * Device Tree Source for OMAP34xx/OMAP35xx SoC
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/media/omap3-isp.h>
+
+#include "omap3.dtsi"
+
+/ {
+	cpus {
+		cpu: cpu@0 {
+			/* OMAP343x/OMAP35xx variants OPP1-5 */
+			operating-points = <
+				/* kHz    uV */
+				125000   975000
+				250000  1075000
+				500000  1200000
+				550000  1270000
+				600000  1350000
+			>;
+			clock-latency = <300000>; /* From legacy driver */
+		};
+	};
+
+	ocp@68000000 {
+		omap3_pmx_core2: pinmux@480025d8 {
+			compatible = "ti,omap3-padconf", "pinctrl-single";
+			reg = <0x480025d8 0x24>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#pinctrl-cells = <1>;
+			#interrupt-cells = <1>;
+			interrupt-controller;
+			pinctrl-single,register-width = <16>;
+			pinctrl-single,function-mask = <0xff1f>;
+		};
+
+		isp: isp@480bc000 {
+			compatible = "ti,omap3-isp";
+			reg = <0x480bc000 0x12fc
+			       0x480bd800 0x017c>;
+			interrupts = <24>;
+			iommus = <&mmu_isp>;
+			syscon = <&scm_conf 0x6c>;
+			ti,phy-type = <OMAP3ISP_PHY_TYPE_COMPLEX_IO>;
+			#clock-cells = <1>;
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+		};
+
+		bandgap: bandgap@48002524 {
+			reg = <0x48002524 0x4>;
+			compatible = "ti,omap34xx-bandgap";
+			#thermal-sensor-cells = <0>;
+		};
+	};
+
+	thermal_zones: thermal-zones {
+		#include "omap3-cpu-thermal.dtsi"
+	};
+};
+
+&ssi {
+	status = "ok";
+
+	clocks = <&ssi_ssr_fck>,
+		 <&ssi_sst_fck>,
+		 <&ssi_ick>;
+	clock-names = "ssi_ssr_fck",
+		      "ssi_sst_fck",
+		      "ssi_ick";
+};
+
+/include/ "omap34xx-omap36xx-clocks.dtsi"
+/include/ "omap36xx-omap3430es2plus-clocks.dtsi"
+/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"

arch/arm/dts/r8a77970-eagle.dts

@@ -0,0 +1,87 @@
+/*
+ * Device Tree Source for the Eagle board
+ *
+ * Copyright (C) 2016-2017 Renesas Electronics Corp.
+ * Copyright (C) 2017 Cogent Embedded, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/dts-v1/;
+#include "r8a77970.dtsi"
+
+/ {
+	model = "Renesas Eagle board based on r8a77970";
+	compatible = "renesas,eagle", "renesas,r8a77970";
+
+	aliases {
+		serial0 = &scif0;
+		ethernet0 = &avb;
+	};
+
+	chosen {
+		bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@48000000 {
+		device_type = "memory";
+		/* first 128MB is reserved for secure area. */
+		reg = <0x0 0x48000000 0x0 0x38000000>;
+	};
+};
+
+&extal_clk {
+	clock-frequency = <16666666>;
+};
+
+&extalr_clk {
+	clock-frequency = <32768>;
+};
+
+&pfc {
+	pinctrl-0 = <&scif_clk_pins>;
+	pinctrl-names = "default";
+
+	scif0_pins: scif0 {
+		groups = "scif0_data";
+		function = "scif0";
+	};
+
+	scif_clk_pins: scif_clk {
+		groups = "scif_clk_b";
+		function = "scif_clk";
+	};
+
+	avb_pins: avb {
+		groups = "avb0_mdc";
+		function = "avb0";
+	};
+};
+
+&scif0 {
+	pinctrl-0 = <&scif0_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&scif_clk {
+	clock-frequency = <14745600>;
+	status = "okay";
+};
+
+&avb {
+	pinctrl-0 = <&avb_pins>;
+	pinctrl-names = "default";
+	renesas,no-ether-link;
+	phy-handle = <&phy0>;
+	status = "okay";
+
+	phy0: ethernet-phy@0 {
+		rxc-skew-ps = <1500>;
+		reg = <0>;
+	};
+};

arch/arm/dts/r8a77970.dtsi

@@ -0,0 +1,392 @@
+/*
+ * Device Tree Source for the r8a77970 SoC
+ *
+ * Copyright (C) 2016-2017 Renesas Electronics Corp.
+ * Copyright (C) 2017 Cogent Embedded, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/ {
+	compatible = "renesas,r8a77970";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	psci {
+		compatible = "arm,psci-1.0", "arm,psci-0.2";
+		method = "smc";
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		a53_0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53", "arm,armv8";
+			reg = <0>;
+			clocks = <&cpg CPG_CORE 0>;
+			power-domains = <&sysc 5>;
+			next-level-cache = <&L2_CA53>;
+			enable-method = "psci";
+		};
+
+		L2_CA53: cache-controller {
+			compatible = "cache";
+			power-domains = <&sysc 21>;
+			cache-unified;
+			cache-level = <2>;
+		};
+	};
+
+	extal_clk: extal {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board */
+		clock-frequency = <0>;
+		u-boot,dm-pre-reloc;
+	};
+
+	extalr_clk: extalr {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board */
+		clock-frequency = <0>;
+		u-boot,dm-pre-reloc;
+	};
+
+	/* External SCIF clock - to be overridden by boards that provide it */
+	scif_clk: scif {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <0>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		interrupt-parent = <&gic>;
+
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		u-boot,dm-pre-reloc;
+
+		gic: interrupt-controller@f1010000 {
+			compatible = "arm,gic-400";
+			#interrupt-cells = <3>;
+			#address-cells = <0>;
+			interrupt-controller;
+			reg = <0 0xf1010000 0 0x1000>,
+			      <0 0xf1020000 0 0x20000>,
+			      <0 0xf1040000 0 0x20000>,
+			      <0 0xf1060000 0 0x20000>;
+			interrupts = <GIC_PPI 9	(GIC_CPU_MASK_SIMPLE(1) |
+				      IRQ_TYPE_LEVEL_HIGH)>;
+			clocks = <&cpg CPG_MOD 408>;
+			clock-names = "clk";
+			power-domains = <&sysc 32>;
+			resets = <&cpg 408>;
+		};
+
+		timer {
+			compatible = "arm,armv8-timer";
+			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
+						  IRQ_TYPE_LEVEL_LOW)>,
+				     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
+						  IRQ_TYPE_LEVEL_LOW)>,
+				     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |
+						  IRQ_TYPE_LEVEL_LOW)>,
+				     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |
+						  IRQ_TYPE_LEVEL_LOW)>;
+		};
+
+		cpg: clock-controller@e6150000 {
+			compatible = "renesas,r8a77970-cpg-mssr";
+			reg = <0 0xe6150000 0 0x1000>;
+			clocks = <&extal_clk>, <&extalr_clk>;
+			clock-names = "extal", "extalr";
+			#clock-cells = <2>;
+			#power-domain-cells = <0>;
+			#reset-cells = <1>;
+			u-boot,dm-pre-reloc;
+		};
+
+		rst: reset-controller@e6160000 {
+			compatible = "renesas,r8a77970-rst";
+			reg = <0 0xe6160000 0 0x200>;
+		};
+
+		sysc: system-controller@e6180000 {
+			compatible = "renesas,r8a77970-sysc";
+			reg = <0 0xe6180000 0 0x440>;
+			#power-domain-cells = <1>;
+		};
+
+		pfc: pfc@e6060000 {
+			compatible = "renesas,pfc-r8a77970";
+			reg = <0 0xe6060000 0 0x50c>;
+		};
+
+		intc_ex: interrupt-controller@e61c0000 {
+			compatible = "renesas,intc-ex-r8a77970", "renesas,irqc";
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			reg = <0 0xe61c0000 0 0x200>;
+			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 407>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 407>;
+		};
+
+		prr: chipid@fff00044 {
+			compatible = "renesas,prr";
+			reg = <0 0xfff00044 0 4>;
+			u-boot,dm-pre-reloc;
+		};
+
+		dmac1: dma-controller@e7300000 {
+			compatible = "renesas,dmac-r8a77970",
+				     "renesas,rcar-dmac";
+			reg = <0 0xe7300000 0 0x10000>;
+			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "error",
+					  "ch0", "ch1", "ch2", "ch3",
+					  "ch4", "ch5", "ch6", "ch7";
+			clocks = <&cpg CPG_MOD 218>;
+			clock-names = "fck";
+			power-domains = <&sysc 32>;
+			resets = <&cpg 218>;
+			#dma-cells = <1>;
+			dma-channels = <8>;
+		};
+
+		dmac2: dma-controller@e7310000 {
+			compatible = "renesas,dmac-r8a77970",
+				     "renesas,rcar-dmac";
+			reg = <0 0xe7310000 0 0x10000>;
+			interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "error",
+					  "ch0", "ch1", "ch2", "ch3",
+					  "ch4", "ch5", "ch6", "ch7";
+			clocks = <&cpg CPG_MOD 217>;
+			clock-names = "fck";
+			power-domains = <&sysc 32>;
+			resets = <&cpg 217>;
+			#dma-cells = <1>;
+			dma-channels = <8>;
+		};
+
+		hscif0: serial@e6540000 {
+			compatible = "renesas,hscif-r8a77970",
+				     "renesas,rcar-gen3-hscif",
+				     "renesas,hscif";
+			reg = <0 0xe6540000 0 96>;
+			interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 520>,
+				 <&cpg CPG_CORE 9>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac1 0x31>, <&dmac1 0x30>,
+			       <&dmac2 0x31>, <&dmac2 0x30>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc 32>;
+			resets = <&cpg 520>;
+			status = "disabled";
+		};
+
+		hscif1: serial@e6550000 {
+			compatible = "renesas,hscif-r8a77970",
+				     "renesas,rcar-gen3-hscif",
+				     "renesas,hscif";
+			reg = <0 0xe6550000 0 96>;
+			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 519>,
+				 <&cpg CPG_CORE 9>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac1 0x33>, <&dmac1 0x32>,
+			       <&dmac2 0x33>, <&dmac2 0x32>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc 32>;
+			resets = <&cpg 519>;
+			status = "disabled";
+		};
+
+		hscif2: serial@e6560000 {
+			compatible = "renesas,hscif-r8a77970",
+				     "renesas,rcar-gen3-hscif",
+				     "renesas,hscif";
+			reg = <0 0xe6560000 0 96>;
+			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 518>,
+				 <&cpg CPG_CORE 9>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac1 0x35>, <&dmac1 0x34>,
+			       <&dmac2 0x35>, <&dmac2 0x34>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc 32>;
+			resets = <&cpg 518>;
+			status = "disabled";
+		};
+
+		hscif3: serial@e66a0000 {
+			compatible = "renesas,hscif-r8a77970",
+				     "renesas,rcar-gen3-hscif", "renesas,hscif";
+			reg = <0 0xe66a0000 0 96>;
+			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 517>,
+				 <&cpg CPG_CORE 9>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac1 0x37>, <&dmac1 0x36>,
+			       <&dmac2 0x37>, <&dmac2 0x36>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc 32>;
+			resets = <&cpg 517>;
+			status = "disabled";
+		};
+
+		scif0: serial@e6e60000 {
+			compatible = "renesas,scif-r8a77970",
+				     "renesas,rcar-gen3-scif",
+				     "renesas,scif";
+			reg = <0 0xe6e60000 0 64>;
+			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 207>,
+				 <&cpg CPG_CORE 9>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac1 0x51>, <&dmac1 0x50>,
+			       <&dmac2 0x51>, <&dmac2 0x50>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc 32>;
+			resets = <&cpg 207>;
+			status = "disabled";
+		};
+
+		scif1: serial@e6e68000 {
+			compatible = "renesas,scif-r8a77970",
+				     "renesas,rcar-gen3-scif",
+				     "renesas,scif";
+			reg = <0 0xe6e68000 0 64>;
+			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 206>,
+				 <&cpg CPG_CORE 9>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac1 0x53>, <&dmac1 0x52>,
+			       <&dmac2 0x53>, <&dmac2 0x52>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc 32>;
+			resets = <&cpg 206>;
+			status = "disabled";
+		};
+
+		scif3: serial@e6c50000 {
+			compatible = "renesas,scif-r8a77970",
+				     "renesas,rcar-gen3-scif",
+				     "renesas,scif";
+			reg = <0 0xe6c50000 0 64>;
+			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 204>,
+				 <&cpg CPG_CORE 9>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac1 0x57>, <&dmac1 0x56>,
+			       <&dmac2 0x57>, <&dmac2 0x56>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc 32>;
+			resets = <&cpg 204>;
+			status = "disabled";
+		};
+
+		scif4: serial@e6c40000 {
+			compatible = "renesas,scif-r8a77970",
+				     "renesas,rcar-gen3-scif", "renesas,scif";
+			reg = <0 0xe6c40000 0 64>;
+			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 203>,
+				 <&cpg CPG_CORE 9>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			dmas = <&dmac1 0x59>, <&dmac1 0x58>,
+			       <&dmac2 0x59>, <&dmac2 0x58>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc 32>;
+			resets = <&cpg 203>;
+			status = "disabled";
+		};
+
+		avb: ethernet@e6800000 {
+			compatible = "renesas,etheravb-r8a77970",
+				     "renesas,etheravb-rcar-gen3";
+			reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
+			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "ch0", "ch1", "ch2", "ch3",
+					  "ch4", "ch5", "ch6", "ch7",
+					  "ch8", "ch9", "ch10", "ch11",
+					  "ch12", "ch13", "ch14", "ch15",
+					  "ch16", "ch17", "ch18", "ch19",
+					  "ch20", "ch21", "ch22", "ch23",
+					  "ch24";
+			clocks = <&cpg CPG_MOD 812>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 812>;
+			phy-mode = "rgmii-id";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
+};

arch/arm/dts/r8a77995-draak.dts

@@ -0,0 +1,124 @@
+/*
+ * Device Tree Source for the Draak board
+ *
+ * Copyright (C) 2016 Renesas Electronics Corp.
+ * Copyright (C) 2017 Glider bvba
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/dts-v1/;
+#include "r8a77995.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "Renesas Draak board based on r8a77995";
+	compatible = "renesas,draak", "renesas,r8a77995";
+
+	aliases {
+		serial0 = &scif2;
+		ethernet0 = &avb;
+	};
+
+	chosen {
+		bootargs = "ignore_loglevel";
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@48000000 {
+		device_type = "memory";
+		/* first 128MB is reserved for secure area. */
+		reg = <0x0 0x48000000 0x0 0x18000000>;
+	};
+};
+
+&extal_clk {
+	clock-frequency = <48000000>;
+};
+
+&pfc {
+	avb0_pins: avb {
+		mux {
+			groups = "avb0_link", "avb0_mdc", "avb0_mii";
+			function = "avb0";
+		};
+	};
+
+	pwm0_pins: pwm0 {
+		groups = "pwm0_c";
+		function = "pwm0";
+	};
+
+	pwm1_pins: pwm1 {
+		groups = "pwm1_c";
+		function = "pwm1";
+	};
+
+	scif2_pins: scif2 {
+		groups = "scif2_data";
+		function = "scif2";
+	};
+
+	usb0_pins: usb0 {
+		groups = "usb0";
+		function = "usb0";
+	};
+};
+
+&ehci0 {
+	status = "okay";
+};
+
+&ohci0 {
+	status = "okay";
+};
+
+&avb {
+	pinctrl-0 = <&avb0_pins>;
+	pinctrl-names = "default";
+	renesas,no-ether-link;
+	phy-handle = <&phy0>;
+	status = "okay";
+
+	phy0: ethernet-phy@0 {
+		rxc-skew-ps = <1500>;
+		reg = <0>;
+		interrupt-parent = <&gpio5>;
+		interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
+	};
+};
+
+&scif2 {
+	pinctrl-0 = <&scif2_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&usb2_phy0 {
+	pinctrl-0 = <&usb0_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&pwm0 {
+	pinctrl-0 = <&pwm0_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&pwm1 {
+	pinctrl-0 = <&pwm1_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&rwdt {
+	timeout-sec = <60>;
+	status = "okay";
+};

arch/arm/dts/r8a77995.dtsi

@@ -0,0 +1,410 @@
+/*
+ * Device Tree Source for the r8a77995 SoC
+ *
+ * Copyright (C) 2016 Renesas Electronics Corp.
+ * Copyright (C) 2017 Glider bvba
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/clock/r8a77995-cpg-mssr.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/r8a77995-sysc.h>
+
+/ {
+	compatible = "renesas,r8a77995";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	psci {
+		compatible = "arm,psci-1.0", "arm,psci-0.2";
+		method = "smc";
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		a53_0: cpu@0 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			reg = <0x0>;
+			device_type = "cpu";
+			power-domains = <&sysc R8A77995_PD_CA53_CPU0>;
+			next-level-cache = <&L2_CA53>;
+			enable-method = "psci";
+		};
+
+		L2_CA53: cache-controller-1 {
+			compatible = "cache";
+			power-domains = <&sysc R8A77995_PD_CA53_SCU>;
+			cache-unified;
+			cache-level = <2>;
+		};
+	};
+
+	extal_clk: extal {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board */
+		clock-frequency = <0>;
+		u-boot,dm-pre-reloc;
+	};
+
+	scif_clk: scif {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <0>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		interrupt-parent = <&gic>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		u-boot,dm-pre-reloc;
+
+		gic: interrupt-controller@f1010000 {
+			compatible = "arm,gic-400";
+			#interrupt-cells = <3>;
+			#address-cells = <0>;
+			interrupt-controller;
+			reg = <0x0 0xf1010000 0 0x1000>,
+			      <0x0 0xf1020000 0 0x20000>,
+			      <0x0 0xf1040000 0 0x20000>,
+			      <0x0 0xf1060000 0 0x20000>;
+			interrupts = <GIC_PPI 9
+					(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
+			clocks = <&cpg CPG_MOD 408>;
+			clock-names = "clk";
+			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+			resets = <&cpg 408>;
+		};
+
+		timer {
+			compatible = "arm,armv8-timer";
+			interrupts = <GIC_PPI 13
+					(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+				     <GIC_PPI 14
+					(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+				     <GIC_PPI 11
+					(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+				     <GIC_PPI 10
+					(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+		};
+
+		rwdt: watchdog@e6020000 {
+			compatible = "renesas,r8a77995-wdt",
+				     "renesas,rcar-gen3-wdt";
+			reg = <0 0xe6020000 0 0x0c>;
+			clocks = <&cpg CPG_MOD 402>;
+			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+			resets = <&cpg 402>;
+			status = "disabled";
+		};
+
+		pmu_a53 {
+			compatible = "arm,cortex-a53-pmu";
+			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		cpg: clock-controller@e6150000 {
+			compatible = "renesas,r8a77995-cpg-mssr";
+			reg = <0 0xe6150000 0 0x1000>;
+			clocks = <&extal_clk>;
+			clock-names = "extal";
+			#clock-cells = <2>;
+			#power-domain-cells = <0>;
+			#reset-cells = <1>;
+			u-boot,dm-pre-reloc;
+		};
+
+		rst: reset-controller@e6160000 {
+			compatible = "renesas,r8a77995-rst";
+			reg = <0 0xe6160000 0 0x0200>;
+		};
+
+		pfc: pin-controller@e6060000 {
+			compatible = "renesas,pfc-r8a77995";
+			reg = <0 0xe6060000 0 0x508>;
+		};
+
+		prr: chipid@fff00044 {
+			compatible = "renesas,prr";
+			reg = <0 0xfff00044 0 4>;
+			u-boot,dm-pre-reloc;
+		};
+
+		sysc: system-controller@e6180000 {
+			compatible = "renesas,r8a77995-sysc";
+			reg = <0 0xe6180000 0 0x0400>;
+			#power-domain-cells = <1>;
+		};
+
+		intc_ex: interrupt-controller@e61c0000 {
+			compatible = "renesas,intc-ex-r8a77995", "renesas,irqc";
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			reg = <0 0xe61c0000 0 0x200>;
+			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 407>;
+			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+			resets = <&cpg 407>;
+		};
+
+		gpio0: gpio@e6050000 {
+			compatible = "renesas,gpio-r8a77995",
+				     "renesas,rcar-gen3-gpio",
+				     "renesas,gpio-rcar";
+			reg = <0 0xe6050000 0 0x50>;
+			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			gpio-ranges = <&pfc 0 0 9>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			clocks = <&cpg CPG_MOD 912>;
+			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+			resets = <&cpg 912>;
+		};
+
+		gpio1: gpio@e6051000 {
+			compatible = "renesas,gpio-r8a77995",
+				     "renesas,rcar-gen3-gpio",
+				     "renesas,gpio-rcar";
+			reg = <0 0xe6051000 0 0x50>;
+			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			gpio-ranges = <&pfc 0 32 32>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			clocks = <&cpg CPG_MOD 911>;
+			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+			resets = <&cpg 911>;
+		};
+
+		gpio2: gpio@e6052000 {
+			compatible = "renesas,gpio-r8a77995",
+				     "renesas,rcar-gen3-gpio",
+				     "renesas,gpio-rcar";
+			reg = <0 0xe6052000 0 0x50>;
+			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			gpio-ranges = <&pfc 0 64 32>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			clocks = <&cpg CPG_MOD 910>;
+			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+			resets = <&cpg 910>;
+		};
+
+		gpio3: gpio@e6053000 {
+			compatible = "renesas,gpio-r8a77995",
+				     "renesas,rcar-gen3-gpio",
+				     "renesas,gpio-rcar";
+			reg = <0 0xe6053000 0 0x50>;
+			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			gpio-ranges = <&pfc 0 96 10>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			clocks = <&cpg CPG_MOD 909>;
+			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+			resets = <&cpg 909>;
+		};
+
+		gpio4: gpio@e6054000 {
+			compatible = "renesas,gpio-r8a77995",
+				     "renesas,rcar-gen3-gpio",
+				     "renesas,gpio-rcar";
+			reg = <0 0xe6054000 0 0x50>;
+			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			gpio-ranges = <&pfc 0 128 32>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			clocks = <&cpg CPG_MOD 908>;
+			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+			resets = <&cpg 908>;
+		};
+
+		gpio5: gpio@e6055000 {
+			compatible = "renesas,gpio-r8a77995",
+				     "renesas,rcar-gen3-gpio",
+				     "renesas,gpio-rcar";
+			reg = <0 0xe6055000 0 0x50>;
+			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			gpio-ranges = <&pfc 0 160 21>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			clocks = <&cpg CPG_MOD 907>;
+			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+			resets = <&cpg 907>;
+		};
+
+		gpio6: gpio@e6055400 {
+			compatible = "renesas,gpio-r8a77995",
+				     "renesas,rcar-gen3-gpio",
+				     "renesas,gpio-rcar";
+			reg = <0 0xe6055400 0 0x50>;
+			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			gpio-ranges = <&pfc 0 192 14>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			clocks = <&cpg CPG_MOD 906>;
+			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+			resets = <&cpg 906>;
+		};
+
+		avb: ethernet@e6800000 {
+			compatible = "renesas,etheravb-r8a77995",
+				     "renesas,etheravb-rcar-gen3";
+			reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
+			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "ch0", "ch1", "ch2", "ch3",
+					  "ch4", "ch5", "ch6", "ch7",
+					  "ch8", "ch9", "ch10", "ch11",
+					  "ch12", "ch13", "ch14", "ch15",
+					  "ch16", "ch17", "ch18", "ch19",
+					  "ch20", "ch21", "ch22", "ch23",
+					  "ch24";
+			clocks = <&cpg CPG_MOD 812>;
+			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+			resets = <&cpg 812>;
+			phy-mode = "rgmii-txid";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		scif2: serial@e6e88000 {
+			compatible = "renesas,scif-r8a77995",
+				     "renesas,rcar-gen3-scif", "renesas,scif";
+			reg = <0 0xe6e88000 0 64>;
+			interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 310>,
+				 <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+			resets = <&cpg 310>;
+			status = "disabled";
+		};
+
+		pwm0: pwm@e6e30000 {
+			compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
+			reg = <0 0xe6e30000 0 0x8>;
+			#pwm-cells = <2>;
+			clocks = <&cpg CPG_MOD 523>;
+			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+			resets = <&cpg 523>;
+			status = "disabled";
+		};
+
+		pwm1: pwm@e6e31000 {
+			compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
+			reg = <0 0xe6e31000 0 0x8>;
+			#pwm-cells = <2>;
+			clocks = <&cpg CPG_MOD 523>;
+			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+			resets = <&cpg 523>;
+			status = "disabled";
+		};
+
+		pwm2: pwm@e6e32000 {
+			compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
+			reg = <0 0xe6e32000 0 0x8>;
+			#pwm-cells = <2>;
+			clocks = <&cpg CPG_MOD 523>;
+			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+			resets = <&cpg 523>;
+			status = "disabled";
+		};
+
+		pwm3: pwm@e6e33000 {
+			compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
+			reg = <0 0xe6e33000 0 0x8>;
+			#pwm-cells = <2>;
+			clocks = <&cpg CPG_MOD 523>;
+			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+			resets = <&cpg 523>;
+			status = "disabled";
+		};
+
+		ehci0: usb@ee080100 {
+			compatible = "generic-ehci";
+			reg = <0 0xee080100 0 0x100>;
+			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 703>;
+			phys = <&usb2_phy0>;
+			phy-names = "usb";
+			companion = <&ohci0>;
+			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+			resets = <&cpg 703>;
+			status = "disabled";
+		};
+
+		ohci0: usb@ee080000 {
+			compatible = "generic-ohci";
+			reg = <0 0xee080000 0 0x100>;
+			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 703>;
+			phys = <&usb2_phy0>;
+			phy-names = "usb";
+			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+			resets = <&cpg 703>;
+			status = "disabled";
+		};
+
+		usb2_phy0: usb-phy@ee080200 {
+			compatible = "renesas,usb2-phy-r8a77995",
+				     "renesas,rcar-gen3-usb2-phy";
+			reg = <0 0xee080200 0 0x700>;
+			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 703>;
+			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+			resets = <&cpg 703>;
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+	};
+};

arch/arm/dts/rk3399-evb.dts

@@ -17,6 +17,8 @@
 
 	chosen {
 		stdout-path = &uart2;
+		u-boot,spl-boot-order = \
+			&sdhci, &sdmmc;
 	};
 
 	vdd_center: vdd-center {
@@ -154,6 +156,7 @@
 };
 
 &sdmmc {
+	u-boot,dm-pre-reloc;
 	bus-width = <4>;
 	status = "okay";
 };

arch/arm/dts/sun50i-h5-nanopi-neo-plus2.dts

@@ -0,0 +1,106 @@
+/*
+ * Copyright (C) 2017 Antony Antony <antony@phenome.org>
+ * Copyright (c) 2016 ARM Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "sun50i-h5.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "FriendlyARM NanoPi NEO Plus 2";
+	compatible = "friendlyarm,nanopi-neo-plus2", "allwinner,sun50i-h5";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	reg_vcc3v3: vcc3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+};
+
+&ehci1 {
+	status = "okay";
+};
+
+&mmc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
+	vmmc-supply = <&reg_vcc3v3>;
+	bus-width = <4>;
+	cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
+	cd-inverted;
+	status = "okay";
+};
+
+&mmc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc2_8bit_pins>;
+	vmmc-supply = <&reg_vcc3v3>;
+	bus-width = <8>;
+	non-removable;
+	cap-mmc-hw-reset;
+	status = "okay";
+};
+
+&ohci1 {
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins_a>;
+	status = "okay";
+};
+
+&usbphy {
+	status = "okay";
+};

arch/arm/dts/sun50i-h5-orangepi-prime.dts

@@ -72,6 +72,10 @@
 	};
 };
 
+&ehci1 {
+	status = "okay";
+};
+
 &mmc0 {
 	compatible = "allwinner,sun50i-h5-mmc",
 		     "allwinner,sun50i-a64-mmc",
@@ -85,6 +89,10 @@
 	status = "okay";
 };
 
+&ohci1 {
+	status = "okay";
+};
+
 &uart0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart0_pins_a>;
@@ -94,11 +102,3 @@
 &usbphy {
 	status = "okay";
 };
-
-&ohci1 {
-	status = "okay";
-};
-
-&ehci1 {
-	status = "okay";
-};

arch/arm/dts/sun50i-h5.dtsi

@@ -72,6 +72,38 @@
 	};
 };
 
+&ccu {
+	compatible = "allwinner,sun50i-h5-ccu";
+};
+
 &gic {
 	compatible = "arm,gic-400";
 };
+
+&mmc0 {
+	compatible = "allwinner,sun50i-h5-mmc",
+		     "allwinner,sun50i-a64-mmc";
+	clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
+	clock-names = "ahb", "mmc";
+};
+
+&mmc1 {
+	compatible = "allwinner,sun50i-h5-mmc",
+		     "allwinner,sun50i-a64-mmc";
+	clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
+	clock-names = "ahb", "mmc";
+};
+
+&mmc2 {
+	compatible = "allwinner,sun50i-h5-emmc",
+		     "allwinner,sun50i-a64-emmc";
+	clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
+	clock-names = "ahb", "mmc";
+};
+
+&pio {
+	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+		   <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+	compatible = "allwinner,sun50i-h5-pinctrl";
+};

arch/arm/dts/sun8i-a83t-tbs-a711.dts

@@ -0,0 +1,76 @@
+/*
+ * Copyright 2017 Ondřej Jirman
+ * Ondřej Jirman <megous@megous.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-a83t.dtsi"
+
+/ {
+	model = "TBS A711 Tablet";
+	compatible = "tbs-biometrics,a711", "allwinner,sun8i-a83t";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&ehci0 {
+	status = "okay";
+};
+
+&ohci0 {
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins_b>;
+	status = "okay";
+};
+
+&usb_otg {
+	status = "okay";
+};

arch/arm/dts/tegra-u-boot.dtsi

@@ -0,0 +1,40 @@
+#include <config.h>
+
+/ {
+	binman {
+		multiple-images;
+		image1 {
+			filename = "u-boot-tegra.bin";
+			pad-byte = <0xff>;
+			u-boot-spl {
+			};
+			u-boot {
+				pos = <(CONFIG_SYS_TEXT_BASE -
+					CONFIG_SPL_TEXT_BASE)>;
+			};
+		};
+
+		/* Same as image1 - some tools still expect the -dtb suffix */
+		image2 {
+			filename = "u-boot-dtb-tegra.bin";
+			pad-byte = <0xff>;
+			u-boot-spl {
+			};
+			u-boot {
+				pos = <(CONFIG_SYS_TEXT_BASE -
+					CONFIG_SPL_TEXT_BASE)>;
+			};
+		};
+
+		image3 {
+			filename = "u-boot-nodtb-tegra.bin";
+			pad-byte = <0xff>;
+			u-boot-spl {
+			};
+			u-boot-nodtb {
+				pos = <(CONFIG_SYS_TEXT_BASE -
+					CONFIG_SPL_TEXT_BASE)>;
+			};
+		};
+	};
+};

arch/arm/dts/tegra114-u-boot.dtsi

@@ -0,0 +1,3 @@
+#include <config.h>
+
+#include "tegra-u-boot.dtsi"

arch/arm/dts/tegra124-nyan-big-u-boot.dtsi

@@ -5,6 +5,8 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
+#include "tegra-u-boot.dtsi"
+
 / {
 	host1x@50000000 {
 		u-boot,dm-pre-reloc;

arch/arm/dts/tegra124-u-boot.dtsi

@@ -0,0 +1,3 @@
+#include <config.h>
+
+#include "tegra-u-boot.dtsi"

arch/arm/dts/tegra20-u-boot.dtsi

@@ -1,8 +1,3 @@
-/ {
-	host1x@50000000 {
-		u-boot,dm-pre-reloc;
-		dc@54200000 {
-			u-boot,dm-pre-reloc;
-		};
-	};
-};
+#include <config.h>
+
+#include "tegra-u-boot.dtsi"

arch/arm/dts/tegra210-u-boot.dtsi

@@ -0,0 +1,3 @@
+#include <config.h>
+
+#include "tegra-u-boot.dtsi"

arch/arm/dts/tegra30-u-boot.dtsi

@@ -0,0 +1,3 @@
+#include <config.h>
+
+#include "tegra-u-boot.dtsi"

arch/arm/dts/zynqmp-ep108.dts

@@ -65,7 +65,7 @@
 	status = "okay";
 	clock-frequency = <400000>;
 	eeprom@54 {
-		compatible = "at,24c64";
+		compatible = "atmel,24c64";
 		reg = <0x54>;
 	};
 };
@@ -74,7 +74,7 @@
 	status = "okay";
 	clock-frequency = <400000>;
 	eeprom@55 {
-		compatible = "at,24c64";
+		compatible = "atmel,24c64";
 		reg = <0x55>;
 	};
 };

arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts

@@ -43,16 +43,10 @@
 /* fpd_dma clk 667MHz, lpd_dma 500MHz */
 &fpd_dma_chan1 {
 	status = "okay";
-	xlnx,include-sg; /* for testing purpose */
-	xlnx,overfetch; /* for testing purpose */
-	xlnx,ratectrl = <0>; /* for testing purpose */
-	xlnx,src-issue = <31>;
 };
 
 &fpd_dma_chan2 {
 	status = "okay";
-	xlnx,ratectrl = <100>; /* for testing purpose */
-	xlnx,src-issue = <4>; /* for testing purpose */
 };
 
 &fpd_dma_chan3 {
@@ -61,7 +55,6 @@
 
 &fpd_dma_chan4 {
 	status = "okay";
-	xlnx,include-sg; /* for testing purpose */
 };
 
 &fpd_dma_chan5 {
@@ -70,7 +63,6 @@
 
 &fpd_dma_chan6 {
 	status = "okay";
-	xlnx,include-sg; /* for testing purpose */
 };
 
 &fpd_dma_chan7 {
@@ -79,7 +71,6 @@
 
 &fpd_dma_chan8 {
 	status = "okay";
-	xlnx,include-sg; /* for testing purpose */
 };
 
 &gem3 {

arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts

@@ -53,16 +53,10 @@
 /* fpd_dma clk 667MHz, lpd_dma 500MHz */
 &fpd_dma_chan1 {
 	status = "okay";
-	xlnx,include-sg; /* for testing purpose */
-	xlnx,overfetch; /* for testing purpose */
-	xlnx,ratectrl = <0>; /* for testing purpose */
-	xlnx,src-issue = <31>;
 };
 
 &fpd_dma_chan2 {
 	status = "okay";
-	xlnx,ratectrl = <100>; /* for testing purpose */
-	xlnx,src-issue = <4>; /* for testing purpose */
 };
 
 &fpd_dma_chan3 {
@@ -71,7 +65,6 @@
 
 &fpd_dma_chan4 {
 	status = "okay";
-	xlnx,include-sg; /* for testing purpose */
 };
 
 &fpd_dma_chan5 {
@@ -80,7 +73,6 @@
 
 &fpd_dma_chan6 {
 	status = "okay";
-	xlnx,include-sg; /* for testing purpose */
 };
 
 &fpd_dma_chan7 {
@@ -89,7 +81,6 @@
 
 &fpd_dma_chan8 {
 	status = "okay";
-	xlnx,include-sg; /* for testing purpose */
 };
 
 &gem2 {

arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts

@@ -55,16 +55,10 @@
 /* fpd_dma clk 667MHz, lpd_dma 500MHz */
 &fpd_dma_chan1 {
 	status = "okay";
-	xlnx,include-sg; /* for testing purpose */
-	xlnx,overfetch; /* for testing purpose */
-	xlnx,ratectrl = <0>; /* for testing purpose */
-	xlnx,src-issue = <31>;
 };
 
 &fpd_dma_chan2 {
 	status = "okay";
-	xlnx,ratectrl = <100>; /* for testing purpose */
-	xlnx,src-issue = <4>; /* for testing purpose */
 };
 
 &fpd_dma_chan3 {
@@ -73,7 +67,6 @@
 
 &fpd_dma_chan4 {
 	status = "okay";
-	xlnx,include-sg; /* for testing purpose */
 };
 
 &fpd_dma_chan5 {
@@ -82,7 +75,6 @@
 
 &fpd_dma_chan6 {
 	status = "okay";
-	xlnx,include-sg; /* for testing purpose */
 };
 
 &fpd_dma_chan7 {
@@ -91,7 +83,6 @@
 
 &fpd_dma_chan8 {
 	status = "okay";
-	xlnx,include-sg; /* for testing purpose */
 };
 
 &lpd_dma_chan1 {

arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts

@@ -28,7 +28,7 @@
 	};
 
 	chosen {
-		bootargs = "earlycon=cdns,mmio,0xff000000,115200n8";
+		bootargs = "earlycon";
 		stdout-path = "serial0:115200n8";
 	};
 
@@ -41,16 +41,10 @@
 /* fpd_dma clk 667MHz, lpd_dma 500MHz */
 &fpd_dma_chan1 {
 	status = "okay";
-	xlnx,include-sg; /* for testing purpose */
-	xlnx,overfetch; /* for testing purpose */
-	xlnx,ratectrl = <0>; /* for testing purpose */
-	xlnx,src-issue = <31>;
 };
 
 &fpd_dma_chan2 {
 	status = "okay";
-	xlnx,ratectrl = <100>; /* for testing purpose */
-	xlnx,src-issue = <4>; /* for testing purpose */
 };
 
 &fpd_dma_chan3 {
@@ -59,7 +53,6 @@
 
 &fpd_dma_chan4 {
 	status = "okay";
-	xlnx,include-sg; /* for testing purpose */
 };
 
 &fpd_dma_chan5 {
@@ -68,7 +61,6 @@
 
 &fpd_dma_chan6 {
 	status = "okay";
-	xlnx,include-sg; /* for testing purpose */
 };
 
 &fpd_dma_chan7 {
@@ -77,7 +69,6 @@
 
 &fpd_dma_chan8 {
 	status = "okay";
-	xlnx,include-sg; /* for testing purpose */
 };
 
 &gem1 {

arch/arm/dts/zynqmp-zcu102-revA.dts

@@ -14,6 +14,7 @@
 #include "zynqmp-clk.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
+#include <dt-bindings/phy/phy.h>
 
 / {
 	model = "ZynqMP ZCU102 RevA";
@@ -80,16 +81,10 @@
 /* fpd_dma clk 667MHz, lpd_dma 500MHz */
 &fpd_dma_chan1 {
 	status = "okay";
-	xlnx,include-sg; /* for testing purpose */
-	xlnx,overfetch; /* for testing purpose */
-	xlnx,ratectrl = <0>; /* for testing purpose */
-	xlnx,src-issue = <31>;
 };
 
 &fpd_dma_chan2 {
 	status = "okay";
-	xlnx,ratectrl = <100>; /* for testing purpose */
-	xlnx,src-issue = <4>; /* for testing purpose */
 };
 
 &fpd_dma_chan3 {
@@ -98,7 +93,6 @@
 
 &fpd_dma_chan4 {
 	status = "okay";
-	xlnx,include-sg; /* for testing purpose */
 };
 
 &fpd_dma_chan5 {
@@ -107,7 +101,6 @@
 
 &fpd_dma_chan6 {
 	status = "okay";
-	xlnx,include-sg; /* for testing purpose */
 };
 
 &fpd_dma_chan7 {
@@ -116,7 +109,6 @@
 
 &fpd_dma_chan8 {
 	status = "okay";
-	xlnx,include-sg; /* for testing purpose */
 };
 
 &gem3 {
@@ -884,6 +876,8 @@ drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751)  += max20751.o
 	ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 	ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 	ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+	phy-names = "sata-phy";
+	phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
 };
 
 /* SD1 with level shifter */
@@ -895,6 +889,10 @@ drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751)  += max20751.o
 	xlnx,mio_bank = <1>;
 };
 
+&serdes {
+	status = "okay";
+};
+
 &uart0 {
 	status = "okay";
 	pinctrl-names = "default";
@@ -917,6 +915,10 @@ drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751)  += max20751.o
 &dwc3_0 {
 	status = "okay";
 	dr_mode = "host";
+	snps,usb3_lpm_capable;
+	phy-names = "usb3-phy";
+	phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
+	maximum-speed = "super-speed";
 };
 
 &watchdog0 {

arch/arm/dts/zynqmp.dtsi

@@ -261,7 +261,7 @@
 		method = "smc";
 	};
 
-	firmware {
+	pmufw: firmware {
 		compatible = "xlnx,zynqmp-pm";
 		method = "smc";
 		interrupt-parent = <&gic>;
@@ -804,6 +804,7 @@
 		};
 
 		qspi: spi@ff0f0000 {
+			u-boot,dm-pre-reloc;
 			compatible = "xlnx,zynqmp-qspi-1.0";
 			status = "disabled";
 			clock-names = "ref_clk", "pclk";

arch/arm/include/asm/arch-fsl-layerscape/soc.h

@@ -76,8 +76,6 @@ struct cpu_type {
 #define SVR_LS2081A		0x870918
 #define SVR_LS2041A		0x870914
 
-#define SVR_DEV_LS2080A		0x8701
-
 #define SVR_MAJ(svr)		(((svr) >> 4) & 0xf)
 #define SVR_MIN(svr)		(((svr) >> 0) & 0xf)
 #define SVR_REV(svr)		(((svr) >> 0) & 0xff)
@@ -85,6 +83,8 @@ struct cpu_type {
 #define IS_E_PROCESSOR(svr)	(!((svr >> 8) & 0x1))
 #define IS_SVR_REV(svr, maj, min) \
 		((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min)))
+#define SVR_DEV(svr)		((svr) >> 8)
+#define IS_SVR_DEV(svr, dev)	(((svr) >> 16) == (dev))
 
 /* ahci port register default value */
 #define AHCI_PORT_PHY_1_CFG    0xa003fffe

arch/arm/include/asm/arch-ls102xa/config.h

@@ -80,8 +80,6 @@
 
 /* SATA */
 #define AHCI_BASE_ADDR				(CONFIG_SYS_IMMR + 0x02200000)
-#define CONFIG_LIBATA
-#define CONFIG_SCSI_AHCI
 #define CONFIG_SCSI_AHCI_PLAT
 #define CONFIG_SYS_SCSI_MAX_SCSI_ID		1
 #define CONFIG_SYS_SCSI_MAX_LUN		1

arch/arm/include/asm/arch-mx6/imx-regs.h

@@ -17,7 +17,7 @@
 #define GPU_2D_ARB_END_ADDR             0x02203FFF
 #define OPENVG_ARB_BASE_ADDR            0x02204000
 #define OPENVG_ARB_END_ADDR             0x02207FFF
-#elif (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
+#elif (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
 #define CAAM_ARB_BASE_ADDR              0x00100000
 #define CAAM_ARB_END_ADDR               0x00107FFF
 #define GPU_ARB_BASE_ADDR               0x01800000
@@ -46,7 +46,8 @@
 #define MXS_BCH_BASE			(APBH_DMA_ARB_BASE_ADDR + 0x04000)
 
 /* GPV - PL301 configuration ports */
-#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
+#if (defined(CONFIG_MX6SX) || \
+	defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
 	defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL))
 #define GPV2_BASE_ADDR                  0x00D00000
 #define GPV3_BASE_ADDR			0x00E00000
@@ -88,7 +89,7 @@
 #define QSPI0_AMBA_END                 0x6FFFFFFF
 #define QSPI1_AMBA_BASE                0x70000000
 #define QSPI1_AMBA_END                 0x7FFFFFFF
-#elif defined(CONFIG_MX6UL)
+#elif (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
 #define WEIM_ARB_BASE_ADDR              0x50000000
 #define WEIM_ARB_END_ADDR               0x57FFFFFF
 #define QSPI0_AMBA_BASE                 0x60000000
@@ -109,7 +110,8 @@
 #endif
 
 #if (defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || \
-	defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
+	defined(CONFIG_MX6SX) || \
+	defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
 #define MMDC0_ARB_BASE_ADDR             0x80000000
 #define MMDC0_ARB_END_ADDR              0xFFFFFFFF
 #define MMDC1_ARB_BASE_ADDR             0xC0000000
@@ -262,7 +264,7 @@
 #define MMDC_P0_BASE_ADDR           (AIPS2_OFF_BASE_ADDR + 0x30000)
 /* i.MX6SL/SLL */
 #define RNGB_IPS_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0x34000)
-#ifdef CONFIG_MX6UL
+#if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
 #define ENET2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x34000)
 #else
 /* i.MX6SX */
@@ -288,7 +290,8 @@
 #define IP2APB_PERFMON3_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x4C000)
 #endif
 #define IP2APB_TZASC1_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x50000)
-#ifdef CONFIG_MX6UL
+#if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
+#define SCTR_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x5C000)
 #define QSPI0_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x60000)
 #define UART6_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x7C000)
 #elif defined(CONFIG_MX6SX)
@@ -337,7 +340,7 @@
 #define PWM6_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xA8000)
 #define PWM7_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xAC000)
 #define PWM8_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xB0000)
-#elif defined(CONFIG_MX6ULL)
+#elif (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
 #define AIPS3_CONFIG_BASE_ADDR      (AIPS3_ARB_BASE_ADDR + 0x7C000)
 #define DCP_BASE_ADDR               (AIPS3_ARB_BASE_ADDR + 0x80000)
 #define RNGB_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x84000)
@@ -354,7 +357,8 @@
 #define MX6SX_LCDIF1_BASE_ADDR      (AIPS3_ARB_BASE_ADDR + 0x20000)
 #define MX6SX_WDOG3_BASE_ADDR       (AIPS3_ARB_BASE_ADDR + 0x88000)
 
-#if !(defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
+#if !(defined(CONFIG_MX6SX) || \
+	defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
 	defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL))
 #define IRAM_SIZE                    0x00040000
 #else
@@ -573,7 +577,7 @@ struct src {
 #define IOMUXC_GPR12_LOS_LEVEL			(0x1f << 4)
 
 struct iomuxc {
-#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
+#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
 	u8 reserved[0x4000];
 #endif
 	u32 gpr[14];
@@ -700,7 +704,7 @@ struct cspi_regs {
 #define MXC_CSPICON_SSPOL	12 /* SS polarity */
 #define MXC_CSPICON_CTL		20 /* inactive state of SCLK */
 #if defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || \
-	defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL)
+	defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
 #define MXC_SPI_BASE_ADDRESSES \
 	ECSPI1_BASE_ADDR, \
 	ECSPI2_BASE_ADDR, \

arch/arm/include/asm/arch-mx6/mx6-ddr.h

@@ -16,7 +16,7 @@
 #ifdef CONFIG_MX6SX
 #include "mx6sx-ddr.h"
 #else
-#ifdef CONFIG_MX6UL
+#if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
 #include "mx6ul-ddr.h"
 #else
 #ifdef CONFIG_MX6SL

arch/arm/include/asm/arch-mx6/mx6ul-ddr.h

@@ -7,7 +7,7 @@
 #ifndef __ASM_ARCH_MX6UL_DDR_H__
 #define __ASM_ARCH_MX6UL_DDR_H__
 
-#ifndef CONFIG_MX6UL
+#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
 #error "wrong CPU"
 #endif
 

arch/arm/include/asm/arch-pxa/hardware.h

@@ -79,33 +79,4 @@
 
 #endif
 
-
-/*
- * Implementation specifics
- */
-
-#ifdef CONFIG_ARCH_LUBBOCK
-#include "lubbock.h"
-#endif
-
-#ifdef CONFIG_ARCH_PXA_IDP
-#include "idp.h"
-#endif
-
-#ifdef CONFIG_ARCH_PXA_CERF
-#include "cerf.h"
-#endif
-
-#ifdef CONFIG_ARCH_CSB226
-#include "csb226.h"
-#endif
-
-#ifdef CONFIG_ARCH_INNOKOM
-#include "innokom.h"
-#endif
-
-#ifdef CONFIG_ARCH_PLEB
-#include "pleb.h"
-#endif
-
 #endif	/* _ASM_ARCH_HARDWARE_H */

arch/arm/include/asm/arch-rockchip/boot0.h

@@ -39,7 +39,12 @@
 entry_counter:
 	.word   0
 #endif
+
+#if (defined(CONFIG_SPL_BUILD) || defined(CONFIG_ARM64))
+	/* U-Boot proper of armv7 do not need this */
 	b reset
+#endif
+
 #if !defined(CONFIG_ARM64)
 	/*
 	 * For armv7, the addr '_start' will used as vector start address
@@ -50,6 +55,6 @@ _start:
 	ARM_VECTORS
 #endif
 
-#if defined(CONFIG_ROCKCHIP_RK3399) && defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SPL_BUILD) && (CONFIG_ROCKCHIP_SPL_RESERVE_IRAM > 0)
 	.space CONFIG_ROCKCHIP_SPL_RESERVE_IRAM	/* space for the ATF data */
 #endif

arch/arm/include/asm/arch-zynqmp/sys_proto.h

@@ -30,6 +30,7 @@ enum {
 	TCM_SPLIT,
 };
 
+int zynq_board_read_rom_ethaddr(unsigned char *ethaddr);
 unsigned int zynqmp_get_silicon_version(void);
 
 void psu_init(void);

arch/arm/include/asm/mach-imx/iomux-v3.h

@@ -127,7 +127,7 @@ typedef u64 iomux_v3_cfg_t;
 
 #define PAD_CTL_ODE		(1 << 11)
 
-#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)
+#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
 #define PAD_CTL_SPEED_LOW	(0 << 6)
 #else
 #define PAD_CTL_SPEED_LOW	(1 << 6)
@@ -253,7 +253,7 @@ if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {				\
 	imx_iomux_v3_setup_pad(MX6Q_##def);
 #define SETUP_IOMUX_PADS(x)					\
 	imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
-#elif defined(CONFIG_MX6UL)
+#elif defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
 #define IOMUX_PADS(x) MX6_##x
 #define SETUP_IOMUX_PAD(def)					\
 	imx_iomux_v3_setup_pad(MX6_##def);

arch/arm/include/asm/mach-imx/regs-lcdif.h

@@ -19,8 +19,11 @@
 struct mxs_lcdif_regs {
 	mxs_reg_32(hw_lcdif_ctrl)		/* 0x00 */
 	mxs_reg_32(hw_lcdif_ctrl1)		/* 0x10 */
-#if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
-	defined(CONFIG_MX7) || defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL)
+
+#if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || \
+	defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
+	defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
+	defined(CONFIG_MX7)
 	mxs_reg_32(hw_lcdif_ctrl2)		/* 0x20 */
 #endif
 	mxs_reg_32(hw_lcdif_transfer_count)	/* 0x20/0x30 */
@@ -55,8 +58,10 @@ struct mxs_lcdif_regs {
 #endif
 	mxs_reg_32(hw_lcdif_data)		/* 0x1b0/0x180 */
 	mxs_reg_32(hw_lcdif_bm_error_stat)	/* 0x1c0/0x190 */
-#if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
-	defined(CONFIG_MX7) || defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL)
+#if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || \
+	defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
+	defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
+	defined(CONFIG_MX7)
 	mxs_reg_32(hw_lcdif_crc_stat)		/* 0x1a0 */
 #endif
 	mxs_reg_32(hw_lcdif_lcdif_stat)		/* 0x1d0/0x1b0 */
@@ -64,8 +69,10 @@ struct mxs_lcdif_regs {
 	mxs_reg_32(hw_lcdif_debug0)		/* 0x1f0/0x1d0 */
 	mxs_reg_32(hw_lcdif_debug1)		/* 0x200/0x1e0 */
 	mxs_reg_32(hw_lcdif_debug2)		/* 0x1f0 */
-#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX7) || \
-	defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL)
+#if defined(CONFIG_MX6SX) || \
+	defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
+	defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
+	defined(CONFIG_MX7)
 	mxs_reg_32(hw_lcdif_thres)
 	mxs_reg_32(hw_lcdif_as_ctrl)
 	mxs_reg_32(hw_lcdif_as_buf)

arch/arm/include/asm/mach-imx/sys_proto.h

@@ -81,7 +81,8 @@ enum imx6_bmode {
 	IMX6_BMODE_ESD,
 	IMX6_BMODE_MMC,
 	IMX6_BMODE_EMMC,
-	IMX6_BMODE_NAND,
+	IMX6_BMODE_NAND_MIN,
+	IMX6_BMODE_NAND_MAX = 0xf,
 };
 
 static inline u8 imx6_is_bmode_from_gpr9(void)
@@ -109,6 +110,9 @@ void imx_wdog_disable_powerdown(void);
 
 int board_mmc_get_env_dev(int devno);
 
+int nxp_board_rev(void);
+char nxp_board_rev_string(void);
+
 /*
  * Initializes on-chip ethernet controllers.
  * to override, implement board_eth_init()

arch/arm/lib/bootm-fdt.c

@@ -25,6 +25,13 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_FMAN_ENET
+__weak int fdt_update_ethernet_dt(void *blob)
+{
+	return 0;
+}
+#endif
+
 int arch_fixup_fdt(void *blob)
 {
 	int ret = 0;
@@ -64,5 +71,10 @@ int arch_fixup_fdt(void *blob)
 #endif
 #endif
 
+#ifdef CONFIG_FMAN_ENET
+	ret = fdt_update_ethernet_dt(blob);
+	if (ret)
+		return ret;
+#endif
 	return 0;
 }

arch/arm/lib/crt0_64.S

@@ -120,8 +120,9 @@ relocation_return:
 #endif /* !CONFIG_SPL_BUILD */
 #if defined(CONFIG_SPL_BUILD)
 	bl	spl_relocate_stack_gd           /* may return NULL */
-	/* set up gd here, outside any C code */
-	mov	x18, x0
+	/* set up gd here, outside any C code, if new stack is returned */
+	cmp	x0, #0
+	csel	x18, x0, x18, ne
 	/*
 	 * Perform 'sp = (x0 != NULL) ? x0 : sp' while working
 	 * around the constraint that conditional moves can not

arch/arm/lib/elf_arm_efi.lds

@@ -55,16 +55,13 @@ SECTIONS
 	.rel.data : { *(.rel.data) *(.rel.data*) }
 	_data_size = . - _etext;
 
-	. = ALIGN(4096);
-	.dynsym   : { *(.dynsym) }
-	. = ALIGN(4096);
-	.dynstr   : { *(.dynstr) }
-	. = ALIGN(4096);
-	.note.gnu.build-id : { *(.note.gnu.build-id) }
 	/DISCARD/ : {
 		*(.rel.reloc)
 		*(.eh_frame)
 		*(.note.GNU-stack)
+		*(.dynsym)
+		*(.dynstr)
+		*(.note.gnu.build-id)
+		*(.comment)
 	}
-	.comment 0 : { *(.comment) }
 }

arch/arm/mach-imx/Kconfig

@@ -1,9 +1,18 @@
+config HAS_CAAM
+	bool
+
 config IMX_CONFIG
 	string
 
 config ROM_UNIFIED_SECTIONS
 	bool
 
+config SYSCOUNTER_TIMER
+	bool
+
+config GPT_TIMER
+	bool
+
 config IMX_RDC
 	bool "i.MX Resource domain controller driver"
 	depends on ARCH_MX6 || ARCH_MX7
@@ -28,7 +37,7 @@ config USE_IMXIMG_PLUGIN
 config SECURE_BOOT
 	bool "Support i.MX HAB features"
 	depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX5
-	select FSL_CAAM
+	select FSL_CAAM if HAS_CAAM
 	imply CMD_DEKBLOB
 	help
 	  This option enables the support for secure boot (HAB).
@@ -61,3 +70,11 @@ config CMD_HDMIDETECT
 	help
 	  This enables the 'hdmidet' command which detects if an HDMI monitor
 	  is connected.
+
+config NXP_BOARD_REVISION
+	bool "Read NXP board revision from fuses"
+	depends on ARCH_MX6 || ARCH_MX7
+	help
+	  NXP boards based on i.MX6/7 contain the board revision information
+	  stored in the fuses. Select this option if you want to be able to
+	  retrieve the board revision information.

arch/arm/mach-imx/Makefile

@@ -11,7 +11,8 @@ ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 vf610))
 obj-y	= iomux-v3.o
 endif
 ifeq ($(SOC),$(filter $(SOC),mx5 mx6))
-obj-y	+= timer.o cpu.o speed.o
+obj-y	+= cpu.o speed.o
+obj-$(CONFIG_GPT_TIMER) += timer.o
 obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
 endif
 ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs))
@@ -21,7 +22,6 @@ endif
 ifeq ($(SOC),$(filter $(SOC),mx7))
 obj-y 	+= cpu.o
 obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
-obj-$(CONFIG_SYSCOUNTER_TIMER) += syscounter.o
 endif
 ifeq ($(SOC),$(filter $(SOC),mx6 mx7))
 obj-y 	+= cache.o init.o
@@ -30,6 +30,7 @@ obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
 obj-$(CONFIG_IMX_RDC) += rdc-sema.o
 obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
 obj-$(CONFIG_SECURE_BOOT)    += hab.o
+obj-$(CONFIG_SYSCOUNTER_TIMER) += syscounter.o
 endif
 ifeq ($(SOC),$(filter $(SOC),mx7ulp))
 obj-y  += cache.o

arch/arm/mach-imx/cpu.c

@@ -323,3 +323,28 @@ void set_chipselect_size(int const cs_size)
 
 	writel(reg, &iomuxc_regs->gpr[1]);
 }
+
+#ifdef CONFIG_NXP_BOARD_REVISION
+int nxp_board_rev(void)
+{
+	/*
+	 * Get Board ID information from OCOTP_GP1[15:8]
+	 * RevA: 0x1
+	 * RevB: 0x2
+	 * RevC: 0x3
+	 */
+	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+	struct fuse_bank *bank = &ocotp->bank[4];
+	struct fuse_bank4_regs *fuse =
+			(struct fuse_bank4_regs *)bank->fuse_regs;
+
+	return (readl(&fuse->gp1) >> 8 & 0x0F);
+}
+
+char nxp_board_rev_string(void)
+{
+	const char *rev = "A";
+
+	return (*rev + nxp_board_rev() - 1);
+}
+#endif

arch/arm/mach-imx/mx5/Kconfig

@@ -1,6 +1,7 @@
 if ARCH_MX5
 
 config MX5
+	select GPT_TIMER
 	bool
 	default y
 

arch/arm/mach-imx/mx6/Kconfig

@@ -8,34 +8,41 @@ config MX6_SMP
 	bool
 
 config MX6
-	select ARM_ERRATA_743622 if !MX6UL
+	select ARM_ERRATA_743622 if !MX6UL && !MX6ULL
+	select GPT_TIMER if !MX6UL && !MX6ULL
 	bool
 	default y
 	imply CMD_FUSE
 
 config MX6D
+	select HAS_CAAM
 	select MX6_SMP
 	bool
 
 config MX6DL
+	select HAS_CAAM
 	select MX6_SMP
 	bool
 
 config MX6Q
+	select HAS_CAAM
 	select MX6_SMP
 	bool
 
 config MX6QDL
+	select HAS_CAAM
 	select MX6_SMP
 	bool
 
 config MX6S
+	select HAS_CAAM
 	bool
 
 config MX6SL
 	bool
 
 config MX6SX
+	select HAS_CAAM
 	select ROM_UNIFIED_SECTIONS
 	bool
 
@@ -44,8 +51,10 @@ config MX6SLL
 	bool
 
 config MX6UL
+	select HAS_CAAM
 	select SYS_L2CACHE_OFF
 	select ROM_UNIFIED_SECTIONS
+	select SYSCOUNTER_TIMER
 	bool
 
 config MX6UL_LITESOM
@@ -66,8 +75,10 @@ config MX6UL_OPOS6UL
 	select SUPPORT_SPL
 
 config MX6ULL
+	select SYS_L2CACHE_OFF
+	select ROM_UNIFIED_SECTIONS
+	select SYSCOUNTER_TIMER
 	bool
-	select MX6UL
 
 config MX6_DDRCAL
 	bool "Include dynamic DDR calibration routines"
@@ -202,6 +213,14 @@ config TARGET_MX6LOGICPD
 	select DM_REGULATOR
 	select OF_CONTROL
 
+config TARGET_MX6MEMCAL
+	bool "mx6memcal"
+	select SUPPORT_SPL
+	help
+	  The mx6memcal board is a virtual board that can be used to validate
+	  and characterize the memory layout of a new design during the initial
+	  development and pre-production stages.
+
 config TARGET_MX6QARM2
 	bool "mx6qarm2"
 
@@ -244,6 +263,7 @@ config TARGET_MX6SABRESD
 
 config TARGET_MX6SLEVK
 	bool "mx6slevk"
+	select MX6SL
 	select SUPPORT_SPL
 
 config TARGET_MX6SLLEVK
@@ -255,6 +275,7 @@ config TARGET_MX6SLLEVK
 
 config TARGET_MX6SXSABRESD
 	bool "mx6sxsabresd"
+	select BOARD_LATE_INIT
 	select MX6SX
 	select SUPPORT_SPL
 	select DM
@@ -395,6 +416,7 @@ config TARGET_WANDBOARD
 
 config TARGET_WARP
 	bool "WaRP"
+	select MX6SL
 	select BOARD_LATE_INIT
 
 config TARGET_XPRESS
@@ -441,6 +463,7 @@ source "board/embest/mx6boards/Kconfig"
 source "board/engicam/imx6q/Kconfig"
 source "board/engicam/imx6ul/Kconfig"
 source "board/freescale/mx6qarm2/Kconfig"
+source "board/freescale/mx6memcal/Kconfig"
 source "board/freescale/mx6sabreauto/Kconfig"
 source "board/freescale/mx6sabresd/Kconfig"
 source "board/freescale/mx6slevk/Kconfig"

arch/arm/mach-imx/mx6/ddr.c

@@ -631,7 +631,7 @@ void mx6sx_dram_iocfg(unsigned width,
 }
 #endif
 
-#ifdef CONFIG_MX6UL
+#if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
 void mx6ul_dram_iocfg(unsigned width,
 		      const struct mx6ul_iomux_ddr_regs *ddr,
 		      const struct mx6ul_iomux_grp_regs *grp)

arch/arm/mach-imx/mx7/Kconfig

@@ -3,6 +3,7 @@ if ARCH_MX7
 config MX7
 	bool
 	select ROM_UNIFIED_SECTIONS
+	select SYSCOUNTER_TIMER
 	select CPU_V7_HAS_VIRT
 	select CPU_V7_HAS_NONSEC
 	select ARCH_SUPPORT_PSCI
@@ -10,6 +11,7 @@ config MX7
 	default y
 
 config MX7D
+	select HAS_CAAM
 	select ROM_UNIFIED_SECTIONS
 	imply CMD_FUSE
 	bool

arch/arm/mach-imx/spl.c

@@ -91,7 +91,7 @@ u32 spl_boot_device(void)
 	case IMX6_BMODE_EMMC:
 		return BOOT_DEVICE_MMC1;
 	/* NAND Flash: 8.5.2, Table 8-10 */
-	case IMX6_BMODE_NAND:
+	case IMX6_BMODE_NAND_MIN ... IMX6_BMODE_NAND_MAX:
 		return BOOT_DEVICE_NAND;
 	}
 	return BOOT_DEVICE_NONE;

arch/arm/mach-kirkwood/include/mach/config.h

@@ -97,7 +97,6 @@
  */
 #ifdef CONFIG_IDE
 #define __io
-#define CONFIG_MVSATA_IDE
 #define CONFIG_IDE_PREINIT
 #define CONFIG_MVSATA_IDE_USE_PORT1
 /* Needs byte-swapping for ATA data register */

arch/arm/mach-meson/eth.c

@@ -38,8 +38,8 @@ void meson_gx_eth_init(phy_interface_t mode, unsigned int flags)
 		/* Use GXL RMII Internal PHY */
 		if (IS_ENABLED(CONFIG_MESON_GXL) &&
 		    (flags & MESON_GXL_USE_INTERNAL_RMII_PHY)) {
-			writel(GXBB_ETH_REG_2, 0x10110181);
-			writel(GXBB_ETH_REG_3, 0xe40908ff);
+			writel(0x10110181, GXBB_ETH_REG_2);
+			writel(0xe40908ff, GXBB_ETH_REG_3);
 		}
 
 		break;

arch/arm/mach-omap2/omap3/Kconfig

@@ -61,6 +61,10 @@ config TARGET_DEVKIT8000
 
 config TARGET_OMAP3_EVM
 	bool "TI OMAP3 EVM"
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
+	select OMAP3_GPIO_3
 
 config TARGET_OMAP3_IGEP00X0
 	bool "IGEP"

arch/arm/mach-rmobile/Kconfig.64

@@ -9,12 +9,28 @@ config R8A7795
 config R8A7796
 	bool "Renesas SoC R8A7796"
 
+config R8A77970
+	bool "Renesas SoC R8A77970"
+
+config R8A77995
+	bool "Renesas SoC R8A77995"
+
 endchoice
 
 choice
 	prompt "Renesus ARM64 SoCs board select"
 	optional
 
+config TARGET_DRAAK
+	bool "Draak board"
+	help
+          Support for Renesas R-Car Gen3 Draak platform
+
+config TARGET_EAGLE
+	bool "Eagle board"
+	help
+          Support for Renesas R-Car Gen3 Eagle platform
+
 config TARGET_SALVATOR_X
 	bool "Salvator-X board"
 	help
@@ -30,6 +46,8 @@ endchoice
 config SYS_SOC
 	default "rmobile"
 
+source "board/renesas/draak/Kconfig"
+source "board/renesas/eagle/Kconfig"
 source "board/renesas/salvator-x/Kconfig"
 source "board/renesas/ulcb/Kconfig"
 

arch/arm/mach-rmobile/cpu_info.c

@@ -61,6 +61,8 @@ static const struct {
 	{ RMOBILE_CPU_TYPE_R8A7794, "R8A7794" },
 	{ RMOBILE_CPU_TYPE_R8A7795, "R8A7795" },
 	{ RMOBILE_CPU_TYPE_R8A7796, "R8A7796" },
+	{ RMOBILE_CPU_TYPE_R8A77970, "R8A77970" },
+	{ RMOBILE_CPU_TYPE_R8A77995, "R8A77995" },
 	{ 0x0, "CPU" },
 };
 

arch/arm/mach-rmobile/include/mach/rmobile.h

@@ -33,6 +33,8 @@
 #define RMOBILE_CPU_TYPE_R8A7794	0x4C
 #define RMOBILE_CPU_TYPE_R8A7795	0x4F
 #define RMOBILE_CPU_TYPE_R8A7796	0x52
+#define RMOBILE_CPU_TYPE_R8A77970	0x54
+#define RMOBILE_CPU_TYPE_R8A77995	0x58
 
 #ifndef __ASSEMBLY__
 u32 rmobile_get_cpu_type(void);

arch/arm/mach-rmobile/memmap-gen3.c

@@ -49,6 +49,46 @@ static struct mm_region r8a7796_mem_map[] = {
 	}
 };
 
+static struct mm_region r8a77970_mem_map[] = {
+	{
+		.virt = 0x0UL,
+		.phys = 0x0UL,
+		.size = 0xe0000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		.virt = 0xe0000000UL,
+		.phys = 0xe0000000UL,
+		.size = 0xe0000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+static struct mm_region r8a77995_mem_map[] = {
+	{
+		.virt = 0x0UL,
+		.phys = 0x0UL,
+		.size = 0xe0000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		.virt = 0xe0000000UL,
+		.phys = 0xe0000000UL,
+		.size = 0xe0000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
 struct mm_region *mem_map = r8a7795_mem_map;
 
 void rcar_gen3_memmap_fixup(void)
@@ -62,5 +102,11 @@ void rcar_gen3_memmap_fixup(void)
 	case RMOBILE_CPU_TYPE_R8A7796:
 		mem_map = r8a7796_mem_map;
 		break;
+	case RMOBILE_CPU_TYPE_R8A77970:
+		mem_map = r8a77970_mem_map;
+		break;
+	case RMOBILE_CPU_TYPE_R8A77995:
+		mem_map = r8a77995_mem_map;
+		break;
 	}
 }

arch/arm/mach-rockchip/Kconfig

@@ -179,7 +179,7 @@ config ROCKCHIP_BOOT_MODE_REG
 
 config ROCKCHIP_SPL_RESERVE_IRAM
 	hex "Size of IRAM reserved in SPL"
-	default 0x4000
+	default 0
 	help
 	  SPL may need reserve memory for firmware loaded by SPL, whose load
 	  address is in IRAM and may overlay with SPL text area if not

arch/arm/mach-rockchip/make_fit_atf.py

@@ -0,0 +1,221 @@
+#!/usr/bin/env python2
+"""
+A script to generate FIT image source for rockchip boards
+with ARM Trusted Firmware
+and multiple device trees (given on the command line)
+
+usage: $0 <dt_name> [<dt_name> [<dt_name] ...]
+"""
+
+import os
+import sys
+import getopt
+
+# pip install pyelftools
+from elftools.elf.elffile import ELFFile
+from elftools.elf.sections import SymbolTableSection
+from elftools.elf.segments import Segment, InterpSegment, NoteSegment
+
+ELF_SEG_P_TYPE='p_type'
+ELF_SEG_P_PADDR='p_paddr'
+ELF_SEG_P_VADDR='p_vaddr'
+ELF_SEG_P_OFFSET='p_offset'
+ELF_SEG_P_FILESZ='p_filesz'
+ELF_SEG_P_MEMSZ='p_memsz'
+
+DT_HEADER="""/*
+ * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * Minimal dts for a SPL FIT image payload.
+ *
+ * SPDX-License-Identifier: GPL-2.0+  X11
+ */
+/dts-v1/;
+
+/ {
+	description = "Configuration to load ATF before U-Boot";
+	#address-cells = <1>;
+
+	images {
+		uboot@1 {
+			description = "U-Boot (64-bit)";
+			data = /incbin/("u-boot-nodtb.bin");
+			type = "standalone";
+			os = "U-Boot";
+			arch = "arm64";
+			compression = "none";
+			load = <0x%08x>;
+		};
+"""
+
+DT_IMAGES_NODE_END="""
+    };
+"""
+
+DT_END="""
+};
+"""
+
+def append_atf_node(file, atf_index, phy_addr):
+    """
+    Append ATF DT node to input FIT dts file.
+    """
+    data = 'bl31_0x%08x.bin' % phy_addr
+    print >> file, '\t\tatf@%d {' % atf_index
+    print >> file, '\t\t\tdescription = \"ARM Trusted Firmware\";'
+    print >> file, '\t\t\tdata = /incbin/("%s");' % data
+    print >> file, '\t\t\ttype = "firmware";'
+    print >> file, '\t\t\tarch = "arm64";'
+    print >> file, '\t\t\tos = "arm-trusted-firmware";'
+    print >> file, '\t\t\tcompression = "none";'
+    print >> file, '\t\t\tload = <0x%08x>;' % phy_addr
+    if atf_index == 1:
+        print >> file, '\t\t\tentry = <0x%08x>;' % phy_addr
+    print >> file, '\t\t};'
+    print >> file, ''
+
+def append_fdt_node(file, dtbs):
+    """
+    Append FDT nodes.
+    """
+    cnt = 1
+    for dtb in dtbs:
+        dtname = os.path.basename(dtb)
+        print >> file, '\t\tfdt@%d {' % cnt
+        print >> file, '\t\t\tdescription = "%s";' % dtname
+        print >> file, '\t\t\tdata = /incbin/("%s");' % dtb
+        print >> file, '\t\t\ttype = "flat_dt";'
+        print >> file, '\t\t\tcompression = "none";'
+        print >> file, '\t\t};'
+        print >> file, ''
+        cnt = cnt + 1
+
+def append_conf_section(file, cnt, dtname, atf_cnt):
+    print >> file, '\t\tconfig@%d {' % cnt
+    print >> file, '\t\t\tdescription = "%s";' % dtname
+    print >> file, '\t\t\tfirmware = "atf@1";'
+    print >> file, '\t\t\tloadables = "uboot@1",',
+    for i in range(1, atf_cnt):
+        print >> file, '"atf@%d"' % (i+1),
+        if i != (atf_cnt - 1):
+            print >> file, ',',
+        else:
+            print >> file, ';'
+    print >> file, '\t\t\tfdt = "fdt@1";'
+    print >> file, '\t\t};'
+    print >> file, ''
+
+def append_conf_node(file, dtbs, atf_cnt):
+    """
+    Append configeration nodes.
+    """
+    cnt = 1
+    print >> file, '\tconfigurations {'
+    print >> file, '\t\tdefault = "config@1";'
+    for dtb in dtbs:
+        dtname = os.path.basename(dtb)
+        append_conf_section(file, cnt, dtname, atf_cnt)
+        cnt = cnt + 1
+    print >> file, '\t};'
+    print >> file, ''
+
+def generate_atf_fit_dts(fit_file_name, bl31_file_name, uboot_file_name, dtbs_file_name):
+    """
+    Generate FIT script for ATF image.
+    """
+    if fit_file_name != sys.stdout:
+        fit_file = open(fit_file_name, "wb")
+    else:
+        fit_file = sys.stdout
+
+    num_load_seg = 0
+    p_paddr = 0xFFFFFFFF
+    with open(uboot_file_name) as uboot_file:
+        uboot = ELFFile(uboot_file)
+        for i in range(uboot.num_segments()):
+            seg = uboot.get_segment(i)
+            if ('PT_LOAD' == seg.__getitem__(ELF_SEG_P_TYPE)):
+                p_paddr = seg.__getitem__(ELF_SEG_P_PADDR)
+                num_load_seg = num_load_seg + 1
+
+    assert (p_paddr != 0xFFFFFFFF and num_load_seg == 1)
+
+    print >> fit_file, DT_HEADER % p_paddr
+
+    with open(bl31_file_name) as bl31_file:
+        bl31 = ELFFile(bl31_file)
+        for i in range(bl31.num_segments()):
+            seg = bl31.get_segment(i)
+            if ('PT_LOAD' == seg.__getitem__(ELF_SEG_P_TYPE)):
+                paddr = seg.__getitem__(ELF_SEG_P_PADDR)
+                p= seg.__getitem__(ELF_SEG_P_PADDR)
+                append_atf_node(fit_file, i+1, paddr)
+    atf_cnt = i+1
+    append_fdt_node(fit_file, dtbs_file_name)
+    print >> fit_file, '%s' % DT_IMAGES_NODE_END
+    append_conf_node(fit_file, dtbs_file_name, atf_cnt)
+    print >> fit_file, '%s' % DT_END
+
+    if fit_file_name != sys.stdout:
+        fit_file.close()
+
+def generate_atf_binary(bl31_file_name):
+    with open(bl31_file_name) as bl31_file:
+        bl31 = ELFFile(bl31_file)
+
+        num = bl31.num_segments()
+        for i in range(num):
+            seg = bl31.get_segment(i)
+            if ('PT_LOAD' == seg.__getitem__(ELF_SEG_P_TYPE)):
+                paddr = seg.__getitem__(ELF_SEG_P_PADDR)
+                file_name = 'bl31_0x%08x.bin' % paddr
+                with open(file_name, "wb") as atf:
+                    atf.write(seg.data());
+
+def get_bl31_segments_info(bl31_file_name):
+    """
+    Get load offset, physical offset, file size
+    from bl31 elf file program headers.
+    """
+    with open(bl31_file_name) as bl31_file:
+        bl31 = ELFFile(bl31_file)
+
+        num = bl31.num_segments()
+        print 'Number of Segments : %d' % bl31.num_segments()
+        for i in range(num):
+            print 'Segment %d' % i
+            seg = bl31.get_segment(i)
+            ptype = seg[ELF_SEG_P_TYPE]
+            poffset = seg[ELF_SEG_P_OFFSET]
+            pmemsz = seg[ELF_SEG_P_MEMSZ]
+            pfilesz = seg[ELF_SEG_P_FILESZ]
+            print 'type: %s\nfilesz: %08x\nmemsz: %08x\noffset: %08x' % (ptype, pfilesz, pmemsz, poffset)
+            paddr = seg[ELF_SEG_P_PADDR]
+            print 'paddr: %08x' % paddr
+
+def main():
+    uboot_elf="./u-boot"
+    bl31_elf="./bl31.elf"
+    FIT_ITS=sys.stdout
+
+    opts, args = getopt.getopt(sys.argv[1:], "o:u:b:h")
+    for opt, val in opts:
+        if opt == "-o":
+            FIT_ITS=val
+        elif opt == "-u":
+            uboot_elf=val
+        elif opt == "-b":
+            bl31_elf=val
+        elif opt == "-h":
+            print __doc__
+            sys.exit(2)
+
+    dtbs = args
+    #get_bl31_segments_info("u-boot")
+    #get_bl31_segments_info("bl31.elf")
+
+    generate_atf_fit_dts(FIT_ITS, bl31_elf, uboot_elf, dtbs)
+    generate_atf_binary(bl31_elf);
+
+if __name__ == "__main__":
+    main()

arch/arm/mach-sunxi/Kconfig

@@ -397,9 +397,9 @@ config SYS_CLK_FREQ
 	default 1008000000 if MACH_SUN5I
 	default 1008000000 if MACH_SUN6I
 	default 912000000 if MACH_SUN7I
+	default 816000000 if MACH_SUN50I || MACH_SUN50I_H5
 	default 1008000000 if MACH_SUN8I
 	default 1008000000 if MACH_SUN9I
-	default 816000000 if MACH_SUN50I
 
 config SYS_CONFIG_NAME
 	default "sun4i" if MACH_SUN4I

arch/arm/mach-tegra/Kconfig

@@ -38,6 +38,7 @@ config TEGRA_COMMON
 	select OF_CONTROL
 	select VIDCONSOLE_AS_LCD if DM_VIDEO
 	select BOARD_EARLY_INIT_F
+	select BINMAN
 	imply CRC32_VERIFY
 
 config TEGRA_NO_BPMP

arch/arm/mach-uniphier/clk/Makefile

@@ -27,3 +27,4 @@ endif
 
 obj-$(CONFIG_ARCH_UNIPHIER_LD11)	+= pll-base-ld20.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= pll-base-ld20.o
+obj-$(CONFIG_ARCH_UNIPHIER_PXS3)	+= pll-base-ld20.o

arch/arm/mach-uniphier/clk/pll-base-ld20.c

@@ -5,8 +5,10 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
+#include <linux/bitfield.h>
 #include <linux/bitops.h>
 #include <linux/delay.h>
+#include <linux/kernel.h>
 #include <linux/errno.h>
 #include <linux/io.h>
 #include <linux/sizes.h>
@@ -18,7 +20,6 @@
 #define SC_PLLCTRL_SSC_EN		BIT(31)
 #define SC_PLLCTRL2_NRSTDS		BIT(28)
 #define SC_PLLCTRL2_SSC_JK_MASK		GENMASK(26, 0)
-#define SC_PLLCTRL3_REGI_SHIFT		16
 #define SC_PLLCTRL3_REGI_MASK		GENMASK(19, 16)
 
 /* PLL type: VPLL27 */
@@ -41,13 +42,17 @@ int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq,
 	if (freq != UNIPHIER_PLL_FREQ_DEFAULT) {
 		tmp = readl(base);	/* SSCPLLCTRL */
 		tmp &= ~SC_PLLCTRL_SSC_DK_MASK;
-		tmp |= (487 * freq * ssc_rate / divn / 512) &
-							SC_PLLCTRL_SSC_DK_MASK;
+		tmp |= FIELD_PREP(SC_PLLCTRL_SSC_DK_MASK,
+				  DIV_ROUND_CLOSEST(487UL * freq * ssc_rate,
+						    divn * 512));
 		writel(tmp, base);
 
 		tmp = readl(base + 4);
 		tmp &= ~SC_PLLCTRL2_SSC_JK_MASK;
-		tmp |= (41859 * freq / divn) & SC_PLLCTRL2_SSC_JK_MASK;
+		tmp |= FIELD_PREP(SC_PLLCTRL2_SSC_JK_MASK,
+				  DIV_ROUND_CLOSEST(21431887UL * freq,
+						    divn * 512));
+		writel(tmp, base + 4);
 
 		udelay(50);
 	}
@@ -90,7 +95,7 @@ int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi)
 
 	tmp = readl(base + 8);	/* SSCPLLCTRL3 */
 	tmp &= ~SC_PLLCTRL3_REGI_MASK;
-	tmp |= regi << SC_PLLCTRL3_REGI_SHIFT;
+	tmp |= FIELD_PREP(SC_PLLCTRL3_REGI_MASK, regi);
 	writel(tmp, base + 8);
 
 	iounmap(base);

arch/powerpc/cpu/mpc83xx/Kconfig

@@ -55,6 +55,7 @@ config TARGET_MPC837XEMDS
 	bool "Support MPC837XEMDS"
 	select BOARD_EARLY_INIT_F
 	imply CMD_SATA
+	imply FSL_SATA
 
 config TARGET_MPC837XERDB
 	bool "Support MPC837XERDB"

arch/powerpc/cpu/mpc85xx/Kconfig

@@ -29,6 +29,7 @@ config TARGET_B4420QDS
 	select ARCH_B4420
 	select SUPPORT_SPL
 	select PHYS_64BIT
+	imply PANIC_HANG
 
 config TARGET_B4860QDS
 	bool "Support B4860QDS"
@@ -36,6 +37,7 @@ config TARGET_B4860QDS
 	select BOARD_LATE_INIT if CHAIN_OF_TRUST
 	select SUPPORT_SPL
 	select PHYS_64BIT
+	imply PANIC_HANG
 
 config TARGET_BSC9131RDB
 	bool "Support BSC9131RDB"
@@ -57,6 +59,7 @@ config TARGET_C29XPCIE
 	select SUPPORT_SPL
 	select SUPPORT_TPL
 	select PHYS_64BIT
+	imply PANIC_HANG
 
 config TARGET_P3041DS
 	bool "Support P3041DS"
@@ -64,6 +67,7 @@ config TARGET_P3041DS
 	select ARCH_P3041
 	select BOARD_LATE_INIT if CHAIN_OF_TRUST
 	imply CMD_SATA
+	imply PANIC_HANG
 
 config TARGET_P4080DS
 	bool "Support P4080DS"
@@ -71,6 +75,7 @@ config TARGET_P4080DS
 	select ARCH_P4080
 	select BOARD_LATE_INIT if CHAIN_OF_TRUST
 	imply CMD_SATA
+	imply PANIC_HANG
 
 config TARGET_P5020DS
 	bool "Support P5020DS"
@@ -78,6 +83,7 @@ config TARGET_P5020DS
 	select ARCH_P5020
 	select BOARD_LATE_INIT if CHAIN_OF_TRUST
 	imply CMD_SATA
+	imply PANIC_HANG
 
 config TARGET_P5040DS
 	bool "Support P5040DS"
@@ -85,6 +91,7 @@ config TARGET_P5040DS
 	select ARCH_P5040
 	select BOARD_LATE_INIT if CHAIN_OF_TRUST
 	imply CMD_SATA
+	imply PANIC_HANG
 
 config TARGET_MPC8536DS
 	bool "Support MPC8536DS"
@@ -92,6 +99,7 @@ config TARGET_MPC8536DS
 # Use DDR3 controller with DDR2 DIMMs on this board
 	select SYS_FSL_DDRC_GEN3
 	imply CMD_SATA
+	imply FSL_SATA
 
 config TARGET_MPC8541CDS
 	bool "Support MPC8541CDS"
@@ -100,6 +108,7 @@ config TARGET_MPC8541CDS
 config TARGET_MPC8544DS
 	bool "Support MPC8544DS"
 	select ARCH_MPC8544
+	imply PANIC_HANG
 
 config TARGET_MPC8548CDS
 	bool "Support MPC8548CDS"
@@ -123,6 +132,7 @@ config TARGET_MPC8572DS
 # Use DDR3 controller with DDR2 DIMMs on this board
 	select SYS_FSL_DDRC_GEN3
 	imply SCSI
+	imply PANIC_HANG
 
 config TARGET_P1010RDB_PA
 	bool "Support P1010RDB_PA"
@@ -132,6 +142,7 @@ config TARGET_P1010RDB_PA
 	select SUPPORT_TPL
 	imply CMD_EEPROM
 	imply CMD_SATA
+	imply PANIC_HANG
 
 config TARGET_P1010RDB_PB
 	bool "Support P1010RDB_PB"
@@ -141,6 +152,7 @@ config TARGET_P1010RDB_PB
 	select SUPPORT_TPL
 	imply CMD_EEPROM
 	imply CMD_SATA
+	imply PANIC_HANG
 
 config TARGET_P1022DS
 	bool "Support P1022DS"
@@ -148,11 +160,13 @@ config TARGET_P1022DS
 	select SUPPORT_SPL
 	select SUPPORT_TPL
 	imply CMD_SATA
+	imply FSL_SATA
 
 config TARGET_P1023RDB
 	bool "Support P1023RDB"
 	select ARCH_P1023
 	imply CMD_EEPROM
+	imply PANIC_HANG
 
 config TARGET_P1020MBG
 	bool "Support P1020MBG-PC"
@@ -161,6 +175,7 @@ config TARGET_P1020MBG
 	select ARCH_P1020
 	imply CMD_EEPROM
 	imply CMD_SATA
+	imply PANIC_HANG
 
 config TARGET_P1020RDB_PC
 	bool "Support P1020RDB-PC"
@@ -169,6 +184,7 @@ config TARGET_P1020RDB_PC
 	select ARCH_P1020
 	imply CMD_EEPROM
 	imply CMD_SATA
+	imply PANIC_HANG
 
 config TARGET_P1020RDB_PD
 	bool "Support P1020RDB-PD"
@@ -177,6 +193,7 @@ config TARGET_P1020RDB_PD
 	select ARCH_P1020
 	imply CMD_EEPROM
 	imply CMD_SATA
+	imply PANIC_HANG
 
 config TARGET_P1020UTM
 	bool "Support P1020UTM"
@@ -185,6 +202,7 @@ config TARGET_P1020UTM
 	select ARCH_P1020
 	imply CMD_EEPROM
 	imply CMD_SATA
+	imply PANIC_HANG
 
 config TARGET_P1021RDB
 	bool "Support P1021RDB"
@@ -193,6 +211,7 @@ config TARGET_P1021RDB
 	select ARCH_P1021
 	imply CMD_EEPROM
 	imply CMD_SATA
+	imply PANIC_HANG
 
 config TARGET_P1024RDB
 	bool "Support P1024RDB"
@@ -201,6 +220,7 @@ config TARGET_P1024RDB
 	select ARCH_P1024
 	imply CMD_EEPROM
 	imply CMD_SATA
+	imply PANIC_HANG
 
 config TARGET_P1025RDB
 	bool "Support P1025RDB"
@@ -209,6 +229,7 @@ config TARGET_P1025RDB
 	select ARCH_P1025
 	imply CMD_EEPROM
 	imply CMD_SATA
+	imply SATA_SIL
 
 config TARGET_P2020RDB
 	bool "Support P2020RDB-PC"
@@ -217,6 +238,7 @@ config TARGET_P2020RDB
 	select ARCH_P2020
 	imply CMD_EEPROM
 	imply CMD_SATA
+	imply SATA_SIL
 
 config TARGET_P1_TWR
 	bool "Support p1_twr"
@@ -228,6 +250,7 @@ config TARGET_P2041RDB
 	select BOARD_LATE_INIT if CHAIN_OF_TRUST
 	select PHYS_64BIT
 	imply CMD_SATA
+	imply FSL_SATA
 
 config TARGET_QEMU_PPCE500
 	bool "Support qemu-ppce500"
@@ -242,6 +265,7 @@ config TARGET_T1024QDS
 	select PHYS_64BIT
 	imply CMD_EEPROM
 	imply CMD_SATA
+	imply FSL_SATA
 
 config TARGET_T1023RDB
 	bool "Support T1023RDB"
@@ -250,6 +274,7 @@ config TARGET_T1023RDB
 	select SUPPORT_SPL
 	select PHYS_64BIT
 	imply CMD_EEPROM
+	imply PANIC_HANG
 
 config TARGET_T1024RDB
 	bool "Support T1024RDB"
@@ -258,6 +283,7 @@ config TARGET_T1024RDB
 	select SUPPORT_SPL
 	select PHYS_64BIT
 	imply CMD_EEPROM
+	imply PANIC_HANG
 
 config TARGET_T1040QDS
 	bool "Support T1040QDS"
@@ -266,6 +292,7 @@ config TARGET_T1040QDS
 	select PHYS_64BIT
 	imply CMD_EEPROM
 	imply CMD_SATA
+	imply PANIC_HANG
 
 config TARGET_T1040RDB
 	bool "Support T1040RDB"
@@ -274,6 +301,7 @@ config TARGET_T1040RDB
 	select SUPPORT_SPL
 	select PHYS_64BIT
 	imply CMD_SATA
+	imply PANIC_HANG
 
 config TARGET_T1040D4RDB
 	bool "Support T1040D4RDB"
@@ -282,6 +310,7 @@ config TARGET_T1040D4RDB
 	select SUPPORT_SPL
 	select PHYS_64BIT
 	imply CMD_SATA
+	imply PANIC_HANG
 
 config TARGET_T1042RDB
 	bool "Support T1042RDB"
@@ -298,6 +327,7 @@ config TARGET_T1042D4RDB
 	select SUPPORT_SPL
 	select PHYS_64BIT
 	imply CMD_SATA
+	imply PANIC_HANG
 
 config TARGET_T1042RDB_PI
 	bool "Support T1042RDB_PI"
@@ -306,6 +336,7 @@ config TARGET_T1042RDB_PI
 	select SUPPORT_SPL
 	select PHYS_64BIT
 	imply CMD_SATA
+	imply PANIC_HANG
 
 config TARGET_T2080QDS
 	bool "Support T2080QDS"
@@ -322,6 +353,7 @@ config TARGET_T2080RDB
 	select SUPPORT_SPL
 	select PHYS_64BIT
 	imply CMD_SATA
+	imply PANIC_HANG
 
 config TARGET_T2081QDS
 	bool "Support T2081QDS"
@@ -336,12 +368,14 @@ config TARGET_T4160QDS
 	select SUPPORT_SPL
 	select PHYS_64BIT
 	imply CMD_SATA
+	imply PANIC_HANG
 
 config TARGET_T4160RDB
 	bool "Support T4160RDB"
 	select ARCH_T4160
 	select SUPPORT_SPL
 	select PHYS_64BIT
+	imply PANIC_HANG
 
 config TARGET_T4240QDS
 	bool "Support T4240QDS"
@@ -350,6 +384,7 @@ config TARGET_T4240QDS
 	select SUPPORT_SPL
 	select PHYS_64BIT
 	imply CMD_SATA
+	imply PANIC_HANG
 
 config TARGET_T4240RDB
 	bool "Support T4240RDB"
@@ -357,6 +392,7 @@ config TARGET_T4240RDB
 	select SUPPORT_SPL
 	select PHYS_64BIT
 	imply CMD_SATA
+	imply PANIC_HANG
 
 config TARGET_CONTROLCENTERD
 	bool "Support controlcenterd"
@@ -387,16 +423,19 @@ config TARGET_UCP1020
 	bool "Support uCP1020"
 	select ARCH_P1020
 	imply CMD_SATA
+	imply PANIC_HANG
 
 config TARGET_CYRUS_P5020
 	bool "Support Varisys Cyrus P5020"
 	select ARCH_P5020
 	select PHYS_64BIT
+	imply PANIC_HANG
 
 config TARGET_CYRUS_P5040
 	 bool "Support Varisys Cyrus P5040"
 	select ARCH_P5040
 	select PHYS_64BIT
+	imply PANIC_HANG
 
 endchoice
 
@@ -640,6 +679,7 @@ config ARCH_P1010
 	imply CMD_SATA
 	imply CMD_PCI
 	imply CMD_REGINFO
+	imply FSL_SATA
 
 config ARCH_P1011
 	bool
@@ -672,6 +712,7 @@ config ARCH_P1020
 	imply CMD_SATA
 	imply CMD_PCI
 	imply CMD_REGINFO
+	imply SATA_SIL
 
 config ARCH_P1021
 	bool
@@ -690,6 +731,7 @@ config ARCH_P1021
 	imply CMD_NAND
 	imply CMD_SATA
 	imply CMD_REGINFO
+	imply SATA_SIL
 
 config ARCH_P1022
 	bool
@@ -737,6 +779,7 @@ config ARCH_P1024
 	imply CMD_SATA
 	imply CMD_PCI
 	imply CMD_REGINFO
+	imply SATA_SIL
 
 config ARCH_P1025
 	bool
@@ -821,6 +864,7 @@ config ARCH_P3041
 	imply CMD_NAND
 	imply CMD_SATA
 	imply CMD_REGINFO
+	imply FSL_SATA
 
 config ARCH_P4080
 	bool
@@ -858,6 +902,7 @@ config ARCH_P4080
 	select FSL_ELBC
 	imply CMD_SATA
 	imply CMD_REGINFO
+	imply SATA_SIL
 
 config ARCH_P5020
 	bool
@@ -881,6 +926,7 @@ config ARCH_P5020
 	select FSL_ELBC
 	imply CMD_SATA
 	imply CMD_REGINFO
+	imply FSL_SATA
 
 config ARCH_P5040
 	bool
@@ -904,6 +950,7 @@ config ARCH_P5040
 	select FSL_ELBC
 	imply CMD_SATA
 	imply CMD_REGINFO
+	imply FSL_SATA
 
 config ARCH_QEMU_E500
 	bool
@@ -970,6 +1017,7 @@ config ARCH_T1040
 	imply CMD_NAND
 	imply CMD_SATA
 	imply CMD_REGINFO
+	imply FSL_SATA
 
 config ARCH_T1042
 	bool
@@ -992,6 +1040,7 @@ config ARCH_T1042
 	imply CMD_NAND
 	imply CMD_SATA
 	imply CMD_REGINFO
+	imply FSL_SATA
 
 config ARCH_T2080
 	bool
@@ -1017,6 +1066,7 @@ config ARCH_T2080
 	imply CMD_SATA
 	imply CMD_NAND
 	imply CMD_REGINFO
+	imply FSL_SATA
 
 config ARCH_T2081
 	bool
@@ -1063,6 +1113,7 @@ config ARCH_T4160
 	imply CMD_SATA
 	imply CMD_NAND
 	imply CMD_REGINFO
+	imply FSL_SATA
 
 config ARCH_T4240
 	bool
@@ -1090,6 +1141,7 @@ config ARCH_T4240
 	imply CMD_SATA
 	imply CMD_NAND
 	imply CMD_REGINFO
+	imply FSL_SATA
 
 config BOOKE
 	bool

arch/sandbox/cpu/os.c

@@ -421,6 +421,17 @@ int os_get_filesize(const char *fname, loff_t *size)
 	return 0;
 }
 
+void os_putc(int ch)
+{
+	putchar(ch);
+}
+
+void os_puts(const char *str)
+{
+	while (*str)
+		os_putc(*str++);
+}
+
 int os_write_ram_buf(const char *fname)
 {
 	struct sandbox_state *state = state_get_current();

arch/sandbox/dts/sandbox_pmic.dtsi

@@ -75,4 +75,10 @@
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
 	};
+
+	no_match_by_nodename {
+		regulator-name = "buck_SUPPLY_1.5V";
+		regulator-min-microvolt = <1500000>;
+		regulator-max-microvolt = <1500000>;
+	};
 };

arch/x86/cpu/baytrail/Kconfig

@@ -19,6 +19,7 @@ config INTEL_BAYTRAIL
 	imply MMC_SDHCI
 	imply MMC_SDHCI_SDMA
 	imply SCSI
+	imply SCSI_AHCI
 	imply SPI_FLASH
 	imply SYS_NS16550
 	imply USB

arch/x86/cpu/braswell/Kconfig

@@ -19,6 +19,7 @@ config INTEL_BRASWELL
 	imply MMC_SDHCI
 	imply MMC_SDHCI_SDMA
 	imply SCSI
+	imply SCSI_AHCI
 	imply SPI_FLASH
 	imply SYS_NS16550
 	imply USB

arch/x86/cpu/broadwell/Kconfig

@@ -13,6 +13,7 @@ config INTEL_BROADWELL
 	imply ICH_SPI
 	imply INTEL_BROADWELL_GPIO
 	imply SCSI
+	imply SCSI_AHCI
 	imply SPI_FLASH
 	imply USB
 	imply USB_EHCI_HCD