Prepare v2018.01

Signed-off-by: Tom Rini <trini@konsulko.com>

Makefile

@@ -5,7 +5,7 @@
 VERSION = 2018
 PATCHLEVEL = 01
 SUBLEVEL =
-EXTRAVERSION = -rc2
+EXTRAVERSION =
 NAME =
 
 # *DOCUMENTATION*

README

@@ -1603,6 +1603,15 @@ The following options need to be configured:
 
 		See doc/README.link-local for more information.
 
+ - MAC address from environment variables
+
+		FDT_SEQ_MACADDR_FROM_ENV
+
+		Fix-up device tree with MAC addresses fetched sequentially from
+		environment variables. This config work on assumption that
+		non-usable ethernet node of device-tree are either not present
+		or their status has been marked as "disabled".
+
  - CDP Options:
 		CONFIG_CDP_DEVICE_ID
 
@@ -2168,16 +2177,6 @@ The following options need to be configured:
 		currently only supports clearing the memory.
 
 - Error Recovery:
-		CONFIG_PANIC_HANG
-
-		Define this variable to stop the system in case of a
-		fatal error, so that you have to reset it manually.
-		This is probably NOT a good idea for an embedded
-		system where you want the system to reboot
-		automatically as fast as possible, but it may be
-		useful during development since you can try to debug
-		the conditions that lead to the situation.
-
 		CONFIG_NET_RETRY_COUNT
 
 		This variable defines the number of retries for

arch/arm/cpu/armv8/fsl-layerscape/Kconfig

@@ -11,6 +11,7 @@ config ARCH_LS1012A
 	select SYS_FSL_ERRATUM_A009008
 	select ARCH_EARLY_INIT_R
 	select BOARD_EARLY_INIT_F
+	imply PANIC_HANG
 
 config ARCH_LS1043A
 	bool
@@ -91,6 +92,7 @@ config ARCH_LS1088A
 	select ARCH_EARLY_INIT_R
 	select BOARD_EARLY_INIT_F
 	imply SCSI
+	imply PANIC_HANG
 
 config ARCH_LS2080A
 	bool
@@ -129,6 +131,7 @@ config ARCH_LS2080A
 	select SYS_FSL_ERRATUM_A009203
 	select ARCH_EARLY_INIT_R
 	select BOARD_EARLY_INIT_F
+	imply PANIC_HANG
 
 config FSL_LSCH2
 	bool

arch/arm/dts/Makefile

@@ -324,7 +324,8 @@ dtb-$(CONFIG_MACH_SUN8I_A33) += \
 dtb-$(CONFIG_MACH_SUN8I_A83T) += \
 	sun8i-a83t-allwinner-h8homlet-v2.dtb \
 	sun8i-a83t-bananapi-m3.dtb \
-	sun8i-a83t-cubietruck-plus.dtb
+	sun8i-a83t-cubietruck-plus.dtb \
+	sun8i-a83t-tbs-a711.dts
 dtb-$(CONFIG_MACH_SUN8I_H3) += \
 	sun8i-h2-plus-orangepi-zero.dtb \
 	sun8i-h3-bananapi-m2-plus.dtb \
@@ -345,6 +346,7 @@ dtb-$(CONFIG_MACH_SUN8I_V3S) += \
 	sun8i-v3s-licheepi-zero.dtb
 dtb-$(CONFIG_MACH_SUN50I_H5) += \
 	sun50i-h5-nanopi-neo2.dtb \
+	sun50i-h5-nanopi-neo-plus2.dtb \
 	sun50i-h5-orangepi-pc2.dtb \
 	sun50i-h5-orangepi-prime.dtb \
 	sun50i-h5-orangepi-zero-plus2.dtb
@@ -432,6 +434,10 @@ dtb-$(CONFIG_TARGET_OMAP3_LOGIC) += \
 	logicpd-torpedo-37xx-devkit.dtb \
 	logicpd-som-lv-37xx-devkit.dtb
 
+dtb-$(CONFIG_TARGET_OMAP3_EVM) += \
+	omap3-evm-37xx.dtb \
+	omap3-evm.dtb
+
 dtb-$(CONFIG_TARGET_SAMA5D2_PTC_EK) += \
 	at91-sama5d2_ptc_ek.dtb
 

arch/arm/dts/imx53.dtsi

@@ -23,10 +23,18 @@
 		serial1 = &uart2;
 	};
 
+	tzic: tz-interrupt-controller@fffc000 {
+		compatible = "fsl,imx53-tzic", "fsl,tzic";
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		reg = <0x0fffc000 0x4000>;
+	};
+
 	soc {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "simple-bus";
+		interrupt-parent = <&tzic>;
 		ranges;
 
 		aips@50000000 { /* AIPS1 */

arch/arm/dts/imx6q-cm-fx6.dts

@@ -3,15 +3,46 @@
  *
  * Author: Valentin Raevsky <valentin@compulab.co.il>
  *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
  *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
 #include "imx6q.dtsi"
 
 / {
@@ -31,6 +62,118 @@
 			linux,default-trigger = "heartbeat";
 		};
 	};
+
+	awnh387_pwrseq: pwrseq {
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_pwrseq>;
+		compatible = "mmc-pwrseq-sd8787";
+		powerdown-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>;
+		reset-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
+	};
+
+	reg_pcie_power_on_gpio: regulator-pcie-power-on-gpio {
+		compatible = "regulator-fixed";
+		regulator-name = "regulator-pcie-power-on-gpio";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio2 24 GPIO_ACTIVE_LOW>;
+	};
+
+	reg_usb_h1_vbus: usb_h1_vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "usb_h1_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	reg_usb_otg_vbus: usb_otg_vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "usb_otg_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	sound-analog {
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "On-board analog audio";
+		simple-audio-card,widgets =
+			"Headphone", "Headphone Jack",
+			"Line", "Line Out",
+			"Microphone", "Mic Jack",
+			"Line", "Line In";
+		simple-audio-card,routing =
+			"Headphone Jack", "RHPOUT",
+			"Headphone Jack", "LHPOUT",
+			"MICIN", "Mic Bias",
+			"Mic Bias", "Mic Jack";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,bitclock-master = <&sound_master>;
+		simple-audio-card,frame-master = <&sound_master>;
+		simple-audio-card,bitclock-inversion;
+
+		sound_master: simple-audio-card,cpu {
+			sound-dai = <&ssi2>;
+			system-clock-frequency = <2822400>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <&wm8731>;
+		};
+	};
+
+	sound-spdif {
+		compatible = "fsl,imx-audio-spdif";
+		model = "imx-spdif";
+		spdif-controller = <&spdif>;
+		spdif-out;
+		spdif-in;
+	};
+};
+
+/*
+ * The U-Boot: audio mux node has been removed because the required dt-bindings
+ * header file is not present in the U-Boot.
+ */
+
+&cpu0 {
+	/*
+	 * Although the imx6q fuse indicates that 1.2GHz operation is possible,
+	 * the module behaves unstable at this frequency. Hence, remove the
+	 * 1.2GHz operation point here.
+	 */
+	operating-points = <
+		/* kHz	uV */
+		996000	1250000
+		852000	1250000
+		792000	1175000
+		396000	975000
+	>;
+	fsl,soc-operating-points = <
+		/* ARM kHz	SOC-PU uV */
+		996000		1250000
+		852000		1250000
+		792000		1175000
+		396000		1175000
+	>;
+};
+
+&ecspi1 {
+	cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>, <&gpio3 19 GPIO_ACTIVE_HIGH>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi1>;
+	status = "okay";
+
+	m25p80@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "st,m25p", "jedec,spi-nor";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+	};
 };
 
 &fec {
@@ -46,58 +189,176 @@
 	status = "okay";
 };
 
-&iomuxc {
-	imx6q-cm-fx6 {
-		pinctrl_enet: enetgrp {
-			fsl,pins = <
-				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
-				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0
-				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0
-				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0
-				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0
-				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0
-				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b0b0
-				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b0b0
-				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b0b0
-				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b0b0
-				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b0b0
-				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b0b0
-				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
-				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
-				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
-				MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
-			>;
-		};
+&i2c3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	status = "okay";
+	clock-frequency = <100000>;
 
-		pinctrl_gpmi_nand: gpminandgrp {
-			fsl,pins = <
-				MX6QDL_PAD_NANDF_CLE__NAND_CLE		0xb0b1
-				MX6QDL_PAD_NANDF_ALE__NAND_ALE		0xb0b1
-				MX6QDL_PAD_NANDF_WP_B__NAND_WP_B	0xb0b1
-				MX6QDL_PAD_NANDF_RB0__NAND_READY_B	0xb000
-				MX6QDL_PAD_NANDF_CS0__NAND_CE0_B	0xb0b1
-				MX6QDL_PAD_NANDF_CS1__NAND_CE1_B	0xb0b1
-				MX6QDL_PAD_SD4_CMD__NAND_RE_B		0xb0b1
-				MX6QDL_PAD_SD4_CLK__NAND_WE_B		0xb0b1
-				MX6QDL_PAD_NANDF_D0__NAND_DATA00	0xb0b1
-				MX6QDL_PAD_NANDF_D1__NAND_DATA01	0xb0b1
-				MX6QDL_PAD_NANDF_D2__NAND_DATA02	0xb0b1
-				MX6QDL_PAD_NANDF_D3__NAND_DATA03	0xb0b1
-				MX6QDL_PAD_NANDF_D4__NAND_DATA04	0xb0b1
-				MX6QDL_PAD_NANDF_D5__NAND_DATA05	0xb0b1
-				MX6QDL_PAD_NANDF_D6__NAND_DATA06	0xb0b1
-				MX6QDL_PAD_NANDF_D7__NAND_DATA07	0xb0b1
-				MX6QDL_PAD_SD4_DAT0__NAND_DQS		0x00b1
-			>;
-		};
-
-		pinctrl_uart4: uart4grp {
-			fsl,pins = <
-				MX6QDL_PAD_KEY_COL0__UART4_TX_DATA	0x1b0b1
-				MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA	0x1b0b1
-			>;
-		};
+	eeprom@50 {
+		compatible = "atmel,24c02";
+		reg = <0x50>;
+		pagesize = <16>;
 	};
+
+	wm8731: codec@1a {
+		#sound-dai-cells = <0>;
+		compatible = "wlf,wm8731";
+		reg = <0x1a>;
+	};
+};
+
+&iomuxc {
+	pinctrl_audmux: audmuxgrp {
+		fsl,pins = <
+			MX6QDL_PAD_SD2_CMD__AUD4_RXC   0x17059
+			MX6QDL_PAD_SD2_DAT0__AUD4_RXD  0x17059
+			MX6QDL_PAD_SD2_DAT3__AUD4_TXC  0x17059
+			MX6QDL_PAD_SD2_DAT2__AUD4_TXD  0x17059
+			MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x17059
+		>;
+	};
+
+	pinctrl_ecspi1: ecspi1grp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D16__ECSPI1_SCLK	0x100b1
+			MX6QDL_PAD_EIM_D17__ECSPI1_MISO	0x100b1
+			MX6QDL_PAD_EIM_D18__ECSPI1_MOSI	0x100b1
+			MX6QDL_PAD_EIM_EB2__GPIO2_IO30	0x100b1
+			MX6QDL_PAD_EIM_D19__GPIO3_IO19	0x100b1
+		>;
+	};
+
+	pinctrl_enet: enetgrp {
+		fsl,pins = <
+			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
+			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
+			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
+			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
+			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
+			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
+			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
+			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
+			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
+			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
+			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
+			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
+			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
+			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
+			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
+		>;
+	};
+
+	pinctrl_gpmi_nand: gpminandgrp {
+		fsl,pins = <
+			MX6QDL_PAD_NANDF_CLE__NAND_CLE		0xb0b1
+			MX6QDL_PAD_NANDF_ALE__NAND_ALE		0xb0b1
+			MX6QDL_PAD_NANDF_WP_B__NAND_WP_B	0xb0b1
+			MX6QDL_PAD_NANDF_RB0__NAND_READY_B	0xb000
+			MX6QDL_PAD_NANDF_CS0__NAND_CE0_B	0xb0b1
+			MX6QDL_PAD_NANDF_CS1__NAND_CE1_B	0xb0b1
+			MX6QDL_PAD_SD4_CMD__NAND_RE_B		0xb0b1
+			MX6QDL_PAD_SD4_CLK__NAND_WE_B		0xb0b1
+			MX6QDL_PAD_NANDF_D0__NAND_DATA00	0xb0b1
+			MX6QDL_PAD_NANDF_D1__NAND_DATA01	0xb0b1
+			MX6QDL_PAD_NANDF_D2__NAND_DATA02	0xb0b1
+			MX6QDL_PAD_NANDF_D3__NAND_DATA03	0xb0b1
+			MX6QDL_PAD_NANDF_D4__NAND_DATA04	0xb0b1
+			MX6QDL_PAD_NANDF_D5__NAND_DATA05	0xb0b1
+			MX6QDL_PAD_NANDF_D6__NAND_DATA06	0xb0b1
+			MX6QDL_PAD_NANDF_D7__NAND_DATA07	0xb0b1
+			MX6QDL_PAD_SD4_DAT0__NAND_DQS		0x00b1
+		>;
+	};
+
+	pinctrl_i2c3: i2c3grp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_3__I2C3_SCL	0x4001b8b1
+			MX6QDL_PAD_GPIO_6__I2C3_SDA	0x4001b8b1
+		>;
+	};
+
+	pinctrl_pcie: pciegrp {
+		fsl,pins = <
+			MX6QDL_PAD_ENET_RXD1__GPIO1_IO26	0x1b0b1
+			MX6QDL_PAD_EIM_CS1__GPIO2_IO24	0x1b0b1
+		>;
+	};
+
+	pinctrl_pwrseq: pwrseqgrp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_17__GPIO7_IO12		0x1b0b0
+			MX6QDL_PAD_NANDF_CS3__GPIO6_IO16	0x1b0b0
+		>;
+	};
+
+	pinctrl_spdif: spdifgrp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_16__SPDIF_IN  0x1b0b0
+			MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x1b0b0
+		>;
+	};
+
+	pinctrl_uart4: uart4grp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_COL0__UART4_TX_DATA	0x1b0b1
+			MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA	0x1b0b1
+		>;
+	};
+
+	pinctrl_usbh1: usbh1grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD3_RST__GPIO7_IO08	0x1b0b1
+		>;
+	};
+
+	pinctrl_usbotg: usbotggrp {
+		fsl,pins = <
+			MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID	0x17059
+			MX6QDL_PAD_EIM_D22__GPIO3_IO22	0x130b0
+		>;
+	};
+
+	pinctrl_usdhc1: usdhc1grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD1_CMD__SD1_CMD	0x17071
+			MX6QDL_PAD_SD1_CLK__SD1_CLK	0x10071
+			MX6QDL_PAD_SD1_DAT0__SD1_DATA0	0x17071
+			MX6QDL_PAD_SD1_DAT1__SD1_DATA1	0x17071
+			MX6QDL_PAD_SD1_DAT2__SD1_DATA2	0x17071
+			MX6QDL_PAD_SD1_DAT3__SD1_DATA3	0x17071
+		>;
+	};
+};
+
+&pcie {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pcie>;
+	reset-gpio = <&gpio1 26 GPIO_ACTIVE_LOW>;
+	vpcie-supply = <&reg_pcie_power_on_gpio>;
+	status = "okay";
+};
+
+&sata {
+	status = "okay";
+};
+
+&snvs_poweroff {
+	status = "okay";
+};
+
+&spdif {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_spdif>;
+	status = "okay";
+};
+
+&ssi2 {
+	assigned-clocks = <&clks IMX6QDL_CLK_SSI2_SEL>,
+			<&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
+	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
+	assigned-clock-rates = <0>, <786432000>;
+	status = "okay";
 };
 
 &uart4 {
@@ -106,10 +367,37 @@
 	status = "okay";
 };
 
-&sata {
+&usbh1 {
+	vbus-supply = <&reg_usb_h1_vbus>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usbh1>;
 	status = "okay";
 };
 
+&usbotg {
+	vbus-supply = <&reg_usb_otg_vbus>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usbotg>;
+	dr_mode = "otg";
+	status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	mmc-pwrseq = <&awnh387_pwrseq>;
+	non-removable;
+	/*
+	 * If the OS probes the Bluetooth AMP function advertised on this bus
+	 * but the firmware in place does not support it, the WiFi/BT module
+	 * gets unresponsive.
+	 * Users who configured their OS properly can enable this node to gain
+	 * WiFi and/or plain Bluetooth support.
+	 */
+	status = "disabled";
+};
+
+/* The U-Boot: enable usdhc3 for mmc boot */
 &usdhc3 {
 	status = "okay";
 };

arch/arm/dts/omap-gpmc-smsc911x.dtsi

@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Common file for GPMC connected smsc911x on omaps
+ *
+ * Note that the board specifc DTS file needs to specify
+ * ranges, pinctrl, reg, interrupt parent and interrupts.
+ */
+
+/ {
+	vddvario: regulator-vddvario {
+		  compatible = "regulator-fixed";
+		  regulator-name = "vddvario";
+		  regulator-always-on;
+	};
+
+	vdd33a: regulator-vdd33a {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd33a";
+		regulator-always-on;
+	};
+};
+
+&gpmc {
+	ethernet@gpmc {
+		compatible = "smsc,lan9221", "smsc,lan9115";
+		bank-width = <2>;
+		gpmc,device-width = <1>;
+		gpmc,cycle2cycle-samecsen = <1>;
+		gpmc,cycle2cycle-diffcsen = <1>;
+		gpmc,cs-on-ns = <5>;
+		gpmc,cs-rd-off-ns = <150>;
+		gpmc,cs-wr-off-ns = <150>;
+		gpmc,adv-on-ns = <0>;
+		gpmc,adv-rd-off-ns = <15>;
+		gpmc,adv-wr-off-ns = <40>;
+		gpmc,oe-on-ns = <45>;
+		gpmc,oe-off-ns = <140>;
+		gpmc,we-on-ns = <45>;
+		gpmc,we-off-ns = <140>;
+		gpmc,rd-cycle-ns = <155>;
+		gpmc,wr-cycle-ns = <155>;
+		gpmc,access-ns = <120>;
+		gpmc,page-burst-access-ns = <20>;
+		gpmc,bus-turnaround-ns = <75>;
+		gpmc,cycle2cycle-delay-ns = <75>;
+		gpmc,wait-monitoring-ns = <0>;
+		gpmc,clk-activation-ns = <0>;
+		gpmc,wr-data-mux-bus-ns = <0>;
+		gpmc,wr-access-ns = <0>;
+		vddvario-supply = <&vddvario>;
+		vdd33a-supply = <&vdd33a>;
+		reg-io-width = <4>;
+		smsc,save-mac-address;
+	};
+};

arch/arm/dts/omap3-evm-37xx-u-boot.dtsi

@@ -0,0 +1,29 @@
+/*
+ * U-Boot additions
+ *
+ * (C) Copyright 2017 Derald D. Woods <woods.technical@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/ {
+	chosen {
+		stdout-path = &uart1;
+	};
+};
+
+&mmc1 {
+	cd-inverted;
+};
+
+&uart1 {
+	reg-shift = <2>;
+};
+
+&uart2 {
+	reg-shift = <2>;
+};
+
+&uart3 {
+	reg-shift = <2>;
+};

arch/arm/dts/omap3-evm-37xx.dts

@@ -0,0 +1,110 @@
+/*
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "omap36xx.dtsi"
+#include "omap3-evm-common.dtsi"
+#include "omap3-evm-processor-common.dtsi"
+
+/ {
+	model = "TI OMAP37XX EVM (TMDSEVM3730)";
+	compatible = "ti,omap3-evm-37xx", "ti,omap3630", "ti,omap3";
+};
+
+&omap3_pmx_core2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&hsusb2_2_pins>;
+
+	ehci_phy_pins: pinmux_ehci_phy_pins {
+		pinctrl-single,pins = <
+
+		/* EHCI PHY reset GPIO etk_d7.gpio_21 */
+		OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4)
+
+		/* EHCI VBUS etk_d8.gpio_22 */
+		OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4)
+		>;
+	};
+
+	/* Used by OHCI and EHCI. OHCI won't work without external phy */
+	hsusb2_2_pins: pinmux_hsusb2_2_pins {
+		pinctrl-single,pins = <
+
+		/* etk_d10.hsusb2_clk */
+		OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3)
+
+		/* etk_d11.hsusb2_stp */
+		OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3)
+
+		/* etk_d12.hsusb2_dir */
+		OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3)
+
+		/* etk_d13.hsusb2_nxt */
+		OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3)
+
+		/* etk_d14.hsusb2_data0 */
+		OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3)
+
+		/* etk_d15.hsusb2_data1 */
+		OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3)
+		>;
+	};
+};
+
+&gpmc {
+	nand@0,0 {
+		compatible = "ti,omap2-nand";
+		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+		interrupt-parent = <&gpmc>;
+		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+			     <1 IRQ_TYPE_NONE>;	/* termcount */
+		linux,mtd-name= "hynix,h8kds0un0mer-4em";
+		nand-bus-width = <16>;
+		gpmc,device-width = <2>;
+		ti,nand-ecc-opt = "bch8";
+
+		gpmc,sync-clk-ps = <0>;
+		gpmc,cs-on-ns = <0>;
+		gpmc,cs-rd-off-ns = <44>;
+		gpmc,cs-wr-off-ns = <44>;
+		gpmc,adv-on-ns = <6>;
+		gpmc,adv-rd-off-ns = <34>;
+		gpmc,adv-wr-off-ns = <44>;
+		gpmc,we-off-ns = <40>;
+		gpmc,oe-off-ns = <54>;
+		gpmc,access-ns = <64>;
+		gpmc,rd-cycle-ns = <82>;
+		gpmc,wr-cycle-ns = <82>;
+		gpmc,wr-access-ns = <40>;
+		gpmc,wr-data-mux-bus-ns = <0>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@0 {
+			label = "X-Loader";
+			reg = <0 0x80000>;
+		};
+		partition@0x80000 {
+			label = "U-Boot";
+			reg = <0x80000 0x1c0000>;
+		};
+		partition@0x1c0000 {
+			label = "Environment";
+			reg = <0x240000 0x40000>;
+		};
+		partition@0x280000 {
+			label = "Kernel";
+			reg = <0x280000 0x500000>;
+		};
+		partition@0x780000 {
+			label = "Filesystem";
+			reg = <0x780000 0x1f880000>;
+		};
+	};
+};

arch/arm/dts/omap3-evm-common.dtsi

@@ -0,0 +1,195 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Common support for omap3 EVM boards
+ */
+
+#include <dt-bindings/input/input.h>
+#include "omap-gpmc-smsc911x.dtsi"
+
+/ {
+	cpus {
+		cpu@0 {
+			cpu0-supply = <&vcc>;
+		};
+	};
+
+	/* HS USB Port 2 Power */
+	hsusb2_power: hsusb2_power_reg {
+		compatible = "regulator-fixed";
+		regulator-name = "hsusb2_vbus";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; /* gpio_22 */
+		startup-delay-us = <70000>;
+		enable-active-high;
+	};
+
+	/* HS USB Host PHY on PORT 2 */
+	hsusb2_phy: hsusb2_phy {
+		compatible = "usb-nop-xceiv";
+		reset-gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */
+		vcc-supply = <&hsusb2_power>;
+		#phy-cells = <0>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		ledb {
+			label = "omap3evm::ledb";
+			gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */
+			linux,default-trigger = "default-on";
+		};
+	};
+
+	wl12xx_vmmc: wl12xx_vmmc {
+		compatible = "regulator-fixed";
+		regulator-name = "vwl1271";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		gpio = <&gpio5 22 GPIO_ACTIVE_HIGH>;	/* gpio150 */
+		startup-delay-us = <70000>;
+		enable-active-high;
+		vin-supply = <&vmmc2>;
+	};
+};
+
+&i2c1 {
+	clock-frequency = <2600000>;
+
+	twl: twl@48 {
+		reg = <0x48>;
+		interrupts = <7>; /* SYS_NIRQ cascaded to intc */
+		interrupt-parent = <&intc>;
+	};
+};
+
+#include "twl4030.dtsi"
+#include "twl4030_omap3.dtsi"
+#include "omap3-panel-sharp-ls037v7dw01.dtsi"
+
+&backlight0 {
+	gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>;
+};
+
+&twl {
+	twl_power: power {
+		compatible = "ti,twl4030-power-omap3-evm", "ti,twl4030-power-idle";
+		ti,use_poweroff;
+	};
+};
+
+&i2c2 {
+	clock-frequency = <400000>;
+};
+
+&i2c3 {
+	clock-frequency = <400000>;
+
+	/*
+	 * TVP5146 Video decoder-in for analog input support.
+	 */
+	tvp5146@5c {
+		compatible = "ti,tvp5146m2";
+		reg = <0x5c>;
+	};
+};
+
+&lcd_3v3 {
+	gpio = <&gpio5 25 GPIO_ACTIVE_LOW>;	/* gpio153 */
+};
+
+&lcd0 {
+	enable-gpios = <&gpio5 24 GPIO_ACTIVE_HIGH>;	/* gpio152, lcd INI */
+	reset-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>;	/* gpio155, lcd RESB */
+	mode-gpios = <&gpio5 26 GPIO_ACTIVE_HIGH	/* gpio154, lcd MO */
+		      &gpio1 2 GPIO_ACTIVE_HIGH		/* gpio2, lcd LR */
+		      &gpio1 3 GPIO_ACTIVE_HIGH>;	/* gpio3, lcd UD */
+};
+
+&mcspi1 {
+	tsc2046@0 {
+		interrupt-parent = <&gpio6>;
+		interrupts = <15 0>;		/* gpio175 */
+		pendown-gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&mmc1 {
+	interrupts-extended = <&intc 83 &omap3_pmx_core 0x11a>;
+	vmmc-supply = <&vmmc1>;
+	vqmmc-supply = <&vsim>;
+	bus-width = <8>;
+};
+
+&mmc2 {
+	vmmc-supply = <&wl12xx_vmmc>;
+	non-removable;
+	bus-width = <4>;
+	cap-power-off-card;
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+	wlcore: wlcore@2 {
+		compatible = "ti,wl1271";
+		reg = <2>;
+		interrupt-parent = <&gpio5>;
+		interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; /* gpio 149 */
+		ref-clock-frequency = <38400000>;
+	};
+};
+
+&twl_gpio {
+	ti,use-leds;
+};
+
+&twl_keypad {
+	linux,keymap = <
+			MATRIX_KEY(2, 2, KEY_1)
+			MATRIX_KEY(1, 1, KEY_2)
+			MATRIX_KEY(0, 0, KEY_3)
+			MATRIX_KEY(3, 2, KEY_4)
+			MATRIX_KEY(2, 1, KEY_5)
+			MATRIX_KEY(1, 0, KEY_6)
+			MATRIX_KEY(1, 3, KEY_7)
+			MATRIX_KEY(3, 1, KEY_8)
+			MATRIX_KEY(2, 0, KEY_9)
+			MATRIX_KEY(2, 3, KEY_KPASTERISK)
+			MATRIX_KEY(0, 2, KEY_0)
+			MATRIX_KEY(3, 0, KEY_KPDOT)
+			/* s4 not wired */
+			MATRIX_KEY(1, 2, KEY_BACKSPACE)
+			MATRIX_KEY(0, 1, KEY_ENTER)
+			>;
+};
+
+&usbhshost {
+	port2-mode = "ehci-phy";
+};
+
+&usbhsehci {
+	phys = <0 &hsusb2_phy>;
+};
+
+&usb_otg_hs {
+	interface-type = <0>;
+	usb-phy = <&usb2_phy>;
+	phys = <&usb2_phy>;
+	phy-names = "usb2-phy";
+	mode = <3>;
+	power = <50>;
+};
+
+&gpmc {
+	ethernet@gpmc {
+		interrupt-parent = <&gpio6>;
+		interrupts = <16 8>;
+		reg = <5 0 0xff>;
+	};
+};
+
+&vaux2 {
+	regulator-name = "usb_1v8";
+	regulator-min-microvolt = <1800000>;
+	regulator-max-microvolt = <1800000>;
+	regulator-always-on;
+};

arch/arm/dts/omap3-evm-processor-common.dtsi

@@ -0,0 +1,216 @@
+/*
+ * Common support for omap3 EVM 35xx/37xx processor modules
+ */
+
+/ {
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x80000000 0x10000000>; /* 256 MB */
+	};
+
+	wl12xx_vmmc: wl12xx_vmmc {
+		pinctrl-names = "default";
+		pinctrl-0 = <&wl12xx_gpio>;
+	};
+};
+
+&dss {
+	vdds_dsi-supply = <&vpll2>;
+	vdda_video-supply = <&lcd_3v3>;
+	pinctrl-names = "default";
+	pinctrl-0 = <
+		&dss_dpi_pins1
+		&dss_dpi_pins2
+	>;
+};
+
+&hsusb2_phy {
+	pinctrl-names = "default";
+	pinctrl-0 = <&ehci_phy_pins>;
+};
+
+&omap3_pmx_core {
+	pinctrl-names = "default";
+	pinctrl-0 = <&on_board_gpio_61 &hsusb2_pins>;
+
+	dss_dpi_pins1: pinmux_dss_dpi_pins2 {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0)   /* dss_pclk.dss_pclk */
+			OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0)   /* dss_hsync.dss_hsync */
+			OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0)   /* dss_vsync.dss_vsync */
+			OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0)   /* dss_acbias.dss_acbias */
+
+			OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0)   /* dss_data6.dss_data6 */
+			OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0)   /* dss_data7.dss_data7 */
+			OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0)   /* dss_data8.dss_data8 */
+			OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0)   /* dss_data9.dss_data9 */
+			OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0)   /* dss_data10.dss_data10 */
+			OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0)   /* dss_data11.dss_data11 */
+			OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0)   /* dss_data12.dss_data12 */
+			OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0)   /* dss_data13.dss_data13 */
+			OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0)   /* dss_data14.dss_data14 */
+			OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0)   /* dss_data15.dss_data15 */
+			OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0)   /* dss_data16.dss_data16 */
+			OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0)   /* dss_data17.dss_data17 */
+
+			OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE3)   /* dss_data18.dss_data0 */
+			OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE3)   /* dss_data19.dss_data1 */
+			OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE3)   /* dss_data20.dss_data2 */
+			OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE3)   /* dss_data21.dss_data3 */
+			OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE3)   /* dss_data22.dss_data4 */
+			OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE3)   /* dss_data23.dss_data5 */
+		>;
+	};
+
+	mmc1_pins: pinmux_mmc1_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT_PULLUP | MUX_MODE0)	/* sdmmc1_clk.sdmmc1_clk */
+			OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0)		/* sdmmc1_cmd.sdmmc1_cmd */
+			OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) 	/* sdmmc1_dat0.sdmmc1_dat0 */
+			OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) 	/* sdmmc1_dat1.sdmmc1_dat1 */
+			OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) 	/* sdmmc1_dat2.sdmmc1_dat2 */
+			OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) 	/* sdmmc1_dat3.sdmmc1_dat3 */
+			OMAP3_CORE1_IOPAD(0x2150, PIN_INPUT_PULLUP | MUX_MODE0) 	/* sdmmc1_dat4.sdmmc1_dat4 */
+			OMAP3_CORE1_IOPAD(0x2152, PIN_INPUT_PULLUP | MUX_MODE0) 	/* sdmmc1_dat5.sdmmc1_dat5 */
+			OMAP3_CORE1_IOPAD(0x2154, PIN_INPUT_PULLUP | MUX_MODE0) 	/* sdmmc1_dat6.sdmmc1_dat6 */
+			OMAP3_CORE1_IOPAD(0x2156, PIN_INPUT_PULLUP | MUX_MODE0) 	/* sdmmc1_dat7.sdmmc1_dat7 */
+		>;
+	};
+
+	/* NOTE: Clocked externally, needs INPUT also for sdmmc2_clk.sdmmc2_clk */
+	mmc2_pins: pinmux_mmc2_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc2_clk.sdmmc2_clk */
+			OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc2_cmd.sdmmc2_cmd */
+			OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc2_dat0.sdmmc2_dat0 */
+			OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */
+			OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc2_dat2.sdmmc2_dat2 */
+			OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc2_dat3.sdmmc2_dat3 */
+		>;
+	};
+
+	uart3_pins: pinmux_uart3_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x219e, WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
+			OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0)		/* uart3_tx_irtx.uart3_tx_irtx */
+		>;
+	};
+
+	/* Devices are routed with gpmc_nbe1.gpio_61 to on-board devices */
+	on_board_gpio_61: pinmux_ehci_port_select_pins {
+		pinctrl-single,pins = <
+		OMAP3_CORE1_IOPAD(0x20c8, PIN_OUTPUT | MUX_MODE4)
+		>;
+	};
+
+	/* Used by OHCI and EHCI. OHCI won't work without external phy */
+	hsusb2_pins: pinmux_hsusb2_pins {
+		pinctrl-single,pins = <
+
+		/* mcspi1_cs3.hsusb2_data2 */
+		OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3)
+
+		/* mcspi2_clk.hsusb2_data7 */
+		OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3)
+
+		/* mcspi2_simo.hsusb2_data4 */
+		OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3)
+
+		/* mcspi2_somi.hsusb2_data5 */
+		OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3)
+
+		/* mcspi2_cs0.hsusb2_data6 */
+		OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3)
+
+		/* mcspi2_cs1.hsusb2_data3 */
+		OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3)
+		>;
+	};
+
+	wl12xx_gpio: pinmux_wl12xx_gpio {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x2180, PIN_OUTPUT | MUX_MODE4)		/* uart1_cts.gpio_150 */
+			OMAP3_CORE1_IOPAD(0x217e, PIN_INPUT | MUX_MODE4)		/* uart1_rts.gpio_149 */
+		>;
+	};
+
+	smsc911x_pins: pinmux_smsc911x_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT | MUX_MODE4)		/* mcspi1_cs2.gpio_176 */
+		>;
+	};
+};
+
+&omap3_pmx_wkup {
+	dss_dpi_pins2: pinmux_dss_dpi_pins1 {
+		pinctrl-single,pins = <
+			OMAP3_WKUP_IOPAD(0x2a0a, PIN_OUTPUT | MUX_MODE3)   /* sys_boot0.dss_data18 */
+			OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE3)   /* sys_boot1.dss_data19 */
+			OMAP3_WKUP_IOPAD(0x2a10, PIN_OUTPUT | MUX_MODE3)   /* sys_boot3.dss_data20 */
+			OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE3)   /* sys_boot4.dss_data21 */
+			OMAP3_WKUP_IOPAD(0x2a14, PIN_OUTPUT | MUX_MODE3)   /* sys_boot5.dss_data22 */
+			OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | MUX_MODE3)   /* sys_boot6.dss_data23 */
+		>;
+	};
+};
+
+&mmc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc1_pins>;
+};
+
+&mmc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc2_pins>;
+};
+
+&mmc3 {
+	status = "disabled";
+};
+
+&uart1 {
+	interrupts-extended = <&intc 72 &omap3_pmx_core OMAP3_UART1_RX>;
+};
+
+&uart2 {
+	interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>;
+};
+
+&uart3 {
+	interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart3_pins>;
+};
+
+/*
+ * GPIO_61 (nUSB2_EN_1V8) must be low to enable on-board EHCI USB2 interface
+ * for bus switch SN74CB3Q3384A, level-shifter SN74AVC16T245DGGR, and 1.8V.
+ */
+&gpio2 {
+	en_usb2_port {
+		gpio-hog;
+		gpios = <29 GPIO_ACTIVE_HIGH>;	/* gpio_61 */
+		output-low;
+		line-name = "enable usb2 port";
+	};
+};
+
+/* T2_GPIO_2 low to route GPIO_61 to on-board devices */
+&twl_gpio {
+	en_on_board_gpio_61 {
+		gpio-hog;
+		gpios = <2 GPIO_ACTIVE_HIGH>;
+		output-low;
+		line-name = "en_hsusb2_clk";
+	};
+};
+
+&gpmc {
+	ranges = <0 0 0x30000000 0x1000000>,	/* CS0: 16MB for NAND */
+		 <5 0 0x2c000000 0x01000000>;	/* CS5: 16MB for LAN9220 */
+
+	ethernet@gpmc {
+		pinctrl-names = "default";
+		pinctrl-0 = <&smsc911x_pins>;
+	};
+};

arch/arm/dts/omap3-evm-u-boot.dtsi

@@ -0,0 +1,29 @@
+/*
+ * U-Boot additions
+ *
+ * (C) Copyright 2017 Derald D. Woods <woods.technical@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/ {
+	chosen {
+		stdout-path = &uart1;
+	};
+};
+
+&mmc1 {
+	cd-inverted;
+};
+
+&uart1 {
+	reg-shift = <2>;
+};
+
+&uart2 {
+	reg-shift = <2>;
+};
+
+&uart3 {
+	reg-shift = <2>;
+};

arch/arm/dts/omap3-evm.dts

@@ -0,0 +1,89 @@
+/*
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "omap34xx.dtsi"
+#include "omap3-evm-common.dtsi"
+#include "omap3-evm-processor-common.dtsi"
+
+/ {
+	model = "TI OMAP35XX EVM (TMDSEVM3530)";
+	compatible = "ti,omap3-evm", "ti,omap3430", "ti,omap3";
+};
+
+&omap3_pmx_core2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&hsusb2_2_pins>;
+
+	ehci_phy_pins: pinmux_ehci_phy_pins {
+		pinctrl-single,pins = <
+
+		/* EHCI PHY reset GPIO etk_d7.gpio_21 */
+		OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4)
+
+		/* EHCI VBUS etk_d8.gpio_22 */
+		OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4)
+		>;
+	};
+
+	/* Used by OHCI and EHCI. OHCI won't work without external phy */
+	hsusb2_2_pins: pinmux_hsusb2_2_pins {
+		pinctrl-single,pins = <
+
+		/* etk_d10.hsusb2_clk */
+		OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3)
+
+		/* etk_d11.hsusb2_stp */
+		OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3)
+
+		/* etk_d12.hsusb2_dir */
+		OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3)
+
+		/* etk_d13.hsusb2_nxt */
+		OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3)
+
+		/* etk_d14.hsusb2_data0 */
+		OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3)
+
+		/* etk_d15.hsusb2_data1 */
+		OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3)
+		>;
+	};
+};
+
+&gpmc {
+	nand@0,0 {
+		compatible = "ti,omap2-nand";
+		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+		interrupt-parent = <&gpmc>;
+		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+			     <1 IRQ_TYPE_NONE>;	/* termcount */
+		linux,mtd-name= "micron,mt29f2g16abdhc";
+		nand-bus-width = <16>;
+		gpmc,device-width = <2>;
+		ti,nand-ecc-opt = "bch8";
+
+		gpmc,sync-clk-ps = <0>;
+		gpmc,cs-on-ns = <0>;
+		gpmc,cs-rd-off-ns = <44>;
+		gpmc,cs-wr-off-ns = <44>;
+		gpmc,adv-on-ns = <6>;
+		gpmc,adv-rd-off-ns = <34>;
+		gpmc,adv-wr-off-ns = <44>;
+		gpmc,we-off-ns = <40>;
+		gpmc,oe-off-ns = <54>;
+		gpmc,access-ns = <64>;
+		gpmc,rd-cycle-ns = <82>;
+		gpmc,wr-cycle-ns = <82>;
+		gpmc,wr-access-ns = <40>;
+		gpmc,wr-data-mux-bus-ns = <0>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+	};
+};

arch/arm/dts/omap3-panel-sharp-ls037v7dw01.dtsi

@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Common file for omap dpi panels with QVGA and reset pins
+ *
+ * Note that the board specifc DTS file needs to specify
+ * at minimum the GPIO enable-gpios for display, and
+ * gpios for gpio-backlight.
+ */
+
+/ {
+	aliases {
+		display0 = &lcd0;
+	};
+
+	backlight0: backlight {
+		compatible = "gpio-backlight";
+		default-on;
+	};
+
+	/* 3.3V GPIO controlled regulator for LCD_ENVDD */
+	lcd_3v3: regulator-lcd-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "lcd_3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		startup-delay-us = <70000>;
+	};
+
+	lcd0: display {
+		compatible = "sharp,ls037v7dw01";
+		label = "lcd";
+		power-supply = <&lcd_3v3>;
+		envdd-supply = <&lcd_3v3>;
+
+		port {
+			lcd_in: endpoint {
+				remote-endpoint = <&dpi_out>;
+			};
+		};
+	};
+};
+
+/* Needed to power the DPI pins */
+&vpll2 {
+	regulator-always-on;
+};
+
+&dss {
+	status = "ok";
+	port {
+		dpi_out: endpoint {
+			remote-endpoint = <&lcd_in>;
+			data-lines = <18>;
+		};
+	};
+};
+
+&mcspi1 {
+	tsc2046@0 {
+		reg = <0>;			/* CS0 */
+		compatible = "ti,tsc2046";
+		spi-max-frequency = <1000000>;
+		vcc-supply = <&lcd_3v3>;
+		ti,x-min = /bits/ 16 <0>;
+		ti,x-max = /bits/ 16 <8000>;
+		ti,y-min = /bits/ 16 <0>;
+		ti,y-max = /bits/ 16 <4800>;
+		ti,x-plate-ohms = /bits/ 16 <40>;
+		ti,pressure-max = /bits/ 16 <255>;
+		ti,swap-xy;
+		wakeup-source;
+	};
+};

arch/arm/dts/omap34xx.dtsi

@@ -0,0 +1,84 @@
+/*
+ * Device Tree Source for OMAP34xx/OMAP35xx SoC
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/media/omap3-isp.h>
+
+#include "omap3.dtsi"
+
+/ {
+	cpus {
+		cpu: cpu@0 {
+			/* OMAP343x/OMAP35xx variants OPP1-5 */
+			operating-points = <
+				/* kHz    uV */
+				125000   975000
+				250000  1075000
+				500000  1200000
+				550000  1270000
+				600000  1350000
+			>;
+			clock-latency = <300000>; /* From legacy driver */
+		};
+	};
+
+	ocp@68000000 {
+		omap3_pmx_core2: pinmux@480025d8 {
+			compatible = "ti,omap3-padconf", "pinctrl-single";
+			reg = <0x480025d8 0x24>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#pinctrl-cells = <1>;
+			#interrupt-cells = <1>;
+			interrupt-controller;
+			pinctrl-single,register-width = <16>;
+			pinctrl-single,function-mask = <0xff1f>;
+		};
+
+		isp: isp@480bc000 {
+			compatible = "ti,omap3-isp";
+			reg = <0x480bc000 0x12fc
+			       0x480bd800 0x017c>;
+			interrupts = <24>;
+			iommus = <&mmu_isp>;
+			syscon = <&scm_conf 0x6c>;
+			ti,phy-type = <OMAP3ISP_PHY_TYPE_COMPLEX_IO>;
+			#clock-cells = <1>;
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+		};
+
+		bandgap: bandgap@48002524 {
+			reg = <0x48002524 0x4>;
+			compatible = "ti,omap34xx-bandgap";
+			#thermal-sensor-cells = <0>;
+		};
+	};
+
+	thermal_zones: thermal-zones {
+		#include "omap3-cpu-thermal.dtsi"
+	};
+};
+
+&ssi {
+	status = "ok";
+
+	clocks = <&ssi_ssr_fck>,
+		 <&ssi_sst_fck>,
+		 <&ssi_ick>;
+	clock-names = "ssi_ssr_fck",
+		      "ssi_sst_fck",
+		      "ssi_ick";
+};
+
+/include/ "omap34xx-omap36xx-clocks.dtsi"
+/include/ "omap36xx-omap3430es2plus-clocks.dtsi"
+/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"

arch/arm/dts/rk3399-evb.dts

@@ -17,6 +17,8 @@
 
 	chosen {
 		stdout-path = &uart2;
+		u-boot,spl-boot-order = \
+			&sdhci, &sdmmc;
 	};
 
 	vdd_center: vdd-center {
@@ -154,6 +156,7 @@
 };
 
 &sdmmc {
+	u-boot,dm-pre-reloc;
 	bus-width = <4>;
 	status = "okay";
 };

arch/arm/dts/sun50i-h5-nanopi-neo-plus2.dts

@@ -0,0 +1,106 @@
+/*
+ * Copyright (C) 2017 Antony Antony <antony@phenome.org>
+ * Copyright (c) 2016 ARM Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "sun50i-h5.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "FriendlyARM NanoPi NEO Plus 2";
+	compatible = "friendlyarm,nanopi-neo-plus2", "allwinner,sun50i-h5";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	reg_vcc3v3: vcc3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+};
+
+&ehci1 {
+	status = "okay";
+};
+
+&mmc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
+	vmmc-supply = <&reg_vcc3v3>;
+	bus-width = <4>;
+	cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
+	cd-inverted;
+	status = "okay";
+};
+
+&mmc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc2_8bit_pins>;
+	vmmc-supply = <&reg_vcc3v3>;
+	bus-width = <8>;
+	non-removable;
+	cap-mmc-hw-reset;
+	status = "okay";
+};
+
+&ohci1 {
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins_a>;
+	status = "okay";
+};
+
+&usbphy {
+	status = "okay";
+};

arch/arm/dts/sun50i-h5-orangepi-prime.dts

@@ -72,6 +72,10 @@
 	};
 };
 
+&ehci1 {
+	status = "okay";
+};
+
 &mmc0 {
 	compatible = "allwinner,sun50i-h5-mmc",
 		     "allwinner,sun50i-a64-mmc",
@@ -85,6 +89,10 @@
 	status = "okay";
 };
 
+&ohci1 {
+	status = "okay";
+};
+
 &uart0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart0_pins_a>;
@@ -94,11 +102,3 @@
 &usbphy {
 	status = "okay";
 };
-
-&ohci1 {
-	status = "okay";
-};
-
-&ehci1 {
-	status = "okay";
-};

arch/arm/dts/sun50i-h5.dtsi

@@ -72,6 +72,38 @@
 	};
 };
 
+&ccu {
+	compatible = "allwinner,sun50i-h5-ccu";
+};
+
 &gic {
 	compatible = "arm,gic-400";
 };
+
+&mmc0 {
+	compatible = "allwinner,sun50i-h5-mmc",
+		     "allwinner,sun50i-a64-mmc";
+	clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
+	clock-names = "ahb", "mmc";
+};
+
+&mmc1 {
+	compatible = "allwinner,sun50i-h5-mmc",
+		     "allwinner,sun50i-a64-mmc";
+	clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
+	clock-names = "ahb", "mmc";
+};
+
+&mmc2 {
+	compatible = "allwinner,sun50i-h5-emmc",
+		     "allwinner,sun50i-a64-emmc";
+	clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
+	clock-names = "ahb", "mmc";
+};
+
+&pio {
+	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+		   <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+	compatible = "allwinner,sun50i-h5-pinctrl";
+};

arch/arm/dts/sun8i-a83t-tbs-a711.dts

@@ -0,0 +1,76 @@
+/*
+ * Copyright 2017 Ondřej Jirman
+ * Ondřej Jirman <megous@megous.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-a83t.dtsi"
+
+/ {
+	model = "TBS A711 Tablet";
+	compatible = "tbs-biometrics,a711", "allwinner,sun8i-a83t";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&ehci0 {
+	status = "okay";
+};
+
+&ohci0 {
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins_b>;
+	status = "okay";
+};
+
+&usb_otg {
+	status = "okay";
+};

arch/arm/include/asm/arch-mx6/imx-regs.h

@@ -17,7 +17,7 @@
 #define GPU_2D_ARB_END_ADDR             0x02203FFF
 #define OPENVG_ARB_BASE_ADDR            0x02204000
 #define OPENVG_ARB_END_ADDR             0x02207FFF
-#elif (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
+#elif (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
 #define CAAM_ARB_BASE_ADDR              0x00100000
 #define CAAM_ARB_END_ADDR               0x00107FFF
 #define GPU_ARB_BASE_ADDR               0x01800000
@@ -46,7 +46,8 @@
 #define MXS_BCH_BASE			(APBH_DMA_ARB_BASE_ADDR + 0x04000)
 
 /* GPV - PL301 configuration ports */
-#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
+#if (defined(CONFIG_MX6SX) || \
+	defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
 	defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL))
 #define GPV2_BASE_ADDR                  0x00D00000
 #define GPV3_BASE_ADDR			0x00E00000
@@ -88,7 +89,7 @@
 #define QSPI0_AMBA_END                 0x6FFFFFFF
 #define QSPI1_AMBA_BASE                0x70000000
 #define QSPI1_AMBA_END                 0x7FFFFFFF
-#elif defined(CONFIG_MX6UL)
+#elif (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
 #define WEIM_ARB_BASE_ADDR              0x50000000
 #define WEIM_ARB_END_ADDR               0x57FFFFFF
 #define QSPI0_AMBA_BASE                 0x60000000
@@ -109,7 +110,8 @@
 #endif
 
 #if (defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || \
-	defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
+	defined(CONFIG_MX6SX) || \
+	defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
 #define MMDC0_ARB_BASE_ADDR             0x80000000
 #define MMDC0_ARB_END_ADDR              0xFFFFFFFF
 #define MMDC1_ARB_BASE_ADDR             0xC0000000
@@ -262,7 +264,7 @@
 #define MMDC_P0_BASE_ADDR           (AIPS2_OFF_BASE_ADDR + 0x30000)
 /* i.MX6SL/SLL */
 #define RNGB_IPS_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0x34000)
-#ifdef CONFIG_MX6UL
+#if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
 #define ENET2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x34000)
 #else
 /* i.MX6SX */
@@ -288,7 +290,8 @@
 #define IP2APB_PERFMON3_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x4C000)
 #endif
 #define IP2APB_TZASC1_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x50000)
-#ifdef CONFIG_MX6UL
+#if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
+#define SCTR_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x5C000)
 #define QSPI0_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x60000)
 #define UART6_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x7C000)
 #elif defined(CONFIG_MX6SX)
@@ -337,7 +340,7 @@
 #define PWM6_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xA8000)
 #define PWM7_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xAC000)
 #define PWM8_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xB0000)
-#elif defined(CONFIG_MX6ULL)
+#elif (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
 #define AIPS3_CONFIG_BASE_ADDR      (AIPS3_ARB_BASE_ADDR + 0x7C000)
 #define DCP_BASE_ADDR               (AIPS3_ARB_BASE_ADDR + 0x80000)
 #define RNGB_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x84000)
@@ -354,7 +357,8 @@
 #define MX6SX_LCDIF1_BASE_ADDR      (AIPS3_ARB_BASE_ADDR + 0x20000)
 #define MX6SX_WDOG3_BASE_ADDR       (AIPS3_ARB_BASE_ADDR + 0x88000)
 
-#if !(defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
+#if !(defined(CONFIG_MX6SX) || \
+	defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
 	defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL))
 #define IRAM_SIZE                    0x00040000
 #else
@@ -573,7 +577,7 @@ struct src {
 #define IOMUXC_GPR12_LOS_LEVEL			(0x1f << 4)
 
 struct iomuxc {
-#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
+#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
 	u8 reserved[0x4000];
 #endif
 	u32 gpr[14];
@@ -700,7 +704,7 @@ struct cspi_regs {
 #define MXC_CSPICON_SSPOL	12 /* SS polarity */
 #define MXC_CSPICON_CTL		20 /* inactive state of SCLK */
 #if defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || \
-	defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL)
+	defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
 #define MXC_SPI_BASE_ADDRESSES \
 	ECSPI1_BASE_ADDR, \
 	ECSPI2_BASE_ADDR, \

arch/arm/include/asm/arch-mx6/mx6-ddr.h

@@ -16,7 +16,7 @@
 #ifdef CONFIG_MX6SX
 #include "mx6sx-ddr.h"
 #else
-#ifdef CONFIG_MX6UL
+#if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
 #include "mx6ul-ddr.h"
 #else
 #ifdef CONFIG_MX6SL

arch/arm/include/asm/arch-mx6/mx6ul-ddr.h

@@ -7,7 +7,7 @@
 #ifndef __ASM_ARCH_MX6UL_DDR_H__
 #define __ASM_ARCH_MX6UL_DDR_H__
 
-#ifndef CONFIG_MX6UL
+#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
 #error "wrong CPU"
 #endif
 

arch/arm/include/asm/mach-imx/iomux-v3.h

@@ -127,7 +127,7 @@ typedef u64 iomux_v3_cfg_t;
 
 #define PAD_CTL_ODE		(1 << 11)
 
-#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)
+#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
 #define PAD_CTL_SPEED_LOW	(0 << 6)
 #else
 #define PAD_CTL_SPEED_LOW	(1 << 6)
@@ -253,7 +253,7 @@ if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {				\
 	imx_iomux_v3_setup_pad(MX6Q_##def);
 #define SETUP_IOMUX_PADS(x)					\
 	imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
-#elif defined(CONFIG_MX6UL)
+#elif defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
 #define IOMUX_PADS(x) MX6_##x
 #define SETUP_IOMUX_PAD(def)					\
 	imx_iomux_v3_setup_pad(MX6_##def);

arch/arm/include/asm/mach-imx/regs-lcdif.h

@@ -19,8 +19,11 @@
 struct mxs_lcdif_regs {
 	mxs_reg_32(hw_lcdif_ctrl)		/* 0x00 */
 	mxs_reg_32(hw_lcdif_ctrl1)		/* 0x10 */
-#if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
-	defined(CONFIG_MX7) || defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL)
+
+#if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || \
+	defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
+	defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
+	defined(CONFIG_MX7)
 	mxs_reg_32(hw_lcdif_ctrl2)		/* 0x20 */
 #endif
 	mxs_reg_32(hw_lcdif_transfer_count)	/* 0x20/0x30 */
@@ -55,8 +58,10 @@ struct mxs_lcdif_regs {
 #endif
 	mxs_reg_32(hw_lcdif_data)		/* 0x1b0/0x180 */
 	mxs_reg_32(hw_lcdif_bm_error_stat)	/* 0x1c0/0x190 */
-#if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
-	defined(CONFIG_MX7) || defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL)
+#if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || \
+	defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
+	defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
+	defined(CONFIG_MX7)
 	mxs_reg_32(hw_lcdif_crc_stat)		/* 0x1a0 */
 #endif
 	mxs_reg_32(hw_lcdif_lcdif_stat)		/* 0x1d0/0x1b0 */
@@ -64,8 +69,10 @@ struct mxs_lcdif_regs {
 	mxs_reg_32(hw_lcdif_debug0)		/* 0x1f0/0x1d0 */
 	mxs_reg_32(hw_lcdif_debug1)		/* 0x200/0x1e0 */
 	mxs_reg_32(hw_lcdif_debug2)		/* 0x1f0 */
-#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX7) || \
-	defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL)
+#if defined(CONFIG_MX6SX) || \
+	defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
+	defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
+	defined(CONFIG_MX7)
 	mxs_reg_32(hw_lcdif_thres)
 	mxs_reg_32(hw_lcdif_as_ctrl)
 	mxs_reg_32(hw_lcdif_as_buf)

arch/arm/include/asm/mach-imx/sys_proto.h

@@ -81,7 +81,8 @@ enum imx6_bmode {
 	IMX6_BMODE_ESD,
 	IMX6_BMODE_MMC,
 	IMX6_BMODE_EMMC,
-	IMX6_BMODE_NAND,
+	IMX6_BMODE_NAND_MIN,
+	IMX6_BMODE_NAND_MAX = 0xf,
 };
 
 static inline u8 imx6_is_bmode_from_gpr9(void)
@@ -109,6 +110,9 @@ void imx_wdog_disable_powerdown(void);
 
 int board_mmc_get_env_dev(int devno);
 
+int nxp_board_rev(void);
+char nxp_board_rev_string(void);
+
 /*
  * Initializes on-chip ethernet controllers.
  * to override, implement board_eth_init()

arch/arm/lib/bootm-fdt.c

@@ -25,6 +25,13 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_FMAN_ENET
+__weak int fdt_update_ethernet_dt(void *blob)
+{
+	return 0;
+}
+#endif
+
 int arch_fixup_fdt(void *blob)
 {
 	int ret = 0;
@@ -64,5 +71,10 @@ int arch_fixup_fdt(void *blob)
 #endif
 #endif
 
+#ifdef CONFIG_FMAN_ENET
+	ret = fdt_update_ethernet_dt(blob);
+	if (ret)
+		return ret;
+#endif
 	return 0;
 }

arch/arm/mach-imx/Kconfig

@@ -1,9 +1,18 @@
+config HAS_CAAM
+	bool
+
 config IMX_CONFIG
 	string
 
 config ROM_UNIFIED_SECTIONS
 	bool
 
+config SYSCOUNTER_TIMER
+	bool
+
+config GPT_TIMER
+	bool
+
 config IMX_RDC
 	bool "i.MX Resource domain controller driver"
 	depends on ARCH_MX6 || ARCH_MX7
@@ -28,7 +37,7 @@ config USE_IMXIMG_PLUGIN
 config SECURE_BOOT
 	bool "Support i.MX HAB features"
 	depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX5
-	select FSL_CAAM
+	select FSL_CAAM if HAS_CAAM
 	imply CMD_DEKBLOB
 	help
 	  This option enables the support for secure boot (HAB).
@@ -61,3 +70,11 @@ config CMD_HDMIDETECT
 	help
 	  This enables the 'hdmidet' command which detects if an HDMI monitor
 	  is connected.
+
+config NXP_BOARD_REVISION
+	bool "Read NXP board revision from fuses"
+	depends on ARCH_MX6 || ARCH_MX7
+	help
+	  NXP boards based on i.MX6/7 contain the board revision information
+	  stored in the fuses. Select this option if you want to be able to
+	  retrieve the board revision information.

arch/arm/mach-imx/Makefile

@@ -11,7 +11,8 @@ ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 vf610))
 obj-y	= iomux-v3.o
 endif
 ifeq ($(SOC),$(filter $(SOC),mx5 mx6))
-obj-y	+= timer.o cpu.o speed.o
+obj-y	+= cpu.o speed.o
+obj-$(CONFIG_GPT_TIMER) += timer.o
 obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
 endif
 ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs))
@@ -21,7 +22,6 @@ endif
 ifeq ($(SOC),$(filter $(SOC),mx7))
 obj-y 	+= cpu.o
 obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
-obj-$(CONFIG_SYSCOUNTER_TIMER) += syscounter.o
 endif
 ifeq ($(SOC),$(filter $(SOC),mx6 mx7))
 obj-y 	+= cache.o init.o
@@ -30,6 +30,7 @@ obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
 obj-$(CONFIG_IMX_RDC) += rdc-sema.o
 obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
 obj-$(CONFIG_SECURE_BOOT)    += hab.o
+obj-$(CONFIG_SYSCOUNTER_TIMER) += syscounter.o
 endif
 ifeq ($(SOC),$(filter $(SOC),mx7ulp))
 obj-y  += cache.o

arch/arm/mach-imx/cpu.c

@@ -323,3 +323,28 @@ void set_chipselect_size(int const cs_size)
 
 	writel(reg, &iomuxc_regs->gpr[1]);
 }
+
+#ifdef CONFIG_NXP_BOARD_REVISION
+int nxp_board_rev(void)
+{
+	/*
+	 * Get Board ID information from OCOTP_GP1[15:8]
+	 * RevA: 0x1
+	 * RevB: 0x2
+	 * RevC: 0x3
+	 */
+	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+	struct fuse_bank *bank = &ocotp->bank[4];
+	struct fuse_bank4_regs *fuse =
+			(struct fuse_bank4_regs *)bank->fuse_regs;
+
+	return (readl(&fuse->gp1) >> 8 & 0x0F);
+}
+
+char nxp_board_rev_string(void)
+{
+	const char *rev = "A";
+
+	return (*rev + nxp_board_rev() - 1);
+}
+#endif

arch/arm/mach-imx/mx5/Kconfig

@@ -1,6 +1,7 @@
 if ARCH_MX5
 
 config MX5
+	select GPT_TIMER
 	bool
 	default y
 

arch/arm/mach-imx/mx6/Kconfig

@@ -8,34 +8,41 @@ config MX6_SMP
 	bool
 
 config MX6
-	select ARM_ERRATA_743622 if !MX6UL
+	select ARM_ERRATA_743622 if !MX6UL && !MX6ULL
+	select GPT_TIMER if !MX6UL && !MX6ULL
 	bool
 	default y
 	imply CMD_FUSE
 
 config MX6D
+	select HAS_CAAM
 	select MX6_SMP
 	bool
 
 config MX6DL
+	select HAS_CAAM
 	select MX6_SMP
 	bool
 
 config MX6Q
+	select HAS_CAAM
 	select MX6_SMP
 	bool
 
 config MX6QDL
+	select HAS_CAAM
 	select MX6_SMP
 	bool
 
 config MX6S
+	select HAS_CAAM
 	bool
 
 config MX6SL
 	bool
 
 config MX6SX
+	select HAS_CAAM
 	select ROM_UNIFIED_SECTIONS
 	bool
 
@@ -44,8 +51,10 @@ config MX6SLL
 	bool
 
 config MX6UL
+	select HAS_CAAM
 	select SYS_L2CACHE_OFF
 	select ROM_UNIFIED_SECTIONS
+	select SYSCOUNTER_TIMER
 	bool
 
 config MX6UL_LITESOM
@@ -66,8 +75,10 @@ config MX6UL_OPOS6UL
 	select SUPPORT_SPL
 
 config MX6ULL
+	select SYS_L2CACHE_OFF
+	select ROM_UNIFIED_SECTIONS
+	select SYSCOUNTER_TIMER
 	bool
-	select MX6UL
 
 config MX6_DDRCAL
 	bool "Include dynamic DDR calibration routines"
@@ -202,6 +213,14 @@ config TARGET_MX6LOGICPD
 	select DM_REGULATOR
 	select OF_CONTROL
 
+config TARGET_MX6MEMCAL
+	bool "mx6memcal"
+	select SUPPORT_SPL
+	help
+	  The mx6memcal board is a virtual board that can be used to validate
+	  and characterize the memory layout of a new design during the initial
+	  development and pre-production stages.
+
 config TARGET_MX6QARM2
 	bool "mx6qarm2"
 
@@ -244,6 +263,7 @@ config TARGET_MX6SABRESD
 
 config TARGET_MX6SLEVK
 	bool "mx6slevk"
+	select MX6SL
 	select SUPPORT_SPL
 
 config TARGET_MX6SLLEVK
@@ -255,6 +275,7 @@ config TARGET_MX6SLLEVK
 
 config TARGET_MX6SXSABRESD
 	bool "mx6sxsabresd"
+	select BOARD_LATE_INIT
 	select MX6SX
 	select SUPPORT_SPL
 	select DM
@@ -395,6 +416,7 @@ config TARGET_WANDBOARD
 
 config TARGET_WARP
 	bool "WaRP"
+	select MX6SL
 	select BOARD_LATE_INIT
 
 config TARGET_XPRESS
@@ -441,6 +463,7 @@ source "board/embest/mx6boards/Kconfig"
 source "board/engicam/imx6q/Kconfig"
 source "board/engicam/imx6ul/Kconfig"
 source "board/freescale/mx6qarm2/Kconfig"
+source "board/freescale/mx6memcal/Kconfig"
 source "board/freescale/mx6sabreauto/Kconfig"
 source "board/freescale/mx6sabresd/Kconfig"
 source "board/freescale/mx6slevk/Kconfig"

arch/arm/mach-imx/mx6/ddr.c

@@ -631,7 +631,7 @@ void mx6sx_dram_iocfg(unsigned width,
 }
 #endif
 
-#ifdef CONFIG_MX6UL
+#if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
 void mx6ul_dram_iocfg(unsigned width,
 		      const struct mx6ul_iomux_ddr_regs *ddr,
 		      const struct mx6ul_iomux_grp_regs *grp)

arch/arm/mach-imx/mx7/Kconfig

@@ -3,6 +3,7 @@ if ARCH_MX7
 config MX7
 	bool
 	select ROM_UNIFIED_SECTIONS
+	select SYSCOUNTER_TIMER
 	select CPU_V7_HAS_VIRT
 	select CPU_V7_HAS_NONSEC
 	select ARCH_SUPPORT_PSCI
@@ -10,6 +11,7 @@ config MX7
 	default y
 
 config MX7D
+	select HAS_CAAM
 	select ROM_UNIFIED_SECTIONS
 	imply CMD_FUSE
 	bool

arch/arm/mach-imx/spl.c

@@ -91,7 +91,7 @@ u32 spl_boot_device(void)
 	case IMX6_BMODE_EMMC:
 		return BOOT_DEVICE_MMC1;
 	/* NAND Flash: 8.5.2, Table 8-10 */
-	case IMX6_BMODE_NAND:
+	case IMX6_BMODE_NAND_MIN ... IMX6_BMODE_NAND_MAX:
 		return BOOT_DEVICE_NAND;
 	}
 	return BOOT_DEVICE_NONE;

arch/arm/mach-omap2/omap3/Kconfig

@@ -61,6 +61,10 @@ config TARGET_DEVKIT8000
 
 config TARGET_OMAP3_EVM
 	bool "TI OMAP3 EVM"
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
+	select OMAP3_GPIO_3
 
 config TARGET_OMAP3_IGEP00X0
 	bool "IGEP"

arch/arm/mach-sunxi/Kconfig

@@ -397,9 +397,9 @@ config SYS_CLK_FREQ
 	default 1008000000 if MACH_SUN5I
 	default 1008000000 if MACH_SUN6I
 	default 912000000 if MACH_SUN7I
+	default 816000000 if MACH_SUN50I || MACH_SUN50I_H5
 	default 1008000000 if MACH_SUN8I
 	default 1008000000 if MACH_SUN9I
-	default 816000000 if MACH_SUN50I
 
 config SYS_CONFIG_NAME
 	default "sun4i" if MACH_SUN4I

arch/powerpc/cpu/mpc85xx/Kconfig

@@ -29,6 +29,7 @@ config TARGET_B4420QDS
 	select ARCH_B4420
 	select SUPPORT_SPL
 	select PHYS_64BIT
+	imply PANIC_HANG
 
 config TARGET_B4860QDS
 	bool "Support B4860QDS"
@@ -36,6 +37,7 @@ config TARGET_B4860QDS
 	select BOARD_LATE_INIT if CHAIN_OF_TRUST
 	select SUPPORT_SPL
 	select PHYS_64BIT
+	imply PANIC_HANG
 
 config TARGET_BSC9131RDB
 	bool "Support BSC9131RDB"
@@ -57,6 +59,7 @@ config TARGET_C29XPCIE
 	select SUPPORT_SPL
 	select SUPPORT_TPL
 	select PHYS_64BIT
+	imply PANIC_HANG
 
 config TARGET_P3041DS
 	bool "Support P3041DS"
@@ -64,6 +67,7 @@ config TARGET_P3041DS
 	select ARCH_P3041
 	select BOARD_LATE_INIT if CHAIN_OF_TRUST
 	imply CMD_SATA
+	imply PANIC_HANG
 
 config TARGET_P4080DS
 	bool "Support P4080DS"
@@ -71,6 +75,7 @@ config TARGET_P4080DS
 	select ARCH_P4080
 	select BOARD_LATE_INIT if CHAIN_OF_TRUST
 	imply CMD_SATA
+	imply PANIC_HANG
 
 config TARGET_P5020DS
 	bool "Support P5020DS"
@@ -78,6 +83,7 @@ config TARGET_P5020DS
 	select ARCH_P5020
 	select BOARD_LATE_INIT if CHAIN_OF_TRUST
 	imply CMD_SATA
+	imply PANIC_HANG
 
 config TARGET_P5040DS
 	bool "Support P5040DS"
@@ -85,6 +91,7 @@ config TARGET_P5040DS
 	select ARCH_P5040
 	select BOARD_LATE_INIT if CHAIN_OF_TRUST
 	imply CMD_SATA
+	imply PANIC_HANG
 
 config TARGET_MPC8536DS
 	bool "Support MPC8536DS"
@@ -101,6 +108,7 @@ config TARGET_MPC8541CDS
 config TARGET_MPC8544DS
 	bool "Support MPC8544DS"
 	select ARCH_MPC8544
+	imply PANIC_HANG
 
 config TARGET_MPC8548CDS
 	bool "Support MPC8548CDS"
@@ -124,6 +132,7 @@ config TARGET_MPC8572DS
 # Use DDR3 controller with DDR2 DIMMs on this board
 	select SYS_FSL_DDRC_GEN3
 	imply SCSI
+	imply PANIC_HANG
 
 config TARGET_P1010RDB_PA
 	bool "Support P1010RDB_PA"
@@ -133,6 +142,7 @@ config TARGET_P1010RDB_PA
 	select SUPPORT_TPL
 	imply CMD_EEPROM
 	imply CMD_SATA
+	imply PANIC_HANG
 
 config TARGET_P1010RDB_PB
 	bool "Support P1010RDB_PB"
@@ -142,6 +152,7 @@ config TARGET_P1010RDB_PB
 	select SUPPORT_TPL
 	imply CMD_EEPROM
 	imply CMD_SATA
+	imply PANIC_HANG
 
 config TARGET_P1022DS
 	bool "Support P1022DS"
@@ -155,6 +166,7 @@ config TARGET_P1023RDB
 	bool "Support P1023RDB"
 	select ARCH_P1023
 	imply CMD_EEPROM
+	imply PANIC_HANG
 
 config TARGET_P1020MBG
 	bool "Support P1020MBG-PC"
@@ -163,6 +175,7 @@ config TARGET_P1020MBG
 	select ARCH_P1020
 	imply CMD_EEPROM
 	imply CMD_SATA
+	imply PANIC_HANG
 
 config TARGET_P1020RDB_PC
 	bool "Support P1020RDB-PC"
@@ -171,6 +184,7 @@ config TARGET_P1020RDB_PC
 	select ARCH_P1020
 	imply CMD_EEPROM
 	imply CMD_SATA
+	imply PANIC_HANG
 
 config TARGET_P1020RDB_PD
 	bool "Support P1020RDB-PD"
@@ -179,6 +193,7 @@ config TARGET_P1020RDB_PD
 	select ARCH_P1020
 	imply CMD_EEPROM
 	imply CMD_SATA
+	imply PANIC_HANG
 
 config TARGET_P1020UTM
 	bool "Support P1020UTM"
@@ -187,6 +202,7 @@ config TARGET_P1020UTM
 	select ARCH_P1020
 	imply CMD_EEPROM
 	imply CMD_SATA
+	imply PANIC_HANG
 
 config TARGET_P1021RDB
 	bool "Support P1021RDB"
@@ -195,6 +211,7 @@ config TARGET_P1021RDB
 	select ARCH_P1021
 	imply CMD_EEPROM
 	imply CMD_SATA
+	imply PANIC_HANG
 
 config TARGET_P1024RDB
 	bool "Support P1024RDB"
@@ -203,6 +220,7 @@ config TARGET_P1024RDB
 	select ARCH_P1024
 	imply CMD_EEPROM
 	imply CMD_SATA
+	imply PANIC_HANG
 
 config TARGET_P1025RDB
 	bool "Support P1025RDB"
@@ -256,6 +274,7 @@ config TARGET_T1023RDB
 	select SUPPORT_SPL
 	select PHYS_64BIT
 	imply CMD_EEPROM
+	imply PANIC_HANG
 
 config TARGET_T1024RDB
 	bool "Support T1024RDB"
@@ -264,6 +283,7 @@ config TARGET_T1024RDB
 	select SUPPORT_SPL
 	select PHYS_64BIT
 	imply CMD_EEPROM
+	imply PANIC_HANG
 
 config TARGET_T1040QDS
 	bool "Support T1040QDS"
@@ -272,6 +292,7 @@ config TARGET_T1040QDS
 	select PHYS_64BIT
 	imply CMD_EEPROM
 	imply CMD_SATA
+	imply PANIC_HANG
 
 config TARGET_T1040RDB
 	bool "Support T1040RDB"
@@ -280,6 +301,7 @@ config TARGET_T1040RDB
 	select SUPPORT_SPL
 	select PHYS_64BIT
 	imply CMD_SATA
+	imply PANIC_HANG
 
 config TARGET_T1040D4RDB
 	bool "Support T1040D4RDB"
@@ -288,6 +310,7 @@ config TARGET_T1040D4RDB
 	select SUPPORT_SPL
 	select PHYS_64BIT
 	imply CMD_SATA
+	imply PANIC_HANG
 
 config TARGET_T1042RDB
 	bool "Support T1042RDB"
@@ -304,6 +327,7 @@ config TARGET_T1042D4RDB
 	select SUPPORT_SPL
 	select PHYS_64BIT
 	imply CMD_SATA
+	imply PANIC_HANG
 
 config TARGET_T1042RDB_PI
 	bool "Support T1042RDB_PI"
@@ -312,6 +336,7 @@ config TARGET_T1042RDB_PI
 	select SUPPORT_SPL
 	select PHYS_64BIT
 	imply CMD_SATA
+	imply PANIC_HANG
 
 config TARGET_T2080QDS
 	bool "Support T2080QDS"
@@ -328,6 +353,7 @@ config TARGET_T2080RDB
 	select SUPPORT_SPL
 	select PHYS_64BIT
 	imply CMD_SATA
+	imply PANIC_HANG
 
 config TARGET_T2081QDS
 	bool "Support T2081QDS"
@@ -342,12 +368,14 @@ config TARGET_T4160QDS
 	select SUPPORT_SPL
 	select PHYS_64BIT
 	imply CMD_SATA
+	imply PANIC_HANG
 
 config TARGET_T4160RDB
 	bool "Support T4160RDB"
 	select ARCH_T4160
 	select SUPPORT_SPL
 	select PHYS_64BIT
+	imply PANIC_HANG
 
 config TARGET_T4240QDS
 	bool "Support T4240QDS"
@@ -356,6 +384,7 @@ config TARGET_T4240QDS
 	select SUPPORT_SPL
 	select PHYS_64BIT
 	imply CMD_SATA
+	imply PANIC_HANG
 
 config TARGET_T4240RDB
 	bool "Support T4240RDB"
@@ -363,6 +392,7 @@ config TARGET_T4240RDB
 	select SUPPORT_SPL
 	select PHYS_64BIT
 	imply CMD_SATA
+	imply PANIC_HANG
 
 config TARGET_CONTROLCENTERD
 	bool "Support controlcenterd"
@@ -393,16 +423,19 @@ config TARGET_UCP1020
 	bool "Support uCP1020"
 	select ARCH_P1020
 	imply CMD_SATA
+	imply PANIC_HANG
 
 config TARGET_CYRUS_P5020
 	bool "Support Varisys Cyrus P5020"
 	select ARCH_P5020
 	select PHYS_64BIT
+	imply PANIC_HANG
 
 config TARGET_CYRUS_P5040
 	 bool "Support Varisys Cyrus P5040"
 	select ARCH_P5040
 	select PHYS_64BIT
+	imply PANIC_HANG
 
 endchoice
 

arch/x86/include/asm/arch-tangier/acpi/southcluster.asl

@@ -173,13 +173,13 @@ Device (PCI0)
         Name (RBUF, ResourceTemplate()
         {
             GpioIo(Exclusive, PullUp, 0, 0, IoRestrictionOutputOnly,
-                "\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 91 }
+                "\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 110 }
             GpioIo(Exclusive, PullUp, 0, 0, IoRestrictionOutputOnly,
-                "\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 92 }
+                "\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 111 }
             GpioIo(Exclusive, PullUp, 0, 0, IoRestrictionOutputOnly,
-                "\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 93 }
+                "\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 112 }
             GpioIo(Exclusive, PullUp, 0, 0, IoRestrictionOutputOnly,
-                "\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 94 }
+                "\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 113 }
         })
 
         Method (_CRS, 0, NotSerialized)
@@ -245,7 +245,7 @@ Device (PCI0)
         {
             Connection (
                 GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly,
-                    "\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 56 }
+                    "\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 96 }
             ),
             WFD3, 1,
         }
@@ -260,11 +260,62 @@ Device (PCI0)
             Return (STA_VISIBLE)
         }
     }
+
+    Device (HSU0)
+    {
+        Name (_ADR, 0x00040001)
+
+        Method (_STA, 0, NotSerialized)
+        {
+            Return (STA_VISIBLE)
+        }
+
+        Device (BTH0)
+        {
+            Name (_HID, "BCM2E95")
+            Name (_DEP, Package ()
+            {
+                GPIO,
+                HSU0
+            })
+
+            Method (_STA, 0, NotSerialized)
+            {
+                Return (STA_VISIBLE)
+            }
+
+            Method (_CRS, 0, NotSerialized)
+            {
+                Name (RBUF, ResourceTemplate ()
+                {
+                    UartSerialBus (0x0001C200, DataBitsEight, StopBitsOne,
+                        0xFC, LittleEndian, ParityTypeNone, FlowControlHardware,
+                        0x20, 0x20, "\\_SB.PCI0.HSU0", 0, ResourceConsumer, , )
+                    GpioInt (Level, ActiveHigh, Exclusive, PullNone, 0,
+                        "\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 185 }
+                    GpioIo (Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly,
+                        "\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 184 }
+                    GpioIo (Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly,
+                        "\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 71 }
+                })
+                Return (RBUF)
+            }
+
+            Name (_DSD, Package () {
+                ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+                Package () {
+                    Package () { "host-wakeup-gpios", Package () { ^BTH0, 0, 0, 0 } },
+                    Package () { "device-wakeup-gpios", Package () { ^BTH0, 1, 0, 0 } },
+                    Package () { "shutdown-gpios", Package () { ^BTH0, 2, 0, 0 } },
+                }
+            })
+        }
+    }
 }
 
 Device (FLIS)
 {
-    Name (_HID, "PRP0001")
+    Name (_HID, "INTC1002")
     Name (_DDN, "Intel Merrifield Family-Level Interface Shim")
     Name (RBUF, ResourceTemplate()
     {
@@ -284,13 +335,6 @@ Device (FLIS)
         Return (RBUF)
     }
 
-    Name (_DSD, Package () {
-        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
-        Package () {
-            Package () {"compatible", "intel,merrifield-pinctrl"},
-        }
-    })
-
     Method (_STA, 0, NotSerialized)
     {
         Return (STA_VISIBLE)

arch/x86/lib/Makefile

@@ -23,7 +23,6 @@ obj-y	+= interrupts.o
 obj-y	+= lpc-uclass.o
 obj-y	+= mpspec.o
 obj-$(CONFIG_ENABLE_MRC_CACHE) += mrccache.o
-obj-y += cmd_mtrr.o
 obj-y	+= northbridge-uclass.o
 obj-$(CONFIG_I8259_PIC) += i8259.o
 obj-$(CONFIG_I8254_TIMER) += i8254.o

arch/x86/lib/fsp/Makefile

@@ -4,7 +4,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-y += cmd_fsp.o
 obj-y += fsp_car.o
 obj-y += fsp_common.o
 obj-y += fsp_dram.o

board/amlogic/khadas-vim/README

@@ -1,7 +1,7 @@
 U-Boot for Khadas VIM
 =======================
 
-Khadas VIM is an Open Source DIY Box manufactured by Shenzhen Tomato
+Khadas VIM is an Open Source DIY Box manufactured by Shenzhen Wesion
 Technology Co., Ltd with the following specifications:
 
  - Amlogic S905x ARM Cortex-A53 quad-core SoC @ 2GHz

board/compulab/cm_fx6/cm_fx6.c

@@ -210,48 +210,6 @@ static int cm_fx6_setup_issd(void)
 
 #define CM_FX6_SATA_INIT_RETRIES	10
 
-# if !CONFIG_IS_ENABLED(AHCI)
-int sata_initialize(void)
-{
-	int err, i;
-
-	/* Make sure this gpio has logical 0 value */
-	gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
-	udelay(100);
-	cm_fx6_sata_power(1);
-
-	for (i = 0; i < CM_FX6_SATA_INIT_RETRIES; i++) {
-		err = setup_sata();
-		if (err) {
-			printf("SATA setup failed: %d\n", err);
-			return err;
-		}
-
-		udelay(100);
-
-		err = __sata_initialize();
-		if (!err)
-			break;
-
-		/* There is no device on the SATA port */
-		if (sata_port_status(0, 0) == 0)
-			break;
-
-		/* There's a device, but link not established. Retry */
-	}
-
-	return err;
-}
-
-int sata_stop(void)
-{
-	__sata_stop();
-	cm_fx6_sata_power(0);
-	mdelay(250);
-
-	return 0;
-}
-# endif
 #else
 static int cm_fx6_setup_issd(void) { return 0; }
 #endif
@@ -548,35 +506,6 @@ static void cm_fx6_setup_gpmi_nand(void)
 static void cm_fx6_setup_gpmi_nand(void) {}
 #endif
 
-#ifdef CONFIG_FSL_ESDHC
-static struct fsl_esdhc_cfg usdhc_cfg[3] = {
-	{USDHC1_BASE_ADDR},
-	{USDHC2_BASE_ADDR},
-	{USDHC3_BASE_ADDR},
-};
-
-static enum mxc_clock usdhc_clk[3] = {
-	MXC_ESDHC_CLK,
-	MXC_ESDHC2_CLK,
-	MXC_ESDHC3_CLK,
-};
-
-int board_mmc_init(bd_t *bis)
-{
-	int i;
-
-	cm_fx6_set_usdhc_iomux();
-	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
-		usdhc_cfg[i].sdhc_clk = mxc_get_clock(usdhc_clk[i]);
-		usdhc_cfg[i].max_bus_width = 4;
-		fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
-		enable_usdhc_clk(1, i);
-	}
-
-	return 0;
-}
-#endif
-
 #ifdef CONFIG_MXC_SPI
 int cm_fx6_setup_ecspi(void)
 {

board/dhelectronics/dh_imx6/dh_imx6_spl.c

@@ -387,10 +387,6 @@ void board_init_f(ulong dummy)
 				  &dhcom6sdl_grp_ioregs);
 	mx6_dram_cfg(&dhcom_ddr_info, &dhcom_mmdc_calib, &dhcom_mem_ddr);
 
-	/* Perform DDR DRAM calibration */
-	udelay(100);
-	mmdc_do_dqs_calibration(&dhcom_ddr_info);
-
 	/* Clear the BSS. */
 	memset(__bss_start, 0, __bss_end - __bss_start);
 

board/engicam/common/board.c

@@ -69,7 +69,7 @@ int board_late_init(void)
 #endif
 		env_set("modeboot", "mmcboot");
 		break;
-	case IMX6_BMODE_NAND:
+	case IMX6_BMODE_NAND_MIN ... IMX6_BMODE_NAND_MAX:
 		env_set("modeboot", "nandboot");
 		break;
 	default:

board/engicam/icorem6_rqs/icorem6_rqs.c

@@ -1,48 +0,0 @@
-/*
- * Copyright (C) 2016 Amarula Solutions B.V.
- * Copyright (C) 2016 Engicam S.r.l.
- * Author: Jagan Teki <jagan@amarulasolutions.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm/arch/sys_proto.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_ENV_IS_IN_MMC
-int board_mmc_get_env_dev(int devno)
-{
-	return devno - 1;
-}
-#endif
-
-#ifdef CONFIG_SPL_BUILD
-#include <spl.h>
-
-#ifdef CONFIG_ENV_IS_IN_MMC
-void board_boot_order(u32 *spl_boot_list)
-{
-	u32 bmode = imx6_src_get_boot_mode();
-	u8 boot_dev = BOOT_DEVICE_MMC1;
-
-	switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
-	case IMX6_BMODE_SD:
-	case IMX6_BMODE_ESD:
-		/* SD/eSD - BOOT_DEVICE_MMC1 */
-		break;
-	case IMX6_BMODE_MMC:
-	case IMX6_BMODE_EMMC:
-		/* MMC/eMMC */
-		boot_dev = BOOT_DEVICE_MMC2;
-		break;
-	default:
-		/* Default - BOOT_DEVICE_MMC1 */
-		printf("Wrong board boot order\n");
-		break;
-	}
-
-	spl_boot_list[0] = boot_dev;
-}
-#endif
-#endif /* CONFIG_SPL_BUILD */

board/freescale/ls1046ardb/eth.c

@@ -75,3 +75,54 @@ int board_eth_init(bd_t *bis)
 
 	return pci_eth_init(bis);
 }
+
+#ifdef CONFIG_FMAN_ENET
+int fdt_update_ethernet_dt(void *blob)
+{
+	u32 srds_s1;
+	int i, prop;
+	int offset, nodeoff;
+	const char *path;
+	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+
+	srds_s1 = in_be32(&gur->rcwsr[4]) &
+			FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
+	srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+	/* Cycle through all aliases */
+	for (prop = 0; ; prop++) {
+		const char *name;
+
+		/* FDT might have been edited, recompute the offset */
+		offset = fdt_first_property_offset(blob,
+						   fdt_path_offset(blob,
+								   "/aliases")
+						   );
+		/* Select property number 'prop' */
+		for (i = 0; i < prop; i++)
+			offset = fdt_next_property_offset(blob, offset);
+
+		if (offset < 0)
+			break;
+
+		path = fdt_getprop_by_offset(blob, offset, &name, NULL);
+		nodeoff = fdt_path_offset(blob, path);
+
+		switch (srds_s1) {
+		case 0x1133:
+			if (!strcmp(name, "ethernet0"))
+				fdt_status_disabled(blob, nodeoff);
+
+			if (!strcmp(name, "ethernet1"))
+				fdt_status_disabled(blob, nodeoff);
+		break;
+		default:
+			printf("%s: Invalid SerDes prtcl 0x%x for LS1046ARDB\n",
+			       __func__, srds_s1);
+		break;
+		}
+	}
+
+	return 0;
+}
+#endif

board/freescale/mx6memcal/Kconfig

@@ -0,0 +1,235 @@
+if TARGET_MX6MEMCAL
+
+config SYS_BOARD
+	default "mx6memcal"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "mx6memcal"
+
+menu "mx6memcal specifics"
+choice
+	prompt "Serial console"
+	help
+	  Either UART1 or UART2 will be used as the console for
+	  displaying the calibration values or errors.
+
+config SERIAL_CONSOLE_UART1
+	bool "UART1"
+	help
+	  Select this if your board uses UART1 for its' console.
+
+config SERIAL_CONSOLE_UART2
+	bool "UART2"
+	help
+	  Select this if your board uses UART2 for its' console.
+
+endchoice
+
+choice
+	prompt "UART pads"
+	help
+	  Select the RX and TX pads used for your serial console.
+	  The choices below reflect the most commonly used options
+	  for your UART.
+
+	config UART2_EIM_D26_27
+		bool "UART2 on EIM_D26/27 (SabreLite, Nitrogen6x)"
+		depends on SERIAL_CONSOLE_UART2
+		help
+		  Choose this configuration if you're using pads
+		  EIM_D26 and D27 for a console on UART2.
+		  This is typical for designs that are based on the
+		  NXP SABRELite.
+
+	config UART1_CSI0_DAT10_11
+		bool "UART1 on CSI0_DAT10/11 (Wand)"
+		depends on SERIAL_CONSOLE_UART1
+		help
+		  Choose this configuration if you're using pads
+		  CSI0_DAT10 and DAT11 for a console on UART1 as
+		  is done on the i.MX6 Wand board.
+
+	config UART1_SD3_DAT6_7
+		bool "UART1 on SD3_DAT6/7 (SabreSD, SabreAuto)"
+		depends on SERIAL_CONSOLE_UART1
+		help
+		  Choose this configuration if you're using pads
+		  SD3_DAT6 and DAT7 for a console on UART1 as is
+		  done on the NXP SABRESD or SABREAUTO designs.
+
+	config UART1_UART1
+		bool "UART1 on UART1 (i.MX6SL EVK, WaRP)"
+		depends on SERIAL_CONSOLE_UART1
+		help
+		  Choose this configuration if you're using pads
+		  UART1_TXD/RXD for a console on UART1 as is done
+		  on most i.MX6SL designs.
+
+endchoice
+
+config IMXIMAGE_OUTPUT
+	bool "Include output for imximage .cfg files"
+	default y
+	help
+	  Say "Y" if you want output formatted for use in non-SPL
+	  (DCD-style) configuration files.
+
+config DDRWIDTH
+	int "DDR bus width"
+	default 64
+	help
+	  Select either 32 or 64 to reflect the DDR bus width.
+
+config DDRCS
+	int "DDR chip selects"
+	default 2
+	range 1 2
+	help
+	  Select the number of chip selects used in your board design
+
+choice
+	prompt "Memory type"
+	help
+	  Select the type of DDR (DDR3 or LPDDR2) used on your design
+
+config	DDR3
+	bool "DDR3"
+	help
+	  Select this if your board design uses DDR3.
+
+config	LPDDR2
+	bool "LPDDR2"
+	help
+	  Select this if your board design uses LPDDR2.
+
+endchoice
+
+choice
+	prompt "Memory device"
+
+config MT41K512M16TNA
+	bool "Micron MT41K512M16TNA 512Mx16 (1GiB/chip)"
+	depends on DDR3
+
+config MT41K128M16JT
+	bool "Micron MT41K128M16JT 128Mx16 (256 MiB/chip)"
+	depends on DDR3
+
+config H5TQ4G63AFR
+	bool "Hynix H5TQ4G63AFR 256Mx16 (512 MiB/chip)"
+	depends on DDR3
+
+config H5TQ2G63DFR
+	bool "Hynix H5TQ2G63DFR 128Mx16 (256 MiB/chip)"
+	depends on DDR3
+
+config MT42L256M32D2LG
+	bool "Micron MT42L256M32D2LG LPDDR2 256Mx32 (1GiB/chip)"
+	depends on LPDDR2
+
+config MT29PZZZ4D4BKESK
+	bool "Micron MT29PZZZ4D4BKESK multi-chip 512MiB LPDDR2/4GiB eMMC"
+	depends on LPDDR2
+
+endchoice
+
+config DDR_ODT
+	int "DDR On-die-termination"
+	default 2
+	range 0 7
+	help
+	  Enter the on-die termination value as an index defined for
+	  IOMUX settings for PAD_DRAM_SDCLK0_P and others.
+	  0 == Disabled
+	  1 == 120 Ohm
+	  2 == 60 Ohm
+	  3 == 40 Ohm
+	  4 == 30 Ohm
+	  5 == 24 Ohm
+	  6 == 20 Ohm
+	  7 == 17 Ohm
+	  Value will be applied to all clock and data lines
+
+
+config DRAM_DRIVE_STRENGTH
+	int "DRAM Drive strength"
+	default 6
+	range 0 7
+	help
+	  Enter drive strength as an index defined for IOMUX settings
+	  for GRP_B1DS and others.
+	  0 == Hi Z
+	  6 == 40 Ohm (default)
+	  7 == 34 Ohm
+	  Value will be applied to all clock and data lines
+
+config RTT_NOM
+	int "RTT_NOM"
+	default 1
+	range 1 2
+	help
+	  Enter the RTT_NOM selector
+	  1 == RZQ/4 (60ohm)
+	  2 == RZQ/2 (120ohm)
+
+config RTT_WR
+	int "RTT_WR"
+	default 1
+	range 0 2
+	help
+	  Enter the RTT_WR selector for MR2
+	  0 == Dynamic ODT disabled
+	  1 == RZQ/4 (60ohm)
+	  2 == RZQ/2 (120ohm)
+
+config RALAT
+	int "Read additional latency"
+	default 5
+	range 0 7
+	help
+	  Enter a latency in number of cycles. This will be added to
+	  CAS and internal delays for which the MMDC will retrieve the
+	  read data from the internal FIFO.
+	  This is used to compensate for board/chip delays.
+
+config WALAT
+	int "Write additional latency"
+	default 0
+	range 0 7
+	help
+	  Enter a latency in number of cycles. This will be added to
+	  CAS and internal delays for which the MMDC will retrieve the
+	  read data from the internal FIFO
+	  This is used to compensate for board/chip delays.
+
+config REFSEL
+	int "Refresh period"
+	range 0 3
+	default 1
+	help
+	  Select the DDR refresh period.
+	  See the description of bitfield REF_SEL in the reference manual
+	  for details.
+	  0 == disabled
+	  1 == 32 kHz
+	  2 == 64 kHz
+	  3 == fast counter
+
+config REFR
+	int "Number of refreshes"
+	range 0 7
+	default 7
+	help
+	   This selects the number of refreshes (-1) during each period.
+	   i.e.:
+	   0 == 1 refresh (tRFC)
+	   7 == 8 refreshes (tRFC*8)
+	   See the description of MDREF[REFR] in the reference manual for
+	   details.
+
+endmenu
+endif
+

board/freescale/mx6memcal/MAINTAINERS

@@ -0,0 +1,7 @@
+MX6MEMCAL BOARD
+M:	Eric Nelson <eric@nelint.com>
+S:	Maintained
+F:	board/freescale/mx6memcal/
+F:	include/configs/mx6memcal.h
+F:	configs/mx6memcal_defconfig
+

board/freescale/mx6memcal/Makefile

@@ -0,0 +1,13 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y	:= spl.o
+else
+obj-y	:= mx6memcal.o
+endif

board/freescale/mx6memcal/README

@@ -0,0 +1,49 @@
+mx6memcal - a tool for calibrating DDR on i.MX6 boards.
+
+The mx6memcal board isn't a real board, but a tool for use in bring-up of
+new i.MX6 board designs.
+
+It provides a similar function to the tool from NXP([1]) with a number
+of advantages:
+
+1. It's open-source, so it's easier to change if needed.
+   Typical reasons for needing to change include the use of alternate
+   UARTs and PMIC initialization.
+2. It produces an image that's directly loadable with imx_usb [2] or
+   SB_LOADER.exe [3].
+   The NXP tool requires either a cumbersome JTAG connection that
+   makes running the DDR very slow or a working U-Boot image that
+   suffers from a chicken-and-egg problem (i.e. where do you get the
+   DDR parameters for U-Boot?).
+3. It doesn't prompt for parameters, so it's much faster to gather
+   data from multiple boards.
+4. Parameters to the calibration process can be chosen through
+   'make menuconfig'.
+
+When booted, the mx6memcal board will run the DDR calibration
+routines and display the result in a form suitable for cut and
+paste into struct mx6_mmdc_calibration. It can also optionally
+produce output in a form usable in a DCD-style .cfg file.
+
+Selections in Kconfig allow most system design settings to be chosen:
+
+1. The UART number and pad configuration for the UART. Options
+   include support for the most frequent reference designs on
+   i.MX6DQ/SDL (SABRE Lite and SABRESD designs).
+2. The memory bus width (64 and 32-bit)
+3. The number of chip-selects in use
+4. The type of DDR (DDR3 or LPDDR2). Note that LPDDR2 support
+   is incomplete as of this writing.
+5. The type of DDR chips in use. This selection allows re-use of common
+   parts and four DDR3 and two LPDDR2 parts are currently defined
+6. The On-die termination value for the DRAM lines
+7. The DRAM drive strength
+8. The RTT_NOM and RTT_WR termination settings
+9. RALAT/WALAT latency values
+
+References:
+[1] - NXP DDR Stress Test Tool - https://community.nxp.com/docs/DOC-105652
+[2] - Boundary Devices imx_usb_loader
+      https://github.com/boundarydevices/imx_usb_loader
+[3] - Use of SB_Loader.exe
+      https://boundarydevices.com/windows-users-and-unbricking

board/freescale/mx6memcal/mx6memcal.c

@@ -0,0 +1,32 @@
+/*
+ * mx6memcal board support - provides a minimal, UART-only
+ * U-Boot that's capable of running a memory test.
+ *
+ * Copyright (C) 2016 Nelson Integration, LLC
+ * Author: Eric Nelson <eric@nelint.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: mx6memcal\n");
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+	return 0;
+}
+

board/freescale/mx6memcal/spl.c

@@ -0,0 +1,456 @@
+/*
+ * Copyright (C) 2016 Nelson Integration, LLC
+ * Author: Eric Nelson <eric@nelint.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const uart_pads[] = {
+#ifdef CONFIG_UART2_EIM_D26_27
+	IOMUX_PADS(PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+#elif defined(CONFIG_UART1_CSI0_DAT10_11)
+	IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+	IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+#elif defined(CONFIG_UART1_SD3_DAT6_7)
+	IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+#elif defined(CONFIG_UART1_UART1)
+	MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+#else
+#error select UART console pads
+#endif
+};
+
+#ifdef CONFIG_DDR3
+#define GRP_DDRTYPE	0x000C0000
+#else
+#define GRP_DDRTYPE	0x00080000
+#endif
+
+/* all existing designs have this disabled */
+#define DDR_PKE		0
+
+/* use Kconfig for ODT and DRIVE_STRENGTH */
+#define DDR_ODT	\
+	(CONFIG_DDR_ODT << 8)
+#define DRAM_DRIVE_STRENGTH \
+	(CONFIG_DRAM_DRIVE_STRENGTH << 3)
+
+/* configure MX6Q/DUAL mmdc DDR io registers */
+static struct mx6dq_iomux_ddr_regs const mx6dq_ddr_ioregs = {
+	/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
+	.dram_sdclk_0 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+	.dram_sdclk_1 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+	.dram_cas = DDR_ODT + DRAM_DRIVE_STRENGTH,
+	.dram_ras = DDR_ODT + DRAM_DRIVE_STRENGTH,
+	.dram_reset = DDR_ODT + DRAM_DRIVE_STRENGTH,
+	/* SDCKE[0:1]: 100k pull-up */
+	.dram_sdcke0 = 0x00003000,
+	.dram_sdcke1 = 0x00003000,
+	/* SDBA2: pull-up disabled */
+	.dram_sdba2 = 0x00000000,
+	/* SDODT[0:1]: 100k pull-up, 40 ohm */
+	.dram_sdodt0 = 0x00003000 + DRAM_DRIVE_STRENGTH,
+	.dram_sdodt1 = 0x00003000 + DRAM_DRIVE_STRENGTH,
+	/* SDQS[0:7]: Differential input, 40 ohm */
+	.dram_sdqs0 = DRAM_DRIVE_STRENGTH,
+	.dram_sdqs1 = DRAM_DRIVE_STRENGTH,
+	.dram_sdqs2 = DRAM_DRIVE_STRENGTH,
+	.dram_sdqs3 = DRAM_DRIVE_STRENGTH,
+	.dram_sdqs4 = DRAM_DRIVE_STRENGTH,
+	.dram_sdqs5 = DRAM_DRIVE_STRENGTH,
+	.dram_sdqs6 = DRAM_DRIVE_STRENGTH,
+	.dram_sdqs7 = DRAM_DRIVE_STRENGTH,
+
+	/* DQM[0:7]: Differential input, 40 ohm */
+	.dram_dqm0 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+	.dram_dqm1 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+	.dram_dqm2 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+	.dram_dqm3 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+	.dram_dqm4 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+	.dram_dqm5 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+	.dram_dqm6 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+	.dram_dqm7 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+};
+
+/* configure MX6Q/DUAL mmdc GRP io registers */
+static struct mx6dq_iomux_grp_regs const mx6dq_grp_ioregs = {
+	/* DDR3 */
+	.grp_ddr_type = GRP_DDRTYPE,
+	.grp_ddrmode_ctl = DDR_ODT,
+	/* disable DDR pullups */
+	.grp_ddrpke = DDR_PKE,
+	/* ADDR[00:16], SDBA[0:1]: 40 ohm */
+	.grp_addds = DRAM_DRIVE_STRENGTH,
+	/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
+	.grp_ctlds = DRAM_DRIVE_STRENGTH,
+	/* DATA[00:63]: Differential input, 40 ohm */
+	.grp_ddrmode = DDR_ODT,
+	.grp_b0ds = DRAM_DRIVE_STRENGTH,
+	.grp_b1ds = DRAM_DRIVE_STRENGTH,
+	.grp_b2ds = DRAM_DRIVE_STRENGTH,
+	.grp_b3ds = DRAM_DRIVE_STRENGTH,
+	.grp_b4ds = DRAM_DRIVE_STRENGTH,
+	.grp_b5ds = DRAM_DRIVE_STRENGTH,
+	.grp_b6ds = DRAM_DRIVE_STRENGTH,
+	.grp_b7ds = DRAM_DRIVE_STRENGTH,
+};
+
+static struct mx6sdl_iomux_ddr_regs const mx6sdl_ddr_ioregs = {
+	/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
+	.dram_sdclk_0 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+	.dram_sdclk_1 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+	.dram_cas = DDR_ODT + DRAM_DRIVE_STRENGTH,
+	.dram_ras = DDR_ODT + DRAM_DRIVE_STRENGTH,
+	.dram_reset = DDR_ODT + DRAM_DRIVE_STRENGTH,
+	/* SDCKE[0:1]: 100k pull-up */
+	.dram_sdcke0 = 0x00003000,
+	.dram_sdcke1 = 0x00003000,
+	/* SDBA2: pull-up disabled */
+	.dram_sdba2 = 0x00000000,
+	/* SDODT[0:1]: 100k pull-up, 40 ohm */
+	.dram_sdodt0 = 0x00003000 + DRAM_DRIVE_STRENGTH,
+	.dram_sdodt1 = 0x00003000 + DRAM_DRIVE_STRENGTH,
+	/* SDQS[0:7]: Differential input, 40 ohm */
+	.dram_sdqs0 = DRAM_DRIVE_STRENGTH,
+	.dram_sdqs1 = DRAM_DRIVE_STRENGTH,
+	.dram_sdqs2 = DRAM_DRIVE_STRENGTH,
+	.dram_sdqs3 = DRAM_DRIVE_STRENGTH,
+	.dram_sdqs4 = DRAM_DRIVE_STRENGTH,
+	.dram_sdqs5 = DRAM_DRIVE_STRENGTH,
+	.dram_sdqs6 = DRAM_DRIVE_STRENGTH,
+	.dram_sdqs7 = DRAM_DRIVE_STRENGTH,
+
+	/* DQM[0:7]: Differential input, 40 ohm */
+	.dram_dqm0 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+	.dram_dqm1 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+	.dram_dqm2 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+	.dram_dqm3 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+	.dram_dqm4 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+	.dram_dqm5 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+	.dram_dqm6 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+	.dram_dqm7 = DDR_ODT + DRAM_DRIVE_STRENGTH,
+};
+
+/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
+static struct mx6sdl_iomux_grp_regs const mx6sdl_grp_ioregs = {
+	/* DDR3 */
+	.grp_ddr_type = GRP_DDRTYPE,
+	/* SDQS[0:7]: Differential input, 40 ohm */
+	.grp_ddrmode_ctl = DDR_ODT,
+	/* disable DDR pullups */
+	.grp_ddrpke = DDR_PKE,
+	/* ADDR[00:16], SDBA[0:1]: 40 ohm */
+	.grp_addds = DRAM_DRIVE_STRENGTH,
+	/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
+	.grp_ctlds = DRAM_DRIVE_STRENGTH,
+	/* DATA[00:63]: Differential input, 40 ohm */
+	.grp_ddrmode = DDR_ODT,
+	.grp_b0ds = DRAM_DRIVE_STRENGTH,
+	.grp_b1ds = DRAM_DRIVE_STRENGTH,
+	.grp_b2ds = DRAM_DRIVE_STRENGTH,
+	.grp_b3ds = DRAM_DRIVE_STRENGTH,
+	.grp_b4ds = DRAM_DRIVE_STRENGTH,
+	.grp_b5ds = DRAM_DRIVE_STRENGTH,
+	.grp_b6ds = DRAM_DRIVE_STRENGTH,
+	.grp_b7ds = DRAM_DRIVE_STRENGTH,
+};
+
+const struct mx6sl_iomux_ddr_regs mx6sl_ddr_ioregs = {
+	.dram_sdqs0 = DRAM_DRIVE_STRENGTH,
+	.dram_sdqs1 = DRAM_DRIVE_STRENGTH,
+	.dram_sdqs2 = DRAM_DRIVE_STRENGTH,
+	.dram_sdqs3 = DRAM_DRIVE_STRENGTH,
+	.dram_dqm0 = DRAM_DRIVE_STRENGTH,
+	.dram_dqm1 = DRAM_DRIVE_STRENGTH,
+	.dram_dqm2 = DRAM_DRIVE_STRENGTH,
+	.dram_dqm3 = DRAM_DRIVE_STRENGTH,
+	.dram_cas  = DRAM_DRIVE_STRENGTH,
+	.dram_ras  = DRAM_DRIVE_STRENGTH,
+	.dram_sdclk_0 = DRAM_DRIVE_STRENGTH,
+	.dram_reset = DRAM_DRIVE_STRENGTH,
+	.dram_sdba2 = 0x00020000,
+	.dram_odt0 = 0x00030000 + DRAM_DRIVE_STRENGTH,
+	.dram_odt1 = 0x00030000 + DRAM_DRIVE_STRENGTH,
+};
+
+const struct mx6sl_iomux_grp_regs mx6sl_grp_ioregs = {
+	.grp_b0ds = DRAM_DRIVE_STRENGTH,
+	.grp_b1ds = DRAM_DRIVE_STRENGTH,
+	.grp_b2ds = DRAM_DRIVE_STRENGTH,
+	.grp_b3ds = DRAM_DRIVE_STRENGTH,
+	.grp_addds = DRAM_DRIVE_STRENGTH,
+	.grp_ctlds = DRAM_DRIVE_STRENGTH,
+	.grp_ddrmode_ctl = DDR_ODT,
+	.grp_ddrpke = DDR_PKE,
+	.grp_ddrmode = DDR_ODT,
+	.grp_ddr_type = GRP_DDRTYPE,
+};
+
+static struct mx6_ddr_sysinfo const sysinfo = {
+	/* width of data bus:0=16,1=32,2=64 */
+#if CONFIG_DDRWIDTH == 32
+	.dsize = 1,
+#elif CONFIG_DDRWIDTH == 64
+	.dsize = 2,
+#else
+#error missing CONFIG_DDRWIDTH
+#endif
+	/* config for full 4GB range so that get_mem_size() works */
+	.cs_density = 32, /* 32Gb per CS */
+
+	/* # of chip selects */
+	.ncs = CONFIG_DDRCS,
+	.cs1_mirror = 0,
+	.bi_on = 1,	/* Bank interleaving enabled */
+	.rtt_nom = CONFIG_RTT_NOM,
+	.rtt_wr = CONFIG_RTT_WR,
+	.ralat = CONFIG_RALAT,	/* Read additional latency */
+	.walat = CONFIG_WALAT,	/* Write additional latency */
+	.mif3_mode = 3,	/* Command prediction working mode */
+#ifdef CONFIG_DDR3
+	.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
+	.sde_to_rst = 0x10,	/* JEDEC value for LPDDR2 - 200us */
+	.pd_fast_exit = 0,	/* immaterial for calibration */
+	.ddr_type = DDR_TYPE_DDR3,
+#else
+	.rst_to_cke = 0x10,	/* JEDEC value for LPDDR2: 200us */
+	.sde_to_rst = 0,	/* LPDDR2 does not need this field */
+	.pd_fast_exit = 0,	/* immaterial for calibration */
+	.ddr_type = DDR_TYPE_LPDDR2,
+#endif
+	.refsel = CONFIG_REFSEL,
+	.refr = CONFIG_REFR,
+};
+
+#ifdef CONFIG_MT41K512M16TNA
+/* Micron MT41K512M16TNA-125 */
+static struct mx6_ddr3_cfg const ddrtype = {
+	.mem_speed = 1600,
+	.density = 8,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 15,
+	.coladdr = 10,
+	.pagesz = 1,
+	.trcd = 1375,
+	.trcmin = 5062,
+	.trasmin = 3750,
+};
+#elif defined(CONFIG_MT41K128M16JT)
+/* Micron MT41K128M16JT-125 */
+static struct mx6_ddr3_cfg const ddrtype = {
+	.mem_speed = 1600,
+	.density = 2,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 14,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1375,
+	.trcmin = 4875,
+	.trasmin = 3500,
+};
+#elif defined(CONFIG_H5TQ4G63AFR)
+/* Hynix H5TQ4G63AFR */
+static struct mx6_ddr3_cfg const ddrtype = {
+	.mem_speed = 1600,
+	.density = 4,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 15,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1375,
+	.trcmin = 4875,
+	.trasmin = 3500,
+};
+#elif defined CONFIG_H5TQ2G63DFR
+/* Hynix H5TQ2G63DFR */
+static struct mx6_ddr3_cfg const ddrtype = {
+	.mem_speed = 1333,
+	.density = 2,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 14,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1350,
+	.trcmin = 4950,
+	.trasmin = 3600,
+};
+#elif defined(CONFIG_MT42L256M32D2LG)
+/* Micron MT42L256M32D2LG */
+static struct mx6_lpddr2_cfg ddrtype = {
+	.mem_speed = 800,
+	.density = 4,
+	.width = 32,
+	.banks = 8,
+	.rowaddr = 14,
+	.coladdr = 10,
+	.trcd_lp = 2000,
+	.trppb_lp = 2000,
+	.trpab_lp = 2250,
+	.trasmin = 4200,
+};
+#elif defined(CONFIG_MT29PZZZ4D4BKESK)
+/* Micron MT29PZZZ4D4BKESK */
+static struct mx6_lpddr2_cfg ddrtype = {
+	.mem_speed = 800,
+	.density = 4,
+	.width = 32,
+	.banks = 8,
+	.rowaddr = 14,
+	.coladdr = 10,
+	.trcd_lp = 2000,
+	.trppb_lp = 2000,
+	.trpab_lp = 2250,
+	.trasmin = 4200,
+};
+#else
+#error please select DDR type using menuconfig
+#endif
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	/* FIXME: these should probably be checked, especially
+	 * for i.MX6SL, UL, ULL
+	 */
+	writel(0x00C03F3F, &ccm->CCGR0);
+	writel(0x0030FC03, &ccm->CCGR1);
+	writel(0x0FFFC000, &ccm->CCGR2);
+	writel(0x3FF00000, &ccm->CCGR3);
+	writel(0x00FFF300, &ccm->CCGR4);
+	writel(0x0F0000C3, &ccm->CCGR5);
+	writel(0x000003FF, &ccm->CCGR6);
+}
+
+static void display_calibration(struct mx6_mmdc_calibration *calib)
+{
+	printf(".p0_mpdgctrl0\t= 0x%08X\n", calib->p0_mpdgctrl0);
+	printf(".p0_mpdgctrl1\t= 0x%08X\n", calib->p0_mpdgctrl1);
+	printf(".p0_mprddlctl\t= 0x%08X\n", calib->p0_mprddlctl);
+	printf(".p0_mpwrdlctl\t= 0x%08X\n", calib->p0_mpwrdlctl);
+	printf(".p0_mpwldectrl0\t= 0x%08X\n", calib->p0_mpwldectrl0);
+	printf(".p0_mpwldectrl1\t= 0x%08X\n", calib->p0_mpwldectrl1);
+	if (sysinfo.dsize == 2) {
+		printf(".p1_mpdgctrl0\t= 0x%08X\n", calib->p1_mpdgctrl0);
+		printf(".p1_mpdgctrl1\t= 0x%08X\n", calib->p1_mpdgctrl1);
+		printf(".p1_mprddlctl\t= 0x%08X\n", calib->p1_mprddlctl);
+		printf(".p1_mpwrdlctl\t= 0x%08X\n", calib->p1_mpwrdlctl);
+		printf(".p1_mpwldectrl0\t= 0x%08X\n", calib->p1_mpwldectrl0);
+		printf(".p1_mpwldectrl1\t= 0x%08X\n", calib->p1_mpwldectrl1);
+	}
+#ifdef CONFIG_IMXIMAGE_OUTPUT
+	printf("DATA 4 MX6_MMDC_P0_MPDGCTRL0\t= 0x%08X\n", calib->p0_mpdgctrl0);
+	printf("DATA 4 MX6_MMDC_P0_MPDGCTRL1\t= 0x%08X\n", calib->p0_mpdgctrl1);
+	printf("DATA 4 MX6_MMDC_P0_MPRDDLCTL\t= 0x%08X\n", calib->p0_mprddlctl);
+	printf("DATA 4 MX6_MMDC_P0_MPWRDLCTL\t= 0x%08X\n", calib->p0_mpwrdlctl);
+	printf("DATA 4 MX6_MMDC_P0_MPWLDECTRL0\t= 0x%08X\n",
+	       calib->p0_mpwldectrl0);
+	printf("DATA 4 MX6_MMDC_P0_MPWLDECTRL1\t= 0x%08X\n",
+	       calib->p0_mpwldectrl1);
+	if (sysinfo.dsize == 2) {
+		printf("DATA 4 MX6_MMDC_P1_MPDGCTRL0\t= 0x%08X\n",
+		       calib->p1_mpdgctrl0);
+		printf("DATA 4 MX6_MMDC_P1_MPDGCTRL1\t= 0x%08X\n",
+		       calib->p1_mpdgctrl1);
+		printf("DATA 4 MX6_MMDC_P1_MPRDDLCTL\t= 0x%08X\n",
+		       calib->p1_mprddlctl);
+		printf("DATA 4 MX6_MMDC_P1_MPWRDLCTL\t= 0x%08X\n",
+		       calib->p1_mpwrdlctl);
+		printf("DATA 4 MX6_MMDC_P1_MPWLDECTRL0\t= 0x%08X\n",
+		       calib->p1_mpwldectrl0);
+		printf("DATA 4 MX6_MMDC_P1_MPWLDECTRL1\t= 0x%08X\n",
+		       calib->p1_mpwldectrl1);
+	}
+#endif
+}
+
+/*
+ * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
+ * - we have a stack and a place to store GD, both in SRAM
+ * - no variable global data is available
+ */
+void board_init_f(ulong dummy)
+{
+	int errs;
+	struct mx6_mmdc_calibration calibration = {0};
+
+	memset((void *)gd, 0, sizeof(struct global_data));
+
+	/* write leveling calibration defaults */
+	calibration.p0_mpwrdlctl = 0x40404040;
+	calibration.p1_mpwrdlctl = 0x40404040;
+
+	/* setup AIPS and disable watchdog */
+	arch_cpu_init();
+
+	ccgr_init();
+
+	SETUP_IOMUX_PADS(uart_pads);
+
+	/* setup GP timer */
+	timer_init();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+	if (sysinfo.dsize != 1) {
+		if (is_cpu_type(MXC_CPU_MX6SX) ||
+		    is_cpu_type(MXC_CPU_MX6UL) ||
+		    is_cpu_type(MXC_CPU_MX6SL)) {
+			printf("cpu type 0x%x doesn't support 64-bit bus\n",
+			       get_cpu_type());
+			reset_cpu(0);
+		}
+	}
+#ifdef CONFIG_MX6SL
+	mx6sl_dram_iocfg(CONFIG_DDRWIDTH, &mx6sl_ddr_ioregs,
+			 &mx6sl_grp_ioregs);
+#else
+	if (is_cpu_type(MXC_CPU_MX6Q)) {
+		mx6dq_dram_iocfg(CONFIG_DDRWIDTH, &mx6dq_ddr_ioregs,
+				 &mx6dq_grp_ioregs);
+	} else {
+		mx6sdl_dram_iocfg(CONFIG_DDRWIDTH, &mx6sdl_ddr_ioregs,
+				  &mx6sdl_grp_ioregs);
+	}
+#endif
+	mx6_dram_cfg(&sysinfo, &calibration, &ddrtype);
+
+	errs = mmdc_do_write_level_calibration(&sysinfo);
+	if (errs) {
+		printf("error %d from write level calibration\n", errs);
+	} else {
+		errs = mmdc_do_dqs_calibration(&sysinfo);
+		if (errs) {
+			printf("error %d from write level calibration\n", errs);
+		} else {
+			printf("completed successfully\n");
+			mmdc_read_calibration(&sysinfo, &calibration);
+			display_calibration(&calibration);
+		}
+	}
+	reset_cpu(0);
+}

board/freescale/mx6sabreauto/mx6sabreauto.c

@@ -397,39 +397,9 @@ int board_eth_init(bd_t *bis)
 	return cpu_eth_init(bis);
 }
 
-#define BOARD_REV_B  0x200
-#define BOARD_REV_A  0x100
-
-static int mx6sabre_rev(void)
-{
-	/*
-	 * Get Board ID information from OCOTP_GP1[15:8]
-	 * i.MX6Q ARD RevA: 0x01
-	 * i.MX6Q ARD RevB: 0x02
-	 */
-	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
-	struct fuse_bank *bank = &ocotp->bank[4];
-	struct fuse_bank4_regs *fuse =
-			(struct fuse_bank4_regs *)bank->fuse_regs;
-	int reg = readl(&fuse->gp1);
-	int ret;
-
-	switch (reg >> 8 & 0x0F) {
-	case 0x02:
-		ret = BOARD_REV_B;
-		break;
-	case 0x01:
-	default:
-		ret = BOARD_REV_A;
-		break;
-	}
-
-	return ret;
-}
-
 u32 get_board_rev(void)
 {
-	int rev = mx6sabre_rev();
+	int rev = nxp_board_rev();
 
 	return (get_cpu_rev() & ~(0xF << 8)) | rev;
 }
@@ -703,20 +673,7 @@ int board_late_init(void)
 
 int checkboard(void)
 {
-	int rev = mx6sabre_rev();
-	char *revname;
-
-	switch (rev) {
-	case BOARD_REV_B:
-		revname = "B";
-		break;
-	case BOARD_REV_A:
-	default:
-		revname = "A";
-		break;
-	}
-
-	printf("Board: MX6Q-Sabreauto rev%s\n", revname);
+	printf("Board: MX6Q-Sabreauto rev%c\n", nxp_board_rev_string());
 
 	return 0;
 }

board/freescale/mx6slevk/imximage.cfg

@@ -8,6 +8,8 @@
  *
  * The syntax is taken as close as possible with the kwbimage
  */
+#define __ASSEMBLY__
+#include <config.h>
 
 /* image version */
 
@@ -20,6 +22,13 @@ IMAGE_VERSION 2
 
 BOOT_FROM	sd
 
+/*
+ * Secure boot support
+ */
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
+
 /*
  * Device Configuration Data (DCD)
  *

board/freescale/mx6sxsabresd/mx6sxsabresd.c

@@ -540,9 +540,23 @@ int board_init(void)
 	return 0;
 }
 
+static bool is_reva(void)
+{
+	return (nxp_board_rev() == 1);
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	if (is_reva())
+		env_set("board_rev", "REVA");
+#endif
+	return 0;
+}
+
 int checkboard(void)
 {
-	puts("Board: MX6SX SABRE SDB\n");
+	printf("Board: MX6SX SABRE SDB rev%c\n", nxp_board_rev_string());
 
 	return 0;
 }

board/ge/common/Makefile

@@ -4,4 +4,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-y  := vpd_reader.o
+obj-y  := vpd_reader.o ge_common.o

board/ge/common/ge_common.c

@@ -0,0 +1,55 @@
+/*
+ * Copyright 2017 General Electric Company
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <rtc.h>
+
+void check_time(void)
+{
+	int ret, i;
+	struct rtc_time tm;
+	u8 retry = 3;
+
+	unsigned int current_i2c_bus = i2c_get_bus_num();
+
+	ret = i2c_set_bus_num(CONFIG_SYS_RTC_BUS_NUM);
+	if (ret < 0)
+		return;
+
+	rtc_init();
+
+	for (i = 0; i < retry; i++) {
+		ret = rtc_get(&tm);
+		if (!ret || ret == -EINVAL)
+			break;
+	}
+
+	if (ret < 0)
+		env_set("rtc_status", "RTC_ERROR");
+
+	if (tm.tm_year > 2037) {
+		tm.tm_sec  = 0;
+		tm.tm_min  = 0;
+		tm.tm_hour = 0;
+		tm.tm_mday = 1;
+		tm.tm_wday = 2;
+		tm.tm_mon  = 1;
+		tm.tm_year = 2036;
+
+		for (i = 0; i < retry; i++) {
+			ret = rtc_set(&tm);
+			if (!ret)
+				break;
+		}
+
+		if (ret < 0)
+			env_set("rtc_status", "RTC_ERROR");
+	}
+
+	i2c_set_bus_num(current_i2c_bus);
+}
+

board/ge/common/ge_common.h

@@ -0,0 +1,7 @@
+/*
+ * Copyright 2017 General Electric Company
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+void check_time(void);

board/ge/mx53ppd/mx53ppd.c

@@ -33,8 +33,8 @@
 #include <watchdog.h>
 #include "ppd_gpio.h"
 #include <stdlib.h>
+#include "../../ge/common/ge_common.h"
 #include "../../ge/common/vpd_reader.h"
-#include <rtc.h>
 
 #define MX53PPD_LCD_POWER		IMX_GPIO_NR(3, 24)
 
@@ -357,51 +357,6 @@ static int read_vpd(uint eeprom_bus)
 	return res;
 }
 
-static void check_time(void)
-{
-	int ret, i;
-	struct rtc_time tm;
-	u8 retry = 3;
-
-	unsigned int current_i2c_bus = i2c_get_bus_num();
-
-	ret = i2c_set_bus_num(CONFIG_SYS_RTC_BUS_NUM);
-	if (ret < 0)
-		return;
-
-	rtc_init();
-
-	for (i = 0; i < retry; i++) {
-		ret = rtc_get(&tm);
-		if (!ret || ret == -EINVAL)
-			break;
-	}
-
-	if (ret < 0)
-		env_set("rtc_status", "RTC_ERROR");
-
-	if (tm.tm_year > 2037) {
-		tm.tm_sec  = 0;
-		tm.tm_min  = 0;
-		tm.tm_hour = 0;
-		tm.tm_mday = 1;
-		tm.tm_wday = 2;
-		tm.tm_mon  = 1;
-		tm.tm_year = 2036;
-
-		for (i = 0; i < retry; i++) {
-			ret = rtc_set(&tm);
-			if (!ret)
-				break;
-		}
-
-		if (ret < 0)
-			env_set("rtc_status", "RTC_ERROR");
-	}
-
-	i2c_set_bus_num(current_i2c_bus);
-}
-
 int board_init(void)
 {
 	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;

board/sunxi/MAINTAINERS

@@ -286,6 +286,11 @@ M:	Jagan Teki <jagan@amarulasolutions.com>
 S:	Maintained
 F:	configs/nanopi_neo2_defconfig
 
+NANOPI-NEO-PLUS2 BOARD
+M:	Antony Antony <antony@phenome.org>
+S:	Maintained
+F:	configs/nanopi_neo_plus2_defconfig
+
 NANOPI-NEO-AIR BOARD
 M:	Jelle van der Waa <jelle@vdwaa.nl>
 S:	Maintained

board/sunxi/gmac.c

@@ -33,7 +33,11 @@ void eth_init_board(void)
 
 #ifndef CONFIG_MACH_SUN6I
 	/* Configure pin mux settings for GMAC */
+#ifdef CONFIG_SUN7I_GMAC_FORCE_TXERR
+	for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++) {
+#else
 	for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) {
+#endif
 #ifdef CONFIG_RGMII
 		/* skip unused pins in RGMII mode */
 		if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14))

board/theobroma-systems/lion_rk3368/Kconfig

@@ -12,4 +12,10 @@ config SYS_CONFIG_NAME
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 
+config ENV_SIZE
+	default 0x2000
+
+config ENV_OFFSET
+	default 0x3c000 if ENV_IS_IN_SPI_FLASH
+
 endif

board/theobroma-systems/puma_rk3399/Kconfig

@@ -13,7 +13,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 
 config ENV_SIZE
-	default 0x2000 if ENV_IS_IN_SPI_FLASH
+	default 0x2000
 
 config ENV_OFFSET
 	default 0x3c000 if ENV_IS_IN_SPI_FLASH

board/ti/evm/evm.c

@@ -299,26 +299,12 @@ static void reset_net_chip(void)
 
 int board_eth_init(bd_t *bis)
 {
-	int rc = 0;
 #if defined(CONFIG_SMC911X)
-#define STR_ENV_ETHADDR	"ethaddr"
-
-	struct eth_device *dev;
-	uchar eth_addr[6];
-
-	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
-
-	if (!eth_env_get_enetaddr(STR_ENV_ETHADDR, eth_addr)) {
-		dev = eth_get_dev_by_index(0);
-		if (dev) {
-			eth_env_set_enetaddr(STR_ENV_ETHADDR, dev->enetaddr);
-		} else {
-			printf("omap3evm: Couldn't get eth device\n");
-			rc = -1;
-		}
-	}
-#endif /* CONFIG_SMC911X */
-	return rc;
+	env_set("ethaddr", NULL);
+	return smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#else
+	return 0;
+#endif
 }
 #endif /* CONFIG_CMD_NET */
 

board/warp/imximage.cfg

@@ -8,6 +8,8 @@
  *
  * The syntax is taken as close as possible with the kwbimage
  */
+#define __ASSEMBLY__
+#include <config.h>
 
 /* image version */
 
@@ -20,6 +22,13 @@ IMAGE_VERSION 2
 
 BOOT_FROM	sd
 
+/*
+ * Secure boot support
+ */
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
+
 /*
  * Device Configuration Data (DCD)
  *

cmd/Makefile

@@ -150,6 +150,8 @@ obj-$(CONFIG_CMD_PMIC) += pmic.o
 obj-$(CONFIG_CMD_REGULATOR) += regulator.o
 
 obj-$(CONFIG_CMD_BLOB) += blob.o
+
+obj-$(CONFIG_X86) += x86/
 endif # !CONFIG_SPL_BUILD
 
 # core command

cmd/fastboot/Kconfig

@@ -66,6 +66,7 @@ config FASTBOOT_USB_DEV
 
 config FASTBOOT_FLASH
 	bool "Enable FASTBOOT FLASH command"
+	default y if ARCH_SUNXI
 	help
 	  The fastboot protocol includes a "flash" command for writing
 	  the downloaded image to a non-volatile storage device. Define

cmd/x86/Makefile

@@ -0,0 +1,6 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += mtrr.o
+obj-$(CONFIG_HAVE_FSP) += fsp.o

common/fdt_support.c

@@ -508,12 +508,16 @@ int fdt_fixup_memory(void *blob, u64 start, u64 size)
 
 void fdt_fixup_ethernet(void *fdt)
 {
-	int i, j, prop;
+	int i = 0, j, prop;
 	char *tmp, *end;
 	char mac[16];
 	const char *path;
 	unsigned char mac_addr[ARP_HLEN];
 	int offset;
+#ifdef FDT_SEQ_MACADDR_FROM_ENV
+	int nodeoff;
+	const struct fdt_property *fdt_prop;
+#endif
 
 	if (fdt_path_offset(fdt, "/aliases") < 0)
 		return;
@@ -526,7 +530,7 @@ void fdt_fixup_ethernet(void *fdt)
 		offset = fdt_first_property_offset(fdt,
 			fdt_path_offset(fdt, "/aliases"));
 		/* Select property number 'prop' */
-		for (i = 0; i < prop; i++)
+		for (j = 0; j < prop; j++)
 			offset = fdt_next_property_offset(fdt, offset);
 
 		if (offset < 0)
@@ -535,11 +539,16 @@ void fdt_fixup_ethernet(void *fdt)
 		path = fdt_getprop_by_offset(fdt, offset, &name, NULL);
 		if (!strncmp(name, "ethernet", 8)) {
 			/* Treat plain "ethernet" same as "ethernet0". */
-			if (!strcmp(name, "ethernet"))
+			if (!strcmp(name, "ethernet")
+#ifdef FDT_SEQ_MACADDR_FROM_ENV
+			 || !strcmp(name, "ethernet0")
+#endif
+			)
 				i = 0;
+#ifndef FDT_SEQ_MACADDR_FROM_ENV
 			else
 				i = trailing_strtol(name);
-
+#endif
 			if (i != -1) {
 				if (i == 0)
 					strcpy(mac, "ethaddr");
@@ -548,6 +557,14 @@ void fdt_fixup_ethernet(void *fdt)
 			} else {
 				continue;
 			}
+#ifdef FDT_SEQ_MACADDR_FROM_ENV
+			nodeoff = fdt_path_offset(fdt, path);
+			fdt_prop = fdt_get_property(fdt, nodeoff, "status",
+						    NULL);
+			if (fdt_prop && !strcmp(fdt_prop->data, "disabled"))
+				continue;
+			i++;
+#endif
 			tmp = env_get(mac);
 			if (!tmp)
 				continue;

common/spl/Kconfig

@@ -721,10 +721,24 @@ config SPL_ATF
 	bool "Support ARM Trusted Firmware"
 	depends on ARM64
 	help
-	  ATF(ARM Trusted Firmware) is a component for ARM arch64 which
-	  is loaded by SPL(which is considered as BL2 in ATF terminology).
+	  ATF(ARM Trusted Firmware) is a component for ARM AArch64 which
+	  is loaded by SPL (which is considered as BL2 in ATF terminology).
 	  More detail at: https://github.com/ARM-software/arm-trusted-firmware
 
+config SPL_ATF_NO_PLATFORM_PARAM
+        bool "Pass no platform parameter"
+	depends on SPL_ATF
+	help
+	  While we expect to call a pointer to a valid FDT (or NULL)
+	  as the platform parameter to an ATF, some ATF versions are
+	  not U-Boot aware and have an insufficiently robust parameter
+	  validation to gracefully reject a FDT being passed.
+
+	  If this option is enabled, the spl_atf os-type handler will
+	  always pass NULL for the platform parameter.
+
+	  If your ATF is affected, say Y.
+
 config TPL
 	bool
 	depends on SUPPORT_TPL

common/spl/spl_atf.c

@@ -144,6 +144,7 @@ void spl_invoke_atf(struct spl_image_info *spl_image)
 {
 	uintptr_t  bl33_entry = CONFIG_SYS_TEXT_BASE;
 	void *blob = spl_image->fdt_addr;
+	uintptr_t platform_param = (uintptr_t)blob;
 	int node;
 
 	/*
@@ -157,9 +158,18 @@ void spl_invoke_atf(struct spl_image_info *spl_image)
 	if (node >= 0)
 		bl33_entry = spl_fit_images_get_entry(blob, node);
 
+	/*
+	 * If ATF_NO_PLATFORM_PARAM is set, we override the platform
+	 * parameter and always pass 0.  This is a workaround for
+	 * older ATF versions that have insufficiently robust (or
+	 * overzealous) argument validation.
+	 */
+	if (CONFIG_IS_ENABLED(ATF_NO_PLATFORM_PARAM))
+		platform_param = 0;
+
 	/*
 	 * We don't provide a BL3-2 entry yet, but this will be possible
 	 * using similar logic.
 	 */
-	bl31_entry(spl_image->entry_point, bl33_entry, (uintptr_t)blob);
+	bl31_entry(spl_image->entry_point, bl33_entry, platform_param);
 }

configs/A13-OLinuXino_defconfig

@@ -16,7 +16,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-olinuxino"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_FASTBOOT_FLASH=y
 CONFIG_CMD_DFU=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set

configs/A20-OLinuXino-Lime2-eMMC_defconfig

@@ -13,7 +13,6 @@ CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_FASTBOOT_FLASH=y
 CONFIG_CMD_DFU=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set

configs/A20-OLinuXino-Lime2_defconfig

@@ -12,7 +12,6 @@ CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_FASTBOOT_FLASH=y
 CONFIG_CMD_DFU=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set

configs/A20-OLinuXino_MICRO-eMMC_defconfig

@@ -20,6 +20,7 @@ CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SCSI_AHCI=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SUN7I_GMAC=y
+CONFIG_SUN7I_GMAC_FORCE_TXERR=y
 CONFIG_AXP_ALDO3_VOLT=2800
 CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_SCSI=y

configs/A20-OLinuXino_MICRO_defconfig

@@ -21,6 +21,7 @@ CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SCSI_AHCI=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SUN7I_GMAC=y
+CONFIG_SUN7I_GMAC_FORCE_TXERR=y
 CONFIG_AXP_ALDO3_VOLT=2800
 CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_SCSI=y

configs/A33-OLinuXino_defconfig

@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
+CONFIG_CONS_INDEX=1
 CONFIG_MACH_SUN8I_A33=y
 CONFIG_DRAM_CLK=432
 CONFIG_DRAM_ZQ=15291

configs/CHIP_defconfig

@@ -7,7 +7,6 @@ CONFIG_VIDEO_COMPOSITE=y
 CONFIG_DEFAULT_DEVICE_TREE="sun5i-r8-chip"
 CONFIG_SPL=y
 CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_FASTBOOT_FLASH=y
 CONFIG_CMD_DFU=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_SPL_DOS_PARTITION is not set

configs/CHIP_pro_defconfig

@@ -8,7 +8,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-gr8-chip-pro"
 CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BLOCK_SIZE=0x40000,SYS_NAND_PAGE_SIZE=4096,SYS_NAND_OOBSIZE=256"
 CONFIG_SPL=y
 CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_FASTBOOT_FLASH=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_LOADB is not set

configs/Cubietruck_defconfig

@@ -14,7 +14,6 @@ CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_FASTBOOT_FLASH=y
 CONFIG_CMD_DFU=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set

configs/Nintendo_NES_Classic_Edition_defconfig

@@ -9,7 +9,6 @@ CONFIG_AXP_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-r16-nintendo-nes-classic-edition"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_FASTBOOT_FLASH=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 # CONFIG_SPL_DOS_PARTITION is not set

configs/Sinlinx_SinA33_defconfig

@@ -14,7 +14,6 @@ CONFIG_VIDEO_LCD_BL_PWM="PH0"
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-sinlinx-sina33"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_FASTBOOT_FLASH=y
 CONFIG_CMD_DFU=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set

configs/TWR-P1025_defconfig

@@ -35,4 +35,5 @@ CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
+CONFIG_PANIC_HANG=y
 CONFIG_OF_LIBFDT=y

configs/UCP1020_SPIFLASH_defconfig

@@ -43,4 +43,5 @@ CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_FS_CRAMFS=y
+CONFIG_PANIC_HANG=y
 CONFIG_OF_LIBFDT=y

configs/UCP1020_defconfig

@@ -43,4 +43,5 @@ CONFIG_FSL_ESPI=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_FS_CRAMFS=y
+CONFIG_PANIC_HANG=y
 CONFIG_OF_LIBFDT=y

configs/adp-ae3xx_defconfig

@@ -39,3 +39,4 @@ CONFIG_DM_SPI=y
 CONFIG_ATCSPI200_SPI=y
 CONFIG_TIMER=y
 CONFIG_ATCPIT100_TIMER=y
+CONFIG_PANIC_HANG=y

configs/am335x_boneblack_defconfig

@@ -5,6 +5,7 @@ CONFIG_AM33XX=y
 # CONFIG_SPL_NAND_SUPPORT is not set
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT"
+CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd"
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
 CONFIG_VERSION_VARIABLE=y
 CONFIG_ARCH_MISC_INIT=y

configs/am335x_boneblack_vboot_defconfig

@@ -8,6 +8,7 @@ CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT"
+CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd"
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
 CONFIG_VERSION_VARIABLE=y
 CONFIG_ARCH_MISC_INIT=y

configs/cm_fx6_defconfig

@@ -12,9 +12,11 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y
 # CONFIG_CMD_BMODE is not set
 CONFIG_DEFAULT_DEVICE_TREE="imx6q-cm-fx6"
 CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
 CONFIG_BOOTDELAY=3
+CONFIG_BOOTCOMMAND="run distro_bootcmd; run legacy_bootcmd"
 CONFIG_SPL=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x80
 CONFIG_SPL_I2C_SUPPORT=y
@@ -53,6 +55,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:768k(uboot),256k(uboot-environment),-(r
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_DWC_AHSATA=y
+CONFIG_DM_KEYBOARD=y
 CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y

configs/display5_factory_defconfig

@@ -11,6 +11,8 @@ CONFIG_FIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
 CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run factory"
 CONFIG_SPL=y
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set

configs/firefly-rk3399_defconfig

@@ -15,6 +15,7 @@ CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py"
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
 CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y

configs/mx23evk_defconfig

@@ -4,7 +4,6 @@ CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_BOOTDELAY=1
 # CONFIG_CONSOLE_MUX is not set
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_VERSION_VARIABLE=y

configs/mx25pdk_defconfig

@@ -2,7 +2,6 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX25=y
 CONFIG_TARGET_MX25PDK=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx25pdk/imximage.cfg"
-CONFIG_BOOTDELAY=1
 CONFIG_DEFAULT_FDT_FILE="imx25-pdk.dtb"
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y

configs/mx28evk_auart_console_defconfig

@@ -5,7 +5,6 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SYS_EXTRA_OPTIONS="MXS_AUART,MXS_AUART_BASE=MXS_UARTAPP3_BASE"
-CONFIG_BOOTDELAY=1
 # CONFIG_CONSOLE_MUX is not set
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_VERSION_VARIABLE=y

configs/mx28evk_defconfig

@@ -5,7 +5,6 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_FIT=y
-CONFIG_BOOTDELAY=1
 # CONFIG_CONSOLE_MUX is not set
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_VERSION_VARIABLE=y

configs/mx28evk_nand_defconfig

@@ -4,7 +4,6 @@ CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_BOOTDELAY=1
 # CONFIG_CONSOLE_MUX is not set
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_VERSION_VARIABLE=y

configs/mx28evk_spi_defconfig

@@ -4,7 +4,6 @@ CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_BOOTDELAY=1
 # CONFIG_CONSOLE_MUX is not set
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_VERSION_VARIABLE=y