Prepare v2018.03-rc2

Signed-off-by: Tom Rini <trini@konsulko.com>

.travis.yml

@@ -101,9 +101,8 @@ script:
  #
  # Exit code 129 means warnings only.
  - if [[ "${BUILDMAN}" != "" ]]; then
-     set +e;
-     tools/buildman/buildman -P ${BUILDMAN};
-     ret=$?;
+     ret=0;
+     tools/buildman/buildman -P -E ${BUILDMAN} || ret=$?;
      if [[ $ret -ne 0 && $ret -ne 129 ]]; then
        tools/buildman/buildman -sdeP ${BUILDMAN};
        exit $ret;

Kconfig

@@ -69,20 +69,32 @@ config DISTRO_DEFAULTS
 	imply USE_BOOTCOMMAND
 	select CMD_BOOTZ if ARM && !ARM64
 	select CMD_BOOTI if ARM64
-	select CMD_DHCP
-	select CMD_PXE
+	select CMD_DHCP if NET
+	select CMD_PXE if NET
 	select CMD_EXT2
 	select CMD_EXT4
 	select CMD_FAT
 	select CMD_FS_GENERIC
-	select CMD_MII
-	select CMD_PING
+	select CMD_MII if NET
+	select CMD_PING if NET
 	select CMD_PART
 	select HUSH_PARSER
 	help
 	  Select this to enable various options and commands which are suitable
 	  for building u-boot for booting general purpose Linux distributions.
 
+config SYS_BOOT_GET_CMDLINE
+	bool "Enable kernel command line setup"
+	help
+	  Enables allocating and saving kernel cmdline in space between
+	  "bootm_low" and "bootm_low" + BOOTMAPSZ.
+
+config SYS_BOOT_GET_KBD
+	bool "Enable kernel board information setup"
+	help
+	  Enables allocating and saving a kernel copy of the bd_info in
+	  space between "bootm_low" and "bootm_low" + BOOTMAPSZ.
+
 config SYS_MALLOC_F
 	bool "Enable malloc() pool before relocation"
 	default y if DM
@@ -366,15 +378,13 @@ config SYS_EXTRA_OPTIONS
 	  new boards should not use this option.
 
 config SYS_TEXT_BASE
-	depends on ARC || X86 || ARCH_UNIPHIER || ARCH_ZYNQMP || \
-		(M68K && !TARGET_ASTRO_MCF5373L) || MICROBLAZE || MIPS || \
-		ARCH_ZYNQ || ARCH_KEYSTONE || ARCH_OMAP2PLUS
+	depends on !NIOS2 && !XTENSA
 	depends on !EFI_APP
+	default 0x80800000 if ARCH_OMAP2PLUS
 	hex "Text Base"
 	help
-	  TODO: Move CONFIG_SYS_TEXT_BASE for all the architecture
+	  The address in memory that U-Boot will be running from, initially.
 
-	default 0x80800000 if ARCH_OMAP2PLUS
 
 
 config SYS_CLK_FREQ

MAINTAINERS

@@ -205,7 +205,7 @@ F:	arch/arm/include/asm/arch-sti*/
 
 ARM SUNXI
 M:	Jagan Teki <jagan@openedev.com>
-M:	Maxime Ripard <maxime.ripard@free-electrons.com>
+M:	Maxime Ripard <maxime.ripard@bootlin.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-sunxi.git
 F:	arch/arm/cpu/armv7/sunxi/
@@ -289,8 +289,11 @@ EFI PAYLOAD
 M:	Alexander Graf <agraf@suse.de>
 S:	Maintained
 T:	git git://github.com/agraf/u-boot.git
+F:	doc/README.efi
 F:	doc/README.iscsi
 F:	include/efi*
+F:	include/pe.h
+F:	include/asm-generic/pe.h
 F:	lib/efi*/
 F:	test/py/tests/test_efi*
 F:	cmd/bootefi.c

Makefile

@@ -5,7 +5,7 @@
 VERSION = 2018
 PATCHLEVEL = 03
 SUBLEVEL =
-EXTRAVERSION = -rc1
+EXTRAVERSION = -rc2
 NAME =
 
 # *DOCUMENTATION*

README

@@ -2311,18 +2311,6 @@ The following options need to be configured:
 		CONFIG_SF_DEFAULT_MODE 		(see include/spi.h)
 		CONFIG_SF_DEFAULT_SPEED		in Hz
 
-		CONFIG_SYSTEMACE
-
-		Adding this option adds support for Xilinx SystemACE
-		chips attached via some sort of local bus. The address
-		of the chip must also be defined in the
-		CONFIG_SYS_SYSTEMACE_BASE macro. For example:
-
-		#define CONFIG_SYSTEMACE
-		#define CONFIG_SYS_SYSTEMACE_BASE 0xf0000000
-
-		When SystemACE support is added, the "ace" device type
-		becomes available to the fat commands, i.e. fatls.
 
 - TFTP Fixed UDP Port:
 		CONFIG_TFTP_PORT
@@ -3719,6 +3707,11 @@ this behavior and build U-Boot to some external directory:
 Note that the command line "O=" setting overrides the KBUILD_OUTPUT environment
 variable.
 
+User specific CPPFLAGS, AFLAGS and CFLAGS can be passed to the compiler by
+setting the according environment variables KCPPFLAGS, KAFLAGS and KCFLAGS.
+For example to treat all compiler warnings as errors:
+
+	make KCFLAGS=-Werror
 
 Please be aware that the Makefiles assume you are using GNU make, so
 for instance on NetBSD you might need to use "gmake" instead of

arch/Kconfig

@@ -26,6 +26,8 @@ config ARM
 config M68K
 	bool "M68000 architecture"
 	select HAVE_PRIVATE_LIBGCC
+	select SYS_BOOT_GET_CMDLINE
+	select SYS_BOOT_GET_KBD
 
 config MICROBLAZE
 	bool "MicroBlaze architecture"
@@ -53,6 +55,8 @@ config PPC
 	bool "PowerPC architecture"
 	select HAVE_PRIVATE_LIBGCC
 	select SUPPORT_OF_CONTROL
+	select SYS_BOOT_GET_CMDLINE
+	select SYS_BOOT_GET_KBD
 
 config RISCV
 	bool "riscv architecture"
@@ -70,6 +74,7 @@ config SANDBOX
 	select DM_SPI
 	select DM_GPIO
 	select DM_MMC
+	select HAVE_BLOCK_DEVICE
 	select LZO
 	imply CMD_GETTIME
 	imply CMD_HASH

arch/arm/Kconfig

@@ -396,63 +396,6 @@ config TARGET_APF27
 	select CPU_ARM926EJS
 	select SUPPORT_SPL
 
-config TARGET_APX4DEVKIT
-	bool "Support apx4devkit"
-	select CPU_ARM926EJS
-	select SUPPORT_SPL
-	select PL011_SERIAL
-
-config TARGET_XFI3
-	bool "Support xfi3"
-	select CPU_ARM926EJS
-	select SUPPORT_SPL
-	select PL011_SERIAL
-
-config TARGET_M28EVK
-	bool "Support m28evk"
-	select CPU_ARM926EJS
-	select SUPPORT_SPL
-	select PL011_SERIAL
-
-config TARGET_MX23EVK
-	bool "Support mx23evk"
-	select CPU_ARM926EJS
-	select SUPPORT_SPL
-	select BOARD_EARLY_INIT_F
-	select PL011_SERIAL
-
-config TARGET_MX28EVK
-	bool "Support mx28evk"
-	select CPU_ARM926EJS
-	select SUPPORT_SPL
-	select BOARD_EARLY_INIT_F
-	select PL011_SERIAL
-
-config TARGET_MX23_OLINUXINO
-	bool "Support mx23_olinuxino"
-	select CPU_ARM926EJS
-	select SUPPORT_SPL
-	select BOARD_EARLY_INIT_F
-	select PL011_SERIAL
-
-config TARGET_BG0900
-	bool "Support bg0900"
-	select CPU_ARM926EJS
-	select SUPPORT_SPL
-	select PL011_SERIAL
-
-config TARGET_SANSA_FUZE_PLUS
-	bool "Support sansa_fuze_plus"
-	select CPU_ARM926EJS
-	select SUPPORT_SPL
-	select PL011_SERIAL
-
-config TARGET_SC_SPS_1
-	bool "Support sc_sps_1"
-	select CPU_ARM926EJS
-	select SUPPORT_SPL
-	select PL011_SERIAL
-
 config ORION5X
 	bool "Marvell Orion"
 	select CPU_ARM926EJS
@@ -660,14 +603,34 @@ config ARCH_MESON
 	  targeted at media players and tablet computers. We currently
 	  support the S905 (GXBaby) 64-bit SoC.
 
+config ARCH_MX8M
+	bool "NXP i.MX8M platform"
+	select ARM64
+	select DM
+	select SUPPORT_SPL
+
+config ARCH_MX23
+	bool "NXP i.MX23 family"
+	select CPU_ARM926EJS
+	select PL011_SERIAL
+	select SUPPORT_SPL
+
 config ARCH_MX25
 	bool "NXP MX25"
 	select CPU_ARM926EJS
+	imply MXC_GPIO
+
+config ARCH_MX28
+	bool "NXP i.MX28 family"
+	select CPU_ARM926EJS
+	select PL011_SERIAL
+	select SUPPORT_SPL
 
 config ARCH_MX7ULP
         bool "NXP MX7ULP"
         select CPU_V7
 	select ROM_UNIFIED_SECTIONS
+	imply MXC_GPIO
 
 config ARCH_MX7
 	bool "Freescale MX7"
@@ -677,6 +640,7 @@ config ARCH_MX7
 	select SYS_FSL_SEC_LE
 	select BOARD_EARLY_INIT_F
 	select ARCH_MISC_INIT
+	imply MXC_GPIO
 
 config ARCH_MX6
 	bool "Freescale MX6"
@@ -685,6 +649,7 @@ config ARCH_MX6
 	select SYS_FSL_SEC_COMPAT_4
 	select SYS_FSL_SEC_LE
 	select SYS_THUMB_BUILD if SPL
+	imply MXC_GPIO
 
 if ARCH_MX6
 config SPL_LDSCRIPT
@@ -695,6 +660,7 @@ config ARCH_MX5
 	bool "Freescale MX5"
 	select CPU_V7
 	select BOARD_EARLY_INIT_F
+	imply MXC_GPIO
 
 config ARCH_QEMU
 	bool "QEMU Virtual Platform"
@@ -781,12 +747,6 @@ config ARCH_SUNXI
 	imply SPL_SERIAL_SUPPORT
 	imply USB_GADGET
 
-config TARGET_TS4600
-	bool "Support TS4600"
-	select CPU_ARM926EJS
-	select SUPPORT_SPL
-	select PL011_SERIAL
-
 config ARCH_VF610
 	bool "Freescale Vybrid"
 	select CPU_V7
@@ -803,18 +763,16 @@ config ARCH_ZYNQ
 	select SPL_BOARD_INIT if SPL
 	select SPL_OF_CONTROL if SPL
 	select DM
-	select DM_ETH
-	select DM_GPIO
+	select DM_ETH if NET
 	select SPL_DM if SPL
-	select DM_MMC
+	select DM_MMC if MMC
 	select DM_SPI
 	select DM_SERIAL
 	select DM_SPI_FLASH
 	select SPL_SEPARATE_BSS if SPL
 	select DM_USB if USB
-	select BLK
 	select CLK
-	select SPL_CLK
+	select SPL_CLK if SPL
 	select CLK_ZYNQ
 	imply CMD_CLK
 	imply FAT_WRITE
@@ -1256,13 +1214,17 @@ source "arch/arm/cpu/armv7/ls102xa/Kconfig"
 
 source "arch/arm/mach-imx/mx2/Kconfig"
 
-source "arch/arm/mach-imx/mx7ulp/Kconfig"
-
-source "arch/arm/mach-imx/mx7/Kconfig"
+source "arch/arm/mach-imx/mx5/Kconfig"
 
 source "arch/arm/mach-imx/mx6/Kconfig"
 
-source "arch/arm/mach-imx/mx5/Kconfig"
+source "arch/arm/mach-imx/mx7/Kconfig"
+
+source "arch/arm/mach-imx/mx7ulp/Kconfig"
+
+source "arch/arm/mach-imx/mx8m/Kconfig"
+
+source "arch/arm/mach-imx/mxs/Kconfig"
 
 source "arch/arm/mach-omap2/Kconfig"
 
@@ -1306,7 +1268,6 @@ source "arch/arm/cpu/armv8/Kconfig"
 
 source "arch/arm/mach-imx/Kconfig"
 
-source "board/aries/m28evk/Kconfig"
 source "board/bosch/shc/Kconfig"
 source "board/CarMediaLab/flea3/Kconfig"
 source "board/Marvell/aspenite/Kconfig"
@@ -1314,7 +1275,6 @@ source "board/Marvell/gplugd/Kconfig"
 source "board/armadeus/apf27/Kconfig"
 source "board/armltd/vexpress/Kconfig"
 source "board/armltd/vexpress64/Kconfig"
-source "board/bluegiga/apx4devkit/Kconfig"
 source "board/broadcom/bcm23550_w1d/Kconfig"
 source "board/broadcom/bcm28155_ap/Kconfig"
 source "board/broadcom/bcmcygnus/Kconfig"
@@ -1322,7 +1282,6 @@ source "board/broadcom/bcmnsp/Kconfig"
 source "board/broadcom/bcmns2/Kconfig"
 source "board/cavium/thunderx/Kconfig"
 source "board/cirrus/edb93xx/Kconfig"
-source "board/creative/xfi3/Kconfig"
 source "board/eets/pdu001/Kconfig"
 source "board/freescale/ls2080a/Kconfig"
 source "board/freescale/ls2080aqds/Kconfig"
@@ -1338,8 +1297,6 @@ source "board/freescale/ls1046ardb/Kconfig"
 source "board/freescale/ls1012aqds/Kconfig"
 source "board/freescale/ls1012ardb/Kconfig"
 source "board/freescale/ls1012afrdm/Kconfig"
-source "board/freescale/mx23evk/Kconfig"
-source "board/freescale/mx28evk/Kconfig"
 source "board/freescale/mx31ads/Kconfig"
 source "board/freescale/mx31pdk/Kconfig"
 source "board/freescale/mx35pdk/Kconfig"
@@ -1352,11 +1309,7 @@ source "board/hisilicon/hikey/Kconfig"
 source "board/hisilicon/poplar/Kconfig"
 source "board/imx31_phycore/Kconfig"
 source "board/isee/igep003x/Kconfig"
-source "board/olimex/mx23_olinuxino/Kconfig"
 source "board/phytec/pcm051/Kconfig"
-source "board/ppcag/bg0900/Kconfig"
-source "board/sandisk/sansa_fuze_plus/Kconfig"
-source "board/schulercontrol/sc_sps_1/Kconfig"
 source "board/silica/pengwyn/Kconfig"
 source "board/spear/spear300/Kconfig"
 source "board/spear/spear310/Kconfig"
@@ -1368,7 +1321,6 @@ source "board/tcl/sl50/Kconfig"
 source "board/birdland/bav335x/Kconfig"
 source "board/timll/devkit3250/Kconfig"
 source "board/toradex/colibri_pxa270/Kconfig"
-source "board/technologic/ts4600/Kconfig"
 source "board/vscom/baltos/Kconfig"
 source "board/woodburn/Kconfig"
 source "board/work-microwave/work_92105/Kconfig"
@@ -1379,7 +1331,7 @@ source "arch/arm/Kconfig.debug"
 endmenu
 
 config SPL_LDSCRIPT
-        default "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" if TARGET_APX4DEVKIT || TARGET_BG0900 || TARGET_M28EVK || TARGET_MX23_OLINUXINO || TARGET_MX23EVK || TARGET_MX28EVK || TARGET_SANSA_FUZE_PLUS || TARGET_SC_SPS_1 || TARGET_TS4600 || TARGET_XFI3
+        default "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" if ARCH_MX23 || ARCH_MX28
         default "arch/arm/cpu/arm1136/u-boot-spl.lds" if CPU_ARM1136
 	default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64
 

arch/arm/Makefile

@@ -95,11 +95,11 @@ libs-y += arch/arm/cpu/
 libs-y += arch/arm/lib/
 
 ifeq ($(CONFIG_SPL_BUILD),y)
-ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35))
+ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 mx8m))
 libs-y += arch/arm/mach-imx/
 endif
 else
-ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs vf610))
+ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs mx8m vf610))
 libs-y += arch/arm/mach-imx/
 endif
 endif

arch/arm/cpu/arm1136/mx35/generic.c

@@ -524,24 +524,3 @@ u32 spl_boot_device(void)
 
 	return BOOT_DEVICE_NONE;
 }
-
-#ifdef CONFIG_SPL_BUILD
-u32 spl_boot_mode(const u32 boot_device)
-{
-	switch (spl_boot_device()) {
-	case BOOT_DEVICE_MMC1:
-#ifdef CONFIG_SPL_FAT_SUPPORT
-		return MMCSD_MODE_FS;
-#else
-		return MMCSD_MODE_RAW;
-#endif
-		break;
-	case BOOT_DEVICE_NAND:
-		return 0;
-		break;
-	default:
-		puts("spl: ERROR:  unsupported device\n");
-		hang();
-	}
-}
-#endif

arch/arm/cpu/armv7/ls102xa/spl.c

@@ -14,20 +14,3 @@ u32 spl_boot_device(void)
 #endif
 	return BOOT_DEVICE_NAND;
 }
-
-u32 spl_boot_mode(const u32 boot_device)
-{
-	switch (spl_boot_device()) {
-	case BOOT_DEVICE_MMC1:
-#ifdef CONFIG_SPL_FAT_SUPPORT
-		return MMCSD_MODE_FS;
-#else
-		return MMCSD_MODE_RAW;
-#endif
-	case BOOT_DEVICE_NAND:
-		return 0;
-	default:
-		puts("spl: error: unsupported device\n");
-		hang();
-	}
-}

arch/arm/cpu/armv8/fsl-layerscape/Kconfig

@@ -3,6 +3,8 @@ config ARCH_LS1012A
 	select ARMV8_SET_SMPEN
 	select ARM_ERRATA_855873
 	select FSL_LSCH2
+	select SYS_FSL_SRDS_1
+	select SYS_HAS_SERDES
 	select SYS_FSL_DDR_BE
 	select SYS_FSL_MMDC
 	select SYS_FSL_ERRATUM_A010315
@@ -19,6 +21,8 @@ config ARCH_LS1043A
 	select ARMV8_SET_SMPEN
 	select ARM_ERRATA_855873
 	select FSL_LSCH2
+	select SYS_FSL_SRDS_1
+	select SYS_HAS_SERDES
 	select SYS_FSL_DDR
 	select SYS_FSL_DDR_BE
 	select SYS_FSL_DDR_VER_50
@@ -45,6 +49,8 @@ config ARCH_LS1046A
 	bool
 	select ARMV8_SET_SMPEN
 	select FSL_LSCH2
+	select SYS_FSL_SRDS_1
+	select SYS_HAS_SERDES
 	select SYS_FSL_DDR
 	select SYS_FSL_DDR_BE
 	select SYS_FSL_DDR_VER_50
@@ -72,6 +78,8 @@ config ARCH_LS1088A
 	select ARMV8_SET_SMPEN
 	select ARM_ERRATA_855873
 	select FSL_LSCH3
+	select SYS_FSL_SRDS_1
+	select SYS_HAS_SERDES
 	select SYS_FSL_DDR
 	select SYS_FSL_DDR_LE
 	select SYS_FSL_DDR_VER_50
@@ -105,6 +113,8 @@ config ARCH_LS2080A
 	select ARM_ERRATA_829520
 	select ARM_ERRATA_833471
 	select FSL_LSCH3
+	select SYS_FSL_SRDS_1
+	select SYS_HAS_SERDES
 	select SYS_FSL_DDR
 	select SYS_FSL_DDR_LE
 	select SYS_FSL_DDR_VER_50
@@ -142,13 +152,9 @@ config FSL_LSCH2
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_COMPAT_5
 	select SYS_FSL_SEC_BE
-	select SYS_FSL_SRDS_1
-	select SYS_HAS_SERDES
 
 config FSL_LSCH3
 	bool
-	select SYS_FSL_SRDS_1
-	select SYS_HAS_SERDES
 
 config FSL_MC_ENET
 	bool "Management Complex network"

arch/arm/cpu/armv8/fsl-layerscape/spl.c

@@ -26,23 +26,6 @@ u32 spl_boot_device(void)
 	return 0;
 }
 
-u32 spl_boot_mode(const u32 boot_device)
-{
-	switch (spl_boot_device()) {
-	case BOOT_DEVICE_MMC1:
-#ifdef CONFIG_SPL_FAT_SUPPORT
-		return MMCSD_MODE_FS;
-#else
-		return MMCSD_MODE_RAW;
-#endif
-	case BOOT_DEVICE_NAND:
-		return 0;
-	default:
-		puts("spl: error: unsupported device\n");
-		hang();
-	}
-}
-
 #ifdef CONFIG_SPL_BUILD
 
 void spl_board_init(void)

arch/arm/cpu/armv8/zynqmp/Kconfig

@@ -68,6 +68,12 @@ config PMUFW_INIT_FILE
 config ZYNQMP_USB
 	bool "Configure ZynqMP USB"
 
+config ZYNQMP_NO_DDR
+	bool "Disable DDR MMU mapping"
+	help
+	  This option configures MMU with no DDR to avoid speculative
+	  access to DDR memory where DDR is not present.
+
 config SYS_MALLOC_F_LEN
 	default 0x600
 
@@ -107,7 +113,7 @@ config SPL_ZYNQMP_ALT_BOOTMODE
 choice
 	prompt "Boot mode"
 	depends on SPL_ZYNQMP_ALT_BOOTMODE_ENABLED
-	default JTAG
+	default JTAG_MODE
 
 config JTAG_MODE
 	bool "JTAG_MODE"

arch/arm/cpu/armv8/zynqmp/Makefile

@@ -9,3 +9,4 @@ obj-y	+= clk.o
 obj-y	+= cpu.o
 obj-$(CONFIG_MP)	+= mp.o
 obj-$(CONFIG_SPL_BUILD) += spl.o handoff.o
+obj-$(CONFIG_ZYNQMP_PSU_INIT_ENABLED)	+= psu_spl_init.o

arch/arm/cpu/armv8/zynqmp/cpu.c

@@ -17,20 +17,24 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 static struct mm_region zynqmp_mem_map[] = {
+#if !defined(CONFIG_ZYNQMP_NO_DDR)
 	{
 		.virt = 0x0UL,
 		.phys = 0x0UL,
 		.size = 0x80000000UL,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 			 PTE_BLOCK_INNER_SHARE
-	}, {
+	},
+#endif
+	{
 		.virt = 0x80000000UL,
 		.phys = 0x80000000UL,
 		.size = 0x70000000UL,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 			 PTE_BLOCK_NON_SHARE |
 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	}, {
+	},
+	{
 		.virt = 0xf8000000UL,
 		.phys = 0xf8000000UL,
 		.size = 0x07e00000UL,
@@ -48,20 +52,24 @@ static struct mm_region zynqmp_mem_map[] = {
 #endif
 		.virt = 0x400000000UL,
 		.phys = 0x400000000UL,
-		.size = 0x200000000UL,
+		.size = 0x400000000UL,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 			 PTE_BLOCK_NON_SHARE |
 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	}, {
-		.virt = 0x600000000UL,
-		.phys = 0x600000000UL,
+	},
+#if !defined(CONFIG_ZYNQMP_NO_DDR)
+	{
+		.virt = 0x800000000UL,
+		.phys = 0x800000000UL,
 		.size = 0x800000000UL,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 			 PTE_BLOCK_INNER_SHARE
-	}, {
-		.virt = 0xe00000000UL,
-		.phys = 0xe00000000UL,
-		.size = 0xf200000000UL,
+	},
+#endif
+	{
+		.virt = 0x1000000000UL,
+		.phys = 0x1000000000UL,
+		.size = 0xf000000000UL,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 			 PTE_BLOCK_NON_SHARE |
 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN

arch/arm/cpu/armv8/zynqmp/psu_spl_init.c

@@ -0,0 +1,80 @@
+/*
+ * Copyright 2018 Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/psu_init_gpl.h>
+
+#define PSU_MASK_POLL_TIME 1100000
+
+int __maybe_unused mask_pollonvalue(unsigned long add, u32 mask, u32 value)
+{
+	int i = 0;
+
+	while ((__raw_readl(add) & mask) != value) {
+		if (i == PSU_MASK_POLL_TIME)
+			return 0;
+		i++;
+	}
+	return 1;
+}
+
+__weak int mask_poll(u32 add, u32 mask)
+{
+	int i = 0;
+	unsigned long addr = add;
+
+	while (!(__raw_readl(addr) & mask)) {
+		if (i == PSU_MASK_POLL_TIME)
+			return 0;
+		i++;
+	}
+	return 1;
+}
+
+__weak u32 mask_read(u32 add, u32 mask)
+{
+	unsigned long addr = add;
+
+	return __raw_readl(addr) & mask;
+}
+
+__weak void mask_delay(u32 delay)
+{
+	udelay(delay);
+}
+
+__weak void psu_mask_write(unsigned long offset, unsigned long mask,
+			   unsigned long val)
+{
+	unsigned long regval = 0;
+
+	regval = readl(offset);
+	regval &= ~(mask);
+	regval |= (val & mask);
+	writel(regval, offset);
+}
+
+__weak void prog_reg(unsigned long addr, unsigned long mask,
+		     unsigned long shift, unsigned long value)
+{
+	int rdata = 0;
+
+	rdata = readl(addr);
+	rdata = rdata & (~mask);
+	rdata = rdata | (value << shift);
+	writel(rdata, addr);
+}
+
+__weak int psu_init(void)
+{
+	/*
+	 * This function is overridden by the one in
+	 * board/xilinx/zynqmp/(platform)/psu_init_gpl.c, if it exists.
+	 */
+	return -1;
+}

arch/arm/cpu/armv8/zynqmp/spl.c

@@ -115,28 +115,6 @@ u32 spl_boot_device(void)
 	return 0;
 }
 
-u32 spl_boot_mode(const u32 boot_device)
-{
-	switch (boot_device) {
-	case BOOT_DEVICE_RAM:
-		return 0;
-	case BOOT_DEVICE_MMC1:
-	case BOOT_DEVICE_MMC2:
-		return MMCSD_MODE_FS;
-	default:
-		puts("spl: error: unsupported device\n");
-		hang();
-	}
-}
-
-__weak void psu_init(void)
-{
-	 /*
-	  * This function is overridden by the one in
-	  * board/xilinx/zynqmp/(platform)/psu_init_gpl.c, if it exists.
-	  */
-}
-
 #ifdef CONFIG_SPL_OS_BOOT
 int spl_start_uboot(void)
 {

arch/arm/dts/Makefile

@@ -147,6 +147,8 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
 	zynq-zybo.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP) += \
 	zynqmp-ep108.dtb			\
+	zynqmp-mini-emmc.dtb			\
+	zynqmp-mini-nand.dtb			\
 	zynqmp-zcu102-revA.dtb			\
 	zynqmp-zcu102-revB.dtb			\
 	zynqmp-zcu102-rev1.0.dtb		\
@@ -383,9 +385,11 @@ dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \
 	imx6sl-evk.dtb \
 	imx6sll-evk.dtb \
 	imx6dl-icore.dtb \
+	imx6dl-icore-mipi.dtb \
 	imx6dl-icore-rqs.dtb \
 	imx6q-cm-fx6.dtb \
 	imx6q-icore.dtb \
+	imx6q-icore-mipi.dtb \
 	imx6q-icore-rqs.dtb \
 	imx6q-logicpd.dtb \
 	imx6sx-sabreauto.dtb \

arch/arm/dts/fsl-imx8-ca53.dtsi

@@ -0,0 +1,92 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/{
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		idle-states {
+			entry-method = "psci";
+
+			CPU_SLEEP: cpu-sleep {
+				compatible = "arm,idle-state";
+				local-timer-stop;
+				arm,psci-suspend-param = <0x0000000>;
+				entry-latency-us = <700>;
+				exit-latency-us = <250>;
+				min-residency-us = <1000>;
+			};
+
+			CLUSTER_SLEEP: cluster-sleep {
+				compatible = "arm,idle-state";
+				local-timer-stop;
+				arm,psci-suspend-param = <0x1000000>;
+				entry-latency-us = <1000>;
+				exit-latency-us = <700>;
+				min-residency-us = <2700>;
+				wakeup-latency-us = <1500>;
+			};
+		};
+
+		/* We have 1 clusters having 4 Cortex-A53 cores */
+		A53_0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x0 0x0>;
+			enable-method = "psci";
+			next-level-cache = <&A53_L2>;
+			cpu-idle-states = <&CPU_SLEEP>;
+		};
+
+		A53_1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x0 0x1>;
+			enable-method = "psci";
+			next-level-cache = <&A53_L2>;
+			cpu-idle-states = <&CPU_SLEEP>;
+		};
+
+		A53_2: cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x0 0x2>;
+			enable-method = "psci";
+			next-level-cache = <&A53_L2>;
+			cpu-idle-states = <&CPU_SLEEP>;
+		};
+
+		A53_3: cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x0 0x3>;
+			enable-method = "psci";
+			next-level-cache = <&A53_L2>;
+			cpu-idle-states = <&CPU_SLEEP>;
+		};
+
+		A53_L2: l2-cache0 {
+			compatible = "cache";
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+		cpu_suspend   = <0xc4000001>;
+		cpu_off	      = <0xc4000002>;
+		cpu_on	      = <0xc4000003>;
+	};
+};

arch/arm/dts/fsl-imx8mq.dtsi

@@ -0,0 +1,429 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "fsl-imx8-ca53.dtsi"
+#include <dt-bindings/clock/imx8mq-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/pins-imx8mq.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+	compatible = "fsl,imx8mq";
+	interrupt-parent = <&gpc>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	aliases {
+		ethernet0 = &fec1;
+		mmc0 = &usdhc1;
+		mmc1 = &usdhc2;
+		gpio0 = &gpio1;
+		gpio1 = &gpio2;
+		gpio2 = &gpio3;
+		gpio3 = &gpio4;
+		gpio4 = &gpio5;
+		i2c0 = &i2c1;
+		i2c1 = &i2c2;
+		i2c2 = &i2c3;
+		i2c3 = &i2c4;
+	};
+
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0x00000000 0x40000000 0 0xc0000000>;
+	};
+
+	gic: interrupt-controller@38800000 {
+		compatible = "arm,gic-v3";
+		reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */
+		      <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&gic>;
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) |
+			     IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) |
+			     IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) |
+			     IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) |
+			     IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
+		clock-frequency = <8333333>;
+		interrupt-parent = <&gic>;
+	};
+
+	power: power-controller {
+		compatible = "fsl,imx8mq-pm-domain";
+		num-domains = <11>;
+		#power-domain-cells = <1>;
+	};
+
+	pwm2: pwm@30670000 {
+		compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
+		reg = <0x0 0x30670000 0x0 0x10000>;
+		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>,
+			 <&clk IMX8MQ_CLK_PWM2_ROOT>;
+		clock-names = "ipg", "per";
+		#pwm-cells = <2>;
+		status = "disabled";
+	};
+
+	gpio1: gpio@30200000 {
+		compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
+		reg = <0x0 0x30200000 0x0 0x10000>;
+		interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpio2: gpio@30210000 {
+		compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
+		reg = <0x0 0x30210000 0x0 0x10000>;
+		interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpio3: gpio@30220000 {
+		compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
+		reg = <0x0 0x30220000 0x0 0x10000>;
+		interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpio4: gpio@30230000 {
+		compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
+		reg = <0x0 0x30230000 0x0 0x10000>;
+		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpio5: gpio@30240000 {
+		compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
+		reg = <0x0 0x30240000 0x0 0x10000>;
+		interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	tmu: tmu@30260000 {
+		compatible = "fsl,imx8mq-tmu";
+		reg = <0x0 0x30260000 0x0 0x10000>;
+		interrupt = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+		little-endian;
+		u-boot,dm-pre-reloc;
+		fsl,tmu-range = <0xa0000 0x90026 0x8004a 0x1006a>;
+		fsl,tmu-calibration = <0x00000000 0x00000020
+				       0x00000001 0x00000028
+				       0x00000002 0x00000030
+				       0x00000003 0x00000038
+				       0x00000004 0x00000040
+				       0x00000005 0x00000048
+				       0x00000006 0x00000050
+				       0x00000007 0x00000058
+				       0x00000008 0x00000060
+				       0x00000009 0x00000068
+				       0x0000000a 0x00000070
+				       0x0000000b 0x00000077
+
+				       0x00010000 0x00000057
+				       0x00010001 0x0000005b
+				       0x00010002 0x0000005f
+				       0x00010003 0x00000063
+				       0x00010004 0x00000067
+				       0x00010005 0x0000006b
+				       0x00010006 0x0000006f
+				       0x00010007 0x00000073
+				       0x00010008 0x00000077
+				       0x00010009 0x0000007b
+				       0x0001000a 0x0000007f
+
+				       0x00020000 0x00000002
+				       0x00020001 0x0000000e
+				       0x00020002 0x0000001a
+				       0x00020003 0x00000026
+				       0x00020004 0x00000032
+				       0x00020005 0x0000003e
+				       0x00020006 0x0000004a
+				       0x00020007 0x00000056
+				       0x00020008 0x00000062
+
+				       0x00030000 0x00000000
+				       0x00030001 0x00000008
+				       0x00030002 0x00000010
+				       0x00030003 0x00000018
+				       0x00030004 0x00000020
+				       0x00030005 0x00000028
+				       0x00030006 0x00000030
+				       0x00030007 0x00000038>;
+		#thermal-sensor-cells =  <0>;
+	};
+
+	thermal-zones {
+		/* cpu thermal */
+		cpu-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <2000>;
+			thermal-sensors = <&tmu>;
+			trips {
+				cpu_alert0: trip0 {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+				cpu_crit0: trip1 {
+					temperature = <125000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu_alert0>;
+					cooling-device =
+					<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+	};
+
+	lcdif: lcdif@30320000 {
+		compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif";
+		reg = <0x0 0x30320000 0x0 0x10000>;
+		clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL_DIV>,
+			 <&clk IMX8MQ_CLK_DUMMY>,
+			 <&clk IMX8MQ_CLK_DUMMY>;
+		clock-names = "pix", "axi", "disp_axi";
+		assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL_SRC>;
+		assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>;
+		assigned-clock-rate = <594000000>;
+		interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+		status = "disabled";
+	};
+
+	iomuxc: iomuxc@30330000 {
+		compatible = "fsl,imx8mq-iomuxc";
+		reg = <0x0 0x30330000 0x0 0x10000>;
+	};
+
+	gpr: iomuxc-gpr@30340000 {
+		compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx7d-iomuxc-gpr", "syscon";
+		reg = <0x0 0x30340000 0x0 0x10000>;
+	};
+
+	ocotp: ocotp-ctrl@30350000 {
+		compatible = "fsl,imx8mq-ocotp", "fsl,imx7d-ocotp", "syscon";
+		reg = <0x0 0x30350000 0x0 0x10000>;
+	};
+
+	anatop: anatop@30360000 {
+		compatible = "fsl,imx8mq-anatop", "fsl,imx6q-anatop",
+			"syscon", "simple-bus";
+		reg = <0x0 0x30360000 0x0 0x10000>;
+		interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	clk: ccm@30380000 {
+		compatible = "fsl,imx8mq-ccm";
+		reg = <0x0 0x30380000 0x0 0x10000>;
+		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+		#clock-cells = <1>;
+	};
+
+	gpc: gpc@303a0000 {
+		compatible = "fsl,imx8mq-gpc", "fsl,imx7d-gpc", "syscon";
+		reg = <0x0 0x303a0000 0x0 0x10000>;
+		interrupt-controller;
+		interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+		#interrupt-cells = <3>;
+		interrupt-parent = <&gic>;
+	};
+
+	usdhc1: usdhc@30b40000 {
+		compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc";
+		reg = <0x0 0x30b40000 0x0 0x10000>;
+		interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8MQ_CLK_DUMMY>,
+			<&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>,
+			<&clk IMX8MQ_CLK_USDHC1_ROOT>;
+		clock-names = "ipg", "ahb", "per";
+		assigned-clocks = <&clk IMX8MQ_CLK_USDHC1_DIV>;
+		assigned-clock-rates = <400000000>;
+		fsl,tuning-start-tap = <20>;
+		fsl,tuning-step= <2>;
+		bus-width = <4>;
+		status = "disabled";
+	};
+
+	usdhc2: usdhc@30b50000 {
+		compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc";
+		reg = <0x0 0x30b50000 0x0 0x10000>;
+		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8MQ_CLK_DUMMY>,
+			<&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>,
+			<&clk IMX8MQ_CLK_USDHC2_ROOT>;
+		clock-names = "ipg", "ahb", "per";
+		fsl,tuning-start-tap = <20>;
+		fsl,tuning-step= <2>;
+		bus-width = <4>;
+		status = "disabled";
+	};
+
+	fec1: ethernet@30be0000 {
+		compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
+		reg = <0x0 0x30be0000 0x0 0x10000>;
+		interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
+			<&clk IMX8MQ_CLK_ENET1_ROOT>,
+			<&clk IMX8MQ_CLK_ENET_TIMER_DIV>,
+			<&clk IMX8MQ_CLK_ENET_REF_DIV>,
+			<&clk IMX8MQ_CLK_ENET_PHY_REF_DIV>;
+		clock-names = "ipg", "ahb", "ptp",
+			"enet_clk_ref", "enet_out";
+		assigned-clocks = <&clk IMX8MQ_CLK_ENET_AXI_SRC>,
+				  <&clk IMX8MQ_CLK_ENET_TIMER_SRC>,
+				  <&clk IMX8MQ_CLK_ENET_REF_SRC>,
+				  <&clk IMX8MQ_CLK_ENET_TIMER_DIV>;
+		assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
+					 <&clk IMX8MQ_SYS2_PLL_100M>,
+					 <&clk IMX8MQ_SYS2_PLL_125M>;
+		assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
+		stop-mode = <&gpr 0x10 3>;
+		fsl,num-tx-queues=<3>;
+		fsl,num-rx-queues=<3>;
+		fsl,wakeup_irq = <2>;
+		status = "disabled";
+	};
+
+	imx_ion {
+		compatible = "fsl,mxc-ion";
+		fsl,heap-id = <0>;
+	};
+
+	i2c1: i2c@30a20000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,imx21-i2c";
+		reg = <0x0 0x30a20000 0x0 0x10000>;
+		interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>;
+		status = "disabled";
+	};
+
+	i2c2: i2c@30a30000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,imx21-i2c";
+		reg = <0x0 0x30a30000 0x0 0x10000>;
+		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>;
+		status = "disabled";
+	};
+
+	i2c3: i2c@30a40000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,imx21-i2c";
+		reg = <0x0 0x30a40000 0x0 0x10000>;
+		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>;
+		status = "disabled";
+	};
+
+	i2c4: i2c@30a50000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,imx21-i2c";
+		reg = <0x0 0x30a50000 0x0 0x10000>;
+		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>;
+		status = "disabled";
+	};
+
+	wdog1: wdog@30280000 {
+			compatible = "fsl,imx21-wdt";
+			reg = <0 0x30280000 0 0x10000>;
+			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>;
+			status = "disabled";
+	};
+
+	wdog2: wdog@30290000 {
+			compatible = "fsl,imx21-wdt";
+			reg = <0 0x30290000 0 0x10000>;
+			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>;
+			status = "disabled";
+	};
+
+	wdog3: wdog@302a0000 {
+			compatible = "fsl,imx21-wdt";
+			reg = <0 0x302a0000 0 0x10000>;
+			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>;
+			status = "disabled";
+	};
+
+	dma_cap: dma_cap {
+		compatible = "dma-capability";
+		only-dma-mask32 = <1>;
+	};
+
+	qspi: qspi@30bb0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,imx7d-qspi";
+		reg = <0 0x30bb0000 0 0x10000>, <0 0x08000000 0 0x10000000>;
+		reg-names = "QuadSPI", "QuadSPI-memory";
+		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>,
+		<&clk IMX8MQ_CLK_QSPI_ROOT>;
+		clock-names = "qspi_en", "qspi";
+		status = "disabled";
+	};
+};
+
+&A53_0 {
+	#cooling-cells = <2>;
+};

arch/arm/dts/imx6dl-icore-mipi.dts

@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2017 Engicam S.r.l.
+ * Copyright (C) 2017 Amarula Solutions B.V.
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+/dts-v1/;
+
+#include "imx6dl.dtsi"
+#include "imx6qdl-icore.dtsi"
+
+/ {
+	model = "Engicam i.CoreM6 DualLite/Solo MIPI Starter Kit";
+	compatible = "engicam,imx6-icore", "fsl,imx6dl";
+};
+
+&usdhc3 {
+	u-boot,dm-spl;
+	status = "okay";
+};

arch/arm/dts/imx6q-icore-mipi.dts

@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2017 Engicam S.r.l.
+ * Copyright (C) 2017 Amarula Solutions B.V.
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+/dts-v1/;
+
+#include "imx6q.dtsi"
+#include "imx6qdl-icore.dtsi"
+
+/ {
+	model = "Engicam i.CoreM6 Quad/Dual MIPI Starter Kit";
+	compatible = "engicam,imx6-icore", "fsl,imx6q";
+};
+
+&usdhc3 {
+	u-boot,dm-spl;
+	status = "okay";
+};

arch/arm/dts/imx6qdl-icore.dtsi

@@ -44,6 +44,10 @@
 #include <dt-bindings/input/input.h>
 
 / {
+	aliases {
+		mmc1 = &usdhc3;
+	};
+
 	memory {
 		reg = <0x10000000 0x80000000>;
 	};
@@ -126,6 +130,14 @@
 	status = "okay";
 };
 
+&usdhc3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	no-1-8-v;
+	non-removable;
+	status = "disabled";
+};
+
 &iomuxc {
 	pinctrl_enet: enetgrp {
 		fsl,pins = <
@@ -219,4 +231,20 @@
 			MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17070
 		>;
 	};
+
+	pinctrl_usdhc3: usdhc3grp {
+		u-boot,dm-spl;
+		fsl,pins = <
+			MX6QDL_PAD_SD3_CMD__SD3_CMD    0x17059
+			MX6QDL_PAD_SD3_CLK__SD3_CLK    0x10059
+			MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+			MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+			MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+			MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+			MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
+			MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
+			MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
+			MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
+		>;
+	};
 };

arch/arm/dts/imx6ull-14x14-evk.dts

@@ -8,7 +8,6 @@
 
 /dts-v1/;
 
-#include <dt-bindings/input/input.h>
 #include "imx6ull.dtsi"
 
 / {

arch/arm/dts/imx6ull.dtsi

@@ -8,6 +8,7 @@
 
 #include <dt-bindings/clock/imx6ul-clock.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include "imx6ull-pinfunc.h"
 #include "imx6ull-pinfunc-snvs.h"

arch/arm/dts/imx7d-sdb.dts

@@ -134,6 +134,28 @@
 			>;
 		};
 
+		pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
+			fsl,pins = <
+				MX7D_PAD_SD1_CMD__SD1_CMD		0x5a
+				MX7D_PAD_SD1_CLK__SD1_CLK		0x1a
+				MX7D_PAD_SD1_DATA0__SD1_DATA0		0x5a
+				MX7D_PAD_SD1_DATA1__SD1_DATA1		0x5a
+				MX7D_PAD_SD1_DATA2__SD1_DATA2		0x5a
+				MX7D_PAD_SD1_DATA3__SD1_DATA3		0x5a
+			>;
+		};
+
+		pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
+			fsl,pins = <
+				MX7D_PAD_SD1_CMD__SD1_CMD		0x5b
+				MX7D_PAD_SD1_CLK__SD1_CLK		0x1b
+				MX7D_PAD_SD1_DATA0__SD1_DATA0		0x5b
+				MX7D_PAD_SD1_DATA1__SD1_DATA1		0x5b
+				MX7D_PAD_SD1_DATA2__SD1_DATA2		0x5b
+				MX7D_PAD_SD1_DATA3__SD1_DATA3		0x5b
+			>;
+		};
+
 		pinctrl_usdhc2: usdhc2grp {
 			fsl,pins = <
 				MX7D_PAD_SD2_CMD__SD2_CMD       0x59
@@ -147,6 +169,28 @@
 			>;
 		};
 
+		pinctrl_usdhc2_100mhz: usdhc2grp_100mhz {
+			fsl,pins = <
+				MX7D_PAD_SD2_CMD__SD2_CMD		0x5a
+				MX7D_PAD_SD2_CLK__SD2_CLK		0x1a
+				MX7D_PAD_SD2_DATA0__SD2_DATA0		0x5a
+				MX7D_PAD_SD2_DATA1__SD2_DATA1		0x5a
+				MX7D_PAD_SD2_DATA2__SD2_DATA2		0x5a
+				MX7D_PAD_SD2_DATA3__SD2_DATA3		0x5a
+			>;
+		};
+
+		pinctrl_usdhc2_200mhz: usdhc2grp_200mhz {
+			fsl,pins = <
+				MX7D_PAD_SD2_CMD__SD2_CMD		0x5b
+				MX7D_PAD_SD2_CLK__SD2_CLK		0x1b
+				MX7D_PAD_SD2_DATA0__SD2_DATA0		0x5b
+				MX7D_PAD_SD2_DATA1__SD2_DATA1		0x5b
+				MX7D_PAD_SD2_DATA2__SD2_DATA2		0x5b
+				MX7D_PAD_SD2_DATA3__SD2_DATA3		0x5b
+			>;
+		};
+
 		pinctrl_usdhc3: usdhc3grp {
 			fsl,pins = <
 				MX7D_PAD_SD3_CMD__SD3_CMD		0x59
@@ -162,6 +206,38 @@
 				MX7D_PAD_SD3_STROBE__SD3_STROBE         0x19
 			>;
 		};
+
+		pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
+			fsl,pins = <
+				MX7D_PAD_SD3_CMD__SD3_CMD		0x5a
+				MX7D_PAD_SD3_CLK__SD3_CLK		0x1a
+				MX7D_PAD_SD3_DATA0__SD3_DATA0		0x5a
+				MX7D_PAD_SD3_DATA1__SD3_DATA1		0x5a
+				MX7D_PAD_SD3_DATA2__SD3_DATA2		0x5a
+				MX7D_PAD_SD3_DATA3__SD3_DATA3		0x5a
+				MX7D_PAD_SD3_DATA4__SD3_DATA4		0x5a
+				MX7D_PAD_SD3_DATA5__SD3_DATA5		0x5a
+				MX7D_PAD_SD3_DATA6__SD3_DATA6		0x5a
+				MX7D_PAD_SD3_DATA7__SD3_DATA7		0x5a
+				MX7D_PAD_SD3_STROBE__SD3_STROBE		0x1a
+			>;
+		};
+
+		pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
+			fsl,pins = <
+				MX7D_PAD_SD3_CMD__SD3_CMD		0x5b
+				MX7D_PAD_SD3_CLK__SD3_CLK		0x1b
+				MX7D_PAD_SD3_DATA0__SD3_DATA0		0x5b
+				MX7D_PAD_SD3_DATA1__SD3_DATA1		0x5b
+				MX7D_PAD_SD3_DATA2__SD3_DATA2		0x5b
+				MX7D_PAD_SD3_DATA3__SD3_DATA3		0x5b
+				MX7D_PAD_SD3_DATA4__SD3_DATA4		0x5b
+				MX7D_PAD_SD3_DATA5__SD3_DATA5		0x5b
+				MX7D_PAD_SD3_DATA6__SD3_DATA6		0x5b
+				MX7D_PAD_SD3_DATA7__SD3_DATA7		0x5b
+				MX7D_PAD_SD3_STROBE__SD3_STROBE		0x1b
+			>;
+		};
 	};
 };
 
@@ -287,23 +363,35 @@
 &usdhc1 {
 	pinctrl-names = "default", "state_100mhz", "state_200mhz";
 	pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
 	cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
 	wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
 	vmmc-supply = <&reg_sd1_vmmc>;
+	fsl,tuning-start-tap = <20>;
+	fsl,tuning-step= <2>;
 	status = "okay";
 };
 
 &usdhc2 {
 	pinctrl-names = "default", "state_100mhz", "state_200mhz";
 	pinctrl-0 = <&pinctrl_usdhc2>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
 	non-removable;
+	fsl,tuning-start-tap = <20>;
+	fsl,tuning-step= <2>;
 	status = "okay";
 };
 
 &usdhc3 {
 	pinctrl-names = "default", "state_100mhz", "state_200mhz";
 	pinctrl-0 = <&pinctrl_usdhc3>;
+	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 	bus-width = <8>;
 	non-removable;
+	fsl,tuning-start-tap = <20>;
+	fsl,tuning-step= <2>;
 	status = "okay";
 };

arch/arm/dts/keystone-k2g-ice.dts

@@ -34,3 +34,51 @@
 &i2c1 {
 	status = "okay";
 };
+
+&qspi {
+	status = "okay";
+
+	flash0: m25p80@0 {
+		compatible = "s25fl256s1", "spi-flash";
+		reg = <0>;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <4>;
+		spi-max-frequency = <96000000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		cdns,read-delay = <5>;
+		cdns,tshsl-ns = <500>;
+		cdns,tsd2d-ns = <500>;
+		cdns,tchsh-ns = <119>;
+		cdns,tslch-ns = <119>;
+
+		partition@0 {
+			label = "QSPI.u-boot";
+			reg = <0x00000000 0x00100000>;
+		};
+		partition@1 {
+			label = "QSPI.u-boot-env";
+			reg = <0x00100000 0x00040000>;
+		};
+		partition@2 {
+			label = "QSPI.skern";
+			reg = <0x00140000 0x0040000>;
+		};
+		partition@3 {
+			label = "QSPI.pmmc-firmware";
+			reg = <0x00180000 0x0040000>;
+		};
+		partition@4 {
+			label = "QSPI.kernel";
+			reg = <0x001c0000 0x0800000>;
+		};
+		partition@5 {
+			label = "QSPI.u-boot-spl-os";
+			reg = <0x009c0000 0x0040000>;
+		};
+		partition@6 {
+			label = "QSPI.file-system";
+			reg = <0x00a00000 0x1600000>;
+		};
+	};
+};

arch/arm/dts/zynq-7000.dtsi

@@ -50,7 +50,8 @@
 		compatible = "arm,cortex-a9-pmu";
 		interrupts = <0 5 4>, <0 6 4>;
 		interrupt-parent = <&intc>;
-		reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
+		reg = <0xf8891000 0x1000>,
+		      <0xf8893000 0x1000>;
 	};
 
 	regulator_vccpint: fixedregulator {

arch/arm/dts/zynq-cc108.dts

@@ -100,6 +100,7 @@
 };
 
 &uart0 {
+	u-boot,dm-pre-reloc;
 	status = "okay";
 };
 

arch/arm/dts/zynq-topic-miami.dts

@@ -13,7 +13,6 @@
 	compatible = "topic,miami", "xlnx,zynq-7000";
 
 	aliases {
-		ethernet0 = &gem0;
 		serial0 = &uart0;
 		spi0 = &qspi;
 		i2c0 = &i2c0;

arch/arm/dts/zynq-zc770-xm011-x16.dts

@@ -0,0 +1 @@
+zynq-zc770-xm011.dts

arch/arm/dts/zynqmp-mini-emmc.dts

@@ -0,0 +1,76 @@
+/*
+ * dts file for Xilinx ZynqMP Mini Configuration
+ *
+ * (C) Copyright 2018, Xilinx, Inc.
+ *
+ * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+
+/ {
+	model = "ZynqMP MINI EMMC";
+	compatible = "xlnx,zynqmp";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	aliases {
+		serial0 = &dcc;
+		mmc0 = &sdhci0;
+		mmc1 = &sdhci1;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x20000000>;
+	};
+
+	dcc: dcc {
+		compatible = "arm,dcc";
+		status = "disabled";
+		u-boot,dm-pre-reloc;
+	};
+
+	amba: amba {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		sdhci0: sdhci@ff160000 {
+			u-boot,dm-pre-reloc;
+			compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
+			status = "disabled";
+			reg = <0x0 0xff160000 0x0 0x1000>;
+			clock-names = "clk_xin", "clk_ahb";
+			xlnx,device_id = <0>;
+		};
+
+		sdhci1: sdhci@ff170000 {
+			u-boot,dm-pre-reloc;
+			compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
+			status = "disabled";
+			reg = <0x0 0xff170000 0x0 0x1000>;
+			clock-names = "clk_xin", "clk_ahb";
+			xlnx,device_id = <1>;
+		};
+	};
+};
+
+&dcc {
+	status = "okay";
+};
+
+&sdhci0 {
+	status = "okay";
+};
+
+&sdhci1 {
+	status = "okay";
+};

arch/arm/dts/zynqmp-mini-nand.dts

@@ -0,0 +1,109 @@
+/*
+ * dts file for Xilinx ZynqMP Mini Configuration
+ *
+ * (C) Copyright 2018, Xilinx, Inc.
+ *
+ * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+
+/ {
+	model = "ZynqMP MINI NAND";
+	compatible = "xlnx,zynqmp";
+	#address-cells = <2>;
+	#size-cells = <1>;
+
+	aliases {
+		serial0 = &dcc;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x40000000>;
+	};
+
+	dcc: dcc {
+		compatible = "arm,dcc";
+		status = "disabled";
+		u-boot,dm-pre-reloc;
+	};
+
+	amba: amba {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <1>;
+		ranges;
+
+		nand0: nand@ff100000 {
+			compatible = "arasan,nfc-v3p10";
+			status = "okay";
+			reg = <0x0 0xff100000 0x1000>;
+			clock-names = "clk_sys", "clk_flash";
+			#address-cells = <2>;
+			#size-cells = <1>;
+			arasan,has-mdma;
+			num-cs = <2>;
+
+			partition@0 {	/* for testing purpose */
+				label = "nand-fsbl-uboot";
+				reg = <0x0 0x0 0x400000>;
+			};
+			partition@1 {	/* for testing purpose */
+				label = "nand-linux";
+				reg = <0x0 0x400000 0x1400000>;
+			};
+			partition@2 {	/* for testing purpose */
+				label = "nand-device-tree";
+				reg = <0x0 0x1800000 0x400000>;
+			};
+			partition@3 {	/* for testing purpose */
+				label = "nand-rootfs";
+				reg = <0x0 0x1C00000 0x1400000>;
+			};
+			partition@4 {	/* for testing purpose */
+				label = "nand-bitstream";
+				reg = <0x0 0x3000000 0x400000>;
+			};
+			partition@5 {	/* for testing purpose */
+				label = "nand-misc";
+				reg = <0x0 0x3400000 0xFCC00000>;
+			};
+			partition@6 {	/* for testing purpose */
+				label = "nand1-fsbl-uboot";
+				reg = <0x1 0x0 0x400000>;
+			};
+			partition@7 {	/* for testing purpose */
+				label = "nand1-linux";
+				reg = <0x1 0x400000 0x1400000>;
+			};
+			partition@8 {	/* for testing purpose */
+				label = "nand1-device-tree";
+				reg = <0x1 0x1800000 0x400000>;
+			};
+			partition@9 {	/* for testing purpose */
+				label = "nand1-rootfs";
+				reg = <0x1 0x1C00000 0x1400000>;
+			};
+			partition@10 {	/* for testing purpose */
+				label = "nand1-bitstream";
+				reg = <0x1 0x3000000 0x400000>;
+			};
+			partition@11 {	/* for testing purpose */
+				label = "nand1-misc";
+				reg = <0x1 0x3400000 0xFCC00000>;
+			};
+		};
+	};
+};
+
+&dcc {
+	status = "okay";
+};

arch/arm/include/asm/arch-imx/cpu.h

@@ -25,12 +25,14 @@
 #define MXC_CPU_MX6QP		0x69
 #define MXC_CPU_MX7S		0x71 /* dummy ID */
 #define MXC_CPU_MX7D		0x72
-#define MXC_CPU_MX7ULP		0x81 /* Temporally hard code */
+#define MXC_CPU_MX8MQ		0x82
+#define MXC_CPU_MX7ULP		0xE1 /* Temporally hard code */
 #define MXC_CPU_VF610		0xF6 /* dummy ID */
 
 #define MXC_SOC_MX6		0x60
 #define MXC_SOC_MX7		0x70
-#define MXC_SOC_MX7ULP		0x80 /* dummy */
+#define MXC_SOC_MX8M		0x80
+#define MXC_SOC_MX7ULP		0xE0 /* dummy */
 
 #define CHIP_REV_1_0            0x10
 #define CHIP_REV_1_1            0x11

arch/arm/include/asm/arch-mx25/iomux-mx25.h

@@ -36,59 +36,59 @@ enum {
 	MX25_PAD_A13__A13			= IOMUX_PAD(0x22C, 0x00c, 0x00, 0, 0, NO_PAD_CTRL),
 	MX25_PAD_A13__GPIO_4_1			= IOMUX_PAD(0x22C, 0x00c, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_A14__A14			= IOMUX_PAD(0x230, 0x010, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_A14__GPIO_2_0			= IOMUX_PAD(0x230, 0x010, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A14__A14			= IOMUX_PAD(0x230, 0x010, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A14__GPIO_2_0			= IOMUX_PAD(0x230, 0x010, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_A15__A15			= IOMUX_PAD(0x234, 0x014, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_A15__GPIO_2_1			= IOMUX_PAD(0x234, 0x014, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A15__A15			= IOMUX_PAD(0x234, 0x014, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A15__GPIO_2_1			= IOMUX_PAD(0x234, 0x014, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_A16__A16			= IOMUX_PAD(0x000, 0x018, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_A16__GPIO_2_2			= IOMUX_PAD(0x000, 0x018, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A16__A16			= IOMUX_PAD(0x000, 0x018, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A16__GPIO_2_2			= IOMUX_PAD(0x000, 0x018, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_A17__A17			= IOMUX_PAD(0x238, 0x01c, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_A17__GPIO_2_3			= IOMUX_PAD(0x238, 0x01c, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A17__A17			= IOMUX_PAD(0x238, 0x01c, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A17__GPIO_2_3			= IOMUX_PAD(0x238, 0x01c, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_A18__A18			= IOMUX_PAD(0x23c, 0x020, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_A18__GPIO_2_4			= IOMUX_PAD(0x23c, 0x020, 0x15, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_A18__FEC_COL			= IOMUX_PAD(0x23c, 0x020, 0x17, 0x504, 0, NO_PAD_CTRL),
+	MX25_PAD_A18__A18			= IOMUX_PAD(0x23c, 0x020, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A18__GPIO_2_4			= IOMUX_PAD(0x23c, 0x020, 0x05, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A18__FEC_COL			= IOMUX_PAD(0x23c, 0x020, 0x07, 0x504, 0, NO_PAD_CTRL),
 
-	MX25_PAD_A19__A19			= IOMUX_PAD(0x240, 0x024, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_A19__FEC_RX_ER			= IOMUX_PAD(0x240, 0x024, 0x17, 0x518, 0, NO_PAD_CTRL),
-	MX25_PAD_A19__GPIO_2_5			= IOMUX_PAD(0x240, 0x024, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A19__A19			= IOMUX_PAD(0x240, 0x024, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A19__FEC_RX_ER			= IOMUX_PAD(0x240, 0x024, 0x07, 0x518, 0, NO_PAD_CTRL),
+	MX25_PAD_A19__GPIO_2_5			= IOMUX_PAD(0x240, 0x024, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_A20__A20			= IOMUX_PAD(0x244, 0x028, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_A20__GPIO_2_6			= IOMUX_PAD(0x244, 0x028, 0x15, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_A20__FEC_RDATA2		= IOMUX_PAD(0x244, 0x028, 0x17, 0x50c, 0, NO_PAD_CTRL),
+	MX25_PAD_A20__A20			= IOMUX_PAD(0x244, 0x028, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A20__GPIO_2_6			= IOMUX_PAD(0x244, 0x028, 0x05, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A20__FEC_RDATA2		= IOMUX_PAD(0x244, 0x028, 0x07, 0x50c, 0, NO_PAD_CTRL),
 
-	MX25_PAD_A21__A21			= IOMUX_PAD(0x248, 0x02c, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_A21__GPIO_2_7			= IOMUX_PAD(0x248, 0x02c, 0x15, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_A21__FEC_RDATA3		= IOMUX_PAD(0x248, 0x02c, 0x17, 0x510, 0, NO_PAD_CTRL),
+	MX25_PAD_A21__A21			= IOMUX_PAD(0x248, 0x02c, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A21__GPIO_2_7			= IOMUX_PAD(0x248, 0x02c, 0x05, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A21__FEC_RDATA3		= IOMUX_PAD(0x248, 0x02c, 0x07, 0x510, 0, NO_PAD_CTRL),
 
-	MX25_PAD_A22__A22			= IOMUX_PAD(0x000, 0x030, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_A22__GPIO_2_8			= IOMUX_PAD(0x000, 0x030, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A22__A22			= IOMUX_PAD(0x000, 0x030, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A22__GPIO_2_8			= IOMUX_PAD(0x000, 0x030, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_A23__A23			= IOMUX_PAD(0x24c, 0x034, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_A23__GPIO_2_9			= IOMUX_PAD(0x24c, 0x034, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A23__A23			= IOMUX_PAD(0x24c, 0x034, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A23__GPIO_2_9			= IOMUX_PAD(0x24c, 0x034, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_A24__A24			= IOMUX_PAD(0x250, 0x038, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_A24__GPIO_2_10			= IOMUX_PAD(0x250, 0x038, 0x15, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_A24__FEC_RX_CLK		= IOMUX_PAD(0x250, 0x038, 0x17, 0x514, 0, NO_PAD_CTRL),
+	MX25_PAD_A24__A24			= IOMUX_PAD(0x250, 0x038, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A24__GPIO_2_10			= IOMUX_PAD(0x250, 0x038, 0x05, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A24__FEC_RX_CLK		= IOMUX_PAD(0x250, 0x038, 0x07, 0x514, 0, NO_PAD_CTRL),
 
-	MX25_PAD_A25__A25			= IOMUX_PAD(0x254, 0x03c, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_A25__GPIO_2_11			= IOMUX_PAD(0x254, 0x03c, 0x15, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_A25__FEC_CRS			= IOMUX_PAD(0x254, 0x03c, 0x17, 0x508, 0, NO_PAD_CTRL),
+	MX25_PAD_A25__A25			= IOMUX_PAD(0x254, 0x03c, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A25__GPIO_2_11			= IOMUX_PAD(0x254, 0x03c, 0x05, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A25__FEC_CRS			= IOMUX_PAD(0x254, 0x03c, 0x07, 0x508, 0, NO_PAD_CTRL),
 
-	MX25_PAD_EB0__EB0			= IOMUX_PAD(0x258, 0x040, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_EB0__AUD4_TXD			= IOMUX_PAD(0x258, 0x040, 0x14, 0x464, 0, NO_PAD_CTRL),
-	MX25_PAD_EB0__GPIO_2_12			= IOMUX_PAD(0x258, 0x040, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_EB0__EB0			= IOMUX_PAD(0x258, 0x040, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_EB0__AUD4_TXD			= IOMUX_PAD(0x258, 0x040, 0x04, 0x464, 0, NO_PAD_CTRL),
+	MX25_PAD_EB0__GPIO_2_12			= IOMUX_PAD(0x258, 0x040, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_EB1__EB1			= IOMUX_PAD(0x25c, 0x044, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_EB1__AUD4_RXD			= IOMUX_PAD(0x25c, 0x044, 0x14, 0x460, 0, NO_PAD_CTRL),
-	MX25_PAD_EB1__GPIO_2_13			= IOMUX_PAD(0x25c, 0x044, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_EB1__EB1			= IOMUX_PAD(0x25c, 0x044, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_EB1__AUD4_RXD			= IOMUX_PAD(0x25c, 0x044, 0x04, 0x460, 0, NO_PAD_CTRL),
+	MX25_PAD_EB1__GPIO_2_13			= IOMUX_PAD(0x25c, 0x044, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_OE__OE				= IOMUX_PAD(0x260, 0x048, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_OE__AUD4_TXC			= IOMUX_PAD(0x260, 0x048, 0x14, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_OE__GPIO_2_14			= IOMUX_PAD(0x260, 0x048, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_OE__OE				= IOMUX_PAD(0x260, 0x048, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_OE__AUD4_TXC			= IOMUX_PAD(0x260, 0x048, 0x04, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_OE__GPIO_2_14			= IOMUX_PAD(0x260, 0x048, 0x05, 0, 0, NO_PAD_CTRL),
 
 	MX25_PAD_CS0__CS0			= IOMUX_PAD(0x000, 0x04c, 0x00, 0, 0, NO_PAD_CTRL),
 	MX25_PAD_CS0__GPIO_4_2			= IOMUX_PAD(0x000, 0x04c, 0x05, 0, 0, NO_PAD_CTRL),
@@ -97,51 +97,51 @@ enum {
 	MX25_PAD_CS1__NF_CE3			= IOMUX_PAD(0x000, 0x050, 0x01, 0, 0, NO_PAD_CTRL),
 	MX25_PAD_CS1__GPIO_4_3			= IOMUX_PAD(0x000, 0x050, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_CS4__CS4			= IOMUX_PAD(0x264, 0x054, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CS4__CS4			= IOMUX_PAD(0x264, 0x054, 0x00, 0, 0, NO_PAD_CTRL),
 	MX25_PAD_CS4__NF_CE1			= IOMUX_PAD(0x264, 0x054, 0x01, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CS4__UART5_CTS			= IOMUX_PAD(0x264, 0x054, 0x13, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CS4__GPIO_3_20			= IOMUX_PAD(0x264, 0x054, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CS4__UART5_CTS			= IOMUX_PAD(0x264, 0x054, 0x03, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CS4__GPIO_3_20			= IOMUX_PAD(0x264, 0x054, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_CS5__CS5			= IOMUX_PAD(0x268, 0x058, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CS5__CS5			= IOMUX_PAD(0x268, 0x058, 0x00, 0, 0, NO_PAD_CTRL),
 	MX25_PAD_CS5__NF_CE2			= IOMUX_PAD(0x268, 0x058, 0x01, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CS5__UART5_RTS			= IOMUX_PAD(0x268, 0x058, 0x13, 0x574, 0, NO_PAD_CTRL),
-	MX25_PAD_CS5__GPIO_3_21			= IOMUX_PAD(0x268, 0x058, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CS5__UART5_RTS			= IOMUX_PAD(0x268, 0x058, 0x03, 0x574, 0, NO_PAD_CTRL),
+	MX25_PAD_CS5__GPIO_3_21			= IOMUX_PAD(0x268, 0x058, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_NF_CE0__NF_CE0			= IOMUX_PAD(0x26c, 0x05c, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_NF_CE0__GPIO_3_22		= IOMUX_PAD(0x26c, 0x05c, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_NF_CE0__NF_CE0			= IOMUX_PAD(0x26c, 0x05c, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_NF_CE0__GPIO_3_22		= IOMUX_PAD(0x26c, 0x05c, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_ECB__ECB			= IOMUX_PAD(0x270, 0x060, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_ECB__UART5_TXD_MUX		= IOMUX_PAD(0x270, 0x060, 0x13, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_ECB__GPIO_3_23			= IOMUX_PAD(0x270, 0x060, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_ECB__ECB			= IOMUX_PAD(0x270, 0x060, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_ECB__UART5_TXD_MUX		= IOMUX_PAD(0x270, 0x060, 0x03, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_ECB__GPIO_3_23			= IOMUX_PAD(0x270, 0x060, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_LBA__LBA			= IOMUX_PAD(0x274, 0x064, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_LBA__UART5_RXD_MUX		= IOMUX_PAD(0x274, 0x064, 0x13, 0x578, 0, NO_PAD_CTRL),
-	MX25_PAD_LBA__GPIO_3_24			= IOMUX_PAD(0x274, 0x064, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_LBA__LBA			= IOMUX_PAD(0x274, 0x064, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_LBA__UART5_RXD_MUX		= IOMUX_PAD(0x274, 0x064, 0x03, 0x578, 0, NO_PAD_CTRL),
+	MX25_PAD_LBA__GPIO_3_24			= IOMUX_PAD(0x274, 0x064, 0x05, 0, 0, NO_PAD_CTRL),
 
 	MX25_PAD_BCLK__BCLK			= IOMUX_PAD(0x000, 0x068, 0x00, 0, 0, NO_PAD_CTRL),
 	MX25_PAD_BCLK__GPIO_4_4			= IOMUX_PAD(0x000, 0x068, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_RW__RW				= IOMUX_PAD(0x278, 0x06c, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_RW__AUD4_TXFS			= IOMUX_PAD(0x278, 0x06c, 0x14, 0x474, 0, NO_PAD_CTRL),
-	MX25_PAD_RW__GPIO_3_25			= IOMUX_PAD(0x278, 0x06c, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_RW__RW				= IOMUX_PAD(0x278, 0x06c, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_RW__AUD4_TXFS			= IOMUX_PAD(0x278, 0x06c, 0x04, 0x474, 0, NO_PAD_CTRL),
+	MX25_PAD_RW__GPIO_3_25			= IOMUX_PAD(0x278, 0x06c, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_NFWE_B__NFWE_B			= IOMUX_PAD(0x000, 0x070, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_NFWE_B__GPIO_3_26		= IOMUX_PAD(0x000, 0x070, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_NFWE_B__NFWE_B			= IOMUX_PAD(0x000, 0x070, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_NFWE_B__GPIO_3_26		= IOMUX_PAD(0x000, 0x070, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_NFRE_B__NFRE_B			= IOMUX_PAD(0x000, 0x074, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_NFRE_B__GPIO_3_27		= IOMUX_PAD(0x000, 0x074, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_NFRE_B__NFRE_B			= IOMUX_PAD(0x000, 0x074, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_NFRE_B__GPIO_3_27		= IOMUX_PAD(0x000, 0x074, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_NFALE__NFALE			= IOMUX_PAD(0x000, 0x078, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_NFALE__GPIO_3_28		= IOMUX_PAD(0x000, 0x078, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_NFALE__NFALE			= IOMUX_PAD(0x000, 0x078, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_NFALE__GPIO_3_28		= IOMUX_PAD(0x000, 0x078, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_NFCLE__NFCLE			= IOMUX_PAD(0x000, 0x07c, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_NFCLE__GPIO_3_29		= IOMUX_PAD(0x000, 0x07c, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_NFCLE__NFCLE			= IOMUX_PAD(0x000, 0x07c, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_NFCLE__GPIO_3_29		= IOMUX_PAD(0x000, 0x07c, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_NFWP_B__NFWP_B			= IOMUX_PAD(0x000, 0x080, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_NFWP_B__GPIO_3_30		= IOMUX_PAD(0x000, 0x080, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_NFWP_B__NFWP_B			= IOMUX_PAD(0x000, 0x080, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_NFWP_B__GPIO_3_30		= IOMUX_PAD(0x000, 0x080, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_NFRB__NFRB			= IOMUX_PAD(0x27c, 0x084, 0x10, 0, 0, PAD_CTL_PKE),
-	MX25_PAD_NFRB__GPIO_3_31		= IOMUX_PAD(0x27c, 0x084, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_NFRB__NFRB			= IOMUX_PAD(0x27c, 0x084, 0x00, 0, 0, PAD_CTL_PKE),
+	MX25_PAD_NFRB__GPIO_3_31		= IOMUX_PAD(0x27c, 0x084, 0x05, 0, 0, NO_PAD_CTRL),
 
 	MX25_PAD_D15__D15			= IOMUX_PAD(0x280, 0x088, 0x00, 0, 0, NO_PAD_CTRL),
 	MX25_PAD_D15__LD16			= IOMUX_PAD(0x280, 0x088, 0x01, 0, 0, PAD_CTL_SRE_FAST),
@@ -197,309 +197,318 @@ enum {
 	MX25_PAD_D0__D0				= IOMUX_PAD(0x2bc, 0x0c4, 0x00, 0, 0, NO_PAD_CTRL),
 	MX25_PAD_D0__GPIO_4_20			= IOMUX_PAD(0x2bc, 0x0c4, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_LD0__LD0			= IOMUX_PAD(0x2c0, 0x0c8, 0x10, 0, 0, PAD_CTL_SRE_FAST),
-	MX25_PAD_LD0__CSI_D0			= IOMUX_PAD(0x2c0, 0x0c8, 0x12, 0x488, 0, NO_PAD_CTRL),
-	MX25_PAD_LD0__GPIO_2_15			= IOMUX_PAD(0x2c0, 0x0c8, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_LD0__LD0			= IOMUX_PAD(0x2c0, 0x0c8, 0x00, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD0__CSI_D0			= IOMUX_PAD(0x2c0, 0x0c8, 0x02, 0x488, 0, NO_PAD_CTRL),
+	MX25_PAD_LD0__GPIO_2_15			= IOMUX_PAD(0x2c0, 0x0c8, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_LD1__LD1			= IOMUX_PAD(0x2c4, 0x0cc, 0x10, 0, 0, PAD_CTL_SRE_FAST),
-	MX25_PAD_LD1__CSI_D1			= IOMUX_PAD(0x2c4, 0x0cc, 0x12, 0x48c, 0, NO_PAD_CTRL),
-	MX25_PAD_LD1__GPIO_2_16			= IOMUX_PAD(0x2c4, 0x0cc, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_LD1__LD1			= IOMUX_PAD(0x2c4, 0x0cc, 0x00, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD1__CSI_D1			= IOMUX_PAD(0x2c4, 0x0cc, 0x02, 0x48c, 0, NO_PAD_CTRL),
+	MX25_PAD_LD1__GPIO_2_16			= IOMUX_PAD(0x2c4, 0x0cc, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_LD2__LD2			= IOMUX_PAD(0x2c8, 0x0d0, 0x10, 0, 0, PAD_CTL_SRE_FAST),
-	MX25_PAD_LD2__GPIO_2_17			= IOMUX_PAD(0x2c8, 0x0d0, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_LD2__LD2			= IOMUX_PAD(0x2c8, 0x0d0, 0x00, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD2__GPIO_2_17			= IOMUX_PAD(0x2c8, 0x0d0, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_LD3__LD3			= IOMUX_PAD(0x2cc, 0x0d4, 0x10, 0, 0, PAD_CTL_SRE_FAST),
-	MX25_PAD_LD3__GPIO_2_18			= IOMUX_PAD(0x2cc, 0x0d4, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_LD3__LD3			= IOMUX_PAD(0x2cc, 0x0d4, 0x00, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD3__GPIO_2_18			= IOMUX_PAD(0x2cc, 0x0d4, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_LD4__LD4			= IOMUX_PAD(0x2d0, 0x0d8, 0x10, 0, 0, PAD_CTL_SRE_FAST),
-	MX25_PAD_LD4__GPIO_2_19			= IOMUX_PAD(0x2d0, 0x0d8, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_LD4__LD4			= IOMUX_PAD(0x2d0, 0x0d8, 0x00, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD4__GPIO_2_19			= IOMUX_PAD(0x2d0, 0x0d8, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_LD5__LD5			= IOMUX_PAD(0x2d4, 0x0dc, 0x10, 0, 0, PAD_CTL_SRE_FAST),
-	MX25_PAD_LD5__GPIO_1_19			= IOMUX_PAD(0x2d4, 0x0dc, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_LD5__LD5			= IOMUX_PAD(0x2d4, 0x0dc, 0x00, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD5__GPIO_1_19			= IOMUX_PAD(0x2d4, 0x0dc, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_LD6__LD6			= IOMUX_PAD(0x2d8, 0x0e0, 0x10, 0, 0, PAD_CTL_SRE_FAST),
-	MX25_PAD_LD6__GPIO_1_20			= IOMUX_PAD(0x2d8, 0x0e0, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_LD6__LD6			= IOMUX_PAD(0x2d8, 0x0e0, 0x00, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD6__GPIO_1_20			= IOMUX_PAD(0x2d8, 0x0e0, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_LD7__LD7			= IOMUX_PAD(0x2dc, 0x0e4, 0x10, 0, 0, PAD_CTL_SRE_FAST),
-	MX25_PAD_LD7__GPIO_1_21			= IOMUX_PAD(0x2dc, 0x0e4, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_LD7__LD7			= IOMUX_PAD(0x2dc, 0x0e4, 0x00, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD7__GPIO_1_21			= IOMUX_PAD(0x2dc, 0x0e4, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_LD8__LD8			= IOMUX_PAD(0x2e0, 0x0e8, 0x10, 0, 0, PAD_CTL_SRE_FAST),
-	MX25_PAD_LD8__FEC_TX_ERR		= IOMUX_PAD(0x2e0, 0x0e8, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_LD8__LD8			= IOMUX_PAD(0x2e0, 0x0e8, 0x00, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD8__FEC_TX_ERR		= IOMUX_PAD(0x2e0, 0x0e8, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_LD9__LD9			= IOMUX_PAD(0x2e4, 0x0ec, 0x10, 0, 0, PAD_CTL_SRE_FAST),
-	MX25_PAD_LD9__FEC_COL			= IOMUX_PAD(0x2e4, 0x0ec, 0x15, 0x504, 1, NO_PAD_CTRL),
+	MX25_PAD_LD9__LD9			= IOMUX_PAD(0x2e4, 0x0ec, 0x00, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD9__FEC_COL			= IOMUX_PAD(0x2e4, 0x0ec, 0x05, 0x504, 1, NO_PAD_CTRL),
 
-	MX25_PAD_LD10__LD10			= IOMUX_PAD(0x2e8, 0x0f0, 0x10, 0, 0, PAD_CTL_SRE_FAST),
-	MX25_PAD_LD10__FEC_RX_ER		= IOMUX_PAD(0x2e8, 0x0f0, 0x15, 0x518, 1, NO_PAD_CTRL),
+	MX25_PAD_LD10__LD10			= IOMUX_PAD(0x2e8, 0x0f0, 0x00, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD10__FEC_RX_ER		= IOMUX_PAD(0x2e8, 0x0f0, 0x05, 0x518, 1, NO_PAD_CTRL),
 
-	MX25_PAD_LD11__LD11			= IOMUX_PAD(0x2ec, 0x0f4, 0x10, 0, 0, PAD_CTL_SRE_FAST),
-	MX25_PAD_LD11__FEC_RDATA2		= IOMUX_PAD(0x2ec, 0x0f4, 0x15, 0x50c, 1, NO_PAD_CTRL),
+	MX25_PAD_LD11__LD11			= IOMUX_PAD(0x2ec, 0x0f4, 0x00, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD11__FEC_RDATA2		= IOMUX_PAD(0x2ec, 0x0f4, 0x05, 0x50c, 1, NO_PAD_CTRL),
 
-	MX25_PAD_LD12__LD12			= IOMUX_PAD(0x2f0, 0x0f8, 0x10, 0, 0, PAD_CTL_SRE_FAST),
-	MX25_PAD_LD12__FEC_RDATA3		= IOMUX_PAD(0x2f0, 0x0f8, 0x15, 0x510, 1, NO_PAD_CTRL),
+	MX25_PAD_LD12__LD12			= IOMUX_PAD(0x2f0, 0x0f8, 0x00, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD12__FEC_RDATA3		= IOMUX_PAD(0x2f0, 0x0f8, 0x05, 0x510, 1, NO_PAD_CTRL),
 
-	MX25_PAD_LD13__LD13			= IOMUX_PAD(0x2f4, 0x0fc, 0x10, 0, 0, PAD_CTL_SRE_FAST),
-	MX25_PAD_LD13__FEC_TDATA2		= IOMUX_PAD(0x2f4, 0x0fc, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_LD13__LD13			= IOMUX_PAD(0x2f4, 0x0fc, 0x00, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD13__FEC_TDATA2		= IOMUX_PAD(0x2f4, 0x0fc, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_LD14__LD14			= IOMUX_PAD(0x2f8, 0x100, 0x10, 0, 0, PAD_CTL_SRE_FAST),
-	MX25_PAD_LD14__FEC_TDATA3		= IOMUX_PAD(0x2f8, 0x100, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_LD14__LD14			= IOMUX_PAD(0x2f8, 0x100, 0x00, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD14__FEC_TDATA3		= IOMUX_PAD(0x2f8, 0x100, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_LD15__LD15			= IOMUX_PAD(0x2fc, 0x104, 0x10, 0, 0, PAD_CTL_SRE_FAST),
-	MX25_PAD_LD15__FEC_RX_CLK		= IOMUX_PAD(0x2fc, 0x104, 0x15, 0x514, 1, NO_PAD_CTRL),
+	MX25_PAD_LD15__LD15			= IOMUX_PAD(0x2fc, 0x104, 0x00, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD15__FEC_RX_CLK		= IOMUX_PAD(0x2fc, 0x104, 0x05, 0x514, 1, NO_PAD_CTRL),
 
-	MX25_PAD_HSYNC__HSYNC			= IOMUX_PAD(0x300, 0x108, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_HSYNC__GPIO_1_22		= IOMUX_PAD(0x300, 0x108, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_HSYNC__HSYNC			= IOMUX_PAD(0x300, 0x108, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_HSYNC__GPIO_1_22		= IOMUX_PAD(0x300, 0x108, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_VSYNC__VSYNC			= IOMUX_PAD(0x304, 0x10c, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_VSYNC__GPIO_1_23		= IOMUX_PAD(0x304, 0x10c, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_VSYNC__VSYNC			= IOMUX_PAD(0x304, 0x10c, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_VSYNC__GPIO_1_23		= IOMUX_PAD(0x304, 0x10c, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_LSCLK__LSCLK			= IOMUX_PAD(0x308, 0x110, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_LSCLK__GPIO_1_24		= IOMUX_PAD(0x308, 0x110, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_LSCLK__LSCLK			= IOMUX_PAD(0x308, 0x110, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_LSCLK__GPIO_1_24		= IOMUX_PAD(0x308, 0x110, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_OE_ACD__OE_ACD			= IOMUX_PAD(0x30c, 0x114, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_OE_ACD__GPIO_1_25		= IOMUX_PAD(0x30c, 0x114, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_OE_ACD__OE_ACD			= IOMUX_PAD(0x30c, 0x114, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_OE_ACD__GPIO_1_25		= IOMUX_PAD(0x30c, 0x114, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_CONTRAST__CONTRAST		= IOMUX_PAD(0x310, 0x118, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CONTRAST__PWM4_PWMO		= IOMUX_PAD(0x310, 0x118, 0x14, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CONTRAST__FEC_CRS		= IOMUX_PAD(0x310, 0x118, 0x15, 0x508, 1, NO_PAD_CTRL),
+	MX25_PAD_CONTRAST__CONTRAST		= IOMUX_PAD(0x310, 0x118, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CONTRAST__PWM4_PWMO		= IOMUX_PAD(0x310, 0x118, 0x04, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CONTRAST__FEC_CRS		= IOMUX_PAD(0x310, 0x118, 0x05, 0x508, 1, NO_PAD_CTRL),
 
-	MX25_PAD_PWM__PWM			= IOMUX_PAD(0x314, 0x11c, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_PWM__GPIO_1_26			= IOMUX_PAD(0x314, 0x11c, 0x15, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_PWM__USBH2_OC			= IOMUX_PAD(0x314, 0x11c, 0x16, 0x580, 1, PAD_CTL_PUS_100K_UP),
+	MX25_PAD_PWM__PWM			= IOMUX_PAD(0x314, 0x11c, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_PWM__GPIO_1_26			= IOMUX_PAD(0x314, 0x11c, 0x05, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_PWM__USBH2_OC			= IOMUX_PAD(0x314, 0x11c, 0x06, 0x580, 1, PAD_CTL_PUS_100K_UP),
 
-	MX25_PAD_CSI_D2__CSI_D2			= IOMUX_PAD(0x318, 0x120, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CSI_D2__UART5_RXD_MUX		= IOMUX_PAD(0x318, 0x120, 0x11, 0x578, 1, NO_PAD_CTRL),
-	MX25_PAD_CSI_D2__GPIO_1_27		= IOMUX_PAD(0x318, 0x120, 0x15, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CSI_D2__CSPI3_MOSI		= IOMUX_PAD(0x318, 0x120, 0x17, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D2__CSI_D2			= IOMUX_PAD(0x318, 0x120, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D2__UART5_RXD_MUX		= IOMUX_PAD(0x318, 0x120, 0x01, 0x578, 1, NO_PAD_CTRL),
+	MX25_PAD_CSI_D2__GPIO_1_27		= IOMUX_PAD(0x318, 0x120, 0x05, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D2__CSPI3_MOSI		= IOMUX_PAD(0x318, 0x120, 0x07, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_CSI_D3__CSI_D3			= IOMUX_PAD(0x31c, 0x124, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CSI_D3__GPIO_1_28		= IOMUX_PAD(0x31c, 0x124, 0x15, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CSI_D3__CSPI3_MISO		= IOMUX_PAD(0x31c, 0x124, 0x17, 0x4b4, 1, NO_PAD_CTRL),
+	MX25_PAD_CSI_D3__CSI_D3			= IOMUX_PAD(0x31c, 0x124, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D3__GPIO_1_28		= IOMUX_PAD(0x31c, 0x124, 0x05, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D3__CSPI3_MISO		= IOMUX_PAD(0x31c, 0x124, 0x07, 0x4b4, 1, NO_PAD_CTRL),
 
-	MX25_PAD_CSI_D4__CSI_D4			= IOMUX_PAD(0x320, 0x128, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CSI_D4__UART5_RTS		= IOMUX_PAD(0x320, 0x128, 0x11, 0x574, 1, NO_PAD_CTRL),
-	MX25_PAD_CSI_D4__GPIO_1_29		= IOMUX_PAD(0x320, 0x128, 0x15, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CSI_D4__CSPI3_SCLK		= IOMUX_PAD(0x320, 0x128, 0x17, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D4__CSI_D4			= IOMUX_PAD(0x320, 0x128, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D4__UART5_RTS		= IOMUX_PAD(0x320, 0x128, 0x01, 0x574, 1, NO_PAD_CTRL),
+	MX25_PAD_CSI_D4__GPIO_1_29		= IOMUX_PAD(0x320, 0x128, 0x05, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D4__CSPI3_SCLK		= IOMUX_PAD(0x320, 0x128, 0x07, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_CSI_D5__CSI_D5			= IOMUX_PAD(0x324, 0x12c, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CSI_D5__GPIO_1_30		= IOMUX_PAD(0x324, 0x12c, 0x15, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CSI_D5__CSPI3_RDY		= IOMUX_PAD(0x324, 0x12c, 0x17, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D5__CSI_D5			= IOMUX_PAD(0x324, 0x12c, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D5__GPIO_1_30		= IOMUX_PAD(0x324, 0x12c, 0x05, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D5__CSPI3_RDY		= IOMUX_PAD(0x324, 0x12c, 0x07, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_CSI_D6__CSI_D6			= IOMUX_PAD(0x328, 0x130, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CSI_D6__GPIO_1_31		= IOMUX_PAD(0x328, 0x130, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D6__CSI_D6			= IOMUX_PAD(0x328, 0x130, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D6__GPIO_1_31		= IOMUX_PAD(0x328, 0x130, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_CSI_D7__CSI_D7			= IOMUX_PAD(0x32c, 0x134, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CSI_D7__GPIO_1_6		= IOMUX_PAD(0x32c, 0x134, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D7__CSI_D7			= IOMUX_PAD(0x32c, 0x134, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D7__GPIO_1_6		= IOMUX_PAD(0x32c, 0x134, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_CSI_D8__CSI_D8			= IOMUX_PAD(0x330, 0x138, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CSI_D8__GPIO_1_7		= IOMUX_PAD(0x330, 0x138, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D8__CSI_D8			= IOMUX_PAD(0x330, 0x138, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D8__GPIO_1_7		= IOMUX_PAD(0x330, 0x138, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_CSI_D9__CSI_D9			= IOMUX_PAD(0x334, 0x13c, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CSI_D9__GPIO_4_21		= IOMUX_PAD(0x334, 0x13c, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D9__CSI_D9			= IOMUX_PAD(0x334, 0x13c, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D9__GPIO_4_21		= IOMUX_PAD(0x334, 0x13c, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_CSI_MCLK__CSI_MCLK		= IOMUX_PAD(0x338, 0x140, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CSI_MCLK__GPIO_1_8		= IOMUX_PAD(0x338, 0x140, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_MCLK__CSI_MCLK		= IOMUX_PAD(0x338, 0x140, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_MCLK__GPIO_1_8		= IOMUX_PAD(0x338, 0x140, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_CSI_VSYNC__CSI_VSYNC		= IOMUX_PAD(0x33c, 0x144, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CSI_VSYNC__GPIO_1_9		= IOMUX_PAD(0x33c, 0x144, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_VSYNC__CSI_VSYNC		= IOMUX_PAD(0x33c, 0x144, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_VSYNC__GPIO_1_9		= IOMUX_PAD(0x33c, 0x144, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_CSI_HSYNC__CSI_HSYNC		= IOMUX_PAD(0x340, 0x148, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CSI_HSYNC__GPIO_1_10		= IOMUX_PAD(0x340, 0x148, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_HSYNC__CSI_HSYNC		= IOMUX_PAD(0x340, 0x148, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_HSYNC__GPIO_1_10		= IOMUX_PAD(0x340, 0x148, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_CSI_PIXCLK__CSI_PIXCLK		= IOMUX_PAD(0x344, 0x14c, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CSI_PIXCLK__GPIO_1_11		= IOMUX_PAD(0x344, 0x14c, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_PIXCLK__CSI_PIXCLK		= IOMUX_PAD(0x344, 0x14c, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_PIXCLK__GPIO_1_11		= IOMUX_PAD(0x344, 0x14c, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_I2C1_CLK__I2C1_CLK		= IOMUX_PAD(0x348, 0x150, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_I2C1_CLK__GPIO_1_12		= IOMUX_PAD(0x348, 0x150, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_I2C1_CLK__I2C1_CLK		= IOMUX_PAD(0x348, 0x150, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_I2C1_CLK__GPIO_1_12		= IOMUX_PAD(0x348, 0x150, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_I2C1_DAT__I2C1_DAT		= IOMUX_PAD(0x34c, 0x154, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_I2C1_DAT__GPIO_1_13		= IOMUX_PAD(0x34c, 0x154, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_I2C1_DAT__I2C1_DAT		= IOMUX_PAD(0x34c, 0x154, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_I2C1_DAT__GPIO_1_13		= IOMUX_PAD(0x34c, 0x154, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_CSPI1_MOSI__CSPI1_MOSI		= IOMUX_PAD(0x350, 0x158, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CSPI1_MOSI__GPIO_1_14		= IOMUX_PAD(0x350, 0x158, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSPI1_MOSI__CSPI1_MOSI		= IOMUX_PAD(0x350, 0x158, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSPI1_MOSI__GPIO_1_14		= IOMUX_PAD(0x350, 0x158, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_CSPI1_MISO__CSPI1_MISO		= IOMUX_PAD(0x354, 0x15c, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CSPI1_MISO__GPIO_1_15		= IOMUX_PAD(0x354, 0x15c, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSPI1_MISO__CSPI1_MISO		= IOMUX_PAD(0x354, 0x15c, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSPI1_MISO__GPIO_1_15		= IOMUX_PAD(0x354, 0x15c, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_CSPI1_SS0__CSPI1_SS0		= IOMUX_PAD(0x358, 0x160, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CSPI1_SS0__GPIO_1_16		= IOMUX_PAD(0x358, 0x160, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSPI1_SS0__CSPI1_SS0		= IOMUX_PAD(0x358, 0x160, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSPI1_SS0__GPIO_1_16		= IOMUX_PAD(0x358, 0x160, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_CSPI1_SS1__CSPI1_SS1		= IOMUX_PAD(0x35c, 0x164, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CSPI1_SS1__I2C3_DAT		= IOMUX_PAD(0x35c, 0x164, 0x11, 0x528, 1, NO_PAD_CTRL),
-	MX25_PAD_CSPI1_SS1__GPIO_1_17		= IOMUX_PAD(0x35c, 0x164, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSPI1_SS1__CSPI1_SS1		= IOMUX_PAD(0x35c, 0x164, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSPI1_SS1__I2C3_DAT		= IOMUX_PAD(0x35c, 0x164, 0x01, 0x528, 1, NO_PAD_CTRL),
+	MX25_PAD_CSPI1_SS1__GPIO_1_17		= IOMUX_PAD(0x35c, 0x164, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_CSPI1_SCLK__CSPI1_SCLK		= IOMUX_PAD(0x360, 0x168, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CSPI1_SCLK__GPIO_1_18		= IOMUX_PAD(0x360, 0x168, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSPI1_SCLK__CSPI1_SCLK		= IOMUX_PAD(0x360, 0x168, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSPI1_SCLK__GPIO_1_18		= IOMUX_PAD(0x360, 0x168, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_CSPI1_RDY__CSPI1_RDY		= IOMUX_PAD(0x364, 0x16c, 0x10, 0, 0, PAD_CTL_PKE),
-	MX25_PAD_CSPI1_RDY__GPIO_2_22		= IOMUX_PAD(0x364, 0x16c, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSPI1_RDY__CSPI1_RDY		= IOMUX_PAD(0x364, 0x16c, 0x00, 0, 0, PAD_CTL_PKE),
+	MX25_PAD_CSPI1_RDY__GPIO_2_22		= IOMUX_PAD(0x364, 0x16c, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_UART1_RXD__UART1_RXD		= IOMUX_PAD(0x368, 0x170, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN),
-	MX25_PAD_UART1_RXD__GPIO_4_22		= IOMUX_PAD(0x368, 0x170, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_UART1_RXD__UART1_RXD		= IOMUX_PAD(0x368, 0x170, 0x00, 0, 0, PAD_CTL_PUS_100K_DOWN),
+	MX25_PAD_UART1_RXD__GPIO_4_22		= IOMUX_PAD(0x368, 0x170, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_UART1_TXD__UART1_TXD		= IOMUX_PAD(0x36c, 0x174, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_UART1_TXD__GPIO_4_23		= IOMUX_PAD(0x36c, 0x174, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_UART1_TXD__UART1_TXD		= IOMUX_PAD(0x36c, 0x174, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_UART1_TXD__GPIO_4_23		= IOMUX_PAD(0x36c, 0x174, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_UART1_RTS__UART1_RTS		= IOMUX_PAD(0x370, 0x178, 0x10, 0, 0, PAD_CTL_PUS_100K_UP),
-	MX25_PAD_UART1_RTS__CSI_D0		= IOMUX_PAD(0x370, 0x178, 0x11, 0x488, 1, NO_PAD_CTRL),
-	MX25_PAD_UART1_RTS__GPIO_4_24		= IOMUX_PAD(0x370, 0x178, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_UART1_RTS__UART1_RTS		= IOMUX_PAD(0x370, 0x178, 0x00, 0, 0, PAD_CTL_PUS_100K_UP),
+	MX25_PAD_UART1_RTS__CSI_D0		= IOMUX_PAD(0x370, 0x178, 0x01, 0x488, 1, NO_PAD_CTRL),
+	MX25_PAD_UART1_RTS__GPIO_4_24		= IOMUX_PAD(0x370, 0x178, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_UART1_CTS__UART1_CTS		= IOMUX_PAD(0x374, 0x17c, 0x10, 0, 0, PAD_CTL_PUS_100K_UP),
-	MX25_PAD_UART1_CTS__CSI_D1		= IOMUX_PAD(0x374, 0x17c, 0x11, 0x48c, 1, NO_PAD_CTRL),
-	MX25_PAD_UART1_CTS__GPIO_4_25		= IOMUX_PAD(0x374, 0x17c, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_UART1_CTS__UART1_CTS		= IOMUX_PAD(0x374, 0x17c, 0x00, 0, 0, PAD_CTL_PUS_100K_UP),
+	MX25_PAD_UART1_CTS__CSI_D1		= IOMUX_PAD(0x374, 0x17c, 0x01, 0x48c, 1, NO_PAD_CTRL),
+	MX25_PAD_UART1_CTS__GPIO_4_25		= IOMUX_PAD(0x374, 0x17c, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_UART2_RXD__UART2_RXD		= IOMUX_PAD(0x378, 0x180, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_UART2_RXD__GPIO_4_26		= IOMUX_PAD(0x378, 0x180, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_UART2_RXD__UART2_RXD		= IOMUX_PAD(0x378, 0x180, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_UART2_RXD__GPIO_4_26		= IOMUX_PAD(0x378, 0x180, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_UART2_TXD__UART2_TXD		= IOMUX_PAD(0x37c, 0x184, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_UART2_TXD__GPIO_4_27		= IOMUX_PAD(0x37c, 0x184, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_UART2_TXD__UART2_TXD		= IOMUX_PAD(0x37c, 0x184, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_UART2_TXD__GPIO_4_27		= IOMUX_PAD(0x37c, 0x184, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_UART2_RTS__UART2_RTS		= IOMUX_PAD(0x380, 0x188, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_UART2_RTS__FEC_COL		= IOMUX_PAD(0x380, 0x188, 0x12, 0x504, 2, NO_PAD_CTRL),
-	MX25_PAD_UART2_RTS__GPIO_4_28		= IOMUX_PAD(0x380, 0x188, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_UART2_RTS__UART2_RTS		= IOMUX_PAD(0x380, 0x188, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_UART2_RTS__FEC_COL		= IOMUX_PAD(0x380, 0x188, 0x02, 0x504, 2, NO_PAD_CTRL),
+	MX25_PAD_UART2_RTS__GPIO_4_28		= IOMUX_PAD(0x380, 0x188, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_UART2_CTS__FEC_RX_ER		= IOMUX_PAD(0x384, 0x18c, 0x12, 0x518, 2, NO_PAD_CTRL),
-	MX25_PAD_UART2_CTS__UART2_CTS		= IOMUX_PAD(0x384, 0x18c, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_UART2_CTS__GPIO_4_29		= IOMUX_PAD(0x384, 0x18c, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_UART2_CTS__FEC_RX_ER		= IOMUX_PAD(0x384, 0x18c, 0x02, 0x518, 2, NO_PAD_CTRL),
+	MX25_PAD_UART2_CTS__UART2_CTS		= IOMUX_PAD(0x384, 0x18c, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_UART2_CTS__GPIO_4_29		= IOMUX_PAD(0x384, 0x18c, 0x05, 0, 0, NO_PAD_CTRL),
 
+	/*
+	 * Removing the SION bit from MX25_PAD_SD1_CMD__SD1_CMD breaks detecting an SD
+	 * card. According to the i.MX25 reference manual (e.g. Figure 23-2 in IMX25RM
+	 * Rev. 2 from 01/2011) this pin is bidirectional. So it seems to be a silicon
+	 * bug that configuring the SD1_CMD function doesn't enable the input path for
+	 * this pin.
+	 * This might have side effects for other hardware units that are connected to
+	 * that pin and use the respective function as input.
+	 */
 	MX25_PAD_SD1_CMD__SD1_CMD		= IOMUX_PAD(0x388, 0x190, 0x10, 0, 0, PAD_CTL_PUS_47K_UP),
-	MX25_PAD_SD1_CMD__FEC_RDATA2		= IOMUX_PAD(0x388, 0x190, 0x12, 0x50c, 2, NO_PAD_CTRL),
-	MX25_PAD_SD1_CMD__GPIO_2_23		= IOMUX_PAD(0x388, 0x190, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_SD1_CMD__FEC_RDATA2		= IOMUX_PAD(0x388, 0x190, 0x02, 0x50c, 2, NO_PAD_CTRL),
+	MX25_PAD_SD1_CMD__GPIO_2_23		= IOMUX_PAD(0x388, 0x190, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_SD1_CLK__SD1_CLK		= IOMUX_PAD(0x38c, 0x194, 0x10, 0, 0, PAD_CTL_PUS_47K_UP),
-	MX25_PAD_SD1_CLK__FEC_RDATA3		= IOMUX_PAD(0x38c, 0x194, 0x12, 0x510, 2, NO_PAD_CTRL),
-	MX25_PAD_SD1_CLK__GPIO_2_24		= IOMUX_PAD(0x38c, 0x194, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_SD1_CLK__SD1_CLK		= IOMUX_PAD(0x38c, 0x194, 0x00, 0, 0, PAD_CTL_PUS_47K_UP),
+	MX25_PAD_SD1_CLK__FEC_RDATA3		= IOMUX_PAD(0x38c, 0x194, 0x02, 0x510, 2, NO_PAD_CTRL),
+	MX25_PAD_SD1_CLK__GPIO_2_24		= IOMUX_PAD(0x38c, 0x194, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_SD1_DATA0__SD1_DATA0		= IOMUX_PAD(0x390, 0x198, 0x10, 0, 0, PAD_CTL_PUS_47K_UP),
-	MX25_PAD_SD1_DATA0__GPIO_2_25		= IOMUX_PAD(0x390, 0x198, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_SD1_DATA0__SD1_DATA0		= IOMUX_PAD(0x390, 0x198, 0x00, 0, 0, PAD_CTL_PUS_47K_UP),
+	MX25_PAD_SD1_DATA0__GPIO_2_25		= IOMUX_PAD(0x390, 0x198, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_SD1_DATA1__SD1_DATA1		= IOMUX_PAD(0x394, 0x19c, 0x10, 0, 0, PAD_CTL_PUS_47K_UP),
-	MX25_PAD_SD1_DATA1__AUD7_RXD		= IOMUX_PAD(0x394, 0x19c, 0x13, 0x478, 0, NO_PAD_CTRL),
-	MX25_PAD_SD1_DATA1__GPIO_2_26		= IOMUX_PAD(0x394, 0x19c, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_SD1_DATA1__SD1_DATA1		= IOMUX_PAD(0x394, 0x19c, 0x00, 0, 0, PAD_CTL_PUS_47K_UP),
+	MX25_PAD_SD1_DATA1__AUD7_RXD		= IOMUX_PAD(0x394, 0x19c, 0x03, 0x478, 0, NO_PAD_CTRL),
+	MX25_PAD_SD1_DATA1__GPIO_2_26		= IOMUX_PAD(0x394, 0x19c, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_SD1_DATA2__SD1_DATA2		= IOMUX_PAD(0x398, 0x1a0, 0x10, 0, 0, PAD_CTL_PUS_47K_UP),
-	MX25_PAD_SD1_DATA2__FEC_RX_CLK		= IOMUX_PAD(0x398, 0x1a0, 0x15, 0x514, 2, NO_PAD_CTRL),
-	MX25_PAD_SD1_DATA2__GPIO_2_27		= IOMUX_PAD(0x398, 0x1a0, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_SD1_DATA2__SD1_DATA2		= IOMUX_PAD(0x398, 0x1a0, 0x00, 0, 0, PAD_CTL_PUS_47K_UP),
+	MX25_PAD_SD1_DATA2__FEC_RX_CLK		= IOMUX_PAD(0x398, 0x1a0, 0x05, 0x514, 2, NO_PAD_CTRL),
+	MX25_PAD_SD1_DATA2__GPIO_2_27		= IOMUX_PAD(0x398, 0x1a0, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_SD1_DATA3__SD1_DATA3		= IOMUX_PAD(0x39c, 0x1a4, 0x10, 0, 0, PAD_CTL_PUS_47K_UP),
-	MX25_PAD_SD1_DATA3__FEC_CRS		= IOMUX_PAD(0x39c, 0x1a4, 0x10, 0x508, 2, NO_PAD_CTRL),
-	MX25_PAD_SD1_DATA3__GPIO_2_28		= IOMUX_PAD(0x39c, 0x1a4, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_SD1_DATA3__SD1_DATA3		= IOMUX_PAD(0x39c, 0x1a4, 0x00, 0, 0, PAD_CTL_PUS_47K_UP),
+	MX25_PAD_SD1_DATA3__FEC_CRS		= IOMUX_PAD(0x39c, 0x1a4, 0x00, 0x508, 2, NO_PAD_CTRL),
+	MX25_PAD_SD1_DATA3__GPIO_2_28		= IOMUX_PAD(0x39c, 0x1a4, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_KPP_ROW0__KPP_ROW0		= IOMUX_PAD(0x3a0, 0x1a8, 0x10, 0, 0, MX25_KPP_ROW_PAD_CTRL),
-	MX25_PAD_KPP_ROW0__GPIO_2_29		= IOMUX_PAD(0x3a0, 0x1a8, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_KPP_ROW0__KPP_ROW0		= IOMUX_PAD(0x3a0, 0x1a8, 0x00, 0, 0, MX25_KPP_ROW_PAD_CTRL),
+	MX25_PAD_KPP_ROW0__GPIO_2_29		= IOMUX_PAD(0x3a0, 0x1a8, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_KPP_ROW1__KPP_ROW1		= IOMUX_PAD(0x3a4, 0x1ac, 0x10, 0, 0, MX25_KPP_ROW_PAD_CTRL),
-	MX25_PAD_KPP_ROW1__GPIO_2_30		= IOMUX_PAD(0x3a4, 0x1ac, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_KPP_ROW1__KPP_ROW1		= IOMUX_PAD(0x3a4, 0x1ac, 0x00, 0, 0, MX25_KPP_ROW_PAD_CTRL),
+	MX25_PAD_KPP_ROW1__GPIO_2_30		= IOMUX_PAD(0x3a4, 0x1ac, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_KPP_ROW2__KPP_ROW2		= IOMUX_PAD(0x3a8, 0x1b0, 0x10, 0, 0, MX25_KPP_ROW_PAD_CTRL),
-	MX25_PAD_KPP_ROW2__CSI_D0		= IOMUX_PAD(0x3a8, 0x1b0, 0x13, 0x488, 2, NO_PAD_CTRL),
-	MX25_PAD_KPP_ROW2__GPIO_2_31		= IOMUX_PAD(0x3a8, 0x1b0, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_KPP_ROW2__KPP_ROW2		= IOMUX_PAD(0x3a8, 0x1b0, 0x00, 0, 0, MX25_KPP_ROW_PAD_CTRL),
+	MX25_PAD_KPP_ROW2__CSI_D0		= IOMUX_PAD(0x3a8, 0x1b0, 0x03, 0x488, 2, NO_PAD_CTRL),
+	MX25_PAD_KPP_ROW2__GPIO_2_31		= IOMUX_PAD(0x3a8, 0x1b0, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_KPP_ROW3__KPP_ROW3		= IOMUX_PAD(0x3ac, 0x1b4, 0x10, 0, 0, MX25_KPP_ROW_PAD_CTRL),
-	MX25_PAD_KPP_ROW3__CSI_LD1		= IOMUX_PAD(0x3ac, 0x1b4, 0x13, 0x48c, 2, NO_PAD_CTRL),
-	MX25_PAD_KPP_ROW3__GPIO_3_0		= IOMUX_PAD(0x3ac, 0x1b4, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_KPP_ROW3__KPP_ROW3		= IOMUX_PAD(0x3ac, 0x1b4, 0x00, 0, 0, MX25_KPP_ROW_PAD_CTRL),
+	MX25_PAD_KPP_ROW3__CSI_LD1		= IOMUX_PAD(0x3ac, 0x1b4, 0x03, 0x48c, 2, NO_PAD_CTRL),
+	MX25_PAD_KPP_ROW3__GPIO_3_0		= IOMUX_PAD(0x3ac, 0x1b4, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_KPP_COL0__KPP_COL0		= IOMUX_PAD(0x3b0, 0x1b8, 0x10, 0, 0, MX25_KPP_COL_PAD_CTRL),
-	MX25_PAD_KPP_COL0__UART4_RXD_MUX	= IOMUX_PAD(0x3b0, 0x1b8, 0x11, 0x570, 1, NO_PAD_CTRL),
-	MX25_PAD_KPP_COL0__AUD5_TXD		= IOMUX_PAD(0x3b0, 0x1b8, 0x12, 0, 0, PAD_CTL_PUS_100K_UP),
-	MX25_PAD_KPP_COL0__GPIO_3_1		= IOMUX_PAD(0x3b0, 0x1b8, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_KPP_COL0__KPP_COL0		= IOMUX_PAD(0x3b0, 0x1b8, 0x00, 0, 0, MX25_KPP_COL_PAD_CTRL),
+	MX25_PAD_KPP_COL0__UART4_RXD_MUX	= IOMUX_PAD(0x3b0, 0x1b8, 0x01, 0x570, 1, NO_PAD_CTRL),
+	MX25_PAD_KPP_COL0__AUD5_TXD		= IOMUX_PAD(0x3b0, 0x1b8, 0x02, 0, 0, PAD_CTL_PUS_100K_UP),
+	MX25_PAD_KPP_COL0__GPIO_3_1		= IOMUX_PAD(0x3b0, 0x1b8, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_KPP_COL1__KPP_COL1		= IOMUX_PAD(0x3b4, 0x1bc, 0x10, 0, 0, MX25_KPP_COL_PAD_CTRL),
-	MX25_PAD_KPP_COL1__UART4_TXD_MUX	= IOMUX_PAD(0x3b4, 0x1bc, 0x11, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_KPP_COL1__AUD5_RXD		= IOMUX_PAD(0x3b4, 0x1bc, 0x12, 0, 0, PAD_CTL_PUS_100K_UP),
-	MX25_PAD_KPP_COL1__GPIO_3_2		= IOMUX_PAD(0x3b4, 0x1bc, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_KPP_COL1__KPP_COL1		= IOMUX_PAD(0x3b4, 0x1bc, 0x00, 0, 0, MX25_KPP_COL_PAD_CTRL),
+	MX25_PAD_KPP_COL1__UART4_TXD_MUX	= IOMUX_PAD(0x3b4, 0x1bc, 0x01, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_KPP_COL1__AUD5_RXD		= IOMUX_PAD(0x3b4, 0x1bc, 0x02, 0, 0, PAD_CTL_PUS_100K_UP),
+	MX25_PAD_KPP_COL1__GPIO_3_2		= IOMUX_PAD(0x3b4, 0x1bc, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_KPP_COL2__KPP_COL2		= IOMUX_PAD(0x3b8, 0x1c0, 0x10, 0, 0, MX25_KPP_COL_PAD_CTRL),
-	MX25_PAD_KPP_COL2__UART4_RTS		= IOMUX_PAD(0x3b8, 0x1c0, 0x11, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_KPP_COL2__AUD5_TXC		= IOMUX_PAD(0x3b8, 0x1c0, 0x12, 0, 0, PAD_CTL_PUS_100K_UP),
-	MX25_PAD_KPP_COL2__GPIO_3_3		= IOMUX_PAD(0x3b8, 0x1c0, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_KPP_COL2__KPP_COL2		= IOMUX_PAD(0x3b8, 0x1c0, 0x00, 0, 0, MX25_KPP_COL_PAD_CTRL),
+	MX25_PAD_KPP_COL2__UART4_RTS		= IOMUX_PAD(0x3b8, 0x1c0, 0x01, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_KPP_COL2__AUD5_TXC		= IOMUX_PAD(0x3b8, 0x1c0, 0x02, 0, 0, PAD_CTL_PUS_100K_UP),
+	MX25_PAD_KPP_COL2__GPIO_3_3		= IOMUX_PAD(0x3b8, 0x1c0, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_KPP_COL3__KPP_COL3		= IOMUX_PAD(0x3bc, 0x1c4, 0x10, 0, 0, MX25_KPP_COL_PAD_CTRL),
-	MX25_PAD_KPP_COL3__UART4_CTS		= IOMUX_PAD(0x3bc, 0x1c4, 0x11, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_KPP_COL3__AUD5_TXFS		= IOMUX_PAD(0x3bc, 0x1c4, 0x12, 0, 0, PAD_CTL_PUS_100K_UP),
-	MX25_PAD_KPP_COL3__GPIO_3_4		= IOMUX_PAD(0x3bc, 0x1c4, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_KPP_COL3__KPP_COL3		= IOMUX_PAD(0x3bc, 0x1c4, 0x00, 0, 0, MX25_KPP_COL_PAD_CTRL),
+	MX25_PAD_KPP_COL3__UART4_CTS		= IOMUX_PAD(0x3bc, 0x1c4, 0x01, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_KPP_COL3__AUD5_TXFS		= IOMUX_PAD(0x3bc, 0x1c4, 0x02, 0, 0, PAD_CTL_PUS_100K_UP),
+	MX25_PAD_KPP_COL3__GPIO_3_4		= IOMUX_PAD(0x3bc, 0x1c4, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_FEC_MDC__FEC_MDC		= IOMUX_PAD(0x3c0, 0x1c8, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_FEC_MDC__AUD4_TXD		= IOMUX_PAD(0x3c0, 0x1c8, 0x12, 0x464, 1, NO_PAD_CTRL),
-	MX25_PAD_FEC_MDC__GPIO_3_5		= IOMUX_PAD(0x3c0, 0x1c8, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_FEC_MDC__FEC_MDC		= IOMUX_PAD(0x3c0, 0x1c8, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_FEC_MDC__AUD4_TXD		= IOMUX_PAD(0x3c0, 0x1c8, 0x02, 0x464, 1, NO_PAD_CTRL),
+	MX25_PAD_FEC_MDC__GPIO_3_5		= IOMUX_PAD(0x3c0, 0x1c8, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_FEC_MDIO__FEC_MDIO		= IOMUX_PAD(0x3c4, 0x1cc, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_22K_UP),
-	MX25_PAD_FEC_MDIO__AUD4_RXD		= IOMUX_PAD(0x3c4, 0x1cc, 0x12, 0x460, 1, NO_PAD_CTRL),
-	MX25_PAD_FEC_MDIO__GPIO_3_6		= IOMUX_PAD(0x3c4, 0x1cc, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_FEC_MDIO__FEC_MDIO		= IOMUX_PAD(0x3c4, 0x1cc, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_22K_UP),
+	MX25_PAD_FEC_MDIO__AUD4_RXD		= IOMUX_PAD(0x3c4, 0x1cc, 0x02, 0x460, 1, NO_PAD_CTRL),
+	MX25_PAD_FEC_MDIO__GPIO_3_6		= IOMUX_PAD(0x3c4, 0x1cc, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_FEC_TDATA0__FEC_TDATA0		= IOMUX_PAD(0x3c8, 0x1d0, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_FEC_TDATA0__GPIO_3_7		= IOMUX_PAD(0x3c8, 0x1d0, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_FEC_TDATA0__FEC_TDATA0		= IOMUX_PAD(0x3c8, 0x1d0, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_FEC_TDATA0__GPIO_3_7		= IOMUX_PAD(0x3c8, 0x1d0, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_FEC_TDATA1__FEC_TDATA1		= IOMUX_PAD(0x3cc, 0x1d4, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_FEC_TDATA1__AUD4_TXFS		= IOMUX_PAD(0x3cc, 0x1d4, 0x12, 0x474, 1, NO_PAD_CTRL),
-	MX25_PAD_FEC_TDATA1__GPIO_3_8		= IOMUX_PAD(0x3cc, 0x1d4, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_FEC_TDATA1__FEC_TDATA1		= IOMUX_PAD(0x3cc, 0x1d4, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_FEC_TDATA1__AUD4_TXFS		= IOMUX_PAD(0x3cc, 0x1d4, 0x02, 0x474, 1, NO_PAD_CTRL),
+	MX25_PAD_FEC_TDATA1__GPIO_3_8		= IOMUX_PAD(0x3cc, 0x1d4, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_FEC_TX_EN__FEC_TX_EN		= IOMUX_PAD(0x3d0, 0x1d8, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_FEC_TX_EN__GPIO_3_9		= IOMUX_PAD(0x3d0, 0x1d8, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_FEC_TX_EN__FEC_TX_EN		= IOMUX_PAD(0x3d0, 0x1d8, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_FEC_TX_EN__GPIO_3_9		= IOMUX_PAD(0x3d0, 0x1d8, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_FEC_RDATA0__FEC_RDATA0		= IOMUX_PAD(0x3d4, 0x1dc, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
-	MX25_PAD_FEC_RDATA0__GPIO_3_10		= IOMUX_PAD(0x3d4, 0x1dc, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_FEC_RDATA0__FEC_RDATA0		= IOMUX_PAD(0x3d4, 0x1dc, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
+	MX25_PAD_FEC_RDATA0__GPIO_3_10		= IOMUX_PAD(0x3d4, 0x1dc, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_FEC_RDATA1__FEC_RDATA1		= IOMUX_PAD(0x3d8, 0x1e0, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
-	MX25_PAD_FEC_RDATA1__GPIO_3_11		= IOMUX_PAD(0x3d8, 0x1e0, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_FEC_RDATA1__FEC_RDATA1		= IOMUX_PAD(0x3d8, 0x1e0, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
+	MX25_PAD_FEC_RDATA1__GPIO_3_11		= IOMUX_PAD(0x3d8, 0x1e0, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_FEC_RX_DV__FEC_RX_DV		= IOMUX_PAD(0x3dc, 0x1e4, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
-	MX25_PAD_FEC_RX_DV__CAN2_RX		= IOMUX_PAD(0x3dc, 0x1e4, 0x14, 0x484, 0, PAD_CTL_PUS_22K_UP),
-	MX25_PAD_FEC_RX_DV__GPIO_3_12		= IOMUX_PAD(0x3dc, 0x1e4, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_FEC_RX_DV__FEC_RX_DV		= IOMUX_PAD(0x3dc, 0x1e4, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
+	MX25_PAD_FEC_RX_DV__CAN2_RX		= IOMUX_PAD(0x3dc, 0x1e4, 0x04, 0x484, 0, PAD_CTL_PUS_22K_UP),
+	MX25_PAD_FEC_RX_DV__GPIO_3_12		= IOMUX_PAD(0x3dc, 0x1e4, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_FEC_TX_CLK__FEC_TX_CLK		= IOMUX_PAD(0x3e0, 0x1e8, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
-	MX25_PAD_FEC_TX_CLK__GPIO_3_13		= IOMUX_PAD(0x3e0, 0x1e8, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_FEC_TX_CLK__FEC_TX_CLK		= IOMUX_PAD(0x3e0, 0x1e8, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
+	MX25_PAD_FEC_TX_CLK__GPIO_3_13		= IOMUX_PAD(0x3e0, 0x1e8, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_RTCK__RTCK			= IOMUX_PAD(0x3e4, 0x1ec, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_RTCK__OWIRE			= IOMUX_PAD(0x3e4, 0x1ec, 0x11, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_RTCK__GPIO_3_14		= IOMUX_PAD(0x3e4, 0x1ec, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_RTCK__RTCK			= IOMUX_PAD(0x3e4, 0x1ec, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_RTCK__OWIRE			= IOMUX_PAD(0x3e4, 0x1ec, 0x01, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_RTCK__GPIO_3_14		= IOMUX_PAD(0x3e4, 0x1ec, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_DE_B__DE_B			= IOMUX_PAD(0x3ec, 0x1f0, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_DE_B__GPIO_2_20		= IOMUX_PAD(0x3ec, 0x1f0, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_DE_B__DE_B			= IOMUX_PAD(0x3ec, 0x1f0, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_DE_B__GPIO_2_20		= IOMUX_PAD(0x3ec, 0x1f0, 0x05, 0, 0, NO_PAD_CTRL),
 
 	MX25_PAD_TDO__TDO			= IOMUX_PAD(0x3e8, 0x000, 0x00, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_GPIO_A__GPIO_A			= IOMUX_PAD(0x3f0, 0x1f4, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_GPIO_A__CAN1_TX		= IOMUX_PAD(0x3f0, 0x1f4, 0x16, 0, 0, PAD_CTL_PUS_22K_UP),
-	MX25_PAD_GPIO_A__USBOTG_PWR		= IOMUX_PAD(0x3f0, 0x1f4, 0x12, 0, 0, PAD_CTL_PKE),
+	MX25_PAD_GPIO_A__GPIO_A			= IOMUX_PAD(0x3f0, 0x1f4, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_GPIO_A__CAN1_TX		= IOMUX_PAD(0x3f0, 0x1f4, 0x06, 0, 0, PAD_CTL_PUS_22K_UP),
+	MX25_PAD_GPIO_A__USBOTG_PWR		= IOMUX_PAD(0x3f0, 0x1f4, 0x02, 0, 0, PAD_CTL_PKE),
 
-	MX25_PAD_GPIO_B__GPIO_B			= IOMUX_PAD(0x3f4, 0x1f8, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_GPIO_B__CAN1_RX		= IOMUX_PAD(0x3f4, 0x1f8, 0x16, 0x480, 1, PAD_CTL_PUS_22K_UP),
-	MX25_PAD_GPIO_B__USBOTG_OC		= IOMUX_PAD(0x3f4, 0x1f8, 0x12, 0x57c, 1, PAD_CTL_PUS_100K_UP),
+	MX25_PAD_GPIO_B__GPIO_B			= IOMUX_PAD(0x3f4, 0x1f8, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_GPIO_B__CAN1_RX		= IOMUX_PAD(0x3f4, 0x1f8, 0x06, 0x480, 1, PAD_CTL_PUS_22K_UP),
+	MX25_PAD_GPIO_B__USBOTG_OC		= IOMUX_PAD(0x3f4, 0x1f8, 0x02, 0x57c, 1, PAD_CTL_PUS_100K_UP),
 
-	MX25_PAD_GPIO_C__GPIO_C			= IOMUX_PAD(0x3f8, 0x1fc, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_GPIO_C__CAN2_TX		= IOMUX_PAD(0x3f8, 0x1fc, 0x16, 0, 0, PAD_CTL_PUS_22K_UP),
+	MX25_PAD_GPIO_C__GPIO_C			= IOMUX_PAD(0x3f8, 0x1fc, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_GPIO_C__CAN2_TX		= IOMUX_PAD(0x3f8, 0x1fc, 0x06, 0, 0, PAD_CTL_PUS_22K_UP),
 
-	MX25_PAD_GPIO_D__GPIO_D			= IOMUX_PAD(0x3fc, 0x200, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_GPIO_D__GPIO_D			= IOMUX_PAD(0x3fc, 0x200, 0x00, 0, 0, NO_PAD_CTRL),
 	MX25_PAD_GPIO_E__LD16			= IOMUX_PAD(0x400, 0x204, 0x02, 0, 0, PAD_CTL_SRE_FAST),
-	MX25_PAD_GPIO_D__CAN2_RX		= IOMUX_PAD(0x3fc, 0x200, 0x16, 0x484, 1, PAD_CTL_PUS_22K_UP),
+	MX25_PAD_GPIO_D__CAN2_RX		= IOMUX_PAD(0x3fc, 0x200, 0x06, 0x484, 1, PAD_CTL_PUS_22K_UP),
 
-	MX25_PAD_GPIO_E__GPIO_E			= IOMUX_PAD(0x400, 0x204, 0x10, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_GPIO_E__GPIO_E			= IOMUX_PAD(0x400, 0x204, 0x00, 0, 0, NO_PAD_CTRL),
 	MX25_PAD_GPIO_F__LD17			= IOMUX_PAD(0x404, 0x208, 0x02, 0, 0, PAD_CTL_SRE_FAST),
-	MX25_PAD_GPIO_E__I2C3_CLK		= IOMUX_PAD(0x400, 0x204, 0x11, 0x524, 2, NO_PAD_CTRL),
-	MX25_PAD_GPIO_E__AUD7_TXD		= IOMUX_PAD(0x400, 0x204, 0x14, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_GPIO_E__I2C3_CLK		= IOMUX_PAD(0x400, 0x204, 0x01, 0x524, 2, NO_PAD_CTRL),
+	MX25_PAD_GPIO_E__AUD7_TXD		= IOMUX_PAD(0x400, 0x204, 0x04, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_GPIO_F__GPIO_F			= IOMUX_PAD(0x404, 0x208, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_GPIO_F__AUD7_TXC		= IOMUX_PAD(0x404, 0x208, 0x14, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_GPIO_F__GPIO_F			= IOMUX_PAD(0x404, 0x208, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_GPIO_F__AUD7_TXC		= IOMUX_PAD(0x404, 0x208, 0x04, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_EXT_ARMCLK__EXT_ARMCLK		= IOMUX_PAD(0x000, 0x20c, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_EXT_ARMCLK__GPIO_3_15		= IOMUX_PAD(0x000, 0x20c, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_EXT_ARMCLK__EXT_ARMCLK		= IOMUX_PAD(0x000, 0x20c, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_EXT_ARMCLK__GPIO_3_15		= IOMUX_PAD(0x000, 0x20c, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK	= IOMUX_PAD(0x000, 0x210, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_UPLL_BYPCLK__GPIO_3_16		= IOMUX_PAD(0x000, 0x210, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK	= IOMUX_PAD(0x000, 0x210, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_UPLL_BYPCLK__GPIO_3_16		= IOMUX_PAD(0x000, 0x210, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_VSTBY_REQ__VSTBY_REQ		= IOMUX_PAD(0x408, 0x214, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_VSTBY_REQ__AUD7_TXFS		= IOMUX_PAD(0x408, 0x214, 0x14, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_VSTBY_REQ__GPIO_3_17		= IOMUX_PAD(0x408, 0x214, 0x15, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_VSTBY_ACK__VSTBY_ACK		= IOMUX_PAD(0x40c, 0x218, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_VSTBY_ACK__GPIO_3_18		= IOMUX_PAD(0x40c, 0x218, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_VSTBY_REQ__VSTBY_REQ		= IOMUX_PAD(0x408, 0x214, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_VSTBY_REQ__AUD7_TXFS		= IOMUX_PAD(0x408, 0x214, 0x04, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_VSTBY_REQ__GPIO_3_17		= IOMUX_PAD(0x408, 0x214, 0x05, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_VSTBY_ACK__VSTBY_ACK		= IOMUX_PAD(0x40c, 0x218, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_VSTBY_ACK__GPIO_3_18		= IOMUX_PAD(0x40c, 0x218, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_POWER_FAIL__POWER_FAIL		= IOMUX_PAD(0x410, 0x21c, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_POWER_FAIL__AUD7_RXD		= IOMUX_PAD(0x410, 0x21c, 0x14, 0x478, 1, NO_PAD_CTRL),
-	MX25_PAD_POWER_FAIL__GPIO_3_19		= IOMUX_PAD(0x410, 0x21c, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_POWER_FAIL__POWER_FAIL		= IOMUX_PAD(0x410, 0x21c, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_POWER_FAIL__AUD7_RXD		= IOMUX_PAD(0x410, 0x21c, 0x04, 0x478, 1, NO_PAD_CTRL),
+	MX25_PAD_POWER_FAIL__GPIO_3_19		= IOMUX_PAD(0x410, 0x21c, 0x05, 0, 0, NO_PAD_CTRL),
 
-	MX25_PAD_CLKO__CLKO			= IOMUX_PAD(0x414, 0x220, 0x10, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CLKO__GPIO_2_21		= IOMUX_PAD(0x414, 0x220, 0x15, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CLKO__CLKO			= IOMUX_PAD(0x414, 0x220, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CLKO__GPIO_2_21		= IOMUX_PAD(0x414, 0x220, 0x05, 0, 0, NO_PAD_CTRL),
 
 	MX25_PAD_BOOT_MODE0__BOOT_MODE0		= IOMUX_PAD(0x000, 0x224, 0x00, 0, 0, NO_PAD_CTRL),
 	MX25_PAD_BOOT_MODE0__GPIO_4_30		= IOMUX_PAD(0x000, 0x224, 0x05, 0, 0, NO_PAD_CTRL),

arch/arm/include/asm/arch-mx6/imx-regs.h

@@ -482,10 +482,11 @@ struct src {
 
 #define src_base ((struct src *)SRC_BASE_ADDR)
 
-#define SRC_SCR_M4_ENABLE_OFFSET                22
-#define SRC_SCR_M4_ENABLE_MASK                  (1 << 22)
-#define SRC_SCR_M4C_NON_SCLR_RST_OFFSET         4
-#define SRC_SCR_M4C_NON_SCLR_RST_MASK           (1 << 4)
+#define SRC_M4_REG_OFFSET		0
+#define SRC_M4_ENABLE_OFFSET		22
+#define SRC_M4_ENABLE_MASK		BIT(22)
+#define SRC_M4C_NON_SCLR_RST_OFFSET	4
+#define SRC_M4C_NON_SCLR_RST_MASK	BIT(4)
 
 /* GPR1 bitfields */
 #define IOMUXC_GPR1_APP_CLK_REQ_N		BIT(30)

arch/arm/include/asm/arch-mx7/imx-regs.h

@@ -264,10 +264,12 @@ struct src {
 	u32 ddrc_rcr;
 };
 
-#define SRC_M4RCR_M4C_NON_SCLR_RST_OFFSET	0
-#define SRC_M4RCR_M4C_NON_SCLR_RST_MASK		(1 << 0)
-#define SRC_M4RCR_ENABLE_M4_OFFSET		3
-#define SRC_M4RCR_ENABLE_M4_MASK		(1 << 3)
+#define SRC_M4_REG_OFFSET		0xC
+#define SRC_M4C_NON_SCLR_RST_OFFSET	0
+#define SRC_M4C_NON_SCLR_RST_MASK	BIT(0)
+#define SRC_M4_ENABLE_OFFSET		3
+#define SRC_M4_ENABLE_MASK		BIT(3)
+
 #define SRC_DDRC_RCR_DDRC_CORE_RST_OFFSET	1
 #define SRC_DDRC_RCR_DDRC_CORE_RST_MASK		(1 << 1)
 
@@ -1208,14 +1210,6 @@ extern void pcie_power_off(void);
 	readl(USBOTG2_IPS_BASE_ADDR + 0x158))
 #define	disconnect_from_pc(void) writel(0x0, USBOTG1_IPS_BASE_ADDR + 0x140)
 
-/* Boot device type */
-#define BOOT_TYPE_SD		0x1
-#define BOOT_TYPE_MMC		0x2
-#define BOOT_TYPE_NAND		0x3
-#define BOOT_TYPE_QSPI		0x4
-#define BOOT_TYPE_WEIM		0x5
-#define BOOT_TYPE_SPINOR	0x6
-
 struct bootrom_sw_info {
 	u8 reserved_1;
 	u8 boot_dev_instance;

arch/arm/include/asm/arch-mx8m/clock.h

@@ -0,0 +1,657 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * Peng Fan <peng.fan@nxp.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_IMX8M_CLOCK_H
+#define _ASM_ARCH_IMX8M_CLOCK_H
+
+#include <linux/bitops.h>
+
+enum pll_clocks {
+	ANATOP_ARM_PLL,
+	ANATOP_GPU_PLL,
+	ANATOP_SYSTEM_PLL1,
+	ANATOP_SYSTEM_PLL2,
+	ANATOP_SYSTEM_PLL3,
+	ANATOP_AUDIO_PLL1,
+	ANATOP_AUDIO_PLL2,
+	ANATOP_VIDEO_PLL1,
+	ANATOP_VIDEO_PLL2,
+	ANATOP_DRAM_PLL,
+};
+
+enum clk_slice_type {
+	CORE_CLOCK_SLICE,
+	BUS_CLOCK_SLICE,
+	IP_CLOCK_SLICE,
+	AHB_CLOCK_SLICE,
+	IPG_CLOCK_SLICE,
+	CORE_SEL_CLOCK_SLICE,
+	DRAM_SEL_CLOCK_SLICE,
+};
+
+enum clk_root_index {
+	MXC_ARM_CLK			= 0,
+	ARM_A53_CLK_ROOT		= 0,
+	ARM_M4_CLK_ROOT			= 1,
+	VPU_A53_CLK_ROOT		= 2,
+	GPU_CORE_CLK_ROOT		= 3,
+	GPU_SHADER_CLK_ROOT		= 4,
+	MAIN_AXI_CLK_ROOT		= 16,
+	ENET_AXI_CLK_ROOT		= 17,
+	NAND_USDHC_BUS_CLK_ROOT		= 18,
+	VPU_BUS_CLK_ROOT		= 19,
+	DISPLAY_AXI_CLK_ROOT		= 20,
+	DISPLAY_APB_CLK_ROOT		= 21,
+	DISPLAY_RTRM_CLK_ROOT		= 22,
+	USB_BUS_CLK_ROOT		= 23,
+	GPU_AXI_CLK_ROOT		= 24,
+	GPU_AHB_CLK_ROOT		= 25,
+	NOC_CLK_ROOT			= 26,
+	NOC_APB_CLK_ROOT		= 27,
+	AHB_CLK_ROOT			= 32,
+	IPG_CLK_ROOT			= 33,
+	MXC_IPG_CLK			= 33,
+	AUDIO_AHB_CLK_ROOT		= 34,
+	MIPI_DSI_ESC_RX_CLK_ROOT	= 36,
+	DRAM_SEL_CFG			= 48,
+	CORE_SEL_CFG			= 49,
+	DRAM_ALT_CLK_ROOT		= 64,
+	DRAM_APB_CLK_ROOT		= 65,
+	VPU_G1_CLK_ROOT			= 66,
+	VPU_G2_CLK_ROOT			= 67,
+	DISPLAY_DTRC_CLK_ROOT		= 68,
+	DISPLAY_DC8000_CLK_ROOT		= 69,
+	PCIE1_CTRL_CLK_ROOT		= 70,
+	PCIE1_PHY_CLK_ROOT		= 71,
+	PCIE1_AUX_CLK_ROOT		= 72,
+	DC_PIXEL_CLK_ROOT		= 73,
+	LCDIF_PIXEL_CLK_ROOT		= 74,
+	SAI1_CLK_ROOT			= 75,
+	SAI2_CLK_ROOT			= 76,
+	SAI3_CLK_ROOT			= 77,
+	SAI4_CLK_ROOT			= 78,
+	SAI5_CLK_ROOT			= 79,
+	SAI6_CLK_ROOT			= 80,
+	SPDIF1_CLK_ROOT			= 81,
+	SPDIF2_CLK_ROOT			= 82,
+	ENET_REF_CLK_ROOT		= 83,
+	ENET_TIMER_CLK_ROOT		= 84,
+	ENET_PHY_REF_CLK_ROOT		= 85,
+	NAND_CLK_ROOT			= 86,
+	QSPI_CLK_ROOT			= 87,
+	MXC_ESDHC_CLK			= 88,
+	USDHC1_CLK_ROOT			= 88,
+	MXC_ESDHC2_CLK			= 89,
+	USDHC2_CLK_ROOT			= 89,
+	I2C1_CLK_ROOT			= 90,
+	MXC_I2C_CLK			= 90,
+	I2C2_CLK_ROOT			= 91,
+	I2C3_CLK_ROOT			= 92,
+	I2C4_CLK_ROOT			= 93,
+	UART1_CLK_ROOT			= 94,
+	UART2_CLK_ROOT			= 95,
+	UART3_CLK_ROOT			= 96,
+	UART4_CLK_ROOT			= 97,
+	USB_CORE_REF_CLK_ROOT		= 98,
+	USB_PHY_REF_CLK_ROOT		= 99,
+	GIC_CLK_ROOT			= 100,
+	ECSPI1_CLK_ROOT			= 101,
+	ECSPI2_CLK_ROOT			= 102,
+	PWM1_CLK_ROOT			= 103,
+	PWM2_CLK_ROOT			= 104,
+	PWM3_CLK_ROOT			= 105,
+	PWM4_CLK_ROOT			= 106,
+	GPT1_CLK_ROOT			= 107,
+	GPT2_CLK_ROOT			= 108,
+	GPT3_CLK_ROOT			= 109,
+	GPT4_CLK_ROOT			= 110,
+	GPT5_CLK_ROOT			= 111,
+	GPT6_CLK_ROOT			= 112,
+	TRACE_CLK_ROOT			= 113,
+	WDOG_CLK_ROOT			= 114,
+	WRCLK_CLK_ROOT			= 115,
+	IPP_DO_CLKO1			= 116,
+	IPP_DO_CLKO2			= 117,
+	MIPI_DSI_CORE_CLK_ROOT		= 118,
+	MIPI_DSI_PHY_REF_CLK_ROOT	= 119,
+	MIPI_DSI_DBI_CLK_ROOT		= 120,
+	OLD_MIPI_DSI_ESC_CLK_ROOT	= 121,
+	MIPI_CSI1_CORE_CLK_ROOT		= 122,
+	MIPI_CSI1_PHY_REF_CLK_ROOT	= 123,
+	MIPI_CSI1_ESC_CLK_ROOT		= 124,
+	MIPI_CSI2_CORE_CLK_ROOT		= 125,
+	MIPI_CSI2_PHY_REF_CLK_ROOT	= 126,
+	MIPI_CSI2_ESC_CLK_ROOT		= 127,
+	PCIE2_CTRL_CLK_ROOT		= 128,
+	PCIE2_PHY_CLK_ROOT		= 129,
+	PCIE2_AUX_CLK_ROOT		= 130,
+	ECSPI3_CLK_ROOT			= 131,
+	OLD_MIPI_DSI_ESC_RX_ROOT	= 132,
+	DISPLAY_HDMI_CLK_ROOT		= 133,
+	CLK_ROOT_MAX,
+};
+
+enum clk_root_src {
+	OSC_25M_CLK,
+	ARM_PLL_CLK,
+	DRAM_PLL1_CLK,
+	VIDEO_PLL2_CLK,
+	VPU_PLL_CLK,
+	GPU_PLL_CLK,
+	SYSTEM_PLL1_800M_CLK,
+	SYSTEM_PLL1_400M_CLK,
+	SYSTEM_PLL1_266M_CLK,
+	SYSTEM_PLL1_200M_CLK,
+	SYSTEM_PLL1_160M_CLK,
+	SYSTEM_PLL1_133M_CLK,
+	SYSTEM_PLL1_100M_CLK,
+	SYSTEM_PLL1_80M_CLK,
+	SYSTEM_PLL1_40M_CLK,
+	SYSTEM_PLL2_1000M_CLK,
+	SYSTEM_PLL2_500M_CLK,
+	SYSTEM_PLL2_333M_CLK,
+	SYSTEM_PLL2_250M_CLK,
+	SYSTEM_PLL2_200M_CLK,
+	SYSTEM_PLL2_166M_CLK,
+	SYSTEM_PLL2_125M_CLK,
+	SYSTEM_PLL2_100M_CLK,
+	SYSTEM_PLL2_50M_CLK,
+	SYSTEM_PLL3_CLK,
+	AUDIO_PLL1_CLK,
+	AUDIO_PLL2_CLK,
+	VIDEO_PLL_CLK,
+	OSC_32K_CLK,
+	EXT_CLK_1,
+	EXT_CLK_2,
+	EXT_CLK_3,
+	EXT_CLK_4,
+	OSC_27M_CLK,
+};
+
+/* CCGR index */
+enum clk_ccgr_index {
+	CCGR_DVFS = 0,
+	CCGR_ANAMIX = 1,
+	CCGR_CPU = 2,
+	CCGR_CSU = 4,
+	CCGR_DRAM1 = 5,
+	CCGR_DRAM2_OBSOLETE = 6,
+	CCGR_ECSPI1 = 7,
+	CCGR_ECSPI2 = 8,
+	CCGR_ECSPI3 = 9,
+	CCGR_ENET1 = 10,
+	CCGR_GPIO1 = 11,
+	CCGR_GPIO2 = 12,
+	CCGR_GPIO3 = 13,
+	CCGR_GPIO4 = 14,
+	CCGR_GPIO5 = 15,
+	CCGR_GPT1 = 16,
+	CCGR_GPT2 = 17,
+	CCGR_GPT3 = 18,
+	CCGR_GPT4 = 19,
+	CCGR_GPT5 = 20,
+	CCGR_GPT6 = 21,
+	CCGR_HS = 22,
+	CCGR_I2C1 = 23,
+	CCGR_I2C2 = 24,
+	CCGR_I2C3 = 25,
+	CCGR_I2C4 = 26,
+	CCGR_IOMUX = 27,
+	CCGR_IOMUX1 = 28,
+	CCGR_IOMUX2 = 29,
+	CCGR_IOMUX3 = 30,
+	CCGR_IOMUX4 = 31,
+	CCGR_M4 = 32,
+	CCGR_MU = 33,
+	CCGR_OCOTP = 34,
+	CCGR_OCRAM = 35,
+	CCGR_OCRAM_S = 36,
+	CCGR_PCIE = 37,
+	CCGR_PERFMON1 = 38,
+	CCGR_PERFMON2 = 39,
+	CCGR_PWM1 = 40,
+	CCGR_PWM2 = 41,
+	CCGR_PWM3 = 42,
+	CCGR_PWM4 = 43,
+	CCGR_QOS = 44,
+	CCGR_DISMIX = 45,
+	CCGR_MEGAMIX = 46,
+	CCGR_QSPI = 47,
+	CCGR_RAWNAND = 48,
+	CCGR_RDC = 49,
+	CCGR_ROM = 50,
+	CCGR_SAI1 = 51,
+	CCGR_SAI2 = 52,
+	CCGR_SAI3 = 53,
+	CCGR_SAI4 = 54,
+	CCGR_SAI5 = 55,
+	CCGR_SAI6 = 56,
+	CCGR_SCTR = 57,
+	CCGR_SDMA1 = 58,
+	CCGR_SDMA2 = 59,
+	CCGR_SEC_DEBUG = 60,
+	CCGR_SEMA1 = 61,
+	CCGR_SEMA2 = 62,
+	CCGR_SIM_DISPLAY = 63,
+	CCGR_SIM_ENET = 64,
+	CCGR_SIM_M = 65,
+	CCGR_SIM_MAIN = 66,
+	CCGR_SIM_S = 67,
+	CCGR_SIM_WAKEUP = 68,
+	CCGR_SIM_USB = 69,
+	CCGR_SIM_VPU = 70,
+	CCGR_SNVS = 71,
+	CCGR_TRACE = 72,
+	CCGR_UART1 = 73,
+	CCGR_UART2 = 74,
+	CCGR_UART3 = 75,
+	CCGR_UART4 = 76,
+	CCGR_USB_CTRL1 = 77,
+	CCGR_USB_CTRL2 = 78,
+	CCGR_USB_PHY1 = 79,
+	CCGR_USB_PHY2 = 80,
+	CCGR_USDHC1 = 81,
+	CCGR_USDHC2 = 82,
+	CCGR_WDOG1 = 83,
+	CCGR_WDOG2 = 84,
+	CCGR_WDOG3 = 85,
+	CCGR_VA53 = 86,
+	CCGR_GPU = 87,
+	CCGR_HEVC = 88,
+	CCGR_AVC = 89,
+	CCGR_VP9 = 90,
+	CCGR_HEVC_INTER = 91,
+	CCGR_GIC = 92,
+	CCGR_DISPLAY = 93,
+	CCGR_HDMI = 94,
+	CCGR_HDMI_PHY = 95,
+	CCGR_XTAL = 96,
+	CCGR_PLL = 97,
+	CCGR_TSENSOR = 98,
+	CCGR_VPU_DEC = 99,
+	CCGR_PCIE2 = 100,
+	CCGR_MIPI_CSI1 = 101,
+	CCGR_MIPI_CSI2 = 102,
+	CCGR_MAX,
+};
+
+/* src index */
+enum clk_src_index {
+	CLK_SRC_CKIL_SYNC_REQ = 0,
+	CLK_SRC_ARM_PLL_EN = 1,
+	CLK_SRC_GPU_PLL_EN = 2,
+	CLK_SRC_VPU_PLL_EN = 3,
+	CLK_SRC_DRAM_PLL_EN = 4,
+	CLK_SRC_SYSTEM_PLL1_EN = 5,
+	CLK_SRC_SYSTEM_PLL2_EN = 6,
+	CLK_SRC_SYSTEM_PLL3_EN = 7,
+	CLK_SRC_AUDIO_PLL1_EN = 8,
+	CLK_SRC_AUDIO_PLL2_EN = 9,
+	CLK_SRC_VIDEO_PLL1_EN = 10,
+	CLK_SRC_VIDEO_PLL2_EN = 11,
+	CLK_SRC_ARM_PLL = 12,
+	CLK_SRC_GPU_PLL = 13,
+	CLK_SRC_VPU_PLL = 14,
+	CLK_SRC_DRAM_PLL = 15,
+	CLK_SRC_SYSTEM_PLL1_800M = 16,
+	CLK_SRC_SYSTEM_PLL1_400M = 17,
+	CLK_SRC_SYSTEM_PLL1_266M = 18,
+	CLK_SRC_SYSTEM_PLL1_200M = 19,
+	CLK_SRC_SYSTEM_PLL1_160M = 20,
+	CLK_SRC_SYSTEM_PLL1_133M = 21,
+	CLK_SRC_SYSTEM_PLL1_100M = 22,
+	CLK_SRC_SYSTEM_PLL1_80M = 23,
+	CLK_SRC_SYSTEM_PLL1_40M = 24,
+	CLK_SRC_SYSTEM_PLL2_1000M = 25,
+	CLK_SRC_SYSTEM_PLL2_500M = 26,
+	CLK_SRC_SYSTEM_PLL2_333M = 27,
+	CLK_SRC_SYSTEM_PLL2_250M = 28,
+	CLK_SRC_SYSTEM_PLL2_200M = 29,
+	CLK_SRC_SYSTEM_PLL2_166M = 30,
+	CLK_SRC_SYSTEM_PLL2_125M = 31,
+	CLK_SRC_SYSTEM_PLL2_100M = 32,
+	CLK_SRC_SYSTEM_PLL2_50M = 33,
+	CLK_SRC_SYSTEM_PLL3 = 34,
+	CLK_SRC_AUDIO_PLL1 = 35,
+	CLK_SRC_AUDIO_PLL2 = 36,
+	CLK_SRC_VIDEO_PLL1 = 37,
+	CLK_SRC_VIDEO_PLL2 = 38,
+	CLK_SRC_OSC_25M = 39,
+	CLK_SRC_OSC_27M = 40,
+};
+
+enum root_pre_div {
+	CLK_ROOT_PRE_DIV1 = 0,
+	CLK_ROOT_PRE_DIV2,
+	CLK_ROOT_PRE_DIV3,
+	CLK_ROOT_PRE_DIV4,
+	CLK_ROOT_PRE_DIV5,
+	CLK_ROOT_PRE_DIV6,
+	CLK_ROOT_PRE_DIV7,
+	CLK_ROOT_PRE_DIV8,
+};
+
+enum root_post_div {
+	CLK_ROOT_POST_DIV1 = 0,
+	CLK_ROOT_POST_DIV2,
+	CLK_ROOT_POST_DIV3,
+	CLK_ROOT_POST_DIV4,
+	CLK_ROOT_POST_DIV5,
+	CLK_ROOT_POST_DIV6,
+	CLK_ROOT_POST_DIV7,
+	CLK_ROOT_POST_DIV8,
+	CLK_ROOT_POST_DIV9,
+	CLK_ROOT_POST_DIV10,
+	CLK_ROOT_POST_DIV11,
+	CLK_ROOT_POST_DIV12,
+	CLK_ROOT_POST_DIV13,
+	CLK_ROOT_POST_DIV14,
+	CLK_ROOT_POST_DIV15,
+	CLK_ROOT_POST_DIV16,
+	CLK_ROOT_POST_DIV17,
+	CLK_ROOT_POST_DIV18,
+	CLK_ROOT_POST_DIV19,
+	CLK_ROOT_POST_DIV20,
+	CLK_ROOT_POST_DIV21,
+	CLK_ROOT_POST_DIV22,
+	CLK_ROOT_POST_DIV23,
+	CLK_ROOT_POST_DIV24,
+	CLK_ROOT_POST_DIV25,
+	CLK_ROOT_POST_DIV26,
+	CLK_ROOT_POST_DIV27,
+	CLK_ROOT_POST_DIV28,
+	CLK_ROOT_POST_DIV29,
+	CLK_ROOT_POST_DIV30,
+	CLK_ROOT_POST_DIV31,
+	CLK_ROOT_POST_DIV32,
+	CLK_ROOT_POST_DIV33,
+	CLK_ROOT_POST_DIV34,
+	CLK_ROOT_POST_DIV35,
+	CLK_ROOT_POST_DIV36,
+	CLK_ROOT_POST_DIV37,
+	CLK_ROOT_POST_DIV38,
+	CLK_ROOT_POST_DIV39,
+	CLK_ROOT_POST_DIV40,
+	CLK_ROOT_POST_DIV41,
+	CLK_ROOT_POST_DIV42,
+	CLK_ROOT_POST_DIV43,
+	CLK_ROOT_POST_DIV44,
+	CLK_ROOT_POST_DIV45,
+	CLK_ROOT_POST_DIV46,
+	CLK_ROOT_POST_DIV47,
+	CLK_ROOT_POST_DIV48,
+	CLK_ROOT_POST_DIV49,
+	CLK_ROOT_POST_DIV50,
+	CLK_ROOT_POST_DIV51,
+	CLK_ROOT_POST_DIV52,
+	CLK_ROOT_POST_DIV53,
+	CLK_ROOT_POST_DIV54,
+	CLK_ROOT_POST_DIV55,
+	CLK_ROOT_POST_DIV56,
+	CLK_ROOT_POST_DIV57,
+	CLK_ROOT_POST_DIV58,
+	CLK_ROOT_POST_DIV59,
+	CLK_ROOT_POST_DIV60,
+	CLK_ROOT_POST_DIV61,
+	CLK_ROOT_POST_DIV62,
+	CLK_ROOT_POST_DIV63,
+	CLK_ROOT_POST_DIV64,
+};
+
+struct clk_root_map {
+	enum clk_root_index entry;
+	enum clk_slice_type slice_type;
+	u32 slice_index;
+	u8 src_mux[8];
+};
+
+struct ccm_ccgr {
+	u32 ccgr;
+	u32 ccgr_set;
+	u32 ccgr_clr;
+	u32 ccgr_tog;
+};
+
+struct ccm_root {
+	u32 target_root;
+	u32 target_root_set;
+	u32 target_root_clr;
+	u32 target_root_tog;
+	u32 misc;
+	u32 misc_set;
+	u32 misc_clr;
+	u32 misc_tog;
+	u32 nm_post;
+	u32 nm_post_root_set;
+	u32 nm_post_root_clr;
+	u32 nm_post_root_tog;
+	u32 nm_pre;
+	u32 nm_pre_root_set;
+	u32 nm_pre_root_clr;
+	u32 nm_pre_root_tog;
+	u32 db_post;
+	u32 db_post_root_set;
+	u32 db_post_root_clr;
+	u32 db_post_root_tog;
+	u32 db_pre;
+	u32 db_pre_root_set;
+	u32 db_pre_root_clr;
+	u32 db_pre_root_tog;
+	u32 reserved[4];
+	u32 access_ctrl;
+	u32 access_ctrl_root_set;
+	u32 access_ctrl_root_clr;
+	u32 access_ctrl_root_tog;
+};
+
+struct ccm_reg {
+	u32 reserved_0[4096];
+	struct ccm_ccgr ccgr_array[192];
+	u32 reserved_1[3328];
+	struct ccm_root core_root[5];
+	u32 reserved_2[352];
+	struct ccm_root bus_root[12];
+	u32 reserved_3[128];
+	struct ccm_root ahb_ipg_root[4];
+	u32 reserved_4[384];
+	struct ccm_root dram_sel;
+	struct ccm_root core_sel;
+	u32 reserved_5[448];
+	struct ccm_root ip_root[78];
+};
+
+#define CCGR_CLK_ON_MASK	0x03
+#define CLK_SRC_ON_MASK		0x03
+
+#define CLK_ROOT_ON		BIT(28)
+#define CLK_ROOT_OFF		(0 << 28)
+#define CLK_ROOT_ENABLE_MASK	BIT(28)
+#define CLK_ROOT_ENABLE_SHIFT	28
+#define CLK_ROOT_SOURCE_SEL(n)	(((n) & 0x7) << 24)
+
+/* For SEL, only use 1 bit */
+#define CLK_ROOT_SRC_MUX_MASK	0x07000000
+#define CLK_ROOT_SRC_MUX_SHIFT	24
+#define CLK_ROOT_SRC_0		0x00000000
+#define CLK_ROOT_SRC_1		0x01000000
+#define CLK_ROOT_SRC_2		0x02000000
+#define CLK_ROOT_SRC_3		0x03000000
+#define CLK_ROOT_SRC_4		0x04000000
+#define CLK_ROOT_SRC_5		0x05000000
+#define CLK_ROOT_SRC_6		0x06000000
+#define CLK_ROOT_SRC_7		0x07000000
+
+#define CLK_ROOT_PRE_DIV_MASK	(0x00070000)
+#define CLK_ROOT_PRE_DIV_SHIFT	16
+#define CLK_ROOT_PRE_DIV(n)	(((n) << 16) & 0x00070000)
+
+#define CLK_ROOT_AUDO_SLOW_EN	0x1000
+
+#define CLK_ROOT_AUDO_DIV_MASK	0x700
+#define CLK_ROOT_AUDO_DIV_SHIFT	0x8
+#define CLK_ROOT_AUDO_DIV(n)	(((n) << 8) & 0x700)
+
+/* For CORE: mask is 0x7; For IPG: mask is 0x3 */
+#define CLK_ROOT_POST_DIV_MASK		0x3f
+#define CLK_ROOT_CORE_POST_DIV_MASK	0x7
+#define CLK_ROOT_IPG_POST_DIV_MASK	0x3
+#define CLK_ROOT_POST_DIV_SHIFT		0
+#define CLK_ROOT_POST_DIV(n)		((n) & 0x3f)
+
+/* AUDIO PLL1/2 VIDEO PLL1 GPU PLL VPU PLL ARM PLL*/
+#define FRAC_PLL_LOCK_MASK		BIT(31)
+#define FRAC_PLL_CLKE_MASK		BIT(21)
+#define FRAC_PLL_PD_MASK		BIT(19)
+#define FRAC_PLL_REFCLK_SEL_MASK	BIT(16)
+#define FRAC_PLL_LOCK_SEL_MASK		BIT(15)
+#define FRAC_PLL_BYPASS_MASK		BIT(14)
+#define FRAC_PLL_COUNTCLK_SEL_MASK	BIT(13)
+#define FRAC_PLL_NEWDIV_VAL_MASK	BIT(12)
+#define FRAC_PLL_NEWDIV_ACK_MASK	BIT(11)
+#define FRAC_PLL_REFCLK_DIV_VAL(n)	(((n) << 5) & (0x3f << 5))
+#define FRAC_PLL_REFCLK_DIV_VAL_MASK	(0x3f << 5)
+#define FRAC_PLL_REFCLK_DIV_VAL_SHIFT	5
+#define FRAC_PLL_OUTPUT_DIV_VAL_MASK	0x1f
+#define FRAC_PLL_OUTPUT_DIV_VAL(n)	((n) & 0x1f)
+
+#define FRAC_PLL_REFCLK_SEL_OSC_25M	(0 << 16)
+#define FRAC_PLL_REFCLK_SEL_OSC_27M	BIT(16)
+#define FRAC_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16)
+#define FRAC_PLL_REFCLK_SEL_CLK_PN	(3 << 16)
+
+#define FRAC_PLL_FRAC_DIV_CTL_MASK	(0x1ffffff << 7)
+#define FRAC_PLL_FRAC_DIV_CTL_SHIFT	7
+#define FRAC_PLL_INT_DIV_CTL_MASK	0x7f
+#define FRAC_PLL_INT_DIV_CTL_VAL(n)	((n) & 0x7f)
+
+/* SYS PLL1/2/3 VIDEO PLL2 DRAM PLL */
+#define SSCG_PLL_LOCK_MASK		BIT(31)
+#define SSCG_PLL_CLKE_MASK		BIT(25)
+#define SSCG_PLL_DIV2_CLKE_MASK		BIT(23)
+#define SSCG_PLL_DIV3_CLKE_MASK		BIT(21)
+#define SSCG_PLL_DIV4_CLKE_MASK		BIT(19)
+#define SSCG_PLL_DIV5_CLKE_MASK		BIT(17)
+#define SSCG_PLL_DIV6_CLKE_MASK		BIT(15)
+#define SSCG_PLL_DIV8_CLKE_MASK		BIT(13)
+#define SSCG_PLL_DIV10_CLKE_MASK	BIT(11)
+#define SSCG_PLL_DIV20_CLKE_MASK	BIT(9)
+#define SSCG_PLL_VIDEO_PLL2_CLKE_MASK	BIT(9)
+#define SSCG_PLL_DRAM_PLL_CLKE_MASK	BIT(9)
+#define SSCG_PLL_PLL3_CLKE_MASK		BIT(9)
+#define SSCG_PLL_PD_MASK		BIT(7)
+#define SSCG_PLL_BYPASS1_MASK		BIT(5)
+#define SSCG_PLL_BYPASS2_MASK		BIT(4)
+#define SSCG_PLL_LOCK_SEL_MASK		BIT(3)
+#define SSCG_PLL_COUNTCLK_SEL_MASK	BIT(2)
+#define SSCG_PLL_REFCLK_SEL_MASK	0x3
+#define SSCG_PLL_REFCLK_SEL_OSC_25M	(0 << 16)
+#define SSCG_PLL_REFCLK_SEL_OSC_27M	BIT(16)
+#define SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16)
+#define SSCG_PLL_REFCLK_SEL_CLK_PN	(3 << 16)
+
+#define SSCG_PLL_SSDS_MASK		BIT(8)
+#define SSCG_PLL_SSMD_MASK		(0x7 << 5)
+#define SSCG_PLL_SSMF_MASK		(0xf << 1)
+#define SSCG_PLL_SSE_MASK		0x1
+
+#define SSCG_PLL_REF_DIVR1_MASK		(0x7 << 25)
+#define SSCG_PLL_REF_DIVR1_SHIFT	25
+#define SSCG_PLL_REF_DIVR1_VAL(n)	(((n) << 25) & SSCG_PLL_REF_DIVR1_MASK)
+#define SSCG_PLL_REF_DIVR2_MASK		(0x3f << 19)
+#define SSCG_PLL_REF_DIVR2_SHIFT	19
+#define SSCG_PLL_REF_DIVR2_VAL(n)	(((n) << 19) & SSCG_PLL_REF_DIVR2_MASK)
+#define SSCG_PLL_FEEDBACK_DIV_F1_MASK	(0x3f << 13)
+#define SSCG_PLL_FEEDBACK_DIV_F1_SHIFT	13
+#define SSCG_PLL_FEEDBACK_DIV_F1_VAL(n)	(((n) << 13) & \
+					 SSCG_PLL_FEEDBACK_DIV_F1_MASK)
+#define SSCG_PLL_FEEDBACK_DIV_F2_MASK	(0x3f << 7)
+#define SSCG_PLL_FEEDBACK_DIV_F2_SHIFT	7
+#define SSCG_PLL_FEEDBACK_DIV_F2_VAL(n)	(((n) << 7) & \
+					 SSCG_PLL_FEEDBACK_DIV_F2_MASK)
+#define SSCG_PLL_OUTPUT_DIV_VAL_MASK	(0x3f << 1)
+#define SSCG_PLL_OUTPUT_DIV_VAL_SHIFT	1
+#define SSCG_PLL_OUTPUT_DIV_VAL(n)	(((n) << 1) & \
+					 SSCG_PLL_OUTPUT_DIV_VAL_MASK)
+#define SSCG_PLL_FILTER_RANGE_MASK	0x1
+
+#define HW_DIGPROG_MAJOR_UPPER_MASK	(0xff << 16)
+#define HW_DIGPROG_MAJOR_LOWER_MASK	(0xff << 8)
+#define HW_DIGPROG_MINOR_MASK		0xff
+
+#define HW_OSC_27M_CLKE_MASK		BIT(4)
+#define HW_OSC_25M_CLKE_MASK		BIT(2)
+#define HW_OSC_32K_SEL_MASK		0x1
+#define HW_OSC_32K_SEL_RTC		0x1
+#define HW_OSC_32K_SEL_25M_DIV800	0x0
+
+#define HW_FRAC_ARM_PLL_DIV_MASK	(0x7 << 20)
+#define HW_FRAC_ARM_PLL_DIV_SHIFT	20
+#define HW_FRAC_VPU_PLL_DIV_MASK	(0x7 << 16)
+#define HW_FRAC_VPU_PLL_DIV_SHIFT	16
+#define HW_FRAC_GPU_PLL_DIV_MASK	(0x7 << 12)
+#define HW_FRAC_GPU_PLL_DIV_SHIFT	12
+#define HW_FRAC_VIDEO_PLL1_DIV_MASK	(0x7 << 10)
+#define HW_FRAC_VIDEO_PLL1_DIV_SHIFT	10
+#define HW_FRAC_AUDIO_PLL2_DIV_MASK	(0x7 << 4)
+#define HW_FRAC_AUDIO_PLL2_DIV_SHIFT	4
+#define HW_FRAC_AUDIO_PLL1_DIV_MASK	0x7
+#define HW_FRAC_AUDIO_PLL1_DIV_SHIFT	0
+
+#define HW_SSCG_VIDEO_PLL2_DIV_MASK	(0x7 << 16)
+#define HW_SSCG_VIDEO_PLL2_DIV_SHIFT	16
+#define HW_SSCG_DRAM_PLL_DIV_MASK	(0x7 << 14)
+#define HW_SSCG_DRAM_PLL_DIV_SHIFT	14
+#define HW_SSCG_SYSTEM_PLL3_DIV_MASK	(0x7 << 8)
+#define HW_SSCG_SYSTEM_PLL3_DIV_SHIFT	8
+#define HW_SSCG_SYSTEM_PLL2_DIV_MASK	(0x7 << 4)
+#define HW_SSCG_SYSTEM_PLL2_DIV_SHIFT	4
+#define HW_SSCG_SYSTEM_PLL1_DIV_MASK	0x7
+#define HW_SSCG_SYSTEM_PLL1_DIV_SHIFT	0
+
+#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK		0x01000000
+#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK		0x02000000
+#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK		0x03000000
+#define ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK			0x07000000
+#define ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M			0x01000000
+#define ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK		0x01000000
+#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK	0x01000000
+
+enum enet_freq {
+	ENET_25MHZ = 0,
+	ENET_50MHZ,
+	ENET_125MHZ,
+};
+
+enum frac_pll_out_val {
+	FRAC_PLL_OUT_1000M,
+	FRAC_PLL_OUT_1600M,
+};
+
+u32 imx_get_fecclk(void);
+u32 imx_get_uartclk(void);
+int clock_init(void);
+void init_clk_usdhc(u32 index);
+void init_uart_clk(u32 index);
+void init_wdog_clk(void);
+unsigned int mxc_get_clock(enum clk_root_index clk);
+int clock_enable(enum clk_ccgr_index index, bool enable);
+int clock_root_enabled(enum clk_root_index clock_id);
+int clock_root_cfg(enum clk_root_index clock_id, enum root_pre_div pre_div,
+		   enum root_post_div post_div, enum clk_root_src clock_src);
+int clock_set_target_val(enum clk_root_index clock_id, u32 val);
+int clock_get_target_val(enum clk_root_index clock_id, u32 *val);
+int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div);
+int clock_get_postdiv(enum clk_root_index clock_id,
+		      enum root_post_div *post_div);
+int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src);
+void mxs_set_lcdclk(u32 base_addr, u32 freq);
+int set_clk_qspi(void);
+void enable_ocotp_clk(unsigned char enable);
+int enable_i2c_clk(unsigned char enable, unsigned int i2c_num);
+int set_clk_enet(enum enet_freq type);
+#endif

arch/arm/include/asm/arch-mx8m/crm_regs.h

@@ -0,0 +1,10 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_MX8M_CRM_REGS_H
+#define _ASM_ARCH_MX8M_CRM_REGS_H
+/* Dummy header, some imx-common code needs this file */
+#endif

arch/arm/include/asm/arch-mx8m/ddr.h

@@ -0,0 +1,356 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_MX8M_DDR_H
+#define __ASM_ARCH_MX8M_DDR_H
+
+#define DDRC_DDR_SS_GPR0		0x3d000000
+#define DDRC_IPS_BASE_ADDR_0		0x3f400000
+#define IP2APB_DDRPHY_IPS_BASE_ADDR(X)	(0x3c000000 + (X * 0x2000000))
+#define DDRPHY_MEM(X)			(0x3c000000 + (X * 0x2000000) + 0x50000)
+
+struct ddrc_freq {
+	u32 res0[8];
+	u32 derateen;
+	u32 derateint;
+	u32 res1[10];
+	u32 rfshctl0;
+	u32 res2[4];
+	u32 rfshtmg;
+	u32 rfshtmg1;
+	u32 res3[28];
+	u32 init3;
+	u32 init4;
+	u32 res;
+	u32 init6;
+	u32 init7;
+	u32 res4[4];
+	u32 dramtmg0;
+	u32 dramtmg1;
+	u32 dramtmg2;
+	u32 dramtmg3;
+	u32 dramtmg4;
+	u32 dramtmg5;
+	u32 dramtmg6;
+	u32 dramtmg7;
+	u32 dramtmg8;
+	u32 dramtmg9;
+	u32 dramtmg10;
+	u32 dramtmg11;
+	u32 dramtmg12;
+	u32 dramtmg13;
+	u32 dramtmg14;
+	u32 dramtmg15;
+	u32 dramtmg16;
+	u32 dramtmg17;
+	u32 res5[10];
+	u32 mramtmg0;
+	u32 mramtmg1;
+	u32 mramtmg4;
+	u32 mramtmg9;
+	u32 zqctl0;
+	u32 res6[3];
+	u32 dfitmg0;
+	u32 dfitmg1;
+	u32 res7[7];
+	u32 dfitmg2;
+	u32 dfitmg3;
+	u32 res8[33];
+	u32 odtcfg;
+};
+
+struct imx8m_ddrc_regs {
+	u32 mstr;
+	u32 stat;
+	u32 mstr1;
+	u32 res1;
+	u32 mrctrl0;
+	u32 mrctrl1;
+	u32 mrstat;
+	u32 mrctrl2;
+	u32 derateen;
+	u32 derateint;
+	u32 mstr2;
+	u32 res2;
+	u32 pwrctl;
+	u32 pwrtmg;
+	u32 hwlpctl;
+	u32 hwffcctl;
+	u32 hwffcstat;
+	u32 res3[3];
+	u32 rfshctl0;
+	u32 rfshctl1;
+	u32 rfshctl2;
+	u32 rfshctl4;
+	u32 rfshctl3;
+	u32 rfshtmg;
+	u32 rfshtmg1;
+	u32 res4;
+	u32 ecccfg0;
+	u32 ecccfg1;
+	u32 eccstat;
+	u32 eccclr;
+	u32 eccerrcnt;
+	u32 ecccaddr0;
+	u32 ecccaddr1;
+	u32 ecccsyn0;
+	u32 ecccsyn1;
+	u32 ecccsyn2;
+	u32 eccbitmask0;
+	u32 eccbitmask1;
+	u32 eccbitmask2;
+	u32 eccuaddr0;
+	u32 eccuaddr1;
+	u32 eccusyn0;
+	u32 eccusyn1;
+	u32 eccusyn2;
+	u32 eccpoisonaddr0;
+	u32 eccpoisonaddr1;
+	u32 crcparctl0;
+	u32 crcparctl1;
+	u32 crcparctl2;
+	u32 crcparstat;
+	u32 init0;
+	u32 init1;
+	u32 init2;
+	u32 init3;
+	u32 init4;
+	u32 init5;
+	u32 init6;
+	u32 init7;
+	u32 dimmctl;
+	u32 rankctl;
+	u32 res5;
+	u32 chctl;
+	u32 dramtmg0;
+	u32 dramtmg1;
+	u32 dramtmg2;
+	u32 dramtmg3;
+	u32 dramtmg4;
+	u32 dramtmg5;
+	u32 dramtmg6;
+	u32 dramtmg7;
+	u32 dramtmg8;
+	u32 dramtmg9;
+	u32 dramtmg10;
+	u32 dramtmg11;
+	u32 dramtmg12;
+	u32 dramtmg13;
+	u32 dramtmg14;
+	u32 dramtmg15;
+	u32 dramtmg16;
+	u32 dramtmg17;
+	u32 res6[10];
+	u32 mramtmg0;
+	u32 mramtmg1;
+	u32 mramtmg4;
+	u32 mramtmg9;
+	u32 zqctl0;
+	u32 zqctl1;
+	u32 zqctl2;
+	u32 zqstat;
+	u32 dfitmg0;
+	u32 dfitmg1;
+	u32 dfilpcfg0;
+	u32 dfilpcfg1;
+	u32 dfiupd0;
+	u32 dfiupd1;
+	u32 dfiupd2;
+	u32 res7;
+	u32 dfimisc;
+	u32 dfitmg2;
+	u32 dfitmg3;
+	u32 dfistat;
+	u32 dbictl;
+	u32 dfiphymstr;
+	u32 res8[14];
+	u32 addrmap0;
+	u32 addrmap1;
+	u32 addrmap2;
+	u32 addrmap3;
+	u32 addrmap4;
+	u32 addrmap5;
+	u32 addrmap6;
+	u32 addrmap7;
+	u32 addrmap8;
+	u32 addrmap9;
+	u32 addrmap10;
+	u32 addrmap11;
+	u32 res9[4];
+	u32 odtcfg;
+	u32 odtmap;
+	u32 res10[2];
+	u32 sched;
+	u32 sched1;
+	u32 sched2;
+	u32 perfhpr1;
+	u32 res11;
+	u32 perflpr1;
+	u32 res12;
+	u32 perfwr1;
+	u32 res13[4];
+	u32 dqmap0;
+	u32 dqmap1;
+	u32 dqmap2;
+	u32 dqmap3;
+	u32 dqmap4;
+	u32 dqmap5;
+	u32 res14[26];
+	u32 dbg0;
+	u32 dbg1;
+	u32 dbgcam;
+	u32 dbgcmd;
+	u32 dbgstat;
+	u32 res15[3];
+	u32 swctl;
+	u32 swstat;
+	u32 res16[2];
+	u32 ocparcfg0;
+	u32 ocparcfg1;
+	u32 ocparcfg2;
+	u32 ocparcfg3;
+	u32 ocparstat0;
+	u32 ocparstat1;
+	u32 ocparwlog0;
+	u32 ocparwlog1;
+	u32 ocparwlog2;
+	u32 ocparawlog0;
+	u32 ocparawlog1;
+	u32 ocparrlog0;
+	u32 ocparrlog1;
+	u32 ocpararlog0;
+	u32 ocpararlog1;
+	u32 poisoncfg;
+	u32 poisonstat;
+	u32 adveccindex;
+	union  {
+		u32 adveccstat;
+		u32 eccapstat;
+	};
+	u32 eccpoisonpat0;
+	u32 eccpoisonpat1;
+	u32 eccpoisonpat2;
+	u32 res17[6];
+	u32 caparpoisonctl;
+	u32 caparpoisonstat;
+	u32 res18[2];
+	u32 dynbsmstat;
+	u32 res19[18];
+	u32 pstat;
+	u32 pccfg;
+	struct {
+		u32 pcfgr;
+		u32 pcfgw;
+		u32 pcfgc;
+		struct {
+			u32 pcfgidmaskch0;
+			u32 pcfidvaluech0;
+		} pcfgid[16];
+		u32 pctrl;
+		u32 pcfgqos0;
+		u32 pcfgqos1;
+		u32 pcfgwqos0;
+		u32 pcfgwqos1;
+		u32 res[4];
+	} pcfg[16];
+	struct {
+		u32 sarbase;
+		u32 sarsize;
+	} sar[4];
+	u32 sbrctl;
+	u32 sbrstat;
+	u32 sbrwdata0;
+	u32 sbrwdata1;
+	u32 pdch;
+	u32 res20[755];
+	/* umctl2_regs_dch1 */
+	u32 ch1_stat;
+	u32 res21[2];
+	u32 ch1_mrctrl0;
+	u32 ch1_mrctrl1;
+	u32 ch1_mrstat;
+	u32 ch1_mrctrl2;
+	u32 res22[4];
+	u32 ch1_pwrctl;
+	u32 ch1_pwrtmg;
+	u32 ch1_hwlpctl;
+	u32 res23[15];
+	u32 ch1_eccstat;
+	u32 ch1_eccclr;
+	u32 ch1_eccerrcnt;
+	u32 ch1_ecccaddr0;
+	u32 ch1_ecccaddr1;
+	u32 ch1_ecccsyn0;
+	u32 ch1_ecccsyn1;
+	u32 ch1_ecccsyn2;
+	u32 ch1_eccbitmask0;
+	u32 ch1_eccbitmask1;
+	u32 ch1_eccbitmask2;
+	u32 ch1_eccuaddr0;
+	u32 ch1_eccuaddr1;
+	u32 ch1_eccusyn0;
+	u32 ch1_eccusyn1;
+	u32 ch1_eccusyn2;
+	u32 res24[2];
+	u32 ch1_crcparctl0;
+	u32 res25[2];
+	u32 ch1_crcparstat;
+	u32 res26[46];
+	u32 ch1_zqctl2;
+	u32 ch1_zqstat;
+	u32 res27[11];
+	u32 ch1_dfistat;
+	u32 res28[33];
+	u32 ch1_odtmap;
+	u32 res29[47];
+	u32 ch1_dbg1;
+	u32 ch1_dbgcam;
+	u32 ch1_dbgcmd;
+	u32 ch1_dbgstat;
+	u32 res30[123];
+	/* umctl2_regs_freq1 */
+	struct ddrc_freq freq1;
+	u32 res31[109];
+	/* umctl2_regs_addrmap_alt */
+	u32 addrmap0_alt;
+	u32 addrmap1_alt;
+	u32 addrmap2_alt;
+	u32 addrmap3_alt;
+	u32 addrmap4_alt;
+	u32 addrmap5_alt;
+	u32 addrmap6_alt;
+	u32 addrmap7_alt;
+	u32 addrmap8_alt;
+	u32 addrmap9_alt;
+	u32 addrmap10_alt;
+	u32 addrmap11_alt;
+	u32 res32[758];
+	/* umctl2_regs_freq2 */
+	struct ddrc_freq freq2;
+	u32 res33[879];
+	/* umctl2_regs_freq3 */
+	struct ddrc_freq freq3;
+};
+
+struct imx8m_ddrphy_regs {
+	u32 reg[0xf0000];
+};
+
+/* PHY State */
+enum pstate {
+	PS0,
+	PS1,
+	PS2,
+	PS3,
+};
+
+enum msg_response {
+	TRAIN_SUCCESS = 0x7,
+	TRAIN_STREAM_START = 0x8,
+	TRAIN_FAIL = 0xff,
+};
+
+#endif

arch/arm/include/asm/arch-mx8m/gpio.h

@@ -0,0 +1,12 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_MX8M_GPIO_H
+#define __ASM_ARCH_MX8M_GPIO_H
+
+#include <asm/mach-imx/gpio.h>
+
+#endif

arch/arm/include/asm/arch-mx8m/imx-regs.h

@@ -0,0 +1,468 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_MX8M_REGS_H__
+#define __ASM_ARCH_MX8M_REGS_H__
+
+#include <asm/mach-imx/regs-lcdif.h>
+
+#define ROM_VERSION_A0		0x800
+#define ROM_VERSION_B0		0x83C
+
+#define M4_BOOTROM_BASE_ADDR	0x007E0000
+
+#define SAI1_BASE_ADDR		0x30010000
+#define SAI6_BASE_ADDR		0x30030000
+#define SAI5_BASE_ADDR		0x30040000
+#define SAI4_BASE_ADDR		0x30050000
+#define SPBA2_BASE_ADDR		0x300F0000
+#define AIPS1_BASE_ADDR		0x301F0000
+#define GPIO1_BASE_ADDR		0X30200000
+#define GPIO2_BASE_ADDR		0x30210000
+#define GPIO3_BASE_ADDR		0x30220000
+#define GPIO4_BASE_ADDR		0x30230000
+#define GPIO5_BASE_ADDR		0x30240000
+#define ANA_TSENSOR_BASE_ADDR	0x30260000
+#define ANA_OSC_BASE_ADDR	0x30270000
+#define WDOG1_BASE_ADDR		0x30280000
+#define WDOG2_BASE_ADDR		0x30290000
+#define WDOG3_BASE_ADDR		0x302A0000
+#define SDMA2_BASE_ADDR		0x302C0000
+#define GPT1_BASE_ADDR		0x302D0000
+#define GPT2_BASE_ADDR		0x302E0000
+#define GPT3_BASE_ADDR		0x302F0000
+#define ROMCP_BASE_ADDR		0x30310000
+#define LCDIF_BASE_ADDR		0x30320000
+#define IOMUXC_BASE_ADDR	0x30330000
+#define IOMUXC_GPR_BASE_ADDR	0x30340000
+#define OCOTP_BASE_ADDR		0x30350000
+#define ANATOP_BASE_ADDR	0x30360000
+#define SNVS_HP_BASE_ADDR	0x30370000
+#define CCM_BASE_ADDR		0x30380000
+#define SRC_BASE_ADDR		0x30390000
+#define GPC_BASE_ADDR		0x303A0000
+#define SEMAPHORE1_BASE_ADDR	0x303B0000
+#define SEMAPHORE2_BASE_ADDR	0x303C0000
+#define RDC_BASE_ADDR		0x303D0000
+#define CSU_BASE_ADDR		0x303E0000
+
+#define AIPS2_BASE_ADDR		0x305F0000
+#define PWM1_BASE_ADDR		0x30660000
+#define PWM2_BASE_ADDR		0x30670000
+#define PWM3_BASE_ADDR		0x30680000
+#define PWM4_BASE_ADDR		0x30690000
+#define SYSCNT_RD_BASE_ADDR	0x306A0000
+#define SYSCNT_CMP_BASE_ADDR	0x306B0000
+#define SYSCNT_CTRL_BASE_ADDR	0x306C0000
+#define GPT6_BASE_ADDR		0x306E0000
+#define GPT5_BASE_ADDR		0x306F0000
+#define GPT4_BASE_ADDR		0x30700000
+#define PERFMON1_BASE_ADDR	0x307C0000
+#define PERFMON2_BASE_ADDR	0x307D0000
+#define QOSC_BASE_ADDR		0x307F0000
+
+#define SPDIF1_BASE_ADDR	0x30810000
+#define ECSPI1_BASE_ADDR	0x30820000
+#define ECSPI2_BASE_ADDR	0x30830000
+#define ECSPI3_BASE_ADDR	0x30840000
+#define UART1_BASE_ADDR		0x30860000
+#define UART3_BASE_ADDR		0x30880000
+#define UART2_BASE_ADDR		0x30890000
+#define SPDIF2_BASE_ADDR	0x308A0000
+#define SAI2_BASE_ADDR		0x308B0000
+#define SAI3_BASE_ADDR		0x308C0000
+#define SPBA1_BASE_ADDR		0x308F0000
+#define CAAM_BASE_ADDR		0x30900000
+#define AIPS3_BASE_ADDR		0x309F0000
+#define MIPI_PHY_BASE_ADDR	0x30A00000
+#define MIPI_DSI_BASE_ADDR	0x30A10000
+#define I2C1_BASE_ADDR		0x30A20000
+#define I2C2_BASE_ADDR		0x30A30000
+#define I2C3_BASE_ADDR		0x30A40000
+#define I2C4_BASE_ADDR		0x30A50000
+#define UART4_BASE_ADDR		0x30A60000
+#define MIPI_CSI_BASE_ADDR	0x30A70000
+#define MIPI_CSI_PHY1_BASE_ADDR	0x30A80000
+#define CSI1_BASE_ADDR		0x30A90000
+#define MU_A_BASE_ADDR		0x30AA0000
+#define MU_B_BASE_ADDR		0x30AB0000
+#define SEMAPHOR_HS_BASE_ADDR	0x30AC0000
+#define USDHC1_BASE_ADDR	0x30B40000
+#define USDHC2_BASE_ADDR	0x30B50000
+#define MIPI_CS2_BASE_ADDR	0x30B60000
+#define MIPI_CSI_PHY2_BASE_ADDR	0x30B70000
+#define CSI2_BASE_ADDR		0x30B80000
+#define QSPI0_BASE_ADDR		0x30BB0000
+#define QSPI0_AMBA_BASE		0x08000000
+#define SDMA1_BASE_ADDR		0x30BD0000
+#define ENET1_BASE_ADDR		0x30BE0000
+
+#define HDMI_CTRL_BASE_ADDR	0x32C00000
+#define AIPS4_BASE_ADDR		0x32DF0000
+#define DC1_BASE_ADDR		0x32E00000
+#define DC2_BASE_ADDR		0x32E10000
+#define DC3_BASE_ADDR		0x32E20000
+#define HDMI_SEC_BASE_ADDR	0x32E40000
+#define TZASC_BASE_ADDR		0x32F80000
+#define MTR_BASE_ADDR		0x32FB0000
+#define PLATFORM_CTRL_BASE_ADDR	0x32FE0000
+
+#define MXS_APBH_BASE		0x33000000
+#define MXS_GPMI_BASE		0x33002000
+#define MXS_BCH_BASE		0x33004000
+
+#define USB1_BASE_ADDR		0x38100000
+#define USB2_BASE_ADDR		0x38200000
+#define USB1_PHY_BASE_ADDR	0x381F0000
+#define USB2_PHY_BASE_ADDR	0x382F0000
+
+#define MXS_LCDIF_BASE		LCDIF_BASE_ADDR
+
+#define SRC_IPS_BASE_ADDR	0x30390000
+#define SRC_DDRC_RCR_ADDR	0x30391000
+#define SRC_DDRC2_RCR_ADDR	0x30391004
+
+#define DDRC_DDR_SS_GPR0	0x3d000000
+#define DDRC_IPS_BASE_ADDR(X)	(0x3d400000 + ((X) * 0x2000000))
+#define DDR_CSD1_BASE_ADDR	0x40000000
+
+#if !defined(__ASSEMBLY__)
+#include <asm/types.h>
+#include <linux/bitops.h>
+#include <stdbool.h>
+
+#define GPR_TZASC_EN		BIT(0)
+#define GPR_TZASC_EN_LOCK	BIT(16)
+
+#define SRC_SCR_M4_ENABLE_OFFSET	3
+#define SRC_SCR_M4_ENABLE_MASK		BIT(3)
+#define SRC_SCR_M4C_NON_SCLR_RST_OFFSET	0
+#define SRC_SCR_M4C_NON_SCLR_RST_MASK	BIT(0)
+#define SRC_DDR1_ENABLE_MASK		0x8F000000UL
+#define SRC_DDR2_ENABLE_MASK		0x8F000000UL
+#define SRC_DDR1_RCR_PHY_PWROKIN_N_MASK	BIT(3)
+#define SRC_DDR1_RCR_PHY_RESET_MASK	BIT(2)
+#define SRC_DDR1_RCR_CORE_RESET_N_MASK	BIT(1)
+#define SRC_DDR1_RCR_PRESET_N_MASK	BIT(0)
+
+struct iomuxc_gpr_base_regs {
+	u32 gpr[47];
+};
+
+struct ocotp_regs {
+	u32	ctrl;
+	u32	ctrl_set;
+	u32     ctrl_clr;
+	u32	ctrl_tog;
+	u32	timing;
+	u32     rsvd0[3];
+	u32     data;
+	u32     rsvd1[3];
+	u32     read_ctrl;
+	u32     rsvd2[3];
+	u32	read_fuse_data;
+	u32     rsvd3[3];
+	u32	sw_sticky;
+	u32     rsvd4[3];
+	u32     scs;
+	u32     scs_set;
+	u32     scs_clr;
+	u32     scs_tog;
+	u32     crc_addr;
+	u32     rsvd5[3];
+	u32     crc_value;
+	u32     rsvd6[3];
+	u32     version;
+	u32     rsvd7[0xdb];
+
+	/* fuse banks */
+	struct fuse_bank {
+		u32	fuse_regs[0x10];
+	} bank[0];
+};
+
+struct fuse_bank0_regs {
+	u32 lock;
+	u32 rsvd0[3];
+	u32 uid_low;
+	u32 rsvd1[3];
+	u32 uid_high;
+	u32 rsvd2[7];
+};
+
+struct fuse_bank1_regs {
+	u32 tester3;
+	u32 rsvd0[3];
+	u32 tester4;
+	u32 rsvd1[3];
+	u32 tester5;
+	u32 rsvd2[3];
+	u32 cfg0;
+	u32 rsvd3[3];
+};
+
+struct anamix_pll {
+	u32 audio_pll1_cfg0;
+	u32 audio_pll1_cfg1;
+	u32 audio_pll2_cfg0;
+	u32 audio_pll2_cfg1;
+	u32 video_pll_cfg0;
+	u32 video_pll_cfg1;
+	u32 gpu_pll_cfg0;
+	u32 gpu_pll_cfg1;
+	u32 vpu_pll_cfg0;
+	u32 vpu_pll_cfg1;
+	u32 arm_pll_cfg0;
+	u32 arm_pll_cfg1;
+	u32 sys_pll1_cfg0;
+	u32 sys_pll1_cfg1;
+	u32 sys_pll1_cfg2;
+	u32 sys_pll2_cfg0;
+	u32 sys_pll2_cfg1;
+	u32 sys_pll2_cfg2;
+	u32 sys_pll3_cfg0;
+	u32 sys_pll3_cfg1;
+	u32 sys_pll3_cfg2;
+	u32 video_pll2_cfg0;
+	u32 video_pll2_cfg1;
+	u32 video_pll2_cfg2;
+	u32 dram_pll_cfg0;
+	u32 dram_pll_cfg1;
+	u32 dram_pll_cfg2;
+	u32 digprog;
+	u32 osc_misc_cfg;
+	u32 pllout_monitor_cfg;
+	u32 frac_pllout_div_cfg;
+	u32 sscg_pllout_div_cfg;
+};
+
+struct fuse_bank9_regs {
+	u32 mac_addr0;
+	u32 rsvd0[3];
+	u32 mac_addr1;
+	u32 rsvd1[11];
+};
+
+/* System Reset Controller (SRC) */
+struct src {
+	u32 scr;
+	u32 a53rcr;
+	u32 a53rcr1;
+	u32 m4rcr;
+	u32 reserved1[4];
+	u32 usbophy1_rcr;
+	u32 usbophy2_rcr;
+	u32 mipiphy_rcr;
+	u32 pciephy_rcr;
+	u32 hdmi_rcr;
+	u32 disp_rcr;
+	u32 reserved2[2];
+	u32 gpu_rcr;
+	u32 vpu_rcr;
+	u32 pcie2_rcr;
+	u32 mipiphy1_rcr;
+	u32 mipiphy2_rcr;
+	u32 reserved3;
+	u32 sbmr1;
+	u32 srsr;
+	u32 reserved4[2];
+	u32 sisr;
+	u32 simr;
+	u32 sbmr2;
+	u32 gpr1;
+	u32 gpr2;
+	u32 gpr3;
+	u32 gpr4;
+	u32 gpr5;
+	u32 gpr6;
+	u32 gpr7;
+	u32 gpr8;
+	u32 gpr9;
+	u32 gpr10;
+	u32 reserved5[985];
+	u32 ddr1_rcr;
+	u32 ddr2_rcr;
+};
+
+struct gpc_reg {
+	u32 lpcr_bsc;
+	u32 lpcr_ad;
+	u32 lpcr_cpu1;
+	u32 lpcr_cpu2;
+	u32 lpcr_cpu3;
+	u32 slpcr;
+	u32 mst_cpu_mapping;
+	u32 mmdc_cpu_mapping;
+	u32 mlpcr;
+	u32 pgc_ack_sel;
+	u32 pgc_ack_sel_m4;
+	u32 gpc_misc;
+	u32 imr1_core0;
+	u32 imr2_core0;
+	u32 imr3_core0;
+	u32 imr4_core0;
+	u32 imr1_core1;
+	u32 imr2_core1;
+	u32 imr3_core1;
+	u32 imr4_core1;
+	u32 imr1_cpu1;
+	u32 imr2_cpu1;
+	u32 imr3_cpu1;
+	u32 imr4_cpu1;
+	u32 imr1_cpu3;
+	u32 imr2_cpu3;
+	u32 imr3_cpu3;
+	u32 imr4_cpu3;
+	u32 isr1_cpu0;
+	u32 isr2_cpu0;
+	u32 isr3_cpu0;
+	u32 isr4_cpu0;
+	u32 isr1_cpu1;
+	u32 isr2_cpu1;
+	u32 isr3_cpu1;
+	u32 isr4_cpu1;
+	u32 isr1_cpu2;
+	u32 isr2_cpu2;
+	u32 isr3_cpu2;
+	u32 isr4_cpu2;
+	u32 isr1_cpu3;
+	u32 isr2_cpu3;
+	u32 isr3_cpu3;
+	u32 isr4_cpu3;
+	u32 slt0_cfg;
+	u32 slt1_cfg;
+	u32 slt2_cfg;
+	u32 slt3_cfg;
+	u32 slt4_cfg;
+	u32 slt5_cfg;
+	u32 slt6_cfg;
+	u32 slt7_cfg;
+	u32 slt8_cfg;
+	u32 slt9_cfg;
+	u32 slt10_cfg;
+	u32 slt11_cfg;
+	u32 slt12_cfg;
+	u32 slt13_cfg;
+	u32 slt14_cfg;
+	u32 pgc_cpu_0_1_mapping;
+	u32 cpu_pgc_up_trg;
+	u32 mix_pgc_up_trg;
+	u32 pu_pgc_up_trg;
+	u32 cpu_pgc_dn_trg;
+	u32 mix_pgc_dn_trg;
+	u32 pu_pgc_dn_trg;
+	u32 lpcr_bsc2;
+	u32 pgc_cpu_2_3_mapping;
+	u32 lps_cpu0;
+	u32 lps_cpu1;
+	u32 lps_cpu2;
+	u32 lps_cpu3;
+	u32 gpc_gpr;
+	u32 gtor;
+	u32 debug_addr1;
+	u32 debug_addr2;
+	u32 cpu_pgc_up_status1;
+	u32 mix_pgc_up_status0;
+	u32 mix_pgc_up_status1;
+	u32 mix_pgc_up_status2;
+	u32 m4_mix_pgc_up_status0;
+	u32 m4_mix_pgc_up_status1;
+	u32 m4_mix_pgc_up_status2;
+	u32 pu_pgc_up_status0;
+	u32 pu_pgc_up_status1;
+	u32 pu_pgc_up_status2;
+	u32 m4_pu_pgc_up_status0;
+	u32 m4_pu_pgc_up_status1;
+	u32 m4_pu_pgc_up_status2;
+	u32 a53_lp_io_0;
+	u32 a53_lp_io_1;
+	u32 a53_lp_io_2;
+	u32 cpu_pgc_dn_status1;
+	u32 mix_pgc_dn_status0;
+	u32 mix_pgc_dn_status1;
+	u32 mix_pgc_dn_status2;
+	u32 m4_mix_pgc_dn_status0;
+	u32 m4_mix_pgc_dn_status1;
+	u32 m4_mix_pgc_dn_status2;
+	u32 pu_pgc_dn_status0;
+	u32 pu_pgc_dn_status1;
+	u32 pu_pgc_dn_status2;
+	u32 m4_pu_pgc_dn_status0;
+	u32 m4_pu_pgc_dn_status1;
+	u32 m4_pu_pgc_dn_status2;
+	u32 res[3];
+	u32 mix_pdn_flg;
+	u32 pu_pdn_flg;
+	u32 m4_mix_pdn_flg;
+	u32 m4_pu_pdn_flg;
+	u32 imr1_core2;
+	u32 imr2_core2;
+	u32 imr3_core2;
+	u32 imr4_core2;
+	u32 imr1_core3;
+	u32 imr2_core3;
+	u32 imr3_core3;
+	u32 imr4_core3;
+	u32 pgc_ack_sel_pu;
+	u32 pgc_ack_sel_m4_pu;
+	u32 slt15_cfg;
+	u32 slt16_cfg;
+	u32 slt17_cfg;
+	u32 slt18_cfg;
+	u32 slt19_cfg;
+	u32 gpc_pu_pwrhsk;
+	u32 slt0_cfg_pu;
+	u32 slt1_cfg_pu;
+	u32 slt2_cfg_pu;
+	u32 slt3_cfg_pu;
+	u32 slt4_cfg_pu;
+	u32 slt5_cfg_pu;
+	u32 slt6_cfg_pu;
+	u32 slt7_cfg_pu;
+	u32 slt8_cfg_pu;
+	u32 slt9_cfg_pu;
+	u32 slt10_cfg_pu;
+	u32 slt11_cfg_pu;
+	u32 slt12_cfg_pu;
+	u32 slt13_cfg_pu;
+	u32 slt14_cfg_pu;
+	u32 slt15_cfg_pu;
+	u32 slt16_cfg_pu;
+	u32 slt17_cfg_pu;
+	u32 slt18_cfg_pu;
+	u32 slt19_cfg_pu;
+};
+
+#define WDOG_WDT_MASK	BIT(3)
+#define WDOG_WDZST_MASK	BIT(0)
+struct wdog_regs {
+	u16	wcr;	/* Control */
+	u16	wsr;	/* Service */
+	u16	wrsr;	/* Reset Status */
+	u16	wicr;	/* Interrupt Control */
+	u16	wmcr;	/* Miscellaneous Control */
+};
+
+struct bootrom_sw_info {
+	u8 reserved_1;
+	u8 boot_dev_instance;
+	u8 boot_dev_type;
+	u8 reserved_2;
+	u32 core_freq;
+	u32 axi_freq;
+	u32 ddr_freq;
+	u32 tick_freq;
+	u32 reserved_3[3];
+};
+
+#define ROM_SW_INFO_ADDR_B0	0x00000968
+#define ROM_SW_INFO_ADDR_A0	0x000009e8
+
+#define ROM_SW_INFO_ADDR is_soc_rev(CHIP_REV_1_0) ? \
+		(struct bootrom_sw_info **)ROM_SW_INFO_ADDR_A0 : \
+		(struct bootrom_sw_info **)ROM_SW_INFO_ADDR_B0
+#endif
+#endif

arch/arm/include/asm/arch-mx8m/mx8mq_pins.h

@@ -0,0 +1,623 @@
+/*
+ * Copyright (C) 2017 NXP
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_MX8MQ_PINS_H__
+#define __ASM_ARCH_MX8MQ_PINS_H__
+
+#include <asm/mach-imx/iomux-v3.h>
+
+enum {
+		IMX8MQ_PAD_GPIO1_IO00__GPIO1_IO0                    = IOMUX_PAD(0x0290, 0x0028, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT    = IOMUX_PAD(0x0290, 0x0028, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO00__XTALOSC_REF_CLK_32K          = IOMUX_PAD(0x0290, 0x0028, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO00__CCM_EXT_CLK1                 = IOMUX_PAD(0x0290, 0x0028, 6, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO00__JTAG_FAIL                    = IOMUX_PAD(0x0290, 0x0028, 7, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_GPIO1_IO01__GPIO1_IO1                    = IOMUX_PAD(0x0294, 0x002C, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO01__PWM1_OUT                     = IOMUX_PAD(0x0294, 0x002C, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO01__XTALOSC_REF_CLK_24M          = IOMUX_PAD(0x0294, 0x002C, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO01__CCM_EXT_CLK2                 = IOMUX_PAD(0x0294, 0x002C, 6, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO01__JTAG_ACTIVE                  = IOMUX_PAD(0x0294, 0x002C, 7, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_GPIO1_IO02__GPIO1_IO2                    = IOMUX_PAD(0x0298, 0x0030, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B                 = IOMUX_PAD(0x0298, 0x0030, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_ANY               = IOMUX_PAD(0x0298, 0x0030, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO02__JTAG_DE_B                    = IOMUX_PAD(0x0298, 0x0030, 7, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_GPIO1_IO03__GPIO1_IO3                    = IOMUX_PAD(0x029C, 0x0034, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO03__USDHC1_VSELECT               = IOMUX_PAD(0x029C, 0x0034, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO03__SDMA1_EXT_EVENT0             = IOMUX_PAD(0x029C, 0x0034, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO03__XTALOSC_XTAL_OK              = IOMUX_PAD(0x029C, 0x0034, 6, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO03__JTAG_DONE                    = IOMUX_PAD(0x029C, 0x0034, 7, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_GPIO1_IO04__GPIO1_IO4                    = IOMUX_PAD(0x02A0, 0x0038, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO04__USDHC2_VSELECT               = IOMUX_PAD(0x02A0, 0x0038, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO04__SDMA1_EXT_EVENT1             = IOMUX_PAD(0x02A0, 0x0038, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO04__XTALOSC_XTAL_OK_1V           = IOMUX_PAD(0x02A0, 0x0038, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_GPIO1_IO05__GPIO1_IO5                    = IOMUX_PAD(0x02A4, 0x003C, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO05__ARM_PLATFORM_CM4_NMI         = IOMUX_PAD(0x02A4, 0x003C, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO05__CCM_PMIC_READY               = IOMUX_PAD(0x02A4, 0x003C, 5, 0x04BC, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO05__SRC_INT_BOOT                 = IOMUX_PAD(0x02A4, 0x003C, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_GPIO1_IO06__GPIO1_IO6                    = IOMUX_PAD(0x02A8, 0x0040, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO06__ENET_MDC                     = IOMUX_PAD(0x02A8, 0x0040, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO06__USDHC1_CD_B                  = IOMUX_PAD(0x02A8, 0x0040, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO06__CCM_EXT_CLK3                 = IOMUX_PAD(0x02A8, 0x0040, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_GPIO1_IO07__GPIO1_IO7                    = IOMUX_PAD(0x02AC, 0x0044, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO07__ENET_MDIO                    = IOMUX_PAD(0x02AC, 0x0044, 1, 0x04C0, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO07__USDHC1_WP                    = IOMUX_PAD(0x02AC, 0x0044, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO07__CCM_EXT_CLK4                 = IOMUX_PAD(0x02AC, 0x0044, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_GPIO1_IO08__GPIO1_IO8                    = IOMUX_PAD(0x02B0, 0x0048, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO08__ENET_1588_EVENT0_IN          = IOMUX_PAD(0x02B0, 0x0048, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO08__USDHC2_RESET_B               = IOMUX_PAD(0x02B0, 0x0048, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO08__CCM_WAIT                     = IOMUX_PAD(0x02B0, 0x0048, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9                    = IOMUX_PAD(0x02B4, 0x004C, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO09__ENET_1588_EVENT0_OUT         = IOMUX_PAD(0x02B4, 0x004C, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO09__SDMA2_EXT_EVENT0             = IOMUX_PAD(0x02B4, 0x004C, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO09__CCM_STOP                     = IOMUX_PAD(0x02B4, 0x004C, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_GPIO1_IO10__GPIO1_IO10                   = IOMUX_PAD(0x02B8, 0x0050, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO10__USB1_OTG_ID                  = IOMUX_PAD(0x02B8, 0x0050, 1, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_GPIO1_IO11__GPIO1_IO11                   = IOMUX_PAD(0x02BC, 0x0054, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO11__USB2_OTG_ID                  = IOMUX_PAD(0x02BC, 0x0054, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO11__CCM_PMIC_READY               = IOMUX_PAD(0x02BC, 0x0054, 5, 0x04BC, 1, 0),
+
+		IMX8MQ_PAD_GPIO1_IO12__GPIO1_IO12                   = IOMUX_PAD(0x02C0, 0x0058, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO12__USB1_OTG_PWR                 = IOMUX_PAD(0x02C0, 0x0058, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO12__SDMA2_EXT_EVENT1             = IOMUX_PAD(0x02C0, 0x0058, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO12__CSU_CSU_ALARM_AUT0           = IOMUX_PAD(0x02C0, 0x0058, 7, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_GPIO1_IO13__GPIO1_IO13                   = IOMUX_PAD(0x02C4, 0x005C, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO13__USB1_OTG_OC                  = IOMUX_PAD(0x02C4, 0x005C, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO13__PWM2_OUT                     = IOMUX_PAD(0x02C4, 0x005C, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO13__CSU_CSU_ALARM_AUT1           = IOMUX_PAD(0x02C4, 0x005C, 7, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_GPIO1_IO14__GPIO1_IO14                   = IOMUX_PAD(0x02C8, 0x0060, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO14__USB2_OTG_PWR                 = IOMUX_PAD(0x02C8, 0x0060, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO14__PWM3_OUT                     = IOMUX_PAD(0x02C8, 0x0060, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO14__CCM_CLKO1                    = IOMUX_PAD(0x02C8, 0x0060, 6, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO14__CSU_CSU_ALARM_AUT2           = IOMUX_PAD(0x02C8, 0x0060, 7, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_GPIO1_IO15__GPIO1_IO15                   = IOMUX_PAD(0x02CC, 0x0064, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO15__USB2_OTG_OC                  = IOMUX_PAD(0x02CC, 0x0064, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO15__PWM4_OUT                     = IOMUX_PAD(0x02CC, 0x0064, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO15__CCM_CLKO2                    = IOMUX_PAD(0x02CC, 0x0064, 6, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO15__CSU_CSU_INT_DEB              = IOMUX_PAD(0x02CC, 0x0064, 7, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ENET_MDC__ENET_MDC                       = IOMUX_PAD(0x02D0, 0x0068, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ENET_MDC__GPIO1_IO16                     = IOMUX_PAD(0x02D0, 0x0068, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ENET_MDIO__ENET_MDIO                     = IOMUX_PAD(0x02D4, 0x006C, 0, 0x04C0, 1, 0),
+		IMX8MQ_PAD_ENET_MDIO__GPIO1_IO17                    = IOMUX_PAD(0x02D4, 0x006C, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ENET_TD3__ENET_RGMII_TD3                 = IOMUX_PAD(0x02D8, 0x0070, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ENET_TD3__GPIO1_IO18                     = IOMUX_PAD(0x02D8, 0x0070, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ENET_TD2__ENET_RGMII_TD2                 = IOMUX_PAD(0x02DC, 0x0074, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ENET_TD2__ENET_TX_CLK                    = IOMUX_PAD(0x02DC, 0x0074, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_ENET_TD2__GPIO1_IO19                     = IOMUX_PAD(0x02DC, 0x0074, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ENET_TD1__ENET_RGMII_TD1                 = IOMUX_PAD(0x02E0, 0x0078, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ENET_TD1__GPIO1_IO20                     = IOMUX_PAD(0x02E0, 0x0078, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ENET_TD0__ENET_RGMII_TD0                 = IOMUX_PAD(0x02E4, 0x007C, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ENET_TD0__GPIO1_IO21                     = IOMUX_PAD(0x02E4, 0x007C, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ENET_TX_CTL__ENET_RGMII_TX_CTL           = IOMUX_PAD(0x02E8, 0x0080, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ENET_TX_CTL__GPIO1_IO22                  = IOMUX_PAD(0x02E8, 0x0080, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ENET_TXC__ENET_RGMII_TXC                 = IOMUX_PAD(0x02EC, 0x0084, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ENET_TXC__ENET_TX_ER                     = IOMUX_PAD(0x02EC, 0x0084, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_ENET_TXC__GPIO1_IO23                     = IOMUX_PAD(0x02EC, 0x0084, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ENET_RX_CTL__ENET_RGMII_RX_CTL           = IOMUX_PAD(0x02F0, 0x0088, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ENET_RX_CTL__GPIO1_IO24                  = IOMUX_PAD(0x02F0, 0x0088, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ENET_RXC__ENET_RGMII_RXC                 = IOMUX_PAD(0x02F4, 0x008C, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ENET_RXC__ENET_RX_ER                     = IOMUX_PAD(0x02F4, 0x008C, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_ENET_RXC__GPIO1_IO25                     = IOMUX_PAD(0x02F4, 0x008C, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ENET_RD0__ENET_RGMII_RD0                 = IOMUX_PAD(0x02F8, 0x0090, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ENET_RD0__GPIO1_IO26                     = IOMUX_PAD(0x02F8, 0x0090, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ENET_RD1__ENET_RGMII_RD1                 = IOMUX_PAD(0x02FC, 0x0094, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ENET_RD1__GPIO1_IO27                     = IOMUX_PAD(0x02FC, 0x0094, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ENET_RD2__ENET_RGMII_RD2                 = IOMUX_PAD(0x0300, 0x0098, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ENET_RD2__GPIO1_IO28                     = IOMUX_PAD(0x0300, 0x0098, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ENET_RD3__ENET_RGMII_RD3                 = IOMUX_PAD(0x0304, 0x009C, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ENET_RD3__GPIO1_IO29                     = IOMUX_PAD(0x0304, 0x009C, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD1_CLK__USDHC1_CLK                      = IOMUX_PAD(0x0308, 0x00A0, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD1_CLK__GPIO2_IO0                       = IOMUX_PAD(0x0308, 0x00A0, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD1_CMD__USDHC1_CMD                      = IOMUX_PAD(0x030C, 0x00A4, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD1_CMD__GPIO2_IO1                       = IOMUX_PAD(0x030C, 0x00A4, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0                  = IOMUX_PAD(0x0310, 0x00A8, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD1_DATA0__GPIO2_IO2                     = IOMUX_PAD(0x0310, 0x00A8, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1                  = IOMUX_PAD(0x0314, 0x00AC, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD1_DATA1__GPIO2_IO3                     = IOMUX_PAD(0x0314, 0x00AC, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2                  = IOMUX_PAD(0x0318, 0x00B0, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD1_DATA2__GPIO2_IO4                     = IOMUX_PAD(0x0318, 0x00B0, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3                  = IOMUX_PAD(0x031C, 0x00B4, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD1_DATA3__GPIO2_IO5                     = IOMUX_PAD(0x031C, 0x00B4, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4                  = IOMUX_PAD(0x0320, 0x00B8, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD1_DATA4__GPIO2_IO6                     = IOMUX_PAD(0x0320, 0x00B8, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5                  = IOMUX_PAD(0x0324, 0x00BC, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD1_DATA5__GPIO2_IO7                     = IOMUX_PAD(0x0324, 0x00BC, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6                  = IOMUX_PAD(0x0328, 0x00C0, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD1_DATA6__GPIO2_IO8                     = IOMUX_PAD(0x0328, 0x00C0, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7                  = IOMUX_PAD(0x032C, 0x00C4, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD1_DATA7__GPIO2_IO9                     = IOMUX_PAD(0x032C, 0x00C4, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD1_RESET_B__USDHC1_RESET_B              = IOMUX_PAD(0x0330, 0x00C8, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10                  = IOMUX_PAD(0x0330, 0x00C8, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD1_STROBE__USDHC1_STROBE                = IOMUX_PAD(0x0334, 0x00CC, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD1_STROBE__GPIO2_IO11                   = IOMUX_PAD(0x0334, 0x00CC, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD2_CD_B__USDHC2_CD_B                    = IOMUX_PAD(0x0338, 0x00D0, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12                     = IOMUX_PAD(0x0338, 0x00D0, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD2_CLK__USDHC2_CLK                      = IOMUX_PAD(0x033C, 0x00D4, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD2_CLK__GPIO2_IO13                      = IOMUX_PAD(0x033C, 0x00D4, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD2_CMD__USDHC2_CMD                      = IOMUX_PAD(0x0340, 0x00D8, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD2_CMD__GPIO2_IO14                      = IOMUX_PAD(0x0340, 0x00D8, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0                  = IOMUX_PAD(0x0344, 0x00DC, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD2_DATA0__GPIO2_IO15                    = IOMUX_PAD(0x0344, 0x00DC, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1                  = IOMUX_PAD(0x0348, 0x00E0, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD2_DATA1__GPIO2_IO16                    = IOMUX_PAD(0x0348, 0x00E0, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD2_DATA1__CCM_WAIT                      = IOMUX_PAD(0x0348, 0x00E0, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2                  = IOMUX_PAD(0x034C, 0x00E4, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD2_DATA2__GPIO2_IO17                    = IOMUX_PAD(0x034C, 0x00E4, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD2_DATA2__CCM_STOP                      = IOMUX_PAD(0x034C, 0x00E4, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3                  = IOMUX_PAD(0x0350, 0x00E8, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD2_DATA3__GPIO2_IO18                    = IOMUX_PAD(0x0350, 0x00E8, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD2_DATA3__SRC_EARLY_RESET               = IOMUX_PAD(0x0350, 0x00E8, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD2_RESET_B__USDHC2_RESET_B              = IOMUX_PAD(0x0354, 0x00EC, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19                  = IOMUX_PAD(0x0354, 0x00EC, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD2_RESET_B__SRC_SYSTEM_RESET            = IOMUX_PAD(0x0354, 0x00EC, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD2_WP__USDHC2_WP                        = IOMUX_PAD(0x0358, 0x00F0, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD2_WP__GPIO2_IO20                       = IOMUX_PAD(0x0358, 0x00F0, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_ALE__RAWNAND_ALE                    = IOMUX_PAD(0x035C, 0x00F4, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_ALE__QSPI_A_SCLK                    = IOMUX_PAD(0x035C, 0x00F4, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_ALE__GPIO3_IO0                      = IOMUX_PAD(0x035C, 0x00F4, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_CE0_B__RAWNAND_CE0_B                = IOMUX_PAD(0x0360, 0x00F8, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_CE0_B__QSPI_A_SS0_B                 = IOMUX_PAD(0x0360, 0x00F8, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_CE0_B__GPIO3_IO1                    = IOMUX_PAD(0x0360, 0x00F8, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_CE1_B__RAWNAND_CE1_B                = IOMUX_PAD(0x0364, 0x00FC, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_CE1_B__QSPI_A_SS1_B                 = IOMUX_PAD(0x0364, 0x00FC, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_CE1_B__GPIO3_IO2                    = IOMUX_PAD(0x0364, 0x00FC, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_CE2_B__RAWNAND_CE2_B                = IOMUX_PAD(0x0368, 0x0100, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_CE2_B__QSPI_B_SS0_B                 = IOMUX_PAD(0x0368, 0x0100, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_CE2_B__GPIO3_IO3                    = IOMUX_PAD(0x0368, 0x0100, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_CE3_B__RAWNAND_CE3_B                = IOMUX_PAD(0x036C, 0x0104, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_CE3_B__QSPI_B_SS1_B                 = IOMUX_PAD(0x036C, 0x0104, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_CE3_B__GPIO3_IO4                    = IOMUX_PAD(0x036C, 0x0104, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_CLE__RAWNAND_CLE                    = IOMUX_PAD(0x0370, 0x0108, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_CLE__QSPI_B_SCLK                    = IOMUX_PAD(0x0370, 0x0108, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_CLE__GPIO3_IO5                      = IOMUX_PAD(0x0370, 0x0108, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_DATA00__RAWNAND_DATA00              = IOMUX_PAD(0x0374, 0x010C, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_DATA00__QSPI_A_DATA0                = IOMUX_PAD(0x0374, 0x010C, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_DATA00__GPIO3_IO6                   = IOMUX_PAD(0x0374, 0x010C, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_DATA01__RAWNAND_DATA01              = IOMUX_PAD(0x0378, 0x0110, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_DATA01__QSPI_A_DATA1                = IOMUX_PAD(0x0378, 0x0110, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_DATA01__GPIO3_IO7                   = IOMUX_PAD(0x0378, 0x0110, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_DATA02__RAWNAND_DATA02              = IOMUX_PAD(0x037C, 0x0114, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_DATA02__QSPI_A_DATA2                = IOMUX_PAD(0x037C, 0x0114, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_DATA02__GPIO3_IO8                   = IOMUX_PAD(0x037C, 0x0114, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_DATA03__RAWNAND_DATA03              = IOMUX_PAD(0x0380, 0x0118, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_DATA03__QSPI_A_DATA3                = IOMUX_PAD(0x0380, 0x0118, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_DATA03__GPIO3_IO9                   = IOMUX_PAD(0x0380, 0x0118, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_DATA04__RAWNAND_DATA04              = IOMUX_PAD(0x0384, 0x011C, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_DATA04__QSPI_B_DATA0                = IOMUX_PAD(0x0384, 0x011C, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_DATA04__GPIO3_IO10                  = IOMUX_PAD(0x0384, 0x011C, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_DATA05__RAWNAND_DATA05              = IOMUX_PAD(0x0388, 0x0120, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_DATA05__QSPI_B_DATA1                = IOMUX_PAD(0x0388, 0x0120, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_DATA05__GPIO3_IO11                  = IOMUX_PAD(0x0388, 0x0120, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_DATA06__RAWNAND_DATA06              = IOMUX_PAD(0x038C, 0x0124, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_DATA06__QSPI_B_DATA2                = IOMUX_PAD(0x038C, 0x0124, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_DATA06__GPIO3_IO12                  = IOMUX_PAD(0x038C, 0x0124, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_DATA07__RAWNAND_DATA07              = IOMUX_PAD(0x0390, 0x0128, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_DATA07__QSPI_B_DATA3                = IOMUX_PAD(0x0390, 0x0128, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_DATA07__GPIO3_IO13                  = IOMUX_PAD(0x0390, 0x0128, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_DQS__RAWNAND_DQS                    = IOMUX_PAD(0x0394, 0x012C, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_DQS__QSPI_A_DQS                     = IOMUX_PAD(0x0394, 0x012C, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_DQS__GPIO3_IO14                     = IOMUX_PAD(0x0394, 0x012C, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_RE_B__RAWNAND_RE_B                  = IOMUX_PAD(0x0398, 0x0130, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_RE_B__QSPI_B_DQS                    = IOMUX_PAD(0x0398, 0x0130, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_RE_B__GPIO3_IO15                    = IOMUX_PAD(0x0398, 0x0130, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_READY_B__RAWNAND_READY_B            = IOMUX_PAD(0x039C, 0x0134, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_READY_B__GPIO3_IO16                 = IOMUX_PAD(0x039C, 0x0134, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_WE_B__RAWNAND_WE_B                  = IOMUX_PAD(0x03A0, 0x0138, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_WE_B__GPIO3_IO17                    = IOMUX_PAD(0x03A0, 0x0138, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_WP_B__RAWNAND_WP_B                  = IOMUX_PAD(0x03A4, 0x013C, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_WP_B__GPIO3_IO18                    = IOMUX_PAD(0x03A4, 0x013C, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI5_RXFS__SAI5_RX_SYNC                  = IOMUX_PAD(0x03A8, 0x0140, 0, 0x04E4, 0, 0),
+		IMX8MQ_PAD_SAI5_RXFS__SAI1_TX_DATA0                 = IOMUX_PAD(0x03A8, 0x0140, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI5_RXFS__GPIO3_IO19                    = IOMUX_PAD(0x03A8, 0x0140, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI5_RXC__SAI5_RX_BCLK                   = IOMUX_PAD(0x03AC, 0x0144, 0, 0x04D0, 0, 0),
+		IMX8MQ_PAD_SAI5_RXC__SAI1_TX_DATA1                  = IOMUX_PAD(0x03AC, 0x0144, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI5_RXC__GPIO3_IO20                     = IOMUX_PAD(0x03AC, 0x0144, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI5_RXD0__SAI5_RX_DATA0                 = IOMUX_PAD(0x03B0, 0x0148, 0, 0x04D4, 0, 0),
+		IMX8MQ_PAD_SAI5_RXD0__SAI1_TX_DATA2                 = IOMUX_PAD(0x03B0, 0x0148, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI5_RXD0__GPIO3_IO21                    = IOMUX_PAD(0x03B0, 0x0148, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI5_RXD1__SAI5_RX_DATA1                 = IOMUX_PAD(0x03B4, 0x014C, 0, 0x04D8, 0, 0),
+		IMX8MQ_PAD_SAI5_RXD1__SAI1_TX_DATA3                 = IOMUX_PAD(0x03B4, 0x014C, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI5_RXD1__SAI1_TX_SYNC                  = IOMUX_PAD(0x03B4, 0x014C, 2, 0x04CC, 0, 0),
+		IMX8MQ_PAD_SAI5_RXD1__SAI5_TX_SYNC                  = IOMUX_PAD(0x03B4, 0x014C, 3, 0x04EC, 0, 0),
+		IMX8MQ_PAD_SAI5_RXD1__GPIO3_IO22                    = IOMUX_PAD(0x03B4, 0x014C, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI5_RXD2__SAI5_RX_DATA2                 = IOMUX_PAD(0x03B8, 0x0150, 0, 0x04DC, 0, 0),
+		IMX8MQ_PAD_SAI5_RXD2__SAI1_TX_DATA4                 = IOMUX_PAD(0x03B8, 0x0150, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI5_RXD2__SAI1_TX_SYNC                  = IOMUX_PAD(0x03B8, 0x0150, 2, 0x04CC, 1, 0),
+		IMX8MQ_PAD_SAI5_RXD2__SAI5_TX_BCLK                  = IOMUX_PAD(0x03B8, 0x0150, 3, 0x04E8, 0, 0),
+		IMX8MQ_PAD_SAI5_RXD2__GPIO3_IO23                    = IOMUX_PAD(0x03B8, 0x0150, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI5_RXD3__SAI5_RX_DATA3                 = IOMUX_PAD(0x03BC, 0x0154, 0, 0x04E0, 0, 0),
+		IMX8MQ_PAD_SAI5_RXD3__SAI1_TX_DATA5                 = IOMUX_PAD(0x03BC, 0x0154, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI5_RXD3__SAI1_TX_SYNC                  = IOMUX_PAD(0x03BC, 0x0154, 2, 0x04CC, 2, 0),
+		IMX8MQ_PAD_SAI5_RXD3__SAI5_TX_DATA0                 = IOMUX_PAD(0x03BC, 0x0154, 3, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI5_RXD3__GPIO3_IO24                    = IOMUX_PAD(0x03BC, 0x0154, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI5_MCLK__SAI5_MCLK                     = IOMUX_PAD(0x03C0, 0x0158, 0, 0x052C, 0, 0),
+		IMX8MQ_PAD_SAI5_MCLK__SAI1_TX_BCLK                  = IOMUX_PAD(0x03C0, 0x0158, 1, 0x04C8, 0, 0),
+		IMX8MQ_PAD_SAI5_MCLK__SAI4_MCLK                     = IOMUX_PAD(0x03C0, 0x0158, 2, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI5_MCLK__GPIO3_IO25                    = IOMUX_PAD(0x03C0, 0x0158, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI5_MCLK__SRC_TESTER_ACK                = IOMUX_PAD(0x03C0, 0x0158, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_RXFS__SAI1_RX_SYNC                  = IOMUX_PAD(0x03C4, 0x015C, 0, 0x04C4, 0, 0),
+		IMX8MQ_PAD_SAI1_RXFS__SAI5_RX_SYNC                  = IOMUX_PAD(0x03C4, 0x015C, 1, 0x04E4, 1, 0),
+		IMX8MQ_PAD_SAI1_RXFS__ARM_PLATFORM_TRACE_CLK        = IOMUX_PAD(0x03C4, 0x015C, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXFS__GPIO4_IO0                     = IOMUX_PAD(0x03C4, 0x015C, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_RXC__SAI1_RX_BCLK                   = IOMUX_PAD(0x03C8, 0x0160, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXC__SAI5_RX_BCLK                   = IOMUX_PAD(0x03C8, 0x0160, 1, 0x04D0, 1, 0),
+		IMX8MQ_PAD_SAI1_RXC__ARM_PLATFORM_TRACE_CTL         = IOMUX_PAD(0x03C8, 0x0160, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXC__GPIO4_IO1                      = IOMUX_PAD(0x03C8, 0x0160, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_RXD0__SAI1_RX_DATA0                 = IOMUX_PAD(0x03CC, 0x0164, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD0__SAI5_RX_DATA0                 = IOMUX_PAD(0x03CC, 0x0164, 1, 0x04D4, 1, 0),
+		IMX8MQ_PAD_SAI1_RXD0__ARM_PLATFORM_TRACE0           = IOMUX_PAD(0x03CC, 0x0164, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD0__GPIO4_IO2                     = IOMUX_PAD(0x03CC, 0x0164, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD0__SRC_BOOT_CFG0                 = IOMUX_PAD(0x03CC, 0x0164, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_RXD1__SAI1_RX_DATA1                 = IOMUX_PAD(0x03D0, 0x0168, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD1__SAI5_RX_DATA1                 = IOMUX_PAD(0x03D0, 0x0168, 1, 0x04D8, 1, 0),
+		IMX8MQ_PAD_SAI1_RXD1__ARM_PLATFORM_TRACE1           = IOMUX_PAD(0x03D0, 0x0168, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD1__GPIO4_IO3                     = IOMUX_PAD(0x03D0, 0x0168, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD1__SRC_BOOT_CFG1                 = IOMUX_PAD(0x03D0, 0x0168, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_RXD2__SAI1_RX_DATA2                 = IOMUX_PAD(0x03D4, 0x016C, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD2__SAI5_RX_DATA2                 = IOMUX_PAD(0x03D4, 0x016C, 1, 0x04DC, 1, 0),
+		IMX8MQ_PAD_SAI1_RXD2__ARM_PLATFORM_TRACE2           = IOMUX_PAD(0x03D4, 0x016C, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD2__GPIO4_IO4                     = IOMUX_PAD(0x03D4, 0x016C, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD2__SRC_BOOT_CFG2                 = IOMUX_PAD(0x03D4, 0x016C, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_RXD3__SAI1_RX_DATA3                 = IOMUX_PAD(0x03D8, 0x0170, 0, 0x04E0, 1, 0),
+		IMX8MQ_PAD_SAI1_RXD3__SAI5_RX_DATA3                 = IOMUX_PAD(0x03D8, 0x0170, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD3__ARM_PLATFORM_TRACE3           = IOMUX_PAD(0x03D8, 0x0170, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD3__GPIO4_IO5                     = IOMUX_PAD(0x03D8, 0x0170, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD3__SRC_BOOT_CFG3                 = IOMUX_PAD(0x03D8, 0x0170, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_RXD4__SAI1_RX_DATA4                 = IOMUX_PAD(0x03DC, 0x0174, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD4__SAI6_TX_BCLK                  = IOMUX_PAD(0x03DC, 0x0174, 1, 0x051C, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD4__SAI6_RX_BCLK                  = IOMUX_PAD(0x03DC, 0x0174, 2, 0x0510, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD4__ARM_PLATFORM_TRACE4           = IOMUX_PAD(0x03DC, 0x0174, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD4__GPIO4_IO6                     = IOMUX_PAD(0x03DC, 0x0174, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD4__SRC_BOOT_CFG4                 = IOMUX_PAD(0x03DC, 0x0174, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_RXD5__SAI1_RX_DATA5                 = IOMUX_PAD(0x03E0, 0x0178, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD5__SAI6_TX_DATA0                 = IOMUX_PAD(0x03E0, 0x0178, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD5__SAI6_RX_DATA0                 = IOMUX_PAD(0x03E0, 0x0178, 2, 0x0514, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD5__SAI1_RX_SYNC                  = IOMUX_PAD(0x03E0, 0x0178, 3, 0x04C4, 1, 0),
+		IMX8MQ_PAD_SAI1_RXD5__ARM_PLATFORM_TRACE5           = IOMUX_PAD(0x03E0, 0x0178, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD5__GPIO4_IO7                     = IOMUX_PAD(0x03E0, 0x0178, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD5__SRC_BOOT_CFG5                 = IOMUX_PAD(0x03E0, 0x0178, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_RXD6__SAI1_RX_DATA6                 = IOMUX_PAD(0x03E4, 0x017C, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD6__SAI6_TX_SYNC                  = IOMUX_PAD(0x03E4, 0x017C, 1, 0x0520, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD6__SAI6_RX_SYNC                  = IOMUX_PAD(0x03E4, 0x017C, 2, 0x0518, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD6__ARM_PLATFORM_TRACE6           = IOMUX_PAD(0x03E4, 0x017C, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD6__GPIO4_IO8                     = IOMUX_PAD(0x03E4, 0x017C, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD6__SRC_BOOT_CFG6                 = IOMUX_PAD(0x03E4, 0x017C, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_RXD7__SAI1_RX_DATA7                 = IOMUX_PAD(0x03E8, 0x0180, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD7__SAI6_MCLK                     = IOMUX_PAD(0x03E8, 0x0180, 1, 0x0530, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD7__SAI1_TX_SYNC                  = IOMUX_PAD(0x03E8, 0x0180, 2, 0x04CC, 4, 0),
+		IMX8MQ_PAD_SAI1_RXD7__SAI1_TX_DATA4                 = IOMUX_PAD(0x03E8, 0x0180, 3, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD7__ARM_PLATFORM_TRACE7           = IOMUX_PAD(0x03E8, 0x0180, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD7__GPIO4_IO9                     = IOMUX_PAD(0x03E8, 0x0180, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD7__SRC_BOOT_CFG7                 = IOMUX_PAD(0x03E8, 0x0180, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_TXFS__SAI1_TX_SYNC                  = IOMUX_PAD(0x03EC, 0x0184, 0, 0x04CC, 3, 0),
+		IMX8MQ_PAD_SAI1_TXFS__SAI5_TX_SYNC                  = IOMUX_PAD(0x03EC, 0x0184, 1, 0x04EC, 1, 0),
+		IMX8MQ_PAD_SAI1_TXFS__ARM_PLATFORM_EVENTO           = IOMUX_PAD(0x03EC, 0x0184, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXFS__GPIO4_IO10                    = IOMUX_PAD(0x03EC, 0x0184, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_TXC__SAI1_TX_BCLK                   = IOMUX_PAD(0x03F0, 0x0188, 0, 0x04C8, 1, 0),
+		IMX8MQ_PAD_SAI1_TXC__SAI5_TX_BCLK                   = IOMUX_PAD(0x03F0, 0x0188, 1, 0x04E8, 1, 0),
+		IMX8MQ_PAD_SAI1_TXC__ARM_PLATFORM_EVENTI            = IOMUX_PAD(0x03F0, 0x0188, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXC__GPIO4_IO11                     = IOMUX_PAD(0x03F0, 0x0188, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_TXD0__SAI1_TX_DATA0                 = IOMUX_PAD(0x03F4, 0x018C, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD0__SAI5_TX_DATA0                 = IOMUX_PAD(0x03F4, 0x018C, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD0__ARM_PLATFORM_TRACE8           = IOMUX_PAD(0x03F4, 0x018C, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD0__GPIO4_IO12                    = IOMUX_PAD(0x03F4, 0x018C, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD0__SRC_BOOT_CFG8                 = IOMUX_PAD(0x03F4, 0x018C, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_TXD1__SAI1_TX_DATA1                 = IOMUX_PAD(0x03F8, 0x0190, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD1__SAI5_TX_DATA1                 = IOMUX_PAD(0x03F8, 0x0190, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD1__ARM_PLATFORM_TRACE9           = IOMUX_PAD(0x03F8, 0x0190, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD1__GPIO4_IO13                    = IOMUX_PAD(0x03F8, 0x0190, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD1__SRC_BOOT_CFG9                 = IOMUX_PAD(0x03F8, 0x0190, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_TXD2__SAI1_TX_DATA2                 = IOMUX_PAD(0x03FC, 0x0194, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD2__SAI5_TX_DATA2                 = IOMUX_PAD(0x03FC, 0x0194, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD2__ARM_PLATFORM_TRACE10          = IOMUX_PAD(0x03FC, 0x0194, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD2__GPIO4_IO14                    = IOMUX_PAD(0x03FC, 0x0194, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD2__SRC_BOOT_CFG10                = IOMUX_PAD(0x03FC, 0x0194, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_TXD3__SAI1_TX_DATA3                 = IOMUX_PAD(0x0400, 0x0198, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD3__SAI5_TX_DATA3                 = IOMUX_PAD(0x0400, 0x0198, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD3__ARM_PLATFORM_TRACE11          = IOMUX_PAD(0x0400, 0x0198, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD3__GPIO4_IO15                    = IOMUX_PAD(0x0400, 0x0198, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD3__SRC_BOOT_CFG11                = IOMUX_PAD(0x0400, 0x0198, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_TXD4__SAI1_TX_DATA4                 = IOMUX_PAD(0x0404, 0x019C, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD4__SAI6_RX_BCLK                  = IOMUX_PAD(0x0404, 0x019C, 1, 0x0510, 1, 0),
+		IMX8MQ_PAD_SAI1_TXD4__SAI6_TX_BCLK                  = IOMUX_PAD(0x0404, 0x019C, 2, 0x051C, 1, 0),
+		IMX8MQ_PAD_SAI1_TXD4__ARM_PLATFORM_TRACE12          = IOMUX_PAD(0x0404, 0x019C, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD4__GPIO4_IO16                    = IOMUX_PAD(0x0404, 0x019C, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD4__SRC_BOOT_CFG12                = IOMUX_PAD(0x0404, 0x019C, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_TXD5__SAI1_TX_DATA5                 = IOMUX_PAD(0x0408, 0x01A0, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD5__SAI6_RX_DATA0                 = IOMUX_PAD(0x0408, 0x01A0, 1, 0x0514, 1, 0),
+		IMX8MQ_PAD_SAI1_TXD5__SAI6_TX_DATA0                 = IOMUX_PAD(0x0408, 0x01A0, 2, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD5__ARM_PLATFORM_TRACE13          = IOMUX_PAD(0x0408, 0x01A0, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD5__GPIO4_IO17                    = IOMUX_PAD(0x0408, 0x01A0, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD5__SRC_BOOT_CFG13                = IOMUX_PAD(0x0408, 0x01A0, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_TXD6__SAI1_TX_DATA6                 = IOMUX_PAD(0x040C, 0x01A4, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD6__SAI6_RX_SYNC                  = IOMUX_PAD(0x040C, 0x01A4, 1, 0x0518, 1, 0),
+		IMX8MQ_PAD_SAI1_TXD6__SAI6_TX_SYNC                  = IOMUX_PAD(0x040C, 0x01A4, 2, 0x0520, 1, 0),
+		IMX8MQ_PAD_SAI1_TXD6__ARM_PLATFORM_TRACE14          = IOMUX_PAD(0x040C, 0x01A4, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD6__GPIO4_IO18                    = IOMUX_PAD(0x040C, 0x01A4, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD6__SRC_BOOT_CFG14                = IOMUX_PAD(0x040C, 0x01A4, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_TXD7__SAI1_TX_DATA7                 = IOMUX_PAD(0x0410, 0x01A8, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD7__SAI6_MCLK                     = IOMUX_PAD(0x0410, 0x01A8, 1, 0x0530, 1, 0),
+		IMX8MQ_PAD_SAI1_TXD7__ARM_PLATFORM_TRACE15          = IOMUX_PAD(0x0410, 0x01A8, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD7__GPIO4_IO19                    = IOMUX_PAD(0x0410, 0x01A8, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD7__SRC_BOOT_CFG15                = IOMUX_PAD(0x0410, 0x01A8, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_MCLK__SAI1_MCLK                     = IOMUX_PAD(0x0414, 0x01AC, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_MCLK__SAI5_MCLK                     = IOMUX_PAD(0x0414, 0x01AC, 1, 0x052C, 1, 0),
+		IMX8MQ_PAD_SAI1_MCLK__SAI1_TX_BCLK                  = IOMUX_PAD(0x0414, 0x01AC, 2, 0x04C8, 2, 0),
+		IMX8MQ_PAD_SAI1_MCLK__GPIO4_IO20                    = IOMUX_PAD(0x0414, 0x01AC, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI2_RXFS__SAI2_RX_SYNC                  = IOMUX_PAD(0x0418, 0x01B0, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI2_RXFS__SAI5_TX_SYNC                  = IOMUX_PAD(0x0418, 0x01B0, 1, 0x04EC, 2, 0),
+		IMX8MQ_PAD_SAI2_RXFS__GPIO4_IO21                    = IOMUX_PAD(0x0418, 0x01B0, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI2_RXC__SAI2_RX_BCLK                   = IOMUX_PAD(0x041C, 0x01B4, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI2_RXC__SAI5_TX_BCLK                   = IOMUX_PAD(0x041C, 0x01B4, 1, 0x04E8, 2, 0),
+		IMX8MQ_PAD_SAI2_RXC__GPIO4_IO22                     = IOMUX_PAD(0x041C, 0x01B4, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI2_RXD0__SAI2_RX_DATA0                 = IOMUX_PAD(0x0420, 0x01B8, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI2_RXD0__SAI5_TX_DATA0                 = IOMUX_PAD(0x0420, 0x01B8, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI2_RXD0__GPIO4_IO23                    = IOMUX_PAD(0x0420, 0x01B8, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI2_TXFS__SAI2_TX_SYNC                  = IOMUX_PAD(0x0424, 0x01BC, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI2_TXFS__SAI5_TX_DATA1                 = IOMUX_PAD(0x0424, 0x01BC, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI2_TXFS__GPIO4_IO24                    = IOMUX_PAD(0x0424, 0x01BC, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI2_TXC__SAI2_TX_BCLK                   = IOMUX_PAD(0x0428, 0x01C0, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI2_TXC__SAI5_TX_DATA2                  = IOMUX_PAD(0x0428, 0x01C0, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI2_TXC__GPIO4_IO25                     = IOMUX_PAD(0x0428, 0x01C0, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI2_TXD0__SAI2_TX_DATA0                 = IOMUX_PAD(0x042C, 0x01C4, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI2_TXD0__SAI5_TX_DATA3                 = IOMUX_PAD(0x042C, 0x01C4, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI2_TXD0__GPIO4_IO26                    = IOMUX_PAD(0x042C, 0x01C4, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI2_MCLK__SAI2_MCLK                     = IOMUX_PAD(0x0430, 0x01C8, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI2_MCLK__SAI5_MCLK                     = IOMUX_PAD(0x0430, 0x01C8, 1, 0x052C, 2, 0),
+		IMX8MQ_PAD_SAI2_MCLK__GPIO4_IO27                    = IOMUX_PAD(0x0430, 0x01C8, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI3_RXFS__SAI3_RX_SYNC                  = IOMUX_PAD(0x0434, 0x01CC, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI3_RXFS__GPT1_CAPTURE1                 = IOMUX_PAD(0x0434, 0x01CC, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI3_RXFS__SAI5_RX_SYNC                  = IOMUX_PAD(0x0434, 0x01CC, 2, 0x04E4, 2, 0),
+		IMX8MQ_PAD_SAI3_RXFS__GPIO4_IO28                    = IOMUX_PAD(0x0434, 0x01CC, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI3_RXC__SAI3_RX_BCLK                   = IOMUX_PAD(0x0438, 0x01D0, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI3_RXC__GPT1_CAPTURE2                  = IOMUX_PAD(0x0438, 0x01D0, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI3_RXC__SAI5_RX_BCLK                   = IOMUX_PAD(0x0438, 0x01D0, 2, 0x04D0, 2, 0),
+		IMX8MQ_PAD_SAI3_RXC__GPIO4_IO29                     = IOMUX_PAD(0x0438, 0x01D0, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI3_RXD__SAI3_RX_DATA0                  = IOMUX_PAD(0x043C, 0x01D4, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI3_RXD__GPT1_COMPARE1                  = IOMUX_PAD(0x043C, 0x01D4, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI3_RXD__SAI5_RX_DATA0                  = IOMUX_PAD(0x043C, 0x01D4, 2, 0x04D4, 2, 0),
+		IMX8MQ_PAD_SAI3_RXD__GPIO4_IO30                     = IOMUX_PAD(0x043C, 0x01D4, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI3_TXFS__SAI3_TX_SYNC                  = IOMUX_PAD(0x0440, 0x01D8, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI3_TXFS__GPT1_CLK                      = IOMUX_PAD(0x0440, 0x01D8, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI3_TXFS__SAI5_RX_DATA1                 = IOMUX_PAD(0x0440, 0x01D8, 2, 0x04D8, 2, 0),
+		IMX8MQ_PAD_SAI3_TXFS__GPIO4_IO31                    = IOMUX_PAD(0x0440, 0x01D8, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI3_TXC__SAI3_TX_BCLK                   = IOMUX_PAD(0x0444, 0x01DC, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI3_TXC__GPT1_COMPARE2                  = IOMUX_PAD(0x0444, 0x01DC, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI3_TXC__SAI5_RX_DATA2                  = IOMUX_PAD(0x0444, 0x01DC, 2, 0x04DC, 2, 0),
+		IMX8MQ_PAD_SAI3_TXC__GPIO5_IO0                      = IOMUX_PAD(0x0444, 0x01DC, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI3_TXD__SAI3_TX_DATA0                  = IOMUX_PAD(0x0448, 0x01E0, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI3_TXD__GPT1_COMPARE3                  = IOMUX_PAD(0x0448, 0x01E0, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI3_TXD__SAI5_RX_DATA3                  = IOMUX_PAD(0x0448, 0x01E0, 2, 0x04E0, 2, 0),
+		IMX8MQ_PAD_SAI3_TXD__GPIO5_IO1                      = IOMUX_PAD(0x0448, 0x01E0, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI3_MCLK__SAI3_MCLK                     = IOMUX_PAD(0x044C, 0x01E4, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI3_MCLK__PWM4_OUT                      = IOMUX_PAD(0x044C, 0x01E4, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI3_MCLK__SAI5_MCLK                     = IOMUX_PAD(0x044C, 0x01E4, 2, 0x052C, 3, 0),
+		IMX8MQ_PAD_SAI3_MCLK__GPIO5_IO2                     = IOMUX_PAD(0x044C, 0x01E4, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SPDIF_TX__SPDIF1_OUT                     = IOMUX_PAD(0x0450, 0x01E8, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SPDIF_TX__PWM3_OUT                       = IOMUX_PAD(0x0450, 0x01E8, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SPDIF_TX__GPIO5_IO3                      = IOMUX_PAD(0x0450, 0x01E8, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SPDIF_RX__SPDIF1_IN                      = IOMUX_PAD(0x0454, 0x01EC, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SPDIF_RX__PWM2_OUT                       = IOMUX_PAD(0x0454, 0x01EC, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SPDIF_RX__GPIO5_IO4                      = IOMUX_PAD(0x0454, 0x01EC, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SPDIF_EXT_CLK__SPDIF1_EXT_CLK            = IOMUX_PAD(0x0458, 0x01F0, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SPDIF_EXT_CLK__PWM1_OUT                  = IOMUX_PAD(0x0458, 0x01F0, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SPDIF_EXT_CLK__GPIO5_IO5                 = IOMUX_PAD(0x0458, 0x01F0, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ECSPI1_SCLK__ECSPI1_SCLK                 = IOMUX_PAD(0x045C, 0x01F4, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ECSPI1_SCLK__UART3_RX                    = IOMUX_PAD(0x045C, 0x01F4, 1, 0x0504, 0, 0),
+		IMX8MQ_PAD_ECSPI1_SCLK__GPIO5_IO6                   = IOMUX_PAD(0x045C, 0x01F4, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ECSPI1_MOSI__ECSPI1_MOSI                 = IOMUX_PAD(0x0460, 0x01F8, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ECSPI1_MOSI__UART3_TX                    = IOMUX_PAD(0x0460, 0x01F8, 1, 0x0504, 1, 0),
+		IMX8MQ_PAD_ECSPI1_MOSI__GPIO5_IO7                   = IOMUX_PAD(0x0460, 0x01F8, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ECSPI1_MISO__ECSPI1_MISO                 = IOMUX_PAD(0x0464, 0x01FC, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ECSPI1_MISO__UART3_CTS_B                 = IOMUX_PAD(0x0464, 0x01FC, 1, 0x0500, 0, 0),
+		IMX8MQ_PAD_ECSPI1_MISO__GPIO5_IO8                   = IOMUX_PAD(0x0464, 0x01FC, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ECSPI1_SS0__ECSPI1_SS0                   = IOMUX_PAD(0x0468, 0x0200, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ECSPI1_SS0__UART3_RTS_B                  = IOMUX_PAD(0x0468, 0x0200, 1, 0x0500, 1, 0),
+		IMX8MQ_PAD_ECSPI1_SS0__GPIO5_IO9                    = IOMUX_PAD(0x0468, 0x0200, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ECSPI2_SCLK__ECSPI2_SCLK                 = IOMUX_PAD(0x046C, 0x0204, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ECSPI2_SCLK__UART4_RX                    = IOMUX_PAD(0x046C, 0x0204, 1, 0x050C, 0, 0),
+		IMX8MQ_PAD_ECSPI2_SCLK__GPIO5_IO10                  = IOMUX_PAD(0x046C, 0x0204, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ECSPI2_MOSI__ECSPI2_MOSI                 = IOMUX_PAD(0x0470, 0x0208, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ECSPI2_MOSI__UART4_TX                    = IOMUX_PAD(0x0470, 0x0208, 1, 0x050C, 1, 0),
+		IMX8MQ_PAD_ECSPI2_MOSI__GPIO5_IO11                  = IOMUX_PAD(0x0470, 0x0208, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ECSPI2_MISO__ECSPI2_MISO                 = IOMUX_PAD(0x0474, 0x020C, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ECSPI2_MISO__UART4_CTS_B                 = IOMUX_PAD(0x0474, 0x020C, 1, 0x0508, 0, 0),
+		IMX8MQ_PAD_ECSPI2_MISO__GPIO5_IO12                  = IOMUX_PAD(0x0474, 0x020C, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ECSPI2_SS0__ECSPI2_SS0                   = IOMUX_PAD(0x0478, 0x0210, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ECSPI2_SS0__UART4_RTS_B                  = IOMUX_PAD(0x0478, 0x0210, 1, 0x0508, 1, 0),
+		IMX8MQ_PAD_ECSPI2_SS0__GPIO5_IO13                   = IOMUX_PAD(0x0478, 0x0210, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_I2C1_SCL__I2C1_SCL                       = IOMUX_PAD(0x047C, 0x0214, 0x10 | 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_I2C1_SCL__ENET_MDC                       = IOMUX_PAD(0x047C, 0x0214, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14                     = IOMUX_PAD(0x047C, 0x0214, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_I2C1_SDA__I2C1_SDA                       = IOMUX_PAD(0x0480, 0x0218, 0x10 | 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_I2C1_SDA__ENET_MDIO                      = IOMUX_PAD(0x0480, 0x0218, 1, 0x04C0, 2, 0),
+		IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15                     = IOMUX_PAD(0x0480, 0x0218, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_I2C2_SCL__I2C2_SCL                       = IOMUX_PAD(0x0484, 0x021C, 0x10 | 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_I2C2_SCL__ENET_1588_EVENT1_IN            = IOMUX_PAD(0x0484, 0x021C, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_I2C2_SCL__GPIO5_IO16                     = IOMUX_PAD(0x0484, 0x021C, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_I2C2_SDA__I2C2_SDA                       = IOMUX_PAD(0x0488, 0x0220, 0x10 | 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_I2C2_SDA__ENET_1588_EVENT1_OUT           = IOMUX_PAD(0x0488, 0x0220, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_I2C2_SDA__GPIO5_IO17                     = IOMUX_PAD(0x0488, 0x0220, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_I2C3_SCL__I2C3_SCL                       = IOMUX_PAD(0x048C, 0x0224, 0x10 | 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_I2C3_SCL__PWM4_OUT                       = IOMUX_PAD(0x048C, 0x0224, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_I2C3_SCL__GPT2_CLK                       = IOMUX_PAD(0x048C, 0x0224, 2, 0x0000, 0, 0),
+		IMX8MQ_PAD_I2C3_SCL__GPIO5_IO18                     = IOMUX_PAD(0x048C, 0x0224, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_I2C3_SDA__I2C3_SDA                       = IOMUX_PAD(0x0490, 0x0228, 0x10 | 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_I2C3_SDA__PWM3_OUT                       = IOMUX_PAD(0x0490, 0x0228, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_I2C3_SDA__GPT3_CLK                       = IOMUX_PAD(0x0490, 0x0228, 2, 0x0000, 0, 0),
+		IMX8MQ_PAD_I2C3_SDA__GPIO5_IO19                     = IOMUX_PAD(0x0490, 0x0228, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_I2C4_SCL__I2C4_SCL                       = IOMUX_PAD(0x0494, 0x022C, 0x10 | 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_I2C4_SCL__PWM2_OUT                       = IOMUX_PAD(0x0494, 0x022C, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_I2C4_SCL__PCIE1_CLKREQ_B                 = IOMUX_PAD(0x0494, 0x022C, 2, 0x0524, 0, 0),
+		IMX8MQ_PAD_I2C4_SCL__GPIO5_IO20                     = IOMUX_PAD(0x0494, 0x022C, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_I2C4_SDA__I2C4_SDA                       = IOMUX_PAD(0x0498, 0x0230, 0x10 | 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_I2C4_SDA__PWM1_OUT                       = IOMUX_PAD(0x0498, 0x0230, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_I2C4_SDA__PCIE2_CLKREQ_B                 = IOMUX_PAD(0x0498, 0x0230, 2, 0x0528, 0, 0),
+		IMX8MQ_PAD_I2C4_SDA__GPIO5_IO21                     = IOMUX_PAD(0x0498, 0x0230, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_UART1_RXD__UART1_RX                      = IOMUX_PAD(0x049C, 0x0234, 0, 0x04F4, 0, 0),
+		IMX8MQ_PAD_UART1_RXD__ECSPI3_SCLK                   = IOMUX_PAD(0x049C, 0x0234, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_UART1_RXD__GPIO5_IO22                    = IOMUX_PAD(0x049C, 0x0234, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_UART1_TXD__UART1_TX                      = IOMUX_PAD(0x04A0, 0x0238, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_UART1_TXD__ECSPI3_MOSI                   = IOMUX_PAD(0x04A0, 0x0238, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_UART1_TXD__GPIO5_IO23                    = IOMUX_PAD(0x04A0, 0x0238, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_UART2_RXD__UART2_RX                      = IOMUX_PAD(0x04A4, 0x023C, 0, 0x04FC, 0, 0),
+		IMX8MQ_PAD_UART2_RXD__ECSPI3_MISO                   = IOMUX_PAD(0x04A4, 0x023C, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_UART2_RXD__GPIO5_IO24                    = IOMUX_PAD(0x04A4, 0x023C, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_UART2_TXD__UART2_TX                      = IOMUX_PAD(0x04A8, 0x0240, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_UART2_TXD__ECSPI3_SS0                    = IOMUX_PAD(0x04A8, 0x0240, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_UART2_TXD__GPIO5_IO25                    = IOMUX_PAD(0x04A8, 0x0240, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_UART3_RXD__UART3_RX                      = IOMUX_PAD(0x04AC, 0x0244, 0, 0x0504, 2, 0),
+		IMX8MQ_PAD_UART3_RXD__UART1_CTS_B                   = IOMUX_PAD(0x04AC, 0x0244, 1, 0x04F0, 0, 0),
+		IMX8MQ_PAD_UART3_RXD__GPIO5_IO26                    = IOMUX_PAD(0x04AC, 0x0244, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_UART3_TXD__UART3_TX                      = IOMUX_PAD(0x04B0, 0x0248, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_UART3_TXD__UART1_RTS_B                   = IOMUX_PAD(0x04B0, 0x0248, 1, 0x04F0, 1, 0),
+		IMX8MQ_PAD_UART3_TXD__GPIO5_IO27                    = IOMUX_PAD(0x04B0, 0x0248, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_UART4_RXD__UART4_RX                      = IOMUX_PAD(0x04B4, 0x024C, 0, 0x050C, 2, 0),
+		IMX8MQ_PAD_UART4_RXD__UART2_CTS_B                   = IOMUX_PAD(0x04B4, 0x024C, 1, 0x04F8, 0, 0),
+		IMX8MQ_PAD_UART4_RXD__PCIE1_CLKREQ_B                = IOMUX_PAD(0x04B4, 0x024C, 2, 0x0524, 1, 0),
+		IMX8MQ_PAD_UART4_RXD__GPIO5_IO28                    = IOMUX_PAD(0x04B4, 0x024C, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_UART4_TXD__UART4_TX                      = IOMUX_PAD(0x04B8, 0x0250, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_UART4_TXD__UART2_RTS_B                   = IOMUX_PAD(0x04B8, 0x0250, 1, 0x04F8, 1, 0),
+		IMX8MQ_PAD_UART4_TXD__PCIE2_CLKREQ_B                = IOMUX_PAD(0x04B8, 0x0250, 2, 0x0528, 1, 0),
+		IMX8MQ_PAD_UART4_TXD__GPIO5_IO29                    = IOMUX_PAD(0x04B8, 0x0250, 5, 0x0000, 0, 0),
+};
+#endif

arch/arm/include/asm/arch-mx8m/sys_proto.h

@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ARCH_MX8M_SYS_PROTO_H
+#define __ARCH_MX8M_SYS_PROTO_H
+
+#include <asm/mach-imx/sys_proto.h>
+
+void set_wdog_reset(struct wdog_regs *wdog);
+void enable_tzc380(void);
+void restore_boot_params(void);
+extern unsigned long rom_pointer[];
+enum boot_device get_boot_device(void);
+bool is_usb_boot(void);
+#endif

arch/arm/include/asm/arch-zynqmp/psu_init_gpl.h

@@ -0,0 +1,27 @@
+/*
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef _PSU_INIT_GPL_H_ /* prevent circular inclusions */
+#define _PSU_INIT_GPL_H_
+
+#include <asm/io.h>
+#include <common.h>
+
+int mask_pollonvalue(unsigned long add, u32 mask, u32 value);
+
+int mask_poll(u32 add, u32 mask);
+
+u32 mask_read(u32 add, u32 mask);
+
+void mask_delay(u32 delay);
+
+void psu_mask_write(unsigned long offset, unsigned long mask,
+		    unsigned long val);
+
+void prog_reg(unsigned long addr, unsigned long mask,
+	      unsigned long shift, unsigned long value);
+
+int psu_init(void);
+
+#endif /* _PSU_INIT_GPL_H_ */

arch/arm/include/asm/arch-zynqmp/sys_proto.h

@@ -33,8 +33,6 @@ enum {
 int zynq_board_read_rom_ethaddr(unsigned char *ethaddr);
 unsigned int zynqmp_get_silicon_version(void);
 
-void psu_init(void);
-
 void handoff_setup(void);
 
 void zynqmp_pmufw_version(void);

arch/arm/include/asm/iproc-common/configs.h

@@ -14,7 +14,6 @@
 #define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
 
 /* Memory Info */
-#define CONFIG_SYS_TEXT_BASE		0x61000000
 #define CONFIG_SYS_SDRAM_BASE		0x61000000
 
 #endif /* __IPROC_COMMON_CONFIGS_H */

arch/arm/include/asm/mach-imx/boot_mode.h

@@ -26,10 +26,20 @@ enum boot_device {
 	MMC4_BOOT,
 	NAND_BOOT,
 	QSPI_BOOT,
+	USB_BOOT,
 	UNKNOWN_BOOT,
 	BOOT_DEV_NUM = UNKNOWN_BOOT,
 };
 
+/* Boot device type */
+#define BOOT_TYPE_SD		0x1
+#define BOOT_TYPE_MMC		0x2
+#define BOOT_TYPE_NAND		0x3
+#define BOOT_TYPE_QSPI		0x4
+#define BOOT_TYPE_WEIM		0x5
+#define BOOT_TYPE_SPINOR	0x6
+#define BOOT_TYPE_USB		0xF
+
 struct boot_mode {
 	const char *name;
 	unsigned cfg_val;

arch/arm/include/asm/mach-imx/iomux-v3.h

@@ -87,7 +87,27 @@ typedef u64 iomux_v3_cfg_t;
 #define IOMUX_CONFIG_LPSR       0x20
 #define MUX_MODE_LPSR           ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \
 				MUX_MODE_SHIFT)
-#ifdef CONFIG_MX7
+#ifdef CONFIG_MX8M
+#define PAD_CTL_DSE0		(0x0 << 0)
+#define PAD_CTL_DSE1		(0x1 << 0)
+#define PAD_CTL_DSE2		(0x2 << 0)
+#define PAD_CTL_DSE3		(0x3 << 0)
+#define PAD_CTL_DSE4		(0x4 << 0)
+#define PAD_CTL_DSE5		(0x5 << 0)
+#define PAD_CTL_DSE6		(0x6 << 0)
+#define PAD_CTL_DSE7		(0x7 << 0)
+
+#define PAD_CTL_FSEL0		(0x0 << 3)
+#define PAD_CTL_FSEL1		(0x1 << 3)
+#define PAD_CTL_FSEL2		(0x2 << 3)
+#define PAD_CTL_FSEL3		(0x3 << 3)
+
+#define PAD_CTL_ODE		(0x1 << 5)
+#define PAD_CTL_PUE		(0x1 << 6)
+#define PAD_CTL_HYS		(0x1 << 7)
+#define PAD_CTL_LVTTL		(0x1 << 8)
+
+#elif defined CONFIG_MX7
 
 #define IOMUX_LPSR_SEL_INPUT_OFS 0x70000
 
@@ -240,7 +260,7 @@ void imx_iomux_gpio_get_function(unsigned int gpio,
 #if defined(CONFIG_MX6QDL)
 #define IOMUX_PADS(x) (MX6Q_##x), (MX6DL_##x)
 #define SETUP_IOMUX_PAD(def)					\
-if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {				\
+if (is_mx6dq() || is_mx6dqp()) {				\
 	imx_iomux_v3_setup_pad(MX6Q_##def);			\
 } else {							\
 	imx_iomux_v3_setup_pad(MX6DL_##def);			\

arch/arm/include/asm/mach-imx/mxc_i2c.h

@@ -88,8 +88,7 @@ struct mxc_i2c_bus {
 
 
 #define I2C_PADS_INFO(name)	\
-	(is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) ? \
-					&mx6q_##name : &mx6s_##name
+	(is_mx6dq() || is_mx6dqp()) ? &mx6q_##name : &mx6s_##name
 #endif
 
 int setup_i2c(unsigned i2c_index, int speed, int slave_addr,

arch/arm/include/asm/mach-imx/regs-lcdif.h

@@ -19,11 +19,11 @@
 struct mxs_lcdif_regs {
 	mxs_reg_32(hw_lcdif_ctrl)		/* 0x00 */
 	mxs_reg_32(hw_lcdif_ctrl1)		/* 0x10 */
-
 #if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || \
 	defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
 	defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
-	defined(CONFIG_MX7)
+	defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \
+	defined(CONFIG_MX8M)
 	mxs_reg_32(hw_lcdif_ctrl2)		/* 0x20 */
 #endif
 	mxs_reg_32(hw_lcdif_transfer_count)	/* 0x20/0x30 */
@@ -61,7 +61,8 @@ struct mxs_lcdif_regs {
 #if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || \
 	defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
 	defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
-	defined(CONFIG_MX7)
+	defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \
+	defined(CONFIG_MX8M)
 	mxs_reg_32(hw_lcdif_crc_stat)		/* 0x1a0 */
 #endif
 	mxs_reg_32(hw_lcdif_lcdif_stat)		/* 0x1d0/0x1b0 */
@@ -72,7 +73,8 @@ struct mxs_lcdif_regs {
 #if defined(CONFIG_MX6SX) || \
 	defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
 	defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
-	defined(CONFIG_MX7)
+	defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \
+	defined(CONFIG_MX8M)
 	mxs_reg_32(hw_lcdif_thres)
 	mxs_reg_32(hw_lcdif_as_ctrl)
 	mxs_reg_32(hw_lcdif_as_buf)

arch/arm/include/asm/mach-imx/sys_proto.h

@@ -27,6 +27,7 @@
 
 #define is_mx6() (is_soc_type(MXC_SOC_MX6))
 #define is_mx7() (is_soc_type(MXC_SOC_MX7))
+#define is_mx8m() (is_soc_type(MXC_SOC_MX8M))
 
 #define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
 #define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
@@ -126,4 +127,7 @@ void lcdif_power_down(void);
 int mxs_reset_block(struct mxs_register_32 *reg);
 int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout);
 int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout);
+
+unsigned long call_imx_sip(unsigned long id, unsigned long reg0,
+			   unsigned long reg1, unsigned long reg2);
 #endif

arch/arm/lib/Makefile

@@ -32,7 +32,7 @@ endif
 
 obj-$(CONFIG_CPU_V7M) += cmd_boot.o
 obj-$(CONFIG_OF_LIBFDT) += bootm-fdt.o
-obj-$(CONFIG_CMD_BOOTI) += bootm.o
+obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o
 obj-$(CONFIG_CMD_BOOTM) += bootm.o
 obj-$(CONFIG_CMD_BOOTZ) += bootm.o zimage.o
 obj-$(CONFIG_SYS_L2_PL310) += cache-pl310.o

arch/arm/lib/crt0_aarch64_efi.S

@@ -8,6 +8,8 @@
  * This file is taken and modified from the gnu-efi project.
  */
 
+#include <asm-generic/pe.h>
+
 	.section	.text.head
 
 	/*
@@ -62,7 +64,7 @@ extra_header_fields:
 	 */
 	.long	_start - ImageBase		/* SizeOfHeaders */
 	.long	0				/* CheckSum */
-	.short	EFI_SUBSYSTEM			/* Subsystem */
+	.short	IMAGE_SUBSYSTEM_EFI_APPLICATION /* Subsystem */
 	.short	0				/* DllCharacteristics */
 	.quad	0				/* SizeOfStackReserve */
 	.quad	0				/* SizeOfStackCommit */

arch/arm/lib/crt0_arm_efi.S

@@ -8,6 +8,8 @@
  * This file is taken and modified from the gnu-efi project.
  */
 
+#include <asm-generic/pe.h>
+
 	.section	.text.head
 
 	/*
@@ -64,7 +66,7 @@ extra_header_fields:
 	 */
 	.long	_start - image_base		/* SizeOfHeaders */
 	.long	0				/* CheckSum */
-	.short	EFI_SUBSYSTEM			/* Subsystem */
+	.short	IMAGE_SUBSYSTEM_EFI_APPLICATION	/* Subsystem */
 	.short	0				/* DllCharacteristics */
 	.long	0				/* SizeOfStackReserve */
 	.long	0				/* SizeOfStackCommit */

arch/arm/lib/image.c

@@ -0,0 +1,77 @@
+/*
+ * (C) Copyright 2000-2009
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mapmem.h>
+#include <linux/sizes.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define LINUX_ARM64_IMAGE_MAGIC 0x644d5241
+
+/* See Documentation/arm64/booting.txt in the Linux kernel */
+struct Image_header {
+    uint32_t    code0;      /* Executable code */
+    uint32_t    code1;      /* Executable code */
+    uint64_t    text_offset;    /* Image load offset, LE */
+    uint64_t    image_size; /* Effective Image size, LE */
+    uint64_t    flags;      /* Kernel flags, LE */
+    uint64_t    res2;       /* reserved */
+    uint64_t    res3;       /* reserved */
+    uint64_t    res4;       /* reserved */
+    uint32_t    magic;      /* Magic number */
+    uint32_t    res5;
+};
+
+int booti_setup(ulong image, ulong *relocated_addr, ulong *size)
+{
+    struct Image_header *ih;
+    uint64_t dst;
+    uint64_t image_size, text_offset;
+
+    *relocated_addr = image;
+
+    ih = (struct Image_header *)map_sysmem(image, 0);
+
+    if (ih->magic != le32_to_cpu(LINUX_ARM64_IMAGE_MAGIC)) {
+        puts("Bad Linux ARM64 Image magic!\n");
+        return 1;
+    }
+
+    /*
+     * Prior to Linux commit a2c1d73b94ed, the text_offset field
+     * is of unknown endianness.  In these cases, the image_size
+     * field is zero, and we can assume a fixed value of 0x80000.
+     */
+    if (ih->image_size == 0) {
+        puts("Image lacks image_size field, assuming 16MiB\n");
+        image_size = 16 << 20;
+        text_offset = 0x80000;
+    } else {
+        image_size = le64_to_cpu(ih->image_size);
+        text_offset = le64_to_cpu(ih->text_offset);
+    }
+
+    *size = image_size;
+
+    /*
+     * If bit 3 of the flags field is set, the 2MB aligned base of the
+     * kernel image can be anywhere in physical memory, so respect
+     * images->ep.  Otherwise, relocate the image to the base of RAM
+     * since memory below it is not accessible via the linear mapping.
+     */
+    if (le64_to_cpu(ih->flags) & BIT(3))
+        dst = image - text_offset;
+    else
+        dst = gd->bd->bi_dram[0].start;
+
+    *relocated_addr = ALIGN(dst, SZ_2M) + text_offset;
+
+    unmap_sysmem(ih);
+
+    return 0;
+}

arch/arm/mach-at91/spl.c

@@ -87,18 +87,3 @@ u32 spl_boot_device(void)
 	return BOOT_DEVICE_NONE;
 }
 #endif
-
-u32 spl_boot_mode(const u32 boot_device)
-{
-	switch (boot_device) {
-#if defined(CONFIG_SYS_USE_MMC) || defined(CONFIG_SD_BOOT)
-	case BOOT_DEVICE_MMC1:
-	case BOOT_DEVICE_MMC2:
-		return MMCSD_MODE_FS;
-		break;
-#endif
-	case BOOT_DEVICE_NONE:
-	default:
-		hang();
-	}
-}

arch/arm/mach-davinci/Kconfig

@@ -54,7 +54,6 @@ config SYS_DA850_DDR_INIT
 config SOC_DA850
 	bool
 	select SOC_DA8XX
-	select SYS_DA850_DDR_INIT if SUPPORT_SPL || DA850_LOWLEVEL
 
 config SOC_DA8XX
 	bool
@@ -63,6 +62,89 @@ config SOC_DA8XX
 config MACH_DAVINCI_DA850_EVM
 	bool
 
+if SYS_DA850_PLL_INIT
+comment "DA850 PLL Initialization Parameters"
+
+config SYS_DV_CLKMODE
+	int "PLLCTL Clock Mode"
+	default 0
+	help
+	  Set PLLCTL Clock Mode bit as External Clock or On Chip oscillator
+
+config SYS_DA850_PLL0_POSTDIV
+	int "PLLC0 PLL Post-Divider"
+	default 1
+	help
+	  Value written to PLLC0 PLL Post-Divider Control Register
+
+config SYS_DA850_PLL0_PLLDIV1
+	hex "PLLC0 Divider 1"
+	default 0x8000
+	help
+	  Value written to PLLC0 Divider 1 register
+
+config SYS_DA850_PLL0_PLLDIV2
+	hex "PLLC0 Divider 2"
+	default 0x8001
+	help
+	  Value written to PLLC0 Divider 2 register
+
+config SYS_DA850_PLL0_PLLDIV3
+	hex "PLLC0 Divider 3"
+	default 0x8002
+	help
+	  Value written to PLLC0 Divider 3 register
+
+config SYS_DA850_PLL0_PLLDIV4
+	hex "PLLC0 Divider 4"
+	default 0x8003
+	help
+	  Value written to PLLC0 Divider 4 register
+
+config SYS_DA850_PLL0_PLLDIV5
+	hex "PLLC0 Divider 5"
+	default 0x8002
+	help
+	  Value written to PLLC0 Divider 5 register
+
+config SYS_DA850_PLL0_PLLDIV6
+	hex "PLLC0 Divider 6"
+	default 0x8000
+	help
+	  Value written to PLLC0 Divider 6 register
+
+config SYS_DA850_PLL0_PLLDIV7
+	hex "PLLC0 Divider 7"
+	default 0x8005
+	help
+	  Value written to PLLC0 Divider 7 register
+
+config SYS_DA850_PLL1_POSTDIV
+	hex "PLLC1 PLL Post-Divider"
+	default 1
+	help
+	  Value written to PLLC1 PLL Post-Divider Control Register
+
+config SYS_DA850_PLL1_PLLDIV1
+	hex "PLLC1 Divider 2"
+	default 0x8000
+	help
+	  Value written to PLLC1 Divider 1 register
+
+config SYS_DA850_PLL1_PLLDIV2
+	hex "PLLC1 Divider 2"
+	default 0x8001
+	help
+	  Value written to PLLC1 Divider 2 register
+
+config SYS_DA850_PLL1_PLLDIV3
+	hex "PLLC1 Divider 3"
+	default 0x8002
+	help
+	  Value written to PLLC1 Divider 3 register
+
+endif
+
 source "board/Barix/ipam390/Kconfig"
 source "board/davinci/da8xxevm/Kconfig"
 source "board/davinci/ea20/Kconfig"

arch/arm/mach-davinci/spl.c

@@ -45,11 +45,6 @@ void spl_board_init(void)
 	preloader_console_init();
 }
 
-u32 spl_boot_mode(const u32 boot_device)
-{
-	return MMCSD_MODE_RAW;
-}
-
 u32 spl_boot_device(void)
 {
 	switch (davinci_syscfg_regs->bootcfg) {

arch/arm/mach-imx/Makefile

@@ -7,30 +7,41 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 vf610))
+ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 mx8m vf610))
 obj-y	= iomux-v3.o
 endif
+
+ifeq ($(SOC),$(filter $(SOC),mx8m))
+obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
+obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o
+obj-$(CONFIG_FEC_MXC) += mac.o
+obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
+obj-y += cpu.o
+endif
+
 ifeq ($(SOC),$(filter $(SOC),mx5 mx6))
 obj-y	+= cpu.o speed.o
 obj-$(CONFIG_GPT_TIMER) += timer.o
 obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
 endif
-ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs))
+ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs mx8m))
 obj-y	+= misc.o
 obj-$(CONFIG_SPL_BUILD)	+= spl.o
 endif
 ifeq ($(SOC),$(filter $(SOC),mx7))
 obj-y 	+= cpu.o
 obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
+obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o
 endif
 ifeq ($(SOC),$(filter $(SOC),mx6 mx7))
 obj-y 	+= cache.o init.o
-obj-$(CONFIG_SATA) += sata.o
+obj-$(CONFIG_FEC_MXC) += mac.o
 obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
 obj-$(CONFIG_IMX_RDC) += rdc-sema.o
 ifneq ($(CONFIG_SPL_BUILD),y)
 obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
 endif
+obj-$(CONFIG_SATA) += sata.o
 obj-$(CONFIG_SECURE_BOOT)    += hab.o
 obj-$(CONFIG_SYSCOUNTER_TIMER) += syscounter.o
 endif
@@ -124,8 +135,10 @@ spl/u-boot-nand-spl.imx: SPL FORCE
 
 targets += $(addprefix ../../../,$(IMX_CONFIG) SPL u-boot.uim spl/u-boot-nand-spl.imx)
 
+obj-$(CONFIG_ARM64) += sip.o
+
 obj-$(CONFIG_MX5) += mx5/
 obj-$(CONFIG_MX6) += mx6/
 obj-$(CONFIG_MX7) += mx7/
 obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/
-
+obj-$(CONFIG_MX8M) += mx8m/

arch/arm/mach-imx/cpu.c

@@ -16,6 +16,7 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/crm_regs.h>
+#include <asm/mach-imx/boot_mode.h>
 #include <imx_thermal.h>
 #include <ipu_pixfmt.h>
 #include <thermal.h>
@@ -62,6 +63,11 @@ static char *get_reset_cause(void)
 		return "WDOG4";
 	case 0x00200:
 		return "TEMPSENSE";
+#elif defined(CONFIG_MX8M)
+	case 0x00100:
+		return "WDOG2";
+	case 0x00200:
+		return "TEMPSENSE";
 #else
 	case 0x00100:
 		return "TEMPSENSE";
@@ -137,6 +143,8 @@ unsigned imx_ddr_size(void)
 const char *get_imx_type(u32 imxtype)
 {
 	switch (imxtype) {
+	case MXC_CPU_MX8MQ:
+		return "8MQ";	/* Quad-core version of the mx8m */
 	case MXC_CPU_MX7S:
 		return "7S";	/* Single-core version of the mx7 */
 	case MXC_CPU_MX7D:
@@ -259,7 +267,7 @@ int cpu_mmc_init(bd_t *bis)
 }
 #endif
 
-#ifndef CONFIG_MX7
+#if !(defined(CONFIG_MX7) || defined(CONFIG_MX8M))
 u32 get_ahb_clk(void)
 {
 	struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
@@ -293,6 +301,7 @@ void arch_preboot_os(void)
 #endif
 }
 
+#ifndef CONFIG_MX8M
 void set_chipselect_size(int const cs_size)
 {
 	unsigned int reg;
@@ -323,6 +332,125 @@ void set_chipselect_size(int const cs_size)
 
 	writel(reg, &iomuxc_regs->gpr[1]);
 }
+#endif
+
+#if defined(CONFIG_MX7) || defined(CONFIG_MX8M)
+/*
+ * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
+ * defines a 2-bit SPEED_GRADING
+ */
+#define OCOTP_TESTER3_SPEED_SHIFT	8
+enum cpu_speed {
+	OCOTP_TESTER3_SPEED_GRADE0,
+	OCOTP_TESTER3_SPEED_GRADE1,
+	OCOTP_TESTER3_SPEED_GRADE2,
+	OCOTP_TESTER3_SPEED_GRADE3,
+};
+
+u32 get_cpu_speed_grade_hz(void)
+{
+	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+	struct fuse_bank *bank = &ocotp->bank[1];
+	struct fuse_bank1_regs *fuse =
+		(struct fuse_bank1_regs *)bank->fuse_regs;
+	uint32_t val;
+
+	val = readl(&fuse->tester3);
+	val >>= OCOTP_TESTER3_SPEED_SHIFT;
+	val &= 0x3;
+
+	switch(val) {
+	case OCOTP_TESTER3_SPEED_GRADE0:
+		return 800000000;
+	case OCOTP_TESTER3_SPEED_GRADE1:
+		return is_mx7() ? 500000000 : 1000000000;
+	case OCOTP_TESTER3_SPEED_GRADE2:
+		return is_mx7() ? 1000000000 : 1300000000;
+	case OCOTP_TESTER3_SPEED_GRADE3:
+		return is_mx7() ? 1200000000 : 1500000000;
+	}
+
+	return 0;
+}
+
+/*
+ * OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
+ * defines a 2-bit SPEED_GRADING
+ */
+#define OCOTP_TESTER3_TEMP_SHIFT	6
+
+u32 get_cpu_temp_grade(int *minc, int *maxc)
+{
+	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+	struct fuse_bank *bank = &ocotp->bank[1];
+	struct fuse_bank1_regs *fuse =
+		(struct fuse_bank1_regs *)bank->fuse_regs;
+	uint32_t val;
+
+	val = readl(&fuse->tester3);
+	val >>= OCOTP_TESTER3_TEMP_SHIFT;
+	val &= 0x3;
+
+	if (minc && maxc) {
+		if (val == TEMP_AUTOMOTIVE) {
+			*minc = -40;
+			*maxc = 125;
+		} else if (val == TEMP_INDUSTRIAL) {
+			*minc = -40;
+			*maxc = 105;
+		} else if (val == TEMP_EXTCOMMERCIAL) {
+			*minc = -20;
+			*maxc = 105;
+		} else {
+			*minc = 0;
+			*maxc = 95;
+		}
+	}
+	return val;
+}
+#endif
+
+#if defined(CONFIG_MX7) || defined(CONFIG_MX8M)
+enum boot_device get_boot_device(void)
+{
+	struct bootrom_sw_info **p =
+		(struct bootrom_sw_info **)(ulong)ROM_SW_INFO_ADDR;
+
+	enum boot_device boot_dev = SD1_BOOT;
+	u8 boot_type = (*p)->boot_dev_type;
+	u8 boot_instance = (*p)->boot_dev_instance;
+
+	switch (boot_type) {
+	case BOOT_TYPE_SD:
+		boot_dev = boot_instance + SD1_BOOT;
+		break;
+	case BOOT_TYPE_MMC:
+		boot_dev = boot_instance + MMC1_BOOT;
+		break;
+	case BOOT_TYPE_NAND:
+		boot_dev = NAND_BOOT;
+		break;
+	case BOOT_TYPE_QSPI:
+		boot_dev = QSPI_BOOT;
+		break;
+	case BOOT_TYPE_WEIM:
+		boot_dev = WEIM_NOR_BOOT;
+		break;
+	case BOOT_TYPE_SPINOR:
+		boot_dev = SPI_NOR_BOOT;
+		break;
+#ifdef CONFIG_MX8M
+	case BOOT_TYPE_USB:
+		boot_dev = USB_BOOT;
+		break;
+#endif
+	default:
+		break;
+	}
+
+	return boot_dev;
+}
+#endif
 
 #ifdef CONFIG_NXP_BOARD_REVISION
 int nxp_board_rev(void)

arch/arm/mach-imx/imx_bootaux.c

@@ -5,21 +5,51 @@
  */
 
 #include <common.h>
+#include <asm/io.h>
+#include <asm/mach-imx/sys_proto.h>
 #include <command.h>
+#include <imx_sip.h>
 #include <linux/compiler.h>
 
-/* Allow for arch specific config before we boot */
-int __weak arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
+int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
 {
-	/* please define platform specific arch_auxiliary_core_up() */
-	return CMD_RET_FAILURE;
+	ulong stack, pc;
+
+	if (!boot_private_data)
+		return -EINVAL;
+
+	stack = *(ulong *)boot_private_data;
+	pc = *(ulong *)(boot_private_data + 4);
+
+	/* Set the stack and pc to M4 bootROM */
+	writel(stack, M4_BOOTROM_BASE_ADDR);
+	writel(pc, M4_BOOTROM_BASE_ADDR + 4);
+
+	/* Enable M4 */
+#ifdef CONFIG_MX8M
+	call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0);
+#else
+	clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET,
+			SRC_M4C_NON_SCLR_RST_MASK, SRC_M4_ENABLE_MASK);
+#endif
+
+	return 0;
 }
 
-/* Allow for arch specific config before we boot */
-int __weak arch_auxiliary_core_check_up(u32 core_id)
+int arch_auxiliary_core_check_up(u32 core_id)
 {
-	/* please define platform specific arch_auxiliary_core_check_up() */
-	return 0;
+#ifdef CONFIG_MX8M
+	return call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0);
+#else
+	unsigned int val;
+
+	val = readl(SRC_BASE_ADDR + SRC_M4_REG_OFFSET);
+
+	if (val & SRC_M4C_NON_SCLR_RST_MASK)
+		return 0;  /* assert in reset */
+
+	return 1;
+#endif
 }
 
 /*

arch/arm/mach-imx/mac.c

@@ -0,0 +1,61 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * Peng Fan <peng.fan@nxp.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <errno.h>
+
+struct imx_mac_fuse {
+	u32 mac_addr0;
+	u32 rsvd0[3];
+	u32 mac_addr1;
+	u32 rsvd1[3];
+	u32 mac_addr2;
+	u32 rsvd2[7];
+};
+
+#define MAC_FUSE_MX6_OFFSET	0x620
+#define MAC_FUSE_MX7_OFFSET	0x640
+
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+{
+	struct imx_mac_fuse *fuse;
+	u32 offset;
+	bool has_second_mac;
+
+	offset = is_mx6() ? MAC_FUSE_MX6_OFFSET : MAC_FUSE_MX7_OFFSET;
+	fuse = (struct imx_mac_fuse *)(ulong)(OCOTP_BASE_ADDR + offset);
+	has_second_mac = is_mx7() || is_mx6sx() || is_mx6ul() || is_mx6ull();
+
+	if (has_second_mac && dev_id == 1) {
+		u32 value = readl(&fuse->mac_addr2);
+
+		mac[0] = value >> 24;
+		mac[1] = value >> 16;
+		mac[2] = value >> 8;
+		mac[3] = value;
+
+		value = readl(&fuse->mac_addr1);
+		mac[4] = value >> 24;
+		mac[5] = value >> 16;
+
+	} else {
+		u32 value = readl(&fuse->mac_addr1);
+
+		mac[0] = value >> 8;
+		mac[1] = value;
+
+		value = readl(&fuse->mac_addr0);
+		mac[2] = value >> 24;
+		mac[3] = value >> 16;
+		mac[4] = value >> 8;
+		mac[5] = value;
+	}
+}

arch/arm/mach-imx/mmc_env.c

@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <asm/mach-imx/boot_mode.h>
+
+__weak int board_mmc_get_env_dev(int devno)
+{
+	return CONFIG_SYS_MMC_ENV_DEV;
+}
+
+int mmc_get_env_dev(void)
+{
+	struct bootrom_sw_info **p =
+		(struct bootrom_sw_info **)(ulong)ROM_SW_INFO_ADDR;
+	int devno = (*p)->boot_dev_instance;
+	u8 boot_type = (*p)->boot_dev_type;
+
+	/* If not boot from sd/mmc, use default value */
+	if ((boot_type != BOOT_TYPE_SD) && (boot_type != BOOT_TYPE_MMC))
+		return CONFIG_SYS_MMC_ENV_DEV;
+
+	return board_mmc_get_env_dev(devno);
+}

arch/arm/mach-imx/mx5/Makefile

@@ -9,3 +9,8 @@
 
 obj-y := soc.o clock.o
 obj-y += lowlevel_init.o
+
+# common files for mx53 dram initialization
+obj-$(CONFIG_TARGET_M53EVK)     += mx53_dram.o
+obj-$(CONFIG_TARGET_MX53CX9020) += mx53_dram.o
+obj-$(CONFIG_TARGET_MX53LOCO)   += mx53_dram.o

arch/arm/mach-imx/mx5/mx53_dram.c

@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) 2017  Beckhoff Automation GmbH & Co. KG
+ * Patrick Bruenn <p.bruenn@beckhoff.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+phys_size_t get_effective_memsize(void)
+{
+	/*
+	 * WARNING: We must override get_effective_memsize() function here
+	 * to report only the size of the first DRAM bank. This is to make
+	 * U-Boot relocator place U-Boot into valid memory, that is, at the
+	 * end of the first DRAM bank. If we did not override this function
+	 * like so, U-Boot would be placed at the address of the first DRAM
+	 * bank + total DRAM size - sizeof(uboot), which in the setup where
+	 * each DRAM bank contains 512MiB of DRAM would result in placing
+	 * U-Boot into invalid memory area close to the end of the first
+	 * DRAM bank.
+	 */
+	return get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
+	gd->ram_size += get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
+
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
+
+	return 0;
+}

arch/arm/mach-imx/mx6/soc.c

@@ -518,40 +518,6 @@ int board_postclk_init(void)
 	return 0;
 }
 
-#if defined(CONFIG_FEC_MXC)
-void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
-{
-	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
-	struct fuse_bank *bank = &ocotp->bank[4];
-	struct fuse_bank4_regs *fuse =
-			(struct fuse_bank4_regs *)bank->fuse_regs;
-
-	if ((is_mx6sx() || is_mx6ul() || is_mx6ull()) && dev_id == 1) {
-		u32 value = readl(&fuse->mac_addr2);
-		mac[0] = value >> 24 ;
-		mac[1] = value >> 16 ;
-		mac[2] = value >> 8 ;
-		mac[3] = value ;
-
-		value = readl(&fuse->mac_addr1);
-		mac[4] = value >> 24 ;
-		mac[5] = value >> 16 ;
-		
-	} else {
-		u32 value = readl(&fuse->mac_addr1);
-		mac[0] = (value >> 8);
-		mac[1] = value ;
-
-		value = readl(&fuse->mac_addr0);
-		mac[2] = value >> 24 ;
-		mac[3] = value >> 16 ;
-		mac[4] = value >> 8 ;
-		mac[5] = value ;
-	}
-
-}
-#endif
-
 #ifndef CONFIG_SPL_BUILD
 /*
  * cfg_val will be used for
@@ -700,41 +666,3 @@ void gpr_init(void)
 		writel(0x007F007F, &iomux->gpr[7]);
 	}
 }
-
-#ifdef CONFIG_IMX_BOOTAUX
-int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
-{
-	struct src *src_reg;
-	u32 stack, pc;
-
-	if (!boot_private_data)
-		return -EINVAL;
-
-	stack = *(u32 *)boot_private_data;
-	pc = *(u32 *)(boot_private_data + 4);
-
-	/* Set the stack and pc to M4 bootROM */
-	writel(stack, M4_BOOTROM_BASE_ADDR);
-	writel(pc, M4_BOOTROM_BASE_ADDR + 4);
-
-	/* Enable M4 */
-	src_reg = (struct src *)SRC_BASE_ADDR;
-	clrsetbits_le32(&src_reg->scr, SRC_SCR_M4C_NON_SCLR_RST_MASK,
-			SRC_SCR_M4_ENABLE_MASK);
-
-	return 0;
-}
-
-int arch_auxiliary_core_check_up(u32 core_id)
-{
-	struct src *src_reg = (struct src *)SRC_BASE_ADDR;
-	unsigned val;
-
-	val = readl(&src_reg->scr);
-
-	if (val & SRC_SCR_M4C_NON_SCLR_RST_MASK)
-		return 0;  /* assert in reset */
-
-	return 1;
-}
-#endif

arch/arm/mach-imx/mx7/psci-mx7.c

@@ -10,7 +10,7 @@
 #include <asm/secure.h>
 #include <asm/arch/imx-regs.h>
 #include <common.h>
-
+#include <fsl_wdog.h>
 
 #define GPC_CPU_PGC_SW_PDN_REQ	0xfc
 #define GPC_CPU_PGC_SW_PUP_REQ	0xf0
@@ -26,6 +26,15 @@
 #define BP_SRC_A7RCR0_A7_CORE_RESET0	0
 #define BP_SRC_A7RCR1_A7_CORE1_ENABLE	1
 
+#define SNVS_LPCR		0x38
+#define BP_SNVS_LPCR_DP_EN	0x20
+#define BP_SNVS_LPCR_TOP	0x40
+
+#define CCM_CCGR_SNVS		0x4250
+
+#define CCM_ROOT_WDOG		0xbb80
+#define CCM_CCGR_WDOG1		0x49c0
+
 static inline void imx_gpcv2_set_m_core_pgc(bool enable, u32 offset)
 {
 	writel(enable, GPC_IPS_BASE_ADDR + offset);
@@ -74,3 +83,25 @@ __secure int imx_cpu_off(int cpu)
 	writel(0, SRC_BASE_ADDR + cpu * 8 + SRC_GPR1_MX7D + 4);
 	return 0;
 }
+
+__secure void imx_system_reset(void)
+{
+	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+	/* make sure WDOG1 clock is enabled */
+	writel(0x1 << 28, CCM_BASE_ADDR + CCM_ROOT_WDOG);
+	writel(0x3, CCM_BASE_ADDR + CCM_CCGR_WDOG1);
+	writew(WCR_WDE, &wdog->wcr);
+}
+
+__secure void imx_system_off(void)
+{
+	u32 val;
+
+	/* make sure SNVS clock is enabled */
+	writel(0x3, CCM_BASE_ADDR + CCM_CCGR_SNVS);
+
+	val = readl(SNVS_BASE_ADDR + SNVS_LPCR);
+	val |= BP_SNVS_LPCR_DP_EN | BP_SNVS_LPCR_TOP;
+	writel(val, SNVS_BASE_ADDR + SNVS_LPCR);
+}

arch/arm/mach-imx/mx7/psci.S

@@ -43,4 +43,18 @@ psci_cpu_off:
 1: 	wfi
 	b 1b
 
+.globl psci_system_reset
+psci_system_reset:
+	bl	imx_system_reset
+
+2: 	wfi
+	b 2b
+
+.globl psci_system_off
+psci_system_off:
+	bl	imx_system_off
+
+3: 	wfi
+	b 3b
+
 	.popsection

arch/arm/mach-imx/mx7/soc.c

@@ -17,6 +17,7 @@
 #include <asm/arch/crm_regs.h>
 #include <dm.h>
 #include <imx_thermal.h>
+#include <fsl_sec.h>
 
 #if defined(CONFIG_IMX_THERMAL)
 static const struct imx_thermal_plat imx7_thermal_plat = {
@@ -97,77 +98,6 @@ struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
 };
 #endif
 
-/*
- * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
- * defines a 2-bit SPEED_GRADING
- */
-#define OCOTP_TESTER3_SPEED_SHIFT	8
-#define OCOTP_TESTER3_SPEED_800MHZ	0
-#define OCOTP_TESTER3_SPEED_500MHZ	1
-#define OCOTP_TESTER3_SPEED_1GHZ	2
-#define OCOTP_TESTER3_SPEED_1P2GHZ	3
-
-u32 get_cpu_speed_grade_hz(void)
-{
-	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
-	struct fuse_bank *bank = &ocotp->bank[1];
-	struct fuse_bank1_regs *fuse =
-		(struct fuse_bank1_regs *)bank->fuse_regs;
-	uint32_t val;
-
-	val = readl(&fuse->tester3);
-	val >>= OCOTP_TESTER3_SPEED_SHIFT;
-	val &= 0x3;
-
-	switch(val) {
-	case OCOTP_TESTER3_SPEED_800MHZ:
-		return 800000000;
-	case OCOTP_TESTER3_SPEED_500MHZ:
-		return 500000000;
-	case OCOTP_TESTER3_SPEED_1GHZ:
-		return 1000000000;
-	case OCOTP_TESTER3_SPEED_1P2GHZ:
-		return 1200000000;
-	}
-	return 0;
-}
-
-/*
- * OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
- * defines a 2-bit SPEED_GRADING
- */
-#define OCOTP_TESTER3_TEMP_SHIFT	6
-
-u32 get_cpu_temp_grade(int *minc, int *maxc)
-{
-	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
-	struct fuse_bank *bank = &ocotp->bank[1];
-	struct fuse_bank1_regs *fuse =
-		(struct fuse_bank1_regs *)bank->fuse_regs;
-	uint32_t val;
-
-	val = readl(&fuse->tester3);
-	val >>= OCOTP_TESTER3_TEMP_SHIFT;
-	val &= 0x3;
-
-	if (minc && maxc) {
-		if (val == TEMP_AUTOMOTIVE) {
-			*minc = -40;
-			*maxc = 125;
-		} else if (val == TEMP_INDUSTRIAL) {
-			*minc = -40;
-			*maxc = 105;
-		} else if (val == TEMP_EXTCOMMERCIAL) {
-			*minc = -20;
-			*maxc = 105;
-		} else {
-			*minc = 0;
-			*maxc = 95;
-		}
-	}
-	return val;
-}
-
 static bool is_mx7d(void)
 {
 	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
@@ -262,6 +192,10 @@ int arch_misc_init(void)
 		env_set("soc", "imx7s");
 #endif
 
+#ifdef CONFIG_FSL_CAAM
+	sec_init();
+#endif
+
 	return 0;
 }
 #endif
@@ -279,74 +213,6 @@ void get_board_serial(struct tag_serialnr *serialnr)
 }
 #endif
 
-#if defined(CONFIG_FEC_MXC)
-void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
-{
-	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
-	struct fuse_bank *bank = &ocotp->bank[9];
-	struct fuse_bank9_regs *fuse =
-		(struct fuse_bank9_regs *)bank->fuse_regs;
-
-	if (0 == dev_id) {
-		u32 value = readl(&fuse->mac_addr1);
-		mac[0] = (value >> 8);
-		mac[1] = value;
-
-		value = readl(&fuse->mac_addr0);
-		mac[2] = value >> 24;
-		mac[3] = value >> 16;
-		mac[4] = value >> 8;
-		mac[5] = value;
-	} else {
-		u32 value = readl(&fuse->mac_addr2);
-		mac[0] = value >> 24;
-		mac[1] = value >> 16;
-		mac[2] = value >> 8;
-		mac[3] = value;
-
-		value = readl(&fuse->mac_addr1);
-		mac[4] = value >> 24;
-		mac[5] = value >> 16;
-	}
-}
-#endif
-
-#ifdef CONFIG_IMX_BOOTAUX
-int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
-{
-	u32 stack, pc;
-	struct src *src_reg = (struct src *)SRC_BASE_ADDR;
-
-	if (!boot_private_data)
-		return 1;
-
-	stack = *(u32 *)boot_private_data;
-	pc = *(u32 *)(boot_private_data + 4);
-
-	/* Set the stack and pc to M4 bootROM */
-	writel(stack, M4_BOOTROM_BASE_ADDR);
-	writel(pc, M4_BOOTROM_BASE_ADDR + 4);
-
-	/* Enable M4 */
-	clrsetbits_le32(&src_reg->m4rcr, SRC_M4RCR_M4C_NON_SCLR_RST_MASK,
-			SRC_M4RCR_ENABLE_M4_MASK);
-
-	return 0;
-}
-
-int arch_auxiliary_core_check_up(u32 core_id)
-{
-	uint32_t val;
-	struct src *src_reg = (struct src *)SRC_BASE_ADDR;
-
-	val = readl(&src_reg->m4rcr);
-	if (val & 0x00000001)
-		return 0; /* assert in reset */
-
-	return 1;
-}
-#endif
-
 void set_wdog_reset(struct wdog_regs *wdog)
 {
 	u32 reg = readw(&wdog->wcr);
@@ -389,62 +255,6 @@ const struct boot_mode soc_boot_modes[] = {
 	{NULL,		0},
 };
 
-enum boot_device get_boot_device(void)
-{
-	struct bootrom_sw_info **p =
-		(struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
-
-	enum boot_device boot_dev = SD1_BOOT;
-	u8 boot_type = (*p)->boot_dev_type;
-	u8 boot_instance = (*p)->boot_dev_instance;
-
-	switch (boot_type) {
-	case BOOT_TYPE_SD:
-		boot_dev = boot_instance + SD1_BOOT;
-		break;
-	case BOOT_TYPE_MMC:
-		boot_dev = boot_instance + MMC1_BOOT;
-		break;
-	case BOOT_TYPE_NAND:
-		boot_dev = NAND_BOOT;
-		break;
-	case BOOT_TYPE_QSPI:
-		boot_dev = QSPI_BOOT;
-		break;
-	case BOOT_TYPE_WEIM:
-		boot_dev = WEIM_NOR_BOOT;
-		break;
-	case BOOT_TYPE_SPINOR:
-		boot_dev = SPI_NOR_BOOT;
-		break;
-	default:
-		break;
-	}
-
-	return boot_dev;
-}
-
-#ifdef CONFIG_ENV_IS_IN_MMC
-__weak int board_mmc_get_env_dev(int devno)
-{
-	return CONFIG_SYS_MMC_ENV_DEV;
-}
-
-int mmc_get_env_dev(void)
-{
-	struct bootrom_sw_info **p =
-		(struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
-	int devno = (*p)->boot_dev_instance;
-	u8 boot_type = (*p)->boot_dev_type;
-
-	/* If not boot from sd/mmc, use default value */
-	if ((boot_type != BOOT_TYPE_SD) && (boot_type != BOOT_TYPE_MMC))
-		return CONFIG_SYS_MMC_ENV_DEV;
-
-	return board_mmc_get_env_dev(devno);
-}
-#endif
-
 void s_init(void)
 {
 #if !defined CONFIG_SPL_BUILD

arch/arm/mach-imx/mx8m/Kconfig

@@ -0,0 +1,10 @@
+if ARCH_MX8M
+
+config MX8M
+	bool
+	select ROM_UNIFIED_SECTIONS
+
+config SYS_SOC
+	default "mx8m"
+
+endif

arch/arm/mach-imx/mx8m/Makefile

@@ -0,0 +1,8 @@
+#
+# Copyright 2017 NXP
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += lowlevel_init.o
+obj-y += clock.o clock_slice.o soc.o

arch/arm/mach-imx/mx8m/clock.c

@@ -0,0 +1,795 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * Peng Fan <peng.fan@nxp.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <errno.h>
+#include <linux/iopoll.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
+
+static u32 decode_frac_pll(enum clk_root_src frac_pll)
+{
+	u32 pll_cfg0, pll_cfg1, pllout;
+	u32 pll_refclk_sel, pll_refclk;
+	u32 divr_val, divq_val, divf_val, divff, divfi;
+	u32 pllout_div_shift, pllout_div_mask, pllout_div;
+
+	switch (frac_pll) {
+	case ARM_PLL_CLK:
+		pll_cfg0 = readl(&ana_pll->arm_pll_cfg0);
+		pll_cfg1 = readl(&ana_pll->arm_pll_cfg1);
+		pllout_div_shift = HW_FRAC_ARM_PLL_DIV_SHIFT;
+		pllout_div_mask = HW_FRAC_ARM_PLL_DIV_MASK;
+		break;
+	default:
+		printf("Frac PLL %d not supporte\n", frac_pll);
+		return 0;
+	}
+
+	pllout_div = readl(&ana_pll->frac_pllout_div_cfg);
+	pllout_div = (pllout_div & pllout_div_mask) >> pllout_div_shift;
+
+	/* Power down */
+	if (pll_cfg0 & FRAC_PLL_PD_MASK)
+		return 0;
+
+	/* output not enabled */
+	if ((pll_cfg0 & FRAC_PLL_CLKE_MASK) == 0)
+		return 0;
+
+	pll_refclk_sel = pll_cfg0 & FRAC_PLL_REFCLK_SEL_MASK;
+
+	if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_OSC_25M)
+		pll_refclk = 25000000u;
+	else if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_OSC_27M)
+		pll_refclk = 27000000u;
+	else if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_HDMI_PHY_27M)
+		pll_refclk = 27000000u;
+	else
+		pll_refclk = 0;
+
+	if (pll_cfg0 & FRAC_PLL_BYPASS_MASK)
+		return pll_refclk;
+
+	divr_val = (pll_cfg0 & FRAC_PLL_REFCLK_DIV_VAL_MASK) >>
+		FRAC_PLL_REFCLK_DIV_VAL_SHIFT;
+	divq_val = pll_cfg0 & FRAC_PLL_OUTPUT_DIV_VAL_MASK;
+
+	divff = (pll_cfg1 & FRAC_PLL_FRAC_DIV_CTL_MASK) >>
+		FRAC_PLL_FRAC_DIV_CTL_SHIFT;
+	divfi = pll_cfg1 & FRAC_PLL_INT_DIV_CTL_MASK;
+
+	divf_val = 1 + divfi + divff / (1 << 24);
+
+	pllout = pll_refclk / (divr_val + 1) * 8 * divf_val /
+		((divq_val + 1) * 2);
+
+	return pllout / (pllout_div + 1);
+}
+
+static u32 decode_sscg_pll(enum clk_root_src sscg_pll)
+{
+	u32 pll_cfg0, pll_cfg1, pll_cfg2;
+	u32 pll_refclk_sel, pll_refclk;
+	u32 divr1, divr2, divf1, divf2, divq, div;
+	u32 sse;
+	u32 pll_clke;
+	u32 pllout_div_shift, pllout_div_mask, pllout_div;
+	u32 pllout;
+
+	switch (sscg_pll) {
+	case SYSTEM_PLL1_800M_CLK:
+	case SYSTEM_PLL1_400M_CLK:
+	case SYSTEM_PLL1_266M_CLK:
+	case SYSTEM_PLL1_200M_CLK:
+	case SYSTEM_PLL1_160M_CLK:
+	case SYSTEM_PLL1_133M_CLK:
+	case SYSTEM_PLL1_100M_CLK:
+	case SYSTEM_PLL1_80M_CLK:
+	case SYSTEM_PLL1_40M_CLK:
+		pll_cfg0 = readl(&ana_pll->sys_pll1_cfg0);
+		pll_cfg1 = readl(&ana_pll->sys_pll1_cfg1);
+		pll_cfg2 = readl(&ana_pll->sys_pll1_cfg2);
+		pllout_div_shift = HW_SSCG_SYSTEM_PLL1_DIV_SHIFT;
+		pllout_div_mask = HW_SSCG_SYSTEM_PLL1_DIV_MASK;
+		break;
+	case SYSTEM_PLL2_1000M_CLK:
+	case SYSTEM_PLL2_500M_CLK:
+	case SYSTEM_PLL2_333M_CLK:
+	case SYSTEM_PLL2_250M_CLK:
+	case SYSTEM_PLL2_200M_CLK:
+	case SYSTEM_PLL2_166M_CLK:
+	case SYSTEM_PLL2_125M_CLK:
+	case SYSTEM_PLL2_100M_CLK:
+	case SYSTEM_PLL2_50M_CLK:
+		pll_cfg0 = readl(&ana_pll->sys_pll2_cfg0);
+		pll_cfg1 = readl(&ana_pll->sys_pll2_cfg1);
+		pll_cfg2 = readl(&ana_pll->sys_pll2_cfg2);
+		pllout_div_shift = HW_SSCG_SYSTEM_PLL2_DIV_SHIFT;
+		pllout_div_mask = HW_SSCG_SYSTEM_PLL2_DIV_MASK;
+		break;
+	case SYSTEM_PLL3_CLK:
+		pll_cfg0 = readl(&ana_pll->sys_pll3_cfg0);
+		pll_cfg1 = readl(&ana_pll->sys_pll3_cfg1);
+		pll_cfg2 = readl(&ana_pll->sys_pll3_cfg2);
+		pllout_div_shift = HW_SSCG_SYSTEM_PLL3_DIV_SHIFT;
+		pllout_div_mask = HW_SSCG_SYSTEM_PLL3_DIV_MASK;
+		break;
+	case DRAM_PLL1_CLK:
+		pll_cfg0 = readl(&ana_pll->dram_pll_cfg0);
+		pll_cfg1 = readl(&ana_pll->dram_pll_cfg1);
+		pll_cfg2 = readl(&ana_pll->dram_pll_cfg2);
+		pllout_div_shift = HW_SSCG_DRAM_PLL_DIV_SHIFT;
+		pllout_div_mask = HW_SSCG_DRAM_PLL_DIV_MASK;
+		break;
+	default:
+		printf("sscg pll %d not supporte\n", sscg_pll);
+		return 0;
+	}
+
+	switch (sscg_pll) {
+	case DRAM_PLL1_CLK:
+		pll_clke = SSCG_PLL_DRAM_PLL_CLKE_MASK;
+		div = 1;
+		break;
+	case SYSTEM_PLL3_CLK:
+		pll_clke = SSCG_PLL_PLL3_CLKE_MASK;
+		div = 1;
+		break;
+	case SYSTEM_PLL2_1000M_CLK:
+	case SYSTEM_PLL1_800M_CLK:
+		pll_clke = SSCG_PLL_CLKE_MASK;
+		div = 1;
+		break;
+	case SYSTEM_PLL2_500M_CLK:
+	case SYSTEM_PLL1_400M_CLK:
+		pll_clke = SSCG_PLL_DIV2_CLKE_MASK;
+		div = 2;
+		break;
+	case SYSTEM_PLL2_333M_CLK:
+	case SYSTEM_PLL1_266M_CLK:
+		pll_clke = SSCG_PLL_DIV3_CLKE_MASK;
+		div = 3;
+		break;
+	case SYSTEM_PLL2_250M_CLK:
+	case SYSTEM_PLL1_200M_CLK:
+		pll_clke = SSCG_PLL_DIV4_CLKE_MASK;
+		div = 4;
+		break;
+	case SYSTEM_PLL2_200M_CLK:
+	case SYSTEM_PLL1_160M_CLK:
+		pll_clke = SSCG_PLL_DIV5_CLKE_MASK;
+		div = 5;
+		break;
+	case SYSTEM_PLL2_166M_CLK:
+	case SYSTEM_PLL1_133M_CLK:
+		pll_clke = SSCG_PLL_DIV6_CLKE_MASK;
+		div = 6;
+		break;
+	case SYSTEM_PLL2_125M_CLK:
+	case SYSTEM_PLL1_100M_CLK:
+		pll_clke = SSCG_PLL_DIV8_CLKE_MASK;
+		div = 8;
+		break;
+	case SYSTEM_PLL2_100M_CLK:
+	case SYSTEM_PLL1_80M_CLK:
+		pll_clke = SSCG_PLL_DIV10_CLKE_MASK;
+		div = 10;
+		break;
+	case SYSTEM_PLL2_50M_CLK:
+	case SYSTEM_PLL1_40M_CLK:
+		pll_clke = SSCG_PLL_DIV20_CLKE_MASK;
+		div = 20;
+		break;
+	default:
+		printf("sscg pll %d not supporte\n", sscg_pll);
+		return 0;
+	}
+
+	/* Power down */
+	if (pll_cfg0 & SSCG_PLL_PD_MASK)
+		return 0;
+
+	/* output not enabled */
+	if ((pll_cfg0 & pll_clke) == 0)
+		return 0;
+
+	pllout_div = readl(&ana_pll->sscg_pllout_div_cfg);
+	pllout_div = (pllout_div & pllout_div_mask) >> pllout_div_shift;
+
+	pll_refclk_sel = pll_cfg0 & SSCG_PLL_REFCLK_SEL_MASK;
+
+	if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_OSC_25M)
+		pll_refclk = 25000000u;
+	else if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_OSC_27M)
+		pll_refclk = 27000000u;
+	else if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M)
+		pll_refclk = 27000000u;
+	else
+		pll_refclk = 0;
+
+	/* We assume bypass1/2 are the same value */
+	if ((pll_cfg0 & SSCG_PLL_BYPASS1_MASK) ||
+	    (pll_cfg0 & SSCG_PLL_BYPASS2_MASK))
+		return pll_refclk;
+
+	divr1 = (pll_cfg2 & SSCG_PLL_REF_DIVR1_MASK) >>
+		SSCG_PLL_REF_DIVR1_SHIFT;
+	divr2 = (pll_cfg2 & SSCG_PLL_REF_DIVR2_MASK) >>
+		SSCG_PLL_REF_DIVR2_SHIFT;
+	divf1 = (pll_cfg2 & SSCG_PLL_FEEDBACK_DIV_F1_MASK) >>
+		SSCG_PLL_FEEDBACK_DIV_F1_SHIFT;
+	divf2 = (pll_cfg2 & SSCG_PLL_FEEDBACK_DIV_F2_MASK) >>
+		SSCG_PLL_FEEDBACK_DIV_F2_SHIFT;
+	divq = (pll_cfg2 & SSCG_PLL_OUTPUT_DIV_VAL_MASK) >>
+		SSCG_PLL_OUTPUT_DIV_VAL_SHIFT;
+	sse = pll_cfg1 & SSCG_PLL_SSE_MASK;
+
+	if (sse)
+		sse = 8;
+	else
+		sse = 2;
+
+	pllout = pll_refclk / (divr1 + 1) * sse * (divf1 + 1) /
+		(divr2 + 1) * (divf2 + 1) / (divq + 1);
+
+	return pllout / (pllout_div + 1) / div;
+}
+
+static u32 get_root_src_clk(enum clk_root_src root_src)
+{
+	switch (root_src) {
+	case OSC_25M_CLK:
+		return 25000000;
+	case OSC_27M_CLK:
+		return 25000000;
+	case OSC_32K_CLK:
+		return 32000;
+	case ARM_PLL_CLK:
+		return decode_frac_pll(root_src);
+	case SYSTEM_PLL1_800M_CLK:
+	case SYSTEM_PLL1_400M_CLK:
+	case SYSTEM_PLL1_266M_CLK:
+	case SYSTEM_PLL1_200M_CLK:
+	case SYSTEM_PLL1_160M_CLK:
+	case SYSTEM_PLL1_133M_CLK:
+	case SYSTEM_PLL1_100M_CLK:
+	case SYSTEM_PLL1_80M_CLK:
+	case SYSTEM_PLL1_40M_CLK:
+	case SYSTEM_PLL2_1000M_CLK:
+	case SYSTEM_PLL2_500M_CLK:
+	case SYSTEM_PLL2_333M_CLK:
+	case SYSTEM_PLL2_250M_CLK:
+	case SYSTEM_PLL2_200M_CLK:
+	case SYSTEM_PLL2_166M_CLK:
+	case SYSTEM_PLL2_125M_CLK:
+	case SYSTEM_PLL2_100M_CLK:
+	case SYSTEM_PLL2_50M_CLK:
+	case SYSTEM_PLL3_CLK:
+		return decode_sscg_pll(root_src);
+	default:
+		return 0;
+	}
+
+	return 0;
+}
+
+static u32 get_root_clk(enum clk_root_index clock_id)
+{
+	enum clk_root_src root_src;
+	u32 post_podf, pre_podf, root_src_clk;
+
+	if (clock_root_enabled(clock_id) <= 0)
+		return 0;
+
+	if (clock_get_prediv(clock_id, &pre_podf) < 0)
+		return 0;
+
+	if (clock_get_postdiv(clock_id, &post_podf) < 0)
+		return 0;
+
+	if (clock_get_src(clock_id, &root_src) < 0)
+		return 0;
+
+	root_src_clk = get_root_src_clk(root_src);
+
+	return root_src_clk / (post_podf + 1) / (pre_podf + 1);
+}
+
+#ifdef CONFIG_MXC_OCOTP
+void enable_ocotp_clk(unsigned char enable)
+{
+	clock_enable(CCGR_OCOTP, !!enable);
+}
+#endif
+
+int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
+{
+	/* 0 - 3 is valid i2c num */
+	if (i2c_num > 3)
+		return -EINVAL;
+
+	clock_enable(CCGR_I2C1 + i2c_num, !!enable);
+
+	return 0;
+}
+
+unsigned int mxc_get_clock(enum clk_root_index clk)
+{
+	u32 val;
+
+	if (clk >= CLK_ROOT_MAX)
+		return 0;
+
+	if (clk == MXC_ARM_CLK)
+		return get_root_clk(ARM_A53_CLK_ROOT);
+
+	if (clk == MXC_IPG_CLK) {
+		clock_get_target_val(IPG_CLK_ROOT, &val);
+		val = val & 0x3;
+		return get_root_clk(AHB_CLK_ROOT) / (val + 1);
+	}
+
+	return get_root_clk(clk);
+}
+
+u32 imx_get_uartclk(void)
+{
+	return mxc_get_clock(UART1_CLK_ROOT);
+}
+
+void mxs_set_lcdclk(u32 base_addr, u32 freq)
+{
+	/*
+	 * LCDIF_PIXEL_CLK: select 800MHz root clock,
+	 * select pre divider 8, output is 100 MHz
+	 */
+	clock_set_target_val(LCDIF_PIXEL_CLK_ROOT, CLK_ROOT_ON |
+			     CLK_ROOT_SOURCE_SEL(4) |
+			     CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV8));
+}
+
+void init_wdog_clk(void)
+{
+	clock_enable(CCGR_WDOG1, 0);
+	clock_enable(CCGR_WDOG2, 0);
+	clock_enable(CCGR_WDOG3, 0);
+	clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
+			     CLK_ROOT_SOURCE_SEL(0));
+	clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
+			     CLK_ROOT_SOURCE_SEL(0));
+	clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
+			     CLK_ROOT_SOURCE_SEL(0));
+	clock_enable(CCGR_WDOG1, 1);
+	clock_enable(CCGR_WDOG2, 1);
+	clock_enable(CCGR_WDOG3, 1);
+}
+
+void init_usb_clk(void)
+{
+	if (!is_usb_boot()) {
+		clock_enable(CCGR_USB_CTRL1, 0);
+		clock_enable(CCGR_USB_CTRL2, 0);
+		clock_enable(CCGR_USB_PHY1, 0);
+		clock_enable(CCGR_USB_PHY2, 0);
+		/* 500MHz */
+		clock_set_target_val(USB_BUS_CLK_ROOT, CLK_ROOT_ON |
+				     CLK_ROOT_SOURCE_SEL(1));
+		/* 100MHz */
+		clock_set_target_val(USB_CORE_REF_CLK_ROOT, CLK_ROOT_ON |
+				     CLK_ROOT_SOURCE_SEL(1));
+		/* 100MHz */
+		clock_set_target_val(USB_PHY_REF_CLK_ROOT, CLK_ROOT_ON |
+				     CLK_ROOT_SOURCE_SEL(1));
+		clock_enable(CCGR_USB_CTRL1, 1);
+		clock_enable(CCGR_USB_CTRL2, 1);
+		clock_enable(CCGR_USB_PHY1, 1);
+		clock_enable(CCGR_USB_PHY2, 1);
+	}
+}
+
+void init_uart_clk(u32 index)
+{
+	/* Set uart clock root 25M OSC */
+	switch (index) {
+	case 0:
+		clock_enable(CCGR_UART1, 0);
+		clock_set_target_val(UART1_CLK_ROOT, CLK_ROOT_ON |
+				     CLK_ROOT_SOURCE_SEL(0));
+		clock_enable(CCGR_UART1, 1);
+		return;
+	case 1:
+		clock_enable(CCGR_UART2, 0);
+		clock_set_target_val(UART2_CLK_ROOT, CLK_ROOT_ON |
+				     CLK_ROOT_SOURCE_SEL(0));
+		clock_enable(CCGR_UART2, 1);
+		return;
+	case 2:
+		clock_enable(CCGR_UART3, 0);
+		clock_set_target_val(UART3_CLK_ROOT, CLK_ROOT_ON |
+				     CLK_ROOT_SOURCE_SEL(0));
+		clock_enable(CCGR_UART3, 1);
+		return;
+	case 3:
+		clock_enable(CCGR_UART4, 0);
+		clock_set_target_val(UART4_CLK_ROOT, CLK_ROOT_ON |
+				     CLK_ROOT_SOURCE_SEL(0));
+		clock_enable(CCGR_UART4, 1);
+		return;
+	default:
+		printf("Invalid uart index\n");
+		return;
+	}
+}
+
+void init_clk_usdhc(u32 index)
+{
+	/*
+	 * set usdhc clock root
+	 * sys pll1 400M
+	 */
+	switch (index) {
+	case 0:
+		clock_enable(CCGR_USDHC1, 0);
+		clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON |
+				     CLK_ROOT_SOURCE_SEL(1) |
+				     CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
+		clock_enable(CCGR_USDHC1, 1);
+		return;
+	case 1:
+		clock_enable(CCGR_USDHC2, 0);
+		clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON |
+				     CLK_ROOT_SOURCE_SEL(1) |
+				     CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
+		clock_enable(CCGR_USDHC2, 1);
+		return;
+	default:
+		printf("Invalid usdhc index\n");
+		return;
+	}
+}
+
+int set_clk_qspi(void)
+{
+	/*
+	 * set qspi root
+	 * sys pll1 100M
+	 */
+	clock_enable(CCGR_QSPI, 0);
+	clock_set_target_val(QSPI_CLK_ROOT, CLK_ROOT_ON |
+			     CLK_ROOT_SOURCE_SEL(7));
+	clock_enable(CCGR_QSPI, 1);
+
+	return 0;
+}
+
+#ifdef CONFIG_FEC_MXC
+int set_clk_enet(enum enet_freq type)
+{
+	u32 target;
+	u32 enet1_ref;
+
+	switch (type) {
+	case ENET_125MHZ:
+		enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
+		break;
+	case ENET_50MHZ:
+		enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
+		break;
+	case ENET_25MHZ:
+		enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/* disable the clock first */
+	clock_enable(CCGR_ENET1, 0);
+	clock_enable(CCGR_SIM_ENET, 0);
+
+	/* set enet axi clock 266Mhz */
+	target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |
+		 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+		 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+	clock_set_target_val(ENET_AXI_CLK_ROOT, target);
+
+	target = CLK_ROOT_ON | enet1_ref |
+		 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+		 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+	clock_set_target_val(ENET_REF_CLK_ROOT, target);
+
+	target = CLK_ROOT_ON |
+		ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
+		CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+		CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
+	clock_set_target_val(ENET_TIMER_CLK_ROOT, target);
+
+	/* enable clock */
+	clock_enable(CCGR_SIM_ENET, 1);
+	clock_enable(CCGR_ENET1, 1);
+
+	return 0;
+}
+#endif
+
+u32 imx_get_fecclk(void)
+{
+	return get_root_clk(ENET_AXI_CLK_ROOT);
+}
+
+#ifdef CONFIG_SPL_BUILD
+void dram_pll_init(void)
+{
+	struct src *src = (struct src *)SRC_BASE_ADDR;
+	void __iomem *pll_control_reg = &ana_pll->dram_pll_cfg0;
+	u32 pwdn_mask = 0, pll_clke = 0, bypass1 = 0, bypass2 = 0;
+	u32 val;
+	int ret;
+
+	setbits_le32(GPC_BASE_ADDR + 0xEC, BIT(7));
+	setbits_le32(GPC_BASE_ADDR + 0xF8, BIT(5));
+
+	pwdn_mask = SSCG_PLL_PD_MASK;
+	pll_clke = SSCG_PLL_DRAM_PLL_CLKE_MASK;
+	bypass1 = SSCG_PLL_BYPASS1_MASK;
+	bypass2 = SSCG_PLL_BYPASS2_MASK;
+
+	/* Enable DDR1 and DDR2 domain */
+	writel(SRC_DDR1_ENABLE_MASK, &src->ddr1_rcr);
+	writel(SRC_DDR1_ENABLE_MASK, &src->ddr2_rcr);
+
+	/* Clear power down bit */
+	clrbits_le32(pll_control_reg, pwdn_mask);
+	/* Eanble ARM_PLL/SYS_PLL  */
+	setbits_le32(pll_control_reg, pll_clke);
+
+	/* Clear bypass */
+	clrbits_le32(pll_control_reg, bypass1);
+	__udelay(100);
+	clrbits_le32(pll_control_reg, bypass2);
+	/* Wait lock */
+	ret = readl_poll_timeout(pll_control_reg, val,
+				 val & SSCG_PLL_LOCK_MASK, 1);
+	if (ret)
+		printf("%s timeout\n", __func__);
+}
+
+int frac_pll_init(u32 pll, enum frac_pll_out_val val)
+{
+	void __iomem *pll_cfg0, __iomem *pll_cfg1;
+	u32 val_cfg0, val_cfg1;
+	int ret;
+
+	switch (pll) {
+	case ANATOP_ARM_PLL:
+		pll_cfg0 = &ana_pll->arm_pll_cfg0;
+		pll_cfg1 = &ana_pll->arm_pll_cfg1;
+
+		if (val == FRAC_PLL_OUT_1000M)
+			val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(49);
+		else
+			val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(79);
+		val_cfg0 = FRAC_PLL_CLKE_MASK | FRAC_PLL_REFCLK_SEL_OSC_25M |
+			FRAC_PLL_LOCK_SEL_MASK | FRAC_PLL_NEWDIV_VAL_MASK |
+			FRAC_PLL_REFCLK_DIV_VAL(4) |
+			FRAC_PLL_OUTPUT_DIV_VAL(0);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/* bypass the clock */
+	setbits_le32(pll_cfg0, FRAC_PLL_BYPASS_MASK);
+	/* Set the value */
+	writel(val_cfg1, pll_cfg1);
+	writel(val_cfg0 | FRAC_PLL_BYPASS_MASK, pll_cfg0);
+	val_cfg0 = readl(pll_cfg0);
+	/* unbypass the clock */
+	clrbits_le32(pll_cfg0, FRAC_PLL_BYPASS_MASK);
+	ret = readl_poll_timeout(pll_cfg0, val_cfg0,
+				 val_cfg0 & FRAC_PLL_LOCK_MASK, 1);
+	if (ret)
+		printf("%s timeout\n", __func__);
+	clrbits_le32(pll_cfg0, FRAC_PLL_NEWDIV_VAL_MASK);
+
+	return 0;
+}
+
+int sscg_pll_init(u32 pll)
+{
+	void __iomem *pll_cfg0, __iomem *pll_cfg1, __iomem *pll_cfg2;
+	u32 val_cfg0, val_cfg1, val_cfg2, val;
+	u32 bypass1_mask = 0x20, bypass2_mask = 0x10;
+	int ret;
+
+	switch (pll) {
+	case ANATOP_SYSTEM_PLL1:
+		pll_cfg0 = &ana_pll->sys_pll1_cfg0;
+		pll_cfg1 = &ana_pll->sys_pll1_cfg1;
+		pll_cfg2 = &ana_pll->sys_pll1_cfg2;
+		/* 800MHz */
+		val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) |
+			SSCG_PLL_FEEDBACK_DIV_F2_VAL(3);
+		val_cfg1 = 0;
+		val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK |
+			SSCG_PLL_DIV3_CLKE_MASK | SSCG_PLL_DIV4_CLKE_MASK |
+			SSCG_PLL_DIV5_CLKE_MASK | SSCG_PLL_DIV6_CLKE_MASK |
+			SSCG_PLL_DIV8_CLKE_MASK | SSCG_PLL_DIV10_CLKE_MASK |
+			SSCG_PLL_DIV20_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK |
+			SSCG_PLL_REFCLK_SEL_OSC_25M;
+		break;
+	case ANATOP_SYSTEM_PLL2:
+		pll_cfg0 = &ana_pll->sys_pll2_cfg0;
+		pll_cfg1 = &ana_pll->sys_pll2_cfg1;
+		pll_cfg2 = &ana_pll->sys_pll2_cfg2;
+		/* 1000MHz */
+		val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) |
+			SSCG_PLL_FEEDBACK_DIV_F2_VAL(4);
+		val_cfg1 = 0;
+		val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK |
+			SSCG_PLL_DIV3_CLKE_MASK | SSCG_PLL_DIV4_CLKE_MASK |
+			SSCG_PLL_DIV5_CLKE_MASK | SSCG_PLL_DIV6_CLKE_MASK |
+			SSCG_PLL_DIV8_CLKE_MASK | SSCG_PLL_DIV10_CLKE_MASK |
+			SSCG_PLL_DIV20_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK |
+			SSCG_PLL_REFCLK_SEL_OSC_25M;
+		break;
+	case ANATOP_SYSTEM_PLL3:
+		pll_cfg0 = &ana_pll->sys_pll3_cfg0;
+		pll_cfg1 = &ana_pll->sys_pll3_cfg1;
+		pll_cfg2 = &ana_pll->sys_pll3_cfg2;
+		/* 800MHz */
+		val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) |
+			SSCG_PLL_FEEDBACK_DIV_F2_VAL(3);
+		val_cfg1 = 0;
+		val_cfg0 = SSCG_PLL_PLL3_CLKE_MASK |  SSCG_PLL_LOCK_SEL_MASK |
+			SSCG_PLL_REFCLK_SEL_OSC_25M;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/*bypass*/
+	setbits_le32(pll_cfg0, bypass1_mask | bypass2_mask);
+	/* set value */
+	writel(val_cfg2, pll_cfg2);
+	writel(val_cfg1, pll_cfg1);
+	/*unbypass1 and wait 70us */
+	writel(val_cfg0 | bypass2_mask, pll_cfg1);
+
+	__udelay(70);
+
+	/* unbypass2 and wait lock */
+	writel(val_cfg0, pll_cfg1);
+	ret = readl_poll_timeout(pll_cfg0, val, val & SSCG_PLL_LOCK_MASK, 1);
+	if (ret)
+		printf("%s timeout\n", __func__);
+
+	return ret;
+}
+
+int clock_init(void)
+{
+	u32 grade;
+
+	clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
+			     CLK_ROOT_SOURCE_SEL(0));
+
+	/*
+	 * 8MQ only supports two grades: consumer and industrial.
+	 * We set ARM clock to 1Ghz for consumer, 800Mhz for industrial
+	 */
+	grade = get_cpu_temp_grade(NULL, NULL);
+	if (!grade) {
+		frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_1000M);
+		clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
+			     CLK_ROOT_SOURCE_SEL(1) |
+			     CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1));
+	} else {
+		frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_1600M);
+		clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
+			     CLK_ROOT_SOURCE_SEL(1) |
+			     CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
+	}
+	/*
+	 * According to ANAMIX SPEC
+	 * sys pll1 fixed at 800MHz
+	 * sys pll2 fixed at 1GHz
+	 * Here we only enable the outputs.
+	 */
+	setbits_le32(&ana_pll->sys_pll1_cfg0, SSCG_PLL_CLKE_MASK |
+		     SSCG_PLL_DIV2_CLKE_MASK | SSCG_PLL_DIV3_CLKE_MASK |
+		     SSCG_PLL_DIV4_CLKE_MASK | SSCG_PLL_DIV5_CLKE_MASK |
+		     SSCG_PLL_DIV6_CLKE_MASK | SSCG_PLL_DIV8_CLKE_MASK |
+		     SSCG_PLL_DIV10_CLKE_MASK | SSCG_PLL_DIV20_CLKE_MASK);
+
+	setbits_le32(&ana_pll->sys_pll2_cfg0, SSCG_PLL_CLKE_MASK |
+		     SSCG_PLL_DIV2_CLKE_MASK | SSCG_PLL_DIV3_CLKE_MASK |
+		     SSCG_PLL_DIV4_CLKE_MASK | SSCG_PLL_DIV5_CLKE_MASK |
+		     SSCG_PLL_DIV6_CLKE_MASK | SSCG_PLL_DIV8_CLKE_MASK |
+		     SSCG_PLL_DIV10_CLKE_MASK | SSCG_PLL_DIV20_CLKE_MASK);
+
+	clock_set_target_val(NAND_USDHC_BUS_CLK_ROOT, CLK_ROOT_ON |
+			     CLK_ROOT_SOURCE_SEL(1));
+
+	init_wdog_clk();
+	clock_enable(CCGR_TSENSOR, 1);
+
+	return 0;
+}
+#endif
+
+/*
+ * Dump some clockes.
+ */
+#ifndef CONFIG_SPL_BUILD
+int do_mx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
+		       char * const argv[])
+{
+	u32 freq;
+
+	freq = decode_frac_pll(ARM_PLL_CLK);
+	printf("ARM_PLL    %8d MHz\n", freq / 1000000);
+	freq = decode_sscg_pll(SYSTEM_PLL1_800M_CLK);
+	printf("SYS_PLL1_800    %8d MHz\n", freq / 1000000);
+	freq = decode_sscg_pll(SYSTEM_PLL1_400M_CLK);
+	printf("SYS_PLL1_400    %8d MHz\n", freq / 1000000);
+	freq = decode_sscg_pll(SYSTEM_PLL1_266M_CLK);
+	printf("SYS_PLL1_266    %8d MHz\n", freq / 1000000);
+	freq = decode_sscg_pll(SYSTEM_PLL1_200M_CLK);
+	printf("SYS_PLL1_200    %8d MHz\n", freq / 1000000);
+	freq = decode_sscg_pll(SYSTEM_PLL1_160M_CLK);
+	printf("SYS_PLL1_160    %8d MHz\n", freq / 1000000);
+	freq = decode_sscg_pll(SYSTEM_PLL1_133M_CLK);
+	printf("SYS_PLL1_133    %8d MHz\n", freq / 1000000);
+	freq = decode_sscg_pll(SYSTEM_PLL1_100M_CLK);
+	printf("SYS_PLL1_100    %8d MHz\n", freq / 1000000);
+	freq = decode_sscg_pll(SYSTEM_PLL1_80M_CLK);
+	printf("SYS_PLL1_80    %8d MHz\n", freq / 1000000);
+	freq = decode_sscg_pll(SYSTEM_PLL1_40M_CLK);
+	printf("SYS_PLL1_40    %8d MHz\n", freq / 1000000);
+	freq = decode_sscg_pll(SYSTEM_PLL2_1000M_CLK);
+	printf("SYS_PLL2_1000    %8d MHz\n", freq / 1000000);
+	freq = decode_sscg_pll(SYSTEM_PLL2_500M_CLK);
+	printf("SYS_PLL2_500    %8d MHz\n", freq / 1000000);
+	freq = decode_sscg_pll(SYSTEM_PLL2_333M_CLK);
+	printf("SYS_PLL2_333    %8d MHz\n", freq / 1000000);
+	freq = decode_sscg_pll(SYSTEM_PLL2_250M_CLK);
+	printf("SYS_PLL2_250    %8d MHz\n", freq / 1000000);
+	freq = decode_sscg_pll(SYSTEM_PLL2_200M_CLK);
+	printf("SYS_PLL2_200    %8d MHz\n", freq / 1000000);
+	freq = decode_sscg_pll(SYSTEM_PLL2_166M_CLK);
+	printf("SYS_PLL2_166    %8d MHz\n", freq / 1000000);
+	freq = decode_sscg_pll(SYSTEM_PLL2_125M_CLK);
+	printf("SYS_PLL2_125    %8d MHz\n", freq / 1000000);
+	freq = decode_sscg_pll(SYSTEM_PLL2_100M_CLK);
+	printf("SYS_PLL2_100    %8d MHz\n", freq / 1000000);
+	freq = decode_sscg_pll(SYSTEM_PLL2_50M_CLK);
+	printf("SYS_PLL2_50    %8d MHz\n", freq / 1000000);
+	freq = decode_sscg_pll(SYSTEM_PLL3_CLK);
+	printf("SYS_PLL3       %8d MHz\n", freq / 1000000);
+	freq = mxc_get_clock(UART1_CLK_ROOT);
+	printf("UART1          %8d MHz\n", freq / 1000000);
+	freq = mxc_get_clock(USDHC1_CLK_ROOT);
+	printf("USDHC1         %8d MHz\n", freq / 1000000);
+	freq = mxc_get_clock(QSPI_CLK_ROOT);
+	printf("QSPI           %8d MHz\n", freq / 1000000);
+	return 0;
+}
+
+U_BOOT_CMD(
+	clocks,	CONFIG_SYS_MAXARGS, 1, do_mx8m_showclocks,
+	"display clocks",
+	""
+);
+#endif

arch/arm/mach-imx/mx8m/clock_slice.c

@@ -0,0 +1,742 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * Peng Fan <peng.fan@nxp.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/io.h>
+#include <errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct ccm_reg *ccm_reg = (struct ccm_reg *)CCM_BASE_ADDR;
+
+static struct clk_root_map root_array[] = {
+	{ARM_A53_CLK_ROOT, CORE_CLOCK_SLICE, 0,
+	 {OSC_25M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
+	  SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL3_CLK}
+	},
+	{ARM_M4_CLK_ROOT, CORE_CLOCK_SLICE, 1,
+	 {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_250M_CLK,
+	  SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
+	  AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
+	},
+	{VPU_A53_CLK_ROOT, CORE_CLOCK_SLICE, 2,
+	 {OSC_25M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
+	  SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, VPU_PLL_CLK}
+	},
+	{GPU_CORE_CLK_ROOT, CORE_CLOCK_SLICE, 3,
+	 {OSC_25M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
+	  AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
+	},
+	{GPU_SHADER_CLK_ROOT, CORE_CLOCK_SLICE, 4,
+	 {OSC_25M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
+	  AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
+	},
+	{MAIN_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 0,
+	 {OSC_25M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_1000M_CLK,
+	  AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL1_100M_CLK}
+	},
+	{ENET_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 1,
+	 {OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
+	  AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
+	},
+	{NAND_USDHC_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 2,
+	 {OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_133M_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL1_CLK}
+	},
+	{VPU_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 3,
+	 {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, VPU_PLL_CLK,
+	  AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
+	  SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_100M_CLK}
+	},
+	{DISPLAY_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 4,
+	 {OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK,
+	  EXT_CLK_1, EXT_CLK_4}
+	},
+	{DISPLAY_APB_CLK_ROOT, BUS_CLOCK_SLICE, 5,
+	 {OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK,
+	  EXT_CLK_1, EXT_CLK_3}
+	},
+	{DISPLAY_RTRM_CLK_ROOT, BUS_CLOCK_SLICE, 6,
+	 {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_200M_CLK,
+	  SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
+	  EXT_CLK_2, EXT_CLK_3}
+	},
+	{USB_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 7,
+	 {OSC_25M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
+	  EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
+	},
+	{GPU_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 8,
+	 {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
+	  AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
+	},
+	{GPU_AHB_CLK_ROOT, BUS_CLOCK_SLICE, 9,
+	 {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
+	  AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
+	},
+	{NOC_CLK_ROOT, BUS_CLOCK_SLICE, 10,
+	 {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL3_CLK,
+	  SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_500M_CLK,
+	  AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
+	},
+	{NOC_APB_CLK_ROOT, BUS_CLOCK_SLICE, 11,
+	 {OSC_25M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL3_CLK,
+	  SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_200M_CLK,
+	  SYSTEM_PLL1_800M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
+	},
+	{AHB_CLK_ROOT, AHB_CLOCK_SLICE, 0,
+	 {OSC_25M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_125M_CLK,
+	  SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
+	},
+	{IPG_CLK_ROOT, IPG_CLOCK_SLICE, 0,
+	 {}
+	},
+	{AUDIO_AHB_CLK_ROOT, AHB_CLOCK_SLICE, 1,
+	 {OSC_25M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_166M_CLK,
+	  SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
+	},
+	{MIPI_DSI_ESC_RX_CLK_ROOT, AHB_CLOCK_SLICE, 2,
+	 {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_40M_CLK,
+	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+	  SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL1_CLK },
+	},
+	{DRAM_ALT_CLK_ROOT, IP_CLOCK_SLICE, 0,
+	 {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL1_100M_CLK,
+	  SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_250M_CLK,
+	  SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL1_266M_CLK}
+	},
+	{DRAM_APB_CLK_ROOT, IP_CLOCK_SLICE, 1,
+	 {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
+	  SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
+	},
+	{VPU_G1_CLK_ROOT, IP_CLOCK_SLICE, 2,
+	 {OSC_25M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_100M_CLK,
+	  SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK}
+	},
+	{VPU_G2_CLK_ROOT, IP_CLOCK_SLICE, 3,
+	 {OSC_25M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_100M_CLK,
+	  SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK}
+	},
+	{DISPLAY_DTRC_CLK_ROOT, IP_CLOCK_SLICE, 4,
+	 {OSC_25M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_160M_CLK,
+	  SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK}
+	},
+	{DISPLAY_DC8000_CLK_ROOT, IP_CLOCK_SLICE, 5,
+	 {OSC_25M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_160M_CLK,
+	  SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK}
+	},
+	{PCIE1_CTRL_CLK_ROOT, IP_CLOCK_SLICE, 6,
+	 {OSC_25M_CLK, SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
+	  SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL3_CLK}
+	},
+	{PCIE1_PHY_CLK_ROOT, IP_CLOCK_SLICE, 7,
+	 {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_500M_CLK,
+	  EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4,
+	  SYSTEM_PLL1_400M_CLK}
+	},
+	{PCIE1_AUX_CLK_ROOT, IP_CLOCK_SLICE, 8,
+	 {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_50M_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
+	  SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_200M_CLK}
+	},
+	{DC_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 9,
+	 {OSC_25M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
+	  AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
+	},
+	{LCDIF_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 10,
+	 {OSC_25M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
+	  AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
+	},
+	{SAI1_CLK_ROOT, IP_CLOCK_SLICE, 11,
+	 {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+	  VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+	  OSC_27M_CLK, EXT_CLK_1, EXT_CLK_2}
+	},
+	{SAI2_CLK_ROOT, IP_CLOCK_SLICE, 12,
+	 {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+	  VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+	  OSC_27M_CLK, EXT_CLK_2, EXT_CLK_3}
+	},
+	{SAI3_CLK_ROOT, IP_CLOCK_SLICE, 13,
+	 {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+	  VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+	  OSC_27M_CLK, EXT_CLK_3, EXT_CLK_4}
+	},
+	{SAI4_CLK_ROOT, IP_CLOCK_SLICE, 14,
+	 {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+	  VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+	  OSC_27M_CLK, EXT_CLK_1, EXT_CLK_2}
+	},
+	{SAI5_CLK_ROOT, IP_CLOCK_SLICE, 15,
+	 {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+	  VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+	  OSC_27M_CLK, EXT_CLK_2, EXT_CLK_3}
+	},
+	{SAI6_CLK_ROOT, IP_CLOCK_SLICE, 16,
+	 {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+	  VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+	  OSC_27M_CLK, EXT_CLK_3, EXT_CLK_4}
+	},
+	{SPDIF1_CLK_ROOT, IP_CLOCK_SLICE, 17,
+	 {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+	  VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+	  OSC_27M_CLK, EXT_CLK_2, EXT_CLK_3}
+	},
+	{SPDIF2_CLK_ROOT, IP_CLOCK_SLICE, 18,
+	 {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+	  VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+	  OSC_27M_CLK, EXT_CLK_3, EXT_CLK_4}
+	},
+	{ENET_REF_CLK_ROOT, IP_CLOCK_SLICE, 19,
+	 {OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_50M_CLK,
+	  SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
+	  AUDIO_PLL1_CLK, VIDEO_PLL_CLK, EXT_CLK_4}
+	},
+	{ENET_TIMER_CLK_ROOT, IP_CLOCK_SLICE, 20,
+	 {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK,
+	  EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4,
+	  VIDEO_PLL_CLK}
+	},
+	{ENET_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 21,
+	 {OSC_25M_CLK, SYSTEM_PLL2_50M_CLK, SYSTEM_PLL2_125M_CLK,
+	  SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_500M_CLK,
+	  AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
+	},
+	{NAND_CLK_ROOT, IP_CLOCK_SLICE, 22,
+	 {OSC_25M_CLK, SYSTEM_PLL2_500M_CLK, AUDIO_PLL1_CLK,
+	  SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK,
+	  SYSTEM_PLL2_250M_CLK, VIDEO_PLL_CLK}
+	},
+	{QSPI_CLK_ROOT, IP_CLOCK_SLICE, 23,
+	 {OSC_25M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK,
+	  SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_100M_CLK}
+	},
+	{USDHC1_CLK_ROOT, IP_CLOCK_SLICE, 24,
+	 {OSC_25M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK,
+	  SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_100M_CLK}
+	},
+	{USDHC2_CLK_ROOT, IP_CLOCK_SLICE, 25,
+	 {OSC_25M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK,
+	  SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_100M_CLK}
+	},
+	{I2C1_CLK_ROOT, IP_CLOCK_SLICE, 26,
+	 {OSC_25M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
+	  SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
+	  AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
+	},
+	{I2C2_CLK_ROOT, IP_CLOCK_SLICE, 27,
+	 {OSC_25M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
+	  SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
+	  AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
+	},
+	{I2C3_CLK_ROOT, IP_CLOCK_SLICE, 28,
+	 {OSC_25M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
+	  SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
+	  AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
+	},
+	{I2C4_CLK_ROOT, IP_CLOCK_SLICE, 29,
+	 {OSC_25M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
+	  SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
+	  AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
+	},
+	{UART1_CLK_ROOT, IP_CLOCK_SLICE, 30,
+	 {OSC_25M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
+	  SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
+	  EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
+	},
+	{UART2_CLK_ROOT, IP_CLOCK_SLICE, 31,
+	 {OSC_25M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
+	  SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
+	  EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
+	},
+	{UART3_CLK_ROOT, IP_CLOCK_SLICE, 32,
+	 {OSC_25M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
+	  SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
+	  EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
+	},
+	{UART4_CLK_ROOT, IP_CLOCK_SLICE, 33,
+	 {OSC_25M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
+	  SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
+	  EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
+	},
+	{USB_CORE_REF_CLK_ROOT, IP_CLOCK_SLICE, 34,
+	 {OSC_25M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
+	  SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
+	  EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
+	},
+	{USB_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 35,
+	 {OSC_25M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
+	  SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
+	  EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
+	},
+	{GIC_CLK_ROOT, IP_CLOCK_SLICE, 36,
+	 {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
+	  SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_800M_CLK,
+	  EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
+	},
+	{ECSPI1_CLK_ROOT, IP_CLOCK_SLICE, 37,
+	 {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
+	  SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
+	},
+	{ECSPI2_CLK_ROOT, IP_CLOCK_SLICE, 38,
+	 {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
+	  SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
+	},
+	{PWM1_CLK_ROOT, IP_CLOCK_SLICE, 39,
+	 {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
+	  SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
+	  SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
+	},
+	{PWM2_CLK_ROOT, IP_CLOCK_SLICE, 40,
+	 {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
+	  SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
+	  SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
+	},
+	{PWM3_CLK_ROOT, IP_CLOCK_SLICE, 41,
+	 {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
+	  SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
+	  SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
+	},
+	{PWM4_CLK_ROOT, IP_CLOCK_SLICE, 42,
+	 {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
+	  SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
+	  SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
+	},
+	{GPT1_CLK_ROOT, IP_CLOCK_SLICE, 43,
+	 {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
+	  SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
+	  SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
+	},
+	{GPT2_CLK_ROOT, IP_CLOCK_SLICE, 44,
+	 {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
+	  SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
+	  SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
+	},
+	{GPT3_CLK_ROOT, IP_CLOCK_SLICE, 45,
+	 {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
+	  SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
+	  SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
+	},
+	{GPT4_CLK_ROOT, IP_CLOCK_SLICE, 46,
+	 {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
+	  SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
+	  SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
+	},
+	{GPT5_CLK_ROOT, IP_CLOCK_SLICE, 47,
+	 {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
+	  SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
+	  SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
+	},
+	{GPT6_CLK_ROOT, IP_CLOCK_SLICE, 48,
+	 {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
+	  SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
+	  SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
+	},
+	{TRACE_CLK_ROOT, IP_CLOCK_SLICE, 49,
+	 {OSC_25M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
+	  VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
+	  SYSTEM_PLL3_CLK, EXT_CLK_1, EXT_CLK_3}
+	},
+	{WDOG_CLK_ROOT, IP_CLOCK_SLICE, 50,
+	 {OSC_25M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
+	  VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_166M_CLK}
+	},
+	{WRCLK_CLK_ROOT, IP_CLOCK_SLICE, 51,
+	 {OSC_25M_CLK, SYSTEM_PLL1_40M_CLK, VPU_PLL_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL2_200M_CLK,
+	  SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_100M_CLK}
+	},
+	{IPP_DO_CLKO1, IP_CLOCK_SLICE, 52,
+	 {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, OSC_27M_CLK,
+	  SYSTEM_PLL1_200M_CLK, AUDIO_PLL2_CLK,
+	  SYSTEM_PLL2_500M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_80M_CLK}
+	},
+	{IPP_DO_CLKO2, IP_CLOCK_SLICE, 53,
+	 {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_400M_CLK,
+	  SYSTEM_PLL2_166M_CLK, SYSTEM_PLL3_CLK,
+	  AUDIO_PLL1_CLK, VIDEO_PLL_CLK, OSC_32K_CLK}
+	},
+	{MIPI_DSI_CORE_CLK_ROOT, IP_CLOCK_SLICE, 54,
+	 {OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
+	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+	  SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+	},
+	{MIPI_DSI_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 55,
+	 {OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_100M_CLK,
+	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+	  EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+	},
+	{MIPI_DSI_DBI_CLK_ROOT, IP_CLOCK_SLICE, 56,
+	 {OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_100M_CLK,
+	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+	  SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+	},
+	{OLD_MIPI_DSI_ESC_CLK_ROOT, IP_CLOCK_SLICE, 57,
+	 {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
+	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+	  SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
+	},
+	{MIPI_CSI1_CORE_CLK_ROOT, IP_CLOCK_SLICE, 58,
+	 {OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
+	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+	  SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+	},
+	{MIPI_CSI1_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 59,
+	 {OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_100M_CLK,
+	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+	  EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+	},
+	{MIPI_CSI1_ESC_CLK_ROOT, IP_CLOCK_SLICE, 60,
+	 {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
+	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+	  SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
+	},
+	{MIPI_CSI2_CORE_CLK_ROOT, IP_CLOCK_SLICE, 61,
+	 {OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
+	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+	  SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+	},
+	{MIPI_CSI2_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 62,
+	 {OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_100M_CLK,
+	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+	  EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+	},
+	{MIPI_CSI2_ESC_CLK_ROOT, IP_CLOCK_SLICE, 63,
+	 {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
+	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+	  SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
+	},
+	{PCIE2_CTRL_CLK_ROOT, IP_CLOCK_SLICE, 64,
+	 {OSC_25M_CLK, SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
+	  SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL3_CLK}
+	},
+	{PCIE2_PHY_CLK_ROOT, IP_CLOCK_SLICE, 65,
+	 {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_500M_CLK,
+	  EXT_CLK_1, EXT_CLK_2, EXT_CLK_3,
+	  EXT_CLK_4, SYSTEM_PLL1_400M_CLK}
+	},
+	{PCIE2_AUX_CLK_ROOT, IP_CLOCK_SLICE, 66,
+	 {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_50M_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL2_100M_CLK,
+	  SYSTEM_PLL1_80M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_200M_CLK}
+	},
+	{ECSPI3_CLK_ROOT, IP_CLOCK_SLICE, 67,
+	 {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
+	  SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
+	},
+	{OLD_MIPI_DSI_ESC_RX_ROOT, IP_CLOCK_SLICE, 68,
+	 {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
+	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+	  SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK},
+	},
+	{DISPLAY_HDMI_CLK_ROOT, IP_CLOCK_SLICE, 69,
+	 {OSC_25M_CLK, SYSTEM_PLL1_200M_CLK, SYSTEM_PLL2_200M_CLK,
+	  VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
+	},
+	{DRAM_SEL_CFG, DRAM_SEL_CLOCK_SLICE, 0,
+	 {DRAM_PLL1_CLK}
+	},
+	{CORE_SEL_CFG, CORE_SEL_CLOCK_SLICE, 0,
+	 {DRAM_PLL1_CLK}
+	},
+};
+
+static int select(enum clk_root_index clock_id)
+{
+	int i, size;
+	struct clk_root_map *p = root_array;
+
+	size = ARRAY_SIZE(root_array);
+
+	for (i = 0; i < size; i++, p++) {
+		if (clock_id == p->entry)
+			return i;
+	}
+
+	return -EINVAL;
+}
+
+static void __iomem *get_clk_root_target(enum clk_slice_type slice_type,
+					 u32 slice_index)
+{
+	void __iomem *clk_root_target;
+
+	switch (slice_type) {
+	case CORE_CLOCK_SLICE:
+		clk_root_target =
+		(void __iomem *)&ccm_reg->core_root[slice_index];
+		break;
+	case BUS_CLOCK_SLICE:
+		clk_root_target =
+			(void __iomem *)&ccm_reg->bus_root[slice_index];
+		break;
+	case IP_CLOCK_SLICE:
+		clk_root_target =
+			(void __iomem *)&ccm_reg->ip_root[slice_index];
+		break;
+	case AHB_CLOCK_SLICE:
+		clk_root_target =
+			(void __iomem *)&ccm_reg->ahb_ipg_root[slice_index * 2];
+		break;
+	case IPG_CLOCK_SLICE:
+		clk_root_target =
+			(void __iomem *)&ccm_reg->ahb_ipg_root[slice_index * 2 + 1];
+		break;
+	case CORE_SEL_CLOCK_SLICE:
+		clk_root_target = (void __iomem *)&ccm_reg->core_sel;
+		break;
+	case DRAM_SEL_CLOCK_SLICE:
+		clk_root_target = (void __iomem *)&ccm_reg->dram_sel;
+		break;
+	default:
+		return NULL;
+	}
+
+	return clk_root_target;
+}
+
+int clock_get_target_val(enum clk_root_index clock_id, u32 *val)
+{
+	int root_entry;
+	struct clk_root_map *p;
+	void __iomem *clk_root_target;
+
+	if (clock_id >= CLK_ROOT_MAX)
+		return -EINVAL;
+
+	root_entry = select(clock_id);
+	if (root_entry < 0)
+		return -EINVAL;
+
+	p = &root_array[root_entry];
+	clk_root_target = get_clk_root_target(p->slice_type, p->slice_index);
+	if (!clk_root_target)
+		return -EINVAL;
+
+	*val = readl(clk_root_target);
+
+	return 0;
+}
+
+int clock_set_target_val(enum clk_root_index clock_id, u32 val)
+{
+	int root_entry;
+	struct clk_root_map *p;
+	void __iomem *clk_root_target;
+
+	if (clock_id >= CLK_ROOT_MAX)
+		return -EINVAL;
+
+	root_entry = select(clock_id);
+	if (root_entry < 0)
+		return -EINVAL;
+
+	p = &root_array[root_entry];
+	clk_root_target = get_clk_root_target(p->slice_type, p->slice_index);
+	if (!clk_root_target)
+		return -EINVAL;
+
+	writel(val, clk_root_target);
+
+	return 0;
+}
+
+int clock_root_enabled(enum clk_root_index clock_id)
+{
+	void __iomem *clk_root_target;
+	u32 slice_index, slice_type;
+	u32 val;
+	int root_entry;
+
+	if (clock_id >= CLK_ROOT_MAX)
+		return -EINVAL;
+
+	root_entry = select(clock_id);
+	if (root_entry < 0)
+		return -EINVAL;
+
+	slice_type = root_array[root_entry].slice_type;
+	slice_index = root_array[root_entry].slice_index;
+
+	if ((slice_type == IPG_CLOCK_SLICE) ||
+	    (slice_type == DRAM_SEL_CLOCK_SLICE) ||
+	    (slice_type == CORE_SEL_CLOCK_SLICE)) {
+		/*
+		 * Not supported, from CCM doc
+		 * TODO
+		 */
+		return 0;
+	}
+
+	clk_root_target = get_clk_root_target(slice_type, slice_index);
+	if (!clk_root_target)
+		return -EINVAL;
+
+	val = readl(clk_root_target);
+
+	return (val & CLK_ROOT_ON) ? 1 : 0;
+}
+
+/* CCGR CLK gate operation */
+int clock_enable(enum clk_ccgr_index index, bool enable)
+{
+	void __iomem *ccgr;
+
+	if (index >= CCGR_MAX)
+		return -EINVAL;
+
+	if (enable)
+		ccgr = (void __iomem *)&ccm_reg->ccgr_array[index].ccgr_set;
+	else
+		ccgr = (void __iomem *)&ccm_reg->ccgr_array[index].ccgr_clr;
+
+	writel(CCGR_CLK_ON_MASK, ccgr);
+
+	return 0;
+}
+
+int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div)
+{
+	u32 val;
+	int root_entry;
+	struct clk_root_map *p;
+	void __iomem *clk_root_target;
+
+	if (clock_id >= CLK_ROOT_MAX)
+		return -EINVAL;
+
+	root_entry = select(clock_id);
+	if (root_entry < 0)
+		return -EINVAL;
+
+	p = &root_array[root_entry];
+
+	if ((p->slice_type == CORE_CLOCK_SLICE) ||
+	    (p->slice_type == IPG_CLOCK_SLICE) ||
+	    (p->slice_type == CORE_SEL_CLOCK_SLICE) ||
+	    (p->slice_type == DRAM_SEL_CLOCK_SLICE)) {
+		*pre_div = 0;
+		return 0;
+	}
+
+	clk_root_target = get_clk_root_target(p->slice_type, p->slice_index);
+	if (!clk_root_target)
+		return -EINVAL;
+
+	val = readl(clk_root_target);
+	val &= CLK_ROOT_PRE_DIV_MASK;
+	val >>= CLK_ROOT_PRE_DIV_SHIFT;
+
+	*pre_div = val;
+
+	return 0;
+}
+
+int clock_get_postdiv(enum clk_root_index clock_id,
+		      enum root_post_div *post_div)
+{
+	u32 val, mask;
+	int root_entry;
+	struct clk_root_map *p;
+	void __iomem *clk_root_target;
+
+	if (clock_id >= CLK_ROOT_MAX)
+		return -EINVAL;
+
+	root_entry = select(clock_id);
+	if (root_entry < 0)
+		return -EINVAL;
+
+	p = &root_array[root_entry];
+
+	if ((p->slice_type == CORE_SEL_CLOCK_SLICE) ||
+	    (p->slice_type == DRAM_SEL_CLOCK_SLICE)) {
+		*post_div = 0;
+		return 0;
+	}
+
+	clk_root_target = get_clk_root_target(p->slice_type, p->slice_index);
+	if (!clk_root_target)
+		return -EINVAL;
+
+	if (p->slice_type == IPG_CLOCK_SLICE)
+		mask = CLK_ROOT_IPG_POST_DIV_MASK;
+	else if (p->slice_type == CORE_CLOCK_SLICE)
+		mask = CLK_ROOT_CORE_POST_DIV_MASK;
+	else
+		mask = CLK_ROOT_POST_DIV_MASK;
+
+	val = readl(clk_root_target);
+	val &= mask;
+	val >>= CLK_ROOT_POST_DIV_SHIFT;
+
+	*post_div = val;
+
+	return 0;
+}
+
+int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src)
+{
+	u32 val;
+	int root_entry;
+	struct clk_root_map *p;
+	void __iomem *clk_root_target;
+
+	if (clock_id >= CLK_ROOT_MAX)
+		return -EINVAL;
+
+	root_entry = select(clock_id);
+	if (root_entry < 0)
+		return -EINVAL;
+
+	p = &root_array[root_entry];
+
+	clk_root_target = get_clk_root_target(p->slice_type, p->slice_index);
+	if (!clk_root_target)
+		return -EINVAL;
+
+	val = readl(clk_root_target);
+	val &= CLK_ROOT_SRC_MUX_MASK;
+	val >>= CLK_ROOT_SRC_MUX_SHIFT;
+
+	*p_clock_src = p->src_mux[val];
+
+	return 0;
+}

arch/arm/mach-imx/mx8m/lowlevel_init.S

@@ -0,0 +1,63 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+
+.align 8
+.global rom_pointer
+rom_pointer:
+	.space 256
+
+/*
+ * Routine: save_boot_params (called after reset from start.S)
+ */
+
+.global save_boot_params
+save_boot_params:
+	/* The firmware provided ATAG/FDT address can be found in r2/x0 */
+	adr	x0, rom_pointer
+	stp	x1, x2, [x0], #16
+	stp	x3, x4, [x0], #16
+	stp	x5, x6, [x0], #16
+	stp	x7, x8, [x0], #16
+	stp	x9, x10, [x0], #16
+	stp	x11, x12, [x0], #16
+	stp	x13, x14, [x0], #16
+	stp	x15, x16, [x0], #16
+	stp	x17, x18, [x0], #16
+	stp	x19, x20, [x0], #16
+	stp	x21, x22, [x0], #16
+	stp	x23, x24, [x0], #16
+	stp	x25, x26, [x0], #16
+	stp	x27, x28, [x0], #16
+	stp	x29, x30, [x0], #16
+	mov	x30, sp
+	str	x30, [x0], #8
+
+	/* Returns */
+	b	save_boot_params_ret
+
+.global restore_boot_params
+restore_boot_params:
+	adr	x0, rom_pointer
+	ldp	x1, x2, [x0], #16
+	ldp	x3, x4, [x0], #16
+	ldp	x5, x6, [x0], #16
+	ldp	x7, x8, [x0], #16
+	ldp	x9, x10, [x0], #16
+	ldp	x11, x12, [x0], #16
+	ldp	x13, x14, [x0], #16
+	ldp	x15, x16, [x0], #16
+	ldp	x17, x18, [x0], #16
+	ldp	x19, x20, [x0], #16
+	ldp	x21, x22, [x0], #16
+	ldp	x23, x24, [x0], #16
+	ldp	x25, x26, [x0], #16
+	ldp	x27, x28, [x0], #16
+	ldp	x29, x30, [x0], #16
+	ldr	x0, [x0]
+	mov	sp, x0
+	ret

arch/arm/mach-imx/mx8m/soc.c

@@ -0,0 +1,227 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * Peng Fan <peng.fan@nxp.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/hab.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/syscounter.h>
+#include <asm/armv8/mmu.h>
+#include <errno.h>
+#include <fdt_support.h>
+#include <fsl_wdog.h>
+#include <imx_sip.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_SECURE_BOOT)
+struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
+	.bank = 1,
+	.word = 3,
+};
+#endif
+
+int timer_init(void)
+{
+#ifdef CONFIG_SPL_BUILD
+	struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
+	unsigned long freq = readl(&sctr->cntfid0);
+
+	/* Update with accurate clock frequency */
+	asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory");
+
+	clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
+			SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
+#endif
+
+	gd->arch.tbl = 0;
+	gd->arch.tbu = 0;
+
+	return 0;
+}
+
+void enable_tzc380(void)
+{
+	struct iomuxc_gpr_base_regs *gpr =
+		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+	/* Enable TZASC and lock setting */
+	setbits_le32(&gpr->gpr[10], GPR_TZASC_EN);
+	setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK);
+}
+
+void set_wdog_reset(struct wdog_regs *wdog)
+{
+	/*
+	 * Output WDOG_B signal to reset external pmic or POR_B decided by
+	 * the board design. Without external reset, the peripherals/DDR/
+	 * PMIC are not reset, that may cause system working abnormal.
+	 * WDZST bit is write-once only bit. Align this bit in kernel,
+	 * otherwise kernel code will have no chance to set this bit.
+	 */
+	setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK);
+}
+
+static struct mm_region imx8m_mem_map[] = {
+	{
+		/* ROM */
+		.virt = 0x0UL,
+		.phys = 0x0UL,
+		.size = 0x100000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_OUTER_SHARE
+	}, {
+		/* OCRAM */
+		.virt = 0x900000UL,
+		.phys = 0x900000UL,
+		.size = 0x200000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_OUTER_SHARE
+	}, {
+		/* AIPS */
+		.virt = 0xB00000UL,
+		.phys = 0xB00000UL,
+		.size = 0x3f500000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* DRAM1 */
+		.virt = 0x40000000UL,
+		.phys = 0x40000000UL,
+		.size = 0xC0000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_OUTER_SHARE
+	}, {
+		/* DRAM2 */
+		.virt = 0x100000000UL,
+		.phys = 0x100000000UL,
+		.size = 0x040000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_OUTER_SHARE
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = imx8m_mem_map;
+
+u32 get_cpu_rev(void)
+{
+	struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
+	u32 reg = readl(&ana_pll->digprog);
+	u32 type = (reg >> 16) & 0xff;
+	u32 rom_version;
+
+	reg &= 0xff;
+
+	if (reg == CHIP_REV_1_0) {
+		/*
+		 * For B0 chip, the DIGPROG is not updated, still TO1.0.
+		 * we have to check ROM version further
+		 */
+		rom_version = readl((void __iomem *)ROM_VERSION_A0);
+		if (rom_version != CHIP_REV_1_0) {
+			rom_version = readl((void __iomem *)ROM_VERSION_B0);
+			if (rom_version >= CHIP_REV_2_0)
+				reg = CHIP_REV_2_0;
+		}
+	}
+
+	return (type << 12) | reg;
+}
+
+static void imx_set_wdog_powerdown(bool enable)
+{
+	struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
+	struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
+	struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
+
+	/* Write to the PDE (Power Down Enable) bit */
+	writew(enable, &wdog1->wmcr);
+	writew(enable, &wdog2->wmcr);
+	writew(enable, &wdog3->wmcr);
+}
+
+int arch_cpu_init(void)
+{
+	/*
+	 * Init timer at very early state, because sscg pll setting
+	 * will use it
+	 */
+	timer_init();
+
+	if (IS_ENABLED(CONFIG_SPL_BUILD)) {
+		clock_init();
+		imx_set_wdog_powerdown(false);
+	}
+
+	return 0;
+}
+
+bool is_usb_boot(void)
+{
+	return get_boot_device() == USB_BOOT;
+}
+
+#ifdef CONFIG_OF_SYSTEM_SETUP
+int ft_system_setup(void *blob, bd_t *bd)
+{
+	int i = 0;
+	int rc;
+	int nodeoff;
+
+	/* Disable the CPU idle for A0 chip since the HW does not support it */
+	if (is_soc_rev(CHIP_REV_1_0)) {
+		static const char * const nodes_path[] = {
+			"/cpus/cpu@0",
+			"/cpus/cpu@1",
+			"/cpus/cpu@2",
+			"/cpus/cpu@3",
+		};
+
+		for (i = 0; i < ARRAY_SIZE(nodes_path); i++) {
+			nodeoff = fdt_path_offset(blob, nodes_path[i]);
+			if (nodeoff < 0)
+				continue; /* Not found, skip it */
+
+			printf("Found %s node\n", nodes_path[i]);
+
+			rc = fdt_delprop(blob, nodeoff, "cpu-idle-states");
+			if (rc) {
+				printf("Unable to update property %s:%s, err=%s\n",
+				       nodes_path[i], "status", fdt_strerror(rc));
+				return rc;
+			}
+
+			printf("Remove %s:%s\n", nodes_path[i],
+			       "cpu-idle-states");
+		}
+	}
+
+	return 0;
+}
+#endif
+
+void reset_cpu(ulong addr)
+{
+	struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
+
+	/* Clear WDA to trigger WDOG_B immediately */
+	writew((WCR_WDE | WCR_SRS), &wdog->wcr);
+
+	while (1) {
+		/*
+		 * spin for .5 seconds before reset
+		 */
+	}
+}

arch/arm/mach-imx/mxs/Kconfig

@@ -0,0 +1,78 @@
+if ARCH_MX23
+
+config MX23
+	bool
+	default y
+
+choice
+	prompt "MX23 board select"
+	optional
+
+config TARGET_MX23_OLINUXINO
+	bool "Support mx23_olinuxino"
+	select BOARD_EARLY_INIT_F
+
+config TARGET_MX23EVK
+	bool "Support mx23evk"
+	select BOARD_EARLY_INIT_F
+
+config TARGET_SANSA_FUZE_PLUS
+	bool "Support sansa_fuze_plus"
+
+config TARGET_XFI3
+	bool "Support xfi3"
+
+endchoice
+
+config SYS_SOC
+	default "mxs"
+
+source "board/olimex/mx23_olinuxino/Kconfig"
+source "board/freescale/mx23evk/Kconfig"
+source "board/sandisk/sansa_fuze_plus/Kconfig"
+source "board/creative/xfi3/Kconfig"
+
+endif
+
+if ARCH_MX28
+
+config MX28
+	bool
+	default y
+
+choice
+	prompt "MX28 board select"
+	optional
+
+config TARGET_APX4DEVKIT
+	bool "Support apx4devkit"
+
+config TARGET_BG0900
+	bool "Support bg0900"
+
+config TARGET_M28EVK
+	bool "Support m28evk"
+
+config TARGET_MX28EVK
+	bool "Support mx28evk"
+	select BOARD_EARLY_INIT_F
+
+config TARGET_SC_SPS_1
+	bool "Support sc_sps_1"
+
+config TARGET_TS4600
+	bool "Support TS4600"
+
+endchoice
+
+config SYS_SOC
+	default "mxs"
+
+source "board/aries/m28evk/Kconfig"
+source "board/bluegiga/apx4devkit/Kconfig"
+source "board/freescale/mx28evk/Kconfig"
+source "board/ppcag/bg0900/Kconfig"
+source "board/schulercontrol/sc_sps_1/Kconfig"
+source "board/technologic/ts4600/Kconfig"
+
+endif

arch/arm/mach-imx/sip.c

@@ -0,0 +1,23 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+
+unsigned long call_imx_sip(unsigned long id, unsigned long reg0,
+			   unsigned long reg1, unsigned long reg2)
+{
+	struct pt_regs regs;
+
+	regs.regs[0] = id;
+	regs.regs[1] = reg0;
+	regs.regs[2] = reg1;
+	regs.regs[3] = reg2;
+
+	smc_call(&regs);
+
+	return regs.regs[0];
+}

arch/arm/mach-imx/spl.c

@@ -97,8 +97,8 @@ u32 spl_boot_device(void)
 	return BOOT_DEVICE_NONE;
 }
 
-#elif defined(CONFIG_MX7)
-/* Translate iMX7 boot device to the SPL boot device enumeration */
+#elif defined(CONFIG_MX7) || defined(CONFIG_MX8M)
+/* Translate iMX7/MX8M boot device to the SPL boot device enumeration */
 u32 spl_boot_device(void)
 {
 	enum boot_device boot_device_spl = get_boot_device();
@@ -115,11 +115,13 @@ u32 spl_boot_device(void)
 		return BOOT_DEVICE_NAND;
 	case SPI_NOR_BOOT:
 		return BOOT_DEVICE_SPI;
+	case USB_BOOT:
+		return BOOT_DEVICE_USB;
 	default:
 		return BOOT_DEVICE_NONE;
 	}
 }
-#endif /* CONFIG_MX6 || CONFIG_MX7 */
+#endif /* CONFIG_MX6 || CONFIG_MX7 || CONFIG_MX8M */
 
 #ifdef CONFIG_SPL_USB_GADGET_SUPPORT
 int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
@@ -130,29 +132,6 @@ int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
 }
 #endif
 
-#if defined(CONFIG_SPL_MMC_SUPPORT)
-/* called from spl_mmc to see type of boot mode for storage (RAW or FAT) */
-u32 spl_boot_mode(const u32 boot_device)
-{
-	switch (spl_boot_device()) {
-	/* for MMC return either RAW or FAT mode */
-	case BOOT_DEVICE_MMC1:
-	case BOOT_DEVICE_MMC2:
-#if defined(CONFIG_SPL_FAT_SUPPORT)
-		return MMCSD_MODE_FS;
-#elif defined(CONFIG_SUPPORT_EMMC_BOOT)
-		return MMCSD_MODE_EMMCBOOT;
-#else
-		return MMCSD_MODE_RAW;
-#endif
-		break;
-	default:
-		puts("spl: ERROR:  unsupported device\n");
-		hang();
-	}
-}
-#endif
-
 #if defined(CONFIG_SECURE_BOOT)
 
 /*

arch/arm/mach-mvebu/spl.c

@@ -70,13 +70,6 @@ u32 spl_boot_device(void)
 	return get_boot_device();
 }
 
-#ifdef CONFIG_SPL_MMC_SUPPORT
-u32 spl_boot_mode(const u32 boot_device)
-{
-	return MMCSD_MODE_RAW;
-}
-#endif
-
 void board_init_f(ulong dummy)
 {
 	int ret;

arch/arm/mach-rockchip/rk3188-board-spl.c

@@ -72,11 +72,6 @@ fallback:
 	return BOOT_DEVICE_MMC1;
 }
 
-u32 spl_boot_mode(const u32 boot_device)
-{
-	return MMCSD_MODE_RAW;
-}
-
 static int setup_arm_clock(void)
 {
 	struct udevice *dev;

arch/arm/mach-rockchip/rk3288-board-spl.c

@@ -78,11 +78,6 @@ fallback:
 	return BOOT_DEVICE_MMC1;
 }
 
-u32 spl_boot_mode(const u32 boot_device)
-{
-	return MMCSD_MODE_RAW;
-}
-
 #ifdef CONFIG_SPL_MMC_SUPPORT
 static int configure_emmc(struct udevice *pinctrl)
 {

arch/arm/mach-rockchip/rk3368-board-spl.c

@@ -57,11 +57,6 @@ void board_init_f(ulong dummy)
 	}
 }
 
-u32 spl_boot_mode(const u32 boot_device)
-{
-	return MMCSD_MODE_RAW;
-}
-
 u32 spl_boot_device(void)
 {
 	return BOOT_DEVICE_MMC1;

arch/arm/mach-rockchip/rk3399-board-spl.c

@@ -60,11 +60,6 @@ u32 spl_boot_device(void)
 	return boot_device;
 }
 
-u32 spl_boot_mode(const u32 boot_device)
-{
-	return MMCSD_MODE_RAW;
-}
-
 #define TIMER_CHN10_BASE	0xff8680a0
 #define TIMER_END_COUNT_L	0x00
 #define TIMER_END_COUNT_H	0x04

arch/arm/mach-socfpga/spl.c

@@ -66,17 +66,6 @@ u32 spl_boot_device(void)
 	}
 }
 
-#ifdef CONFIG_SPL_MMC_SUPPORT
-u32 spl_boot_mode(const u32 boot_device)
-{
-#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
-	return MMCSD_MODE_FS;
-#else
-	return MMCSD_MODE_RAW;
-#endif
-}
-#endif
-
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static void socfpga_nic301_slave_ns(void)
 {

arch/arm/mach-sunxi/board.c

@@ -260,12 +260,6 @@ u32 spl_boot_device(void)
 	return sunxi_get_boot_device();
 }
 
-/* No confirmation data available in SPL yet. Hardcode bootmode */
-u32 spl_boot_mode(const u32 boot_device)
-{
-	return MMCSD_MODE_RAW;
-}
-
 void board_init_f(ulong dummy)
 {
 	spl_init();

arch/arm/mach-zynq/ddrc.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (C) 2012 - 2013 Michal Simek <monstr@monstr.eu>
- * Copyright (C) 2012 - 2013 Xilinx, Inc. All rights reserved.
+ * Copyright (C) 2012 - 2017 Xilinx, Inc. All rights reserved.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

arch/arm/mach-zynq/lowlevel_init.S

@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2013 Xilinx, Inc. All rights reserved.
+ * Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

arch/arm/mach-zynq/ps7_spl_init.c

@@ -58,7 +58,7 @@ static void perf_start_clock(void)
 }
 
 /* Compute mask for given delay in miliseconds*/
-static int get_number_of_cycles_for_delay(unsigned int delay)
+static unsigned long get_number_of_cycles_for_delay(unsigned long delay)
 {
 	return (APU_FREQ / (2 * 1000)) * delay;
 }
@@ -92,7 +92,7 @@ int __weak ps7_config(unsigned long *ps7_config_init)
 	unsigned long mask;
 	unsigned int numargs;
 	int i;
-	int delay;
+	unsigned long delay;
 
 	for (;;) {
 		opcode = ptr[0];

arch/arm/mach-zynq/slcr.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013 Xilinx Inc.
+ * Copyright (c) 2013 - 2017 Xilinx Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

arch/arm/mach-zynq/spl.c

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2014 Xilinx, Inc. Michal Simek
+ * (C) Copyright 2014 - 2017 Xilinx, Inc. Michal Simek
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -69,13 +69,6 @@ u32 spl_boot_device(void)
 	return mode;
 }
 
-#ifdef CONFIG_SPL_MMC_SUPPORT
-u32 spl_boot_mode(const u32 boot_device)
-{
-	return MMCSD_MODE_FS;
-}
-#endif
-
 #ifdef CONFIG_SPL_OS_BOOT
 int spl_start_uboot(void)
 {

arch/arm/mach-zynq/timer.c

@@ -3,7 +3,7 @@
  * Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
  *
  * Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
- * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved.
+ * Copyright (C) 2011-2017 Xilinx, Inc. All rights reserved.
  *
  * (C) Copyright 2008
  * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>

arch/m68k/include/asm/config.h

@@ -11,7 +11,5 @@
 
 #define CONFIG_LMB
 #define CONFIG_SYS_BOOT_RAMDISK_HIGH
-#define CONFIG_SYS_BOOT_GET_CMDLINE
-#define CONFIG_SYS_BOOT_GET_KBD
 
 #endif

arch/powerpc/include/asm/config.h

@@ -31,8 +31,6 @@
 
 #define CONFIG_LMB
 #define CONFIG_SYS_BOOT_RAMDISK_HIGH
-#define CONFIG_SYS_BOOT_GET_CMDLINE
-#define CONFIG_SYS_BOOT_GET_KBD
 
 #ifndef CONFIG_MAX_MEM_MAPPED
 #if	defined(CONFIG_E500)		|| \
@@ -72,11 +70,9 @@
 #endif
 
 /* The TSEC driver uses the PHYLIB infrastructure */
-#ifndef CONFIG_PHYLIB
-#if defined(CONFIG_TSEC_ENET)
+#if defined(CONFIG_TSEC_ENET) && defined(CONFIG_PHYLIB)
 #include <config_phylib_all_drivers.h>
 #endif /* TSEC_ENET */
-#endif /* !CONFIG_PHYLIB */
 
 /* The FMAN driver uses the PHYLIB infrastructure */
 

arch/x86/cpu/quark/smc.c

@@ -17,15 +17,6 @@
 #include "hte.h"
 #include "smc.h"
 
-/* t_rfc values (in picoseconds) per density */
-static const uint32_t t_rfc[5] = {
-	90000,	/* 512Mb */
-	110000,	/* 1Gb */
-	160000,	/* 2Gb */
-	300000,	/* 4Gb */
-	350000,	/* 8Gb */
-};
-
 /* t_ck clock period in picoseconds per speed index 800, 1066, 1333 */
 static const uint32_t t_ck[3] = {
 	2500,
@@ -35,8 +26,12 @@ static const uint32_t t_ck[3] = {
 
 /* Global variables */
 static const uint16_t ddr_wclk[] = {193, 158};
+#ifdef BACKUP_WCTL
 static const uint16_t ddr_wctl[] = {1, 217};
+#endif
+#ifdef BACKUP_WCMD
 static const uint16_t ddr_wcmd[] = {1, 220};
+#endif
 
 #ifdef BACKUP_RCVN
 static const uint16_t ddr_rcvn[] = {129, 498};

arch/x86/include/asm/acpi_table.h

@@ -329,6 +329,15 @@ void acpi_create_gnvs(struct acpi_global_nvs *gnvs);
 void enter_acpi_mode(int pm1_cnt);
 ulong write_acpi_tables(ulong start);
 
+/**
+ * acpi_get_rsdp_addr() - get ACPI RSDP table address
+ *
+ * This routine returns the ACPI RSDP table address in the system memory.
+ *
+ * @return:	ACPI RSDP table address
+ */
+ulong acpi_get_rsdp_addr(void);
+
 /**
  * acpi_find_fadt() - find ACPI FADT table in the sytem memory
  *

arch/x86/include/asm/arch-tangier/acpi/southcluster.asl

@@ -284,7 +284,7 @@ Device (PCI0)
                 Return (STA_VISIBLE)
             }
 
-            Method (_CRS, 0, NotSerialized)
+            Method (_CRS, 0, Serialized)
             {
                 Name (RBUF, ResourceTemplate ()
                 {

arch/x86/include/asm/bootparam.h

@@ -66,6 +66,7 @@ struct setup_header {
 	__u64	pref_address;
 	__u32	init_size;
 	__u32	handover_offset;
+	__u64   acpi_rsdp_addr;
 } __attribute__((packed));
 
 struct sys_desc_table {

arch/x86/lib/acpi_table.c

@@ -27,6 +27,9 @@
  */
 extern const unsigned char AmlCode[];
 
+/* ACPI RSDP address to be used in boot parameters */
+static ulong acpi_rsdp_addr;
+
 static void acpi_write_rsdp(struct acpi_rsdp *rsdp, struct acpi_rsdt *rsdt,
 			    struct acpi_xsdt *xsdt)
 {
@@ -357,8 +360,7 @@ void enter_acpi_mode(int pm1_cnt)
 }
 
 /*
- * QEMU's version of write_acpi_tables is defined in
- * arch/x86/cpu/qemu/acpi_table.c
+ * QEMU's version of write_acpi_tables is defined in drivers/misc/qfw.c
  */
 ulong write_acpi_tables(ulong start)
 {
@@ -461,6 +463,7 @@ ulong write_acpi_tables(ulong start)
 
 	debug("current = %x\n", current);
 
+	acpi_rsdp_addr = (unsigned long)rsdp;
 	debug("ACPI: done\n");
 
 	/* Don't touch ACPI hardware on HW reduced platforms */
@@ -476,6 +479,11 @@ ulong write_acpi_tables(ulong start)
 	return current;
 }
 
+ulong acpi_get_rsdp_addr(void)
+{
+	return acpi_rsdp_addr;
+}
+
 static struct acpi_rsdp *acpi_valid_rsdp(struct acpi_rsdp *rsdp)
 {
 	if (strncmp((char *)rsdp, RSDP_SIG, sizeof(RSDP_SIG) - 1) != 0)

arch/x86/lib/zimage.c

@@ -14,6 +14,7 @@
  */
 
 #include <common.h>
+#include <asm/acpi_table.h>
 #include <asm/io.h>
 #include <asm/ptrace.h>
 #include <asm/zimage.h>
@@ -246,14 +247,20 @@ int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot,
 			hdr->setup_move_size = 0x9100;
 		}
 
-#if defined(CONFIG_INTEL_MID)
-		hdr->hardware_subarch = X86_SUBARCH_INTEL_MID;
-#endif
-
 		/* build command line at COMMAND_LINE_OFFSET */
 		build_command_line(cmd_line, auto_boot);
 	}
 
+#ifdef CONFIG_INTEL_MID
+	if (bootproto >= 0x0207)
+		hdr->hardware_subarch = X86_SUBARCH_INTEL_MID;
+#endif
+
+#ifdef CONFIG_GENERATE_ACPI_TABLE
+	if (bootproto >= 0x020e)
+		hdr->acpi_rsdp_addr = acpi_get_rsdp_addr();
+#endif
+
 	setup_video(&setup_base->screen_info);
 
 	return 0;