This header needs to know 'fdt_region' is a struct for the
fit_region_make_list() prototype.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Commit 286ede6 ("drivers: core: Add translation in live tree case") made
dev_get_addr always use proper bus translations for addresses read from
the device tree. But this leads to problems with certain busses, e.g.
I2C busses, which run into an error during translation, and hence stop
working.
It turns out that of_translate_address() and fdt_translate_address()
stop the address translation with an error when they're asked to
translate addresses for busses where #size-cells == 0 (comment from
drivers/core/of_addr.c):
* Note: We consider that crossing any level with #size-cells == 0 to mean
* that translation is impossible (that is we are not dealing with a value
* that can be mapped to a cpu physical address). This is not really specified
* that way, but this is traditionally the way IBM at least do things
To fix this case, we check in both the live-tree and non-live tree-case,
whether the bus of the device whose address is about to be translated
has size-cell size zero. If this is the case, we just read the address
as a plain integer and return it, and only apply bus translations if the
size-cell size if greater than zero.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Signed-off-by: Martin Fuzzey <mfuzzey@parkeon.com>
Reported-by: Martin Fuzzey <mfuzzey@parkeon.com>
Fixes: 286ede6 ("drivers: core: Add translation in live tree case")
Reviewed-by: Simon Glass <sjg@chromium.org>
dm_scan_fdt_node can't work when live dt is active,
we should use dm_scan_fdt_live instead.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The cast breaks the pointer on 64bit archs, so lets get rid of it.
Signed-off-by: Andre Heider <a.heider@gmail.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
Since the new pinctrl/gpio driver is used, so this patch removes
the old board specific pin control settings.
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
The commit "arm64: mvebu: Add pinctrl nodes for Armada 3700" has
added new pinctrl nodes.
This reverts commit f7cab0f95b.
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch corrects below mpp definitions for armada 3720 DB board
and ESPRESSOBin board:
- "smi" pins group is added and "smi" function is set for eth0;
- Now pcie pins are used as gpio to implement PCIe function in
hardware, so "pcie" group function is changed to "gpio".
Reviewed-on: http://vgitil04.il.marvell.com:8080/43287
Reviewed-by: Hua Jing <jinghua@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch corrects below mpp definitions:
- The sdio_sb group is composed of 6 pins and not 5;
- The rgmii group contains pins mpp2[17:6] and not mpp2[19:6];
- Pin of group "pmic0" is mpp1[6] but not mpp1[16];
- Pin of group "pmic1" is mpp1[7] but not mpp1[17];
- A new group "smi" is added in A0 with 2 pins - mpp2[19:18], its
bitmask is bit4;
- Group "pcie1" has 3 pins in A0 - mpp2[5:3], its bit mask is
bit5 | bit9 | bit10 but not bit4;
- Group "ptp" has 3 pins in A0 as Z1, but its bitmask is changed to
bit11 | bit12 | bit13.
Reviewed-on: http://vgitil04.il.marvell.com:8080/43288
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Hua Jing <jinghua@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
For armada_37xx_update_reg(), the parameter offset should be pointer so
that it can be updated, otherwise offset will keep old value, and then
when offset is larger than or equal to 32 the mask calculated by
"BIT(offset)" will be 0 in gpio chip hook functions, it's an error,
this patch set offset parameter of armada_37xx_update_reg() as pointer.
Reviewed-on: http://vgitil04.il.marvell.com:8080/43287
Reviewed-by: Hua Jing <jinghua@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Pin 23 on South bridge does not belong to the rgmii group. It belongs to
a separate group which can have 3 functions.
Due to this the fix also have to update the way the functions are
managed. Until now each groups used NB_FUNCS(which was 2) functions. For
the mpp23, 3 functions are available but it is the only group which needs
it, so on the loop involving NB_FUNCS an extra test was added to handle
only the functions added.
The bug was visible when the gpio regulator used the gpio 23, the whole
rgmii group was setup to gpio which broke the Ethernet support on the
Armada 3720 DB board. Thanks to this patch, the UHS SD cards (which need
the vqmmc) _and_ the Ethernet work again.
Reviewed-on: http://vgitil04.il.marvell.com:8080/43284
Reviewed-by: Hua Jing <jinghua@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
The various load address values are taken from the a37xx configuration
and match the dowstream 'u-boot-2017.03-armada-17.10' release where
appropriate.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Signed-off-by: Stefan Roese <sr@denx.de>
The kwbimage format is reading beyond its header structure if it
misdetects a Xilinx Zynq image and tries to read it. Fix it by
sanity checking that the header we want to read fits inside our
file size.
Signed-off-by: Alexander Graf <agraf@suse.de>
Tested-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
This makes the network devices usable when booting a blank board over
UART, with no pre-configured MAC address stored in the environment area.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Currently, ATU (address translation unit) implementation doesn't
support translate addresses > 32 bits.
This patch allows to configure ATU correctly for different
memory accesses (memory, configuration and IO).
The same approach is used in Linux Kernel.
Signed-off-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
On x86 platforms, U-Boot does not pass Device Tree data to the kernel.
This prevents the kernel from using FDT loaded by U-Boot.
Read the working FDT address from the "fdtaddr" environment variable
and add a copy of the FDT data to the kernel setup_data list.
Signed-off-by: Ivan Gorinov <ivan.gorinov@intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: add #include <linux/libfdt.h> to zimage.c to fix build error]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
PCI enumeration may happen very early on an x86 board. The board
information pointer should have been checked in decode_regions()
as its space may not be allocated yet.
With this commit, Intel Galileo board boots again.
Fixes: 664758c ("pci: Fix decode regions for memory banks")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The get_codeseg32() wants to know if a passed in descriptor has
flag GDT_NOTSYS set (desc & GDT_NOTSYS), not whether desc and
GDT_NOTSYS are not != 0 (desk && GDT_NOTSYS).
This is an obvious typo. Fix it up.
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Enable CONFIG_OF_BOAD to support delivery dtb to u-boot
at run time instead of embedded.
There are two methods to delivery dtb.
1 Pass from loader:
When u-boot boot from RAM, gdb or loader can pass dtb
via a2 to u-boot dynamically. Of course gdb or loader
shall be in charge of dtb delivery.
2 Configure CONFIG_SYS_FDT_BASE:
It can be configured as RAM or ROM base statically,
no mater u-boot boot from RAM or ROM.
If it was configured as ROM base, dtb can be burned
into ROM(spi flash) by spi driver.
Meanwhile remove CONFIG_SKIP_LOWLEVEL_INIT which is
useless in nx25-ae250 configuration.
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>
Remove CONFIG_MMC_NDS32 from the three config
(adp-ae3xx_defconfig, adp-ag101p_defconfig, nx25-ae250_defconfig).
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>
nsd32_mmc was created to support ftsdc010 dm.
It is not necessary to separate both, so merge it
to ftsdc010.
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>
Convert CONFIG_FTSDC010_SDIO to Kconfig.
So CONFIG_FTSDC010_SDIO can also be
removed from config_whitelist.txt.
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>
CONFIG_FTSDC010_NUMBER was not used anymore,
can be removed now.
So CONFIG_FTSDC010_NUMBER
can also be removed from config_whitelist.txt.
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>
After drop non-dm code of ftsdc010, the sd register
base definition can be droppped now.
So CONFIG_FTSDC010_BASE and CONFIG_FTSDC010_BASE_LIST both
can be removed from config_whitelist.txt
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>
Only three defconfig(adp-ag101p_defconfig,
adp-ae3xx_defconfig, nx25-ae250_defconfig)
set CONFIG_FTSDC010=y. And they all also
enable CONFIG_DM_MMC. So the non-dm code
of ftsdc010 can be dropped now.
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>
ftsdc010 dm driver has been disable High-Speed mode
as default to work around Andes AE3XX platform's problem,
because of it does not support High-Speed mode in
commit id 73cd56b2df.
But other platforms or SoCs maybe support this function.
So High-Speed mode can be enabled from dts with
cap-mmc-highspeed or cap-sd-highspeed property.
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Simply record riscv-linux booting steps and messages
from bbl via u-boot on QEMU in README.ae250.
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Add riscv uimage arch to support riscv-linux booting.
It can Convert riscv-linux to image which can be
booted by bootm command.
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
ATAGS is not supported and will be replaced
by DT in riscv-linux. So can be removed now.
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
riscv-linux should use BBL (Berkeley bootloader) for
loading the Linux kernel.
U-Boot can play as FSBL(first stage bootloader)
to boot BBL and riscv-linux.
In BBL's init_first_hart(), it will pass dtb with a1.
So implement bootm to pass arguments to BBL correctly.
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
It is reported by checkpatch.pl
WARNING: static const char * array
should probably be static const char * const
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
It is reported by checkpatch.pl
WARNING: Missing a blank line after declarations.
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
It is reported by checkpatch.pl.
CHECK: Alignment should match open parenthesis
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
It is reported by checkpatch.pl
WARNING: Use of volatile is usually wrong: see
Documentation/process/volatile-considered-harmful.rst
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
It is CHECK reported by checkpatch.pl
CHECK: Macro argument reuse 'PTE' - possible side-effects?
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
The Rockchip-specific SDHCI wrapper does not process the 'bus-width'
property in the SDHCI node. Consequently, the bus is always kept in
4bit mode, even if 8bit wide operation is available, supported and
requested in the DTS.
This change adds processing of the 'bus-width' property and sets the
host capability flag for an 8bit wide bus, if set to 8. As the logic
in sdhci.c does not support clearing the 4bit capability, we assume
that 4bit operation is always supported.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
The Rockchip-specific wrappers to the DW-MMC and the SDHCI driver
were not covered as part of what's maintained by the architecture
maintainers. Add them here.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
For the RK3399-Q7, we have a fast eMMC connected in an 8 bit wide
configuration to the SDHCI controller (sdhci@fe330000). Enable DMA
within the SDHCI driver to get the best performance out of it.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
The patch set dpll settings for 300MHz to values used by binary
blob[1]. With new values dpll still generate 300MHz clock, but
EMAC work. Probably with new values dpll generate more stable clock.
dpll on rk3188 provide clocks to DDR and EMAC. With current
dpll settings EMAC doesn't work on radxa rock. EMAC sends packets
to network, but it doesn't receive anything. ifconfig shows a lot
of framing errors.
[1] https://github.com/linux-rockchip/u-boot-rockchip/blob/u-boot-rk3288/
tools/rk_tools/3188_LPDDR2_300MHz_DDR3_300MHz_20130830.bin
Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Introduce another difference from upstream (kernel) source in
fs/ubifs/super.c: adding preprocessor condition as y variable in
mount_ubifs() depends on CONFIG_UBIFS_SILENCE_MSG:
fs/ubifs/super.c:1337:15: error: variable ?y? set but not used [-Werror=unused-but-set-variable]
long long x, y;
Not setting CONFIG_UBIFS_SILENCE_MSG in am335x_igep003x_defconfig and
igep0032_defconfig. Although it was defined in their config headers, it
depends on CMD_UBIFS which is not set for them.
Signed-off-by: Petr Vorel <petr.vorel@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Heiko Schocher <hs@denx.de>
Use of CONFIG_UBIFS_SILENCE_MSG was added in
147162dac6 ("ubi: ubifs: Turn off verbose prints")
Then it was removed in
ff94bc40af ("mtd, ubi, ubifs: resync with Linux-3.14")
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Heiko Schocher <hs@denx.de>
Signed-off-by: Petr Vorel <petr.vorel@gmail.com>
The ti,pindir-d0-out-d1-in property is not expected to have a value
according to the device-tree binding, so treat it as a boolean not a
uint property.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Alexey:
1. Significantly rework cache-related functionality.
In particular that fixes coherency problems in some corner-cases,
allows us to enable and disable caches in run-time and still
have properly running system, finally support execution from
real flash (before we used to run from DDR from the very beginning).
2. Remove string routines implemented in assembly.
That allows us to build and run U-Boot on wide range of ARC cores
with different configurations. I.e. whatever tuning is used on GCC's
command-line we'll get code for desired flavor of ARC.
Otherwise for each and every corner-case we would need to add ifdefs
in assembly code to accommodate missing instructions etc.
3. Get use of GCC's garbage collector which helps to slim-down resulting image
quite a bit.
4. Also now we may disable U-Boot self-relocation for ARC if needed either
by platform or for debugging purposes.
Refactor GO and PREP subcommands implementation for a simpler
override in the boards platform code.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Fix my fragments to list all files in the repo.
Also fix path to for Xilinx Zynq SoC (mach-zynq)
It should be the part of
"ARM: zynq: move SoC sources to mach-zynq"
(sha1: 0107f24036)
And cover dts files in board MAINTAINERS files.
Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
There is an issue to recognize zynq or zynqmp image because header
checking is just the same. That's why zynqmp images are recognized as
zynq one.
Check unused fields which are initialized to zero in zynq format
(__reserved1 0x38 and __reserved2 0x44) which are initialized for
zynqmp. This should ensure that images are properly recognized by:
./tools/mkimage -l spl/boot.bin
Also show image type as ZynqMP instead of Zynq which is confusing.
Reported-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Alexander Graf <agraf@suse.de>
This patch adds new command "zynqmp" to handle zynqmp
specific commands like "zynqmp secure". This secure command is
used for verifying zynqmp specific secure images. The secure
image can either be authenticated or encrypted or both encrypted
and authenticated. The secure image is prepared using bootgen
and will be in xilinx specific BOOT.BIN format. The optional
key can be used for decryption of encrypted image if user
key was specified while creation BOOT.BIN.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The vcu disable bit in efuse ipdisable register is valid only
if PL powered up so, consider PL powerup status for determing
EG/EV part. If PL is not powered up, ignore EG/EV part of string.
The PL powerup status will be filled by pmufw based on PL PROGB
status in the 9th bit of version field.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch print pl clocks (pl0...pl3) and watchdog
clock using clk dump.
Signed-off-by: Vipul Kumar <vipulk@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
NAND erase was not happening for size 1GiB or more. Erase
command was executing successfully but in actual, it was not
erasing.
This patch fixed erase issue for 1 GiB or more size nand.
Signed-off-by: Vipul Kumar <vipulk@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch changed CONFIG_SYS_MEMTEST_SCRATCH address to the
accessible DDR address used by alternate memory test.
Before this, 0xfffc0000 address was used, which is the OCM
address and not enabled in MMU table. So, whenever trying
to access 0xfffc0000 address, got Synchronous Abort exception.
After changing CONFIG_SYS_MEMTEST_SCRATCH address, alternate
memory test is working fine.
Signed-off-by: Vipul Kumar <vipulk@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Watchdog is only enabled in full u-boot. Adoption for SPL should be also
done because that's the right place where watchdog should be enabled.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This IP can be found on Zynq and ZynqMP devices.
The driver was tested with reset-on-timeout; feature.
Also adding WATCHDOG symbol to Kconfig because it is required.
Signed-off-by: Shreenidhi Shedi <imshedi@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
watchdog clock is also connected to cpu 1X clocksource.
Zynq> clk dump
...
Before:
swdt 4294967290
After:
swdt 111111110
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
As of now newer pmufw is keeping old interfaces. That's why permit
u-boot to run on newer version. Recommended version will be setup later.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch bypasses phy detection logic for GMII interface
and just depend on phy address received from DT. This patch
is required as phy detection logic is different for some phys
like xilinx phy which can be connected over SGMII and GMII
interface.
This fixes the issue of ethernet failures when xilinx phy is
connected over GMII interface.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This patch is adding support to switch to EL1 while loading an EL1
application with u-boot running at EL above EL1 in aarch64 mode.
Signed-off-by: Nitin Jain <nitinj@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Enable Driver Model and Device-tree support for omapl138 board
in U-Boot. Also enable DM_SERIAL and DM_I2C.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Sync dts from Linux 4.16 and also add u-boot specific
dtsi for OMAPl138 board.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Commit 6aa4ad8e38 ("Convert CONFIG_SOC_DA8XX et al to Kconfig")
converted SOC_DA8XX to Kconfig but missed enabling DDR_INIT for
SOC_DA8XX, which broke OMAPL138 to boot.
Commit 2e87980580 ("davinci: Fix omapl138_lcdk builds") disabled
DDR_INIT for all DA850 SoCs. This failed all DA850 boards to boot
as ddr is not being initialized.
Enable SYS_DA850_DDR_INIT for DA8XX so that all DA850 and OMAPL138
will have ddr initialized
Fixes: 2e87980580 ("davinci: Fix omapl138_lcdk builds")
Fixes: 6aa4ad8e38 ("Convert CONFIG_SOC_DA8XX et al to Kconfig")
Reported-by: Sekhar Nori <nsekhar@ti.com>
Tested-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: David Lechner <david@lechnology.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
With gpio devices getting created in SPL, the size of the heap is
no longer sufficient. Therefore, increase SPL_SYS_MALLOC_F_LEN
to 0x1000.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
With DM enabled in SPL, DM_FLAG_PRE_RELOC is required for
the omap_gpio driver to be bound to the gpio devices.
Therefore, add DM_FLAG_PRE_RELOC flag to the omap_gpio driver.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
scripts/check-config.sh exits successfully and silently without doing
any checks when the 'comm' command is not found.
The problem triggers from the command around line 39:
comm -23 ${suspects} ${ok} >${new_adhoc}
This statement fails when 'comm' is not in $PATH, creating an empty
${new_adhoc} file. But the script continues and the following line,
which is supposed to detect an error:
if [ -s ${new_adhoc} ]; then
will always be false since the file is empty, and the script will exit
successfully as if everything were OK.
The case where 'comm' in not in $PATH is not theoretical. It used to
happen on yocto until a recent fix [0], and still happens on the
current stable branch (rocko).
Fix by setting the errexit flag to exit with error when a statement
fails, so that at least the problem is noticed.
For additional safety also set the nounset flag to detect expansion
errors.
[0] http://git.yoctoproject.org/cgit/cgit.cgi/poky/commit/?id=fe0b4cb5b48580d4a3f3c0eb82bfa6f1b13801e4
Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
Reviewed-by: Simon Glass <sjg@chromium.org>
commit 1601dd97ed ("davinci: omapl138_lcdk: increase PLL0 frequency")
changed the PLL0 frequency to 456MHz, which is needed for the LCDC IP
block. However, in doing so, it caused the PLLOUT clock to be outside
of the allowable specifications given in the OMAP-L138 data sheet. (It
says PLLOUT must be 600MHz max). It also uses a PLLM value outside of
the range given in the TRM (it says PLLM must in the range 0 to 0x1f).
So here is what we have currently:
PLLOUT = 24 / (0 + 1) * (37 + 1) = 912MHz (out of spec)
^ ^ ^
CLKIN PREDIV PLLM (out of spec)
input to PLLDIVn = 912 / (1 + 1) = 456MHz (desired result)
^ ^
PLLOUT POSTDIV
This changes the PLLM value to 18 and the POSTDIV value to 0 so that
PLLOUT is now within specification but we still get the desired
result.
PLLOUT = 24 / (0 + 1) * (18 + 1) = 456MHz (within spec)
^ ^ ^
CLKIN PREDIV PLLM
input to PLLDIVn = 456 / (0 + 1) = 456MHz (desired result)
^ ^
PLLOUT POSTDIV
Fixes: 1601dd97ed ("davinci: omapl138_lcdk: increase PLL0 frequency")
Signed-off-by: David Lechner <david@lechnology.com>
Reported-by: Sekhar Nori <nsekhar@ti.com>
Tested-by: Sekhar Nori <nsekhar@ti.com>
Last user of this driver went away in October 2014 in
commit d58a9451e7 ("ppc/arm: zap EMK boards").
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
In
if (a > =0) {...}
else (a < 0) {...}
the second logical constraint is superfluous.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
In
int ret = A;
ret = B;
the first assignment has not effect.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The lan75xx and lan78xx drivers need to drive their phy via the generic
phylib framework. Let's reflect that dependency in Kconfig, so that we
don't get build errors when phylib does not get selected.
Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
In the efi_loader main loop we call eth_rx() occasionally. This rx function
might end up calling into devices that haven't been initialized yet,
potentially resulting in a lot of transfer timeouts.
Instead, let's make sure the ethernet device is actually initialized before
reading from or writing to it.
Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The "net_try_count" counter starts from "1".
And the "retrycnt" contains requested amount of retries.
With current logic, that means that the actual retry amount
will be one time less then what we set in "netretry" env.
For example setting "netretry" to "once" will make "retrycnt"
equal "1", so no retries will be triggered at all.
Fix the logic by changing the statement of "if" condition.
Signed-off-by: Leonid Iziumtsev <leonid.iziumtsev@se.atlascopco.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Current Cortina phy driver assumes that firmware upload
is required during initialization and is dependent
on presence of corresponding macros like CONFIG_CORTINA_FW_ADDR
for compilation.
But Cortina phy has provision to store phy firmware in
attached dedicated EEPROM. And boards designed with such
EEPROM does not require firmware upload.
Add CORTINA_NO_FW_UPLOAD option in cortina.c to support
such boards.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Update get_phy_id() implementation in cortina.c to check
for Cortina_phy by comparing device phy_id with cortina phy_id
instead of relying on presence of CORTINA macros.
This will allow get_phy_id to work with non-cortina phy devices
which might have same phy address as Cortina device but on
different bus.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
1. Set AWCACHE0 attribute of PFE DDR and HDBUS master interfaces
to bufferable.
2. Set RD/WR QoS for PFE DDR and HDBUS AXI master interfaces.
3. Disable ECC detection for PFE.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
SoC specific PFE macros are defined and structure ccsr_scfg
is updated with members defined for PFE.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
pfe_command provides command line support for several features that
support pfe, like starting or stopping the pfe, checking the health
of the processor engines and checking status of different units inside
pfe.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This patch adds PFE driver to U-Boot
Following are the main driver files:-
pfe_hw.c: provides low level helper functions to initialize PFE
internal processor engines and other hardware blocks
pfe_driver.c: provides initialization functions
and packet send and receive functions
pfe_eth.c: provides high level gemac initialization functions
pfe_firmware.c: provides functions to load firmware into PFE
internal processor engines.
pfe_mdio.c: provides functions to initialize phy and mdio.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
With CONFIG_DM_ETH enabled, aquantia driver compilation fails with
below error. This patch fixes the issue by including dm.h.
drivers/net/phy/aquantia.c: In function ‘aquantia_startup’:
drivers/net/phy/aquantia.c:73:21: error: dereferencing pointer to
incomplete
type ‘struct udevice’
phydev->dev->name);
^~
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
After allocating plat the pointer is checked.
Afterwards name is allocated and not checked.
Add the missing check to avoid a possible NULL dereference.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The Pine64+ uses a generic PHY driver, so flip it over to using the
Realtek PHY driver to actually apply the RTL8211e fix.
Signed-off-by: Kyle Evans <kevans@FreeBSD.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Setting PHY_RTL8211E_PINE64_GIGABIT_FIX forces internal rx/tx delays off
on the PHY, as well as flipping some magical undocumented bits. The
magic number comes from the Pine64 engineering team, presumably as a
proxy from Realtek. This configuration fixes the throughput on some
Pine64 models. Packet loss of up to 60-70% has been observed without
this.
Signed-off-by: Kyle Evans <kevans@FreeBSD.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Current DW SPI driver uses 32 bit access for some registers and
16 bit access for others. So if DW SPI IP is connected via bus
which doesn't support 16 bit access we will get bus error.
Fix that by switching to 32 bit access only instead of 16 and 32 bit mix
Additional Documentation to Support this Change:
The DW_apb_ssi databook states:
"All registers in the DW_apb_ssi are addressed at 32-bit boundaries
to remain consistent with the AHB bus. Where the physical size of
any register is less than 32-bits wide, the upper unused bits of
the 32-bit boundary are reserved. Writing to these bits has no
effect; reading from these bits returns 0." [1]
[1] Section 6.1 of dw_apb_ssi.pdf (version 3.22a)
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
DW SPI internal chip select management has limitation:
it hold CS line in active state only when the FIFO is not
empty. If the FIFO freed before we add new data the SPI transaction will
be broken.
So add option to use external gpio for chip select. Gpio can be added
via device tree using standard gpio bindings.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
There is no sense in waiting for RX data in dw_reader function:
there is no chance that RX data will appear in RX FIFO if
RX FIFO is empty after previous TX write in dw_writer function.
So get rid of this waiting. After that we can get rid of dw_reader
return value and make it returning void. After that we can get rid
of dw_reader return value check in poll_transfer function.
With these changes we're getting closer to Linux DW SPI driver.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
In current implementation we get -ETIMEDOUT error when we try to use
transmit only mode (SPI_TMOD_TO)
This happens because in transmit only mode input FIFO never gets any data
which breaks our logic in dw_reader(): we are waiting until RX data will be
ready in dw_reader, but this newer happens, so we return with error.
Fix that by using SPI_TMOD_TR instead of SPI_TMOD_TO which allows to use
RX FIFO.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
In current implementation if some data still exists in Tx FIFO it
can be silently flushed, i.e. dropped on disabling of the controller,
which happens when writing 0 to DW_SPI_SSIENR (it happens in the
beginning of new transfer)
So add wait for current transmit operation to complete to be sure
that current transmit operation is finished before new one.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Add a generic function which can be used to compute the CRC32 value of
a region of RAM.
Signed-off-by: Liam Beguin <liambeguin@gmail.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
As opposed to PATH, HOSTNAME is not appended to PYTHONPATH
automatically. Lets add it to the examples to make it more
obvious to new users.
Signed-off-by: Liam Beguin <liambeguin@gmail.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Fix a minor typo causing vim (and possibly other) to get confused with
coloring.
Signed-off-by: Liam Beguin <liambeguin@gmail.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Make sure 0x00 is a valid address to read to. If `addr` is 0x00 then
map_physmem() will return 0 which should be a valid address.
Signed-off-by: Liam Beguin <liambeguin@gmail.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Make sure the user is notified instead of silently returning an error.
Signed-off-by: Liam Beguin <liambeguin@gmail.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
The kwboot tool for Marvell devices isn't currently being built even if
HOST_TOOLS_ALL is set. It doesn't appear to depend on any CONFIG_
options, so it seems appropriate to enable building it here.
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
If we check an index against array bounds, we should do so before
accessing the array and not afterwards.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Add missing cache cleanup before cache disable:
* Flush and invalidate L1 D$ before disabling. Flush and invalidate
SLC before L1 D$ disabling (as it will be bypassed for data)
Otherwise we can lose some data when we disable L1 D$ if this data
isn't flushed to next level cache. Or we can get wrong data if L1 D$
has some entries after enable which we modified when the L1 D$ was
disabled.
* Invalidate L1 I$ before disabling. Otherwise we can execute wrong
instructions after L1 I$ enable if we modified any code when
L1 I$ was disabled.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Add additional cache configuration checks and note about
supported configurations.
It is unlikely to face some configuration in real life but
it's better to be prepared and refuse to work on those.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Implement specialized function to clenup caches (and therefore
sync instruction and data caches) which can be used for cleanup before linux
launch or to sync caches during U-Boot self-relocation.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
If L1 D$ is disabled SLC is bypassed for data and all
load/store requests are sent directly to main memory.
If L1 I$ is disabled SLC is NOT bypassed for instructions
and all instruction requests are fetched through SLC.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Implement icache_enabled() and dcache_enabled() as separate functions
which can be used with "inline" attribute. This is a preparation to
make them always_inline.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Move check for PAE existence into slc_upper_region_init()
instead of its caller as more appropriate place.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
There is a problem with current implementation if we start U-Boot
from ROM, as we use global variables before ther initialization,
so these variables get overwritten when we copy .data section
from ROM.
Instead we move these global variables into our "global data"
structure so that we may really start from ROM.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
There is a problem with current implementation if we start U-Boot
from ROM, as we use global variables before ther initialization,
so these variables get overwritten when we copy .data section
from ROM.
Instead we'll use icache_exists(), dcache_exists(), slc_exists(), pae_exists()
functions which directly check BCRs every time.
In U-Boot case ops are used only during self-relocation and DMA
so we shouldn't be hit by noticeable performance degradation.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
As of today we check SLC status before each call of __slc_rgn_op()
or __slc_entire_op(). So move status check into __slc_rgn_op()
and __slc_entire_op().
As we need to check status before *each* function execution and we
call slc_entire_op() and slc_rgn_op() from different places we add
this check directly into SLC entire/line functions instead of
their callers to avoid code duplication.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Use is_isa_arcv2() function where it is possible instead of
CONFIG_ISA_ARCV2 define check to make code cleaner at the same time
keeping pretty much the same functionality - code in branches
under "if (is_isa_arcv2())" won't be compiled if CONFIG_ISA_ARCV2
is not defined, still we need a couple of CONFIG_ISA_ARCV2
ifdefs to make compiler happy. That's because code in
!is_isa_x() branch gets compiled and only then gets optimized
away.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
As we are planning to get rid of dozens of ifdef's in cache.c we
would better check D$ status before each entire/line operation
then check CONFIG_SYS_DCACHE_OFF config option.
This makes the code cleaner as well as D$ entire/line functions
remain functional even if we enable or disable D$ in run-time.
As we need to check status before *each* function execution and we
call D$ entire/line functions from different places we add
this check directly into D$ entire/line functions instead of
their callers to avoid code duplication.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
We're starting to use more and more BCRs and having their
definitions in-lined in sources becomes a bit annoying
so we move it all to a separate header.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Move IOC initialization from cache_init() to a separate function.
This is the preparation for the next patch where we'll switch
to is_isa_arcv2() function usage instead of "CONFIG_ISA_ARCV2"
ifdef.
Also it makes cache_init function a bit cleaner.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
We don't implement separate flush_dcache_all() intentionally as
entire data cache invalidation is dangerous operation even if we flush
data cache right before invalidation.
There is the real example:
We may get stuck in the following code if we store any context (like
BLINK register) on stack in invalidate_dcache_all() function.
BLINK register is the register where return address is automatically saved
when we do function call with instructions like 'bl'.
void flush_dcache_all() {
__dc_entire_op(OP_FLUSH);
// Other code //
}
void invalidate_dcache_all() {
__dc_entire_op(OP_INV);
// Other code //
}
void foo(void) {
flush_dcache_all();
invalidate_dcache_all();
}
Now let's see what really happens during that code execution:
foo()
|->> call flush_dcache_all
[return address is saved to BLINK register]
[push BLINK] (save to stack) ![point 1]
|->> call __dc_entire_op(OP_FLUSH)
[return address is saved to BLINK register]
[flush L1 D$]
return [jump to BLINK]
<<------
[other flush_dcache_all code]
[pop BLINK] (get from stack)
return [jump to BLINK]
<<------
|->> call invalidate_dcache_all
[return address is saved to BLINK register]
[push BLINK] (save to stack) ![point 2]
|->> call __dc_entire_op(OP_FLUSH)
[return address is saved to BLINK register]
[invalidate L1 D$] ![point 3]
// Oops!!!
// We lose return address from invalidate_dcache_all function:
// we save it to stack and invalidate L1 D$ after that!
return [jump to BLINK]
<<------
[other invalidate_dcache_all code]
[pop BLINK] (get from stack)
// we don't have this data in L1 dcache as we invalidated it in [point 3]
// so we get it from next memory level (for example DDR memory)
// but in the memory we have value which we save in [point 1], which
// is return address from flush_dcache_all function (instead of
// address from current invalidate_dcache_all function which we
// saved in [point 2] !)
return [jump to BLINK]
<<------
// As BLINK points to invalidate_dcache_all, we call it again and
// loop forever.
Fortunately we may do flush and invalidation of D$ with a single one
instruction which automatically mitigates a situation described above.
And because invalidate_dcache_all() isn't used in common U-Boot code we
implement "flush and invalidate dcache all" instead.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Introduce is_isa_arcv2() and is_isa_arcompact() functions.
These functions only check configuration options and return
compile-time constant so they can be used instead of #ifdef's to
to write cleaner code.
Now we can write:
-------------->8---------------
if (is_isa_arcv2())
ioc_configure();
-------------->8---------------
instead of:
-------------->8---------------
ifdef CONFIG_ISA_ARCV2
ioc_configure();
endif
-------------->8---------------
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
As of today __dc_line_op() and __dc_entire_op() support
only separate flush (OP_FLUSH) and invalidate (OP_INV) operations.
Add support of combined flush and invalidate (OP_FLUSH_N_INV)
operation which we planing to use in subsequent patches.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
__cache_line_loop() function was copied from Linux kernel
where per-line instruction cache operations are really used.
In U-Boot we use only entire I$ ops, so we can drop support of
per-line I$ ops from __cache_line_loop() because __cache_line_loop()
is never called with OP_INV_IC parameter.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Move instruction cache entire operation to a separate function
because we are planing to use it in other places like
sync_icache_dcache_all().
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
We improve on 2 things:
1. Only ARC HS family has "dmb" instructions so do compile-time
check for automatically defined macro __ARCHS__.
Previous check for ARCv2 ISA was not good enough because ARC EM
family is v2 ISA as well but still "dmb" instaruction is not
supported in EM family.
2. Still if there's no dedicated instruction for memory barrier
let's at least insert compile-time barrier to make sure
compiler deosn't reorder critical memory operations.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Disabling relocation might be useful on ARC for 2 reasons:
a) For advanced debugging with Synopsys proprietary MetaWare debugger
which is capable of accessing much more specific hardware resources
compared to gdb. For example it may show contents of L1 and L2 caches,
internal states of some hardware blocks etc.
But on the downside MetaWare debugger still cannot work with PIE.
Even though that limitation could be work-arounded with change of ELF's
header and stripping down all debug info but with it we won't have
debug info for source-level debugging which is quite inconvenient.
b) Some platforms which might benefit from usage of U-Boot basically
don't have enough RAM to accommodate relocation of U-Boot so we
keep code in flash and use as much of RAM as possible for more
interesting things.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: York Sun <york.sun@nxp.com>
Cc: Stefan Roese <sr@denx.de>
Finally GCC's garbage collector works on ARC so let's use it.
That's what I may see for HSDK:
Before:
text data bss dec hex filename
290153 10068 222616 522837 7fa55 u-boot
After:
text data bss dec hex filename
261999 9460 222360 493819 788fb u-boot
Overall ~5% of memory footprint saved.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
This commit basically reverts two commits:
1. cf628f772e ("arc: arcv1: Disable master/slave check")
2. 6cba327bd9 ("arcv2: Halt non-master cores")
With mentioned commits in-place we experience more trouble than
benefits. In case of SMP Linux kernel this is really required as
we have all the cores running from the very beginning and then we
need to allow master core to do some preparatory work while slaves
are not getting in the way.
In case of U-Boot we:
a) Don't really run more than 1 core in parallel
b) We may use whatever core for that
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
U-Boot is a bit special piese of software because it is being
only executed once on power-on as compared to operating system
for example. That's why we don't care much about performance
optimizations instead we're more concerned about size. And up-to-date
compilers might produce much smaller code compared to
performance-optimized routines copy-pasted from the Linux kernel.
Here's an example:
------------------------------->8--------------------------
--- size_asm_strings.txt
+++ size_c_strings.txt
@@ -1,2 +1,2 @@
text data bss dec hex filename
- 121260 3784 3308 128352 1f560 u-boot
+ 120448 3784 3308 127540 1f234 u-boot
------------------------------->8--------------------------
See we were able to shave off ~800 bytes of .text section.
Also usage of string routines implemented in C gives us an ability
to support more HW flavors for free: generated instructions will match
our target as long as correct compiler option is used.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Fix NOR, SD and QSPI fallback option in case of secure boot failure.
Signed-off-by: Vinitha V Pillai <vinitha.pillai@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
IFC-NOR and QSPI-NOR pins are multiplexed on SoC, so they cannot be
accessed simultaneously. IFC-NOR can be accessed along with SD-BOOT.
Ls1088aqds_sdcard_ifc_defconfig is default config for SD boot and
IFC-NOR to be used as flash. This allows writing to IFC-NOR flash.
QSPI and DSPI cannot be accessed in this defconfig.
IFC-NOR image is generated using ls1088aqds_defconfig.
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This function is required for enabling access to early i2c function
for correct usage of QIXIS_READ and QIXIS_WRITE.
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
get_board_ddr_clk(), get_board_sys_clk() and if_board_diff_clk() is
now available for SPL build.
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This patch adds a new type IH_OS_TEE. This new OS type will be used for
chain-loading to Linux via a TEE.
With this patch in-place you can generate a bootable OPTEE image like this:
mkimage -A arm -T kernel -O tee -C none -d tee.bin uTee.optee
where "tee.bin" is the input binary prefixed with an OPTEE header and
uTee.optee is the output prefixed with a u-boot wrapper header.
This image type "-T kernel -O tee" is differentiated from the existing
IH_TYPE_TEE "-T tee" in that the IH_TYPE is installed by u-boot (flow
control returns to u-boot) whereas for the new IH_OS_TEE control passes to
the OPTEE firmware and the firmware chainloads onto Linux.
Andrew Davis gave the following ASCII diagram:
IH_OS_TEE: (mkimage -T kernel -O tee)
Non-Secure Secure
BootROM
|
-------------
|
v
SPL
|
v
U-Boot ------>
<----- OP-TEE
|
V
Linux
IH_TYPE_TEE: (mkimage -T tee)
Non-Secure Secure
BootROM
|
-------------
|
v
SPL ------->
<----- OP-TEE
|
v
U-Boot
|
V
Linux
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Suggested-by: Andrew F. Davis <afd@ti.com>
Cc: Harinarayan Bhatta <harinarayan@ti.com>
Cc: Andrew F. Davis <afd@ti.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Cc: Peng Fan <peng.fan@nxp.com>
Link: http://mrvan.github.io/optee-imx6ul
CONFIG_OPTEE_LOAD_ADDR is used to tell u-boot where to load the OPTEE
binary into memory prior to handing off control to OPTEE.
We need to pull this value out of u-boot in order to produce an IMX IVT/CSF
signed pair for the purposes of secure boot. The best way to do that is to
have CONFIG_OPTEE_LOAD_ADDR appear in u-boot.cfg.
Adding new CONFIG entires to u-boot should be kconfig driven so this patch
does just that.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org>
OPTEE is currently linked to a specific area of memory called the TrustZone
DRAM. This patch adds a CONFIG entry for the default address of TrustZone
DRAM that a board-port can over-ride. The region that U-Boot sets aside for
the OPTEE run-time should be verified before attempting to hand off to the
OPTEE run-time. Each board-port should carefully ensure that the TZDRAM
address specified in the OPTEE build and the TZDRAM address specified in
U-Boot match-up.
Further patches will use TZDRAM address with other defines and variables to
carry out a degree of automated verification in U-Boot prior to trying to
boot an OPTEE image.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Cc: Harinarayan Bhatta <harinarayan@ti.com>
Cc: Andrew F. Davis <afd@ti.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
OPTEE is currently linked to a specific area of memory called the TrustZone
DRAM. This patch adds a CONFIG entry for the default size of TrustZone DRAM
that a board-port can over-ride. The region that U-Boot sets aside for the
OPTEE run-time should be verified before attempting to hand off to the
OPTEE run-time. Each board-port should carefully ensure that the TZDRAM
size specified in the OPTEE build and the TZDRAM size specified in U-Boot
match-up.
Further patches will use TZDRAM size with other defines and variables to
carry out a degree of automated verification in U-Boot prior to trying to
boot an OPTEE image.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Cc: Harinarayan Bhatta <harinarayan@ti.com>
Cc: Andrew F. Davis <afd@ti.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Cc: Peng Fan <peng.fan@nxp.com>
Tested-by: Peng Fan <peng.fan@nxp.com>
This patch adds code to lib to enable sharing of useful OPTEE code between
board-ports and architectures. The code on lib/optee/optee.c comes from the
TI omap2 port. Eventually the OMAP2 code will be patched to include the
shared code. The intention here is to add more useful OPTEE specific code
as more functionality gets added.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Cc: Harinarayan Bhatta <harinarayan@ti.com>
Cc: Andrew F. Davis <afd@ti.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Cc: Peng Fan <peng.fan@nxp.com>
Tested-by: Peng Fan <peng.fan@nxp.com>
ppc4xx support was removed some time ago. Lets remove the now unused
entry in MAINTAINERS as well.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
ppc4xx support was removed some time ago. Lets remove the now unused
"pci_fb" variable from "struct pci_controller" as well.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
ppc4xx support was removed some time ago. Lets remove the now unused
NAND driver and all its references for this platform as well.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Cc: Scott Wood <oss@buserror.net>
Add first support for STM32MP157C-ED1 board with "Basic" boot chain
1/ Boot Rom: load SPL with STM32 image header in SYSRAM
2/ SPL: power up and initialize the DDR and load U-Boot image
from SDCARD in DDR
3/ U-Boot: search and load extlinux.conf in SDCARD
(DISTRO activated)
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Add minimal devicetree for STM32MP157C-ED1 board,
with only the devices to allow boot from SDCARD:
- RCC for clock and reset
- UART4 for console
- I2C and PMIC
- DDR
- SDMMC0 for SDCard
Waiting Kernel upstream for alignment.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
add RCC clock driver for STMP32MP157
- base on driver model = UCLASS_CLK
- support ops to enable, disable and get rate
of all SOC clock needed by U-Boot
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
- add the 2 new compatible used by STM32MP157
"st,stm32mp157-pinctrl"
"st,stm32mp157-z-pinctrl"
- update the mask for the port
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
This driver implements register read/write operations for STPMU1.
The STPMU1 PMIC provides 4 BUCKs, 6 LDOs, 1 VREF
and 2 power switches. It is accessed via an I2C interface.
This device is used with STM32MP1 SoCs.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
- add new arch stm32mp for STM32 MPU/Soc based on Cortex A
- support for stm32mp157 SOC
- SPL is used as first boot stage loader
- using driver model for all the drivers, even in SPL
- all security feature are deactivated (ETZC and TZC)
- reused STM32 MCU drivers when it is possible
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Kmalloc is using memalign allocation function. It is not necessary to
align this structure so to save bytes, we move to calloc.
And kmalloc function can't be used in SPL early stage (in board_init_f())
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
The current value timer_rate_hz causes a problem with function
timer_get_us() from lib time and then an issue with
readx_poll_timeout() function.
With corrected value for tbclk() = timer_rate_hz = CONFIG_SYS_HZ_CLOCK
the weak functions in lib timer can be used:
- get_timer()
- __udelay()
So the specific function in this file are removed.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Add option to include RESET driver and uclass in SPL.
That can be useful to handle IP reset with same driver
in U-Boot and in SPL.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
STM32MP157 bootrom needs a specific header for first boot stage.
This patch adds support of this header in mkimage.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
If the U-Boot environment is stored in a regular file and redundant
operation isn't set, then write to a temporary file and perform an
atomic rename.
Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
Extract write path of flash_io() into a separate function. This patch
should be a functional no-op.
Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Pass tools/env/fw_env.c through indent to correct style violations. This
commit consists of only one non-whitespace change:
tools/env/fw_env.c:549: error: do not use assignment in if condition
Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
U-boot proper signature is not verified by SPL on most platforms
even config SPL_FIT_SIGNATURE is enabled. Only fsl-layerscape
platform support secure boot in platform specific code. So
verified boot cannot be achieved if u-boot proper is loaded by
SPL.
This patch add signature verification to u-boot proper images
when loading FIT image in SPL. It is tested on Allwinner bananapi
zero board with H2+ SoC.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Add proper and simple kconfig option for dram_sun8i_a83t.c
instead of using MACH type on Makefile.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Add proper and simple kconfig option for dram_sun8i_a33.c
instead of using MACH type on Makefile.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Add proper and simple kconfig option for dram_sun8i_a23.c
instead of using MACH type on Makefile.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Add simple and meaningful kconfig option for prcm.c
instead of using MACH type on Makefile.
PRCM (Power/Reset/Clock Management) is considered as a
Multi-Functional Device, so used the same on Kconfig definition.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Support several pixel format (8bits, 16bits, 24bits & 32bits).
Add new file st_logo_data.h which contains logo
stmicroelectronics_uboot_logo_8bit_rle.bmp.
Signed-off-by: yannick fertre <yannick.fertre@st.com>
Enable the display controller, panel & backlight.
Set panel display timings & set the RGB data bus.
Signed-off-by: yannick fertre <yannick.fertre@st.com>
This patch increases timeout to 2s.
It was seen on 2 USB devices (Verbatim STORE N GO 070B4AED0FB22358 and
USB DISK 2.0 9000729BA41DDF40) that the request sense command takes
between 1.3s and and 1.5s.
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
This patch adds an interface to disable the power in dwc2 driver.
This new interface is called when the device is removed.
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Factorize PHY get/init/poweron and PHY poweroff/exit operations
into separate function, it simplify the error path.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Add generic_phy_power_on() and generic_phy_power_off()
calls to switch ON/OFF phy during probe and remove functions.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Factorize PHY get/init/poweron and PHY poweroff/exit operations
into separate function, it simplify the error path.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
ppc4xx support was removed some time ago. Lets remove the now unused
EHCI driver and all its references for this platform as well.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Cc: Marek Vasut <marex@denx.de>
DWC3 USB3 controllers will need USB3 PHY to be enabled, in addition to
USB2 PHY, to be functional. Therefore enable USB3 PHY when available.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Refractor PHY get/init/poweron and PHY poweroff/exit operations into
separate function so that its easy to support multiple PHYs.
Signed-off-by: Vignesh R <vigneshr@ti.com>
It is wrong that expect .phy_init() to also power on the PHY. Therefore,
explicitly, call generic_phy_power_on() after generic_phy_power_init() in
order to power on PHY before using it.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
If we use hardware with very small RAM (let's consider just a couple
of hundreds of kB but not megabytes) it is not super convenient to lose
64kB for statically allocated bufer which most probably won't be used
as big as it is. Typically we'll have much shorter data packages to
excahnge and in the worst case longer packets will be split on separate
transactions.
For those corner-cases user will be able to set his buffer size of
choice via USB_DWC2_BUFFER_SIZE option in menuconfig.
By default we'll use 64 kB as it was hard-coeded before so existing
users shouldn't be affected at all.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Marek Vasut <marex@denx.de>
Merge init_helpers.h in the new file init.h
with only prototypes for init_cache_f_r
used in common/board_f.c
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Move prototypes for function used in common/board_f.c
from common.h to init.h
Remove weak for arch_reserve_stacks in prototype
(checkpatch issue)
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
This file is completely unused and it should be removed as the part of
ppc405/ppc440 xilinx platform removal.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Change due to commit b08c8c4870 ("libfdt: move headers to
<linux/libfdt.h> and <linux/libfdt_env.h>")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
arch/arm/cpu/armv7/mx*/ does not relate to any existing directory.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
The 2 functions board_power_mode and board_poweroff
are no more existing in U-Boot code (check with grep)
This patch updates the documentation and removes
the unnecessary prototypes.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Remove the prototypes for 4 functions no more existing
in U-Boot code (checked by grep):
- checkflash
- checkdram
- mdm_init
- setup_board_extra
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Add a new file init.h with the prototype for arch_cpu_init
Add a prototype for mach_cpu_init() to avoid a warning:
no previous prototype for ‘mach_cpu_init’
It is a first step to move all the functions prototype
used during U-Boot initialization (board_f.c / board_r.c)
from common.h to init.h
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This converts the following to Kconfig:
CONFIG_CONS_INDEX
We have existing entries for this option in a number of places, with
different guards on them. They're also sometimes used for things not
directly inside of the serial driver. First, introduce a new symbol to
guard the use of CONFIG_CONS_INDEX, so that in the case where we don't
need this for the serial driver, but for some other use, we can still do
it. Next, consolidate all of these into the single entry in
drivers/serial/Kconfig. Finally, introduce CONS_INDEX_[023456] so that
we can imply a correct value here to make the defconfig side of this
smaller.
Signed-off-by: Adam Ford <aford173@gmail.com>
[trini: Rework a lot of the logic here, such that I took authorship from
Adam, but kept his S-o-B line]
Signed-off-by: Tom Rini <trini@konsulko.com>
It is safe to always setup the pinmux for UART1 and UART3 to be used in
early_padconf and then if these pins are needed later on, they will be
re-muxed. This allows us to drop the usage of CONFIG_CONS_INDEX here.
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Due to adding various new functionalities with SPI and SPI-FLASH
subsystems which are rounding in Mailing list for year these long
term supporting spi driver which never seen any update with
driver-model conversion.
So added migration plan for DM_SPI and DM_SPI_FLASH with
deadline v2018.09
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Adds a dedicated defconfig to build TI K2L secure
devices and updates MAINTAINERS.
k2l_hs_evm_defconfig is created from the k2l_evm_defconfig
and removes support for SPL, as SPL is not supported on K2
HS devices. Corrects SYS_TEXT_BASE for HS devices.
Also adds TI_SECURE_DEVICE and FIT_IMAGE_POST_PROCESS to
include support for secure image creation and authentication
Signed-off-by: Madan Srinivas <madans@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Andrew F. Davis <afd@ti.com>
This patch updates the default u-boot env for K2L HS devices
to install the secure boot monitor and load the fitImage during
boot.
Signed-off-by: Madan Srinivas <madans@ti.com>
Acked-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Remove busy looping during watchdog reset.
Each polling of W_PEND_WTGR bit ("finish posted
write") after watchdog reset takes 120-140us
on BeagleBone Black board. Current U-Boot code
has watchdog resets in random places and often
there is situation when watchdog is reset
few times in a row in nested functions.
This adds extra delays and slows the whole system.
Instead of polling W_PEND_WTGR bit, we skip
watchdog reset if the bit is set. Anyway, watchdog
is in the middle of reset *right now*, so we can
just return.
This noticeably increases performance of the
system. Below are some measurements on BBB:
- DFU upload over USB 15% faster
- fastboot image upload 3x times faster
- USB ep0 transfers with 4k packets 20% faster
Signed-off-by: Ruslan Bilovol <ruslan.bilovol@gmail.com>
Tested-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Tested-by: Alex Kiernan <alex.kiernan@gmail.com>
serial# variable is needed to show the device correctly in "fastboot
devices" output. It's useful when we have several devices (in fastboot
mode) connected to single host and want to choose which one to flash.
We can't use omap_die_id_serial() for this, because AM335x lacks
DIE_ID, as can be seen from AM335x TRM. Let's do next:
- reuse board_serial variable (obtained from EEPROM in
set_board_info_env() function) to set serial#
- if board_serial is "unknown", reuse ethaddr variable to set serial#
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
As said in the SAMA5D2 datasheet, the PLLA clock must be divided
by 2 by writing the PLLADIV2 bit in PMC_MCKR, if the ratio between
PCK and MCK is 3 (MDIV = 3). This is the purpose of the driver.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Add USB clock driver to configure the input clock and the divider
in the PMC_USB register to generate a 48MHz and a 12MHz signal to
the USB Host OHCI.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
The kernel size is getting bigger and bigger. Because the Android
common kernel is even bigger than the vanilla one, so images overlap
in the current memory layout.
Adjust the load address for a bigger kernel image.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
If a bigger EL32 is used, fip.bin can be larger than the currently
assumed boot firmware size. Adjust the update commands.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
With the introduction of ("Boards,Need,to,Switch,DM] spi: omap3_spi:
Full dm conversion"), Driver Model for McSPI is now available on the
omap3. This enables the config by default on omap3_logic boards.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
omap3_spi_set_speed|mode redeclared bus symbol, fix the same.
error:
drivers/spi/omap3_spi.c: In function ‘omap3_spi_set_speed’:
drivers/spi/omap3_spi.c:650:18: error: ‘bus’ redeclared as different kind of symbol
struct udevice *bus = dev->parent;
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Commit 278b90ce78 ("configs: Migrate CONFIG_SYS_TEXT_BASE") made
CONFIG_SYS_TEXT_BASE a proper Kconfig variable, with the consequence
of moving the common definition shared by almost every sunxi board
into 123 individual defconfig files. But the U-Boot start address
for Allwinner boards is a platform decision which has been around for
ages, so defining it in each *board* config file seems a bit over the
top.
Define the standard values (160MB into DRAM for most SoCs, with two
SoC exceptions) if ARCH_SUNXI is selected, and delete the lines from
the individual defconfigs.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
For the last return of function get_ram_size(),
when size=maxsize, restore the base address (*base)
content.
Add comment for the remaining case to avoid regression:
this case is already correctly handled.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Save the content of the base address in a new variable
in stack (save_base) to prepare restore this content.
This patch don't modified code behavior and stack usage.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
When enabling CONFIG_FASTBOOT_FLASH in am335x_boneblack_defconfig, next
build errors and warnings occur:
arch/arm/mach-omap2/utils.c: In function ‘omap_set_fastboot_cpu’:
arch/arm/mach-omap2/utils.c:26:16: warning: implicit declaration of
function ‘omap_revision’ [-Wimplicit-function-declaration]
u32 cpu_rev = omap_revision();
^~~~~~~~~~~~~
arch/arm/mach-omap2/utils.c:29:7: error: ‘DRA762_ES1_0’ undeclared
(first use in this function)
Include asm/omap_common.h explicitly to avoid those.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Acked-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
The SPL can't use high speed MMC modes if the associated pinctrl and
IOdelays are described in the DTS.
Make them available in SPL by tagging the nodes with 'u-boot,dm-spl;'
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Beside enabling the support for HS200 in mmc core, enabling the HS200
support in the SPL requires multi-dtb support in the SPL because pinctrl
and IOdelays vary across SOCs.
Also we need to make sure that the pinctrl properties arenot removed from
the dts by setting CONFIG_OF_SPL_REMOVE_PROPS to remove only clocks and
interrupts properties.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Now that we have a device-tree include file with common
MMC/SD IOdelay data for DRA76x SoC, shift the EVM device-tree
file to using that.
Also fix the name of the IO voltage regulator for mmc1.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Add a common device-tree include file with MMC/SD IOdelay data
for DRA76x SoC based on the linux DTSI file.
In the most common case, IOdelay data available in datamanual
can directly be used. This file caters to that common case.
Data is based on DRA76x datamanual, SPRS993A, revised July 2017.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
This commit does the following for OMAP3 EVM:
- Track omap3_beagle changes where possible
- Remove CONFIG_SYS_MPUCLK and CONFIG_MTD which are not needed for the
default board configuration to work.
- Remove CONFIG_SPL_SYS_MALLOC_SIMPLE and CONFIG_SYS_MALLOC_F_LEN from
default config. CONFIG_SYS_MALLOC_F_LEN=0x400 is set by configuration
automatically. [allows board to boot with SERIAL_SEARCH_ALL=y]
- Use updated NAND layout:
device nand0 <omap2-nand.0>, # parts = 6
#: name size offset
-------------------------------------------------
0: spl 0x00080000(512k) 0x00000000
1: u-boot 0x001e0000(1920k) 0x00080000
2: u-boot-env 0x00020000(128k) 0x00260000
3: dtb 0x00020000(128k) 0x00280000
4: kernel 0x00600000(6m) 0x002a0000
5: rootfs 0x0f760000(-) 0x008a0000
-------------------------------------------------
Signed-off-by: Derald D. Woods <woods.technical@gmail.com>
This commit does the following for BeagleBoard{-xM}:
- Enable DM_SERIAL which also enables SPL_DM_SERIAL
- Misc. config updates in support of DM_SERIAL
- Use updated NAND layout (BeagleBoard):
device nand0 <omap2-nand.0>, # parts = 6
#: name size offset
-------------------------------------------------
0: spl 0x00080000(512k) 0x00000000
1: u-boot 0x001e0000(1920k) 0x00080000
2: u-boot-env 0x00020000(128k) 0x00260000
3: dtb 0x00020000(128k) 0x00280000
4: kernel 0x00600000(6m) 0x002a0000
5: rootfs 0x0f760000(-) 0x008a0000
-------------------------------------------------
- Use MMC and UBIFS support from config_distro_bootcmd.h
- Use LEGACY_MMC and NAND support defined in omap3_beagle.h
[MMC(0:1)/extlinux/extlinux.conf]
---8<-------------------------------------------------------------------
default omap3-beagle-mmc-fat
label omap3-beagle-mmc-fat
kernel /zImage
fdt /omap3-beagle.dtb
append console=ttyO2,115200n8 root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait
---8<-------------------------------------------------------------------
[LEGACY_MMC(0:2)/boot/extlinux/extlinux.conf]
---8<-------------------------------------------------------------------
default omap3-beagle-mmc-ext4
label omap3-beagle-mmc-ext4
kernel /boot/zImage
fdt /boot/omap3-beagle.dtb
append console=ttyO2,115200n8 root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait
---8<-------------------------------------------------------------------
[UBIFS(ubi0:rootfs)/boot/extlinux/extlinux.conf]
---8<-------------------------------------------------------------------
default omap3-beagle-nand-ubifs
label omap3-beagle-nand-ubifs
kernel /boot/zImage
fdt /boot/omap3-beagle.dtb
append console=ttyO2,115200n8 root=ubi0:rootfs rw ubi.mtd=rootfs rootfstype=ubifs rootwait
---8<-------------------------------------------------------------------
The board's 'bootcmd' can also be overridden with:
CONFIG_BOOTCOMMAND="run findfdt; run mmcboot"
CONFIG_BOOTCOMMAND="run findfdt; run nandboot"
CONFIG_BOOTCOMMAND="run findfdt; run ramboot"
or
CONFIG_BOOTCOMMAND="run findfdt; run somethingelse"
The use of 'run findfdt' is required.
Signed-off-by: Derald D. Woods <woods.technical@gmail.com>
BeagleBoard 'xM' does not really have NAND. CONFIG_MTDIDS_DEFAULT and
CONFIG_MTDPARTS_DEFAULT can/should be empty for 'xM'. This commit sets
the defined values if they exist.
Signed-off-by: Derald D. Woods <woods.technical@gmail.com>
Get the start address and the size of partitions using partition names
rather than partition numbers. This way we can change the partition
table further without changing the boot code.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Refactor the code for "part start" and "part size" commands to avoid
code duplication.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Allow passing the partition name to "part start" and "part size"
commands, so we can avoid magic numbers in the environment.
Consider one real use-case: in include/environment/ti/boot.h we have
commands like these:
setenv boot_part 9
part start mmc ${mmcdev} ${boot_part} boot_start
part size mmc ${mmcdev} ${boot_part} boot_size
mmc read ${loadaddr} ${boot_start} ${boot_size}
Now suppose that we have changed the partition table and boot_part now
is 10. We will need to fix commands above. And anyone who relies on
these boot commands, will need to change them accordingly, too (this was
an actual case in our lab while testing Linux boot on Android
environment).
By providing the option to pass partition name instead, we fix mentioned
issue, by eliminating the necessity to use magic numbers.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Currently, if a test emits a warning message but otherwise passes, there's
no indication of this in the log summary, which can lead to warnings being
missed. Enhance the test logic to explicitly mention warnings in otherwise
passing tests, and not to collapse the log sections for tests with
warnings, so that they're more easily seen when scanning the log.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add a standalone MMC block read test. This allows direct testing of MMC
access rather than relying on doing so as a side-effect of e.g. DFU or
UMS testing, which may not be enabled on all platforms.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Do not need to scan disk every time when we get part info
by name.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
[trini: Fix build in !CONFIG_HAVE_BLOCK_DEVICE case]
Signed-off-by: Tom Rini <trini@konsulko.com>
If a DUT do not have partition table, and we write one with 'gpt write'
cmd, we should able to list the partition with 'part list' cmd.
It's reasonable to scan the disk again if the initial part_type is
unknown in case we just write a new one into disk.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
On linux kernel side, on STM32F7 and STM32H7 SoCs, DMA requires
uncachable regions. These regions are defined in DT.
Since kernel linux v4.15, on ARMv7-M Cortex, kernel is able
to configure MPU regions depending on DT settings.
As kernel is able to configure MPU, this allows to remove
MPU region settings in bootloader.
On Cortex M processors, MPU allows to use a default memory map.
(see B3.5.4 MPU Control Register, MPU_CTRL in
https://developer.arm.com/products/architecture/m-profile/docs/ddi0403/latest/armv7-m-architecture-reference-manual)
Use the default memory map as background region for all STM32 SoCs
family with an additional MPU region corresponding to the SDRAM area.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Enable DOS_PARTITION for boards STM32F429-eval, STM32F469-disco
and STM32F746-disco.
This allows to read FAT partition on mmc.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
This board offers:
_ STM32F746NGH6 microcontroller with 1 Mbyte Flash and 320+4 Kbytes RAM
_ Six 5 V power supply options:
Power jack
ST-LINK/V2-1 USB connector
User USB HS connector
User USB FS1 connector
User USB FS2 connector
Daughterboard
_ SAI Audio DAC, stereo audio jack which supports headset with microphone
_ Stereo digital microphone, audio jack connector used to connect
external speakers
_ 2 Gbytes (or more) SDMMC interface microSD card
_ RF-EEPROM on I2C compatible serial interface
_ RS-232 communication
_ IrDA transceiver
_ JTAG/SWD and ETM trace debug support, ST-LINK/V2-1 embedded
_ IEEE-802.3-2002 compliant Ethernet connector
_ Camera module
_ 8Mx32 bit SDRAM, 1Mx16 bit SRAM & 8Mx16 bit Nor Flash
_ 512 Mbits QuadSPI Nor Flash
_ 5.7 inch 640x480 pixel TFT color LCD with capacitive touch panel
_ Joystick with 4-direction control and selector
_ Reset, WakeUp/Tamper or key button
_ 4 color user LEDs
_ Extension connectors & memory connectors for daughterboard or
wrapping board
_ USB OTG HS and FS with Micro-AB connectors
_ RTC with backup battery
_ CAN 2.0A/B compliant connection
_ Potentiometer
_ Motor control connector
More detailed information are available here :
http://www.st.com/en/evaluation-tools/stm32746g-eval.html
To compile stm32f746-eval board, use same defconfig as
stm32f746-disco, the only difference is to pass
"DEVICE_TREE=stm32746g-eval".
Signed-off-by: Christophe Priouzeau <christophe.priouzeau@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Vikas Manocha <vikas.manocha@st.com>
Remove arch/arm/include/asm/arch-stm32fx/stm32_periph.h
as all defines or enums are no more used.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
For STM32F4 and F7 SoCx family, a specific stm32.h file exists.
Some common defines are duplicated or even unused in each of
these stm32.h.
Factorize all common definition in arch/arm/include/asm/stm32f.h and keep
specific definitions in each arch/arm/include/asm/arch-stm32fx/stm32.h.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Instead to have 3 identical gpio.h for all STM32 SoCs,
migrate them in one file in include/asm.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
fmc.h file is no more used, remove it.
All FMC related defines are declared in drivers/ram/stm32_sdram.c
which is common to all STM32 SoCs.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
This avoids the following errors while reading on mmc:
Read data bytes CRC error: 0x2
switch to partitions #0, OK
mmc0 is current device
Read data bytes CRC error: 0x82002
** Unrecognized filesystem type **
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
DSI clock is available on STM32F769-disco and
STM32F469-disco board.
Signed-off-by: Yannick Fertre <yannick.fertre@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Implement set_rate() for LTDC clock only, set_rate for other
clocks will be added if needed. This is needed by future LTDC driver
improvements.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Configure SAI PLL configuration to generate LTDC pixel clock on
the PLLSAIR output.
PLLSAI is enabled only if CONFIG_VIDEO_STM32 flag is set.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Rework the way SDMMC clock get rate is done in a more
generic way :
_ Add stm32_clk_get_pllsai_rate() which give the PLLSAI
indicated output rate.
_ Add stm32_clk_get_pllsai_vco_rate() which give the VCO
internal rate.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Initially, 48Mhz for SDIO clock was generated from SAI pll for
STM32F469 and STM32F746 SoCs, but this solution was not suitable
for STM32F429 SoCs.
A generic solution is to used the PLL_Q output as 48Mhz clock
for all STM32F SOCs family.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Wrong parameter was passed to stm32_clk_pll48clk_rate().
sysclk (PLL_p output value) was passed instead of VCO value.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
This patch adds "st,pin-ckin" support to activate sdmmc_ckin feature.
When using an external driver (a voltage switch transceiver),
it's advised to select SDMMC_CKIN feedback clock input to sample
the received data.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
The hardware flow control functionality is used to avoid
FIFO underrun (TX mode) and overrun (RX mode) errors.
The behavior is to stop SDMMC_CK during data transfer and
freeze the SDMMC state machines.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Use available DM stm32_timer driver instead of dedicated
mach-stm32/stm32fx/timer.c.
Remove all defines or files previously used for timer usage in
arch/arm/include/asm/arch-stm32fx and in arch/arm/mach-stm32/stm32fx
Enable DM STM32_TIMER for STM32F4/F7 and H7.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
This timer driver is using GPT Timer (General Purpose Timer)
available on all STM32 SOCs family.
This driver can be used on STM32F4/F7 and H7 SoCs family
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Add supporting regulators for rk3288-vyasa board, dc12_vbat is
parent regulatorand followed regulators as are child regulators.
regulator naming conversion followed as per schematic for better
readability and easy for identification.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Booting a aarch64 Linux kernel requires the image to be placed
text_offset bytes from a 2MB aligned address.
See https://www.kernel.org/doc/Documentation/arm64/booting.txt
booti_setup() takes care about this alignment and will relocate the
image if not properly aligned with memmove(). This can require up
to double the size of the loaded image and therefore accidentally
overwrite content placed there (i.e ramdisk_addr_r) for large kernel
images.
By adding text_offset to the default kernel_addr_r we can prevent that
from happening for kernels larger 18MB and also save a few cycles.
We can assume a text_offset of 0x80000 for most cases, all others will be
handled by booti_setup() anyway.
Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
A20-SOM204 board has option with onboard 16GB eMMC. The chip is wired
to MMC2 slot.
This patch adds defconfig and dts files for this board. The dts is same
with mainline kernel.
Signed-off-by: Stefan Mavrodiev <stefan@olimex.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
This is new System-On-Module platform with universal dimm socket for
easy insertation. The EVB board is designed to be universal with
future modules.
Base features of A20-SOM204 board includes:
* 1GB DDR3 RAM
* AXP209 PMU
* KSZ9031 Gigabit PHY
* AT24C16 EEPROM
* Status LED
* LCD connector
* GPIO connector
There will be variants with the following options:
* Second LAN8710A Megabit PHY
* 16MB SPI Flash memory
* eMMC card
* ATECC508 crypto device
The EVB board has:
* Debug UART
* MicroSD card connector
* USB-OTG connector
* Two USB host
* RTL8723BS WiFi/BT combo
* IrDA transceiver/receiver
* HDMI connector
* VGA connector
* Megabit ethernet transceiver
* Gigabit ethernet transceiver
* SATA connector
* CAN driver
* CSI camera
* MIC and HP connectors
* PCIe x4 connector
* USB3 connector
* Two UEXT connectors
* Two user LEDs
Some of the features are multiplexed and cannot be used the same time:
CAN and Megabit PHY. Others are not usable with A20 SoC: PCIe and USB3.
This patch adds defconfig and dts files for this board. The dts is same
with mainline kernel, except some nodes are removed to make file
compatible with existing dtsi file.
Signed-off-by: Stefan Mavrodiev <stefan@olimex.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
CONFIG_PHY_ADDR is used for old-style configuration. This makes
impossible changing the PHY address, if multiple boards share a same
config header file (for example include/configs/sunxi-common.h).
Moving this to Kconfig helps overcoming this issue. It's defined
as entry inside PHYLIB section.
After the implemention, moveconfig was run. The issues are:
- edb9315a - CONFIG_PHYLIB is not enabled. Entry is
deleted.
- ds414 - CONFIG_PHYLIB is in incompatible format:
{ 0x1, 0x0 }. This entry is also deleted.
- devkit3250 - The PHY_ADDR is in hex format (0x1F).
Manually CONFIG_PHY_ADDR=31 is added in
the defconfig.
After the changes the suspicious defconfigs passes building.
Signed-off-by: Stefan Mavrodiev <stefan@olimex.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
[jagan: rebased on master]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
The previous code tried to update the PHY parameters without waiting for
autonegotiation to complete. This caused wrong values to be written to
the EMAC in sun8i_adjust_link(). As a result, any commands that called
eth_start() before autonegotiation completed would find the network
nonfunctional. Fix this by using the correct function to start up the
PHY.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
In README.sunxi64 we tell the user how to optionally create
u-boot-sunxi-with-spl.bin by manually running cat. Instead, have the
build system create the file automatically just like it does for 32-bit
sunxi boards.
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
With CONFIG_DM_MMC the BananaPi does not detect SD cards.
The sunxi device trees use the cd-inverted property to indicate that
the card detect is inverted.
This property is documented in Linux kernel devicetree/bindings/mmc/mmc.txt
The property is not marked as deprecated.
A similar patch was posted by Tuomas but is in status "Changes Requested".
https://patchwork.ozlabs.org/patch/850377/
This patch is a stripped down version of his patch.
Suggested-by: Tuomas Tynkkynen <tuomas@tuxera.com>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
When the OTG node was added, its reg property for its address space was
missing. With commit f4f9896ac3 ("musb: sunxi: Use base address from
device tree"), the OTG controller's address is derived from the device
tree exclusively. The missing property results in U-boot crashing when
MUSB is initialized.
Fixes: b0bea66789 ("sunxi: Add USB and R_PIO nodes to sun8i-a83t.dtsi")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@openedev.com>
With the merge of the new u-boot.itb size check now the build for
pine64_plus_defconfig breaks, as this file gets too large:
=============
u-boot.itb exceeds file size limit:
limit: 516096 bytes
actual: 521852 bytes
excess: 5756 bytes
make: *** [u-boot.itb] Error 1
=============
One easily fixable reason is that we actually have two .dtbs in our FIT
image, one for the regular Pine64+ board, and one for the non-plus version.
The only difference U-Boot cares about is the 100Mbit Ethernet PHY used
on the non-plus version, however Ethernet isn't enabled in the non-plus
DT anyway.
So we could avoid the non-plus special handling, and remove that extra
.dtb from the FIT image, which saves a few KBs and brings us back below the
limit. The Pine64 would boot with a Pine64+ .dtb, and would fail to
enable Ethernet. Given that it didn't work in the first place, this is not
a regression.
Once we switch to a non-MMC environment, we can bring this back, then
with a proper .dtb and hopefully working Ethernet.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
This SUNXI variant SPL SPI code doesn't use either SPI or
SPL_FLASG subsystems due to size constraints and also placing
this code in drivers/mtd/spi will unnecessary build SPI_FLASH
code(if defined) which never required, hence moved to arch area.
And also renamed the file according to kconfig which resembles
proper name.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
set_mode, set_seed functions has separate function pointers
in dm_spi_ops, so use them in relevent one instead of
calling from claim_bus.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Boards adp-ae3xx_defconfig, nx25-ae250_defconfig
already enabled DM_SPI, so non-dm code make no use
of it hence droped.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Inform the EFI subsystem that the framebuffer memory is reserved.
Without the patch the AllocatePool boot service allocates memory from the
framebuffer which will will be overwritten by screen output.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Support special rendition code 0 - reset attributes.
Support special rendition code 1 - increased intensity (bold).
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Use constants to refer to colors.
Adjust initialization of foreground and background color to avoid
setting reserved bits.
Consistently u32 instead of unsigned for color bit mask.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
In 16 bit mode we have to copy two bytes per pixels repeatedly and not
four. Otherwise we will see a striped pattern.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Get RGB sequence in pixels right (swap blue and red).
Do not set reserved bits.
qemu-system-i386 -display sdl -vga virtio and
qemu-system-i386 -display sdl -vga cirrus
now display the similar colors (highlighting still missing) as
qemu-system-i386 -nographic
Testing is possible via
setenv efi_selftest test output
bootefi selftest
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-03-06 10:00:32 +01:00
954 changed files with 26525 additions and 7436 deletions
* Copyright (C) 2016, STMicroelectronics - All Rights Reserved
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _STM32_GPT_H
#define _STM32_GPT_H
#include<asm/arch/stm32.h>
structgpt_regs{
u32cr1;
u32cr2;
u32smcr;
u32dier;
u32sr;
u32egr;
u32ccmr1;
u32ccmr2;
u32ccer;
u32cnt;
u32psc;
u32arr;
u32reserved;
u32ccr1;
u32ccr2;
u32ccr3;
u32ccr4;
u32reserved1;
u32dcr;
u32dmar;
u32tim2_5_or;
};
structgpt_regs*constgpt1_regs_ptr=
(structgpt_regs*)TIM2_BASE;
/* Timer control1 register */
#define GPT_CR1_CEN BIT(0)
#define GPT_MODE_AUTO_RELOAD BIT(7)
/* Auto reload register for free running config */
#define GPT_FREE_RUNNING 0xFFFFFFFF
/* Timer, HZ specific defines */
#define CONFIG_STM32_HZ 1000
/* Timer Event Generation registers */
#define TIM_EGR_UG BIT(0)
#endif
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Block a user
Blocking a user prevents them from interacting with repositories, such as opening or commenting on pull requests or issues. Learn more about blocking a user.
