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184 Commits

Author SHA1 Message Date
Tom Rini
ec1754f091 Prepare v2018.05-rc3
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-01 09:09:31 -04:00
Tom Rini
b25f8e2112 Merge git://git.denx.de/u-boot-imx 2018-04-30 07:14:05 -04:00
Tom Rini
abeb9d7897 Merge git://git.denx.de/u-boot-sunxi 2018-04-30 06:52:32 -04:00
Alex Kiernan
8c84287a0f tools: mkimage: Check for datafile when type is script
If generating a script image and no datafile has been passed in, mkimage
dies with SIGSEGV:

  #0  __strchr_sse2 () at ../sysdeps/x86_64/multiarch/../strchr.S:32
  #1  0x0000000000403818 in main
      at tools/mkimage.c:503

Add explicit test for datafile to fix this.

Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
2018-04-28 18:32:25 -04:00
Alexander Dahl
c3b115f4b7 tools: mkenvimage: Fix possible segfault on stdin input
The size of 'filebuf' was not increased as more and more bytes are read
from stdin, but 'filebuf' was always reallocated to the same fix size.
This works as long as only less bytes than the initial buffer size come
in, for more input this will segfault. (It actually does, I tested
that.) So for each loop cycle the buffer size has to be increased by the
number of bytes we want to read.

Signed-off-by: Alexander Dahl <ada@thorsis.com>
2018-04-28 18:32:24 -04:00
Alexander Dahl
3559028cb2 tools: mkenvimage: Fix read() stdin error handling
On success read() returns the number of bytes read or zero for EOF. On
error -1 is returned and errno is set, so the right way to test if read
had failed is to test the return value instead of errno.

Signed-off-by: Alexander Dahl <ada@thorsis.com>
2018-04-28 18:32:24 -04:00
Patrice Chotard
8dc4e1fbf4 serial: serial_stm32: Rename status register flags
Uart status register is named USART_ISR on STM32F7, STM32H7
and STM32MP1 SoCs family, but USART_SR only on STM32F4 SoCs.

Use USART_ISR_ prefix instead of USART_SR_ .

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-04-28 18:32:24 -04:00
Patrice Chotard
7b3b74d321 serial: serial_stm32: Enable overrun
Enable uart overrun feature which allows to benefits of uart
FIFO usage.

Previously overrun management was disabled, this has to effect
to bypassed the uart FIFO usage even if FIFO was enabled.
In particular configuration, for example when video console is
enabled, copy/pasting a long command line in console results in
corruption. This is due to the fact that a lot of time is consumed
in flushing the cache during frame buffer update, so uart chars are
not read fast enough.

By using uart FIFO and managing overrun, long command line can by
copy/paste in console without being corrupted.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-04-28 18:32:24 -04:00
Alex Kiernan
ab9e12f651 spl: disk: usb: Add dependencies to sprintf/strto*
If SPL serial support is disabled nothing brings in sprintf, snprintf
or simple_strtoul:

  env/built-in.o: In function `regex_callback':
  env/attr.c:128: undefined reference to `sprintf'
  disk/built-in.o: In function `blk_get_device_by_str':
  disk/part.c:386: undefined reference to `simple_strtoul'
  disk/part.c:395: undefined reference to `simple_strtoul'
  disk/built-in.o: In function `blk_get_device_part_str':
  disk/part.c:522: undefined reference to `simple_strtoul'
  disk/built-in.o: In function `part_set_generic_name':
  disk/part.c:704: undefined reference to `sprintf'
  drivers/built-in.o: In function `init_peripheral_ep':
  drivers/usb/musb-new/musb_gadget.c:1826: undefined reference to `sprintf'
  drivers/built-in.o: In function `musb_core_init':
  drivers/usb/musb-new/musb_core.c:1451: undefined reference to `snprintf'

Add those dependencies here.

Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
2018-04-28 18:32:24 -04:00
Alex Kiernan
e21c03be6d Consolidate __assert_failed into one implementation
We had two implementations of __assert_failed which were almost identical,
combine them into one.

Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
2018-04-28 18:32:23 -04:00
Alex Kiernan
4f1eed7527 spl: Disable printf if not required
Now we have a guard for printf, disable it in the build if it's not
selected.

Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
2018-04-28 18:32:23 -04:00
Alex Kiernan
14ad44ab46 spl: Split sprintf, strto* from SPL serial in Kconfig
When SPL serial is disabled, callers who need sprintf or strtoul fail
because their inclusion is guarded by CONFIG_SPL_SERIAL_SUPPORT/
CONFIG_TPL_SERIAL_SUPPORT.

Split printf, sprintf and strto into their own entries and then select
all of them if SERIAL_SUPPORT is enabled to match the current behaviour.

Include panic.o unconditionally as it can be called from anywhere which
uses BUG_ON().

Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
2018-04-28 18:32:23 -04:00
Alex Kiernan
d4bb3b3762 spl: ti: Avoid serial calls when serial support is disabled
If CONFIG_SPL_SERIAL_SUPPORT is not set, then the build will fail:

board/ti/am335x/built-in.o: In function `spl_start_uboot':
board/ti/am335x/board.c:247: undefined reference to `serial_tstc'
board/ti/am335x/board.c:247: undefined reference to `serial_getc'

Avoid the calls to the serial functions in that case.

Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
2018-04-28 18:32:23 -04:00
Alex Kiernan
3bac19ce23 spl: Add dependency on serial to Ymodem
Building with Ymodem support requires serial in SPL/TPL, add that
dependency here.

Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
2018-04-28 18:32:23 -04:00
Alex Kiernan
eedecb0fe8 Cleanup CONFIG_SPL_SERIAL_SUPPORT migration
CONFIG_SPL_SERIAL_SUPPORT had already been migrated to Kconfig, but
existed in some include files; fix those up here.

Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
2018-04-28 18:32:22 -04:00
Alex Kiernan
117a0e02be spl: ti: Avoid preloader_console_init if !CONFIG_SPL_SERIAL_SUPPORT
If CONFIG_SPL_SERIAL_SUPPORT is disabled then the build fails because
serial_init is undefined. Guard preloader_console_init() appropriately
to fix this.

Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
2018-04-28 18:32:22 -04:00
Masahiro Yamada
30d313688f test: dm: regmap: fix license header
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-28 18:32:22 -04:00
Andre Przywara
7842b6a91e arm: move SYS_ARCH_TIMER to KConfig
SYS_ARCH_TIMER guards the usage of the ARM Generic Timer (aka arch
timer) in U-Boot.
At the moment it is mandatory for ARMv8 and used by a few ARMv7 boards.
Add a proper Kconfig symbol to express this dependency properly,
allowing certain board configuration to later disable arch timer in case
there are any problems with it.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[tuomas: rebase + fix conflicts and resync with moveconfig & use select]
Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
2018-04-28 18:30:43 -04:00
Tuomas Tynkkynen
1a164ad304 ARM: qemu-arm: Dynamically determine timer frequency
After commit 46fc679ede ("arm: timer: get frequency for arch timer
armv7 in cp15 cntfrq") the ARM architected timer driver knows how to
determine the timer frequency at runtime by reading the CNTFRQ register,
so we don't need to hardcode the timer frequency anymore.

Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
2018-04-28 18:30:43 -04:00
Tom Rini
37dc72f5a5 configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-28 10:48:10 -04:00
Masahiro Yamada
c4f668320a distro: select CMD_ENV_EXISTS
'env exists' is used for scripting in include/config_distro_bootcmd.h
This command is available only when CONFIG_CMD_ENV_EXISTS is enabled.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
2018-04-28 10:42:35 -04:00
Masahiro Yamada
7325f6cfdc distro: use imply to enable DISTRO_DEFAULTS as SoC default
The default of DISTRO_DEFAULTS is messy.  Using the 'imply' keyword
is equivalent and cleaner.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-28 10:42:35 -04:00
Heinrich Schuchardt
b60cfb6a01 powerpc: fix typo in kgdb.c
%s/alingment/alignment/

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2018-04-28 10:42:35 -04:00
Eugeniu Rosca
39883af3f0 lib/rsa: Kconfig: Remove superfluous 'depends on RSA'
RSA_SOFTWARE_EXP and RSA_FREESCALE_EXP are wrapped inside:

if RSA
	...
endif

So, remove the redundant "depends on RSA" from their depends expression.
In addition, move SPL_RSA into the same "if RSA ... endif" block, since
its only direct dependeny is CONFIG_RSA. This tidies up and simplifies
reading of lib/rsa/Kconfig.

No functional change intended.

Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-04-28 10:42:35 -04:00
Alex Kiernan
002c3234e6 Migrate IMAGE_FORMAT_LEGACY to Kconfig
This converts IMAGE_FORMAT_LEGACY to Kconfig

Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-04-28 10:42:35 -04:00
Heinrich Schuchardt
83a1f933d1 cmd: CONFIG_CMD_LOG select CONFIG_LOG
CONFIG_CMD_LOG without CONFIG_LOG leads to a build error:
‘gd_t {aka volatile struct global_data}’ has no member named
‘default_log_level’

So CMD_LOG should select LOG.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-04-28 10:42:35 -04:00
Heinrich Schuchardt
9adc78d278 log: CONFIG_LOG should select CONFIG_DM
Compling with CONFIG_LOG and without CONFIG_DM results in
common/log.c:47: undefined reference to `uclass_get_name'

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-04-28 10:42:35 -04:00
Masahiro Yamada
1eb2e71edd kbuild: use -fmacro-prefix-map to make __FILE__ a relative path
The __FILE__ macro is used everywhere in U-Boot to locate the file
printing the log message, such as WARN_ON(), etc.  If U-Boot is
built out of tree, this can be a long absolute path.

This is because Kbuild runs in the objtree instead of the srctree,
then __FILE__ is expanded to a file path prefixed with $(srctree)/.

A brand-new option from GCC, -fmacro-prefix-map, solves this problem.
If your compiler supports it, __FILE__ is the relative path from the
srctree regardless of O= option.  This provides more readable log,
more reproducible builds, and smaller image size.

[ Linux commit: a73619a845d5625079cc1b3b820f44c899618388 ]

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-04-28 10:42:35 -04:00
Tuomas Tynkkynen
fac379e1ea serial: Migrate CONFIG_FSL_LINFLEXUART to Kconfig
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
2018-04-28 10:42:35 -04:00
Tuomas Tynkkynen
76dd0f2c3d ARM: s32v234evb: Set CONFIG_DM & CONFIG_DM_SERIAL in Kconfig
These symbols are declared in Kconfig, so it's wrong to set them in
header files.

Note that this is not size-neutral - some 'default y' options will now
get turned on by Kconfig, such as CONFIG_CMD_DM=y and CONFIG_DM_STDIO=y.

Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
2018-04-28 10:42:05 -04:00
Tom Rini
ec5c4a8fd6 configs: Drop CONFIG_NET_MULTI
We have not had CONFIG_NET_MULTI be meaningful for quite some time, drop
the last remnants.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-27 14:54:49 -04:00
Tom Rini
3b6407b8ed clang: Update documentation
As of clang-5.0, things have changed a bit.  First, we cannot
automatically guess -target values as if we do not pass one with CC then
cc-option will fail.  Second, to disable movt/movw relocations the
argument has become -mno-movt.

Related to the target part, we cannot use arm-none-eabi as that ends up
being too generic of an ARM target for things like say rpi_3_32b to
work.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-27 14:54:49 -04:00
Tom Rini
4760fe26c7 Makefile: Update clang warning disables from Linux
Re-sync the logic about which clang warnings to disable from v4.17-rc1.
Note that we don't disable all of the same ones as for now we haven't
run into any cases of warnings from clang in code from upstream Linux.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-27 14:54:48 -04:00
Tom Rini
d024236e5a Remove unnecessary instances of DECLARE_GLOBAL_DATA_PTR
We have a large number of places where while we historically referenced
gd in the code we no longer do, as well as cases where the code added
that line "just in case" during development and never dropped it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-27 14:54:48 -04:00
Adam Ford
f1b1f77060 Convert CONFIG_SPI to Kconfig
This converts the following to Kconfig:
   CONFIG_SPI

This partly involves updating code that assumes that CONFIG_SPI implies
things that are specific to the MPC8xx SPI driver.  For now, just update
the CONFIG tests.  This also involves reworking the default for
CONFIG_SYS_DEF_EEPROM_ADDR so that we don't set it when we cannot make a
reasonable default, as it does not cause any compile failures.

Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-27 14:54:11 -04:00
Mans Rullgard
07a8f79ee8 ARM: mxs: support full SPL framework
This allows using the full SPL framework on mxs devices.  In this
mode, the u-boot.sb image loaded by the boot ROM contains only the
SPL which then loads U-Boot proper or a kernel in falcon mode.

Signed-off-by: Mans Rullgard <mans@mansr.com>
2018-04-27 09:32:54 +02:00
Mans Rullgard
33ea119382 ARM: mxs: move spl data
With full SPL enabled, the loaded image overwrites the mxs_spl_data
location.  Moving it a slightly lower address fixes this.

Signed-off-by: Mans Rullgard <mans@mansr.com>
2018-04-27 09:32:54 +02:00
Mans Rullgard
68f835557c ARM: spl: include arm/thumb glue sections
When building in Thumb mode, the linker might generate mode switching
stubs in .glue sections.  Include these in the final link.

Signed-off-by: Mans Rullgard <mans@mansr.com>
2018-04-27 09:32:54 +02:00
Mans Rullgard
da372af6e4 ARM: arm926ejs: fix lowlevel_init call
The code attempts to preserve the value of LR by storing it in R12/IP
across the lowevel_init() call.  However, this register is not saved
by the callee.  Use a register that guaranteed to be preserved instead.

Signed-off-by: Mans Rullgard <mans@mansr.com>
2018-04-27 09:32:54 +02:00
Mans Rullgard
9482aeda66 ARM: mxs: make lowlevel_init() weak
With the full SPL framework enabled, lowlevel_init() is required.
Make the empty stub weak so boards can override it.

Signed-off-by: Mans Rullgard <mans@mansr.com>
2018-04-27 09:32:54 +02:00
Tom Rini
ec37f05ec0 Merge git://git.denx.de/u-boot-usb 2018-04-26 22:09:11 -04:00
Tom Rini
10cd229ec0 Merge git://git.denx.de/u-boot-socfpga 2018-04-26 22:09:03 -04:00
Tom Rini
641bce2635 Merge git://git.denx.de/u-boot-sh 2018-04-26 22:08:58 -04:00
Tien Fong Chee
4ae87a83a6 arm: socfpga: Fix with the correct polling on bit is set
Commit 2baa997240 ("arm: socfpga: Add FPGA driver support for Arria 10")
Polling on wrong cleared bit. Fix with correct polling on bit is set.

Fixes: 2baa997240 ("arm: socfpga: Add FPGA driver support for Arria 10")

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2018-04-27 01:04:08 +02:00
Christophe Kerello
d57ed4d9f2 usb: gadget: composite: fix NULL pointer when a non standard request is received
In case usb configuration is unknown (cdev->config == NULL), non standard
request should not be processed.
Remove also the cdev->config check below which will never happen.

This issue was seen using ums feature.

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-04-26 15:15:07 +02:00
Neil Armstrong
003659bda9 usb: host: dwc3: fix phys init
When no PHYs are declared in the dwc3 node, the phy init fails.
This patch checks if the "phys" property is presend and reports
the error returned by dev_count_phandle_with_args().

This patchs also fixes the styles issues added in last commit.

This patch should fix the DWC3 support on the UniPhier SoC family.

Fixes: 7c839ea70c ("usb: host: dwc3: Add support for multiple PHYs")
Reported-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-04-26 14:03:13 +02:00
Marek Vasut
fe537802f1 ARM: rmobile: Fix PMIC address on E2 Silk
The PMIC is at 0x5a, fix the address.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-04-26 13:56:57 +02:00
Marek Vasut
bb6d2ff2ac ARM: rmobile: Update E2 Alt
The E2 Alt port was broken since some time. This patch updates
the E2 Alt port to use modern frameworks, DM, DT probing, SPL
for the preloading and puts it on par with the M2 Porter board.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-04-26 13:54:39 +02:00
Marek Vasut
49aefe300a ARM: rmobile: Update M2-N Gose
The M2-N Gose port was broken since some time. This patch updates
the M2-N Gose port to use modern frameworks, DM, DT probing, SPL
for the preloading and puts it on par with the M2 Porter board.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-04-26 13:54:39 +02:00
Marek Vasut
e6027e6f45 ARM: rmobile: Update H2 Lager
The H2 Lager port was broken since some time. This patch updates
the H2 Lager port to use modern frameworks, DM, DT probing, SPL
for the preloading and puts it on par with the M2 Porter board.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-04-26 13:54:39 +02:00
Marek Vasut
1d0cb86eb9 ARM: rmobile: Enable HS200 support on M3N Salvator-X
Enable the HS200 support on M3N Salvator-X .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-04-26 13:54:39 +02:00
Tom Rini
d2a1f120cf Merge git://git.denx.de/u-boot-rockchip 2018-04-26 07:21:41 -04:00
Sébastien Szymanski
ea77217828 imx6ul: opos6ul: in Serial Downloader boot mode use ymodem
When booting in Serial Downloader mode load the U-Boot image using
ymodem.

Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
2018-04-26 09:34:16 +02:00
Sébastien Szymanski
30754ef77c imx6ul: opos6ul: add SPL_DM support
Since commit commit 152038ea18 ("i.MX6UL: icore: Add SPL_OF_CONTROL
support") the OPOS6UL board doesn't boot anymore. Adding SPL_DM support
makes the board boot again.

Fixes: commit 152038ea18 ("i.MX6UL: icore: Add SPL_OF_CONTROL support")
Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
2018-04-26 09:34:00 +02:00
Bryan O'Donoghue
e426e19353 warp7: defconfig: Fix CAAM on boot with tip-of-tree
Booting the following image with tip-of-tree we get a CAAM DECO error (and
subsequent crash due to a kernel bug in 4.1).

http://freescale.github.io/#download -> BoardsWaRPboard community - WaRP -
Wearable Reference PlatformFSL Community BSP 2.3fsl-image-multimediawayland

Image: fsl-image-multimedia-imx7s-warp-20180323-90.rootfs.sdcard

Error:
caam 30900000.caam: Entropy delay = 3200
caam 30900000.caam: failed to acquire DECO 0
<snip>
caam 30900000.caam: failed to acquire DECO 0
caam 30900000.caam: Entropy delay = 12400
caam 30900000.caam: failed to acquire DECO 0
caam 30900000.caam: failed to instantiate RNG
------------[ cut here ]------------
WARNING: CPU: 0 PID: 1 at
/home/jenkins/workspace/fsl-community-bsp-pyro_xwayland_2/build/tmp/work-shared/imx7s-warp/kernel-source/mm/vmalloc.c:1465
caam_remove+0x6)
Trying to vfree() nonexistent vm area (88047000)
Modules linked in:
CPU: 0 PID: 1 Comm: swapper/0 Not tainted
4.1.36-4.1-1.0.x-imx-warp7+ga543d1b #1
Hardware name: Freescale i.MX7 Dual (Device Tree)
[<80015d54>] (unwind_backtrace) from [<80012688>] (show_stack+0x10/0x14)
[<80012688>] (show_stack) from [<8076e810>] (dump_stack+0x78/0x8c)
[<8076e810>] (dump_stack) from [<800346a0>]
(warn_slowpath_common+0x80/0xb0)
[<800346a0>] (warn_slowpath_common) from [<80034700>]
(warn_slowpath_fmt+0x30/0x40)
[<80034700>] (warn_slowpath_fmt) from [<8054c278>] (caam_remove+0x6c/0x3f4)
[<8054c278>] (caam_remove) from [<8054ce74>] (caam_probe+0x874/0xfa8)
[<8054ce74>] (caam_probe) from [<80382a7c>] (platform_drv_probe+0x48/0xa4)
[<80382a7c>] (platform_drv_probe) from [<80381328>]
(driver_probe_device+0x174/0x2a8)
[<80381328>] (driver_probe_device) from [<8038152c>]
(__driver_attach+0x8c/0x90)
[<8038152c>] (__driver_attach) from [<8037f9d4>]
(bus_for_each_dev+0x68/0x9c)
[<8037f9d4>] (bus_for_each_dev) from [<80380a68>]
(bus_add_driver+0xf4/0x1e8)
[<80380a68>] (bus_add_driver) from [<80381b38>] (driver_register+0x78/0xf4)
[<80381b38>] (driver_register) from [<80009738>]
(do_one_initcall+0x8c/0x1d0)
[<80009738>] (do_one_initcall) from [<80a66dac>]
(kernel_init_freeable+0x140/0x1d0)
[<80a66dac>] (kernel_init_freeable) from [<8076aa38>]
(kernel_init+0x8/0xe8)
[<8076aa38>] (kernel_init) from [<8000f468>] (ret_from_fork+0x14/0x2c)
---[ end trace d5f941204ed8cb28 ]---
caam: probe of 30900000.caam failed with error -11
Unable to handle kernel NULL pointer dereference at virtual address
00000004
pgd = 80004000
[00000004] *pgd=00000000
Internal error: Oops: 805 [#1] PREEMPT SMP ARM
<snip>
[<8055cdf8>] (caam_sm_startup) from [<80aa83c8>] (caam_sm_init+0x50/0x58)
[<80aa83c8>] (caam_sm_init) from [<80009738>] (do_one_initcall+0x8c/0x1d0)
[<80009738>] (do_one_initcall) from [<80a66dac>]
(kernel_init_freeable+0x140/0x1d0)
[<80a66dac>] (kernel_init_freeable) from [<8076aa38>]
(kernel_init+0x8/0xe8)
[<8076aa38>] (kernel_init) from [<8000f468>] (ret_from_fork+0x14/0x2c)
Code: e59d300c e2832010 e5843008 e5834068 (e58a2004)
---[ end trace d5f941204ed8cb29 ]---
Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b

Fix: Enable the CAAM correctly by setting CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
in the upstream defconfig.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Tested-by: Breno Lima <breno.lima@nxp.com>
2018-04-26 09:32:25 +02:00
Bryan O'Donoghue
8273209bd9 warp7: secure_defconfig: Remove secure_defconfig
This patch removes warp7_secure_defconfig. A previous patch set
CONFIG_ARMV7_BOOT_SEC_DEFAULT=y on the unsecure WaRP7 config. Fabio asked
if I could confirm that the NXP and upstream kernels will boot on the WaRP7
with CONFIG_ARMV7_BOOT_SEC_DEFAULT=y. I can confirm that this is the case,
so there's no need to support the secure defconfig - drop it now.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Suggested-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-04-26 09:31:20 +02:00
Lukasz Majewski
948239ea16 dts: dm: fec: imx53: Provide proper compatible string for imx53 fec driver
After this change the DM FEC ETH driver can be also reused on some imx53
devices.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2018-04-26 09:28:49 +02:00
Lukasz Majewski
178d4f0099 eth: dm: fec: Change FEC PHY mask setting from CONFIG_PHYLIB to CONFIG_FEC_MXC_PHYADDR
Without this commit we do have an explicit dependency on CONFIG_PHYLIB
when one wants to set PHY ADDR on a iMX board (FEC + driver model).

This shall be changed to CONFIG_FEC_MXC_PHYADDR, as only when we do have
it set, we shall mask out other devices.

As a side effect, when CONFIG_FEC_MXC_PHYADDR is not set, we scan PHY bus
for connected PHY devices.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2018-04-26 09:27:22 +02:00
Fabio Estevam
f3c326287e Revert "imximage: Remove failure when no IVT offset is found"
This reverts commit b5b0e4e351.

Commit f916757300 ("imx: Create distinct pre-processed mkimage
config files") provided a proper fix for the parallel mkimage
config files build failure, so the original workaround can be
safely reverted now.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2018-04-26 09:00:44 +02:00
Fabio Estevam
feb14c6348 mx7dsabresd: Remove the mx7dsabresd_secure_defconfig target
mx7dsabresd_secure_defconfig was introduced to allow booting NXP kernel
that has CAAM support and needs to boot in secure mode.

Instead of keeping two different config targets for the same board,
remove mx7dsabresd_secure_defconfig and select
CONFIG_ARMV7_BOOT_SEC_DEFAULT inside mx7dsabresd_defconfig so that
this target could be used to boot both mainline and the vendor kernel.

This makes maintenance task easier and avoid potentially confusion
for the end user.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
2018-04-26 08:57:52 +02:00
Mark Jonas
5ebf9ad96c arm,imx6: fix PAD_CTL_SPEED_LOW constant
For most i.MX6 processors the PAD_CTL_SPEED_LOW constant is the same.
Only the i.MX6 SoloLite is an exemption. So far the code did not
consider that. Additionally, for a few i.MX6 processors the code used
the wrong value for the constant.

This patch fixes the PAD_CTL_SPEED_LOW constant for:
 - i.MX6 Solo [1]
 - i.MX6 DualLite [1]
 - i.MX6 Dual [2]
 - i.MX6 Quad [2]
 - i.MX6 DualPlus [3]
 - i.MX6 QuadPlus [3]

Before, it was already correct for:
 - i.MX6 SoloLite [4]
 - i.MX6 SoloX [5]
 - i.MX6 UtraLite [6]
 - i.MX6 ULL [7]

[1] https://www.nxp.com/docs/en/reference-manual/IMX6SDLRM.pdf
[2] https://www.nxp.com/docs/en/reference-manual/IMX6DQRM.pdf
[3] https://www.nxp.com/docs/en/reference-manual/iMX6DQPRM.pdf
[4] https://www.nxp.com/docs/en/reference-manual/IMX6SLRM.pdf
[5] https://www.nxp.com/docs/en/reference-manual/IMX6SXRM.pdf
[6] https://www.nxp.com/docs/en/reference-manual/IMX6ULRM.pdf
[7] https://www.nxp.com/docs/en/reference-manual/IMX6ULLRM.pdf

Signed-off-by: Mark Jonas <mark.jonas@de.bosch.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2018-04-26 08:55:42 +02:00
Bryan O'Donoghue
bb96a08d5b warp7: Add support for automated secure boot.scr verification
This patch adds support for verifying a signed boot.scr. With this in place
it's possible for run-time Linux to update boot.scr to set different
variables such as switching between different boot partitions, pointing to
different kernels etc and for u-boot to verify these changes via the HAB
prior to executing the commands contained in boot.scr.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Tested-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-04-26 08:54:18 +02:00
Bryan O'Donoghue
baea5ecd26 warp7: defconfig: Enable CMD_SETEXPR
setexpr allows us to do arithmetic for env variables - something that is
both useful and required when doing HAB authentication without hard-coding
HAB load addresses.

This patch enables CMD_SETEXPR for the WaRP7 defconfig.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Tested-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-04-26 08:54:02 +02:00
Bryan O'Donoghue
d9cb9aec74 warp7: hab: Set environment variable indicating IVT offset
This patch introduces the environment variable ivt_offset. When we define a
load address for Linux or DTB or any file the IVT associated with that file
is prepended. We extract the actual load addresses from u-boot.cfg and feed
these values into the code-signing process - hence we want u-boot to have
the real load addresses exported in uboot.cfg.

ivt_offset represents the addition or subtraction from the load address
that must happen to find an IVT header.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Tested-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-04-26 08:54:02 +02:00
Bryan O'Donoghue
c0df0caeb8 warp7: add warp7_auth_or_fail
Doing secure boot on the WaRP7 using a common image format and the same
variable to represent the base address for each call means we can reduce
down the command to a single environment command.

This patch adds warp7_auth_or_fail as a wrapper around
"hab_auth_img_or_fail ${hab_ivt_addr} ${filesize} 0".

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Tested-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-04-26 08:53:42 +02:00
Bryan O'Donoghue
e4514051fc warp7: Define the name of a signed boot-script file
We need to know the name of a signed boot-script, its better to have a
separate variable for this then to simply append some fixed string to an
existing image name.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Tested-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-04-26 08:53:22 +02:00
Bryan O'Donoghue
2948089815 warp7: select uuid partition based on rootpart
Assigning the UUID discovery path to a tweakable environment variable means
that later steps in the boot process - particularly a boot script can
change the target root partition of a particular Linux boot.

Retargeting the rootfs is an important feature when doing ping/pong
upgrades allowing a boot script to select ping or pong as necessary without
reprogramming the bootloader.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Tested-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-04-26 08:53:22 +02:00
Bryan O'Donoghue
95b649f27d warp7: Add Kconfig WARP7_ROOT_PART
Adding CONFIG_WARP7_ROOT_PART allows a defconfig to specify which partition
is use as the root partition on WaRP7, this is a desirable change in order
to support a different partitioning schemes. The default is the current
partition #2.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Tested-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-04-26 08:53:22 +02:00
Bryan O'Donoghue
56eca404e1 warp7: Make CONFIG_SYS_FDT_ADDR a define
In order to sign images with the IMX code-signing-tool (CST) we need to
know the load address of a given image. The best way to derive this load
address is to make it into a define - so that u-boot.cfg contains the
address - which we can then parse when generating the IMX CST headers.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org>
Tested-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-04-26 08:53:22 +02:00
Bryan O'Donoghue
42fcabdb26 warp7: defconfig: Enable CONFIG_BOOTM_TEE
This patch enables CONFIG_BOOTM_TEE. Once enabled its possible to
chain-load Linux through OPTEE.

Loading kernel to 0x80800000
=> run loadimage

Load FDT to 0x83000000
=> run loadfdt

Load OPTEE to 0x84000000
=> fatload mmc 0:5 0x84000000 /lib/firmware/uTee.optee

Then chain-load to the kernel via OPTEE

=> bootm 0x84000000 - 0x83000000

   Image Name:
   Image Type:   ARM Trusted Execution Environment Kernel Image (uncompressed)
   Data Size:    249844 Bytes = 244 KiB
   Load Address: 9dffffe4
   Entry Point:  9e000000
   Verifying Checksum ... OK
   Loading Kernel Image ... OK

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Tested-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-04-26 08:53:22 +02:00
Bryan O'Donoghue
9fb2c1faa1 warp7: defconfig: Enable CONFIG_SECURE_BOOT
Various function associated with booting the WaRP7 in High Assurance Boot
(HAB) mode are enabled by switching on CONFIG_SECURE_BOOT.

This patch enables CONFIG_SECURE_BOOT for the WaRP7 defconfig.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Tested-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-04-26 08:53:22 +02:00
Bryan O'Donoghue
4bcbfcf458 warp7: Specify CONFIG_OPTEE_LOAD_ADDR
In order to sign images with the IMX code-signing-tool (CST) we need to
know the load address of a given image. The best way to derive this load
address is to make it into a define - so that u-boot.cfg contains the
address - which we can then parse when generating the IMX CST headers.

This patch makes the OPTEE_LOAD_ADDR available via u-boot.cfg for further
parsing by external tools.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org>
Tested-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-04-26 08:52:51 +02:00
Bryan O'Donoghue
fbbf44af31 warp7: Print out the OPTEE DRAM region
Right now a region of 0x300000 bytes is allocated at the end of DRAM for
the purposes of loading an OPTEE firmware inside of it. This patch adds the
printout of the relevant address ranges.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Tested-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-04-26 08:52:51 +02:00
Bryan O'Donoghue
7175ef4a71 warp7: Allocate specific region of memory to OPTEE
Subtracts CONFIG_OPTEE_TZDRAM_SIZE from the available DRAM size.

On WaRP7 we simply define the OPTEE region as from the maximum DRAM address
minus CONFIG_OPTEE_TZDRAM_SIZE bytes.

Note the OPTEE boot process will itself subtract the DRAM region it lives
in from the memory map passed to Linux.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Tested-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-04-26 08:52:51 +02:00
Bryan O'Donoghue
c727bba74a warp7: defconfig: Enable OPTEE for WaRP7
Requires setting CONFIG_OPTEE=y and setting an OPTEE TrustZone DRAM base in
include/configs/warp7.h.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Tested-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-04-26 08:52:51 +02:00
Bryan O'Donoghue
a2accd843b warp7: hab: Set environment variable indicating HAB enable
This patch adds an environment variable called "hab_enabled" which gets set
to a boolean status indicating whether HAB is enabled or not.

Subsequent patches can use this environment variable to determine if its
necessary to run a given binary through the hab_auth_img console command.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Tested-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-04-26 08:52:51 +02:00
Bryan O'Donoghue
9c260e862f warp7: hab: Add a CSF location definition
In order to correctly produce an image with a IVT/DCD header we need to
define a CSF in imximage.cfg. We just use the mx7 default here.

All we have to do with this option switched on is "make u-boot.imx" and we
then will get

- u-boot.imx
- u-boot.imx.log

The log file is really important because it gives the addresses for the HAB
that we will require to sign the u-boot image using the CST. Since the
addresses can change this logfile is a critical output.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Tested-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-04-26 08:52:51 +02:00
Bryan O'Donoghue
69f0695067 imximage: Specify default IVT offset in IMX image
This patch adds BOOTROM_IVT_HDR_OFFSET at 0xC00. The BootROM expects to
find the IVT header at a particular offset in an i.MX image.

Defining the expected offset of the IVT header in the first-stage BootROM
image format is of use of later stage authentication routines where those
routines continue to follow the first-stage authentication layout.

This patch defines the first stage offset which later patch make use of.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Cc: Utkarsh Gupta <utkarsh.gupta@nxp.com>
Cc: Breno Lima <breno.lima@nxp.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Tested-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-04-26 08:52:51 +02:00
Bryan O'Donoghue
af1b492dfa tools/imximage: Fix fruity lack of 0x prefix in DCD Blocks
commit 8519c9c98a ("tools/imximage: use 0x prefix in HAB Blocks line")
adds an 0x prefix to each HAB Block number to make it easier for host tools
to process the HAB Block output, however it neglects to apply the same
prefix to the DCD Blocks directive. You need the DCD Blocks directive if
you are making a u-boot recovery image which the BootROM will accept via
the USB upload utility.

This disparity results in a fruity output like this with HAB Blocks
prefixed but DCD Blocks not prefixed - which is pretty inconsistent.

This patch fixes the difference assuming the original commit was a
legitimate change.

Old:
Image Type:   Freescale IMX Boot Image
Image Ver:    2 (i.MX53/6/7 compatible)
Mode:         DCD
Data Size:    430080 Bytes = 420.00 KiB = 0.41 MiB
Load Address: 877ff420
Entry Point:  87800000
HAB Blocks:   0x877ff400 0x00000000 0x00066c00
DCD Blocks:   00910000 0000002c 000001d4

New:
Image Type:   Freescale IMX Boot Image
Image Ver:    2 (i.MX53/6/7 compatible)
Mode:         DCD
Data Size:    430080 Bytes = 420.00 KiB = 0.41 MiB
Load Address: 877ff420
Entry Point:  87800000
HAB Blocks:   0x877ff400 0x00000000 0x00066c00
DCD Blocks:   0x00910000 0x0000002c 0x000001d4

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Cc: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Breno Lima <breno.lima@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-04-26 08:52:51 +02:00
Pierre-Jean TEXIER
0803bcf8a9 warp7: configs: enable CONFIG_CMD_FS_GENERIC
This enable generic file system commands (load, ls).

Signed-off-by: Pierre-Jean TEXIER <texier.pj2@gmail.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
2018-04-26 08:51:36 +02:00
Pierre-Jean TEXIER
206426aa0b warp7: include/configs: use generic fs commands in CONFIG_EXTRA_ENV_SETTINGS
use the generic filesystem command 'load' rather
than 'fatload' to avoid per-fs specific commands.

Signed-off-by: Pierre-Jean TEXIER <texier.pj2@gmail.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
2018-04-26 08:50:45 +02:00
Tom Rini
a61f9d1fbb Merge git://git.denx.de/u-boot-spi 2018-04-25 20:50:28 -04:00
Kever Yang
eb3d707e99 rockchip: defconfig: remove CONFIG_SYS_NS16550
We have enable NS16550 in Kconfig, do not need enable at defconfig

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-04-25 22:20:07 +02:00
Kever Yang
c3c0331db1 rockchip: enable SYS_NS16550 for all SoCs by default
All rockchip SoCs can use ns16550 driver, enable it for all
and set SYS_NS16550_MEM32 for all SoCs.

Version-changes: 2
- use imply instead of select

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-04-25 22:20:07 +02:00
Kever Yang
932b2c98eb Revert "rockchip: firefly: Add "usb start" to auto-start USB device"
This reverts commit a1903c18db.

It's really bad idea to add "usb start" in preboot, it will spend
a lot of time to scan usb bus, and most of people do not need this
feature.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-04-25 22:20:07 +02:00
Kever Yang
cb7116afe8 rockchip: rk322x: update MACRO for back-to-brom
The MACRO has been update after:
ee14d29 rockchip: back-to-bootrom: split BACK_TO_BOOTROM for TPL/SPL
We need to update the C code for it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-04-25 22:20:07 +02:00
Kever Yang
4749436da2 rockchip: rk322x: update TPL_TEXT_BASE
The boot0 hook including the 4-byte TAG which is at the beginning
of the TEXT_BASE, now we can use a aligned TEXT BASE.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-04-25 22:20:07 +02:00
Kever Yang
c877ef3ac1 rockchip: rv1108: add ofdata_to_platdata() method for driver
Parse of data in dedicated api instead of in probe().

The clk_set_rate() may be called before the clk driver is probed,
after core support set default clock.
This patch fix system abort issue since:
f4fcba5 clk: implement clk_set_defaults()

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-sytems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-sytems.com>
2018-04-25 22:20:07 +02:00
Kever Yang
d2e938d993 rockchip: rk3128: add ofdata_to_platdata() method for driver
Parse of data in dedicated api instead of in probe().

The clk_set_rate() may be called before the clk driver is probed,
after core support set default clock.
This patch fix system abort issue since:
f4fcba5 clk: implement clk_set_defaults()

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-sytems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-sytems.com>
2018-04-25 22:20:06 +02:00
Kever Yang
accaaea5cc rockchip: rk3036: add ofdata_to_platdata() method for driver
Parse of data in dedicated api instead of in probe().

The clk_set_rate() may be called before the clk driver is probed,
after core support set default clock.
This patch fix system abort issue since:
f4fcba5 clk: implement clk_set_defaults()

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-04-25 22:20:06 +02:00
Peter Robinson
239a25aef1 config: evb-rk3399: enable make uboot.itb
Similar to firefly 3399 enable the ability to create a FIT image
with combined arm-trusted-firmware.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-04-25 22:20:06 +02:00
Patrick Uiterwijk
ced3c10fd2 arm: rockchip: make_fit_atf: remove unneeded imports
These imports are entirely unused in the entire script.

Signed-off-by: Patrick Uiterwijk <patrick@puiterwijk.org>
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-04-25 22:20:06 +02:00
Kever Yang
fd9e0fe0e3 rockchip: rk3188: use DM timer instead of rk_timer
Disable rk_timer as SYS timer and use DM timer instead,
so that we can get a better timer framework, the rk_timer
is going to be clean after we conver to use DM timer or
ARM arch/generic timer.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-04-25 22:20:06 +02:00
Kever Yang
f9ef544786 rockchip: rk3188: add timer3 node
Add dts node for timer3.
Because of the rockchip timer can only KNOWN "dtd_rockchip_rk3368_timer"
with OF_PLATDATA enable, so we override its compatible to
"rockchip,rk3368-timer".

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-04-25 22:20:05 +02:00
Kever Yang
7abb7e8fcb rockchip: rk3188: add -u-boot.dtsi for rock-rk3188
We should a -u-boot.dtsi for those config need by U-Boot only,
and other part sync with kernel.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-04-25 22:20:05 +02:00
Philipp Tomsich
e0e1d3f98c rockchip: timer: add compatible strings for rk3188 and rk3288
The DM driver for ockchip timer blocks is also applicable to the
RK3188 and RK3288 timer blocks: add 'rockchip,rk3188-timer' and
'rockchip,rk3288-timer' to its compatible list to support devices
claiming compatibility with these.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-04-25 22:20:05 +02:00
Klaus Goger
82a8e6c614 rockchip: defconfig: puma-rk3399: enable RTC
commit: 52280315a4 ("rtc: rewrite isl1208 to support DM") enables us to
use the on-module RTC emulation with the rk3399 device model i2c driver.

Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-04-25 18:25:21 +02:00
Heinrich Schuchardt
2144c74f68 rockchip: rk3288: provide ${fdtfile}
All rk3288 default configs define CONFIG_DEFAULT_DEVICE_TREE.
So we can use it to define ${fdtfile} in rk3288_common.h.

This variable is needed by the distro boot command.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-04-25 18:25:21 +02:00
Wadim Egorov
b0ba1e7e9d rockchip: clk: rk3288: add clk_enable function and support USB HOST0/HSIC
The generic ehci-driver (ehci-generic.c) will try to enable the clocks
listed in the DTSI. If this fails (e.g. due to clk_enable not being
implemented in a driver and -ENOSYS being returned by the clk-uclass),
the driver will bail our and print an error message.

This implements a minimal clk_enable for the RK3288 and supports the
clocks mandatory for the EHCI controllers; as these are enabled by
default we simply return success.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-04-25 14:05:09 +02:00
Philipp Tomsich
5ff8e54888 sunxi: improve throughput in the sunxi_mmc driver
Throughput tests have shown the sunxi_mmc driver to take over 10s to
read 10MB from a fast eMMC device due to excessive delays in polling
loops.

This commit restructures the main polling loops to use get_timer(...)
to determine whether a (millisecond) timeout has expired.  We choose
not to use the wait_bit function, as we don't need interruptability
with ctrl-c and have at least one case where two bits (one for an
error condition and another one for completion) need to be read and
using wait_bit would have not added to the clarity.

The observed speedup in testing on a A31 is greater than 10x (e.g. a
10MB write decreases from 9.302s to 0.884s).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Tested-by: Mylène Josserand <mylene.josserand@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-04-25 10:29:38 +05:30
Tom Rini
5512f5ccf1 Merge git://git.denx.de/u-boot-video 2018-04-24 20:27:43 -04:00
Tom Rini
751641814c video-uclass: Fix logical-not-parentheses warning
With clang-4.0 and later we see:
warning: logical not is only applied to the left hand side of this bitwise
operator [-Wlogical-not-parentheses]
        if ((!gd->flags & GD_FLG_RELOC))
             ^          ~

And while the compiler suggests adding parenthesis around gd->flags, a
reading of the code says that we want to know when GD_FLG_RELOC is not
set and then return.

Cc: Simon Glass <sjg@chromium.org>
Cc: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-24 20:57:14 +02:00
Tom Rini
49f8849de9 Merge tag 'signed-efi-2018.05' of git://github.com/agraf/u-boot
Patch queue for efi - 2018-04-23

Some last minute fixes for 2018.05. Most of them are minor fixes. On
top we have some functional improvements for the device path logic
which should also help us be more compatible.
2018-04-23 16:17:36 -04:00
Marek Vasut
ec360e6486 mmc: Staticize sd_select_bus_width
Staticize the function since it's only used in mmc.c .

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Tom Rini <trini@konsulko.com>
2018-04-23 16:07:46 -04:00
Heinrich Schuchardt
e83222bfc3 efi_selftest: test EFI_DEVICE_PATH_UTILITIES_PROTOCOL
Provide unit tests for the EFI_DEVICE_PATH_UTILITIES_PROTOCOL.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2018-04-23 21:34:28 +02:00
Heinrich Schuchardt
3acef5da40 efi_loader: complete EFI_DEVICE_PATH_UTILITIES_PROTOCOL
The missing services of the EFI_DEVICE_PATH_UTILITIES_PROTOCOL are
implemented.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2018-04-23 21:34:28 +02:00
Heinrich Schuchardt
f6dd3f359c efi_loader: correcty determine total device path length
Device paths may consist of multiple instances. Up to now we have only
considered the size of the first instance. For the services of the
EFI_DEVICE_PATH_UTILITIES_PROTOCOL in most cases the total length of the
device path is relevant.

So let's rename efi_dp_size() to efi_dp_instance_size() and create a new
function efi_dp_size() that calculates the total device path length.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2018-04-23 21:34:28 +02:00
Heinrich Schuchardt
adb575124d efi_loader: correctly determine length of empty device path
efi_dp_size() is meant to return the device path length without the end
node.

The length of a device path containing only an end node was incorrectly
reported as 4.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2018-04-23 21:34:28 +02:00
Heinrich Schuchardt
07836345ba efi_loader: fix AppendDevicePath
The logic of the AppendDevicePath service of the
EFI_DEVICE_PATH_UTILITIES_PROTOCOL is incorrectly implemented:

* if both paths are NULL an end node has to be returned
* if both paths are not NULL the end node of the second device path has to
  be kept

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2018-04-23 21:34:28 +02:00
Heinrich Schuchardt
211314c107 efi_loader: implement CreateDeviceNode
Implement the CreateDeviceNode service of the device path utility protocol.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2018-04-23 21:34:28 +02:00
Heinrich Schuchardt
065a8eca69 efi_selftest: fix typo in efi_selftest_devicepath.c
%s/provice/provide/

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2018-04-23 21:34:28 +02:00
Heinrich Schuchardt
b5cd6878e4 efi_selftest: do not execute test if setup failed
Executing a test after failed setup may lead to unexpected behavior like
an illegal memory access. So after a setup failure we should skip to
teardown.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2018-04-23 21:34:28 +02:00
Heinrich Schuchardt
c524997acb efi_loader: no support for ARMV7_NONSEC=y
We do not support bootefi booting ARMv7 in non-secure mode.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2018-04-23 21:34:28 +02:00
Heinrich Schuchardt
d8d8997bbc log: fix typo LOGL_EFI
According to the documentation the EFI log category is called LOGC_EFI.
All other categories start with LOGC_. So let's fix it.

Fixes: 1973b381a1 ("log: add category LOGC_EFI")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2018-04-23 21:34:28 +02:00
Tom Rini
3853c650e4 Merge git://git.denx.de/u-boot-uniphier 2018-04-23 12:21:20 -04:00
Masahiro Yamada
3ce5b1a8d8 ARM: uniphier: move SPL stack address
Currently, the address region, 0xf8000 - 0x100000, is used for SPL
stack for the 32bit SoCs.  Because the U-Boot proper image starts
from 0x70000, the maximum size of the U-Boot proper image is 544KB
(0x70000 - 0xf8000) for the NOR boot mode.  Now uniphier_v7_defconfig
is almost hitting this size limit.  Changing CONFIG_SPL_STACK can
raise the size limit with less impact.  With this, the size limit
will increase to 576KB (0x70000 - 0x100000).  If we need to increase
it even more, we would be able to change CONFIG_SYS_UBOOT_BASE at the
cost of the flashing command changes.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-24 00:35:35 +09:00
Masahiro Yamada
fbe73dc88d ARM: uniphier: select a correct mmc device before flashing images
Some boards support an SD card and an eMMC device at the same time.
Since both belong to 'mmc', they are identified by a device number.
When the device number of the eMMC is 1 instead 0, "mmc dev" command
must be performed to switch the target device before flashing images.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-24 00:35:35 +09:00
Masahiro Yamada
045e4fcb44 clk: uniphier: disable SPL_CLK
The last clock consumer in SPL, SD/eMMC driver, gave up using the
clock driver.  The clock driver is only used in U-Boot proper.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-24 00:35:35 +09:00
Masahiro Yamada
2a819b9085 ARM: dts: uniphier: drop u-boot, dm-pre-reloc from SD/eMMC clock node
Now that the SD/eMMC driver does not use the clock driver in SPL,
remove u-boot,dm-pre-reloc properties to let the fdtgrep tool drop
the unnecessary nodes.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-24 00:35:34 +09:00
Masahiro Yamada
fc2d0302b6 mmc: uniphier-sd: skip clock set-up for SPL
The size of SPL is hitting the limit (64KB) for uniphier_v7_defconfig.
When booting from SD/eMMC, obviously its clock has been properly set up
by the boot ROM.  Acutually, no need to re-initialize the clock in SPL.

Using a clock driver would generalize the SoC specific code, but
solving the memory footprint problem would win.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-24 00:35:34 +09:00
Masahiro Yamada
30b5d9aa9a mmc: tmio: move clk_enable() to each driver's probe function
I need to differentiate the clock handling for uniphier-sd.  Move it
to each driver's probe function from the tmio common code so that
renesas-sdhi will not be affected.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-24 00:35:34 +09:00
Masahiro Yamada
58d702274c ARM: uniphier: increase CONFIG_SYS_MONITOR_LEN
With the recent changes, the size of the U-Boot proper image for
uniphier_v7_defconfig exceeded the current limit, 512KB, then SPL
fails to load the whole of the U-Boot proper.  Increase the size.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-24 00:33:57 +09:00
Tom Rini
ff719a73d9 Merge tag 'xilinx-for-v2018.05-rc3' of git://git.denx.de/u-boot-microblaze
Xilinx fixes for v2018.05-rc3

- Fix nand initialization
- Runtime ddr detection for static DDR setting
- Enable rewriting env locations
- Sync defconfig for zc770 xm011
- Remove useless ioremap in watchdog
- Check return value from soc_clk_dump()
2018-04-23 10:50:38 -04:00
Heinrich Schuchardt
f6549c8541 mmc: avoid division by zero in meson_mmc_config_clock
The Odroid C2 fails to read from mmc with U-Boot v2018.03.
The change avoids a division by zero.

The fix was suggested by Jaehoon in
https://lists.denx.de/pipermail/u-boot/2018-January/318577.html

Reported-by: Vagrant Cascadian <vagrant@debian.org>
Suggested-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Tested-by: Vagrant Cascadian <vagrant@debian.org>
2018-04-23 10:49:58 -04:00
Michal Simek
ebc675b98d cmd: clk: Check return value from soc_clk_dump
In case of error in soc_clk_dump function are returned different values
then CMD return values (-1, 0, 1).

For example:
ZynqMP> clk dump
exit not allowed from main input shel

The patch is checking all negative return values and return
CMD_RET_FAILURE which is proper reaction for these cases.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-04-23 13:15:32 +02:00
Michal Simek
811c7bdebe watchdog: cadence: Remove useless ioremap
There is no need to call ioremap. Also reg pointer is completely unused
in the driver.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-04-23 13:15:32 +02:00
Michal Simek
6afedb90dd arm: zynq: Sync zc770 xm011 defconfigs
x8 and x16 configurations should be in sync.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-04-23 13:15:32 +02:00
Michal Simek
237dff2265 arm: zynq: Make ENV_SIZE and ENV_OFFSET optional via board file
Boards have an option to rewrite variable locations in their own board
files. This is necessary for qspi and nand configurations where boot
image can be bigger then 896k(current limit).

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-04-23 13:15:32 +02:00
Michal Simek
61dc92a29d arm: zynq: Wire automatic ddr detection for Zynq and ZynqMP case
When static memory configuration is used U-Boot has capability to detect
memory size in setup range. Enable this feature for static
configuration.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-04-23 13:15:32 +02:00
Michal Simek
3b2b2ccac7 arm: zynq: Enable setup board name for different boards
There is no need to use zynq name as SYS_BOARD for all boards.
The patch is adding an option to change it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-04-23 13:15:32 +02:00
Ezequiel Garcia
41b7d7f241 nand: zynq: Cleanup initialization
CONFIG_NAND_ZYNQ selects CONFIG_SYS_NAND_SELF_INIT, so the
driver doesn't have to play any ifdef game.

Also, we can mark zynq_nand_init() as static and get rid
of the mach-specific nand.h header.

This is really a revert of:
"mtd: zynq: nand: Move board_nand_init() function to board.c"
(sha1: 310995d9f9)

Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-04-23 13:15:30 +02:00
Ezequiel Garcia
07c5cbbd1e nand: zynq: Fix driver initialization
This driver is currently broken, refusing to initialize properly.

The reason is that get_nand_dev_by_index() was being called before
nand_register(), thus returning a pointer into uninitialized memory.
In other words, the struct mtd_info used by the driver is total junk.

Fix it by getting the correct struct mtd_info, via nand_to_mtd()
on the driver's struct nand_chip.

Tested on a custom board, where the CPU is halted without this patch.

Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-04-23 13:15:27 +02:00
Stefan Mavrodiev
4744d81cc0 sunxi: mmc: Fix phase delays
U-boot driver for sunxi-mmc uses PLL6, unlike linux kernel where
PLL5 is used, with clock rates respectively 600MHz and 768MHz.
Thus there are different phase degree steps - 24 for the kernel and
30 for u-boot.

In the kernel driver the phase is set 90 deg for output and 120 for
sample. Dividing by 30 will result values 3 and 4. Those are the
values set in the u-boot driver.

However, the condition defining delays is wrong. MMC core driver
requests clock of 52MHz, sunxi-driver sets clock of 50MHz, but
phase is set 30 deg for output and 120 deg for sample.

Apparently this works for most cards.
On A20-SOM204-EVB-eMMC there is eMMC card (KLMAG2GEND) which complains
about it. Maybe there is other boards with similar problem?
So the fix is to match delays for both u-boot and kernel.

Signed-off-by: Stefan Mavrodiev <stefan@olimex.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-04-23 12:12:56 +05:30
Eugeniy Paltsev
9b14ac5cc2 spi: dw: invert wait condition in dw_spi_xfer
While switching to readl_poll_timeout macros from custom code
the waiting condition was accidently inverted, so it was pure
luck that this code works at least in some conditions.

Fix that by inverting exit condition for readl_poll_timeout.

Fixes: c6b4f031d9 ("DW SPI: fix tx data loss on FIFO flush")

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-04-23 11:16:41 +05:30
Tom Rini
275d80a4c2 Merge git://git.denx.de/u-boot-usb 2018-04-22 09:30:36 -04:00
Tom Rini
d335a9e722 Merge git://git.denx.de/u-boot-sh 2018-04-22 09:30:29 -04:00
Neil Armstrong
38276090ee usb: dwc3-of-simple: fix error check of clk_get_bulk when disabled
The disabled clk API returns -ENOSYS unlike the reset API returning -ENOTSUPP.

Fixes: ca7fdc8b12 ("usb: host: Add simple of glue driver for DWC3 USB Controllers integration")
Reported-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-04-21 18:38:56 +02:00
Jean-Jacques Hiblot
cc73ba97c0 usb: dwc3-of-simple: Add support for DRA7/AM57 platforms.
Add the compatibility with "ti,dwc3" and enable it by default if DM_USB
is enabled.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-04-21 18:38:56 +02:00
Jean-Jacques Hiblot
103774b71c usb: dwc3-of-simple: Fix dependencies
This simple glue layer does not require CONFIG_MISC, but it does require
CONFIG_DM_USB.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-04-21 18:38:56 +02:00
Marek Vasut
f7aa3cd4a8 ARM: rmobile: Update E2 Silk
The E2 Silk port was broken since some time. This patch updates
the E2 Silk port to use modern frameworks, DM, DT probing, SPL
for the preloading and puts it on par with the M2 Porter board.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---
NOTE: The port is missing support for I2C1 for DA9063 reset, since the
      I2C driver needs to be converted to DM and DT probing. That's not
      an issue for this patch though, since the reset was broken on Silk
      since forever.
2018-04-21 18:33:31 +02:00
Marek Vasut
1ddbcf46bf mmc: sh_mmcif: Migrate configs to CONFIG_SH_MMCIF
Migrate the U-Boot configs to Kconfig CONFIG_SH_MMCIF .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
2018-04-21 18:33:31 +02:00
Marek Vasut
f3dca4aac6 mmc: sh_mmcif: Add Kconfig entry
Add Kconfig entry for SH MMCIF driver.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
2018-04-21 18:33:30 +02:00
Marek Vasut
48f54a2d74 mmc: sh_mmcif: Add DM and DT probing support
Add MMC DM and DT probing support into the SH MMCIF driver.
This patch abstracts out the common bits of the send command
and set ios functions, so they can be used both by DM and non
DM setups and adds the DM probe support.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
2018-04-21 18:33:19 +02:00
Marek Vasut
010bbe7331 clk: renesas: Minor clean up of the R8A7794 clock driver
The initconst is not used in U-Boot, drop it. The r8a7794_crit_mod_clks
is also not used in U-Boot, so drop it too.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-04-21 18:00:00 +02:00
Marek Vasut
841feae985 clk: renesas: Minor clean up of the R8A7792 clock driver
The initconst is not used in U-Boot, drop it. The r8a7792_crit_mod_clks
is also not used in U-Boot, so drop it too.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-04-21 18:00:00 +02:00
Sean Nyekjaer
4d95ed39a1 sf: Add Spansion s25fl208k entry
Add entry for Spansion s25fl208k part.

Signed-off-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-04-19 16:57:19 +05:30
Eugeniy Paltsev
a19e97157c mtd: sf: add support for sst26wf016, sst26wf032, sst26wf064
This commit adds support for the SST sst26wf016, sst26wf032
and sst26wf064 flash IC.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-04-19 16:54:25 +05:30
Eugeniy Paltsev
3d4fed87a5 mtd: sf: Add support of sst26wf* flash ICs protection ops
sst26wf flash series block protection implementation differs
from other SST series, so add specific implementation
flash_lock/flash_unlock/flash_is_locked functions for sst26wf
flash ICs.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2018-04-19 16:54:01 +05:30
Tom Rini
a35747b5e1 Merge git://git.denx.de/u-boot-uniphier 2018-04-18 16:24:26 -04:00
Tom Rini
8bc51b6e17 Merge git://git.denx.de/u-boot-sh 2018-04-18 16:24:14 -04:00
Kunihiko Hayashi
f8c08ab409 reset: uniphier: add ethernet reset control support
Add reset lines for ethernet controller on each SoC.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-18 23:42:33 +09:00
Kunihiko Hayashi
461766cb69 clk: uniphier: add ethernet clock control support
Add clock control for ethernet controller on each SoC.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-18 23:42:25 +09:00
Masahiro Yamada
3e98fc1236 ARM: dts: uniphier: sync DT with Linux 4.17-rc1
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-18 23:34:36 +09:00
Tom Rini
40df6b3e18 Merge git://git.denx.de/u-boot-socfpga 2018-04-17 17:45:28 -04:00
Tom Rini
f4df1f7678 Merge tag 'arc-for-2018.05-rc3' of git://git.denx.de/u-boot-arc
Subtle ARC fixes for v2018.05-RC3

These are only very subtle clean-ups here and there including:

 * Correctly specified CPU freq for HSDK
   (production boards are all shipped with 500MHZ as opposed
    to early batch running at 1GHz)

 * Addition of SNPS internal group email to MAINTAINERS file
 * Switch to Hush shell on AXS10x boards
2018-04-17 17:45:18 -04:00
Neil Armstrong
1dd181ff2b reset: fix bulk API when DM_RESET is disabled
In the commit "reset: Add get/assert/deassert/release for bulk of reset signals"
the disabled reset_release_bulk() and reset_get_bulk() used the wrong
struct clk_bulk instead of struct reset_ctl_bulk.

Fixes: 0c28233903 ("reset: Add get/assert/deassert/release for bulk of reset signals")
Reported-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-04-17 17:45:08 -04:00
Bryan O'Donoghue
bbac9222dc bootm: Align cache flush begin address
commit b4d956f6bc ("bootm: Align cache flush end address correctly")
aligns the end address of the cache flush operation to a cache-line size to
ensure lower-layers in the code accept the range provided and flush.

A similar action should be taken for the begin address of a cache flush
operation. The load address may not be aligned to a cache-line boundary, so
ensure the passed address is aligned.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reported-by: Breno Matheus Lima <brenomatheus@gmail.com>
Suggested-by: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Tested-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-04-17 17:45:08 -04:00
Neil Armstrong
721881c417 clk: fix clk_get_bulk when phandle error
This fixes the Coverity Defect CID 175347 when dev_count_phandle_with_args()
returns a negative value.

Fixes: a855be87da ("clk: Add get/enable/disable/release for a bulk of clocks")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-04-17 17:45:08 -04:00
Neil Armstrong
895a82ce90 reset: fix reset_get_bulk when phandle error
This fixes the Coverity Defect CID 175348 when dev_count_phandle_with_args()
returns a negative value.

Fixes: 0c28233903 ("reset: Add get/assert/deassert/release for bulk of reset signals")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-04-17 17:45:08 -04:00
Marek Vasut
7d0299cd8f ARM: rmobile: Update M2 Koelsch
The M2 Koelsch port was broken since some time. This patch updates
the M2 Koelsch port to use modern frameworks, DM, DT probing, SPL
for the preloading and puts it on par with the M2 Porter board.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-04-17 20:19:57 +02:00
Eugeniy Paltsev
474e9312a8 ARC: Remove unused DECLARE_GLOBAL_DATA_PTR from init_helpers.c
"Global data" structure "gd" is not used in init_helpers.c
thus DECLARE_GLOBAL_DATA_PTR might be safely removed.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-04-17 20:52:17 +03:00
Eugeniy Paltsev
4006200d49 ARC: Update ARC architecture maintainers
Update ARC architecture maintainers and add
uboot-snps-arc@synopsys.com mailing list.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-04-17 20:52:17 +03:00
Eugeniy Paltsev
9249d74781 ARC: AXS10x: Enable hush shell
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-04-17 20:52:17 +03:00
Eugeniy Paltsev
9289b15aec ARC: HSDK: Fix CPU frequency value
CPU on HSDK board runs at 500MHz after preloader so fix
wrong CPU frequency value in hsdk_defconfig.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-04-17 20:50:49 +03:00
Tom Rini
34b3722e38 configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-17 10:10:47 -04:00
Tom Rini
50b9782c83 Merge git://git.denx.de/u-boot-marvell 2018-04-17 09:14:33 -04:00
Dinh Nguyen
f369e1564c configs: socfpga: disable EFI and ISO partition types
None of the SoCFPGA platforms will support EFI/ISO partition types that
is needed for DISTRO_DEFAULTS. SoCFPGA bootroom will only support 0xa2
partition type.

This is needed to help limit the size of the SPL to within the 64k limit
that is required for SoCFPGA.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-04-17 11:39:50 +02:00
Dinh Nguyen
a8c2dcf098 configs: socfpga: add DM_RESET
Add the DM reset driver to socfpga defconfigs.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-04-17 11:39:50 +02:00
Dinh Nguyen
622597dee4 i2c: designware: add reset ctrl to driver
Add code to look for a reset manager property. Specifically, look for the
reset-names of 'i2c'. A reset property is an optional feature, so only print
out a warning and do not fail if a reset property is not present.

If a reset property is discovered, then use it to deassert, thus bringing the
IP out of reset.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-04-17 11:39:49 +02:00
Dinh Nguyen
449ff9c431 arm: dts: socfpga: add reset property
Add reset dts property to the i2c nodes.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-04-17 11:39:49 +02:00
Dinh Nguyen
67e4436e88 arm: dts: socfpga: enables i2c0 in socfpga_de0_nano
Add all the appropriate i2c alias in the base socfpga dtsi and enables
the i2c node on the DE0 NANO board.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-04-17 11:39:49 +02:00
Dinh Nguyen
2878942aa2 configs: socfpga: convert i2c to dm
Enable DM I2C driver on SoCFPGA platforms.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-04-17 11:39:49 +02:00
Dinh Nguyen
2ac718821a reset: socfpga: add reset driver for SoCFPGA platform
Add a DM compatible reset driver for the SoCFPGA platform.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-04-17 11:39:49 +02:00
Dinh Nguyen
81577a3b04 ARM: dts: stratix10: Add base dtsi and devkit dts
From the Linux v4.16-rc4, add the base dtsi and devkit dts files for
the Stratix10 SoCFPGA platform.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-04-17 11:39:49 +02:00
Dinh Nguyen
e74c15bc81 ARM64: stratix10: add reset manager includes
Pulled from linux v4.16-rc4.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-04-17 11:39:48 +02:00
Chin Liang See
8faeab9304 arm: socfpga: stratix10: Add base address map for Statix10 SoC
Add the base address map for Stratix10 SoC

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-04-17 11:39:48 +02:00
Marek Vasut
f2b6f82b9d ARM: rmobile: Ignore U-Boot env when started via JTAG on Porter
When U-Boot is started via JTAG, ignore the installed environment
as it may interfere with the recovery of the board.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-04-17 11:38:56 +02:00
Marek Vasut
a3c159b9c3 ARM: rmobile: Ignore U-Boot env when started via JTAG on Stout
When U-Boot is started via JTAG, ignore the installed environment
as it may interfere with the recovery of the board.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-04-17 11:38:56 +02:00
Marek Vasut
1a6e8dda49 ARM: rmobile: Enable fitImage support on Gen3
Enable fitImage support to be on the right side of the millenium.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-04-17 11:38:55 +02:00
Marek Vasut
de7496667a ARM: rmobile: Disable SDHI on R8A77970 V3M Eagle
The SDHI is not routed to a slot on the Eagle, so disable it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-04-17 11:38:55 +02:00
Marek Vasut
5e7f63db92 ARM: rmobile: Enable RPC QSPI on R8A77970 V3M Eagle
Enable the RPC QSPI driver on R8A77970 V3M Eagle and configure
the environment layout to match that used by old U-Boot.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-04-17 11:38:55 +02:00
Marek Vasut
93365eff60 ARM: rmobile: Add Renesas RPC HF/QSPI DT nodes
Add device tree nodes for the Renesas RPC HF/QSPI controller.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-04-17 11:38:55 +02:00
Matt Pelland
ca4e7d674e mmc: mv_sdhci: zero out sdhci_host structure
The mv_sdhci driver was not zeroing the sdhci_host structure it
allocates causing random access violations in parts of the mmc core
where the "ops" member pointers are checked and called if not NULL.

Signed-off-by: Matt Pelland <mpelland@starry.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-04-17 10:39:30 +02:00
Fabio Estevam
02325c7bfd treewide: fix up files incorrectly marked executable
Inspired by the following kernel commit:

"commit 90fda63fa1156ec1bcfd7f9ca384cec221f70a21
Author: Linus Torvalds <torvalds@linux-foundation.org>
Date:   Sat Apr 7 13:31:23 2018 -0700

treewide: fix up files incorrectly marked executable

Joe Perches noted that we have a few source files that for some
inexplicable reason (read: I'm too lazy to even go look at the history)
are marked executable:

drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
drivers/net/ethernet/cadence/macb_ptp.c

A simple git command line to show executable C/asm/header files is this:

   git ls-files -s '*.[chsS]' | grep '^100755'

and then you can fix them up with scripting by just feeding that output
into:

  | cut -f2 | xargs chmod -x

and commit it.

Which is exactly what this commit does.

Reported-by: Joe Perches <joe@perches.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>"

Do the same in the U-Boot source tree.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-04-09 15:16:31 +02:00
1398 changed files with 6712 additions and 3365 deletions

16
Kconfig
View File

@@ -68,17 +68,13 @@ config CC_COVERAGE
config DISTRO_DEFAULTS
bool "Select defaults suitable for booting general purpose Linux distributions"
default y if ARCH_SUNXI || TEGRA
default y if ARCH_LS2080A
default y if ARCH_MESON
default y if ARCH_ROCKCHIP
default n
imply USE_BOOTCOMMAND
select CMD_BOOTZ if ARM && !ARM64
select CMD_BOOTI if ARM64
select CMD_DHCP if CMD_NET
select CMD_PING if CMD_NET
select CMD_PXE if NET
select CMD_ENV_EXISTS
select CMD_EXT2
select CMD_EXT4
select CMD_FAT
@@ -361,6 +357,16 @@ endif # SPL
endif # FIT
config IMAGE_FORMAT_LEGACY
bool "Enable support for the legacy image format"
default y if !FIT_SIGNATURE
help
This option enables the legacy image format. It is enabled by
default for backward compatibility, unless FIT_SIGNATURE is
set where it is disabled so that unsigned images cannot be
loaded. If a board needs the legacy image format support in this
case, enable it here.
config OF_BOARD_SETUP
bool "Set up board-specific details in device tree before boot"
depends on OF_LIBFDT

View File

@@ -55,7 +55,9 @@ Maintainers List (try to look for most precise areas first)
-----------------------------------
ARC
M: Alexey Brodkin <alexey.brodkin@synopsys.com>
M: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
S: Maintained
L: uboot-snps-arc@synopsys.com
T: git git://git.denx.de/u-boot-arc.git
F: arch/arc/

View File

@@ -5,7 +5,7 @@
VERSION = 2018
PATCHLEVEL = 05
SUBLEVEL =
EXTRAVERSION = -rc2
EXTRAVERSION = -rc3
NAME =
# *DOCUMENTATION*
@@ -595,6 +595,9 @@ endif
KBUILD_CFLAGS += $(call cc-option,-fno-stack-protector)
KBUILD_CFLAGS += $(call cc-option,-fno-delete-null-pointer-checks)
# change __FILE__ to the relative path from the srctree
KBUILD_CFLAGS += $(call cc-option,-fmacro-prefix-map=$(srctree)/=)
KBUILD_CFLAGS += -g
# $(KBUILD_AFLAGS) sets -g, which causes gcc to pass a suitable -g<format>
# option to the assembler.
@@ -610,6 +613,13 @@ endif
endif
KBUILD_CFLAGS += $(call cc-option,-Wno-format-nonliteral)
ifeq ($(cc-name),clang)
KBUILD_CPPFLAGS += $(call cc-option,-Qunused-arguments,)
KBUILD_CFLAGS += $(call cc-disable-warning, format-invalid-specifier)
KBUILD_CFLAGS += $(call cc-disable-warning, gnu)
KBUILD_CFLAGS += $(call cc-disable-warning, address-of-packed-member)
KBUILD_CFLAGS += $(call cc-option, -fcatch-undefined-behavior)
endif
# turn jbsr into jsr for m68k
ifeq ($(ARCH),m68k)

13
README
View File

@@ -2413,19 +2413,6 @@ FIT uImage format:
-150 common/cmd_nand.c Incorrect FIT image format
151 common/cmd_nand.c FIT image format OK
- legacy image format:
CONFIG_IMAGE_FORMAT_LEGACY
enables the legacy image format support in U-Boot.
Default:
enabled if CONFIG_FIT_SIGNATURE is not defined.
CONFIG_DISABLE_IMAGE_LEGACY
disable the legacy image format
This define is introduced, as the legacy image format is
enabled per default for backward compatibility.
- Standalone program support:
CONFIG_STANDALONE_LOAD_ADDR

View File

@@ -12,8 +12,6 @@
#include <linux/types.h>
#include <api_public.h>
DECLARE_GLOBAL_DATA_PTR;
#define DEBUG
#undef DEBUG

View File

@@ -75,6 +75,7 @@ config SANDBOX
select DM_GPIO
select DM_MMC
select HAVE_BLOCK_DEVICE
select SPI
select LZO
imply CMD_GETTIME
imply CMD_HASH

View File

@@ -7,8 +7,6 @@
#include <asm/cache.h>
#include <common.h>
DECLARE_GLOBAL_DATA_PTR;
int init_cache_f_r(void)
{
sync_n_cleanup_cache_all();

View File

@@ -242,6 +242,16 @@ config SYS_CACHELINE_SIZE
default 64 if SYS_CACHE_SHIFT_6
default 32 if SYS_CACHE_SHIFT_5
config SYS_ARCH_TIMER
bool "ARM Generic Timer support"
depends on CPU_V7 || ARM64
default y if ARM64
help
The ARM Generic Timer (aka arch-timer) provides an architected
interface to a timer source on an SoC.
It is mandantory for ARMv8 implementation and widely available
on ARMv7 systems.
config ARM_SMCCC
bool "Support for ARM SMC Calling Convention (SMCCC)"
depends on CPU_V7 || ARM64
@@ -379,6 +389,7 @@ config ARCH_MVEBU
select DM_SERIAL
select DM_SPI
select DM_SPI_FLASH
select SPI
config TARGET_DEVKIT3250
bool "Support devkit3250"
@@ -434,6 +445,7 @@ config TARGET_STV0991
select DM_SERIAL
select DM_SPI
select DM_SPI_FLASH
select SPI
select SPI_FLASH
select PL01X_SERIAL
@@ -540,6 +552,7 @@ config ARCH_EXYNOS
select DM_SPI
select DM_GPIO
select DM_KEYBOARD
select SPI
imply FAT_WRITE
config ARCH_S5PC1XX
@@ -567,6 +580,7 @@ config ARCH_KEYSTONE
select SUPPORT_SPL
select SYS_THUMB_BUILD
select CMD_POWEROFF
select SYS_ARCH_TIMER
imply CMD_MTDPARTS
imply FIT
imply CMD_SAVES
@@ -581,6 +595,7 @@ config ARCH_OMAP2PLUS
config ARCH_MESON
bool "Amlogic Meson"
imply DISTRO_DEFAULTS
help
Support for the Meson SoC family developed by Amlogic Inc.,
targeted at media players and tablet computers. We currently
@@ -720,6 +735,7 @@ config ARCH_SUNXI
select USB_KEYBOARD if DISTRO_DEFAULTS
select USE_TINY_PRINTF
imply CMD_GPT
imply DISTRO_DEFAULTS
imply FAT_WRITE
imply OF_LIBFDT_OVERLAY
imply PRE_CONSOLE_BUFFER
@@ -760,6 +776,7 @@ config ARCH_ZYNQ
select CLK
select SPL_CLK if SPL
select CLK_ZYNQ
select SPI
imply CMD_CLK
imply FAT_WRITE
imply CMD_SPL
@@ -780,6 +797,7 @@ config ARCH_ZYNQMP
config TEGRA
bool "NVIDIA Tegra"
imply DISTRO_DEFAULTS
imply FAT_WRITE
config TARGET_VEXPRESS64_AEMV8A
@@ -1177,7 +1195,9 @@ config ARCH_ROCKCHIP
select DM_PWM
select DM_REGULATOR
select ENABLE_ARM_SOC_BOOT0_HOOK
select SPI
imply CMD_FASTBOOT
imply DISTRO_DEFAULTS
imply FASTBOOT
imply FAT_WRITE
imply USB_FUNCTION_FASTBOOT
@@ -1185,6 +1205,7 @@ config ARCH_ROCKCHIP
imply TPL_SYSRESET
imply ADC
imply SARADC_ROCKCHIP
imply SYS_NS16550
config TARGET_THUNDERX_88XX
bool "Support ThunderX 88xx"
@@ -1352,7 +1373,7 @@ source "arch/arm/Kconfig.debug"
endmenu
config SPL_LDSCRIPT
default "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" if ARCH_MX23 || ARCH_MX28
default "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" if (ARCH_MX23 || ARCH_MX28) && !SPL_FRAMEWORK
default "arch/arm/cpu/arm1136/u-boot-spl.lds" if CPU_ARM1136
default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64

View File

@@ -23,9 +23,8 @@ PLATFORM_RELFLAGS += $(call cc-option, -msoft-float) \
$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
# LLVM support
LLVMS_RELFLAGS := $(call cc-option,-mllvm,) \
$(call cc-option,-target arm-none-eabi,) \
$(call cc-option,-arm-use-movt=0,)
LLVM_RELFLAGS := $(call cc-option,-mllvm,) \
$(call cc-option,-mno-movt,)
PLATFORM_RELFLAGS += $(LLVM_RELFLAGS)
PLATFORM_CPPFLAGS += -D__ARM__

View File

@@ -23,8 +23,6 @@
#define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source */
#define GPTCR_TEN 1 /* Timer enable */
DECLARE_GLOBAL_DATA_PTR;
/* The 32768Hz 32-bit timer overruns in 131072 seconds */
int timer_init(void)
{

View File

@@ -12,8 +12,6 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
DECLARE_GLOBAL_DATA_PTR;
/* General purpose timers bitfields */
#define GPTCR_SWR (1<<15) /* Software reset */
#define GPTCR_FRR (1<<9) /* Freerun / restart */

View File

@@ -14,8 +14,8 @@ obj-y += spl_boot.o spl_lradc_init.o spl_mem_init.o spl_power_init.o
endif
# Specify the target for use in elftosb call
MKIMAGE_TARGET-$(CONFIG_MX23) = mxsimage.mx23.cfg
MKIMAGE_TARGET-$(CONFIG_MX28) = mxsimage.mx28.cfg
MKIMAGE_TARGET-$(CONFIG_MX23) = mxsimage$(CONFIG_SPL_FRAMEWORK:%=-spl).mx23.cfg
MKIMAGE_TARGET-$(CONFIG_MX28) = mxsimage$(CONFIG_SPL_FRAMEWORK:%=-spl).mx28.cfg
# Generate HAB-capable IVT
#

View File

@@ -24,7 +24,7 @@
DECLARE_GLOBAL_DATA_PTR;
/* Lowlevel init isn't used on i.MX28, so just have a dummy here */
void lowlevel_init(void) {}
__weak void lowlevel_init(void) {}
void reset_cpu(ulong ignored) __attribute__((noreturn));
@@ -178,8 +178,7 @@ const char *get_imx_type(u32 imxtype)
int print_cpuinfo(void)
{
u32 cpurev;
struct mxs_spl_data *data = (struct mxs_spl_data *)
((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf);
struct mxs_spl_data *data = MXS_SPL_DATA;
cpurev = get_cpu_rev();
printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
@@ -277,8 +276,7 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
int mxs_dram_init(void)
{
struct mxs_spl_data *data = (struct mxs_spl_data *)
((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf);
struct mxs_spl_data *data = MXS_SPL_DATA;
if (data->mem_dram_size == 0) {
printf("MXS:\n"

View File

@@ -0,0 +1,5 @@
DISPLAYPROGRESS
SECTION 0x0 BOOTABLE
TAG LAST
LOAD 0x1000 spl/u-boot-spl.bin
CALL 0x1000 0x0

View File

@@ -0,0 +1,6 @@
DISPLAYPROGRESS
SECTION 0x0 BOOTABLE
TAG LAST
LOAD 0x1000 spl/u-boot-spl.bin
LOAD IVT 0x8000 0x1000
CALL HAB 0x8000 0x0

View File

@@ -120,8 +120,7 @@ void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr,
const iomux_cfg_t *iomux_setup,
const unsigned int iomux_size)
{
struct mxs_spl_data *data = (struct mxs_spl_data *)
((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf);
struct mxs_spl_data *data = MXS_SPL_DATA;
uint8_t bootmode = mxs_get_bootmode_index();
gd = &gdata;
@@ -147,6 +146,7 @@ void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr,
}
}
#ifndef CONFIG_SPL_FRAMEWORK
/* Support aparatus */
inline void board_init_f(unsigned long bootflag)
{
@@ -159,3 +159,4 @@ inline void board_init_r(gd_t *id, ulong dest_addr)
for (;;)
;
}
#endif

View File

@@ -105,9 +105,9 @@ flush_dcache:
/*
* Go setup Memory and board specific bits prior to relocation.
*/
mov ip, lr /* perserve link reg across call */
mov r4, lr /* perserve link reg across call */
bl lowlevel_init /* go setup pll,mux,memory */
mov lr, ip /* restore link */
mov lr, r4 /* restore link */
#endif
mov pc, lr /* back to my caller */
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */

View File

@@ -9,7 +9,7 @@ extra-y := start.o
obj-y += cpu.o
ifndef CONFIG_$(SPL_TPL_)TIMER
obj-y += generic_timer.o
obj-$(CONFIG_SYS_ARCH_TIMER) += generic_timer.o
endif
obj-y += cache_v8.o
obj-y += exceptions.o

View File

@@ -167,6 +167,7 @@ config ARCH_LS2080A
select SYS_I2C_MXC_I2C2
select SYS_I2C_MXC_I2C3
select SYS_I2C_MXC_I2C4
imply DISTRO_DEFAULTS
imply PANIC_HANG
config FSL_LSCH2

View File

@@ -26,8 +26,6 @@
#endif
#include <fsl_immap.h>
DECLARE_GLOBAL_DATA_PTR;
bool soc_has_dp_ddr(void)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);

View File

@@ -12,8 +12,6 @@
#include <asm/arch/mc_me_regs.h>
#include "cpu.h"
DECLARE_GLOBAL_DATA_PTR;
u32 cpu_mask(void)
{
return readl(MC_ME_CS);

View File

@@ -9,8 +9,6 @@
#include <common.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
int timer_init(void)
{
writel(0, CONFIG_SYS_TIMER_COUNTER);

View File

@@ -21,6 +21,7 @@ SECTIONS
*(.vectors)
CPUDIR/start.o (.text*)
*(.text*)
*(.glue*)
}
. = ALIGN(4);

View File

@@ -193,6 +193,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \
socfpga_cyclone5_sockit.dtb \
socfpga_cyclone5_socrates.dtb \
socfpga_cyclone5_sr1500.dtb \
socfpga_stratix10_socdk.dtb \
socfpga_cyclone5_vining_fpga.dtb
dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \

View File

@@ -1,5 +1,5 @@
/*
* Copyright 2017 Armadeus Systems <support@armadeus.com>
* Copyright 2018 Armadeus Systems <support@armadeus.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
@@ -99,6 +99,7 @@
/* eMMC */
&usdhc1 {
u-boot,dm-spl;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
bus-width = <8>;
@@ -161,6 +162,7 @@
};
pinctrl_usdhc1: usdhc1grp {
u-boot,dm-spl;
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059

View File

@@ -228,6 +228,7 @@
};
&uart1 {
u-boot,dm-spl;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
@@ -373,6 +374,7 @@
};
pinctrl_uart1: uart1grp {
u-boot,dm-spl;
fsl,pins = <
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1

View File

@@ -194,6 +194,7 @@
#size-cells = <1>;
reg = <0x02000000 0x40000>;
ranges;
u-boot,dm-spl;
ecspi1: ecspi@02008000 {
#address-cells = <1>;

View File

@@ -8,3 +8,7 @@
#include "r8a7790-lager.dts"
#include "r8a7790-u-boot.dtsi"
&scif0 {
u-boot,dm-pre-reloc;
};

View File

@@ -8,3 +8,7 @@
#include "r8a7791-koelsch.dts"
#include "r8a7791-u-boot.dtsi"
&scif0 {
u-boot,dm-pre-reloc;
};

View File

@@ -8,3 +8,7 @@
#include "r8a7793-gose.dts"
#include "r8a7793-u-boot.dtsi"
&scif0 {
u-boot,dm-pre-reloc;
};

View File

@@ -8,3 +8,7 @@
#include "r8a7794-alt.dts"
#include "r8a7794-u-boot.dtsi"
&scif2 {
u-boot,dm-pre-reloc;
};

View File

@@ -8,3 +8,7 @@
#include "r8a7794-silk.dts"
#include "r8a7794-u-boot.dtsi"
&scif2 {
u-boot,dm-pre-reloc;
};

View File

@@ -1525,6 +1525,14 @@
dma-channels = <2>;
};
rpc: rpc@0xee200000 {
compatible = "renesas,rpc-r8a7795", "renesas,rpc";
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
clocks = <&cpg CPG_MOD 917>;
bank-width = <2>;
status = "disabled";
};
sdhi0: sd@ee100000 {
compatible = "renesas,sdhi-r8a7795";
reg = <0 0xee100000 0 0x2000>;

View File

@@ -1350,6 +1350,14 @@
status = "disabled";
};
rpc: rpc@0xee200000 {
compatible = "renesas,rpc-r8a7796", "renesas,rpc";
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
clocks = <&cpg CPG_MOD 917>;
bank-width = <2>;
status = "disabled";
};
sdhi0: sd@ee100000 {
compatible = "renesas,sdhi-r8a7796";
reg = <0 0xee100000 0 0x2000>;

View File

@@ -748,6 +748,14 @@
status = "disabled";
};
rpc: rpc@0xee200000 {
compatible = "renesas,rpc-r8a77965", "renesas,rpc";
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
clocks = <&cpg CPG_MOD 917>;
bank-width = <2>;
status = "disabled";
};
sdhi0: sd@ee100000 {
compatible = "renesas,sdhi-r8a77965";
reg = <0 0xee100000 0 0x2000>;

View File

@@ -17,6 +17,7 @@
aliases {
serial0 = &scif0;
ethernet0 = &avb;
spi0 = &rpc;
};
chosen {
@@ -59,6 +60,25 @@
};
};
&rpc {
num-cs = <1>;
status = "okay";
spi-max-frequency = <50000000>;
#address-cells = <1>;
#size-cells = <0>;
flash0: spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "s25fs512s", "spi-flash", "jedec,spi-nor";
spi-max-frequency = <50000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
reg = <0>;
status = "okay";
};
};
&scif0 {
pinctrl-0 = <&scif0_pins>;
pinctrl-names = "default";

View File

@@ -381,5 +381,13 @@
#address-cells = <1>;
#size-cells = <0>;
};
rpc: rpc@0xee200000 {
compatible = "renesas,rpc-r8a77970", "renesas,rpc";
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
clocks = <&cpg CPG_MOD 917>;
bank-width = <2>;
status = "disabled";
};
};
};

View File

@@ -400,5 +400,13 @@
#phy-cells = <0>;
status = "disabled";
};
rpc: rpc@0xee200000 {
compatible = "renesas,rpc-r8a77995", "renesas,rpc";
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
clocks = <&cpg CPG_MOD 917>;
bank-width = <2>;
status = "disabled";
};
};
};

View File

@@ -0,0 +1,24 @@
/*
* Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd.
*
* SPDX-License-Identifier: GPL-2.0+
*/
&cru {
u-boot,dm-spl;
};
&pinctrl {
u-boot,dm-spl;
};
&uart2 {
status = "okay";
u-boot,dm-spl;
};
&timer3 {
compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
u-boot,dm-spl;
clock-frequency = <24000000>;
};

View File

@@ -7,6 +7,7 @@
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "rk3188.dtsi"
#include "rk3188-radxarock-u-boot.dtsi"
/ {
model = "Radxa Rock";
@@ -356,11 +357,6 @@
status = "okay";
};
&uart2 {
status = "okay";
u-boot,dm-spl;
};
&uart3 {
status = "okay";
};

View File

@@ -105,7 +105,6 @@
compatible = "rockchip,rk3188-cru";
reg = <0x20000000 0x1000>;
rockchip,grf = <&grf>;
u-boot,dm-spl;
#clock-cells = <1>;
#reset-cells = <1>;
@@ -124,6 +123,12 @@
};
};
timer3: timer@2000e000 {
compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
reg = <0x2000e000 0x20>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
};
usbphy: phy {
compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy";
rockchip,grf = <&grf>;
@@ -156,7 +161,6 @@
#address-cells = <1>;
#size-cells = <1>;
ranges;
u-boot,dm-spl;
gpio0: gpio0@2000a000 {
compatible = "rockchip,gpio-bank";

View File

@@ -14,6 +14,10 @@
aliases {
ethernet0 = &gmac0;
ethernet1 = &gmac1;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
serial0 = &uart0;
serial1 = &uart1;
timer0 = &timer0;
@@ -505,6 +509,8 @@
compatible = "snps,designware-i2c";
reg = <0xffc04000 0x1000>;
clocks = <&l4_sp_clk>;
resets = <&rst I2C0_RESET>;
reset-names = "i2c";
interrupts = <0 158 0x4>;
status = "disabled";
};
@@ -515,6 +521,8 @@
compatible = "snps,designware-i2c";
reg = <0xffc05000 0x1000>;
clocks = <&l4_sp_clk>;
resets = <&rst I2C1_RESET>;
reset-names = "i2c";
interrupts = <0 159 0x4>;
status = "disabled";
};
@@ -525,6 +533,8 @@
compatible = "snps,designware-i2c";
reg = <0xffc06000 0x1000>;
clocks = <&l4_sp_clk>;
resets = <&rst I2C2_RESET>;
reset-names = "i2c";
interrupts = <0 160 0x4>;
status = "disabled";
};
@@ -535,6 +545,8 @@
compatible = "snps,designware-i2c";
reg = <0xffc07000 0x1000>;
clocks = <&l4_sp_clk>;
resets = <&rst I2C3_RESET>;
reset-names = "i2c";
interrupts = <0 161 0x4>;
status = "disabled";
};

View File

@@ -56,6 +56,18 @@
status = "okay";
};
&i2c0 {
status = "okay";
dxl345: adxl345@0 {
compatible = "adi,adxl345";
reg = <0x53>;
interrupt-parent = <&portc>;
interrupts = <3 2>;
};
};
&mmc0 {
status = "okay";
u-boot,dm-pre-reloc;

View File

@@ -0,0 +1,381 @@
/*
* Copyright (C) 2018 Intel Corporation
*
* SPDX-License-Identifier: GPL-2.0
*/
/dts-v1/;
#include <dt-bindings/reset/altr,rst-mgr-s10.h>
#include <dt-bindings/gpio/gpio.h>
/ {
compatible = "altr,socfpga-stratix10";
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
enable-method = "psci";
reg = <0x0>;
};
cpu1: cpu@1 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
enable-method = "psci";
reg = <0x1>;
};
cpu2: cpu@2 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
enable-method = "psci";
reg = <0x2>;
};
cpu3: cpu@3 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
enable-method = "psci";
reg = <0x3>;
};
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <0 120 8>,
<0 121 8>,
<0 122 8>,
<0 123 8>;
interrupt-affinity = <&cpu0>,
<&cpu1>,
<&cpu2>,
<&cpu3>;
interrupt-parent = <&intc>;
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
intc: intc@fffc1000 {
compatible = "arm,gic-400", "arm,cortex-a15-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x0 0xfffc1000 0x0 0x1000>,
<0x0 0xfffc2000 0x0 0x2000>,
<0x0 0xfffc4000 0x0 0x2000>,
<0x0 0xfffc6000 0x0 0x2000>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
device_type = "soc";
interrupt-parent = <&intc>;
ranges = <0 0 0 0xffffffff>;
clkmgr@ffd1000 {
compatible = "altr,clk-mgr";
reg = <0xffd10000 0x1000>;
};
gmac0: ethernet@ff800000 {
compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
reg = <0xff800000 0x2000>;
interrupts = <0 90 4>;
interrupt-names = "macirq";
mac-address = [00 00 00 00 00 00];
resets = <&rst EMAC0_RESET>;
reset-names = "stmmaceth";
status = "disabled";
};
gmac1: ethernet@ff802000 {
compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
reg = <0xff802000 0x2000>;
interrupts = <0 91 4>;
interrupt-names = "macirq";
mac-address = [00 00 00 00 00 00];
resets = <&rst EMAC1_RESET>;
reset-names = "stmmaceth";
status = "disabled";
};
gmac2: ethernet@ff804000 {
compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
reg = <0xff804000 0x2000>;
interrupts = <0 92 4>;
interrupt-names = "macirq";
mac-address = [00 00 00 00 00 00];
resets = <&rst EMAC2_RESET>;
reset-names = "stmmaceth";
status = "disabled";
};
gpio0: gpio@ffc03200 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dw-apb-gpio";
reg = <0xffc03200 0x100>;
resets = <&rst GPIO0_RESET>;
status = "disabled";
porta: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <24>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 110 4>;
};
};
gpio1: gpio@ffc03300 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dw-apb-gpio";
reg = <0xffc03300 0x100>;
resets = <&rst GPIO1_RESET>;
status = "disabled";
portb: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <24>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 111 4>;
};
};
i2c0: i2c@ffc02800 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0xffc02800 0x100>;
interrupts = <0 103 4>;
resets = <&rst I2C0_RESET>;
status = "disabled";
};
i2c1: i2c@ffc02900 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0xffc02900 0x100>;
interrupts = <0 104 4>;
resets = <&rst I2C1_RESET>;
status = "disabled";
};
i2c2: i2c@ffc02a00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0xffc02a00 0x100>;
interrupts = <0 105 4>;
resets = <&rst I2C2_RESET>;
status = "disabled";
};
i2c3: i2c@ffc02b00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0xffc02b00 0x100>;
interrupts = <0 106 4>;
resets = <&rst I2C3_RESET>;
status = "disabled";
};
i2c4: i2c@ffc02c00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0xffc02c00 0x100>;
interrupts = <0 107 4>;
resets = <&rst I2C4_RESET>;
status = "disabled";
};
mmc: dwmmc0@ff808000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "altr,socfpga-dw-mshc";
reg = <0xff808000 0x1000>;
interrupts = <0 96 4>;
fifo-depth = <0x400>;
resets = <&rst SDMMC_RESET>;
reset-names = "reset";
status = "disabled";
};
ocram: sram@ffe00000 {
compatible = "mmio-sram";
reg = <0xffe00000 0x100000>;
};
rst: rstmgr@ffd11000 {
#reset-cells = <1>;
compatible = "altr,rst-mgr";
reg = <0xffd11000 0x1000>;
altr,modrst-offset = <0x20>;
};
spi0: spi@ffda4000 {
compatible = "snps,dw-apb-ssi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xffda4000 0x1000>;
interrupts = <0 99 4>;
resets = <&rst SPIM0_RESET>;
reg-io-width = <4>;
num-chipselect = <4>;
bus-num = <0>;
status = "disabled";
};
spi1: spi@ffda5000 {
compatible = "snps,dw-apb-ssi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xffda5000 0x1000>;
interrupts = <0 100 4>;
resets = <&rst SPIM1_RESET>;
reg-io-width = <4>;
num-chipselect = <4>;
bus-num = <0>;
status = "disabled";
};
sysmgr: sysmgr@ffd12000 {
compatible = "altr,sys-mgr", "syscon";
reg = <0xffd12000 0x1000>;
};
/* Local timer */
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 0xf08>,
<1 14 0xf08>,
<1 11 0xf08>,
<1 10 0xf08>;
};
timer0: timer0@ffc03000 {
compatible = "snps,dw-apb-timer";
interrupts = <0 113 4>;
reg = <0xffc03000 0x100>;
};
timer1: timer1@ffc03100 {
compatible = "snps,dw-apb-timer";
interrupts = <0 114 4>;
reg = <0xffc03100 0x100>;
};
timer2: timer2@ffd00000 {
compatible = "snps,dw-apb-timer";
interrupts = <0 115 4>;
reg = <0xffd00000 0x100>;
};
timer3: timer3@ffd00100 {
compatible = "snps,dw-apb-timer";
interrupts = <0 116 4>;
reg = <0xffd00100 0x100>;
};
uart0: serial0@ffc02000 {
compatible = "snps,dw-apb-uart";
reg = <0xffc02000 0x100>;
interrupts = <0 108 4>;
reg-shift = <2>;
reg-io-width = <4>;
resets = <&rst UART0_RESET>;
status = "disabled";
};
uart1: serial1@ffc02100 {
compatible = "snps,dw-apb-uart";
reg = <0xffc02100 0x100>;
interrupts = <0 109 4>;
reg-shift = <2>;
reg-io-width = <4>;
resets = <&rst UART1_RESET>;
status = "disabled";
};
usbphy0: usbphy@0 {
#phy-cells = <0>;
compatible = "usb-nop-xceiv";
status = "okay";
};
usb0: usb@ffb00000 {
compatible = "snps,dwc2";
reg = <0xffb00000 0x40000>;
interrupts = <0 93 4>;
phys = <&usbphy0>;
phy-names = "usb2-phy";
resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
reset-names = "dwc2", "dwc2-ecc";
status = "disabled";
};
usb1: usb@ffb40000 {
compatible = "snps,dwc2";
reg = <0xffb40000 0x40000>;
interrupts = <0 94 4>;
phys = <&usbphy0>;
phy-names = "usb2-phy";
resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
reset-names = "dwc2", "dwc2-ecc";
status = "disabled";
};
watchdog0: watchdog@ffd00200 {
compatible = "snps,dw-wdt";
reg = <0xffd00200 0x100>;
interrupts = <0 117 4>;
resets = <&rst WATCHDOG0_RESET>;
status = "disabled";
};
watchdog1: watchdog@ffd00300 {
compatible = "snps,dw-wdt";
reg = <0xffd00300 0x100>;
interrupts = <0 118 4>;
resets = <&rst WATCHDOG1_RESET>;
status = "disabled";
};
watchdog2: watchdog@ffd00400 {
compatible = "snps,dw-wdt";
reg = <0xffd00400 0x100>;
interrupts = <0 125 4>;
resets = <&rst WATCHDOG2_RESET>;
status = "disabled";
};
watchdog3: watchdog@ffd00500 {
compatible = "snps,dw-wdt";
reg = <0xffd00500 0x100>;
interrupts = <0 126 4>;
resets = <&rst WATCHDOG3_RESET>;
status = "disabled";
};
};
};

View File

@@ -0,0 +1,92 @@
/*
* Copyright (C) 2018 Intel Corporation
*
* SPDX-License-Identifier: GPL-2.0
*/
#include "socfpga_stratix10.dtsi"
/ {
model = "SoCFPGA Stratix 10 SoCDK";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
leds {
compatible = "gpio-leds";
hps0 {
label = "hps_led0";
gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
};
hps1 {
label = "hps_led1";
gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
};
hps2 {
label = "hps_led2";
gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
};
};
memory {
device_type = "memory";
/* We expect the bootloader to fill in the reg */
reg = <0 0 0 0>;
};
};
&gpio1 {
status = "okay";
};
&gmac0 {
status = "okay";
phy-mode = "rgmii";
phy-handle = <&phy0>;
max-frame-size = <3800>;
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy0: ethernet-phy@0 {
reg = <4>;
txd0-skew-ps = <0>; /* -420ps */
txd1-skew-ps = <0>; /* -420ps */
txd2-skew-ps = <0>; /* -420ps */
txd3-skew-ps = <0>; /* -420ps */
rxd0-skew-ps = <420>; /* 0ps */
rxd1-skew-ps = <420>; /* 0ps */
rxd2-skew-ps = <420>; /* 0ps */
rxd3-skew-ps = <420>; /* 0ps */
txen-skew-ps = <0>; /* -420ps */
txc-skew-ps = <1860>; /* 960ps */
rxdv-skew-ps = <420>; /* 0ps */
rxc-skew-ps = <1680>; /* 780ps */
};
};
};
&mmc {
status = "okay";
cap-sd-highspeed;
broken-cd;
bus-width = <4>;
};
&uart0 {
status = "okay";
};
&usb0 {
status = "okay";
};

View File

@@ -1,14 +1,13 @@
/*
* Device Tree Source for UniPhier LD11 Global Board
*
* Copyright (C) 2016-2017 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
* Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Device Tree Source for UniPhier LD11 Global Board
//
// Copyright (C) 2016-2017 Socionext Inc.
// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
// Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
/dts-v1/;
#include <dt-bindings/gpio/uniphier-gpio.h>
#include "uniphier-ld11.dtsi"
/ {
@@ -37,6 +36,53 @@
device_type = "memory";
reg = <0 0x80000000 0 0x40000000>;
};
dvdd_reg: reg-fixed {
compatible = "regulator-fixed";
regulator-name = "DVDD";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
amp_vcc_reg: reg-fixed {
compatible = "regulator-fixed";
regulator-name = "AMP_VCC";
regulator-min-microvolt = <24000000>;
regulator-max-microvolt = <24000000>;
};
sound {
compatible = "audio-graph-card";
label = "UniPhier LD11";
widgets = "Headphone", "Headphone Jack";
dais = <&i2s_port2
&i2s_port3
&i2s_port4
&spdif_port0
&comp_spdif_port0>;
};
spdif-out {
compatible = "linux,spdif-dit";
#sound-dai-cells = <0>;
port@0 {
spdif_tx: endpoint {
remote-endpoint = <&spdif_hiecout1>;
};
};
};
comp-spdif-out {
compatible = "linux,spdif-dit";
#sound-dai-cells = <0>;
port@0 {
comp_spdif_tx: endpoint {
remote-endpoint = <&comp_spdif_hiecout1>;
};
};
};
};
&serial0 {
@@ -47,9 +93,43 @@
status = "okay";
};
&i2s_hpcmout1 {
dai-format = "i2s";
remote-endpoint = <&tas_speaker>;
};
&spdif_hiecout1 {
remote-endpoint = <&spdif_tx>;
};
&comp_spdif_hiecout1 {
remote-endpoint = <&comp_spdif_tx>;
};
&i2c0 {
status = "okay";
tas5707a@1d {
compatible = "ti,tas5711";
reg = <0x1d>;
reset-gpios = <&gpio UNIPHIER_GPIO_PORT(23, 4) GPIO_ACTIVE_LOW>;
pdn-gpios = <&gpio UNIPHIER_GPIO_PORT(23, 5) GPIO_ACTIVE_LOW>;
#sound-dai-cells = <0>;
AVDD-supply = <&dvdd_reg>;
DVDD-supply = <&dvdd_reg>;
PVDD_A-supply = <&amp_vcc_reg>;
PVDD_B-supply = <&amp_vcc_reg>;
PVDD_C-supply = <&amp_vcc_reg>;
PVDD_D-supply = <&amp_vcc_reg>;
port@0 {
tas_speaker: endpoint {
dai-format = "i2s";
remote-endpoint = <&i2s_hpcmout1>;
};
};
};
eeprom@50 {
compatible = "st,24c64", "atmel,24c64", "i2c-eeprom";
reg = <0x50>;
@@ -69,6 +149,17 @@
status = "okay";
};
&eth {
status = "okay";
phy-handle = <&ethphy>;
};
&mdio {
ethphy: ethphy@1 {
reg = <1>;
};
};
&nand {
status = "okay";
};

View File

@@ -1,11 +1,9 @@
/*
* Device Tree Source for UniPhier LD11 Reference Board
*
* Copyright (C) 2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Device Tree Source for UniPhier LD11 Reference Board
//
// Copyright (C) 2016 Socionext Inc.
// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
/dts-v1/;
#include "uniphier-ld11.dtsi"
@@ -70,3 +68,14 @@
&usb2 {
status = "okay";
};
&eth {
status = "okay";
phy-handle = <&ethphy>;
};
&mdio {
ethphy: ethphy@1 {
reg = <1>;
};
};

View File

@@ -1,11 +1,9 @@
/*
* Device Tree Source for UniPhier LD11 SoC
*
* Copyright (C) 2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Device Tree Source for UniPhier LD11 SoC
//
// Copyright (C) 2016 Socionext Inc.
// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/gpio/uniphier-gpio.h>
@@ -191,6 +189,92 @@
<21 217 3>;
};
audio@56000000 {
compatible = "socionext,uniphier-ld11-aio";
reg = <0x56000000 0x80000>;
interrupts = <0 144 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_aout1>,
<&pinctrl_aoutiec1>;
clock-names = "aio";
clocks = <&sys_clk 40>;
reset-names = "aio";
resets = <&sys_rst 40>;
#sound-dai-cells = <1>;
socionext,syscon = <&soc_glue>;
i2s_port0: port@0 {
i2s_hdmi: endpoint {
};
};
i2s_port1: port@1 {
i2s_pcmin2: endpoint {
};
};
i2s_port2: port@2 {
i2s_line: endpoint {
dai-format = "i2s";
remote-endpoint = <&evea_line>;
};
};
i2s_port3: port@3 {
i2s_hpcmout1: endpoint {
};
};
i2s_port4: port@4 {
i2s_hp: endpoint {
dai-format = "i2s";
remote-endpoint = <&evea_hp>;
};
};
spdif_port0: port@5 {
spdif_hiecout1: endpoint {
};
};
src_port0: port@6 {
i2s_epcmout2: endpoint {
};
};
src_port1: port@7 {
i2s_epcmout3: endpoint {
};
};
comp_spdif_port0: port@8 {
comp_spdif_hiecout1: endpoint {
};
};
};
codec@57900000 {
compatible = "socionext,uniphier-evea";
reg = <0x57900000 0x1000>;
clock-names = "evea", "exiv";
clocks = <&sys_clk 41>, <&sys_clk 42>;
reset-names = "evea", "exiv", "adamv";
resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>;
#sound-dai-cells = <1>;
port@0 {
evea_line: endpoint {
remote-endpoint = <&i2s_line>;
};
};
port@1 {
evea_hp: endpoint {
remote-endpoint = <&i2s_hp>;
};
};
};
adamv@57920000 {
compatible = "socionext,uniphier-ld11-adamv",
"simple-mfd", "syscon";
@@ -400,7 +484,7 @@
};
};
soc-glue@5f800000 {
soc_glue: soc-glue@5f800000 {
compatible = "socionext,uniphier-ld11-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
@@ -464,6 +548,22 @@
};
};
eth: ethernet@65000000 {
compatible = "socionext,uniphier-ld11-ave4";
status = "disabled";
reg = <0x65000000 0x8500>;
interrupts = <0 66 4>;
clocks = <&sys_clk 6>;
resets = <&sys_rst 6>;
phy-mode = "rmii";
local-mac-address = [00 00 00 00 00 00];
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
};
};
nand: nand@68000000 {
compatible = "socionext,uniphier-denali-nand-v5b";
status = "disabled";
@@ -479,3 +579,12 @@
};
#include "uniphier-pinctrl.dtsi"
&pinctrl_aoutiec1 {
drive-strength = <4>; /* default: 4mA */
ao1arc {
pins = "AO1ARC";
drive-strength = <8>; /* 8mA */
};
};

View File

@@ -1,14 +1,13 @@
/*
* Device Tree Source for UniPhier LD20 Global Board
*
* Copyright (C) 2015-2017 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
* Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Device Tree Source for UniPhier LD20 Global Board
//
// Copyright (C) 2015-2017 Socionext Inc.
// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
// Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
/dts-v1/;
#include <dt-bindings/gpio/uniphier-gpio.h>
#include "uniphier-ld20.dtsi"
/ {
@@ -37,6 +36,53 @@
device_type = "memory";
reg = <0 0x80000000 0 0xc0000000>;
};
dvdd_reg: reg-fixed {
compatible = "regulator-fixed";
regulator-name = "DVDD";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
amp_vcc_reg: reg-fixed {
compatible = "regulator-fixed";
regulator-name = "AMP_VCC";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
sound {
compatible = "audio-graph-card";
label = "UniPhier LD20";
widgets = "Headphone", "Headphone Jack";
dais = <&i2s_port2
&i2s_port3
&i2s_port4
&spdif_port0
&comp_spdif_port0>;
};
spdif-out {
compatible = "linux,spdif-dit";
#sound-dai-cells = <0>;
port@0 {
spdif_tx: endpoint {
remote-endpoint = <&spdif_hiecout1>;
};
};
};
comp-spdif-out {
compatible = "linux,spdif-dit";
#sound-dai-cells = <0>;
port@0 {
comp_spdif_tx: endpoint {
remote-endpoint = <&comp_spdif_hiecout1>;
};
};
};
};
&serial0 {
@@ -47,8 +93,55 @@
status = "okay";
};
&i2s_hpcmout1 {
dai-format = "i2s";
remote-endpoint = <&tas_speaker>;
};
&spdif_hiecout1 {
remote-endpoint = <&spdif_tx>;
};
&comp_spdif_hiecout1 {
remote-endpoint = <&comp_spdif_tx>;
};
&i2c0 {
status = "okay";
tas5707@1b {
compatible = "ti,tas5711";
reg = <0x1b>;
reset-gpios = <&gpio UNIPHIER_GPIO_PORT(0, 0) GPIO_ACTIVE_LOW>;
pdn-gpios = <&gpio UNIPHIER_GPIO_PORT(0, 1) GPIO_ACTIVE_LOW>;
#sound-dai-cells = <0>;
AVDD-supply = <&dvdd_reg>;
DVDD-supply = <&dvdd_reg>;
PVDD_A-supply = <&amp_vcc_reg>;
PVDD_B-supply = <&amp_vcc_reg>;
PVDD_C-supply = <&amp_vcc_reg>;
PVDD_D-supply = <&amp_vcc_reg>;
port@0 {
tas_speaker: endpoint {
dai-format = "i2s";
remote-endpoint = <&i2s_hpcmout1>;
};
};
};
};
&eth {
status = "okay";
phy-mode = "rmii";
pinctrl-0 = <&pinctrl_ether_rmii>;
phy-handle = <&ethphy>;
};
&mdio {
ethphy: ethphy@1 {
reg = <1>;
};
};
&nand {

View File

@@ -1,11 +1,9 @@
/*
* Device Tree Source for UniPhier LD20 Reference Board
*
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Device Tree Source for UniPhier LD20 Reference Board
//
// Copyright (C) 2015-2016 Socionext Inc.
// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
/dts-v1/;
#include "uniphier-ld20.dtsi"
@@ -58,3 +56,14 @@
&i2c0 {
status = "okay";
};
&eth {
status = "okay";
phy-handle = <&ethphy>;
};
&mdio {
ethphy: ethphy@0 {
reg = <0>;
};
};

View File

@@ -1,11 +1,9 @@
/*
* Device Tree Source for UniPhier LD20 SoC
*
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Device Tree Source for UniPhier LD20 SoC
//
// Copyright (C) 2015-2016 Socionext Inc.
// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/gpio/uniphier-gpio.h>
@@ -291,6 +289,92 @@
<21 217 3>;
};
audio@56000000 {
compatible = "socionext,uniphier-ld20-aio";
reg = <0x56000000 0x80000>;
interrupts = <0 144 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_aout1>,
<&pinctrl_aoutiec1>;
clock-names = "aio";
clocks = <&sys_clk 40>;
reset-names = "aio";
resets = <&sys_rst 40>;
#sound-dai-cells = <1>;
socionext,syscon = <&soc_glue>;
i2s_port0: port@0 {
i2s_hdmi: endpoint {
};
};
i2s_port1: port@1 {
i2s_pcmin2: endpoint {
};
};
i2s_port2: port@2 {
i2s_line: endpoint {
dai-format = "i2s";
remote-endpoint = <&evea_line>;
};
};
i2s_port3: port@3 {
i2s_hpcmout1: endpoint {
};
};
i2s_port4: port@4 {
i2s_hp: endpoint {
dai-format = "i2s";
remote-endpoint = <&evea_hp>;
};
};
spdif_port0: port@5 {
spdif_hiecout1: endpoint {
};
};
src_port0: port@6 {
i2s_epcmout2: endpoint {
};
};
src_port1: port@7 {
i2s_epcmout3: endpoint {
};
};
comp_spdif_port0: port@8 {
comp_spdif_hiecout1: endpoint {
};
};
};
codec@57900000 {
compatible = "socionext,uniphier-evea";
reg = <0x57900000 0x1000>;
clock-names = "evea", "exiv";
clocks = <&sys_clk 41>, <&sys_clk 42>;
reset-names = "evea", "exiv", "adamv";
resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>;
#sound-dai-cells = <1>;
port@0 {
evea_line: endpoint {
remote-endpoint = <&i2s_line>;
};
};
port@1 {
evea_hp: endpoint {
remote-endpoint = <&i2s_hp>;
};
};
};
adamv@57920000 {
compatible = "socionext,uniphier-ld20-adamv",
"simple-mfd", "syscon";
@@ -460,7 +544,7 @@
cap-sd-highspeed;
};
soc-glue@5f800000 {
soc_glue: soc-glue@5f800000 {
compatible = "socionext,uniphier-ld20-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
@@ -531,6 +615,24 @@
};
};
eth: ethernet@65000000 {
compatible = "socionext,uniphier-ld20-ave4";
status = "disabled";
reg = <0x65000000 0x8500>;
interrupts = <0 66 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ether_rgmii>;
clocks = <&sys_clk 6>;
resets = <&sys_rst 6>;
phy-mode = "rgmii";
local-mac-address = [00 00 00 00 00 00];
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
};
};
usb: usb@65b00000 {
compatible = "socionext,uniphier-ld20-dwc3";
reg = <0x65b00000 0x1000>;
@@ -564,3 +666,21 @@
};
#include "uniphier-pinctrl.dtsi"
&pinctrl_aout1 {
drive-strength = <4>; /* default: 3.5mA */
ao1dacck {
pins = "AO1DACCK";
drive-strength = <5>; /* 5mA */
};
};
&pinctrl_aoutiec1 {
drive-strength = <4>; /* default: 3.5mA */
ao1arc {
pins = "AO1ARC";
drive-strength = <11>; /* 11mA */
};
};

View File

@@ -1,11 +1,9 @@
/*
* Device Tree Source for UniPhier LD4 Reference Board
*
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Device Tree Source for UniPhier LD4 Reference Board
//
// Copyright (C) 2015-2016 Socionext Inc.
// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
/dts-v1/;
#include "uniphier-ld4.dtsi"

View File

@@ -1,11 +1,9 @@
/*
* Device Tree Source for UniPhier LD4 SoC
*
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Device Tree Source for UniPhier LD4 SoC
//
// Copyright (C) 2015-2016 Socionext Inc.
// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
#include <dt-bindings/gpio/uniphier-gpio.h>

View File

@@ -1,11 +1,9 @@
/*
* Device Tree Source for UniPhier LD6b Reference Board
*
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Device Tree Source for UniPhier LD6b Reference Board
//
// Copyright (C) 2015-2016 Socionext Inc.
// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
/dts-v1/;
#include "uniphier-ld6b.dtsi"
@@ -71,6 +69,17 @@
status = "okay";
};
&eth {
status = "okay";
phy-handle = <&ethphy>;
};
&mdio {
ethphy: ethphy@0 {
reg = <0>;
};
};
&usb0 {
status = "okay";
};

View File

@@ -1,11 +1,9 @@
/*
* Device Tree Source for UniPhier LD6b SoC
*
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Device Tree Source for UniPhier LD6b SoC
//
// Copyright (C) 2015-2016 Socionext Inc.
// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
/*
* LD6b consists of two silicon dies: D-chip and A-chip.

View File

@@ -1,11 +1,9 @@
/*
* Device Tree Source for UniPhier SoCs default pinctrl settings
*
* Copyright (C) 2015-2017 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Device Tree Source for UniPhier SoCs default pinctrl settings
//
// Copyright (C) 2015-2017 Socionext Inc.
// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
&pinctrl {
pinctrl_aout: aout {
@@ -13,6 +11,46 @@
function = "aout";
};
pinctrl_ain1: ain1 {
groups = "ain1";
function = "ain1";
};
pinctrl_ain2: ain2 {
groups = "ain2";
function = "ain2";
};
pinctrl_ainiec1: ainiec1 {
groups = "ainiec1";
function = "ainiec1";
};
pinctrl_aout1: aout1 {
groups = "aout1";
function = "aout1";
};
pinctrl_aout2: aout2 {
groups = "aout2";
function = "aout2";
};
pinctrl_aout3: aout3 {
groups = "aout3";
function = "aout3";
};
pinctrl_aoutiec1: aoutiec1 {
groups = "aoutiec1";
function = "aoutiec1";
};
pinctrl_aoutiec2: aoutiec2 {
groups = "aoutiec2";
function = "aoutiec2";
};
pinctrl_emmc: emmc {
groups = "emmc", "emmc_dat8";
function = "emmc";
@@ -38,6 +76,16 @@
function = "ether_rmii";
};
pinctrl_ether1_rgmii: ether1-rgmii {
groups = "ether1_rgmii";
function = "ether1_rgmii";
};
pinctrl_ether1_rmii: ether1-rmii {
groups = "ether1_rmii";
function = "ether1_rmii";
};
pinctrl_i2c0: i2c0 {
groups = "i2c0";
function = "i2c0";

View File

@@ -1,11 +1,9 @@
/*
* Device Tree Source for UniPhier Pro4 Ace Board
*
* Copyright (C) 2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Device Tree Source for UniPhier Pro4 Ace Board
//
// Copyright (C) 2016 Socionext Inc.
// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
/dts-v1/;
#include "uniphier-pro4.dtsi"
@@ -83,6 +81,17 @@
status = "okay";
};
&eth {
status = "okay";
phy-handle = <&ethphy>;
};
&mdio {
ethphy: ethphy@1 {
reg = <1>;
};
};
&usb2 {
status = "okay";
};

View File

@@ -1,11 +1,9 @@
/*
* Device Tree Source for UniPhier Pro4 Reference Board
*
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Device Tree Source for UniPhier Pro4 Reference Board
//
// Copyright (C) 2015-2016 Socionext Inc.
// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
/dts-v1/;
#include "uniphier-pro4.dtsi"
@@ -84,6 +82,17 @@
status = "okay";
};
&eth {
status = "okay";
phy-handle = <&ethphy>;
};
&mdio {
ethphy: ethphy@0 {
reg = <0>;
};
};
&usb0 {
status = "okay";
};

View File

@@ -1,11 +1,9 @@
/*
* Device Tree Source for UniPhier Pro4 Sanji Board
*
* Copyright (C) 2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Device Tree Source for UniPhier Pro4 Sanji Board
//
// Copyright (C) 2016 Socionext Inc.
// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
/dts-v1/;
#include "uniphier-pro4.dtsi"
@@ -78,6 +76,17 @@
status = "okay";
};
&eth {
status = "okay";
phy-handle = <&ethphy>;
};
&mdio {
ethphy: ethphy@1 {
reg = <1>;
};
};
&usb2 {
status = "okay";
};

View File

@@ -1,11 +1,9 @@
/*
* Device Tree Source for UniPhier Pro4 SoC
*
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Device Tree Source for UniPhier Pro4 SoC
//
// Copyright (C) 2015-2016 Socionext Inc.
// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
#include <dt-bindings/gpio/uniphier-gpio.h>
@@ -422,6 +420,24 @@
};
};
eth: ethernet@65000000 {
compatible = "socionext,uniphier-pro4-ave4";
status = "disabled";
reg = <0x65000000 0x8500>;
interrupts = <0 66 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ether_rgmii>;
clocks = <&sys_clk 6>;
resets = <&sys_rst 6>;
phy-mode = "rgmii";
local-mac-address = [00 00 00 00 00 00];
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
};
};
usb0: usb@65b00000 {
compatible = "socionext,uniphier-pro4-dwc3";
status = "disabled";

View File

@@ -1,11 +1,9 @@
/*
* Device Tree Source for UniPhier Pro5 SoC
*
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Device Tree Source for UniPhier Pro5 SoC
//
// Copyright (C) 2015-2016 Socionext Inc.
// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
/ {
compatible = "socionext,uniphier-pro5";

View File

@@ -1,11 +1,9 @@
/*
* Device Tree Source for UniPhier PXs2 Gentil Board
*
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Device Tree Source for UniPhier PXs2 Gentil Board
//
// Copyright (C) 2015-2016 Socionext Inc.
// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
/dts-v1/;
#include "uniphier-pxs2.dtsi"
@@ -34,6 +32,12 @@
device_type = "memory";
reg = <0x80000000 0x80000000>;
};
sound {
compatible = "audio-graph-card";
label = "UniPhier PXs2";
dais = <&i2s_port2>;
};
};
&serial2 {
@@ -51,14 +55,43 @@
};
};
&i2s_aux {
dai-format = "i2s";
remote-endpoint = <&wm_speaker>;
};
&i2c2 {
status = "okay";
wm8960@1a {
compatible = "wlf,wm8960";
reg = <0x1a>;
#sound-dai-cells = <0>;
port@0 {
wm_speaker: endpoint {
dai-format = "i2s";
remote-endpoint = <&i2s_aux>;
};
};
};
};
&emmc {
status = "okay";
};
&eth {
status = "okay";
phy-handle = <&ethphy>;
};
&mdio {
ethphy: ethphy@1 {
reg = <1>;
};
};
&usb0 {
status = "okay";
};

View File

@@ -1,11 +1,9 @@
/*
* Device Tree Source for UniPhier PXs2 Vodka Board
*
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Device Tree Source for UniPhier PXs2 Vodka Board
//
// Copyright (C) 2015-2016 Socionext Inc.
// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
/dts-v1/;
#include "uniphier-pxs2.dtsi"
@@ -32,12 +30,49 @@
device_type = "memory";
reg = <0x80000000 0x80000000>;
};
sound {
compatible = "audio-graph-card";
label = "UniPhier PXs2";
dais = <&spdif_port0
&comp_spdif_port0>;
};
spdif-out {
compatible = "linux,spdif-dit";
#sound-dai-cells = <0>;
port@0 {
spdif_tx: endpoint {
remote-endpoint = <&spdif_hiecout1>;
};
};
};
comp-spdif-out {
compatible = "linux,spdif-dit";
#sound-dai-cells = <0>;
port@0 {
comp_spdif_tx: endpoint {
remote-endpoint = <&comp_spdif_hiecout1>;
};
};
};
};
&serial2 {
status = "okay";
};
&spdif_hiecout1 {
remote-endpoint = <&spdif_tx>;
};
&comp_spdif_hiecout1 {
remote-endpoint = <&comp_spdif_tx>;
};
&i2c0 {
status = "okay";
};
@@ -46,6 +81,17 @@
status = "okay";
};
&eth {
status = "okay";
phy-handle = <&ethphy>;
};
&mdio {
ethphy: ethphy@1 {
reg = <1>;
};
};
&usb0 {
status = "okay";
};

View File

@@ -1,11 +1,9 @@
/*
* Device Tree Source for UniPhier PXs2 SoC
*
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Device Tree Source for UniPhier PXs2 SoC
//
// Copyright (C) 2015-2016 Socionext Inc.
// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
#include <dt-bindings/gpio/uniphier-gpio.h>
#include <dt-bindings/thermal/thermal.h>
@@ -231,6 +229,61 @@
<21 217 3>;
};
audio@56000000 {
compatible = "socionext,uniphier-pxs2-aio";
reg = <0x56000000 0x80000>;
interrupts = <0 144 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ain1>,
<&pinctrl_ain2>,
<&pinctrl_ainiec1>,
<&pinctrl_aout2>,
<&pinctrl_aout3>,
<&pinctrl_aoutiec1>,
<&pinctrl_aoutiec2>;
clock-names = "aio";
clocks = <&sys_clk 40>;
reset-names = "aio";
resets = <&sys_rst 40>;
#sound-dai-cells = <1>;
socionext,syscon = <&soc_glue>;
i2s_port0: port@0 {
i2s_hdmi: endpoint {
};
};
i2s_port1: port@1 {
i2s_line: endpoint {
};
};
i2s_port2: port@2 {
i2s_aux: endpoint {
};
};
spdif_port0: port@3 {
spdif_hiecout1: endpoint {
};
};
spdif_port1: port@4 {
spdif_iecout1: endpoint {
};
};
comp_spdif_port0: port@5 {
comp_spdif_hiecout1: endpoint {
};
};
comp_spdif_port1: port@6 {
comp_spdif_iecout1: endpoint {
};
};
};
i2c0: i2c@58780000 {
compatible = "socionext,uniphier-fi2c";
status = "disabled";
@@ -405,7 +458,7 @@
sd-uhs-sdr50;
};
soc-glue@5f800000 {
soc_glue: soc-glue@5f800000 {
compatible = "socionext,uniphier-pxs2-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
@@ -485,6 +538,24 @@
};
};
eth: ethernet@65000000 {
compatible = "socionext,uniphier-pxs2-ave4";
status = "disabled";
reg = <0x65000000 0x8500>;
interrupts = <0 66 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ether_rgmii>;
clocks = <&sys_clk 6>;
resets = <&sys_rst 6>;
phy-mode = "rgmii";
local-mac-address = [00 00 00 00 00 00];
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
};
};
usb0: usb@65b00000 {
compatible = "socionext,uniphier-pxs2-dwc3";
status = "disabled";

View File

@@ -1,11 +1,9 @@
/*
* Device Tree Source for UniPhier PXs3 Reference Board
*
* Copyright (C) 2017 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Device Tree Source for UniPhier PXs3 Reference Board
//
// Copyright (C) 2017 Socionext Inc.
// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
/dts-v1/;
#include "uniphier-pxs3.dtsi"
@@ -77,6 +75,28 @@
status = "okay";
};
&eth0 {
status = "okay";
phy-handle = <&ethphy0>;
};
&mdio0 {
ethphy0: ethphy@0 {
reg = <0>;
};
};
&eth1 {
status = "okay";
phy-handle = <&ethphy1>;
};
&mdio1 {
ethphy1: ethphy@0 {
reg = <0>;
};
};
&usb0 {
status = "okay";
};

View File

@@ -1,11 +1,9 @@
/*
* Device Tree Source for UniPhier PXs3 SoC
*
* Copyright (C) 2017 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Device Tree Source for UniPhier PXs3 SoC
//
// Copyright (C) 2017 Socionext Inc.
// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/gpio/uniphier-gpio.h>
@@ -361,7 +359,7 @@
cap-sd-highspeed;
};
soc-glue@5f800000 {
soc_glue: soc-glue@5f800000 {
compatible = "socionext,uniphier-pxs3-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
@@ -425,6 +423,42 @@
};
};
eth0: ethernet@65000000 {
compatible = "socionext,uniphier-pxs3-ave4";
status = "disabled";
reg = <0x65000000 0x8500>;
interrupts = <0 66 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ether_rgmii>;
clocks = <&sys_clk 6>;
resets = <&sys_rst 6>;
phy-mode = "rgmii";
local-mac-address = [00 00 00 00 00 00];
mdio0: mdio {
#address-cells = <1>;
#size-cells = <0>;
};
};
eth1: ethernet@65200000 {
compatible = "socionext,uniphier-pxs3-ave4";
status = "disabled";
reg = <0x65200000 0x8500>;
interrupts = <0 67 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ether1_rgmii>;
clocks = <&sys_clk 7>;
resets = <&sys_rst 7>;
phy-mode = "rgmii";
local-mac-address = [00 00 00 00 00 00];
mdio1: mdio {
#address-cells = <1>;
#size-cells = <0>;
};
};
usb0: usb@65b00000 {
compatible = "socionext,uniphier-pxs3-dwc3";
status = "disabled";

View File

@@ -1,11 +1,9 @@
/*
* Device Tree Source for UniPhier Reference Daughter Board
*
* Copyright (C) 2015-2017 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Device Tree Source for UniPhier Reference Daughter Board
//
// Copyright (C) 2015-2017 Socionext Inc.
// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
&i2c0 {
eeprom@50 {

View File

@@ -1,11 +1,9 @@
/*
* Device Tree Source for UniPhier sLD8 Reference Board
*
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Device Tree Source for UniPhier sLD8 Reference Board
//
// Copyright (C) 2015-2016 Socionext Inc.
// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
/dts-v1/;
#include "uniphier-sld8.dtsi"

View File

@@ -1,11 +1,9 @@
/*
* Device Tree Source for UniPhier sLD8 SoC
*
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Device Tree Source for UniPhier sLD8 SoC
//
// Copyright (C) 2015-2016 Socionext Inc.
// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
#include <dt-bindings/gpio/uniphier-gpio.h>

View File

@@ -1,11 +1,9 @@
/*
* Device Tree Source for UniPhier Support Card (Expansion Board)
*
* Copyright (C) 2015-2017 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Device Tree Source for UniPhier Support Card (Expansion Board)
//
// Copyright (C) 2015-2017 Socionext Inc.
// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
&system_bus {
status = "okay";

View File

@@ -14,22 +14,6 @@
u-boot,dm-pre-reloc;
};
mioctrl@59810000 {
u-boot,dm-pre-reloc;
clock {
u-boot,dm-pre-reloc;
};
};
sdctrl@59810000 {
u-boot,dm-pre-reloc;
clock {
u-boot,dm-pre-reloc;
};
};
soc-glue@5f800000 {
u-boot,dm-pre-reloc;

View File

@@ -9,8 +9,4 @@
int opos6ul_board_late_init(void);
#ifdef CONFIG_SPL_BUILD
void opos6ul_setup_uart_debug(void);
#endif
#endif

View File

@@ -85,6 +85,8 @@ static const struct mxs_pair mxs_boot_modes[] = {
#define MXS_BM_SDMMC1_3V3 0x0a
#define MXS_BM_SDMMC1_1V8 0x1a
#define MXS_SPL_DATA ((struct mxs_spl_data *)(CONFIG_SYS_TEXT_BASE - 0x200))
struct mxs_spl_data {
uint8_t boot_mode_idx;
uint32_t mem_dram_size;

View File

@@ -16,8 +16,6 @@
#include <asm/arch/mux_omap4.h>
#include <asm/ti-common/sys_proto.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
extern const struct emif_regs emif_regs_elpida_200_mhz_2cs;
extern const struct emif_regs emif_regs_elpida_380_mhz_1cs;

View File

@@ -16,8 +16,6 @@
#include <asm/arch/clock.h>
#include <asm/ti-common/sys_proto.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* Structure for Iodelay configuration registers.
* Theoretical max for g_delay is 21560 ps.

View File

@@ -147,10 +147,10 @@ typedef u64 iomux_v3_cfg_t;
#define PAD_CTL_ODE (1 << 11)
#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
#define PAD_CTL_SPEED_LOW (0 << 6)
#else
#if defined(CONFIG_MX6SL)
#define PAD_CTL_SPEED_LOW (1 << 6)
#else
#define PAD_CTL_SPEED_LOW (0 << 6)
#endif
#define PAD_CTL_SPEED_MED (2 << 6)
#define PAD_CTL_SPEED_HIGH (3 << 6)

View File

@@ -21,8 +21,6 @@
#include <common.h>
#include <command.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* ARMv7M does not support ARM instruction mode. However, the
* interworking BLX and BX instructions do encode the ARM/Thumb

View File

@@ -88,6 +88,7 @@ config TARGET_GURNARD
select DM_SPI
select DM_GPIO
select DM_ETH
select SPI
config TARGET_AT91SAM9261EK
bool "Atmel at91sam9261 reference board"
@@ -202,6 +203,7 @@ config TARGET_MA5D4EVK
select SUPPORT_SPL
select DM
select DM_SPI
select SPI
config TARGET_MEESC
bool "Support meesc"
@@ -225,6 +227,7 @@ config TARGET_TAURUS
select DM_SPI
select DM_GPIO
select DM_ETH
select SPI
config TARGET_SMARTWEB
bool "Support smartweb"
@@ -241,6 +244,7 @@ config TARGET_VINCO
select SUPPORT_SPL
select DM
select DM_SPI
select SPI
config TARGET_WB45N
bool "Support Laird WB45N"

View File

@@ -15,8 +15,6 @@
#include <asm/arch/clk.h>
#include <spl.h>
DECLARE_GLOBAL_DATA_PTR;
static void switch_to_main_crystal_osc(void)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;

View File

@@ -16,8 +16,6 @@
#include <spi_flash.h>
#include <mmc.h>
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SPL_LIBCOMMON_SUPPORT
void puts(const char *str)
{

View File

@@ -21,8 +21,6 @@
#define FSYS1_MMC0_DIV_MASK 0xff0f
#define FSYS1_MMC0_DIV_VAL 0x0701
DECLARE_GLOBAL_DATA_PTR;
struct arm_clk_ratios arm_clk_ratios[] = {
#ifdef CONFIG_EXYNOS5420
{

View File

@@ -8,8 +8,6 @@
#include <common.h>
#include <asm/armv8/mmu.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_EXYNOS7420
static struct mm_region exynos7420_mem_map[] = {
{

View File

@@ -16,8 +16,6 @@
#include <asm/arch/clock.h>
#include <mapmem.h>
DECLARE_GLOBAL_DATA_PTR;
/**
* blob_dek() - Encapsulate the DEK as a blob using CAM's Key
* @src: - Address of data to be encapsulated

View File

@@ -73,6 +73,10 @@ config MX6UL_OPOS6UL
select DM_MMC
select DM_THERMAL
select SUPPORT_SPL
select SPL_DM if SPL
select SPL_OF_CONTROL if SPL
select SPL_SEPARATE_BSS if SPL
select SPL_PINCTRL if SPL
config MX6ULL
select SYS_L2CACHE_OFF

View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2017 Armadeus Systems
* Copyright (C) 2018 Armadeus Systems
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -9,15 +9,12 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/mx6ul_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/io.h>
#include <common.h>
#include <environment.h>
#include <fsl_esdhc.h>
#include <mmc.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -138,12 +135,6 @@ int board_late_init(void)
return opos6ul_board_late_init();
}
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
return cfg->esdhc_base == USDHC1_BASE_ADDR;
}
int dram_init(void)
{
gd->ram_size = imx_ddr_size();
@@ -153,32 +144,9 @@ int dram_init(void)
#ifdef CONFIG_SPL_BUILD
#include <asm/arch/mx6-ddr.h>
#include <asm/arch/opos6ul.h>
#include <linux/libfdt.h>
#include <spl.h>
#define USDHC_PAD_CTRL ( \
PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST \
)
struct fsl_esdhc_cfg usdhc_cfg[1] = {
{USDHC1_BASE_ADDR, 0, 8},
};
static iomux_v3_cfg_t const usdhc1_pads[] = {
MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_READY_B__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_CE0_B__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_CE1_B__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_CLE__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
.grp_addds = 0x00000030,
.grp_ddrmode_ctl = 0x00020000,
@@ -240,11 +208,14 @@ static struct mx6_ddr3_cfg mem_ddr = {
.trasmin = 3750,
};
int board_mmc_init(bd_t *bis)
void board_boot_order(u32 *spl_boot_list)
{
imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
unsigned int bmode = readl(&src_base->sbmr2);
if (((bmode >> 24) & 0x03) == 0x01) /* Serial Downloader */
spl_boot_list[0] = BOOT_DEVICE_UART;
else
spl_boot_list[0] = spl_boot_device();
}
static void ccgr_init(void)
@@ -282,6 +253,11 @@ static void spl_dram_init(void)
mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
}
void spl_board_init(void)
{
preloader_console_init();
}
void board_init_f(ulong dummy)
{
ccgr_init();
@@ -292,10 +268,6 @@ void board_init_f(ulong dummy)
/* setup GP timer */
timer_init();
/* UART clocks enabled and gd valid - init serial console */
opos6ul_setup_uart_debug();
preloader_console_init();
/* DDR initialization */
spl_dram_init();
}

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@@ -9,6 +9,7 @@ choice
config TARGET_MX7ULP_EVK
bool "Support mx7ulp EVK board"
select SYS_ARCH_TIMER
endchoice

View File

@@ -12,8 +12,6 @@
#include <asm/arch/pcc.h>
#include <asm/arch/sys_proto.h>
DECLARE_GLOBAL_DATA_PTR;
#define PCC_CLKSRC_TYPES 2
#define PCC_CLKSRC_NUM 7

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@@ -12,8 +12,6 @@
#include <asm/arch/pcc.h>
#include <asm/arch/sys_proto.h>
DECLARE_GLOBAL_DATA_PTR;
scg_p scg1_regs = (scg_p)SCG1_RBASE;
static u32 scg_src_get_rate(enum scg_clk clksrc)

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@@ -14,8 +14,6 @@
#include <errno.h>
#include <linux/iopoll.h>
DECLARE_GLOBAL_DATA_PTR;
static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
static u32 decode_frac_pll(enum clk_root_src frac_pll)

View File

@@ -12,8 +12,6 @@
#include <asm/io.h>
#include <errno.h>
DECLARE_GLOBAL_DATA_PTR;
static struct ccm_reg *ccm_reg = (struct ccm_reg *)CCM_BASE_ADDR;
static struct clk_root_map root_array[] = {

View File

@@ -38,8 +38,6 @@ static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR;
#define GPTPR_PRESCALER24M_SHIFT 12
#define GPTPR_PRESCALER24M_MASK (0xF << GPTPR_PRESCALER24M_SHIFT)
DECLARE_GLOBAL_DATA_PTR;
static inline int gpt_has_clk_source_osc(void)
{
#if defined(CONFIG_MX6)

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@@ -14,8 +14,6 @@
#include <asm/arch/soc.h>
#include <asm/armv8/mmu.h>
DECLARE_GLOBAL_DATA_PTR;
/* Armada 3700 */
#define MVEBU_GPIO_NB_REG_BASE (MVEBU_REGISTER(0x13800))

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@@ -14,8 +14,6 @@
#include <asm/arch/soc.h>
#include <asm/armv8/mmu.h>
DECLARE_GLOBAL_DATA_PTR;
/* Armada 7k/8k */
#define MVEBU_RFU_BASE (MVEBU_REGISTER(0x6f0000))
#define RFU_GLOBAL_SW_RST (MVEBU_RFU_BASE + 0x84)

View File

@@ -8,8 +8,6 @@
#include <ahci.h>
#include <dm.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* Dummy implementation that can be overwritten by a board
* specific function

View File

@@ -11,8 +11,6 @@
#include <asm/io.h>
#include <asm/arch/soc.h>
DECLARE_GLOBAL_DATA_PTR;
#define TIMER_LOAD_VAL 0xffffffff
static int init_done __attribute__((section(".data"))) = 0;

View File

@@ -196,9 +196,10 @@ u32 spl_boot_mode(const u32 boot_device)
void spl_board_init(void)
{
#ifdef CONFIG_SPL_SERIAL_SUPPORT
/* Prepare console output */
preloader_console_init();
#endif
#if defined(CONFIG_SPL_NAND_SUPPORT) || defined(CONFIG_SPL_ONENAND_SUPPORT)
gpmc_init();
#endif

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@@ -28,8 +28,6 @@
#include <asm/omap_common.h>
#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
/* Declarations */
extern omap3_sysinfo sysinfo;
#ifndef CONFIG_SYS_L2CACHE_OFF

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@@ -21,8 +21,6 @@
#include <asm/arch/gpio.h>
#include <asm/omap_common.h>
DECLARE_GLOBAL_DATA_PTR;
u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;
static const struct gpio_bank gpio_bank_44xx[6] = {

View File

@@ -24,8 +24,6 @@
#include <asm/emif.h>
#include <asm/omap_common.h>
DECLARE_GLOBAL_DATA_PTR;
u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;
#ifndef CONFIG_DM_GPIO

View File

@@ -16,6 +16,7 @@ config TARGET_QEMU_ARM_32BIT
depends on ARCH_QEMU
select CPU_V7
select ARCH_SUPPORT_PSCI
select SYS_ARCH_TIMER
config TARGET_QEMU_ARM_64BIT
bool "Support qemu_arm64"

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