Prepare v2018.07-rc1

Signed-off-by: Tom Rini <trini@konsulko.com>

.gitignore

@@ -13,6 +13,7 @@
 *.su
 *.mod.c
 *.i
+*.lex.c
 *.lst
 *.order
 *.elf
@@ -20,6 +21,7 @@
 *.bin
 *.patch
 *.cfgtmp
+*.tab.[ch]
 
 # host programs on Cygwin
 *.exe
@@ -46,7 +48,6 @@ fit-dtb.blob
 #
 # Generated files
 #
-/LOG
 /spl/
 /tpl/
 /defconfig

.travis.yml

@@ -21,7 +21,6 @@ addons:
     - python-virtualenv
     - swig
     - libpython-dev
-    - gcc-powerpc-linux-gnu
     - iasl
     - grub-efi-ia32-bin
     - rpm2cpio
@@ -29,6 +28,11 @@ addons:
     - device-tree-compiler
     - lzop
 
+before_install:
+ - sudo add-apt-repository ppa:ubuntu-toolchain-r/test -y
+ - sudo apt-get update -q
+ - sudo apt-get install libisl15 -y
+
 install:
  # Clone uboot-test-hooks
  - git clone --depth=1 git://github.com/swarren/uboot-test-hooks.git /tmp/uboot-test-hooks
@@ -36,10 +40,8 @@ install:
  - ln -s travis-ci /tmp/uboot-test-hooks/py/`hostname`
  # prepare buildman environment
  - echo -e "[toolchain]\nroot = /usr" > ~/.buildman
- - echo -e "aarch64 = /tmp/gcc-linaro-6.3.1-2017.02-x86_64_aarch64-linux-gnu" >> ~/.buildman
- - echo -e "arm = /tmp/gcc-linaro-6.3.1-2017.02-x86_64_arm-linux-gnueabihf" >> ~/.buildman
  - echo -e "arc = /tmp/arc_gnu_2017.09_prebuilt_uclibc_le_archs_linux_install" >> ~/.buildman
- - echo -e "\n[toolchain-alias]\nsh = sh4\nopenrisc = or32" >> ~/.buildman
+ - echo -e "\n[toolchain-alias]\nsh = sh2\n" >> ~/.buildman
  - cat ~/.buildman
  - virtualenv /tmp/venv
  - . /tmp/venv/bin/activate
@@ -64,10 +66,10 @@ before_script:
   - if [[ "${TOOLCHAIN}" == *microblaze* ]]; then ./tools/buildman/buildman --fetch-arch microblaze ; fi
   - if [[ "${TOOLCHAIN}" == *mips* ]]; then ./tools/buildman/buildman --fetch-arch mips ; fi
   - if [[ "${TOOLCHAIN}" == *or32* ]]; then ./tools/buildman/buildman --fetch-arch or32 ; fi
-  - if [[ "${TOOLCHAIN}" == *sh4* ]]; then ./tools/buildman/buildman --fetch-arch sh4 ; fi
+  - if [[ "${TOOLCHAIN}" == *sh* ]]; then ./tools/buildman/buildman --fetch-arch sh2 ; fi
   - if [[ "${TOOLCHAIN}" == *x86_64* ]]; then
       ./tools/buildman/buildman --fetch-arch x86_64;
-      echo -e "\n[toolchain-prefix]\nx86 = ${HOME}/.buildman-toolchains/gcc-4.9.0-nolibc/x86_64-linux/bin/x86_64-linux-" >> ~/.buildman;
+      echo -e "\n[toolchain-prefix]\nx86 = ${HOME}/.buildman-toolchains/gcc-7.3.0-nolibc/x86_64-linux/bin/x86_64-linux-" >> ~/.buildman;
     fi
   - if [[ "${TOOLCHAIN}" == arc ]]; then
        wget https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases/download/arc-2017.09-release/arc_gnu_2017.09_prebuilt_uclibc_le_archs_linux_install.tar.gz &&
@@ -80,15 +82,14 @@ before_script:
     fi
   # If TOOLCHAIN is unset, we're on some flavour of ARM.
   - if [[ "${TOOLCHAIN}" == "" ]]; then
-       wget http://releases.linaro.org/components/toolchain/binaries/6.3-2017.02/aarch64-linux-gnu/gcc-linaro-6.3.1-2017.02-x86_64_aarch64-linux-gnu.tar.xz &&
-       wget http://releases.linaro.org/components/toolchain/binaries/6.3-2017.02/arm-linux-gnueabihf/gcc-linaro-6.3.1-2017.02-x86_64_arm-linux-gnueabihf.tar.xz &&
-       tar -C /tmp -xf gcc-linaro-6.3.1-2017.02-x86_64_aarch64-linux-gnu.tar.xz &&
-       tar -C /tmp -xf gcc-linaro-6.3.1-2017.02-x86_64_arm-linux-gnueabihf.tar.xz;
+       ./tools/buildman/buildman --fetch-arch arm &&
+       ./tools/buildman/buildman --fetch-arch aarch64;
     fi
+  - if [[ "${TOOLCHAIN}" == "powerpc" ]]; then ./tools/buildman/buildman --fetch-arch powerpc; fi
   - if [[ "${TOOLCHAIN}" == "riscv" ]]; then
-        wget https://github.com/PkmX/riscv-prebuilt-toolchains/releases/download/20180111/riscv32-unknown-elf-toolchain.tar.gz &&
-        tar -C /tmp -xf riscv32-unknown-elf-toolchain.tar.gz &&
-        echo -e "\n[toolchain-prefix]\nriscv = /tmp/riscv32-unknown-elf/bin/riscv32-unknown-elf-" >> ~/.buildman;
+        wget https://github.com/andestech/prebuilt/releases/download/20180530/riscv64-unknown-linux-gnu.tar.gz &&
+        tar -C /tmp -xf riscv64-unknown-linux-gnu.tar.gz &&
+        echo -e "\n[toolchain-prefix]\nriscv = /tmp/riscv64-unknown-linux-gnu/bin/riscv64-unknown-linux-gnu-" >> ~/.buildman;
     fi
   - if [[ "${QEMU_TARGET}" != "" ]]; then
        git clone git://git.qemu.org/qemu.git /tmp/qemu;
@@ -149,26 +150,16 @@ matrix:
         - BUILDMAN="arc"
           TOOLCHAIN="arc"
     - env:
-        - BUILDMAN="arm11"
-    - env:
-        - BUILDMAN="arm7"
-    - env:
-        - BUILDMAN="arm920t"
+        - BUILDMAN="arm11 arm7 arm920t arm946es"
     - env:
         - JOB="arm926ejs"
           BUILDMAN="arm926ejs -x mx,siemens,atmel"
-    - env:
-        - BUILDMAN="arm946es"
     - env:
         - BUILDMAN="atmel"
     - env:
         - BUILDMAN="aries"
     - env:
-        - JOB="Boundary Devices"
-          BUILDMAN="boundary"
-    - env:
-        - JOB="engicam"
-          BUILDMAN="engicam"
+          BUILDMAN="boundary engicam toradex"
     - env:
         - JOB="Freescale ARM32"
           BUILDMAN="freescale -x powerpc,m68k,aarch64"
@@ -184,9 +175,7 @@ matrix:
     - env:
         - BUILDMAN="k2"
     - env:
-        - BUILDMAN="samsung"
-    - env:
-        - BUILDMAN="socfpga"
+        - BUILDMAN="samsung socfpga"
     - env:
         - BUILDMAN="sun4i"
     - env:
@@ -203,12 +192,10 @@ matrix:
         - BUILDMAN="sun50i"
     - env:
         - JOB="Catch-all ARM"
-          BUILDMAN="arm -x arm11,arm7,arm9,aarch64,atmel,aries,freescale,kirkwood,mvebu,siemens,tegra,uniphier,mx,samsung,sunxi,am33xx,omap3,omap4,omap5,pxa,rockchip,toradex,socfpga,k2,xilinx"
+          BUILDMAN="arm -x arm11,arm7,arm9,aarch64,atmel,aries,freescale,kirkwood,mvebu,siemens,tegra,uniphier,mx,samsung,sunxi,am33xx,omap,pxa,rockchip,toradex,socfpga,k2,xilinx"
     - env:
         - BUILDMAN="sandbox x86"
           TOOLCHAIN="x86_64"
-    - env:
-        - BUILDMAN="toradex"
     - env:
         - BUILDMAN="kirkwood"
     - env:
@@ -226,27 +213,27 @@ matrix:
         - BUILDMAN="mips"
           TOOLCHAIN="mips"
     - env:
-        - BUILDMAN="mpc83xx"
+        - JOB="Non-Freescale PowerPC"
+          BUILDMAN="powerpc -x freescale"
+          TOOLCHAIN="powerpc"
     - env:
-        - BUILDMAN="mpc85xx -x freescale"
+        - BUILDMAN="mpc85xx&freescale -x t208xrdb -x t4qds -x t102* -x p1_p2_rdb_pc -x p1010rdb -x corenet_ds -x b4860qds -x bsc91*"
+          TOOLCHAIN="powerpc"
     - env:
-        - BUILDMAN="mpc85xx -x t208xrdb -x t4qds -x t102* -x p1_p2_rdb_pc -x p1010rdb -x corenet_ds -x b4860qds -x sbc8548 -x bsc91*"
+        - BUILDMAN="t208xrdb corenet_ds"
+          TOOLCHAIN="powerpc"
     - env:
-        - BUILDMAN="t208xrdb"
-    - env:
-        - BUILDMAN="t4qds"
+        - BUILDMAN="t4qds b4860qds mpc83xx&freescale mpc86xx&freescale"
+          TOOLCHAIN="powerpc"
     - env:
         - BUILDMAN="t102*"
+          TOOLCHAIN="powerpc"
     - env:
         - BUILDMAN="p1_p2_rdb_pc"
+          TOOLCHAIN="powerpc"
     - env:
-        - BUILDMAN="p1010rdb"
-    - env:
-        - BUILDMAN="corenet_ds b4860qds sbc8548 bsc91*"
-    - env:
-        - BUILDMAN="mpc86xx"
-    - env:
-        - BUILDMAN="mpc8xx"
+        - BUILDMAN="p1010rdb bsc91"
+          TOOLCHAIN="powerpc"
     - env:
         - BUILDMAN="siemens"
     - env:
@@ -256,21 +243,18 @@ matrix:
         - JOB="am33xx"
           BUILDMAN="am33xx -x siemens"
     - env:
-        - BUILDMAN="omap3"
-    - env:
-        - BUILDMAN="omap4"
-    - env:
-        - BUILDMAN="omap5"
+        - BUILDMAN="omap"
     - env:
         - BUILDMAN="uniphier"
     - env:
-        - JOB="aarch64"
-          BUILDMAN="aarch64 -x tegra,freescale,mvebu,uniphier,sunxi,samsung,rockchip"
+        - JOB="Catch-all AArch64"
+          BUILDMAN="aarch64 -x tegra,freescale,mvebu,uniphier,sunxi,samsung,rockchip,xilinx"
     - env:
         - BUILDMAN="rockchip"
     - env:
-        - BUILDMAN="sh4"
-          TOOLCHAIN="sh4"
+        - JOB="sh"
+          BUILDMAN="sh -x arm"
+          TOOLCHAIN="sh"
     - env:
         - JOB="Xilinx (ARM)"
           BUILDMAN="xilinx -x microblaze"
@@ -376,6 +360,7 @@ matrix:
           TEST_PY_TEST_SPEC="not sleep"
           QEMU_TARGET="ppc-softmmu"
           BUILDMAN="^qemu-ppce500$"
+          TOOLCHAIN="powerpc"
     - env:
         - TEST_PY_BD="qemu-x86"
           TEST_PY_TEST_SPEC="not sleep"

Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt

@@ -0,0 +1,73 @@
+STMicroelectronics STM32 USB HS PHY controller
+
+The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI
+switch. It controls PHY configuration and status, and the UTMI+ switch that
+selects either OTG or HOST controller for the second PHY port. It also sets
+PLL configuration.
+
+USBPHYC
+      |_ PLL
+      |
+      |_ PHY port#1 _________________ HOST controller
+      |                    _                 |
+      |                  / 1|________________|
+      |_ PHY port#2 ----|   |________________
+      |                  \_0|                |
+      |_ UTMI switch_______|          OTG controller
+
+
+Phy provider node
+=================
+
+Required properties:
+- compatible: must be "st,stm32mp1-usbphyc"
+- reg: address and length of the usb phy control register set
+- clocks: phandle + clock specifier for the PLL phy clock
+- #address-cells: number of address cells for phys sub-nodes, must be <1>
+- #size-cells: number of size cells for phys sub-nodes, must be <0>
+
+Optional properties:
+- assigned-clocks: phandle + clock specifier for the PLL phy clock
+- assigned-clock-parents: the PLL phy clock parent
+- resets: phandle + reset specifier
+
+Required nodes: one sub-node per port the controller provides.
+
+Phy sub-nodes
+==============
+
+Required properties:
+- reg: phy port index
+- phy-supply: phandle to the regulator providing 3V3 power to the PHY,
+	      see phy-bindings.txt in the same directory.
+- vdda1v1-supply: phandle to the regulator providing 1V1 power to the PHY
+- vdda1v8-supply: phandle to the regulator providing 1V8 power to the PHY
+- #phy-cells: see phy-bindings.txt in the same directory, must be <0> for PHY
+  port#1 and must be <1> for PHY port#2, to select USB controller
+
+
+Example:
+		usbphyc: usb-phy@5a006000 {
+			compatible = "st,stm32mp1-usbphyc";
+			reg = <0x5a006000 0x1000>;
+			clocks = <&rcc_clk USBPHY_K>;
+			resets = <&rcc_rst USBPHY_R>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			usbphyc_port0: usb-phy@0 {
+				reg = <0>;
+				phy-supply = <&vdd_usb>;
+				vdda1v1-supply = <&reg11>;
+				vdda1v8-supply = <&reg18>
+				#phy-cells = <0>;
+			};
+
+			usbphyc_port1: usb-phy@1 {
+				reg = <1>;
+				phy-supply = <&vdd_usb>;
+				vdda1v1-supply = <&reg11>;
+				vdda1v8-supply = <&reg18>
+				#phy-cells = <1>;
+			};
+		};

Kconfig

@@ -305,6 +305,12 @@ config SPL_FIT
 	depends on SPL
 	select SPL_OF_LIBFDT
 
+config SPL_FIT_PRINT
+	bool "Support FIT printing within SPL"
+	depends on SPL_FIT
+	help
+	  Support printing the content of the fitImage in a verbose manner in SPL.
+
 config SPL_FIT_SIGNATURE
 	bool "Enable signature verification of FIT firmware within SPL"
 	depends on SPL_DM
@@ -322,6 +328,17 @@ config SPL_LOAD_FIT
 	  particular it can handle selecting from multiple device tree
 	  and passing the correct one to U-Boot.
 
+config SPL_LOAD_FIT_FULL
+	bool "Enable SPL loading U-Boot as a FIT"
+	select SPL_FIT
+	help
+	  Normally with the SPL framework a legacy image is generated as part
+	  of the build. This contains U-Boot along with information as to
+	  where it should be loaded. This option instead enables generation
+	  of a FIT (Flat Image Tree) which provides more flexibility. In
+	  particular it can handle selecting from multiple device tree
+	  and passing the correct one to U-Boot.
+
 config SPL_FIT_IMAGE_POST_PROCESS
 	bool "Enable post-processing of FIT artifacts after loading by the SPL"
 	depends on SPL_LOAD_FIT

Licenses/README

@@ -1,3 +1,5 @@
+SPDX-License-Identifier: GPL-2.0
+
   U-Boot is Free Software.  It is copyrighted by Wolfgang Denk and
 many others who contributed code (see the actual source code and the
 git commit messages for details).  You can redistribute U-Boot and/or
@@ -31,27 +33,107 @@ information, ...) which makes automatic processing a nightmare.
 
 To make this easier, such license headers in the source files will be
 replaced with a single line reference to Unique License Identifiers
-as defined by the Linux Foundation's SPDX project [1].  For example,
-in a source file the full "GPL v2.0 or later" header text will be
-replaced by a single line:
-
-	SPDX-License-Identifier:	GPL-2.0+
-
-Ideally, the license terms of all files in the source tree should be
-defined by such License Identifiers; in no case a file can contain
-more than one such License Identifier list.
+as defined by the Linux Foundation's SPDX project [1].
 
 If a "SPDX-License-Identifier:" line references more than one Unique
 License Identifier, then this means that the respective file can be
 used under the terms of either of these licenses, i. e. with
 
-	SPDX-License-Identifier:	GPL-2.0+	BSD-3-Clause
+	SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
 
 you can choose between GPL-2.0+ and BSD-3-Clause licensing.
 
 We use the SPDX Unique License Identifiers here; these are available
 at [2].
 
+License identifier syntax
+-------------------------
+
+1. Placement:
+
+   The SPDX license identifier in U-Boot files shall be added at the first
+   possible line in a file which can contain a comment.  For the majority
+   or files this is the first line, except for scripts which require the
+   '#!PATH_TO_INTERPRETER' in the first line.  For those scripts the SPDX
+   identifier goes into the second line.
+
+|
+
+2. Style:
+
+   The SPDX license identifier is added in form of a comment.  The comment
+   style depends on the file type::
+
+      C source:	// SPDX-License-Identifier: <SPDX License Expression>
+      C header:	/* SPDX-License-Identifier: <SPDX License Expression> */
+      ASM:	/* SPDX-License-Identifier: <SPDX License Expression> */
+      scripts:	# SPDX-License-Identifier: <SPDX License Expression>
+      .rst:	.. SPDX-License-Identifier: <SPDX License Expression>
+      .dts{i}:	// SPDX-License-Identifier: <SPDX License Expression>
+
+   If a specific tool cannot handle the standard comment style, then the
+   appropriate comment mechanism which the tool accepts shall be used. This
+   is the reason for having the "/\* \*/" style comment in C header
+   files. There was build breakage observed with generated .lds files where
+   'ld' failed to parse the C++ comment. This has been fixed by now, but
+   there are still older assembler tools which cannot handle C++ style
+   comments.
+
+|
+
+3. Syntax:
+
+   A <SPDX License Expression> is either an SPDX short form license
+   identifier found on the SPDX License List, or the combination of two
+   SPDX short form license identifiers separated by "WITH" when a license
+   exception applies. When multiple licenses apply, an expression consists
+   of keywords "AND", "OR" separating sub-expressions and surrounded by
+   "(", ")" .
+
+   License identifiers for licenses like [L]GPL with the 'or later' option
+   are constructed by using a "+" for indicating the 'or later' option.::
+
+      // SPDX-License-Identifier: GPL-2.0+
+      // SPDX-License-Identifier: LGPL-2.1+
+
+   WITH should be used when there is a modifier to a license needed.
+   For example, the linux kernel UAPI files use the expression::
+
+      // SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
+      // SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note
+
+   Other examples using WITH exceptions found in the linux kernel are::
+
+      // SPDX-License-Identifier: GPL-2.0 WITH mif-exception
+      // SPDX-License-Identifier: GPL-2.0+ WITH GCC-exception-2.0
+
+   Exceptions can only be used with particular License identifiers. The
+   valid License identifiers are listed in the tags of the exception text
+   file.
+
+   OR should be used if the file is dual licensed and only one license is
+   to be selected.  For example, some dtsi files are available under dual
+   licenses::
+
+      // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
+
+   Examples from U-Boot for license expressions in dual licensed files::
+
+      // SPDX-License-Identifier: GPL-2.0 OR MIT
+      // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+
+   AND should be used if the file has multiple licenses whose terms all
+   apply to use the file. For example, if code is inherited from another
+   project and permission has been given to put it in U-Boot, but the
+   original license terms need to remain in effect::
+
+      // SPDX-License-Identifier: (GPL-2.0 WITH Linux-syscall-note) AND MIT
+
+   Another other example where both sets of license terms need to be
+   adhered to is::
+
+      // SPDX-License-Identifier: GPL-1.0+ AND LGPL-2.1+
+
 [1] http://spdx.org/
 [2] http://spdx.org/licenses/
 

MAINTAINERS

@@ -60,6 +60,7 @@ S:	Maintained
 L:	uboot-snps-arc@synopsys.com
 T:	git git://git.denx.de/u-boot-arc.git
 F:	arch/arc/
+F:	board/synopsys/
 
 ARC HSDK CGU CLOCK
 M:	Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
@@ -135,6 +136,7 @@ S:	Maintained
 T:	git git://git.denx.de/u-boot-marvell.git
 F:	arch/arm/mach-kirkwood/
 F:	arch/arm/mach-mvebu/
+F:	drivers/ata/ahci_mvebu.c
 
 ARM MARVELL PXA
 M:	Marek Vasut <marex@denx.de>
@@ -204,6 +206,7 @@ M:	Patrick Delaunay <patrick.delaunay@st.com>
 S:	Maintained
 F:	arch/arm/mach-stm32mp
 F:	drivers/clk/clk_stm32mp1.c
+F:	drivers/misc/stm32mp_fuse.c
 F:	drivers/ram/stm32mp1/
 
 ARM STM STV0991
@@ -274,7 +277,7 @@ ARM ZYNQMP
 M:	Michal Simek <michal.simek@xilinx.com>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-microblaze.git
-F:	arch/arm/mach-zynq/
+F:	arch/arm/cpu/armv8/zynqmp/
 F:	drivers/clk/clk_zynqmp.c
 F:	drivers/fpga/zynqpl.c
 F:	drivers/gpio/zynq_gpio.c
@@ -288,12 +291,19 @@ F:	drivers/net/zynq_gem.c
 F:	drivers/serial/serial_zynq.c
 F:	drivers/spi/zynq_qspi.c
 F:	drivers/spi/zynq_spi.c
+F:	drivers/timer/cadence-ttc.c
 F:	drivers/usb/host/ehci-zynq.c
 F:	drivers/watchdog/cdns_wdt.c
 F:	include/zynqmppl.h
-F:	tools/zynqimage.c
+F:	tools/zynqmp*
 N:	zynqmp
 
+ARM ZYNQMP R5
+M:	Michal Simek <michal.simek@xilinx.com>
+S:	Maintained
+T:	git git://git.denx.de/u-boot-microblaze.git
+F:	arch/arm/mach-zynqmp-r5/
+
 BUILDMAN
 M:	Simon Glass <sjg@chromium.org>
 S:	Maintained
@@ -332,6 +342,7 @@ EFI PAYLOAD
 M:	Alexander Graf <agraf@suse.de>
 S:	Maintained
 T:	git git://github.com/agraf/u-boot.git
+F:	doc/DocBook/efi.tmpl
 F:	doc/README.uefi
 F:	doc/README.iscsi
 F:	include/efi*

Makefile

@@ -1,9 +1,9 @@
 # SPDX-License-Identifier: GPL-2.0+
 
 VERSION = 2018
-PATCHLEVEL = 05
+PATCHLEVEL = 07
 SUBLEVEL =
-EXTRAVERSION =
+EXTRAVERSION = -rc1
 NAME =
 
 # *DOCUMENTATION*
@@ -258,6 +258,15 @@ HOSTCFLAGS   = -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer \
 		$(if $(CONFIG_TOOLS_DEBUG),-g)
 HOSTCXXFLAGS = -O2
 
+# With the move to GCC 6, we have implicitly upgraded our language
+# standard to GNU11 (see https://gcc.gnu.org/gcc-5/porting_to.html).
+# Some Linux distributions (including RHEL7, SLES13, Debian 8) still
+# have older compilers as their default, so we make it explicit for
+# these that our host tools are GNU11 (i.e. C11 w/ GNU extensions).
+ifeq ($(HOSTOS),linux)
+HOSTCFLAGS += --std=gnu11
+endif
+
 ifeq ($(HOSTOS),cygwin)
 HOSTCFLAGS	+= -ansi
 endif
@@ -344,9 +353,13 @@ LDR		= $(CROSS_COMPILE)ldr
 STRIP		= $(CROSS_COMPILE)strip
 OBJCOPY		= $(CROSS_COMPILE)objcopy
 OBJDUMP		= $(CROSS_COMPILE)objdump
+LEX		= flex
+YACC		= bison
 AWK		= awk
 PERL		= perl
 PYTHON		?= python
+PYTHON2		= python2
+PYTHON3		= python3
 DTC		?= $(objtree)/scripts/dtc/dtc
 CHECK		= sparse
 
@@ -369,7 +382,7 @@ export VERSION PATCHLEVEL SUBLEVEL UBOOTRELEASE UBOOTVERSION
 export ARCH CPU BOARD VENDOR SOC CPUDIR BOARDDIR
 export CONFIG_SHELL HOSTCC HOSTCFLAGS HOSTLDFLAGS CROSS_COMPILE AS LD CC
 export CPP AR NM LDR STRIP OBJCOPY OBJDUMP
-export MAKE AWK PERL PYTHON
+export MAKE LEX YACC AWK PERL PYTHON PYTHON2 PYTHON3
 export HOSTCXX HOSTCXXFLAGS CHECK CHECKFLAGS DTC DTC_FLAGS
 
 export KBUILD_CPPFLAGS NOSTDINC_FLAGS UBOOTINCLUDE OBJCOPYFLAGS LDFLAGS
@@ -505,7 +518,7 @@ $(KCONFIG_CONFIG) include/config/auto.conf.cmd: ;
 # if auto.conf.cmd is missing then we are probably in a cleaned tree so
 # we execute the config step to be sure to catch updated Kconfig files
 include/config/%.conf: $(KCONFIG_CONFIG) include/config/auto.conf.cmd
-	$(Q)$(MAKE) -f $(srctree)/Makefile silentoldconfig
+	$(Q)$(MAKE) -f $(srctree)/Makefile syncconfig
 	@# If the following part fails, include/config/auto.conf should be
 	@# deleted so "make silentoldconfig" will be re-run on the next build.
 	$(Q)$(MAKE) -f $(srctree)/scripts/Makefile.autoconf || \
@@ -1608,10 +1621,12 @@ clean: $(clean-dirs)
 		\( -name '*.[oas]' -o -name '*.ko' -o -name '.*.cmd' \
 		-o -name '*.ko.*' -o -name '*.su' -o -name '*.cfgtmp' \
 		-o -name '.*.d' -o -name '.*.tmp' -o -name '*.mod.c' \
+		-o -name '*.lex.c' -o -name '*.tab.[ch]' \
 		-o -name '*.symtypes' -o -name 'modules.order' \
 		-o -name modules.builtin -o -name '.tmp_*.o.*' \
 		-o -name 'dsdt.aml' -o -name 'dsdt.asl.tmp' -o -name 'dsdt.c' \
-		-o -name '*.gcno' \) -type f -print | xargs rm -f
+		-o -name '*.efi' -o -name '*.gcno' -o -name '*.so' \) \
+		-type f -print | xargs rm -f
 
 # mrproper - Delete all generated files, including .config
 #

README

@@ -331,11 +331,6 @@ The following options need to be configured:
 
 - Board Type:	Define exactly one, e.g. CONFIG_MPC8540ADS.
 
-- Marvell Family Member
-		CONFIG_SYS_MVFS		- define it if you want to enable
-					  multiple fs option at one time
-					  for marvell soc family
-
 - 85xx CPU Options:
 		CONFIG_SYS_PPC64
 
@@ -1172,10 +1167,6 @@ The following options need to be configured:
 		CONFIG_SUPPORT_EMMC_BOOT
 		Enable some additional features of the eMMC boot partitions.
 
-		CONFIG_SUPPORT_EMMC_RPMB
-		Enable the commands for reading, writing and programming the
-		key for the Replay Protection Memory Block partition in eMMC.
-
 - USB Device Firmware Update (DFU) class support:
 		CONFIG_DFU_OVER_USB
 		This enables the USB portion of the DFU USB class
@@ -2695,7 +2686,7 @@ FIT uImage format:
 		use an arch-specific makefile fragment instead, for
 		example if more than one image needs to be produced.
 
-		CONFIG_FIT_SPL_PRINT
+		CONFIG_SPL_FIT_PRINT
 		Printing information about a FIT image adds quite a bit of
 		code to SPL. So this is normally disabled in SPL. Use this
 		option to re-enable it. This will affect the output of the

arch/arc/Kconfig

@@ -150,6 +150,10 @@ config TARGET_AXS101
 config TARGET_AXS103
 	bool "Support Synopsys Designware SDP board AXS103"
 
+config TARGET_EMDK
+	bool "Synopsys EM Development kit"
+	select CPU_ARCEM6
+
 config TARGET_HSDK
 	bool "Support Synpsys HS DevelopmentKit board"
 
@@ -158,6 +162,7 @@ endchoice
 source "board/abilis/tb100/Kconfig"
 source "board/synopsys/Kconfig"
 source "board/synopsys/axs10x/Kconfig"
+source "board/synopsys/emdk/Kconfig"
 source "board/synopsys/hsdk/Kconfig"
 
 endmenu

arch/arc/cpu/u-boot.lds

@@ -5,13 +5,22 @@
 
 #include <config.h>
 
-OUTPUT_FORMAT("elf32-littlearc", "elf32-littlearc", "elf32-littlearc")
+OUTPUT_FORMAT("elf32-littlearc", "elf32-bigarc", "elf32-littlearc")
 OUTPUT_ARCH(arc)
 ENTRY(_start)
 SECTIONS
 {
 	. = CONFIG_SYS_TEXT_BASE;
 	__image_copy_start = .;
+	. = ALIGN(1024);
+	__ivt_start = .;
+	.ivt :
+	{
+		KEEP(*(.ivt))
+	}
+	__ivt_end = .;
+
+	. = ALIGN(1024);
 	__text_start = .;
 	.text :	{
 		arch/arc/lib/start.o (.text*)
@@ -19,14 +28,6 @@ SECTIONS
 	}
 	__text_end = .;
 
-	. = ALIGN(1024);
-	__ivt_start = .;
-	.ivt :
-	{
-		*(.ivt)
-	}
-	__ivt_end = .;
-
 	. = ALIGN(4);
 	.rodata : {
 		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))

arch/arc/dts/Makefile

@@ -4,6 +4,7 @@ dtb-$(CONFIG_TARGET_AXS101) +=  axs101.dtb
 dtb-$(CONFIG_TARGET_AXS103) +=  axs103.dtb
 dtb-$(CONFIG_TARGET_NSIM) +=  nsim.dtb
 dtb-$(CONFIG_TARGET_TB100) +=  abilis_tb100.dtb
+dtb-$(CONFIG_TARGET_EMDK) +=  emdk.dtb
 dtb-$(CONFIG_TARGET_HSDK) +=  hsdk.dtb
 
 targets += $(dtb-y)

arch/arc/dts/emdk.dts

@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Synopsys, Inc. All rights reserved.
+ */
+/dts-v1/;
+
+#include "skeleton.dtsi"
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	aliases {
+		console = &uart0;
+	};
+
+	cpu_card {
+		core_clk: core_clk {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <40000000>;
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	uart0: serial0@f0004000 {
+		compatible = "snps,dw-apb-uart";
+		clock-frequency = <100000000>;
+		reg = <0xf0004000 0x1000>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+	};
+};

arch/arc/lib/cache.c

@@ -432,9 +432,16 @@ void read_decode_cache_bcr(void)
 	int dc_line_sz = 0, ic_line_sz = 0;
 	union bcr_di_cache ibcr, dbcr;
 
+	/*
+	 * We don't care much about I$ line length really as there're
+	 * no per-line ops on I$ instead we only do full invalidation of it
+	 * on occasion of relocation and right before jumping to the OS.
+	 * Still we check insane config with zero-encoded line length in
+	 * presense of version field in I$ BCR. Just in case.
+	 */
 	ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD);
 	if (ibcr.fields.ver) {
-		gd->arch.l1_line_sz = ic_line_sz = 8 << ibcr.fields.line_len;
+		ic_line_sz = 8 << ibcr.fields.line_len;
 		if (!ic_line_sz)
 			panic("Instruction exists but line length is 0\n");
 	}
@@ -445,9 +452,6 @@ void read_decode_cache_bcr(void)
 		if (!dc_line_sz)
 			panic("Data cache exists but line length is 0\n");
 	}
-
-	if (ic_line_sz && dc_line_sz && (ic_line_sz != dc_line_sz))
-		panic("Instruction and data cache line lengths differ\n");
 }
 
 void cache_init(void)

arch/arc/lib/relocate.c

@@ -8,7 +8,9 @@
 #include <asm-generic/sections.h>
 
 extern ulong __image_copy_start;
+extern ulong __ivt_start;
 extern ulong __ivt_end;
+extern ulong __text_end;
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -48,7 +50,7 @@ int do_elf_reloc_fixups(void)
 	debug("Section .rela.dyn is located at %08x-%08x\n",
 	      (unsigned int)re_src, (unsigned int)re_end);
 
-	Elf32_Addr *offset_ptr_rom, *last_offset = NULL;
+	Elf32_Addr *offset_ptr_rom;
 	Elf32_Addr *offset_ptr_ram;
 
 	do {
@@ -57,15 +59,28 @@ int do_elf_reloc_fixups(void)
 
 		/* Check that the location of the relocation is in .text */
 		if (offset_ptr_rom >= (Elf32_Addr *)&__image_copy_start &&
-		    offset_ptr_rom > last_offset) {
-			unsigned int val;
+		    offset_ptr_rom < (Elf32_Addr *)&__image_copy_end) {
+			unsigned int val, do_swap = 0;
 			/* Switch to the in-RAM version */
 			offset_ptr_ram = (Elf32_Addr *)((ulong)offset_ptr_rom +
 							gd->reloc_off);
 
-			debug("Patching value @ %08x (relocated to %08x)\n",
+#ifdef __LITTLE_ENDIAN__
+			/* If location in ".text" section swap value */
+			if (((u32)offset_ptr_rom >= (u32)&__text_start &&
+			     (u32)offset_ptr_rom <= (u32)&__text_end)
+#if defined(__ARC700__) || defined(__ARC600__)
+			    || ((u32)offset_ptr_rom >= (u32)&__ivt_start &&
+				(u32)offset_ptr_rom <= (u32)&__ivt_end)
+#endif
+			   )
+				do_swap = 1;
+#endif
+
+			debug("Patching value @ %08x (relocated to %08x)%s\n",
 			      (unsigned int)offset_ptr_rom,
-			      (unsigned int)offset_ptr_ram);
+			      (unsigned int)offset_ptr_ram,
+			      do_swap ? ", middle-endian encoded" : "");
 
 			/*
 			 * Use "memcpy" because target location might be
@@ -75,28 +90,45 @@ int do_elf_reloc_fixups(void)
 			 */
 			memcpy(&val, offset_ptr_ram, sizeof(int));
 
-#ifdef __LITTLE_ENDIAN__
-			/* If location in ".text" section swap value */
-			if ((unsigned int)offset_ptr_rom <
-			    (unsigned int)&__ivt_end)
+			if (do_swap)
 				val = (val << 16) | (val >> 16);
-#endif
 
 			/* Check that the target points into executable */
-			if (val >= (unsigned int)&__image_copy_start && val <=
-			    (unsigned int)&__image_copy_end) {
-				val += gd->reloc_off;
-#ifdef __LITTLE_ENDIAN__
-				/* If location in ".text" section swap value */
-				if ((unsigned int)offset_ptr_rom <
-				    (unsigned int)&__ivt_end)
-					val = (val << 16) | (val >> 16);
-#endif
-				memcpy(offset_ptr_ram, &val, sizeof(int));
+			if (val < (unsigned int)&__image_copy_start ||
+			    val > (unsigned int)&__image_copy_end) {
+				/* TODO: Use panic() instead of debug()
+				 *
+				 * For some reason GCC might generate
+				 * fake relocation even for LD/SC of constant
+				 * inderectly. See an example below:
+				 * ----------------------->8--------------------
+				 * static int setup_mon_len(void)
+				 * {
+				 *         gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE;
+				 *         return 0;
+				 * }
+				 * ----------------------->8--------------------
+				 *
+				 * And that's what we get in the binary:
+				 * ----------------------->8--------------------
+				 * 10005cb4 <setup_mon_len>:
+				 * 10005cb4:       193c 3f80 0003 2f80     st      0x32f80,[r25,60]
+				 *                         10005cb8: R_ARC_RELATIVE        *ABS*-0x10000000
+				 * 10005cbc:       7fe0                    j_s.d   [blink]
+				 * 10005cbe:       700c                    mov_s   r0,0
+				 * ----------------------->8--------------------
+				 */
+				debug("Relocation target %08x points outside of image\n",
+				      val);
 			}
-		}
-		last_offset = offset_ptr_rom;
 
+			val += gd->reloc_off;
+
+			if (do_swap)
+				val = (val << 16) | (val >> 16);
+
+			memcpy(offset_ptr_ram, &val, sizeof(int));
+		}
 	} while (++re_src < re_end);
 
 	return 0;

arch/arc/lib/reset.c

@@ -6,13 +6,17 @@
 #include <command.h>
 #include <common.h>
 
+__weak void reset_cpu(ulong addr)
+{
+	/* Stop debug session here */
+	__builtin_arc_brk();
+}
+
 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
 {
-	printf("Put your restart handler here\n");
+	printf("Resetting the board...\n");
+
+	reset_cpu(0);
 
-#ifdef DEBUG
-	/* Stop debug session here */
-	__asm__("brk");
-#endif
 	return 0;
 }

arch/arc/lib/start.S

@@ -75,6 +75,11 @@ ENTRY(_start)
 	/* Initialize reserved area - note: r0 already contains address */
 	bl	board_init_f_init_reserve
 
+#ifdef CONFIG_DEBUG_UART
+	/* Earliest point to set up early debug uart */
+	bl	debug_uart_init
+#endif
+
 	/* Zero the one and only argument of "board_init_f" */
 	mov_s	%r0, 0
 	bl	board_init_f

arch/arm/Kconfig

@@ -74,6 +74,28 @@ config ARM_ASM_UNIFIED
 config THUMB2_KERNEL
 	bool
 
+config SYS_ARM_CACHE_CP15
+	bool "CP15 based cache enabling support"
+	help
+	  Select this if your processor suports enabling caches by using
+	  CP15 registers.
+
+config SYS_ARM_MMU
+	bool "MMU-based Paged Memory Management Support"
+	select SYS_ARM_CACHE_CP15
+	help
+	  Select if you want MMU-based virtualised addressing space
+	  support by paged memory management.
+
+config SYS_ARM_MPU
+	bool 'Use the ARM v7 PMSA Compliant MPU'
+	help
+	  Some ARM systems without an MMU have instead a Memory Protection
+	  Unit (MPU) that defines the type and permissions for regions of
+	  memory.
+	  If your CPU has an MPU then you should choose 'y' here unless you
+	  know that you do not want to use the MPU.
+
 # If set, the workarounds for these ARM errata are applied early during U-Boot
 # startup. Note that in general these options force the workarounds to be
 # applied; no CPU-type/version detection exists, unlike the similar options in
@@ -158,47 +180,65 @@ config ARM_ERRATA_855873
 config CPU_ARM720T
 	bool
 	select SYS_CACHE_SHIFT_5
+	imply SYS_ARM_MMU
 
 config CPU_ARM920T
 	bool
 	select SYS_CACHE_SHIFT_5
+	imply SYS_ARM_MMU
 
 config CPU_ARM926EJS
 	bool
 	select SYS_CACHE_SHIFT_5
+	imply SYS_ARM_MMU
 
 config CPU_ARM946ES
 	bool
 	select SYS_CACHE_SHIFT_5
+	imply SYS_ARM_MMU
 
 config CPU_ARM1136
 	bool
 	select SYS_CACHE_SHIFT_5
+	imply SYS_ARM_MMU
 
 config CPU_ARM1176
 	bool
 	select HAS_VBAR
 	select SYS_CACHE_SHIFT_5
+	imply SYS_ARM_MMU
 
-config CPU_V7
+config CPU_V7A
 	bool
 	select HAS_VBAR
 	select HAS_THUMB2
 	select SYS_CACHE_SHIFT_6
+	imply SYS_ARM_MMU
 
 config CPU_V7M
 	bool
 	select HAS_THUMB2
 	select THUMB2_KERNEL
 	select SYS_CACHE_SHIFT_5
+	select SYS_ARM_MPU
+	select SYS_THUMB_BUILD
+
+config CPU_V7R
+	bool
+	select HAS_THUMB2
+	select SYS_CACHE_SHIFT_6
+	select SYS_ARM_MPU
+	select SYS_ARM_CACHE_CP15
 
 config CPU_PXA
 	bool
 	select SYS_CACHE_SHIFT_5
+	imply SYS_ARM_MMU
 
 config CPU_SA1100
 	bool
 	select SYS_CACHE_SHIFT_5
+	imply SYS_ARM_MMU
 
 config SYS_CPU
 	default "arm720t" if CPU_ARM720T
@@ -207,7 +247,8 @@ config SYS_CPU
 	default "arm946es" if CPU_ARM946ES
 	default "arm1136" if CPU_ARM1136
 	default "arm1176" if CPU_ARM1176
-	default "armv7" if CPU_V7
+	default "armv7" if CPU_V7A
+	default "armv7" if CPU_V7R
 	default "armv7m" if CPU_V7M
 	default "pxa" if CPU_PXA
 	default "sa1100" if CPU_SA1100
@@ -221,8 +262,9 @@ config SYS_ARM_ARCH
 	default 5 if CPU_ARM946ES
 	default 6 if CPU_ARM1136
 	default 6 if CPU_ARM1176
-	default 7 if CPU_V7
+	default 7 if CPU_V7A
 	default 7 if CPU_V7M
+	default 7 if CPU_V7R
 	default 5 if CPU_PXA
 	default 4 if CPU_SA1100
 	default 8 if ARM64
@@ -244,7 +286,7 @@ config SYS_CACHELINE_SIZE
 
 config SYS_ARCH_TIMER
 	bool "ARM Generic Timer support"
-	depends on CPU_V7 || ARM64
+	depends on CPU_V7A || ARM64
 	default y if ARM64
 	help
 	  The ARM Generic Timer (aka arch-timer) provides an architected
@@ -254,7 +296,7 @@ config SYS_ARCH_TIMER
 
 config ARM_SMCCC
 	bool "Support for ARM SMC Calling Convention (SMCCC)"
-	depends on CPU_V7 || ARM64
+	depends on CPU_V7A || ARM64
 	select ARM_PSCI_FW
 	help
 	  Say Y here if you want to enable ARM SMC Calling Convention.
@@ -352,7 +394,7 @@ choice
 
 config ARCH_AT91
 	bool "Atmel AT91"
-	select SPL_BOARD_INIT if SPL
+	select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB
 
 config TARGET_EDB93XX
 	bool "Support edb93xx"
@@ -440,7 +482,7 @@ config TARGET_SPEAR600
 
 config TARGET_STV0991
 	bool "Support stv0991"
-	select CPU_V7
+	select CPU_V7A
 	select DM
 	select DM_SERIAL
 	select DM_SPI
@@ -456,13 +498,6 @@ config TARGET_X600
 	select SUPPORT_SPL
 	select PL011_SERIAL
 
-config TARGET_MX31PDK
-	bool "Support mx31pdk"
-	select BOARD_LATE_INIT
-	select CPU_ARM1136
-	select SUPPORT_SPL
-	select BOARD_EARLY_INIT_F
-
 config TARGET_WOODBURN
 	bool "Support woodburn"
 	select CPU_ARM1136
@@ -493,36 +528,36 @@ config ARCH_BCM283X
 
 config TARGET_VEXPRESS_CA15_TC2
 	bool "Support vexpress_ca15_tc2"
-	select CPU_V7
+	select CPU_V7A
 	select CPU_V7_HAS_NONSEC
 	select CPU_V7_HAS_VIRT
 	select PL011_SERIAL
 
 config TARGET_VEXPRESS_CA5X2
 	bool "Support vexpress_ca5x2"
-	select CPU_V7
+	select CPU_V7A
 	select PL011_SERIAL
 
 config TARGET_VEXPRESS_CA9X4
 	bool "Support vexpress_ca9x4"
-	select CPU_V7
+	select CPU_V7A
 	select PL011_SERIAL
 
 config TARGET_BCM23550_W1D
 	bool "Support bcm23550_w1d"
-	select CPU_V7
+	select CPU_V7A
 	imply CRC32_VERIFY
 	imply FAT_WRITE
 
 config TARGET_BCM28155_AP
 	bool "Support bcm28155_ap"
-	select CPU_V7
+	select CPU_V7A
 	imply CRC32_VERIFY
 	imply FAT_WRITE
 
 config TARGET_BCMCYGNUS
 	bool "Support bcmcygnus"
-	select CPU_V7
+	select CPU_V7A
 	imply CRC32_VERIFY
 	imply CMD_HASH
 	imply FAT_WRITE
@@ -533,7 +568,7 @@ config TARGET_BCMCYGNUS
 
 config TARGET_BCMNSP
 	bool "Support bcmnsp"
-	select CPU_V7
+	select CPU_V7A
 
 config TARGET_BCMNS2
 	bool "Support Broadcom Northstar2"
@@ -557,7 +592,7 @@ config ARCH_EXYNOS
 
 config ARCH_S5PC1XX
 	bool "Samsung S5PC1XX"
-	select CPU_V7
+	select CPU_V7A
 	select DM
 	select DM_SERIAL
 	select DM_GPIO
@@ -565,7 +600,7 @@ config ARCH_S5PC1XX
 
 config ARCH_HIGHBANK
 	bool "Calxeda Highbank"
-	select CPU_V7
+	select CPU_V7A
 	select PL011_SERIAL
 
 config ARCH_INTEGRATOR
@@ -576,7 +611,7 @@ config ARCH_INTEGRATOR
 
 config ARCH_KEYSTONE
 	bool "TI Keystone"
-	select CPU_V7
+	select CPU_V7A
 	select SUPPORT_SPL
 	select SYS_THUMB_BUILD
 	select CMD_POWEROFF
@@ -587,7 +622,7 @@ config ARCH_KEYSTONE
 
 config ARCH_OMAP2PLUS
 	bool "TI OMAP2+"
-	select CPU_V7
+	select CPU_V7A
 	select SPL_BOARD_INIT if SPL
 	select SPL_STACK_R if SPL
 	select SUPPORT_SPL
@@ -624,15 +659,19 @@ config ARCH_MX28
 	select PL011_SERIAL
 	select SUPPORT_SPL
 
+config ARCH_MX31
+	bool "NXP i.MX31 family"
+	select CPU_ARM1136
+
 config ARCH_MX7ULP
         bool "NXP MX7ULP"
-        select CPU_V7
+	select CPU_V7A
 	select ROM_UNIFIED_SECTIONS
 	imply MXC_GPIO
 
 config ARCH_MX7
 	bool "Freescale MX7"
-	select CPU_V7
+	select CPU_V7A
 	select SYS_FSL_HAS_SEC if SECURE_BOOT
 	select SYS_FSL_SEC_COMPAT_4
 	select SYS_FSL_SEC_LE
@@ -642,7 +681,7 @@ config ARCH_MX7
 
 config ARCH_MX6
 	bool "Freescale MX6"
-	select CPU_V7
+	select CPU_V7A
 	select SYS_FSL_HAS_SEC if SECURE_BOOT
 	select SYS_FSL_SEC_COMPAT_4
 	select SYS_FSL_SEC_LE
@@ -656,7 +695,7 @@ endif
 
 config ARCH_MX5
 	bool "Freescale MX5"
-	select CPU_V7
+	select CPU_V7A
 	select BOARD_EARLY_INIT_F
 	imply MXC_GPIO
 
@@ -692,14 +731,27 @@ config ARCH_SNAPDRAGON
 
 config ARCH_SOCFPGA
 	bool "Altera SOCFPGA family"
-	select CPU_V7
-	select SUPPORT_SPL
-	select OF_CONTROL
-	select SPL_OF_CONTROL
-	select DM
-	select ENABLE_ARM_SOC_BOOT0_HOOK
 	select ARCH_EARLY_INIT_R
 	select ARCH_MISC_INIT
+	select CPU_V7A
+	select DM
+	select DM_SERIAL
+	select ENABLE_ARM_SOC_BOOT0_HOOK
+	select OF_CONTROL
+	select SPL_LIBCOMMON_SUPPORT
+	select SPL_LIBDISK_SUPPORT
+	select SPL_LIBGENERIC_SUPPORT
+	select SPL_MMC_SUPPORT if DM_MMC
+	select SPL_NAND_SUPPORT if SPL_NAND_DENALI
+	select SPL_OF_CONTROL
+	select SPL_SERIAL_SUPPORT
+	select SPL_DM_SERIAL
+	select SPL_SPI_FLASH_SUPPORT if SPL_SPI_SUPPORT
+	select SPL_SPI_SUPPORT if DM_SPI
+	select SPL_WATCHDOG_SUPPORT
+	select SUPPORT_SPL
+	select SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
+	select SYS_NS16550
 	select SYS_THUMB_BUILD
 	imply CMD_MTDPARTS
 	imply CRC32_VERIFY
@@ -750,7 +802,7 @@ config ARCH_SUNXI
 
 config ARCH_VF610
 	bool "Freescale Vybrid"
-	select CPU_V7
+	select CPU_V7A
 	select SYS_FSL_ERRATUM_ESDHC111
 	imply CMD_MTDPARTS
 	imply NAND
@@ -758,7 +810,7 @@ config ARCH_VF610
 config ARCH_ZYNQ
 	bool "Xilinx Zynq based platform"
 	select BOARD_LATE_INIT
-	select CPU_V7
+	select CPU_V7A
 	select SUPPORT_SPL
 	select OF_CONTROL
 	select SPL_BOARD_INIT if SPL
@@ -780,6 +832,15 @@ config ARCH_ZYNQ
 	imply CMD_CLK
 	imply FAT_WRITE
 	imply CMD_SPL
+	imply ARCH_EARLY_INIT_R
+
+config ARCH_ZYNQMP_R5
+	bool "Xilinx ZynqMP R5 based platform"
+	select CPU_V7R
+	select OF_CONTROL
+	select DM
+	select DM_SERIAL
+	select CLK
 
 config ARCH_ZYNQMP
 	bool "Xilinx ZynqMP based platform"
@@ -1000,7 +1061,7 @@ config TARGET_LS1088ARDB
 config TARGET_LS1021AQDS
 	bool "Support ls1021aqds"
 	select BOARD_LATE_INIT
-	select CPU_V7
+	select CPU_V7A
 	select CPU_V7_HAS_NONSEC
 	select CPU_V7_HAS_VIRT
 	select SUPPORT_SPL
@@ -1014,7 +1075,7 @@ config TARGET_LS1021AQDS
 config TARGET_LS1021ATWR
 	bool "Support ls1021atwr"
 	select BOARD_LATE_INIT
-	select CPU_V7
+	select CPU_V7A
 	select CPU_V7_HAS_NONSEC
 	select CPU_V7_HAS_VIRT
 	select SUPPORT_SPL
@@ -1027,7 +1088,7 @@ config TARGET_LS1021ATWR
 config TARGET_LS1021AIOT
 	bool "Support ls1021aiot"
 	select BOARD_LATE_INIT
-	select CPU_V7
+	select CPU_V7A
 	select CPU_V7_HAS_NONSEC
 	select CPU_V7_HAS_VIRT
 	select SUPPORT_SPL
@@ -1143,7 +1204,7 @@ config STM32
 
 config ARCH_STI
 	bool "Support STMicrolectronics SoCs"
-	select CPU_V7
+	select CPU_V7A
 	select DM
 	select DM_SERIAL
 	select BLK
@@ -1164,6 +1225,7 @@ config ARCH_STM32MP
 	select DM_SERIAL
 	select OF_CONTROL
 	select OF_LIBFDT
+	select MISC
 	select PINCTRL
 	select REGMAP
 	select SUPPORT_SPL
@@ -1196,9 +1258,7 @@ config ARCH_ROCKCHIP
 	select DM_REGULATOR
 	select ENABLE_ARM_SOC_BOOT0_HOOK
 	select SPI
-	imply CMD_FASTBOOT
 	imply DISTRO_DEFAULTS
-	imply FASTBOOT
 	imply FAT_WRITE
 	imply USB_FUNCTION_FASTBOOT
 	imply SPL_SYSRESET
@@ -1255,6 +1315,8 @@ source "arch/arm/cpu/armv7/ls102xa/Kconfig"
 
 source "arch/arm/mach-imx/mx2/Kconfig"
 
+source "arch/arm/mach-imx/mx3/Kconfig"
+
 source "arch/arm/mach-imx/mx5/Kconfig"
 
 source "arch/arm/mach-imx/mx6/Kconfig"
@@ -1303,6 +1365,8 @@ source "arch/arm/cpu/armv7/vf610/Kconfig"
 
 source "arch/arm/mach-zynq/Kconfig"
 
+source "arch/arm/mach-zynqmp-r5/Kconfig"
+
 source "arch/arm/cpu/armv7/Kconfig"
 
 source "arch/arm/cpu/armv8/zynqmp/Kconfig"
@@ -1340,7 +1404,6 @@ source "board/freescale/ls1046ardb/Kconfig"
 source "board/freescale/ls1012aqds/Kconfig"
 source "board/freescale/ls1012ardb/Kconfig"
 source "board/freescale/ls1012afrdm/Kconfig"
-source "board/freescale/mx31pdk/Kconfig"
 source "board/freescale/mx35pdk/Kconfig"
 source "board/freescale/s32v234evb/Kconfig"
 source "board/gdsys/a38x/Kconfig"

arch/arm/Makefile

@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0+
 
 ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TEGRA),yy)
-CONFIG_CPU_V7=
+CONFIG_CPU_V7A=
 CONFIG_CPU_ARM720T=y
 endif
 
@@ -14,8 +14,10 @@ arch-$(CONFIG_CPU_SA1100)	=-march=armv4
 arch-$(CONFIG_CPU_PXA)		=
 arch-$(CONFIG_CPU_ARM1136)	=-march=armv5
 arch-$(CONFIG_CPU_ARM1176)	=-march=armv5t
-arch-$(CONFIG_CPU_V7)		=$(call cc-option, -march=armv7-a, \
+arch-$(CONFIG_CPU_V7A)		=$(call cc-option, -march=armv7-a, \
 				 $(call cc-option, -march=armv7, -march=armv5))
+arch-$(CONFIG_CPU_V7M)		=-march=armv7-m
+arch-$(CONFIG_CPU_V7R)		=-march=armv7-r
 arch-$(CONFIG_ARM64)		=-march=armv8-a
 
 # On Tegra systems we must build SPL for the armv4 core on the device
@@ -38,7 +40,8 @@ tune-$(CONFIG_CPU_SA1100)	=-mtune=strongarm1100
 tune-$(CONFIG_CPU_PXA)		=-mcpu=xscale
 tune-$(CONFIG_CPU_ARM1136)	=
 tune-$(CONFIG_CPU_ARM1176)	=
-tune-$(CONFIG_CPU_V7)		=
+tune-$(CONFIG_CPU_V7A)		=
+tune-$(CONFIG_CPU_V7R)		=
 tune-$(CONFIG_ARM64)		=
 
 # Evaluate tune cc-option calls now
@@ -74,6 +77,7 @@ machine-$(CONFIG_ARCH_STM32MP)		+= stm32mp
 machine-$(CONFIG_TEGRA)			+= tegra
 machine-$(CONFIG_ARCH_UNIPHIER)		+= uniphier
 machine-$(CONFIG_ARCH_ZYNQ)		+= zynq
+machine-$(CONFIG_ARCH_ZYNQMP_R5)	+= zynqmp-r5
 
 machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
 

arch/arm/cpu/armv7/Kconfig

@@ -1,4 +1,4 @@
-if CPU_V7
+if CPU_V7A
 
 config CPU_V7_HAS_NONSEC
         bool
@@ -52,7 +52,7 @@ config ARMV7_PSCI_NR_CPUS
 
 config ARMV7_LPAE
 	bool "Use LPAE page table format" if EXPERT
-	depends on CPU_V7
+	depends on CPU_V7A
 	default n
 	---help---
 	Say Y here to use the long descriptor page table format. This is

arch/arm/cpu/armv7/Makefile

@@ -10,6 +10,12 @@ obj-y	+= cache_v7.o cache_v7_asm.o
 obj-y	+= cpu.o cp15.o
 obj-y	+= syslib.o
 
+obj-$(CONFIG_SYS_ARM_MPU) += mpu_v7r.o
+
+ifneq ($(CONFIG_SPL_BUILD),y)
+obj-$(CONFIG_EFI_LOADER) += sctlr.o
+endif
+
 ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y)
 obj-y	+= lowlevel_init.o
 endif

arch/arm/cpu/armv7/ls102xa/psci.S

@@ -124,7 +124,8 @@ psci_cpu_on:
 
 	mov	r0, r4
 	mov	r1, r2
-	bl	psci_save_target_pc
+	mov	r2, r3
+	bl	psci_save
 	mov	r1, r4
 
 	@ Get DCFG base address

arch/arm/cpu/armv7/mpu_v7r.c

@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Cortex-R Memory Protection Unit specific code
+ *
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ *	Lokesh Vutla <lokeshvutla@ti.com>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/armv7.h>
+#include <asm/system.h>
+#include <asm/barriers.h>
+#include <linux/compiler.h>
+
+#include <asm/armv7_mpu.h>
+
+/* MPU Type register definitions */
+#define MPUIR_S_SHIFT		0
+#define MPUIR_S_MASK		BIT(MPUIR_S_SHIFT)
+#define MPUIR_DREGION_SHIFT	8
+#define MPUIR_DREGION_MASK	(0xff << 8)
+
+/**
+ * Note:
+ * The Memory Protection Unit(MPU) allows to partition memory into regions
+ * and set individual protection attributes for each region. In absence
+ * of MPU a default map[1] will take effect. make sure to run this code
+ * from a region which has execution permissions by default.
+ * [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0460d/I1002400.html
+ */
+
+void disable_mpu(void)
+{
+	u32 reg;
+
+	reg = get_cr();
+	reg &= ~CR_M;
+	dsb();
+	set_cr(reg);
+	isb();
+}
+
+void enable_mpu(void)
+{
+	u32 reg;
+
+	reg = get_cr();
+	reg |= CR_M;
+	dsb();
+	set_cr(reg);
+	isb();
+}
+
+int mpu_enabled(void)
+{
+	return get_cr() & CR_M;
+}
+
+void mpu_config(struct mpu_region_config *rgn)
+{
+	u32 attr, val;
+
+	attr = get_attr_encoding(rgn->mr_attr);
+
+	/* MPU Region Number Register */
+	asm volatile ("mcr p15, 0, %0, c6, c2, 0" : : "r" (rgn->region_no));
+
+	/* MPU Region Base Address Register */
+	asm volatile ("mcr p15, 0, %0, c6, c1, 0" : : "r" (rgn->start_addr));
+
+	/* MPU Region Size and Enable Register */
+	if (rgn->reg_size)
+		val = (rgn->reg_size << REGION_SIZE_SHIFT) | ENABLE_REGION;
+	else
+		val = DISABLE_REGION;
+	asm volatile ("mcr p15, 0, %0, c6, c1, 2" : : "r" (val));
+
+	/* MPU Region Access Control Register */
+	val = rgn->xn << XN_SHIFT | rgn->ap << AP_SHIFT | attr;
+	asm volatile ("mcr p15, 0, %0, c6, c1, 4" : : "r" (val));
+}
+
+void setup_mpu_regions(struct mpu_region_config *rgns, u32 num_rgns)
+{
+	u32 num, i;
+
+	asm volatile ("mrc p15, 0, %0, c0, c0, 4" : "=r" (num));
+	num = (num & MPUIR_DREGION_MASK) >> MPUIR_DREGION_SHIFT;
+	/* Regions to be configured cannot be greater than available regions */
+	if (num < num_rgns)
+		num_rgns = num;
+	/**
+	 * Assuming dcache might not be enabled at this point, disabling
+	 * and invalidating only icache.
+	 */
+	icache_disable();
+	invalidate_icache_all();
+
+	disable_mpu();
+
+	for (i = 0; i < num_rgns; i++)
+		mpu_config(&rgns[i]);
+
+	enable_mpu();
+
+	icache_enable();
+}
+
+void enable_caches(void)
+{
+	/*
+	 * setup_mpu_regions() might have enabled Icache. So add a check
+	 * before enabling Icache
+	 */
+	if (!icache_status())
+		icache_enable();
+	dcache_enable();
+}

arch/arm/cpu/armv7/psci-common.c

@@ -25,10 +25,12 @@
 #include <linux/linkage.h>
 
 static u32 psci_target_pc[CONFIG_ARMV7_PSCI_NR_CPUS] __secure_data = { 0 };
+static u32 psci_context_id[CONFIG_ARMV7_PSCI_NR_CPUS] __secure_data = { 0 };
 
-void __secure psci_save_target_pc(int cpu, u32 pc)
+void __secure psci_save(int cpu, u32 pc, u32 context_id)
 {
 	psci_target_pc[cpu] = pc;
+	psci_context_id[cpu] = context_id;
 	dsb();
 }
 
@@ -37,3 +39,8 @@ u32 __secure psci_get_target_pc(int cpu)
 	return psci_target_pc[cpu];
 }
 
+u32 __secure psci_get_context_id(int cpu)
+{
+	return psci_context_id[cpu];
+}
+

arch/arm/cpu/armv7/psci.S

@@ -321,12 +321,23 @@ ENTRY(psci_arch_init)
 ENDPROC(psci_arch_init)
 .weak psci_arch_init
 
+ENTRY(psci_arch_cpu_entry)
+	mov	pc, lr
+ENDPROC(psci_arch_cpu_entry)
+.weak psci_arch_cpu_entry
+
 ENTRY(psci_cpu_entry)
 	bl	psci_enable_smp
 
 	bl	_nonsec_init
 
+	bl	psci_arch_cpu_entry
+
 	bl	psci_get_cpu_id			@ CPU ID => r0
+	mov	r2, r0				@ CPU ID => r2
+	bl	psci_get_context_id		@ context id => r0
+	mov	r1, r0				@ context id => r1
+	mov	r0, r2				@ CPU ID => r0
 	bl	psci_get_target_pc		@ target PC => r0
 	b	_do_nonsec_entry
 ENDPROC(psci_cpu_entry)

arch/arm/cpu/armv7/sctlr.S

@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier:     GPL-2.0+ */
+/*
+ *  Routines to access the system control register
+ *
+ *  Copyright (c) 2018 Heinrich Schuchardt
+ */
+
+#include <linux/linkage.h>
+
+/*
+ * void allow_unaligned(void) - allow unaligned access
+ *
+ * This routine clears the aligned flag in the system control register.
+ * After calling this routine unaligned access does no longer lead to a
+ * data abort but is handled by the CPU.
+ */
+ENTRY(allow_unaligned)
+	mrc	p15, 0, r0, c1, c0, 0	@ load system control register
+	bic	r0, r0, #2		@ clear aligned flag
+	mcr	p15, 0, r0, c1, c0, 0	@ write system control register
+	bx	lr			@ return
+ENDPROC(allow_unaligned)

arch/arm/cpu/armv7/start.S

@@ -72,14 +72,18 @@ switch_to_hypervisor_ret:
 	bic	r0, #CR_V		@ V = 0
 	mcr	p15, 0, r0, c1, c0, 0	@ Write CP15 SCTLR Register
 
+#ifdef CONFIG_HAS_VBAR
 	/* Set vector address in CP15 VBAR register */
 	ldr	r0, =_start
 	mcr	p15, 0, r0, c12, c0, 0	@Set VBAR
+#endif
 #endif
 
 	/* the mask ROM code should have PLL and others stable */
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#ifdef CONFIG_CPU_V7A
 	bl	cpu_init_cp15
+#endif
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
 	bl	cpu_init_crit
 #endif

arch/arm/cpu/armv7/sunxi/psci.c

@@ -242,14 +242,15 @@ out:
 	cp15_write_scr(scr);
 }
 
-int __secure psci_cpu_on(u32 __always_unused unused, u32 mpidr, u32 pc)
+int __secure psci_cpu_on(u32 __always_unused unused, u32 mpidr, u32 pc,
+			 u32 context_id)
 {
 	struct sunxi_cpucfg_reg *cpucfg =
 		(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
 	u32 cpu = (mpidr & 0x3);
 
-	/* store target PC */
-	psci_save_target_pc(cpu, pc);
+	/* store target PC and context id */
+	psci_save(cpu, pc, context_id);
 
 	/* Set secondary core power on PC */
 	sunxi_set_entry_address(&psci_cpu_entry);

arch/arm/cpu/armv7m/Makefile

@@ -4,5 +4,6 @@
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 
 extra-y := start.o
-obj-y += cpu.o cache.o mpu.o
+obj-y += cpu.o cache.o
+obj-$(CONFIG_SYS_ARM_MPU) += mpu.o
 obj-$(CONFIG_SYS_ARCH_TIMER) += systick-timer.o

arch/arm/cpu/armv7m/config.mk

@@ -3,4 +3,4 @@
 # (C) Copyright 2015
 # Kamil Lulko, <kamil.lulko@gmail.com>
 
-PLATFORM_CPPFLAGS += -march=armv7-m -mthumb -mno-unaligned-access
+PLATFORM_CPPFLAGS += -mno-unaligned-access

arch/arm/cpu/armv7m/mpu.c

@@ -6,7 +6,7 @@
 
 #include <linux/bitops.h>
 #include <asm/armv7m.h>
-#include <asm/armv7m_mpu.h>
+#include <asm/armv7_mpu.h>
 #include <asm/io.h>
 
 #define V7M_MPU_CTRL_ENABLE		BIT(0)
@@ -15,20 +15,6 @@
 #define V7M_MPU_CTRL_PRIVDEFENA		BIT(2)
 #define VALID_REGION			BIT(4)
 
-#define ENABLE_REGION			BIT(0)
-
-#define AP_SHIFT			24
-#define XN_SHIFT			28
-#define TEX_SHIFT			19
-#define S_SHIFT				18
-#define C_SHIFT				17
-#define B_SHIFT				16
-#define REGION_SIZE_SHIFT		1
-
-#define CACHEABLE			(1 << C_SHIFT)
-#define BUFFERABLE			(1 << B_SHIFT)
-#define SHAREABLE			(1 << S_SHIFT)
-
 void disable_mpu(void)
 {
 	writel(0, &V7M_MPU->ctrl);
@@ -47,32 +33,7 @@ void mpu_config(struct mpu_region_config *reg_config)
 {
 	uint32_t attr;
 
-	switch (reg_config->mr_attr) {
-	case STRONG_ORDER:
-		attr = SHAREABLE;
-		break;
-	case SHARED_WRITE_BUFFERED:
-		attr = BUFFERABLE;
-		break;
-	case O_I_WT_NO_WR_ALLOC:
-		attr = CACHEABLE;
-		break;
-	case O_I_WB_NO_WR_ALLOC:
-		attr = CACHEABLE | BUFFERABLE;
-		break;
-	case O_I_NON_CACHEABLE:
-		attr = 1 << TEX_SHIFT;
-		break;
-	case O_I_WB_RD_WR_ALLOC:
-		attr = (1 << TEX_SHIFT) | CACHEABLE | BUFFERABLE;
-		break;
-	case DEVICE_NON_SHARED:
-		attr = (2 << TEX_SHIFT) | BUFFERABLE;
-		break;
-	default:
-		attr = 0; /* strongly ordered */
-		break;
-	};
+	attr = get_attr_encoding(reg_config->mr_attr);
 
 	writel(reg_config->start_addr | VALID_REGION | reg_config->region_no,
 	       &V7M_MPU->rbar);

arch/arm/cpu/armv8/fsl-layerscape/Kconfig

@@ -469,6 +469,14 @@ config SYS_FSL_SDHC_CLK_DIV
 	help
 	  This is the divider that is used to derive SDHC clock from Platform
 	  clock, in another word SDHC_clk = Platform_clk / this_divider.
+
+config SYS_FSL_QMAN_CLK_DIV
+	int "QMAN clock divider"
+	default 1 if ARCH_LS1043A
+	default 2
+	help
+	  This is the divider that is used to derive QMAN clock from Platform
+	  clock, in another word QMAN_clk = Platform_clk / this_divider.
 endmenu
 
 config RESV_RAM

arch/arm/cpu/armv8/fsl-layerscape/fdt.c

@@ -414,8 +414,8 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 		ccsr_sec_t __iomem *sec;
 
 #ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
-		if (fdt_fixup_kaslr(blob))
-			fdt_fixup_remove_jr(blob);
+		fdt_fixup_remove_jr(blob);
+		fdt_fixup_kaslr(blob);
 #endif
 
 		sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;

arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c

@@ -155,7 +155,9 @@ void get_sys_info(struct sys_info *sys_info)
 						CONFIG_SYS_FSL_IFC_CLK_DIV;
 #endif
 #ifdef CONFIG_SYS_DPAA_QBMAN
-	sys_info->freq_qman = sys_info->freq_systembus;
+	sys_info->freq_qman = (sys_info->freq_systembus /
+				CONFIG_SYS_FSL_PCLK_DIV) /
+				CONFIG_SYS_FSL_QMAN_CLK_DIV;
 #endif
 }
 

arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S

@@ -233,39 +233,45 @@ ENTRY(lowlevel_init)
 	 * NOTE: As per the CCSR map doc, TZASC 3 and TZASC 4 are just
 	 * 	 placeholders.
 	 */
+
+.macro tzasc_prog, xreg
+
+	mov     x12, TZASC1_BASE
+	mov     x16, #0x10000
+	mul     x14, \xreg, x16
+	add     x14, x14,x12
+	mov 	x1, #0x8
+	add     x1, x1, x14
+
+	ldr     w0, [x1]		/* Filter 0 Gate Keeper Register */
+	orr     w0, w0, #1 << 0		/* Set open_request for Filter 0 */
+	str     w0, [x1]
+
+	mov	x1, #0x110
+	add     x1, x1, x14
+
+	ldr     w0, [x1]		/* Region-0 Attributes Register */
+	orr     w0, w0, #1 << 31	/* Set Sec global write en, Bit[31] */
+	orr     w0, w0, #1 << 30	/* Set Sec global read en, Bit[30] */
+	str     w0, [x1]
+
+	mov	x1, #0x114
+	add     x1, x1, x14
+
+	ldr     w0, [x1]		/* Region-0 Access Register */
+	mov     w0, #0xFFFFFFFF		/* Set nsaid_wr_en and nsaid_rd_en */
+	str     w0, [x1]
+.endm
+
 #ifdef CONFIG_FSL_TZASC_1
-	ldr	x1, =TZASC_GATE_KEEPER(0)
-	ldr	w0, [x1]		/* Filter 0 Gate Keeper Register */
-	orr	w0, w0, #1 << 0		/* Set open_request for Filter 0 */
-	str	w0, [x1]
+	mov     x13, #0
+	tzasc_prog	x13
 
-	ldr	x1, =TZASC_REGION_ATTRIBUTES_0(0)
-	ldr	w0, [x1]		/* Region-0 Attributes Register */
-	orr	w0, w0, #1 << 31	/* Set Sec global write en, Bit[31] */
-	orr	w0, w0, #1 << 30	/* Set Sec global read en, Bit[30] */
-	str	w0, [x1]
-
-	ldr	x1, =TZASC_REGION_ID_ACCESS_0(0)
-	ldr	w0, [x1]		/* Region-0 Access Register */
-	mov	w0, #0xFFFFFFFF		/* Set nsaid_wr_en and nsaid_rd_en */
-	str	w0, [x1]
 #endif
 #ifdef CONFIG_FSL_TZASC_2
-	ldr	x1, =TZASC_GATE_KEEPER(1)
-	ldr	w0, [x1]		/* Filter 0 Gate Keeper Register */
-	orr	w0, w0, #1 << 0		/* Set open_request for Filter 0 */
-	str	w0, [x1]
+	mov     x13, #1
+	tzasc_prog	x13
 
-	ldr	x1, =TZASC_REGION_ATTRIBUTES_0(1)
-	ldr	w0, [x1]		/* Region-1 Attributes Register */
-	orr	w0, w0, #1 << 31	/* Set Sec global write en, Bit[31] */
-	orr	w0, w0, #1 << 30	/* Set Sec global read en, Bit[30] */
-	str	w0, [x1]
-
-	ldr	x1, =TZASC_REGION_ID_ACCESS_0(1)
-	ldr	w0, [x1]		/* Region-1 Attributes Register */
-	mov	w0, #0xFFFFFFFF		/* Set nsaid_wr_en and nsaid_rd_en */
-	str	w0, [x1]
 #endif
 	isb
 	dsb	sy

arch/arm/cpu/armv8/fsl-layerscape/soc.c

@@ -517,6 +517,7 @@ static void erratum_a010539(void)
 	porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK;
 	out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
 		 porsr1);
+	out_be32((void *)(CONFIG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff);
 #endif
 }
 

arch/arm/cpu/armv8/generic_timer.c

@@ -61,3 +61,10 @@ unsigned long usec2ticks(unsigned long usec)
 
 	return ticks;
 }
+
+ulong timer_get_boot_us(void)
+{
+	u64 val = get_ticks() * 1000000;
+
+	return val / get_tbclk();
+}

arch/arm/cpu/armv8/sec_firmware.c

@@ -115,25 +115,48 @@ static int sec_firmware_check_copy_loadable(const void *sec_firmware_img,
 					    u32 *loadable_l, u32 *loadable_h)
 {
 	phys_addr_t sec_firmware_loadable_addr = 0;
-	int conf_node_off, ld_node_off;
+	int conf_node_off, ld_node_off, images;
 	char *conf_node_name = NULL;
 	const void *data;
 	size_t size;
 	ulong load;
+	const char *name, *str, *type;
+	int len;
 
 	conf_node_name = SEC_FIRMEWARE_FIT_CNF_NAME;
 
 	conf_node_off = fit_conf_get_node(sec_firmware_img, conf_node_name);
 	if (conf_node_off < 0) {
 		printf("SEC Firmware: %s: no such config\n", conf_node_name);
-	return -ENOENT;
+		return -ENOENT;
 	}
 
-	ld_node_off = fit_conf_get_prop_node(sec_firmware_img, conf_node_off,
-					     FIT_LOADABLE_PROP);
-	if (ld_node_off >= 0) {
-		printf("SEC Firmware: '%s' present in config\n",
-		       FIT_LOADABLE_PROP);
+	/* find the node holding the images information */
+	images = fdt_path_offset(sec_firmware_img, FIT_IMAGES_PATH);
+	if (images < 0) {
+		printf("%s: Cannot find /images node: %d\n", __func__, images);
+		return -1;
+	}
+
+	type = FIT_LOADABLE_PROP;
+
+	name = fdt_getprop(sec_firmware_img, conf_node_off, type, &len);
+	if (!name) {
+		/* Loadables not present */
+		return 0;
+	}
+
+	printf("SEC Firmware: '%s' present in config\n", type);
+
+	for (str = name; str && ((str - name) < len);
+	     str = strchr(str, '\0') + 1) {
+		printf("%s: '%s'\n", type, str);
+		ld_node_off = fdt_subnode_offset(sec_firmware_img, images, str);
+		if (ld_node_off < 0) {
+			printf("cannot find image node '%s': %d\n", str,
+			       ld_node_off);
+			return -EINVAL;
+		}
 
 		/* Verify secure firmware image */
 		if (!(fit_image_verify(sec_firmware_img, ld_node_off))) {
@@ -163,11 +186,19 @@ static int sec_firmware_check_copy_loadable(const void *sec_firmware_img,
 		memcpy((void *)sec_firmware_loadable_addr, data, size);
 		flush_dcache_range(sec_firmware_loadable_addr,
 				   sec_firmware_loadable_addr + size);
-	}
 
-	/* Populate address ptrs for loadable image with loadbale addr */
-	out_le32(loadable_l, (sec_firmware_loadable_addr & WORD_MASK));
-	out_le32(loadable_h, (sec_firmware_loadable_addr >> WORD_SHIFT));
+		/* Populate loadable address only for Trusted OS */
+		if (!strcmp(str, "trustedOS@1")) {
+			/*
+			 * Populate address ptrs for loadable image with
+			 * loadbale addr
+			 */
+			out_le32(loadable_l, (sec_firmware_loadable_addr &
+					      WORD_MASK));
+			out_le32(loadable_h, (sec_firmware_loadable_addr >>
+					      WORD_SHIFT));
+		}
+	}
 
 	return 0;
 }
@@ -317,9 +348,7 @@ unsigned int sec_firmware_support_psci_version(void)
  */
 bool sec_firmware_support_hwrng(void)
 {
-	uint8_t rand[8];
 	if (sec_firmware_addr & SEC_FIRMWARE_RUNNING) {
-		if (!sec_firmware_get_random(rand, 8))
 			return true;
 	}
 
@@ -428,8 +457,10 @@ int fdt_fixup_kaslr(void *fdt)
 
 #if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT)
 	/* Check if random seed generation is  supported */
-	if (sec_firmware_support_hwrng() == false)
+	if (sec_firmware_support_hwrng() == false) {
+		printf("WARNING: SEC firmware not running, no kaslr-seed\n");
 		return 0;
+	}
 
 	ret = sec_firmware_get_random(rand, 8);
 	if (ret < 0) {

arch/arm/cpu/armv8/zynqmp/clk.c

@@ -16,10 +16,6 @@ unsigned long zynqmp_get_system_timer_freq(void)
 	u32 ver = zynqmp_get_silicon_version();
 
 	switch (ver) {
-	case ZYNQMP_CSU_VERSION_VELOCE:
-		return 10000;
-	case ZYNQMP_CSU_VERSION_EP108:
-		return 4000000;
 	case ZYNQMP_CSU_VERSION_QEMU:
 		return 50000000;
 	}
@@ -40,11 +36,7 @@ int set_cpu_clk_info(void)
 {
 	gd->cpu_clk = get_tbclk();
 
-	/* Support Veloce to show at least 1MHz via bdi */
-	if (gd->cpu_clk > 1000000)
-		gd->bd->bi_arm_freq = gd->cpu_clk / 1000000;
-	else
-		gd->bd->bi_arm_freq = 1;
+	gd->bd->bi_arm_freq = gd->cpu_clk / 1000000;
 
 	gd->bd->bi_dsp_freq = 0;
 

arch/arm/cpu/armv8/zynqmp/cpu.c

@@ -15,16 +15,28 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static struct mm_region zynqmp_mem_map[] = {
+/*
+ * Number of filled static entries and also the first empty
+ * slot in zynqmp_mem_map.
+ */
+#define ZYNQMP_MEM_MAP_USED	4
+
 #if !defined(CONFIG_ZYNQMP_NO_DDR)
-	{
-		.virt = 0x0UL,
-		.phys = 0x0UL,
-		.size = 0x80000000UL,
-		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-			 PTE_BLOCK_INNER_SHARE
-	},
+#define DRAM_BANKS CONFIG_NR_DRAM_BANKS
+#else
+#define DRAM_BANKS 0
 #endif
+
+#if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
+#define TCM_MAP 1
+#else
+#define TCM_MAP 0
+#endif
+
+/* +1 is end of list which needs to be empty */
+#define ZYNQMP_MEM_MAP_MAX (ZYNQMP_MEM_MAP_USED + DRAM_BANKS + TCM_MAP + 1)
+
+static struct mm_region zynqmp_mem_map[ZYNQMP_MEM_MAP_MAX] = {
 	{
 		.virt = 0x80000000UL,
 		.phys = 0x80000000UL,
@@ -32,8 +44,7 @@ static struct mm_region zynqmp_mem_map[] = {
 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 			 PTE_BLOCK_NON_SHARE |
 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	},
-	{
+	}, {
 		.virt = 0xf8000000UL,
 		.phys = 0xf8000000UL,
 		.size = 0x07e00000UL,
@@ -41,42 +52,51 @@ static struct mm_region zynqmp_mem_map[] = {
 			 PTE_BLOCK_NON_SHARE |
 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	}, {
-#if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
-		.virt = 0xffe00000UL,
-		.phys = 0xffe00000UL,
-		.size = 0x00200000UL,
-		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-			 PTE_BLOCK_INNER_SHARE
-	}, {
-#endif
 		.virt = 0x400000000UL,
 		.phys = 0x400000000UL,
 		.size = 0x400000000UL,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 			 PTE_BLOCK_NON_SHARE |
 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	},
-#if !defined(CONFIG_ZYNQMP_NO_DDR)
-	{
-		.virt = 0x800000000UL,
-		.phys = 0x800000000UL,
-		.size = 0x800000000UL,
-		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-			 PTE_BLOCK_INNER_SHARE
-	},
-#endif
-	{
+	}, {
 		.virt = 0x1000000000UL,
 		.phys = 0x1000000000UL,
 		.size = 0xf000000000UL,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 			 PTE_BLOCK_NON_SHARE |
 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	}, {
-		/* List terminator */
-		0,
 	}
 };
+
+void mem_map_fill(void)
+{
+	int banks = ZYNQMP_MEM_MAP_USED;
+
+#if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
+	zynqmp_mem_map[banks].virt = 0xffe00000UL;
+	zynqmp_mem_map[banks].phys = 0xffe00000UL;
+	zynqmp_mem_map[banks].size = 0x00200000UL;
+	zynqmp_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+				      PTE_BLOCK_INNER_SHARE;
+	banks = banks + 1;
+#endif
+
+#if !defined(CONFIG_ZYNQMP_NO_DDR)
+	for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		/* Zero size means no more DDR that's this is end */
+		if (!gd->bd->bi_dram[i].size)
+			break;
+
+		zynqmp_mem_map[banks].virt = gd->bd->bi_dram[i].start;
+		zynqmp_mem_map[banks].phys = gd->bd->bi_dram[i].start;
+		zynqmp_mem_map[banks].size = gd->bd->bi_dram[i].size;
+		zynqmp_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+					      PTE_BLOCK_INNER_SHARE;
+		banks = banks + 1;
+	}
+#endif
+}
+
 struct mm_region *mem_map = zynqmp_mem_map;
 
 u64 get_page_table_size(void)
@@ -115,12 +135,8 @@ unsigned int zynqmp_get_silicon_version(void)
 	gd->cpu_clk = get_tbclk();
 
 	switch (gd->cpu_clk) {
-	case 0 ... 1000000:
-		return ZYNQMP_CSU_VERSION_VELOCE;
 	case 50000000:
 		return ZYNQMP_CSU_VERSION_QEMU;
-	case 4000000:
-		return ZYNQMP_CSU_VERSION_EP108;
 	}
 
 	return ZYNQMP_CSU_VERSION_SILICON;
@@ -157,8 +173,8 @@ int __maybe_unused invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2,
 
 #define ZYNQMP_SIP_SVC_GET_API_VERSION		0xC2000001
 
-#define ZYNQMP_PM_VERSION_MAJOR		0
-#define ZYNQMP_PM_VERSION_MINOR		3
+#define ZYNQMP_PM_VERSION_MAJOR		1
+#define ZYNQMP_PM_VERSION_MINOR		0
 #define ZYNQMP_PM_VERSION_MAJOR_SHIFT	16
 #define ZYNQMP_PM_VERSION_MINOR_MASK	0xFFFF
 

arch/arm/dts/Makefile

@@ -87,6 +87,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
 dtb-$(CONFIG_ARCH_MVEBU) +=			\
 	armada-3720-db.dtb			\
 	armada-3720-espressobin.dtb		\
+	armada-3720-turris-mox.dtb		\
 	armada-375-db.dtb			\
 	armada-388-clearfog.dtb			\
 	armada-388-gp.dtb			\
@@ -129,6 +130,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
 	zynq-cc108.dtb \
 	zynq-cse-qspi-single.dtb \
 	zynq-microzed.dtb \
+	zynq-minized.dtb \
 	zynq-picozed.dtb \
 	zynq-syzygy-hub.dtb \
 	zynq-topic-miami.dtb \
@@ -157,11 +159,14 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
 	zynqmp-zc1232-revA.dtb			\
 	zynqmp-zc1254-revA.dtb			\
 	zynqmp-zc1275-revA.dtb			\
+	zynqmp-zc1275-revB.dtb			\
 	zynqmp-zc1751-xm015-dc1.dtb		\
 	zynqmp-zc1751-xm016-dc2.dtb		\
 	zynqmp-zc1751-xm017-dc3.dtb		\
 	zynqmp-zc1751-xm018-dc4.dtb		\
 	zynqmp-zc1751-xm019-dc5.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP_R5) += \
+	zynqmp-r5.dtb
 dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-bone.dtb \
 	am335x-draco.dtb \
 	am335x-evm.dtb \
@@ -179,20 +184,20 @@ dtb-$(CONFIG_TI816X) += dm8168-evm.dtb
 dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
 
 dtb-$(CONFIG_ARCH_SOCFPGA) +=				\
-	socfpga_arria10_socdk_sdmmc.dtb			\
 	socfpga_arria5_socdk.dtb			\
+	socfpga_arria10_socdk_sdmmc.dtb			\
 	socfpga_cyclone5_is1.dtb			\
 	socfpga_cyclone5_mcvevk.dtb			\
 	socfpga_cyclone5_socdk.dtb			\
 	socfpga_cyclone5_dbm_soc1.dtb			\
-	socfpga_cyclone5_de0_nano_soc.dtb			\
+	socfpga_cyclone5_de0_nano_soc.dtb		\
 	socfpga_cyclone5_de1_soc.dtb			\
 	socfpga_cyclone5_de10_nano.dtb			\
 	socfpga_cyclone5_sockit.dtb			\
 	socfpga_cyclone5_socrates.dtb			\
 	socfpga_cyclone5_sr1500.dtb			\
-	socfpga_stratix10_socdk.dtb			\
-	socfpga_cyclone5_vining_fpga.dtb
+	socfpga_cyclone5_vining_fpga.dtb		\
+	socfpga_stratix10_socdk.dtb
 
 dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb	\
 	dra72-evm-revc.dtb dra71-evm.dtb dra76-evm.dtb
@@ -349,31 +354,35 @@ dtb-$(CONFIG_MACH_SUN8I_A83T) += \
 	sun8i-a83t-cubietruck-plus.dtb \
 	sun8i-a83t-tbs-a711.dts
 dtb-$(CONFIG_MACH_SUN8I_H3) += \
+	sun8i-h2-plus-libretech-all-h3-cc.dtb \
 	sun8i-h2-plus-orangepi-zero.dtb \
 	sun8i-h3-bananapi-m2-plus.dtb \
 	sun8i-h3-libretech-all-h3-cc.dtb \
+	sun8i-h3-nanopi-m1.dtb \
+	sun8i-h3-nanopi-m1-plus.dtb \
+	sun8i-h3-nanopi-neo.dtb \
+	sun8i-h3-nanopi-neo-air.dtb \
 	sun8i-h3-orangepi-2.dtb \
 	sun8i-h3-orangepi-lite.dtb \
 	sun8i-h3-orangepi-one.dtb \
 	sun8i-h3-orangepi-pc.dtb \
 	sun8i-h3-orangepi-pc-plus.dtb \
 	sun8i-h3-orangepi-plus.dtb \
-	sun8i-h3-orangepi-plus2e.dtb \
-	sun8i-h3-nanopi-m1.dtb \
-	sun8i-h3-nanopi-m1-plus.dtb \
-	sun8i-h3-nanopi-neo.dtb \
-	sun8i-h3-nanopi-neo-air.dtb
+	sun8i-h3-orangepi-plus2e.dtb
 dtb-$(CONFIG_MACH_SUN8I_R40) += \
-	sun8i-r40-bananapi-m2-ultra.dtb
+	sun8i-r40-bananapi-m2-ultra.dtb \
+	sun8i-v40-bananapi-m2-berry.dtb
 dtb-$(CONFIG_MACH_SUN8I_V3S) += \
 	sun8i-v3s-licheepi-zero.dtb
 dtb-$(CONFIG_MACH_SUN50I_H5) += \
+	sun50i-h5-libretech-all-h3-cc.dtb \
 	sun50i-h5-nanopi-neo2.dtb \
 	sun50i-h5-nanopi-neo-plus2.dtb \
 	sun50i-h5-orangepi-pc2.dtb \
 	sun50i-h5-orangepi-prime.dtb \
 	sun50i-h5-orangepi-zero-plus2.dtb
 dtb-$(CONFIG_MACH_SUN50I) += \
+	sun50i-a64-amarula-relic.dtb \
 	sun50i-a64-bananapi-m64.dtb \
 	sun50i-a64-nanopi-a64.dtb \
 	sun50i-a64-olinuxino.dtb \
@@ -393,24 +402,33 @@ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \
 
 dtb-$(CONFIG_MX53) += imx53-cx9020.dtb
 
-dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \
-	imx6sl-evk.dtb \
-	imx6sll-evk.dtb \
+dtb-$(CONFIG_MX6QDL) += \
 	imx6dl-icore.dtb \
 	imx6dl-icore-mipi.dtb \
 	imx6dl-icore-rqs.dtb \
+	imx6dl-mamoj.dtb \
 	imx6q-cm-fx6.dtb \
 	imx6q-icore.dtb \
 	imx6q-icore-mipi.dtb \
 	imx6q-icore-rqs.dtb \
-	imx6q-logicpd.dtb \
+	imx6q-logicpd.dtb
+
+dtb-$(CONFIG_MX6SL) += imx6sl-evk.dtb
+
+dtb-$(CONFIG_MX6SL) += imx6sll-evk.dtb
+
+dtb-$(CONFIG_MX6SX) += \
 	imx6sx-sabreauto.dtb \
-	imx6sx-sdb.dtb \
+	imx6sx-sdb.dtb
+
+dtb-$(CONFIG_MX6UL) += \
 	imx6ul-geam-kit.dtb \
 	imx6ul-isiot-emmc.dtb \
 	imx6ul-isiot-nand.dtb \
 	imx6ul-opos6uldev.dtb
 
+dtb-$(CONFIG_MX6ULL) += imx6ull-14x14-evk.dtb
+
 dtb-$(CONFIG_MX7) += imx7-colibri.dtb \
 	imx7d-sdb.dtb
 
@@ -423,6 +441,7 @@ dtb-$(CONFIG_RCAR_GEN3) += \
 	r8a7796-salvator-x.dtb \
 	r8a77965-salvator-x.dtb \
 	r8a77970-eagle.dtb \
+	r8a77990-ebisu.dtb \
 	r8a77995-draak.dtb
 
 dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \

arch/arm/dts/armada-3720-turris-mox.dts

@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: GPL-2.0+ or X11
+/*
+ * Device Tree file for CZ.NIC Turris Mox Board
+ * 2018 by Marek Behun <marek.behun@nic.cz>
+ *
+ * Based on armada-3720-espressobin.dts by:
+ *   Gregory CLEMENT <gregory.clement@free-electrons.com>
+ *   Konstantin Porotchkin <kostap@marvell.com>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include "armada-372x.dtsi"
+
+/ {
+	model = "CZ.NIC Turris Mox Board";
+	compatible = "cznic,turris-mox", "marvell,armada3720",
+		     "marvell,armada3710";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	aliases {
+		ethernet0 = &eth0;
+		i2c0 = &i2c0;
+		spi0 = &spi0;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
+	};
+
+	reg_usb3_vbus: usb3_vbus@0 {
+		compatible = "regulator-fixed";
+		regulator-name = "usb3-vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		shutdown-delay-us = <1000000>;
+		gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>;
+		regulator-boot-on;
+	};
+
+	mdio {
+		eth_phy1: ethernet-phy@1 {
+			reg = <1>;
+		};
+	};
+};
+
+&comphy {
+	max-lanes = <3>;
+	phy0 {
+		phy-type = <PHY_TYPE_SGMII1>;
+		phy-speed = <PHY_SPEED_3_125G>;
+	};
+
+	phy1 {
+		phy-type = <PHY_TYPE_PEX0>;
+		phy-speed = <PHY_SPEED_2_5G>;
+	};
+
+	phy2 {
+		phy-type = <PHY_TYPE_USB3_HOST0>;
+		phy-speed = <PHY_SPEED_5G>;
+	};
+};
+
+&eth0 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii_pins>, <&smi_pins>;
+	phy-mode = "rgmii";
+	phy = <&eth_phy1>;
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1_pins>;
+	status = "okay";
+};
+
+&sdhci1 {
+	bus-width = <4>;
+	status = "okay";
+};
+
+&pinctrl_nb {
+	spi_cs1_pins: spi-cs1-pins {
+		groups = "spi_cs1";
+		function = "spi";
+	};
+};
+
+&pinctrl_sb {
+	smi_pins: smi-pins {
+		groups = "smi";
+		function = "smi";
+	};
+};
+
+&spi0 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi_cs1_pins>;
+
+	spi-flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "st,s25fl064l", "spi-flash";
+		reg = <0>;
+		spi-max-frequency = <20000000>;
+		m25p,fast-read;
+	};
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1_pins>;
+	status = "okay";
+};
+
+&usb2 {
+	status = "okay";
+};
+
+&usb3 {
+	vbus-supply = <&reg_usb3_vbus>;
+	status = "okay";
+};

arch/arm/dts/armada-37xx.dtsi

@@ -107,6 +107,32 @@
 				status = "disabled";
 			};
 
+			wdt: watchdog-timer@8300 {
+				compatible = "marvell,armada-3700-wdt";
+				reg = <0xd064 0x4>,
+				      <0x8300 0x40>;
+			};
+
+			nb_periph_clk: nb-periph-clk@13000 {
+				compatible = "marvell,armada-3700-periph-clock-nb";
+				reg = <0x13000 0x100>;
+				clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, <&tbg 3>;
+				#clock-cells = <1>;
+			};
+
+			sb_periph_clk: sb-periph-clk@18000 {
+				compatible = "marvell,armada-3700-periph-clock-sb";
+				reg = <0x18000 0x100>;
+				clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, <&tbg 3>;
+				#clock-cells = <1>;
+			};
+
+			tbg: tbg@13200 {
+				compatible = "marvell,armada-3700-tbg-clock";
+				reg = <0x13200 0x100>;
+				#clock-cells = <1>;
+			};
+
 			pinctrl_nb: pinctrl-nb@13800 {
 				compatible = "marvell,armada3710-nb-pinctrl",
 				"syscon", "simple-mfd";
@@ -281,8 +307,8 @@
 				#address-cells = <1>;
 				#size-cells = <0>;
 				#clock-cells = <0>;
-				clock-frequency = <160000>;
-				spi-max-frequency = <40000>;
+				spi-max-frequency = <50000000>;
+				clocks = <&nb_periph_clk 7>;
 				status = "disabled";
 			};
 
@@ -290,8 +316,9 @@
 				compatible = "marvell,mvebu-comphy", "marvell,comphy-armada-3700";
 				reg = <0x18300 0x28>,
 				      <0x1f300 0x3d000>;
-				mux-bitcount = <1>;
-				max-lanes = <2>;
+				mux-bitcount = <4>;
+				mux-lane-order = <1 0 2>;
+				max-lanes = <3>;
 			};
 		};
 

arch/arm/dts/armada-38x-controlcenterdc.dts

@@ -92,14 +92,14 @@
 				spi-flash@0 {
 					#address-cells = <1>;
 					#size-cells = <1>;
-					compatible = "n25q016a";
+					compatible = "n25q016a", "spi-flash";
 					reg = <0>; /* Chip select 0 */
 					spi-max-frequency = <108000000>;
 				};
 				spi-flash@1 {
 					#address-cells = <1>;
 					#size-cells = <1>;
-					compatible = "n25q128a11";
+					compatible = "n25q128a11", "spi-flash";
 					reg = <1>; /* Chip select 1 */
 					spi-max-frequency = <108000000>;
 					u-boot,dm-pre-reloc;

arch/arm/dts/armada-8040-db.dts

@@ -81,6 +81,13 @@
 		     1 3 0 0 0 0 0 0 0 3 >;
 };
 
+&ap_sdhci0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&ap_emmc_pins>;
+	bus-width = <8>;
+	status = "okay";
+};
+
 &cpm_pinctl {
 	/* MPP Bus:
 	 *	[0-31]	= 0xff: Keep default CP0_shared_pins
@@ -182,6 +189,13 @@
 	status = "okay";
 };
 
+&cpm_sdhci0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&cpm_sdhci_pins>;
+	bus-width = <4>;
+	status = "okay";
+};
+
 &cps_pinctl {
 	/* MPP Bus:
 	 *	[0-11]	RGMII0

arch/arm/dts/armada-8040-mcbin.dts

@@ -154,6 +154,14 @@
 	status = "okay";
 };
 
+/* uSD slot */
+&cpm_sdhci0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&cpm_sdhci_pins>;
+	bus-width = <4>;
+	status = "okay";
+};
+
 &cpm_comphy {
 	/*
 	 * CP0 Serdes Configuration:

arch/arm/dts/armada-ap806.dtsi

@@ -141,7 +141,7 @@
 			};
 
 			ap_pinctl: ap-pinctl@6F4000 {
-				compatible = "marvell,armada-ap806-pinctrl";
+				compatible = "marvell,ap806-pinctrl";
 				bank-name ="apn-806";
 				reg = <0x6F4000 0x10>;
 				pin-count = <20>;

arch/arm/dts/armada-cp110-master.dtsi

@@ -120,8 +120,8 @@
 
 			cpm_pinctl: cpm-pinctl@440000 {
 				compatible = "marvell,mvebu-pinctrl",
-					     "marvell,a70x0-pinctrl",
-					     "marvell,a80x0-cp0-pinctrl";
+					     "marvell,armada-7k-pinctrl",
+					     "marvell,armada-8k-cpm-pinctrl";
 				bank-name ="cp0-110";
 				reg = <0x440000 0x20>;
 				pin-count = <63>;

arch/arm/dts/armada-cp110-slave.dtsi

@@ -120,7 +120,7 @@
 
 			cps_pinctl: cps-pinctl@440000 {
 				compatible = "marvell,mvebu-pinctrl",
-					     "marvell,a80x0-cp1-pinctrl";
+					     "marvell,armada-8k-cps-pinctrl";
 				bank-name ="cp1-110";
 				reg = <0x440000 0x20>;
 				pin-count = <63>;

arch/arm/dts/bitmain-antminer-s9.dts

@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Bitmain Antminer S9 board DTS
+ *
+ * Copyright (C) 2018 Michal Simek
+ * Copyright (C) 2018 VanguardiaSur
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+	model = "Bitmain Antminer S9 Board";
+	compatible = "bitmain,antminer-s9", "xlnx,zynq-7000";
+
+	aliases {
+		ethernet0 = &gem0;
+		serial0 = &uart1;
+		mmc0 = &sdhci0;
+		gpio0 = &gpio0;
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x40000000>;
+	};
+
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		bootcount@efffff0 {
+			reg = <0xefffff0 0x10>;
+			no-map;
+		};
+
+		fpga_space@f000000 {
+			reg = <0xf000000 0x1000000>;
+			no-map;
+		};
+	};
+
+	chosen {
+		bootargs = "earlycon";
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&clkc {
+	ps-clk-frequency = <33333333>;
+};
+
+&gem0 {
+	status = "okay";
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethernet_phy>;
+
+	/* 0362/5e62 */
+	ethernet_phy: ethernet-phy@1 {
+		reg = <1>;
+	};
+};
+
+&sdhci0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+	disable-wp;
+};
+
+&uart1 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&watchdog0 {
+	reset-on-timeout;
+	timeout-sec = <200>;
+};

arch/arm/dts/dragonboard410c-uboot.dtsi

@@ -9,6 +9,26 @@
 	config {
 		u-boot,mmc-env-partition = "boot";
 	};
+
+	soc {
+		u-boot,dm-pre-reloc;
+
+		qcom,tlmm@1000000 {
+			u-boot,dm-pre-reloc;
+
+			uart {
+				u-boot,dm-pre-reloc;
+			};
+		};
+
+	qcom,gcc@1800000 {
+		u-boot,dm-pre-reloc;
+	};
+
+	serial@78b0000 {
+		u-boot,dm-pre-reloc;
+		};
+	};
 };
 
 

arch/arm/dts/dragonboard410c.dts

@@ -8,6 +8,7 @@
 /dts-v1/;
 
 #include "skeleton64.dtsi"
+#include <dt-bindings/pinctrl/pinctrl-snapdragon.h>
 
 / {
 	model = "Qualcomm Technologies, Inc. Dragonboard 410c";
@@ -38,6 +39,17 @@
 		ranges = <0x0 0x0 0x0 0xffffffff>;
 		compatible = "simple-bus";
 
+		pinctrl: qcom,tlmm@1000000 {
+			compatible = "qcom,tlmm-apq8016";
+			reg = <0x1000000 0x400000>;
+
+			blsp1_uart: uart {
+				function = "blsp1_uart";
+				pins = "GPIO_4", "GPIO_5";
+				drive-strength = <DRIVE_STRENGTH_8MA>;
+				bias-disable;
+			};
+		};
 		clkc: qcom,gcc@1800000 {
 			compatible = "qcom,gcc-apq8016";
 			reg = <0x1800000 0x80000>;
@@ -48,8 +60,9 @@
 		serial@78b0000 {
 			compatible = "qcom,msm-uartdm-v1.4";
 			reg = <0x78b0000 0x200>;
-			u-boot,dm-pre-reloc;
 			clock = <&clkc 4>;
+			pinctrl-names = "uart";
+			pinctrl-0 = <&blsp1_uart>;
 		};
 
 		soc_gpios: pinctrl@1000000 {

arch/arm/dts/dragonboard820c-uboot.dtsi

@@ -5,6 +5,20 @@
  * (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
  */
 
+/ {
+	soc {
+		u-boot,dm-pre-reloc;
+
+		clock-controller@300000 {
+			u-boot,dm-pre-reloc;
+		};
+
+		serial@75b0000 {
+			u-boot,dm-pre-reloc;
+			};
+		};
+};
+
 &pm8994_pon {
 	key_vol_down {
 		gpios = <&pm8994_pon 1 0>;

arch/arm/dts/dragonboard820c.dts

@@ -50,6 +50,7 @@
 		blsp2_uart1: serial@75b0000 {
 			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 			reg = <0x75b0000 0x1000>;
+			clock = <&gcc 4>;
 		};
 
 		sdhc2: sdhci@74a4900 {

arch/arm/dts/imx53-kp.dts

@@ -0,0 +1,135 @@
+/*
+ * Copyright 2018
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * SPDX-License-Identifier:     GPL-2.0+ or X11
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include "imx53.dtsi"
+#include "imx53-pinfunc.h"
+
+/ {
+	model = "K+P iMX53";
+	compatible = "kp,imx53-kp", "fsl,imx53";
+
+	chosen {
+		stdout-path = &uart2;
+	};
+};
+
+&fec {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_eth>;
+	phy-mode = "rmii";
+	phy-reset-gpios = <&gpio7 6 0>;
+	status = "okay";
+};
+
+&i2c2 {
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	pinctrl-1 = <&pinctrl_i2c2_gpio>;
+	clock_frequency = <100000>;
+
+	scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
+
+	status = "okay";
+
+	pmic: mc34708@8 {
+		compatible = "fsl,mc34708";
+		reg = <0x8>;
+	};
+};
+
+&i2c3 {
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	pinctrl-1 = <&pinctrl_i2c3_gpio>;
+	clock_frequency = <100000>;
+
+	scl-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
+
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog>;
+
+	imx53-kp {
+		pinctrl_eth: ethgrp {
+			fsl,pins = <
+				MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc
+				MX53_PAD_FEC_MDC__FEC_MDC 0x4
+				MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180
+				MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180
+				MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4
+				MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4
+				MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4
+				MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180
+				/* The RX_ER pin needs to be pull down */
+				/* for this device */
+				MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x1c0
+				MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180
+				>;
+		};
+
+		pinctrl_hog: hoggrp {
+			fsl,pins = <
+				/* PHY RESET */
+				MX53_PAD_PATA_DA_0__GPIO7_6 0x182
+				/* VBUS_PWR_EN */
+				MX53_PAD_PATA_DA_2__GPIO7_8 0x1e4
+				/* BOOSTER_OFF */
+				MX53_PAD_EIM_CS0__GPIO2_23 0x1e4
+			>;
+		};
+
+		pinctrl_i2c2: i2c2grp {
+			fsl,pins = <
+				MX53_PAD_KEY_ROW3__I2C2_SDA
+						 (0x1ee | IMX_PAD_SION)
+				MX53_PAD_KEY_COL3__I2C2_SCL
+						 (0x1ee | IMX_PAD_SION)
+			>;
+		};
+
+		pinctrl_i2c2_gpio: i2c2grpgpio {
+			fsl,pins = <
+				MX53_PAD_KEY_ROW3__GPIO4_13 0x1e4
+				MX53_PAD_KEY_COL3__GPIO4_12 0x1e4
+			>;
+		};
+
+		pinctrl_i2c3: i2c3grp {
+			fsl,pins = <
+				MX53_PAD_GPIO_6__I2C3_SDA (0x1ee | IMX_PAD_SION)
+				MX53_PAD_GPIO_5__I2C3_SCL (0x1ee | IMX_PAD_SION)
+			>;
+		};
+
+		pinctrl_i2c3_gpio: i2c3grpgpio {
+			fsl,pins = <
+				MX53_PAD_GPIO_6__GPIO1_6 0x1e4
+				MX53_PAD_GPIO_5__GPIO1_5 0x1e4
+			>;
+		};
+
+		pinctrl_uart2: uart2grp {
+			fsl,pins = <
+				MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
+				MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
+			>;
+		};
+	};
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2>;
+	status = "okay";
+};

arch/arm/dts/imx53-pinfunc.h

@@ -10,6 +10,7 @@
 #ifndef __DTS_IMX53_PINFUNC_H
 #define __DTS_IMX53_PINFUNC_H
 
+#define IMX_PAD_SION       0x40000000
 /*
  * The pin function ID is a tuple of
  * <mux_reg conf_reg input_reg mux_mode input_val>

arch/arm/dts/imx53.dtsi

@@ -21,6 +21,16 @@
 / {
 	aliases {
 		serial1 = &uart2;
+		gpio0 = &gpio1;
+		gpio1 = &gpio2;
+		gpio2 = &gpio3;
+		gpio3 = &gpio4;
+		gpio4 = &gpio5;
+		gpio5 = &gpio6;
+		gpio6 = &gpio7;
+		i2c0 = &i2c1;
+		i2c1 = &i2c2;
+		i2c2 = &i2c3;
 	};
 
 	tzic: tz-interrupt-controller@fffc000 {
@@ -73,6 +83,66 @@
 				#clock-cells = <1>;
 			};
 
+			gpio1: gpio@53f84000 {
+				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
+				reg = <0x53f84000 0x4000>;
+				interrupts = <50 51>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpio2: gpio@53f88000 {
+				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
+				reg = <0x53f88000 0x4000>;
+				interrupts = <52 53>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpio3: gpio@53f8c000 {
+				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
+				reg = <0x53f8c000 0x4000>;
+				interrupts = <54 55>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpio4: gpio@53f90000 {
+				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
+				reg = <0x53f90000 0x4000>;
+				interrupts = <56 57>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpio5: gpio@53fdc000 {
+				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
+				reg = <0x53fdc000 0x4000>;
+				interrupts = <103 104>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpio6: gpio@53fe0000 {
+				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
+				reg = <0x53fe0000 0x4000>;
+				interrupts = <105 106>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
 			gpio7: gpio@53fe4000 {
 				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 				reg = <0x53fe4000 0x4000>;
@@ -82,6 +152,16 @@
 				interrupt-controller;
 				#interrupt-cells = <2>;
 			};
+
+			i2c3: i2c@53fec000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
+				reg = <0x53fec000 0x4000>;
+				interrupts = <64>;
+				clocks = <&clks IMX5_CLK_I2C3_GATE>;
+				status = "disabled";
+			};
 		};
 
 		aips@60000000 {	/* AIPS2 */
@@ -102,7 +182,6 @@
 				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
 			};
 
-
 			fec: ethernet@63fec000 {
 				compatible = "fsl,imx53-fec", "fsl,imx25-fec";
 				reg = <0x63fec000 0x4000>;
@@ -113,6 +192,26 @@
 				clock-names = "ipg", "ahb", "ptp";
 				status = "disabled";
 			};
+
+			i2c2: i2c@63fc4000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
+				reg = <0x63fc4000 0x4000>;
+				interrupts = <63>;
+				clocks = <&clks IMX5_CLK_I2C2_GATE>;
+				status = "disabled";
+			};
+
+			i2c1: i2c@63fc8000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
+				reg = <0x63fc8000 0x4000>;
+				interrupts = <62>;
+				clocks = <&clks IMX5_CLK_I2C1_GATE>;
+				status = "disabled";
+			};
 		};
 	};
 };

arch/arm/dts/imx6dl-icore-mipi-u-boot.dtsi

@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include "imx6qdl-icore-u-boot.dtsi"
+
+&usdhc3 {
+	u-boot,dm-spl;
+};

arch/arm/dts/imx6dl-icore-mipi.dts

@@ -16,6 +16,5 @@
 };
 
 &usdhc3 {
-	u-boot,dm-spl;
 	status = "okay";
 };

arch/arm/dts/imx6dl-icore-rqs-u-boot.dtsi

@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include "imx6qdl-icore-rqs-u-boot.dtsi"

arch/arm/dts/imx6dl-icore-u-boot.dtsi

@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include "imx6qdl-icore-u-boot.dtsi"

arch/arm/dts/imx6dl-mamoj-u-boot.dtsi

@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include "imx6qdl-u-boot.dtsi"
+
+&usdhc3 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+	u-boot,dm-spl;
+};

arch/arm/dts/imx6dl-mamoj.dts

@@ -0,0 +1,225 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2018 BTicino
+ * Copyright (C) 2018 Amarula Solutions B.V.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include "imx6dl.dtsi"
+
+/ {
+	model = "BTicino i.MX6DL Mamoj board";
+	compatible = "bticino,imx6dl-mamoj", "fsl,imx6dl";
+};
+
+&fec {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet>;
+	phy-mode = "mii";
+	status = "okay";
+};
+
+&i2c3 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	status = "okay";
+};
+
+&i2c4 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c4>;
+	status = "okay";
+
+	pmic: pfuze100@08 {
+		compatible = "fsl,pfuze100";
+		reg = <0x08>;
+
+		regulators {
+			/* CPU vdd_arm core */
+			sw1a_reg: sw1ab {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			/* SOC vdd_soc */
+			sw1c_reg: sw1c {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			/* I/O power GEN_3V3 */
+			sw2_reg: sw2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			/* DDR memory */
+			sw3a_reg: sw3a {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			/* DDR memory */
+			sw3b_reg: sw3b {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			/* not used */
+			sw4_reg: sw4 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+			/* not used */
+			swbst_reg: swbst {
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5150000>;
+			};
+
+			/* PMIC vsnvs. EX boot mode */
+			snvs_reg: vsnvs {
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vref_reg: vrefddr {
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			/* not used */
+			vgen1_reg: vgen1 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+			};
+
+			/* not used */
+			vgen2_reg: vgen2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+			};
+
+			/* not used */
+			vgen3_reg: vgen3 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+			/* 1v8 general power */
+			vgen4_reg: vgen4 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			/* 2v8 general power IMX6 */
+			vgen5_reg: vgen5 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			/* 3v3 Ethernet */
+			vgen6_reg: vgen6 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart3>;
+	status = "okay";
+};
+
+&usdhc3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	bus-width = <8>;
+	non-removable;
+	keep-power-in-suspend;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl_enet: enetgrp {
+		fsl,pins = <
+			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
+			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
+			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b1
+			MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0	0x1b0b0
+			MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1	0x1b0b0
+			MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2	0x1b0b0
+			MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3	0x1b0b0
+			MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN	0x1b0b0
+			MX6QDL_PAD_GPIO_19__ENET_TX_ER		0x1b0b0
+			MX6QDL_PAD_GPIO_18__ENET_RX_CLK		0x1b0b1
+			MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0	0x1b0b0
+			MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1	0x1b0b0
+			MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2	0x1b0b0
+			MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3      0x1b0b0
+			MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN	0x1b0b0
+			MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER	0x1b0b0
+			MX6QDL_PAD_KEY_COL3__ENET_CRS		0x1b0b0
+			MX6QDL_PAD_KEY_ROW1__ENET_COL		0x1b0b0
+		>;
+	};
+
+	pinctrl_i2c3: i2c3grp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_3__I2C3_SCL     0x4001b8b1
+			MX6QDL_PAD_GPIO_6__I2C3_SDA     0x4001b8b1
+		>;
+	};
+
+	pinctrl_i2c4: i2c4grp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_7__I2C4_SCL	0x4001b8b1
+			MX6QDL_PAD_GPIO_8__I2C4_SDA	0x4001b8b1
+		>;
+	};
+
+	pinctrl_uart3: uart3grp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D24__UART3_TX_DATA	0x1b0b1
+			MX6QDL_PAD_EIM_D25__UART3_RX_DATA	0x1b0b1
+		>;
+	};
+
+	pinctrl_usdhc3: usdhc3grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD3_CMD__SD3_CMD	0x17059
+			MX6QDL_PAD_SD3_CLK__SD3_CLK	0x10059
+			MX6QDL_PAD_SD3_DAT0__SD3_DATA0	0x17059
+			MX6QDL_PAD_SD3_DAT1__SD3_DATA1	0x17059
+			MX6QDL_PAD_SD3_DAT2__SD3_DATA2	0x17059
+			MX6QDL_PAD_SD3_DAT3__SD3_DATA3	0x17059
+			MX6QDL_PAD_SD3_DAT4__SD3_DATA4	0x17059
+			MX6QDL_PAD_SD3_DAT5__SD3_DATA5	0x17059
+			MX6QDL_PAD_SD3_DAT6__SD3_DATA6	0x17059
+			MX6QDL_PAD_SD3_DAT7__SD3_DATA7	0x17059
+		>;
+	};
+};

arch/arm/dts/imx6q-icore-mipi-u-boot.dtsi

@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include "imx6qdl-icore-u-boot.dtsi"
+
+&usdhc3 {
+	u-boot,dm-spl;
+};

arch/arm/dts/imx6q-icore-mipi.dts

@@ -16,6 +16,5 @@
 };
 
 &usdhc3 {
-	u-boot,dm-spl;
 	status = "okay";
 };

arch/arm/dts/imx6q-icore-rqs-u-boot.dtsi

@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include "imx6qdl-icore-rqs-u-boot.dtsi"

arch/arm/dts/imx6q-icore-u-boot.dtsi

@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include "imx6qdl-icore-u-boot.dtsi"

arch/arm/dts/imx6qdl-icore-rqs-u-boot.dtsi

@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include "imx6qdl-u-boot.dtsi"
+
+&usdhc3 {
+	u-boot,dm-spl;
+};
+
+&usdhc4 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc4 {
+	u-boot,dm-spl;
+};

arch/arm/dts/imx6qdl-icore-rqs.dtsi

@@ -105,7 +105,6 @@
 };
 
 &usdhc3 {
-	u-boot,dm-spl;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_usdhc3>;
 	cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
@@ -114,7 +113,6 @@
 };
 
 &usdhc4 {
-	u-boot,dm-spl;
 	pinctrl-names = "default", "state_100mhz", "state_200mhz";
 	pinctrl-0 = <&pinctrl_usdhc4>;
 	pinctrl-1 = <&pinctrl_usdhc4_100mhz>;
@@ -176,7 +174,6 @@
 	};
 
 	pinctrl_usdhc3: usdhc3grp {
-		u-boot,dm-spl;
 		fsl,pins = <
 			MX6QDL_PAD_SD3_CMD__SD3_CMD    0x17070
 			MX6QDL_PAD_SD3_CLK__SD3_CLK    0x10070
@@ -188,7 +185,6 @@
 	};
 
 	pinctrl_usdhc4: usdhc4grp {
-		u-boot,dm-spl;
 		fsl,pins = <
 			MX6QDL_PAD_SD4_CMD__SD4_CMD    0x17070
 			MX6QDL_PAD_SD4_CLK__SD4_CLK    0x10070

arch/arm/dts/imx6qdl-icore-u-boot.dtsi

@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include "imx6qdl-u-boot.dtsi"
+
+&usdhc1 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc1 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+	u-boot,dm-spl;
+};

arch/arm/dts/imx6qdl-icore.dtsi

@@ -122,7 +122,6 @@
 };
 
 &usdhc1 {
-	u-boot,dm-spl;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_usdhc1>;
 	cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
@@ -221,7 +220,6 @@
 	};
 
 	pinctrl_usdhc1: usdhc1grp {
-		u-boot,dm-spl;
 		fsl,pins = <
 			MX6QDL_PAD_SD1_CMD__SD1_CMD    0x17070
 			MX6QDL_PAD_SD1_CLK__SD1_CLK    0x10070
@@ -233,7 +231,6 @@
 	};
 
 	pinctrl_usdhc3: usdhc3grp {
-		u-boot,dm-spl;
 		fsl,pins = <
 			MX6QDL_PAD_SD3_CMD__SD3_CMD    0x17059
 			MX6QDL_PAD_SD3_CLK__SD3_CLK    0x10059

arch/arm/dts/imx6qdl-u-boot.dtsi

@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+/ {
+	soc {
+		u-boot,dm-spl;
+
+		aips-bus@02000000 {
+			u-boot,dm-spl;
+		};
+
+		aips-bus@02100000 {
+			u-boot,dm-spl;
+		};
+	};
+};
+
+&gpio1 {
+	u-boot,dm-spl;
+};
+
+&iomuxc {
+	u-boot,dm-spl;
+};

arch/arm/dts/imx6qdl.dtsi

@@ -77,7 +77,6 @@
 		compatible = "simple-bus";
 		interrupt-parent = <&gpc>;
 		ranges;
-		u-boot,dm-spl;
 
 		dma_apbh: dma-apbh@00110000 {
 			compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
@@ -226,7 +225,6 @@
 			#size-cells = <1>;
 			reg = <0x02000000 0x100000>;
 			ranges;
-			u-boot,dm-spl;
 
 			spba-bus@02000000 {
 				compatible = "fsl,spba-bus", "simple-bus";
@@ -518,7 +516,6 @@
 				#gpio-cells = <2>;
 				interrupt-controller;
 				#interrupt-cells = <2>;
-				u-boot,dm-spl;
 			};
 
 			gpio2: gpio@020a0000 {
@@ -808,7 +805,6 @@
 			iomuxc: iomuxc@020e0000 {
 				compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
 				reg = <0x020e0000 0x4000>;
-				u-boot,dm-spl;
 			};
 
 			ldb: ldb@020e0008 {
@@ -893,7 +889,6 @@
 			#size-cells = <1>;
 			reg = <0x02100000 0x100000>;
 			ranges;
-			u-boot,dm-spl;
 
 			crypto: caam@2100000 {
 				compatible = "fsl,sec-v4.0";

arch/arm/dts/imx6ul-geam-kit-u-boot.dtsi

@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include "imx6ul-u-boot.dtsi"
+
+&usdhc1 {
+	u-boot,dm-spl;
+};
+
+&iomuxc {
+	pinctrl_usdhc1: usdhc1grp {
+		u-boot,dm-spl;
+	};
+
+	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+		u-boot,dm-spl;
+	};
+
+	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+		u-boot,dm-spl;
+	};
+};

arch/arm/dts/imx6ul-geam-kit.dts

@@ -87,7 +87,6 @@
 };
 
 &usdhc1 {
-	u-boot,dm-spl;
 	pinctrl-names = "default", "state_100mhz", "state_200mhz";
 	pinctrl-0 = <&pinctrl_usdhc1>;
 	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
@@ -135,7 +134,6 @@
 	};
 
 	pinctrl_usdhc1: usdhc1grp {
-		u-boot,dm-spl;
 		fsl,pins = <
 			MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x17059
 			MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x10059
@@ -147,7 +145,6 @@
 	};
 
 	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
-		u-boot,dm-spl;
 		fsl,pins = <
 			MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170b9
 			MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100b9
@@ -159,7 +156,6 @@
 	};
 
 	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
-		u-boot,dm-spl;
 		fsl,pins = <
 			MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170f9
 			MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100f9

arch/arm/dts/imx6ul-isiot-emmc-u-boot.dtsi

@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include "imx6ul-isiot-u-boot.dtsi"
+
+&usdhc2 {
+	u-boot,dm-spl;
+};

arch/arm/dts/imx6ul-isiot-emmc.dts

@@ -42,6 +42,7 @@
 
 /dts-v1/;
 
+#include "imx6ul.dtsi"
 #include "imx6ul-isiot.dtsi"
 
 / {
@@ -51,29 +52,5 @@
 
 &usdhc2 {
 	u-boot,dm-spl;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usdhc2>;
-	cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
-	bus-width = <8>;
-	no-1-8-v;
 	status = "okay";
 };
-
-&iomuxc {
-	pinctrl_usdhc2: usdhc2grp {
-		u-boot,dm-spl;
-		fsl,pins = <
-			MX6UL_PAD_NAND_RE_B__USDHC2_CLK      0x17070
-			MX6UL_PAD_NAND_WE_B__USDHC2_CMD      0x10070
-			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0  0x17070
-			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1  0x17070
-			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2  0x17070
-			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3  0x17070
-			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4  0x17070
-			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5  0x17070
-			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6  0x17070
-			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7  0x17070
-			MX6UL_PAD_NAND_ALE__USDHC2_RESET_B   0x17070
-		>;
-	};
-};

arch/arm/dts/imx6ul-isiot-nand.dts

@@ -42,6 +42,7 @@
 
 /dts-v1/;
 
+#include "imx6ul.dtsi"
 #include "imx6ul-isiot.dtsi"
 
 / {

arch/arm/dts/imx6ul-isiot-u-boot.dtsi

@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include "imx6ul-u-boot.dtsi"
+
+&usdhc1 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc1 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2 {
+	u-boot,dm-spl;
+};

arch/arm/dts/imx6ul-isiot.dtsi

@@ -42,7 +42,6 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
-#include "imx6ul.dtsi"
 
 / {
 	memory {
@@ -82,7 +81,6 @@
 };
 
 &usdhc1 {
-	u-boot,dm-spl;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_usdhc1>;
 	cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
@@ -91,6 +89,15 @@
 	status = "okay";
 };
 
+&usdhc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc2>;
+	cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
+	bus-width = <8>;
+	no-1-8-v;
+	status = "disabled";
+};
+
 &iomuxc {
 	pinctrl_enet1: enet1grp {
 		fsl,pins = <
@@ -129,7 +136,6 @@
 	};
 
 	pinctrl_usdhc1: usdhc1grp {
-		u-boot,dm-spl;
 		fsl,pins = <
 			MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x17059
 			MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x10059
@@ -139,4 +145,21 @@
 			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
 		>;
 	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		u-boot,dm-spl;
+		fsl,pins = <
+			MX6UL_PAD_NAND_RE_B__USDHC2_CLK      0x17070
+			MX6UL_PAD_NAND_WE_B__USDHC2_CMD      0x10070
+			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0  0x17070
+			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1  0x17070
+			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2  0x17070
+			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3  0x17070
+			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4  0x17070
+			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5  0x17070
+			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6  0x17070
+			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7  0x17070
+			MX6UL_PAD_NAND_ALE__USDHC2_RESET_B   0x17070
+		>;
+	};
 };

arch/arm/dts/imx6ul-u-boot.dtsi

@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+/ {
+	soc {
+		u-boot,dm-spl;
+	};
+};
+
+&aips1 {
+	u-boot,dm-spl;
+};
+
+&gpio1 {
+	u-boot,dm-spl;
+};
+
+&gpio4 {
+	u-boot,dm-spl;
+};
+
+&iomuxc {
+	u-boot,dm-spl;
+};
+
+&aips2 {
+	u-boot,dm-spl;
+};

arch/arm/dts/imx6ul.dtsi

@@ -134,7 +134,6 @@
 		compatible = "simple-bus";
 		interrupt-parent = <&gpc>;
 		ranges;
-		u-boot,dm-spl;
 
 		pmu {
 			compatible = "arm,cortex-a7-pmu";
@@ -186,7 +185,6 @@
 			#size-cells = <1>;
 			reg = <0x02000000 0x100000>;
 			ranges;
-			u-boot,dm-spl;
 
 			spba-bus@02000000 {
 				compatible = "fsl,spba-bus", "simple-bus";
@@ -418,7 +416,6 @@
 				#interrupt-cells = <2>;
 				gpio-ranges = <&iomuxc  0 23 10>, <&iomuxc 10 17 6>,
 					      <&iomuxc 16 33 16>;
-				u-boot,dm-spl;
 			};
 
 			gpio2: gpio@020a0000 {
@@ -455,7 +452,6 @@
 				interrupt-controller;
 				#interrupt-cells = <2>;
 				gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>;
-				u-boot,dm-spl;
 			};
 
 			gpio5: gpio@020ac000 {
@@ -654,7 +650,6 @@
 			iomuxc: iomuxc@020e0000 {
 				compatible = "fsl,imx6ul-iomuxc";
 				reg = <0x020e0000 0x4000>;
-				u-boot,dm-spl;
 			};
 
 			gpr: iomuxc-gpr@020e4000 {
@@ -735,7 +730,6 @@
 			#size-cells = <1>;
 			reg = <0x02100000 0x100000>;
 			ranges;
-			u-boot,dm-spl;
 
 			usbotg1: usb@02184000 {
 				compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";

arch/arm/dts/kirkwood-6192.dtsi

@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: GPL-2.0
+/ {
+	mbus@f1000000 {
+		pciec: pcie@82000000 {
+			compatible = "marvell,kirkwood-pcie";
+			status = "disabled";
+			device_type = "pci";
+
+			#address-cells = <3>;
+			#size-cells = <2>;
+
+			bus-range = <0x00 0xff>;
+
+			ranges =
+			       <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
+				0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0       1 0 /* Port 0.0 MEM */
+				0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0       1 0 /* Port 0.0 IO  */>;
+
+			pcie0: pcie@1,0 {
+				device_type = "pci";
+				assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
+				reg = <0x0800 0 0 0 0>;
+				#address-cells = <3>;
+				#size-cells = <2>;
+				#interrupt-cells = <1>;
+				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
+					  0x81000000 0 0 0x81000000 0x1 0 1 0>;
+				bus-range = <0x00 0xff>;
+				interrupt-map-mask = <0 0 0 0>;
+				interrupt-map = <0 0 0 0 &intc 9>;
+				marvell,pcie-port = <0>;
+				marvell,pcie-lane = <0>;
+				clocks = <&gate_clk 2>;
+				status = "disabled";
+			};
+		};
+	};
+
+	ocp@f1000000 {
+		pinctrl: pin-controller@10000 {
+			compatible = "marvell,88f6192-pinctrl";
+
+			pmx_sata0: pmx-sata0 {
+				marvell,pins = "mpp5", "mpp21", "mpp23";
+				marvell,function = "sata0";
+			};
+			pmx_sata1: pmx-sata1 {
+				marvell,pins = "mpp4", "mpp20", "mpp22";
+				marvell,function = "sata1";
+			};
+			pmx_sdio: pmx-sdio {
+				marvell,pins = "mpp12", "mpp13", "mpp14",
+					       "mpp15", "mpp16", "mpp17";
+				marvell,function = "sdio";
+			};
+		};
+
+		rtc: rtc@10300 {
+			compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
+			reg = <0x10300 0x20>;
+			interrupts = <53>;
+			clocks = <&gate_clk 7>;
+		};
+
+		sata: sata@80000 {
+			compatible = "marvell,orion-sata";
+			reg = <0x80000 0x5000>;
+			interrupts = <21>;
+			clocks = <&gate_clk 14>, <&gate_clk 15>;
+			clock-names = "0", "1";
+			phys = <&sata_phy0>, <&sata_phy1>;
+			phy-names = "port0", "port1";
+			status = "disabled";
+		};
+
+		sdio: mvsdio@90000 {
+			compatible = "marvell,orion-sdio";
+			reg = <0x90000 0x200>;
+			interrupts = <28>;
+			clocks = <&gate_clk 4>;
+			bus-width = <4>;
+			cap-sdio-irq;
+			cap-sd-highspeed;
+			cap-mmc-highspeed;
+			status = "disabled";
+		};
+	};
+};

arch/arm/dts/kirkwood-6281.dtsi

@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: GPL-2.0
+/ {
+	mbus@f1000000 {
+		pciec: pcie@82000000 {
+			compatible = "marvell,kirkwood-pcie";
+			status = "disabled";
+			device_type = "pci";
+
+			#address-cells = <3>;
+			#size-cells = <2>;
+
+			bus-range = <0x00 0xff>;
+
+			ranges =
+			       <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
+				0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0       1 0 /* Port 0.0 MEM */
+				0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0       1 0 /* Port 0.0 IO  */>;
+
+			pcie0: pcie@1,0 {
+				device_type = "pci";
+				assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
+				reg = <0x0800 0 0 0 0>;
+				#address-cells = <3>;
+				#size-cells = <2>;
+				#interrupt-cells = <1>;
+				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
+					  0x81000000 0 0 0x81000000 0x1 0 1 0>;
+				bus-range = <0x00 0xff>;
+				interrupt-map-mask = <0 0 0 0>;
+				interrupt-map = <0 0 0 0 &intc 9>;
+				marvell,pcie-port = <0>;
+				marvell,pcie-lane = <0>;
+				clocks = <&gate_clk 2>;
+				status = "disabled";
+			};
+		};
+	};
+
+	ocp@f1000000 {
+		pinctrl: pin-controller@10000 {
+			compatible = "marvell,88f6281-pinctrl";
+
+			pmx_sata0: pmx-sata0 {
+				marvell,pins = "mpp5", "mpp21", "mpp23";
+				marvell,function = "sata0";
+			};
+			pmx_sata1: pmx-sata1 {
+				marvell,pins = "mpp4", "mpp20", "mpp22";
+				marvell,function = "sata1";
+			};
+			pmx_sdio: pmx-sdio {
+				marvell,pins = "mpp12", "mpp13", "mpp14",
+					       "mpp15", "mpp16", "mpp17";
+				marvell,function = "sdio";
+			};
+		};
+
+		rtc: rtc@10300 {
+			compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
+			reg = <0x10300 0x20>;
+			interrupts = <53>;
+			clocks = <&gate_clk 7>;
+		};
+
+		sata: sata@80000 {
+			compatible = "marvell,orion-sata";
+			reg = <0x80000 0x5000>;
+			interrupts = <21>;
+			clocks = <&gate_clk 14>, <&gate_clk 15>;
+			clock-names = "0", "1";
+			phys = <&sata_phy0>, <&sata_phy1>;
+			phy-names = "port0", "port1";
+			status = "disabled";
+		};
+
+		sdio: mvsdio@90000 {
+			compatible = "marvell,orion-sdio";
+			reg = <0x90000 0x200>;
+			interrupts = <28>;
+			clocks = <&gate_clk 4>;
+			pinctrl-0 = <&pmx_sdio>;
+			pinctrl-names = "default";
+			bus-width = <4>;
+			cap-sdio-irq;
+			cap-sd-highspeed;
+			cap-mmc-highspeed;
+			status = "disabled";
+		};
+	};
+};

arch/arm/dts/kirkwood-98dx4122.dtsi

@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0
+/ {
+	mbus@f1000000 {
+		pciec: pcie@82000000 {
+			compatible = "marvell,kirkwood-pcie";
+			status = "disabled";
+			device_type = "pci";
+
+			#address-cells = <3>;
+			#size-cells = <2>;
+
+			bus-range = <0x00 0xff>;
+
+			ranges =
+			       <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
+				0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0       1 0 /* Port 0.0 MEM */
+				0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0       1 0 /* Port 0.0 IO  */>;
+
+			pcie0: pcie@1,0 {
+				device_type = "pci";
+				assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
+				reg = <0x0800 0 0 0 0>;
+				#address-cells = <3>;
+				#size-cells = <2>;
+				#interrupt-cells = <1>;
+				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
+					  0x81000000 0 0 0x81000000 0x1 0 1 0>;
+				bus-range = <0x00 0xff>;
+				interrupt-map-mask = <0 0 0 0>;
+				interrupt-map = <0 0 0 0 &intc 9>;
+				marvell,pcie-port = <0>;
+				marvell,pcie-lane = <0>;
+				clocks = <&gate_clk 2>;
+				status = "disabled";
+			};
+		};
+	};
+
+	ocp@f1000000 {
+		pinctrl: pin-controller@10000 {
+			compatible = "marvell,98dx4122-pinctrl";
+
+		};
+	};
+};
+
+&sata_phy0 {
+	status = "disabled";
+};
+
+&sata_phy1 {
+	status = "disabled";
+};

arch/arm/dts/kirkwood-blackarmor-nas220.dts

@@ -0,0 +1,172 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Device Tree file for Seagate Blackarmor NAS220
+ *
+ * Copyright (C) 2014 Evgeni Dobrev <evgeni@studio-punkt.com>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "kirkwood.dtsi"
+#include "kirkwood-6192.dtsi"
+
+/ {
+	model = "Seagate Blackarmor NAS220";
+	compatible = "seagate,blackarmor-nas220","marvell,kirkwood-88f6192",
+		     "marvell,kirkwood";
+
+	memory { /* 128 MB */
+		device_type = "memory";
+		reg = <0x00000000 0x8000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8";
+		stdout-path = &uart0;
+	};
+
+	gpio_poweroff {
+		compatible = "gpio-poweroff";
+		gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "Reset";
+			linux,code = <KEY_POWER>;
+			gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>;
+		};
+
+		button {
+			label = "Power";
+			linux,code = <KEY_SLEEP>;
+			gpios = <&gpio0 26 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		blue-power {
+			label = "nas220:blue:power";
+			gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "default-on";
+		};
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		pinctrl-0 = <&pmx_power_sata0 &pmx_power_sata1>;
+		pinctrl-names = "default";
+
+		sata0_power: regulator@1 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+			regulator-name = "SATA0 Power";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			enable-active-high;
+			regulator-always-on;
+			regulator-boot-on;
+			gpio = <&gpio0 24 GPIO_ACTIVE_LOW>;
+		};
+
+		sata1_power: regulator@2 {
+			compatible = "regulator-fixed";
+			reg = <2>;
+			regulator-name = "SATA1 Power";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			enable-active-high;
+			regulator-always-on;
+			regulator-boot-on;
+			gpio = <&gpio0 28 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+/*
+ * Serial port routed to connector CN5
+ *
+ * pin 1 - TX (CPU's TX)
+ * pin 4 - RX (CPU's RX)
+ * pin 6 - GND
+ */
+&uart0 {
+	status = "okay";
+};
+
+&pinctrl {
+	pinctrl-0 = <&pmx_button_reset &pmx_button_power>;
+	pinctrl-names = "default";
+
+	pmx_act_sata0: pmx-act-sata0 {
+		marvell,pins = "mpp15";
+		marvell,function = "sata0";
+	};
+
+	pmx_act_sata1: pmx-act-sata1 {
+		marvell,pins = "mpp16";
+		marvell,function = "sata1";
+	};
+
+	pmx_power_sata0: pmx-power-sata0 {
+		marvell,pins = "mpp24";
+		marvell,function = "gpio";
+	};
+
+	pmx_power_sata1: pmx-power-sata1 {
+		marvell,pins = "mpp28";
+		marvell,function = "gpio";
+	};
+
+	pmx_button_reset: pmx-button-reset {
+		marvell,pins = "mpp29";
+		marvell,function = "gpio";
+	};
+
+	pmx_button_power: pmx-button-power {
+		marvell,pins = "mpp26";
+		marvell,function = "gpio";
+	};
+};
+
+&sata {
+	status = "okay";
+	nr-ports = <2>;
+};
+
+&i2c0 {
+	status = "okay";
+
+	adt7476: thermal@2e {
+		compatible = "adi,adt7476";
+		reg = <0x2e>;
+	};
+};
+
+&nand {
+	status = "okay";
+};
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy@8 {
+		 reg = <8>;
+	};
+};
+
+&eth0 {
+	status = "okay";
+
+	ethernet0-port@0 {
+		phy-handle = <&ethphy0>;
+	};
+};

arch/arm/dts/kirkwood-d2net.dts

@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree file for d2 Network v2
+ *
+ * Copyright (C) 2014 Simon Guinot <simon.guinot@sequanux.org>
+ *
+*/
+
+/dts-v1/;
+
+#include <dt-bindings/leds/leds-ns2.h>
+#include "kirkwood-netxbig.dtsi"
+
+/ {
+	model = "LaCie d2 Network v2";
+	compatible = "lacie,d2net_v2", "lacie,netxbig", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x10000000>;
+	};
+
+	ns2-leds {
+		compatible = "lacie,ns2-leds";
+
+		blue-sata {
+			label = "d2net_v2:blue:sata";
+			slow-gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>;
+			cmd-gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>;
+			modes-map = <NS_V2_LED_OFF  1 0
+				     NS_V2_LED_ON   0 1
+				     NS_V2_LED_ON   1 1
+				     NS_V2_LED_SATA 0 0>;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		red-fail {
+			label = "d2net_v2:red:fail";
+			gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};

arch/arm/dts/kirkwood-dns325.dts

@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "kirkwood-dnskw.dtsi"
+
+/ {
+	model = "D-Link DNS-325 NAS (Rev A1)";
+	compatible = "dlink,dns-325-a1", "dlink,dns-325", "dlink,dns-kirkwood", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x10000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8 earlyprintk";
+		stdout-path = &uart0;
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+		pinctrl-0 = <&pmx_led_power &pmx_led_red_usb_325
+			     &pmx_led_red_left_hdd &pmx_led_red_right_hdd
+			     &pmx_led_white_usb>;
+		pinctrl-names = "default";
+
+		white-power {
+			label = "dns325:white:power";
+			gpios = <&gpio0 26 GPIO_ACTIVE_LOW>;
+			default-state = "keep";
+		};
+		white-usb {
+			label = "dns325:white:usb";
+			gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; /* GPIO 43 */
+		};
+		red-l_hdd {
+			label = "dns325:red:l_hdd";
+			gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
+		};
+		red-r_hdd {
+			label = "dns325:red:r_hdd";
+			gpios = <&gpio0 27 GPIO_ACTIVE_LOW>;
+		};
+		red-usb {
+			label = "dns325:red:usb";
+			gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	ocp@f1000000 {
+		i2c@11000 {
+			status = "okay";
+
+			lm75: lm75@48 {
+				compatible = "national,lm75";
+				reg = <0x48>;
+			};
+		};
+		serial@12000 {
+			status = "okay";
+		};
+	};
+};

arch/arm/dts/kirkwood-dnskw.dtsi

@@ -0,0 +1,235 @@
+// SPDX-License-Identifier: GPL-2.0
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
+
+/ {
+	model = "D-Link DNS NASes (kirkwood-based)";
+	compatible = "dlink,dns-kirkwood", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		pinctrl-0 = <&pmx_button_power &pmx_button_unmount
+			     &pmx_button_reset>;
+		pinctrl-names = "default";
+
+		power {
+			label = "Power button";
+			linux,code = <KEY_POWER>;
+			gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
+		};
+		eject {
+			label = "USB unmount button";
+			linux,code = <KEY_EJECTCD>;
+			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
+		};
+		reset {
+			label = "Reset button";
+			linux,code = <KEY_RESTART>;
+			gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	gpio_fan {
+		/* Fan: ADDA AD045HB-G73 40mm 6000rpm@5v */
+		compatible = "gpio-fan";
+		pinctrl-0 = <&pmx_fan_high_speed &pmx_fan_low_speed>;
+		pinctrl-names = "default";
+		gpios = <&gpio1 14 GPIO_ACTIVE_LOW
+			 &gpio1 13 GPIO_ACTIVE_LOW>;
+		gpio-fan,speed-map = <0    0
+				      3000 1
+				      6000 2>;
+	};
+
+	gpio_poweroff {
+		compatible = "gpio-poweroff";
+		pinctrl-0 = <&pmx_power_off>;
+		pinctrl-names = "default";
+		gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+	};
+
+	ocp@f1000000 {
+		pinctrl: pin-controller@10000 {
+
+			pinctrl-0 = <&pmx_power_back_on &pmx_present_sata0
+				     &pmx_present_sata1 &pmx_fan_tacho
+				     &pmx_temp_alarm>;
+			pinctrl-names = "default";
+
+			pmx_sata0: pmx-sata0 {
+				marvell,pins = "mpp20";
+				marvell,function = "sata1";
+			};
+			pmx_sata1: pmx-sata1 {
+				marvell,pins = "mpp21";
+				marvell,function = "sata0";
+			};
+			pmx_led_power: pmx-led-power {
+				marvell,pins = "mpp26";
+				marvell,function = "gpio";
+			};
+			pmx_led_red_right_hdd: pmx-led-red-right-hdd {
+				marvell,pins = "mpp27";
+				marvell,function = "gpio";
+			};
+			pmx_led_red_left_hdd: pmx-led-red-left-hdd {
+				marvell,pins = "mpp28";
+				marvell,function = "gpio";
+			};
+			pmx_led_red_usb_325: pmx-led-red-usb-325 {
+				marvell,pins = "mpp29";
+				marvell,function = "gpio";
+			};
+			pmx_button_power: pmx-button-power {
+				marvell,pins = "mpp34";
+				marvell,function = "gpio";
+			};
+			pmx_led_red_usb_320: pmx-led-red-usb-320 {
+				marvell,pins = "mpp35";
+				marvell,function = "gpio";
+			};
+			pmx_power_off: pmx-power-off {
+				marvell,pins = "mpp36";
+				marvell,function = "gpio";
+			};
+			pmx_power_back_on: pmx-power-back-on {
+				marvell,pins = "mpp37";
+				marvell,function = "gpio";
+			};
+			pmx_power_sata0: pmx-power-sata0 {
+				marvell,pins = "mpp39";
+				marvell,function = "gpio";
+			};
+			pmx_power_sata1: pmx-power-sata1 {
+				marvell,pins = "mpp40";
+				marvell,function = "gpio";
+			};
+			pmx_present_sata0: pmx-present-sata0 {
+				marvell,pins = "mpp41";
+				marvell,function = "gpio";
+			};
+			pmx_present_sata1: pmx-present-sata1 {
+				marvell,pins = "mpp42";
+				marvell,function = "gpio";
+			};
+			pmx_led_white_usb: pmx-led-white-usb {
+				marvell,pins = "mpp43";
+				marvell,function = "gpio";
+			};
+			pmx_fan_tacho: pmx-fan-tacho {
+				marvell,pins = "mpp44";
+				marvell,function = "gpio";
+			};
+			pmx_fan_high_speed: pmx-fan-high-speed {
+				marvell,pins = "mpp45";
+				marvell,function = "gpio";
+			};
+			pmx_fan_low_speed: pmx-fan-low-speed {
+				marvell,pins = "mpp46";
+				marvell,function = "gpio";
+			};
+			pmx_button_unmount: pmx-button-unmount {
+				marvell,pins = "mpp47";
+				marvell,function = "gpio";
+			};
+			pmx_button_reset: pmx-button-reset {
+				marvell,pins = "mpp48";
+				marvell,function = "gpio";
+			};
+			pmx_temp_alarm: pmx-temp-alarm {
+				marvell,pins = "mpp49";
+				marvell,function = "gpio";
+			};
+		};
+		sata@80000 {
+			pinctrl-0 = <&pmx_sata0 &pmx_sata1>;
+			pinctrl-names = "default";
+			status = "okay";
+			nr-ports = <2>;
+		};
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		pinctrl-0 = <&pmx_power_sata0 &pmx_power_sata1>;
+		pinctrl-names = "default";
+
+		sata0_power: regulator@1 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+			regulator-name = "SATA0 Power";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			enable-active-high;
+			regulator-always-on;
+			regulator-boot-on;
+			gpio = <&gpio1 7 0>;
+		};
+		sata1_power: regulator@2 {
+			compatible = "regulator-fixed";
+			reg = <2>;
+			regulator-name = "SATA1 Power";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			enable-active-high;
+			regulator-always-on;
+			regulator-boot-on;
+			gpio = <&gpio1 8 0>;
+		};
+	};
+};
+
+&nand {
+	status = "okay";
+	chip-delay = <35>;
+
+	partition@0 {
+		label = "u-boot";
+		reg = <0x0000000 0x100000>;
+		read-only;
+	};
+
+	partition@100000 {
+		label = "uImage";
+		reg = <0x0100000 0x500000>;
+	};
+
+	partition@600000 {
+		label = "ramdisk";
+		reg = <0x0600000 0x500000>;
+	};
+
+	partition@b00000 {
+		label = "image";
+		reg = <0x0b00000 0x6600000>;
+	};
+
+	partition@7100000 {
+		label = "mini firmware";
+		reg = <0x7100000 0xa00000>;
+	};
+
+	partition@7b00000 {
+		label = "config";
+		reg = <0x7b00000 0x500000>;
+	};
+};
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy@8 {
+		reg = <8>;
+	};
+};
+
+&eth0 {
+	status = "okay";
+	ethernet0-port@0 {
+		phy-handle = <&ethphy0>;
+	};
+};

arch/arm/dts/kirkwood-dockstar.dts

@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
+
+/ {
+	model = "Seagate FreeAgent Dockstar";
+	compatible = "seagate,dockstar", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x8000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/sda1 rootdelay=10";
+		stdout-path = &uart0;
+	};
+
+	ocp@f1000000 {
+		pinctrl: pin-controller@10000 {
+			pmx_usb_power_enable: pmx-usb-power-enable {
+				marvell,pins = "mpp29";
+				marvell,function = "gpio";
+			};
+			pmx_led_green: pmx-led-green {
+				marvell,pins = "mpp46";
+				marvell,function = "gpio";
+			};
+			pmx_led_orange: pmx-led-orange {
+				marvell,pins = "mpp47";
+				marvell,function = "gpio";
+			};
+		};
+		serial@12000 {
+			status = "ok";
+		};
+	};
+	gpio-leds {
+		compatible = "gpio-leds";
+		pinctrl-0 = <&pmx_led_green &pmx_led_orange>;
+		pinctrl-names = "default";
+
+		health {
+			label = "status:green:health";
+			gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
+			default-state = "keep";
+		};
+		fault {
+			label = "status:orange:fault";
+			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
+		};
+	};
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		pinctrl-0 = <&pmx_usb_power_enable>;
+		pinctrl-names = "default";
+
+		usb_power: regulator@1 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+			regulator-name = "USB Power";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			enable-active-high;
+			regulator-always-on;
+			regulator-boot-on;
+			gpio = <&gpio0 29 0>;
+		};
+	};
+};
+
+&nand {
+	status = "okay";
+
+	partition@0 {
+		label = "u-boot";
+		reg = <0x0000000 0x100000>;
+		read-only;
+	};
+
+	partition@100000 {
+		label = "uImage";
+		reg = <0x0100000 0x400000>;
+	};
+
+	partition@500000 {
+		label = "data";
+		reg = <0x0500000 0xfb00000>;
+	};
+};
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy@0 {
+		compatible = "marvell,88e1116";
+		reg = <0>;
+	};
+};
+
+&eth0 {
+	status = "okay";
+	ethernet0-port@0 {
+		phy-handle = <&ethphy0>;
+	};
+};

arch/arm/dts/kirkwood-dreamplug.dts

@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
+
+/ {
+	model = "Globalscale Technologies Dreamplug";
+	compatible = "globalscale,dreamplug-003-ds2001", "globalscale,dreamplug", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x20000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8 earlyprintk";
+		stdout-path = &uart0;
+	};
+
+	ocp@f1000000 {
+		pinctrl: pin-controller@10000 {
+			pmx_led_bluetooth: pmx-led-bluetooth {
+				marvell,pins = "mpp47";
+				marvell,function = "gpio";
+			};
+			pmx_led_wifi: pmx-led-wifi {
+				marvell,pins = "mpp48";
+				marvell,function = "gpio";
+			};
+			pmx_led_wifi_ap: pmx-led-wifi-ap {
+				marvell,pins = "mpp49";
+				marvell,function = "gpio";
+			};
+		};
+		serial@12000 {
+			status = "ok";
+		};
+
+		spi@10600 {
+			status = "okay";
+
+			m25p40@0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "mxicy,mx25l1606e", "jedec,spi-nor", "spi-flash";
+				reg = <0>;
+				spi-max-frequency = <50000000>;
+				mode = <0>;
+
+				partition@0 {
+					reg = <0x0 0x80000>;
+					label = "u-boot";
+				};
+
+				partition@100000 {
+					reg = <0x100000 0x10000>;
+					label = "u-boot env";
+				};
+
+				partition@180000 {
+					reg = <0x180000 0x10000>;
+					label = "dtb";
+				};
+			};
+		};
+
+		sata@80000 {
+			status = "okay";
+			nr-ports = <1>;
+		};
+
+		mvsdio@90000 {
+			pinctrl-0 = <&pmx_sdio>;
+			pinctrl-names = "default";
+			status = "okay";
+			/* No CD or WP GPIOs */
+			broken-cd;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+		pinctrl-0 = <&pmx_led_bluetooth &pmx_led_wifi
+			     &pmx_led_wifi_ap >;
+		pinctrl-names = "default";
+
+		bluetooth {
+			label = "dreamplug:blue:bluetooth";
+			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
+		};
+		wifi {
+			label = "dreamplug:green:wifi";
+			gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
+		};
+		wifi-ap {
+			label = "dreamplug:green:wifi_ap";
+			gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy@0 {
+		reg = <0>;
+	};
+
+	ethphy1: ethernet-phy@1 {
+		reg = <1>;
+	};
+};
+
+&eth0 {
+	status = "okay";
+	ethernet0-port@0 {
+		phy-handle = <&ethphy0>;
+	};
+};
+
+&eth1 {
+	status = "okay";
+	ethernet1-port@0 {
+		phy-handle = <&ethphy1>;
+	};
+};

arch/arm/dts/kirkwood-ds109.dts

@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Andrew Lunn <andrew@lunn.ch>
+ * Ben Peddell <klightspeed@killerwolves.net>
+ *
+ */
+
+/dts-v1/;
+
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
+#include "kirkwood-synology.dtsi"
+
+/ {
+	model = "Synology DS109, DS110, DS110jv20";
+	compatible = "synology,ds109", "synology,ds110jv20",
+		     "synology,ds110", "marvell,kirkwood";
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x8000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8";
+		stdout-path = &uart0;
+	};
+
+	gpio-fan-150-32-35 {
+		status = "okay";
+	};
+
+	gpio-leds-hdd-21-1 {
+		status = "okay";
+	};
+};
+
+&rs5c372 {
+	status = "okay";
+};

arch/arm/dts/kirkwood-goflexnet.dts

@@ -0,0 +1,190 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
+
+/ {
+	model = "Seagate GoFlex Net";
+	compatible = "seagate,goflexnet", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x8000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/sda1 rootdelay=10";
+		stdout-path = &uart0;
+	};
+
+	ocp@f1000000 {
+		pinctrl: pin-controller@10000 {
+			pmx_usb_power_enable: pmx-usb-power-enable {
+				marvell,pins = "mpp29";
+				marvell,function = "gpio";
+			};
+			pmx_led_right_cap_0: pmx-led_right_cap_0 {
+				marvell,pins = "mpp38";
+				marvell,function = "gpio";
+			};
+			pmx_led_right_cap_1: pmx-led_right_cap_1 {
+				marvell,pins = "mpp39";
+				marvell,function = "gpio";
+			};
+			pmx_led_right_cap_2: pmx-led_right_cap_2 {
+				marvell,pins = "mpp40";
+				marvell,function = "gpio";
+			};
+			pmx_led_right_cap_3: pmx-led_right_cap_3 {
+				marvell,pins = "mpp41";
+				marvell,function = "gpio";
+			};
+			pmx_led_left_cap_0: pmx-led_left_cap_0 {
+				marvell,pins = "mpp42";
+				marvell,function = "gpio";
+			};
+			pmx_led_left_cap_1: pmx-led_left_cap_1 {
+				marvell,pins = "mpp43";
+				marvell,function = "gpio";
+			};
+			pmx_led_left_cap_2: pmx-led_left_cap_2 {
+				marvell,pins = "mpp44";
+				marvell,function = "gpio";
+			};
+			pmx_led_left_cap_3: pmx-led_left_cap_3 {
+				marvell,pins = "mpp45";
+				marvell,function = "gpio";
+			};
+			pmx_led_green: pmx-led_green {
+				marvell,pins = "mpp46";
+				marvell,function = "gpio";
+			};
+			pmx_led_orange: pmx-led_orange {
+				marvell,pins = "mpp47";
+				marvell,function = "gpio";
+			};
+		};
+		serial@12000 {
+			status = "ok";
+		};
+
+		sata@80000 {
+			status = "okay";
+			nr-ports = <2>;
+		};
+
+	};
+	gpio-leds {
+		compatible = "gpio-leds";
+		pinctrl-0 = < &pmx_led_orange
+			      &pmx_led_left_cap_0 &pmx_led_left_cap_1
+			      &pmx_led_left_cap_2 &pmx_led_left_cap_3
+			      &pmx_led_right_cap_0 &pmx_led_right_cap_1
+			      &pmx_led_right_cap_2 &pmx_led_right_cap_3
+			    >;
+		pinctrl-names = "default";
+
+		health {
+			label = "status:green:health";
+			gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
+			default-state = "keep";
+		};
+		fault {
+			label = "status:orange:fault";
+			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
+		};
+		left0 {
+			label = "status:white:left0";
+			gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+		};
+		left1 {
+			label = "status:white:left1";
+			gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
+		};
+		left2 {
+			label = "status:white:left2";
+			gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+		};
+		left3 {
+			label = "status:white:left3";
+			gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+		};
+		right0 {
+			label = "status:white:right0";
+			gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
+		};
+		right1 {
+			label = "status:white:right1";
+			gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+		};
+		right2 {
+			label = "status:white:right2";
+			gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
+		};
+		right3 {
+			label = "status:white:right3";
+			gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+		};
+	};
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		pinctrl-0 = <&pmx_usb_power_enable>;
+		pinctrl-names = "default";
+
+		usb_power: regulator@1 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+			regulator-name = "USB Power";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			enable-active-high;
+			regulator-always-on;
+			regulator-boot-on;
+			gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
+
+&nand {
+	chip-delay = <40>;
+	status = "okay";
+
+	partition@0 {
+		label = "u-boot";
+		reg = <0x0000000 0x100000>;
+		read-only;
+	};
+
+	partition@100000 {
+		label = "uImage";
+		reg = <0x0100000 0x400000>;
+	};
+
+	partition@500000 {
+		label = "pogoplug";
+		reg = <0x0500000 0x2000000>;
+	};
+
+	partition@2500000 {
+		label = "root";
+		reg = <0x02500000 0xd800000>;
+	};
+};
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy@0 {
+		reg = <0>;
+	};
+};
+
+&eth0 {
+	status = "okay";
+	ethernet0-port@0 {
+		phy-handle = <&ethphy0>;
+	};
+};

arch/arm/dts/kirkwood-guruplug-server-plus.dts

@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
+
+/ {
+	model = "Globalscale Technologies Guruplug Server Plus";
+	compatible = "globalscale,guruplug-server-plus", "globalscale,guruplug", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x20000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8 earlyprintk";
+		stdout-path = &uart0;
+	};
+
+	ocp@f1000000 {
+		pinctrl: pin-controller@10000 {
+			pmx_led_health_r: pmx-led-health-r {
+				marvell,pins = "mpp46";
+				marvell,function = "gpio";
+			};
+			pmx_led_health_g: pmx-led-health-g {
+				marvell,pins = "mpp47";
+				marvell,function = "gpio";
+			};
+			pmx_led_wmode_r: pmx-led-wmode-r {
+				marvell,pins = "mpp48";
+				marvell,function = "gpio";
+			};
+			pmx_led_wmode_g: pmx-led-wmode-g {
+				marvell,pins = "mpp49";
+				marvell,function = "gpio";
+			};
+		};
+		serial@12000 {
+			status = "ok";
+		};
+
+		sata@80000 {
+			status = "okay";
+			nr-ports = <1>;
+		};
+
+		/* AzureWave AW-GH381 WiFi/BT */
+		mvsdio@90000 {
+			status = "okay";
+			non-removable;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+		pinctrl-0 = < &pmx_led_health_r &pmx_led_health_g
+			      &pmx_led_wmode_r &pmx_led_wmode_g >;
+		pinctrl-names = "default";
+
+		health-r {
+			label = "guruplug:red:health";
+			gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
+		};
+		health-g {
+			label = "guruplug:green:health";
+			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
+		};
+		wmode-r {
+			label = "guruplug:red:wmode";
+			gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
+		};
+		wmode-g {
+			label = "guruplug:green:wmode";
+			gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&nand {
+	status = "okay";
+
+	partition@0 {
+		label = "u-boot";
+		reg = <0x00000000 0x00100000>;
+		read-only;
+	};
+
+	partition@100000 {
+		label = "uImage";
+		reg = <0x00100000 0x00400000>;
+	};
+
+	partition@500000 {
+		label = "data";
+		reg = <0x00500000 0x1fb00000>;
+	};
+};
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy@0 {
+		/* Marvell 88E1121R */
+		compatible = "ethernet-phy-id0141.0cb0",
+		             "ethernet-phy-ieee802.3-c22";
+		reg = <0>;
+	};
+
+	ethphy1: ethernet-phy@1 {
+		/* Marvell 88E1121R */
+		compatible = "ethernet-phy-id0141.0cb0",
+		             "ethernet-phy-ieee802.3-c22";
+		reg = <1>;
+	};
+};
+
+&eth0 {
+	status = "okay";
+	ethernet0-port@0 {
+		phy-handle = <&ethphy0>;
+		phy-connection-type = "rgmii-id";
+	};
+};
+
+&eth1 {
+	status = "okay";
+	ethernet1-port@0 {
+		phy-handle = <&ethphy1>;
+		phy-connection-type = "rgmii-id";
+	};
+};

arch/arm/dts/kirkwood-ib62x0.dts

@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
+
+/ {
+	model = "RaidSonic ICY BOX IB-NAS62x0 (Rev B)";
+	compatible = "raidsonic,ib-nas6210-b", "raidsonic,ib-nas6220-b", "raidsonic,ib-nas6210", "raidsonic,ib-nas6220", "raidsonic,ib-nas62x0", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x10000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8 earlyprintk";
+		stdout-path = &uart0;
+	};
+
+	ocp@f1000000 {
+		pinctrl: pin-controller@10000 {
+			pmx_led_os_red: pmx-led-os-red {
+				marvell,pins = "mpp22";
+				marvell,function = "gpio";
+			};
+			pmx_power_off: pmx-power-off {
+				marvell,pins = "mpp24";
+				marvell,function = "gpio";
+			};
+			pmx_led_os_green: pmx-led-os-green {
+				marvell,pins = "mpp25";
+				marvell,function = "gpio";
+			};
+			pmx_led_usb_transfer: pmx-led-usb-transfer {
+				marvell,pins = "mpp27";
+				marvell,function = "gpio";
+			};
+			pmx_button_reset: pmx-button-reset {
+				marvell,pins = "mpp28";
+				marvell,function = "gpio";
+			};
+			pmx_button_usb_copy: pmx-button-usb-copy {
+				marvell,pins = "mpp29";
+				marvell,function = "gpio";
+			};
+		};
+
+		serial@12000 {
+			status = "okay";
+		};
+
+		sata@80000 {
+			status = "okay";
+			nr-ports = <2>;
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		pinctrl-0 = <&pmx_button_reset &pmx_button_usb_copy>;
+		pinctrl-names = "default";
+
+		copy {
+			label = "USB Copy";
+			linux,code = <KEY_COPY>;
+			gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
+		};
+		reset {
+			label = "Reset";
+			linux,code = <KEY_RESTART>;
+			gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+		pinctrl-0 = <&pmx_led_os_red &pmx_led_os_green
+			     &pmx_led_usb_transfer>;
+		pinctrl-names = "default";
+
+		green-os {
+			label = "ib62x0:green:os";
+			gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>;
+			default-state = "keep";
+		};
+		red-os {
+			label = "ib62x0:red:os";
+			gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;
+		};
+		usb-copy {
+			label = "ib62x0:red:usb_copy";
+			gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	gpio_poweroff {
+		compatible = "gpio-poweroff";
+		pinctrl-0 = <&pmx_power_off>;
+		pinctrl-names = "default";
+		gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&nand {
+	status = "okay";
+
+	partition@0 {
+		label = "u-boot";
+		reg = <0x0000000 0xe0000>;
+	};
+
+	partition@e0000 {
+		label = "u-boot environment";
+		reg = <0xe0000 0x20000>;
+	};
+
+	partition@100000 {
+		label = "uImage";
+		reg = <0x0100000 0x600000>;
+	};
+
+	partition@700000 {
+		label = "root";
+		reg = <0x0700000 0xf900000>;
+	};
+
+};
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy@8 {
+		reg = <8>;
+	};
+};
+
+&eth0 {
+	status = "okay";
+
+	ethernet0-port@0 {
+		phy-handle = <&ethphy0>;
+	};
+};

arch/arm/dts/kirkwood-iconnect.dts

@@ -0,0 +1,195 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
+
+/ {
+	model = "Iomega Iconnect";
+	compatible = "iom,iconnect-1.1", "iom,iconnect", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x10000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8 earlyprintk";
+		stdout-path = &uart0;
+		linux,initrd-start = <0x4500040>;
+		linux,initrd-end   = <0x4800000>;
+	};
+
+	ocp@f1000000 {
+		pinctrl: pin-controller@10000 {
+			pmx_button_reset: pmx-button-reset {
+				marvell,pins = "mpp12";
+				marvell,function = "gpio";
+			};
+			pmx_button_otb: pmx-button-otb {
+				marvell,pins = "mpp35";
+				marvell,function = "gpio";
+			};
+			pmx_led_level: pmx-led-level {
+				marvell,pins = "mpp41";
+				marvell,function = "gpio";
+			};
+			pmx_led_power_blue: pmx-led-power-blue {
+				marvell,pins = "mpp42";
+				marvell,function = "gpio";
+			};
+			pmx_led_power_red: pmx-power-red {
+				marvell,pins = "mpp43";
+				marvell,function = "gpio";
+			};
+			pmx_led_usb1: pmx-led-usb1 {
+				marvell,pins = "mpp44";
+				marvell,function = "gpio";
+			};
+			pmx_led_usb2: pmx-led-usb2 {
+				marvell,pins = "mpp45";
+				marvell,function = "gpio";
+			};
+			pmx_led_usb3: pmx-led-usb3 {
+				marvell,pins = "mpp46";
+				marvell,function = "gpio";
+			};
+			pmx_led_usb4: pmx-led-usb4 {
+				marvell,pins = "mpp47";
+				marvell,function = "gpio";
+			};
+			pmx_led_otb: pmx-led-otb {
+				marvell,pins = "mpp48";
+				marvell,function = "gpio";
+			};
+		};
+		i2c@11000 {
+			status = "okay";
+
+			lm63: lm63@4c {
+				compatible = "national,lm63";
+				reg = <0x4c>;
+			};
+		};
+		serial@12000 {
+			status = "ok";
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+		pinctrl-0 = < &pmx_led_level &pmx_led_power_blue
+			      &pmx_led_power_red &pmx_led_usb1
+			      &pmx_led_usb2 &pmx_led_usb3
+			      &pmx_led_usb4 &pmx_led_otb >;
+		pinctrl-names = "default";
+
+		led-level {
+			label = "led_level";
+			gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+		power-blue {
+			label = "power:blue";
+			gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+			default-state = "keep";
+		};
+		power-red {
+			label = "power:red";
+			gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
+		};
+		usb1 {
+			label = "usb1:blue";
+			gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+		};
+		usb2 {
+			label = "usb2:blue";
+			gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+		};
+		usb3 {
+			label = "usb3:blue";
+			gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+		};
+		usb4 {
+			label = "usb4:blue";
+			gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
+		};
+		otb {
+			label = "otb:blue";
+			gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		pinctrl-0 = < &pmx_button_reset &pmx_button_otb >;
+		pinctrl-names = "default";
+
+		otb {
+			label = "OTB Button";
+			linux,code = <KEY_COPY>;
+			gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
+			debounce-interval = <100>;
+		};
+		reset {
+			label = "Reset";
+			linux,code = <KEY_RESTART>;
+			gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
+			debounce-interval = <100>;
+		};
+	};
+};
+
+&nand {
+	status = "okay";
+
+	partition@0 {
+		label = "uboot";
+		reg = <0x0000000 0xc0000>;
+	};
+
+	partition@a0000 {
+		label = "env";
+		reg = <0xa0000 0x20000>;
+	};
+
+	partition@100000 {
+		label = "zImage";
+		reg = <0x100000 0x300000>;
+	};
+
+	partition@540000 {
+		label = "initrd";
+		reg = <0x540000 0x300000>;
+	};
+
+	partition@980000 {
+		label = "boot";
+		reg = <0x980000 0x1f400000>;
+	};
+};
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy@11 {
+		reg = <11>;
+	};
+};
+
+&eth0 {
+	status = "okay";
+	ethernet0-port@0 {
+		phy-handle = <&ethphy0>;
+	};
+};
+
+&pciec {
+        status = "okay";
+};
+
+&pcie0 {
+	status = "okay";
+};

arch/arm/dts/kirkwood-is2.dts

@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include <dt-bindings/leds/leds-ns2.h>
+#include "kirkwood-ns2-common.dtsi"
+
+/ {
+	model = "LaCie Internet Space v2";
+	compatible = "lacie,inetspace_v2", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x8000000>;
+	};
+
+	ocp@f1000000 {
+		sata@80000 {
+			pinctrl-0 = <&pmx_ns2_sata0>;
+			pinctrl-names = "default";
+			status = "okay";
+			nr-ports = <1>;
+		};
+	};
+
+	ns2-leds {
+		compatible = "lacie,ns2-leds";
+
+		blue-sata {
+			label = "ns2:blue:sata";
+			slow-gpio = <&gpio0 29 0>;
+			cmd-gpio = <&gpio0 30 0>;
+			modes-map = <NS_V2_LED_OFF  1 0
+				     NS_V2_LED_ON   0 1
+				     NS_V2_LED_ON   1 1
+				     NS_V2_LED_SATA 0 0>;
+		};
+	};
+};
+
+&ethphy0 { reg = <8>; };

arch/arm/dts/kirkwood-km_common.dtsi

@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0
+/ {
+	chosen {
+		bootargs = "console=ttyS0,115200n8 earlyprintk";
+		stdout-path = &uart0;
+	};
+
+	ocp@f1000000 {
+		pinctrl: pin-controller@10000 {
+			pinctrl-0 = < &pmx_i2c_gpio_sda &pmx_i2c_gpio_scl >;
+			pinctrl-names = "default";
+
+			pmx_i2c_gpio_sda: pmx-gpio-sda {
+				marvell,pins = "mpp8";
+				marvell,function = "gpio";
+			};
+			pmx_i2c_gpio_scl: pmx-gpio-scl {
+				marvell,pins = "mpp9";
+				marvell,function = "gpio";
+			};
+		};
+
+		serial@12000 {
+			status = "okay";
+		};
+	};
+
+	i2c {
+		compatible = "i2c-gpio";
+		gpios = < &gpio0 8 GPIO_ACTIVE_HIGH		/* sda */
+			  &gpio0 9 GPIO_ACTIVE_HIGH>;		/* scl */
+		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
+	};
+};
+
+&nand {
+	status = "okay";
+	chip-delay = <25>;
+};
+
+&pciec {
+        status = "okay";
+};
+
+&pcie0 {
+	status = "okay";
+};

arch/arm/dts/kirkwood-km_kirkwood.dts

@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "kirkwood.dtsi"
+#include "kirkwood-98dx4122.dtsi"
+#include "kirkwood-km_common.dtsi"
+
+/ {
+	model = "Keymile Kirkwood Reference Design";
+	compatible = "keymile,km_kirkwood", "marvell,kirkwood-98DX4122", "marvell,kirkwood";
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x08000000>;
+	};
+};
+
+&mdio {
+	status = "okay";
+
+	ethphy0: ethernet-phy@0 {
+		reg = <0>;
+	};
+};
+
+&eth0 {
+	status = "okay";
+	ethernet0-port@0 {
+		phy-handle = <&ethphy0>;
+	};
+};

arch/arm/dts/kirkwood-lschlv2.dts

@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "kirkwood-lsxl.dtsi"
+
+/ {
+	model = "Buffalo Linkstation LS-CHLv2";
+	compatible = "buffalo,lschlv2", "buffalo,lsxl", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x4000000>;
+	};
+
+	ocp@f1000000 {
+		serial@12000 {
+			status = "okay";
+		};
+	};
+};

arch/arm/dts/kirkwood-lsxhl.dts

@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "kirkwood-lsxl.dtsi"
+
+/ {
+	model = "Buffalo Linkstation LS-XHL";
+	compatible = "buffalo,lsxhl", "buffalo,lsxl", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x10000000>;
+	};
+
+	ocp@f1000000 {
+		serial@12000 {
+			status = "okay";
+		};
+	};
+};