Prepare v2018.07

Signed-off-by: Tom Rini <trini@konsulko.com>

.travis.yml

@@ -156,8 +156,6 @@ matrix:
           BUILDMAN="arm926ejs -x mx,siemens,atmel"
     - env:
         - BUILDMAN="atmel"
-    - env:
-        - BUILDMAN="aries"
     - env:
           BUILDMAN="boundary engicam toradex"
     - env:
@@ -192,7 +190,7 @@ matrix:
         - BUILDMAN="sun50i"
     - env:
         - JOB="Catch-all ARM"
-          BUILDMAN="arm -x arm11,arm7,arm9,aarch64,atmel,aries,freescale,kirkwood,mvebu,siemens,tegra,uniphier,mx,samsung,sunxi,am33xx,omap,pxa,rockchip,toradex,socfpga,k2,xilinx"
+          BUILDMAN="arm -x arm11,arm7,arm9,aarch64,atmel,freescale,kirkwood,mvebu,siemens,tegra,uniphier,mx,samsung,sunxi,am33xx,omap,pxa,rockchip,toradex,socfpga,k2,xilinx"
     - env:
         - BUILDMAN="sandbox x86"
           TOOLCHAIN="x86_64"

Makefile

@@ -3,7 +3,7 @@
 VERSION = 2018
 PATCHLEVEL = 07
 SUBLEVEL =
-EXTRAVERSION = -rc2
+EXTRAVERSION =
 NAME =
 
 # *DOCUMENTATION*
@@ -263,8 +263,9 @@ HOSTCXXFLAGS = -O2
 # Some Linux distributions (including RHEL7, SLES13, Debian 8) still
 # have older compilers as their default, so we make it explicit for
 # these that our host tools are GNU11 (i.e. C11 w/ GNU extensions).
+CSTD_FLAG := -std=gnu11
 ifeq ($(HOSTOS),linux)
-HOSTCFLAGS += --std=gnu11
+HOSTCFLAGS += $(CSTD_FLAG)
 endif
 
 ifeq ($(HOSTOS),cygwin)
@@ -370,7 +371,7 @@ KBUILD_CPPFLAGS := -D__KERNEL__ -D__UBOOT__
 
 KBUILD_CFLAGS   := -Wall -Wstrict-prototypes \
 		   -Wno-format-security \
-		   -fno-builtin -ffreestanding
+		   -fno-builtin -ffreestanding $(CSTD_FLAG)
 KBUILD_CFLAGS	+= -fshort-wchar
 KBUILD_AFLAGS   := -D__ASSEMBLY__
 

README

@@ -2625,6 +2625,10 @@ FIT uImage format:
 		CONFIG_SPL_NAND_DRIVERS
 		SPL uses normal NAND drivers, not minimal drivers.
 
+		CONFIG_SPL_NAND_IDENT
+		SPL uses the chip ID list to identify the NAND flash.
+		Requires CONFIG_SPL_NAND_BASE.
+
 		CONFIG_SPL_NAND_ECC
 		Include standard software ECC in the SPL
 

arch/arm/Kconfig

@@ -108,6 +108,9 @@ config SYS_ARM_MPU
 # CONFIG_ARM_ERRATA_621766
 # CONFIG_ARM_ERRATA_798870
 # CONFIG_ARM_ERRATA_801819
+# CONFIG_ARM_CORTEX_A8_CVE_2017_5715
+# CONFIG_ARM_CORTEX_A15_CVE_2017_5715
+
 config ARM_ERRATA_430973
 	bool
 
@@ -177,6 +180,12 @@ config ARM_ERRATA_852423
 config ARM_ERRATA_855873
 	bool
 
+config ARM_CORTEX_A8_CVE_2017_5715
+	bool
+
+config ARM_CORTEX_A15_CVE_2017_5715
+	bool
+
 config CPU_ARM720T
 	bool
 	select SYS_CACHE_SHIFT_5

arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c

@@ -15,7 +15,7 @@
 
 #include "mxs_init.h"
 
-static uint32_t dram_vals[] = {
+__weak uint32_t mxs_dram_vals[] = {
 /*
  * i.MX28 DDR2 at 200MHz
  */
@@ -100,11 +100,11 @@ static void initialize_dram_values(void)
 	int i;
 
 	debug("SPL: Setting mx28 board specific SDRAM parameters\n");
-	mxs_adjust_memory_params(dram_vals);
+	mxs_adjust_memory_params(mxs_dram_vals);
 
 	debug("SPL: Applying SDRAM parameters\n");
-	for (i = 0; i < ARRAY_SIZE(dram_vals); i++)
-		writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
+	for (i = 0; i < ARRAY_SIZE(mxs_dram_vals); i++)
+		writel(mxs_dram_vals[i], MXS_DRAM_BASE + (4 * i));
 }
 #else
 static void initialize_dram_values(void)
@@ -112,7 +112,7 @@ static void initialize_dram_values(void)
 	int i;
 
 	debug("SPL: Setting mx23 board specific SDRAM parameters\n");
-	mxs_adjust_memory_params(dram_vals);
+	mxs_adjust_memory_params(mxs_dram_vals);
 
 	/*
 	 * HW_DRAM_CTL27, HW_DRAM_CTL28 and HW_DRAM_CTL35 are not initialized as
@@ -124,10 +124,10 @@ static void initialize_dram_values(void)
 	 * So skip the initialization of these HW_DRAM_CTL registers.
 	 */
 	debug("SPL: Applying SDRAM parameters\n");
-	for (i = 0; i < ARRAY_SIZE(dram_vals); i++) {
+	for (i = 0; i < ARRAY_SIZE(mxs_dram_vals); i++) {
 		if (i == 8 || i == 27 || i == 28 || i == 35)
 			continue;
-		writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
+		writel(mxs_dram_vals[i], MXS_DRAM_BASE + (4 * i));
 	}
 
 	/*

arch/arm/cpu/armv7/start.S

@@ -241,6 +241,14 @@ skip_errata_798870:
 skip_errata_801819:
 #endif
 
+#ifdef CONFIG_ARM_CORTEX_A15_CVE_2017_5715
+	mrc	p15, 0, r0, c1, c0, 1	@ read auxilary control register
+	orr	r0, r0, #1 << 0		@ Enable invalidates of BTB
+	push	{r1-r5}			@ Save the cpu info registers
+	bl	v7_arch_cp15_set_acr
+	pop	{r1-r5}			@ Restore the cpu info - fall through
+#endif
+
 #ifdef CONFIG_ARM_ERRATA_454179
 	mrc	p15, 0, r0, c1, c0, 1	@ Read ACR
 
@@ -252,12 +260,15 @@ skip_errata_801819:
 	pop	{r1-r5}			@ Restore the cpu info - fall through
 #endif
 
-#ifdef CONFIG_ARM_ERRATA_430973
+#if defined(CONFIG_ARM_ERRATA_430973) || defined (CONFIG_ARM_CORTEX_A8_CVE_2017_5715)
 	mrc	p15, 0, r0, c1, c0, 1	@ Read ACR
 
+#ifdef CONFIG_ARM_CORTEX_A8_CVE_2017_5715
+	orr	r0, r0, #(0x1 << 6)	@ Set IBE bit always to enable OS WA
+#else
 	cmp	r2, #0x21		@ Only on < r2p1
 	orrlt	r0, r0, #(0x1 << 6)	@ Set IBE bit
-
+#endif
 	push	{r1-r5}			@ Save the cpu info registers
 	bl	v7_arch_cp15_set_acr
 	pop	{r1-r5}			@ Restore the cpu info - fall through

arch/arm/cpu/armv8/generic_timer.c

@@ -20,27 +20,70 @@ unsigned long get_tbclk(void)
 	return cntfrq;
 }
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008585
 /*
- * Generic timer implementation of timer_read_counter()
+ * FSL erratum A-008585 says that the ARM generic timer counter "has the
+ * potential to contain an erroneous value for a small number of core
+ * clock cycles every time the timer value changes".
+ * This sometimes leads to a consecutive counter read returning a lower
+ * value than the previous one, thus reporting the time to go backwards.
+ * The workaround is to read the counter twice and only return when the value
+ * was the same in both reads.
+ * Assumes that the CPU runs in much higher frequency than the timer.
  */
 unsigned long timer_read_counter(void)
 {
 	unsigned long cntpct;
-#ifdef CONFIG_SYS_FSL_ERRATUM_A008585
-	/* This erratum number needs to be confirmed to match ARM document */
 	unsigned long temp;
-#endif
+
 	isb();
 	asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct));
-#ifdef CONFIG_SYS_FSL_ERRATUM_A008585
 	asm volatile("mrs %0, cntpct_el0" : "=r" (temp));
 	while (temp != cntpct) {
 		asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct));
 		asm volatile("mrs %0, cntpct_el0" : "=r" (temp));
 	}
-#endif
+
 	return cntpct;
 }
+#elif CONFIG_SUNXI_A64_TIMER_ERRATUM
+/*
+ * This erratum sometimes flips the lower 11 bits of the counter value
+ * to all 0's or all 1's, leading to jumps forwards or backwards.
+ * Backwards jumps might be interpreted all roll-overs and be treated as
+ * huge jumps forward.
+ * The workaround is to check whether the lower 11 bits of the counter are
+ * all 0 or all 1, then discard this value and read again.
+ * This occasionally discards valid values, but will catch all erroneous
+ * reads and fixes the problem reliably. Also this mostly requires only a
+ * single read, so does not have any significant overhead.
+ * The algorithm was conceived by Samuel Holland.
+ */
+unsigned long timer_read_counter(void)
+{
+	unsigned long cntpct;
+
+	isb();
+	do {
+		asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct));
+	} while (((cntpct + 1) & GENMASK(10, 0)) <= 1);
+
+	return cntpct;
+}
+#else
+/*
+ * timer_read_counter() using the Arm Generic Timer (aka arch timer).
+ */
+unsigned long timer_read_counter(void)
+{
+	unsigned long cntpct;
+
+	isb();
+	asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct));
+
+	return cntpct;
+}
+#endif
 
 uint64_t get_ticks(void)
 {

arch/arm/dts/Makefile

@@ -189,7 +189,6 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=				\
 	socfpga_arria5_socdk.dtb			\
 	socfpga_arria10_socdk_sdmmc.dtb			\
 	socfpga_cyclone5_is1.dtb			\
-	socfpga_cyclone5_mcvevk.dtb			\
 	socfpga_cyclone5_socdk.dtb			\
 	socfpga_cyclone5_dbm_soc1.dtb			\
 	socfpga_cyclone5_de0_nano_soc.dtb		\
@@ -358,6 +357,7 @@ dtb-$(CONFIG_MACH_SUN8I_A83T) += \
 	sun8i-a83t-tbs-a711.dts
 dtb-$(CONFIG_MACH_SUN8I_H3) += \
 	sun8i-h2-plus-libretech-all-h3-cc.dtb \
+	sun8i-h2-plus-orangepi-r1.dtb \
 	sun8i-h2-plus-orangepi-zero.dtb \
 	sun8i-h3-bananapi-m2-plus.dtb \
 	sun8i-h3-libretech-all-h3-cc.dtb \
@@ -381,6 +381,7 @@ dtb-$(CONFIG_MACH_SUN50I_H5) += \
 	sun50i-h5-libretech-all-h3-cc.dtb \
 	sun50i-h5-nanopi-neo2.dtb \
 	sun50i-h5-nanopi-neo-plus2.dtb \
+	sun50i-h5-orangepi-zero-plus.dtb \
 	sun50i-h5-orangepi-pc2.dtb \
 	sun50i-h5-orangepi-prime.dtb \
 	sun50i-h5-orangepi-zero-plus2.dtb
@@ -425,7 +426,7 @@ dtb-$(CONFIG_MX6SX) += \
 	imx6sx-sdb.dtb
 
 dtb-$(CONFIG_MX6UL) += \
-	imx6ul-geam-kit.dtb \
+	imx6ul-geam.dtb \
 	imx6ul-isiot-emmc.dtb \
 	imx6ul-isiot-nand.dtb \
 	imx6ul-opos6uldev.dtb
@@ -511,9 +512,6 @@ dtb-$(CONFIG_TARGET_SAMA5D3XEK) += \
 dtb-$(CONFIG_TARGET_SAMA5D3_XPLAINED) += \
 	at91-sama5d3_xplained.dtb
 
-dtb-$(CONFIG_TARGET_MA5D4EK) += \
-	at91-sama5d4_ma5d4evk.dts.dtb
-
 dtb-$(CONFIG_TARGET_SAMA5D4EK) += \
 	at91-sama5d4ek.dtb
 

arch/arm/dts/at91-sama5d4_ma5d4.dtsi

@@ -1,142 +0,0 @@
-/*
- * Copyright (C) 2015 Marek Vasut <marex@denx.de>
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include "sama5d4.dtsi"
-
-/ {
-	model = "Aries/DENX MA5D4";
-	compatible = "aries,ma5d4", "denx,ma5d4", "atmel,sama5d4", "atmel,sama5";
-
-	memory {
-		reg = <0x20000000 0x10000000>;
-	};
-
-	clocks {
-		slow_xtal {
-			clock-frequency = <32768>;
-		};
-
-		main_xtal {
-			clock-frequency = <12000000>;
-		};
-
-		clk20m: clk20m {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <20000000>;
-			clock-output-names = "clk20m";
-		};
-	};
-
-	ahb {
-		apb {
-			mmc0: mmc@f8000000 {
-				pinctrl-names = "default";
-				pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>;
-				vmmc-supply = <&vcc_mmc0_reg>;
-				vqmmc-supply = <&vcc_3v3_reg>;
-				status = "okay";
-				slot@0 {
-					reg = <0>;
-					bus-width = <8>;
-					broken-cd;
-				};
-			};
-
-			spi0: spi@f8010000 {
-				cs-gpios = <&pioC 3 0>, <0>, <0>, <0>;
-				status = "okay";
-
-				m25p80@0 {
-					compatible = "atmel,at25df321a";
-					spi-max-frequency = <50000000>;
-					reg = <0>;
-				};
-			};
-
-			i2c0: i2c@f8014000 {
-				status = "okay";
-			};
-
-			spi1: spi@fc018000 {
-				cs-gpios = <&pioB 22 0>, <&pioB 23 0>, <0>, <0>;
-				status = "okay";
-
-				can0: can@0 {
-					compatible = "microchip,mcp2515";
-					reg = <0>;
-					clocks = <&clk20m>;
-					interrupt-parent = <&pioE>;
-					interrupts = <6 IRQ_TYPE_EDGE_RISING>;
-					spi-max-frequency = <10000000>;
-				};
-
-				can1: can@1 {
-					compatible = "microchip,mcp2515";
-					reg = <1>;
-					clocks = <&clk20m>;
-					interrupt-parent = <&pioE>;
-					interrupts = <7 IRQ_TYPE_EDGE_RISING>;
-					spi-max-frequency = <10000000>;
-				};
-			};
-
-			tcb2: timer@fc024000 {
-				timer@0 {
-					compatible = "atmel,tcb-timer";
-					reg = <0>;
-				};
-
-				timer@1 {
-					compatible = "atmel,tcb-timer";
-					reg = <1>;
-				};
-			};
-
-			adc0: adc@fc034000 {
-				pinctrl-names = "default";
-				pinctrl-0 = <
-					/* external trigger conflicts with USBA_VBUS */
-					&pinctrl_adc0_ad0
-					&pinctrl_adc0_ad1
-					&pinctrl_adc0_ad2
-					&pinctrl_adc0_ad3
-					&pinctrl_adc0_ad4
-					>;
-				atmel,adc-vref = <3300>;
-				status = "okay";
-			};
-
-			watchdog@fc068640 {
-				status = "okay";
-			};
-		};
-	};
-
-	vcc_3v3_reg: fixedregulator_3v3 {
-		compatible = "regulator-fixed";
-		regulator-name = "VCC 3V3";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	vcc_mmc0_reg: fixedregulator_mmc0 {
-		compatible = "regulator-fixed";
-		gpio = <&pioE 15 GPIO_ACTIVE_HIGH>;
-		regulator-name = "RST_n MCI0";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		vin-supply = <&vcc_3v3_reg>;
-		regulator-boot-on;
-	};
-};

arch/arm/dts/at91-sama5d4_ma5d4evk.dts

@@ -1,149 +0,0 @@
-/*
- * Copyright (C) 2015 Marek Vasut <marex@denx.de>
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-/dts-v1/;
-#include "at91-sama5d4_ma5d4.dtsi"
-
-/ {
-	model = "Aries/DENX MA5D4EVK";
-	compatible = "aries,ma5d4evk", "denx,ma5d4evk", "atmel,sama5d4", "atmel,sama5";
-
-	chosen {
-		stdout-path = "serial3:115200n8";
-	};
-
-	ahb {
-		apb {
-			hlcdc: hlcdc@f0000000 {
-				status = "okay";
-
-				hlcdc-display-controller {
-					pinctrl-names = "default";
-					pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>;
-
-					port@0 {
-						hlcdc_panel_output: endpoint@0 {
-							reg = <0>;
-							remote-endpoint = <&panel_input>;
-						};
-					};
-				};
-
-			};
-
-			macb0: ethernet@f8020000 {
-				phy-mode = "rmii";
-				status = "okay";
-
-				phy0: ethernet-phy@0 {
-					reg = <0>;
-				};
-			};
-
-			usart0: serial@f802c000 {
-				status = "okay";
-			};
-
-			usart1: serial@f8030000 {
-				status = "okay";
-			};
-
-			mmc1: mmc@fc000000 {
-				pinctrl-names = "default";
-				pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>;
-				vmmc-supply = <&vcc_mmc1_reg>;
-				vqmmc-supply = <&vcc_3v3_reg>;
-				status = "okay";
-				slot@0 {
-					reg = <0>;
-					bus-width = <4>;
-					cd-gpios = <&pioE 5 0>;
-				};
-			};
-
-			adc0: adc@fc034000 {
-				atmel,adc-ts-wires = <4>;
-				atmel,adc-ts-pressure-threshold = <10000>;
-			};
-
-
-			pinctrl@fc06a000 {
-				board {
-					pinctrl_mmc1_cd: mmc1_cd {
-						atmel,pins = <AT91_PIOE 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
-					};
-					pinctrl_usba_vbus: usba_vbus {
-						atmel,pins =
-							<AT91_PIOE 31 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>;
-					};
-				};
-			};
-		};
-	};
-
-	backlight: backlight {
-		compatible = "pwm-backlight";
-		brightness-levels = <0 4 8 16 32 64 128 255>;
-		default-brightness-level = <6>;
-		status = "okay";
-	};
-
-	leds {
-		compatible = "gpio-leds";
-		status = "okay";
-
-		user1 {
-			label = "user1";
-			gpios = <&pioD 28 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "heartbeat";
-		};
-
-		user2 {
-			label = "user2";
-			gpios = <&pioD 29 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "heartbeat";
-		};
-
-		user3 {
-			label = "user3";
-			gpios = <&pioD 30 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "heartbeat";
-		};
-	};
-
-	panel: panel {
-		/* Actually Ampire 800480R2 */
-		compatible = "foxlink,fl500wvr00-a0t", "simple-panel";
-		backlight = <&backlight>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "okay";
-
-		port@0 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			panel_input: endpoint@0 {
-				reg = <0>;
-				remote-endpoint = <&hlcdc_panel_output>;
-			};
-		};
-	};
-
-	vcc_mmc1_reg: fixedregulator_mmc1 {
-		compatible = "regulator-fixed";
-		gpio = <&pioE 17 GPIO_ACTIVE_LOW>;
-		regulator-name = "VDD MCI1";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		vin-supply = <&vcc_3v3_reg>;
-	};
-};

arch/arm/dts/imx53-kp.dts

@@ -86,6 +86,10 @@
 				MX53_PAD_PATA_DA_2__GPIO7_8 0x1e4
 				/* BOOSTER_OFF */
 				MX53_PAD_EIM_CS0__GPIO2_23 0x1e4
+				/* LCD BACKLIGHT */
+				MX53_PAD_GPIO_1__GPIO1_1 0x1e4
+				/* KEY1 GPIO */
+				MX53_PAD_EIM_RW__GPIO2_26 0x1e4
 			>;
 		};
 

arch/arm/dts/imx7-colibri.dts

@@ -16,6 +16,15 @@
 	};
 };
 
+&gpmi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpmi_nand>;
+	fsl,use-minimum-ecc;
+	nand-on-flash-bbt;
+	nand-ecc-mode = "hw";
+	status = "okay";
+};
+
 &i2c1 {
 	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c1>;
@@ -48,6 +57,25 @@
 };
 
 &iomuxc {
+	pinctrl_gpmi_nand: gpmi-nand-grp {
+		fsl,pins = <
+			MX7D_PAD_SD3_CLK__NAND_CLE		0x71
+			MX7D_PAD_SD3_CMD__NAND_ALE		0x71
+			MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B	0x71
+			MX7D_PAD_SAI1_TX_DATA__NAND_READY_B	0x74
+			MX7D_PAD_SD3_STROBE__NAND_RE_B		0x71
+			MX7D_PAD_SD3_RESET_B__NAND_WE_B		0x71
+			MX7D_PAD_SD3_DATA0__NAND_DATA00		0x71
+			MX7D_PAD_SD3_DATA1__NAND_DATA01		0x71
+			MX7D_PAD_SD3_DATA2__NAND_DATA02		0x71
+			MX7D_PAD_SD3_DATA3__NAND_DATA03		0x71
+			MX7D_PAD_SD3_DATA4__NAND_DATA04		0x71
+			MX7D_PAD_SD3_DATA5__NAND_DATA05		0x71
+			MX7D_PAD_SD3_DATA6__NAND_DATA06		0x71
+			MX7D_PAD_SD3_DATA7__NAND_DATA07		0x71
+		>;
+	};
+
 	pinctrl_i2c4: i2c4-grp {
 		fsl,pins = <
 			MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA	0x4000007f

arch/arm/dts/imx7s.dtsi

@@ -42,6 +42,7 @@
  */
 
 #include <dt-bindings/clock/imx7d-clock.h>
+#include <dt-bindings/power/imx7-power.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -57,7 +58,7 @@
 	 * Also for U-Boot there must be a pre-existing /memory node.
 	 */
 	chosen {};
-	memory { device_type = "memory"; reg = <0 0>; };
+	memory { device_type = "memory"; };
 
 	aliases {
 		gpio0 = &gpio1;
@@ -115,11 +116,77 @@
 		clock-output-names = "osc";
 	};
 
+	usbphynop1: usbphynop1 {
+		compatible = "usb-nop-xceiv";
+		clocks = <&clks IMX7D_USB_PHY1_CLK>;
+		clock-names = "main_clk";
+		#phy-cells = <0>;
+	};
+
+	usbphynop3: usbphynop3 {
+		compatible = "usb-nop-xceiv";
+		clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
+		clock-names = "main_clk";
+		#phy-cells = <0>;
+	};
+
+	pmu {
+		compatible = "arm,cortex-a7-pmu";
+		interrupt-parent = <&gpc>;
+		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&cpu0>;
+	};
+
+	replicator {
+		/*
+		 * non-configurable replicators don't show up on the
+		 * AMBA bus.  As such no need to add "arm,primecell"
+		 */
+		compatible = "arm,coresight-replicator";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+				/* replicator output ports */
+			port@0 {
+				reg = <0>;
+				replicator_out_port0: endpoint {
+					remote-endpoint = <&tpiu_in_port>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				replicator_out_port1: endpoint {
+					remote-endpoint = <&etr_in_port>;
+				};
+			};
+
+			/* replicator input port */
+			port@2 {
+				reg = <0>;
+				replicator_in_port0: endpoint {
+					slave-mode;
+					remote-endpoint = <&etf_out_port>;
+				};
+			};
+		};
+	};
+
+	timer {
+		compatible = "arm,armv7-timer";
+		interrupt-parent = <&intc>;
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+
 	soc {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "simple-bus";
-		interrupt-parent = <&intc>;
+		interrupt-parent = <&gpc>;
 		ranges;
 
 		funnel@30041000 {
@@ -259,62 +326,18 @@
 			};
 		};
 
-		replicator {
-			/*
-			 * non-configurable replicators don't show up on the
-			 * AMBA bus.  As such no need to add "arm,primecell"
-			 */
-			compatible = "arm,coresight-replicator";
-
-			ports {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				/* replicator output ports */
-				port@0 {
-					reg = <0>;
-					replicator_out_port0: endpoint {
-						remote-endpoint = <&tpiu_in_port>;
-					};
-				};
-
-				port@1 {
-					reg = <1>;
-					replicator_out_port1: endpoint {
-						remote-endpoint = <&etr_in_port>;
-					};
-				};
-
-				/* replicator input port */
-				port@2 {
-					reg = <0>;
-					replicator_in_port0: endpoint {
-						slave-mode;
-						remote-endpoint = <&etf_out_port>;
-					};
-				};
-			};
-		};
-
 		intc: interrupt-controller@31001000 {
 			compatible = "arm,cortex-a7-gic";
 			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 			#interrupt-cells = <3>;
 			interrupt-controller;
+			interrupt-parent = <&intc>;
 			reg = <0x31001000 0x1000>,
 			      <0x31002000 0x2000>,
 			      <0x31004000 0x2000>,
 			      <0x31006000 0x2000>;
 		};
 
-		timer {
-			compatible = "arm,armv7-timer";
-			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-				     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-				     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-				     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
-		};
-
 		aips1: aips-bus@30000000 {
 			compatible = "fsl,aips-bus", "simple-bus";
 			#address-cells = <1>;
@@ -482,20 +505,49 @@
 				status = "disabled";
 			};
 
+			kpp: kpp@30320000 {
+				compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp";
+				reg = <0x30320000 0x10000>;
+				interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX7D_KPP_ROOT_CLK>;
+				status = "disabled";
+			};
+
 			iomuxc: iomuxc@30330000 {
 				compatible = "fsl,imx7d-iomuxc";
 				reg = <0x30330000 0x10000>;
 			};
 
 			gpr: iomuxc-gpr@30340000 {
-				compatible = "fsl,imx7d-iomuxc-gpr", "syscon";
+				compatible = "fsl,imx7d-iomuxc-gpr",
+					"fsl,imx6q-iomuxc-gpr", "syscon";
 				reg = <0x30340000 0x10000>;
 			};
 
 			ocotp: ocotp-ctrl@30350000 {
+				#address-cells = <1>;
+				#size-cells = <1>;
 				compatible = "fsl,imx7d-ocotp", "syscon";
 				reg = <0x30350000 0x10000>;
 				clocks = <&clks IMX7D_OCOTP_CLK>;
+
+				tempmon_calib: calib@3c {
+					reg = <0x3c 0x4>;
+				};
+
+				tempmon_temp_grade: temp-grade@10 {
+					reg = <0x10 0x4>;
+				};
+			};
+
+			tempmon: tempmon {
+				compatible = "fsl,imx7d-tempmon";
+				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+				fsl,tempmon =<&anatop>;
+				nvmem-cells = <&tempmon_calib>,
+					<&tempmon_temp_grade>;
+				nvmem-cell-names = "calib", "temp_grade";
+				clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>;
 			};
 
 			anatop: anatop@30360000 {
@@ -504,8 +556,11 @@
 				reg = <0x30360000 0x10000>;
 				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 					<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
 
-				reg_1p0d: regulator-vdd1p0d {
+				reg_1p0d: regulator-vdd1p0d@30360210 {
+					reg = <0x30360210>;
 					compatible = "fsl,anatop-regulator";
 					regulator-name = "vdd1p0d";
 					regulator-min-microvolt = <800000>;
@@ -516,6 +571,7 @@
 					anatop-min-bit-val = <8>;
 					anatop-min-voltage = <800000>;
 					anatop-max-voltage = <1200000>;
+					anatop-enable-bit = <0>;
 				};
 			};
 
@@ -529,12 +585,15 @@
 					offset = <0x34>;
 					interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 						     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&clks IMX7D_SNVS_CLK>;
+					clock-names = "snvs-rtc";
 				};
 
 				snvs_poweroff: snvs-poweroff {
 					compatible = "syscon-poweroff";
 					regmap = <&snvs>;
 					offset = <0x38>;
+					value = <0x60>;
 					mask = <0x60>;
 				};
 
@@ -558,11 +617,32 @@
 			};
 
 			src: src@30390000 {
-				compatible = "fsl,imx7d-src", "fsl,imx51-src", "syscon";
+				compatible = "fsl,imx7d-src", "syscon";
 				reg = <0x30390000 0x10000>;
 				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 				#reset-cells = <1>;
 			};
+
+			gpc: gpc@303a0000 {
+				compatible = "fsl,imx7d-gpc";
+				reg = <0x303a0000 0x10000>;
+				interrupt-controller;
+				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+				#interrupt-cells = <3>;
+				interrupt-parent = <&intc>;
+				#power-domain-cells = <1>;
+
+				pgc {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					pgc_pcie_phy: pgc-power-domain@1 {
+						#power-domain-cells = <0>;
+						reg = <1>;
+						power-supply = <&reg_1p0d>;
+					};
+				};
+			};
 		};
 
 		aips2: aips-bus@30400000 {
@@ -609,7 +689,7 @@
 				clocks = <&clks IMX7D_PWM1_ROOT_CLK>,
 					 <&clks IMX7D_PWM1_ROOT_CLK>;
 				clock-names = "ipg", "per";
-				#pwm-cells = <2>;
+				#pwm-cells = <3>;
 				status = "disabled";
 			};
 
@@ -620,7 +700,7 @@
 				clocks = <&clks IMX7D_PWM2_ROOT_CLK>,
 					 <&clks IMX7D_PWM2_ROOT_CLK>;
 				clock-names = "ipg", "per";
-				#pwm-cells = <2>;
+				#pwm-cells = <3>;
 				status = "disabled";
 			};
 
@@ -631,7 +711,7 @@
 				clocks = <&clks IMX7D_PWM3_ROOT_CLK>,
 					 <&clks IMX7D_PWM3_ROOT_CLK>;
 				clock-names = "ipg", "per";
-				#pwm-cells = <2>;
+				#pwm-cells = <3>;
 				status = "disabled";
 			};
 
@@ -642,7 +722,7 @@
 				clocks = <&clks IMX7D_PWM4_ROOT_CLK>,
 					 <&clks IMX7D_PWM4_ROOT_CLK>;
 				clock-names = "ipg", "per";
-				#pwm-cells = <2>;
+				#pwm-cells = <3>;
 				status = "disabled";
 			};
 
@@ -664,118 +744,156 @@
 			reg = <0x30800000 0x400000>;
 			ranges;
 
-			ecspi1: ecspi@30820000 {
+			spba-bus@30800000 {
+				compatible = "fsl,spba-bus", "simple-bus";
 				#address-cells = <1>;
-				#size-cells = <0>;
-				compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
-				reg = <0x30820000 0x10000>;
-				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
-					<&clks IMX7D_ECSPI1_ROOT_CLK>;
-				clock-names = "ipg", "per";
-				status = "disabled";
+				#size-cells = <1>;
+				reg = <0x30800000 0x100000>;
+				ranges;
+
+				ecspi1: ecspi@30820000 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
+					reg = <0x30820000 0x10000>;
+					interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
+						<&clks IMX7D_ECSPI1_ROOT_CLK>;
+					clock-names = "ipg", "per";
+					status = "disabled";
+				};
+
+				ecspi2: ecspi@30830000 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
+					reg = <0x30830000 0x10000>;
+					interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
+						<&clks IMX7D_ECSPI2_ROOT_CLK>;
+					clock-names = "ipg", "per";
+					status = "disabled";
+				};
+
+				ecspi3: ecspi@30840000 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
+					reg = <0x30840000 0x10000>;
+					interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
+						<&clks IMX7D_ECSPI3_ROOT_CLK>;
+					clock-names = "ipg", "per";
+					status = "disabled";
+				};
+
+				uart1: serial@30860000 {
+					compatible = "fsl,imx7d-uart",
+						     "fsl,imx6q-uart";
+					reg = <0x30860000 0x10000>;
+					interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&clks IMX7D_UART1_ROOT_CLK>,
+						<&clks IMX7D_UART1_ROOT_CLK>;
+					clock-names = "ipg", "per";
+					status = "disabled";
+				};
+
+				uart2: serial@30890000 {
+					compatible = "fsl,imx7d-uart",
+						     "fsl,imx6q-uart";
+					reg = <0x30890000 0x10000>;
+					interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&clks IMX7D_UART2_ROOT_CLK>,
+						<&clks IMX7D_UART2_ROOT_CLK>;
+					clock-names = "ipg", "per";
+					status = "disabled";
+				};
+
+				uart3: serial@30880000 {
+					compatible = "fsl,imx7d-uart",
+						     "fsl,imx6q-uart";
+					reg = <0x30880000 0x10000>;
+					interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&clks IMX7D_UART3_ROOT_CLK>,
+						<&clks IMX7D_UART3_ROOT_CLK>;
+					clock-names = "ipg", "per";
+					status = "disabled";
+				};
+
+				sai1: sai@308a0000 {
+					#sound-dai-cells = <0>;
+					compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
+					reg = <0x308a0000 0x10000>;
+					interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&clks IMX7D_SAI1_IPG_CLK>,
+						 <&clks IMX7D_SAI1_ROOT_CLK>,
+						 <&clks IMX7D_CLK_DUMMY>,
+						 <&clks IMX7D_CLK_DUMMY>;
+					clock-names = "bus", "mclk1", "mclk2", "mclk3";
+					dma-names = "rx", "tx";
+					dmas = <&sdma 8 24 0>, <&sdma 9 24 0>;
+					status = "disabled";
+				};
+
+				sai2: sai@308b0000 {
+					#sound-dai-cells = <0>;
+					compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
+					reg = <0x308b0000 0x10000>;
+					interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&clks IMX7D_SAI2_IPG_CLK>,
+						 <&clks IMX7D_SAI2_ROOT_CLK>,
+						 <&clks IMX7D_CLK_DUMMY>,
+						 <&clks IMX7D_CLK_DUMMY>;
+					clock-names = "bus", "mclk1", "mclk2", "mclk3";
+					dma-names = "rx", "tx";
+					dmas = <&sdma 10 24 0>, <&sdma 11 24 0>;
+					status = "disabled";
+				};
+
+				sai3: sai@308c0000 {
+					#sound-dai-cells = <0>;
+					compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
+					reg = <0x308c0000 0x10000>;
+					interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&clks IMX7D_SAI3_IPG_CLK>,
+						 <&clks IMX7D_SAI3_ROOT_CLK>,
+						 <&clks IMX7D_CLK_DUMMY>,
+						 <&clks IMX7D_CLK_DUMMY>;
+					clock-names = "bus", "mclk1", "mclk2", "mclk3";
+					dma-names = "rx", "tx";
+					dmas = <&sdma 12 24 0>, <&sdma 13 24 0>;
+					status = "disabled";
+				};
 			};
 
-			ecspi2: ecspi@30830000 {
+			crypto: caam@30900000 {
+				compatible = "fsl,sec-v4.0";
 				#address-cells = <1>;
-				#size-cells = <0>;
-				compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
-				reg = <0x30830000 0x10000>;
-				interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
-					<&clks IMX7D_ECSPI2_ROOT_CLK>;
-				clock-names = "ipg", "per";
-				status = "disabled";
-			};
+				#size-cells = <1>;
+				reg = <0x30900000 0x40000>;
+				ranges = <0 0x30900000 0x40000>;
+				interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX7D_CAAM_CLK>,
+					 <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
+				clock-names = "ipg", "aclk";
 
-			ecspi3: ecspi@30840000 {
-				#address-cells = <1>;
-				#size-cells = <0>;
-				compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
-				reg = <0x30840000 0x10000>;
-				interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
-					<&clks IMX7D_ECSPI3_ROOT_CLK>;
-				clock-names = "ipg", "per";
-				status = "disabled";
-			};
+				sec_jr0: jr0@1000 {
+					compatible = "fsl,sec-v4.0-job-ring";
+					reg = <0x1000 0x1000>;
+					interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+				};
 
-			uart1: serial@30860000 {
-				compatible = "fsl,imx7d-uart",
-					     "fsl,imx6q-uart";
-				reg = <0x30860000 0x10000>;
-				interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clks IMX7D_UART1_ROOT_CLK>,
-					<&clks IMX7D_UART1_ROOT_CLK>;
-				clock-names = "ipg", "per";
-				status = "disabled";
-			};
+				sec_jr1: jr1@2000 {
+					compatible = "fsl,sec-v4.0-job-ring";
+					reg = <0x2000 0x1000>;
+					interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+				};
 
-			uart2: serial@30890000 {
-				compatible = "fsl,imx7d-uart",
-					     "fsl,imx6q-uart";
-				reg = <0x30890000 0x10000>;
-				interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clks IMX7D_UART2_ROOT_CLK>,
-					<&clks IMX7D_UART2_ROOT_CLK>;
-				clock-names = "ipg", "per";
-				status = "disabled";
-			};
-
-			uart3: serial@30880000 {
-				compatible = "fsl,imx7d-uart",
-					     "fsl,imx6q-uart";
-				reg = <0x30880000 0x10000>;
-				interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clks IMX7D_UART3_ROOT_CLK>,
-					<&clks IMX7D_UART3_ROOT_CLK>;
-				clock-names = "ipg", "per";
-				status = "disabled";
-			};
-
-			sai1: sai@308a0000 {
-				#sound-dai-cells = <0>;
-				compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
-				reg = <0x308a0000 0x10000>;
-				interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clks IMX7D_SAI1_IPG_CLK>,
-					 <&clks IMX7D_SAI1_ROOT_CLK>,
-					 <&clks IMX7D_CLK_DUMMY>,
-					 <&clks IMX7D_CLK_DUMMY>;
-				clock-names = "bus", "mclk1", "mclk2", "mclk3";
-				dma-names = "rx", "tx";
-				dmas = <&sdma 8 24 0>, <&sdma 9 24 0>;
-				status = "disabled";
-			};
-
-			sai2: sai@308b0000 {
-				#sound-dai-cells = <0>;
-				compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
-				reg = <0x308b0000 0x10000>;
-				interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clks IMX7D_SAI2_IPG_CLK>,
-					 <&clks IMX7D_SAI2_ROOT_CLK>,
-					 <&clks IMX7D_CLK_DUMMY>,
-					 <&clks IMX7D_CLK_DUMMY>;
-				clock-names = "bus", "mclk1", "mclk2", "mclk3";
-				dma-names = "rx", "tx";
-				dmas = <&sdma 10 24 0>, <&sdma 11 24 0>;
-				status = "disabled";
-			};
-
-			sai3: sai@308c0000 {
-				#sound-dai-cells = <0>;
-				compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
-				reg = <0x308c0000 0x10000>;
-				interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clks IMX7D_SAI3_IPG_CLK>,
-					 <&clks IMX7D_SAI3_ROOT_CLK>,
-					 <&clks IMX7D_CLK_DUMMY>,
-					 <&clks IMX7D_CLK_DUMMY>;
-				clock-names = "bus", "mclk1", "mclk2", "mclk3";
-				dma-names = "rx", "tx";
-				dmas = <&sdma 12 24 0>, <&sdma 13 24 0>;
-				status = "disabled";
+				sec_jr2: jr1@3000 {
+					compatible = "fsl,sec-v4.0-job-ring";
+					reg = <0x3000 0x1000>;
+					interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+				};
 			};
 
 			flexcan1: can@30a00000 {
@@ -918,24 +1036,12 @@
 				reg = <0x30b30200 0x200>;
 			};
 
-			usbphynop1: usbphynop1 {
-				compatible = "usb-nop-xceiv";
-				clocks = <&clks IMX7D_USB_PHY1_CLK>;
-				clock-names = "main_clk";
-			};
-
-			usbphynop3: usbphynop3 {
-				compatible = "usb-nop-xceiv";
-				clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
-				clock-names = "main_clk";
-			};
-
 			usdhc1: usdhc@30b40000 {
 				compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
 				reg = <0x30b40000 0x10000>;
 				interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clks IMX7D_CLK_DUMMY>,
-					<&clks IMX7D_CLK_DUMMY>,
+				clocks = <&clks IMX7D_IPG_ROOT_CLK>,
+					<&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
 					<&clks IMX7D_USDHC1_ROOT_CLK>;
 				clock-names = "ipg", "ahb", "per";
 				bus-width = <4>;
@@ -946,8 +1052,8 @@
 				compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
 				reg = <0x30b50000 0x10000>;
 				interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clks IMX7D_CLK_DUMMY>,
-					<&clks IMX7D_CLK_DUMMY>,
+				clocks = <&clks IMX7D_IPG_ROOT_CLK>,
+					<&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
 					<&clks IMX7D_USDHC2_ROOT_CLK>;
 				clock-names = "ipg", "ahb", "per";
 				bus-width = <4>;
@@ -958,8 +1064,8 @@
 				compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
 				reg = <0x30b60000 0x10000>;
 				interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clks IMX7D_CLK_DUMMY>,
-					<&clks IMX7D_CLK_DUMMY>,
+				clocks = <&clks IMX7D_IPG_ROOT_CLK>,
+					<&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
 					<&clks IMX7D_USDHC3_ROOT_CLK>;
 				clock-names = "ipg", "ahb", "per";
 				bus-width = <4>;
@@ -980,9 +1086,11 @@
 			fec1: ethernet@30be0000 {
 				compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
 				reg = <0x30be0000 0x10000>;
-				interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+				interrupt-names = "int0", "int1", "int2", "pps";
+				interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 					<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
-					<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+					<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
 					<&clks IMX7D_ENET_AXI_ROOT_CLK>,
 					<&clks IMX7D_ENET1_TIME_ROOT_CLK>,
@@ -995,5 +1103,36 @@
 				status = "disabled";
 			};
 		};
+
+		dma_apbh: dma-apbh@33000000 {
+			compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
+			reg = <0x33000000 0x2000>;
+			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
+			#dma-cells = <1>;
+			dma-channels = <4>;
+			clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
+		};
+
+		gpmi: gpmi-nand@33002000{
+			compatible = "fsl,imx7d-gpmi-nand";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
+			reg-names = "gpmi-nand", "bch";
+			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "bch";
+			clocks = <&clks IMX7D_NAND_RAWNAND_CLK>,
+				<&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
+			clock-names = "gpmi_io", "gpmi_bch_apb";
+			dmas = <&dma_apbh 0>;
+			dma-names = "rx-tx";
+			status = "disabled";
+			assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>;
+			assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>;
+		};
 	};
 };

arch/arm/dts/r8a77970-eagle.dts

@@ -39,13 +39,13 @@
 	phy-handle = <&phy0>;
 	phy-mode = "rgmii-id";
 	status = "okay";
-	reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
 
 	phy0: ethernet-phy@0 {
 		rxc-skew-ps = <1500>;
 		reg = <0>;
 		interrupt-parent = <&gpio1>;
 		interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
+		reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
 	};
 };
 

arch/arm/dts/r8a77990-ebisu.dts

@@ -28,6 +28,24 @@
 		/* first 128MB is reserved for secure area. */
 		reg = <0x0 0x48000000 0x0 0x38000000>;
 	};
+
+	reg_1p8v: regulator0 {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-1.8V";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	reg_3p3v: regulator1 {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
 };
 
 &avb {
@@ -71,6 +89,18 @@
 		groups = "scif_clk_a";
 		function = "scif_clk";
 	};
+
+	sdhi3_pins: sd2 {
+		groups = "sdhi3_data8", "sdhi3_ctrl";
+		function = "sdhi3";
+		power-source = <1800>;
+	};
+
+	sdhi3_pins_uhs: sd2_uhs {
+		groups = "sdhi3_data8", "sdhi3_ctrl";
+		function = "sdhi3";
+		power-source = <1800>;
+	};
 };
 
 &sdhi0 {
@@ -82,7 +112,15 @@
 };
 
 &sdhi3 {
+	/* used for on-board 8bit eMMC */
+	pinctrl-0 = <&sdhi3_pins>;
+	pinctrl-1 = <&sdhi3_pins_uhs>;
+	pinctrl-names = "default", "state_uhs";
+
+	vmmc-supply = <&reg_3p3v>;
+	vqmmc-supply = <&reg_1p8v>;
 	bus-width = <8>;
+	mmc-hs200-1_8v;
 	non-removable;
 	status = "okay";
 };

arch/arm/dts/socfpga_cyclone5_mcvevk.dts

@@ -1,58 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2015 Marek Vasut <marex@denx.de>
- */
-
-#include "socfpga_cyclone5.dtsi"
-
-/ {
-	model = "Aries MCVEVK";
-	compatible = "altr,socfpga-cyclone5", "altr,socfpga";
-
-	chosen {
-		bootargs = "console=ttyS0,115200";
-	};
-
-	aliases {
-		ethernet0 = &gmac0;
-		udc0 = &usb1;
-	};
-
-	memory {
-		name = "memory";
-		device_type = "memory";
-		reg = <0x0 0x40000000>; /* 1GB */
-	};
-
-	soc {
-		u-boot,dm-pre-reloc;
-	};
-};
-
-&gmac0 {
-	status = "okay";
-	phy-mode = "rgmii";
-};
-
-&gpio0 {
-	status = "okay";
-};
-
-&gpio1 {
-	status = "okay";
-};
-
-&gpio2 {
-	status = "okay";
-};
-
-&mmc0 {
-	status = "okay";
-	bus-width = <8>;
-	u-boot,dm-pre-reloc;
-};
-
-&usb1 {
-	disable-over-current;
-	status = "okay";
-};

arch/arm/dts/sun50i-h5-orangepi-zero-plus.dts

@@ -0,0 +1,145 @@
+/*
+ * Copyright (C) 2016 ARM Ltd.
+ * Copyright (C) 2018 Hauke Mehrtens <hauke@hauke-m.de>
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR X11)
+ */
+
+/dts-v1/;
+#include "sun50i-h5.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+	model = "Xunlong Orange Pi Zero Plus";
+	compatible = "xunlong,orangepi-zero-plus", "allwinner,sun50i-h5";
+
+	reg_vcc3v3: vcc3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	aliases {
+		ethernet0 = &emac;
+		ethernet1 = &rtl8189ftv;
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		pwr {
+			label = "orangepi:green:pwr";
+			gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */
+			default-state = "on";
+		};
+
+		status {
+			label = "orangepi:red:status";
+			gpios = <&pio 0 17 GPIO_ACTIVE_HIGH>; /* PA17 */
+		};
+	};
+
+	reg_gmac_3v3: gmac-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "gmac-3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		startup-delay-us = <100000>;
+		enable-active-high;
+		gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
+	};
+};
+
+&ehci0 {
+	status = "okay";
+};
+
+&ehci1 {
+	status = "okay";
+};
+
+&emac {
+	pinctrl-names = "default";
+	pinctrl-0 = <&emac_rgmii_pins>;
+	phy-supply = <&reg_gmac_3v3>;
+	phy-handle = <&ext_rgmii_phy>;
+	phy-mode = "rgmii";
+	status = "okay";
+};
+
+&external_mdio {
+	ext_rgmii_phy: ethernet-phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <1>;
+	};
+};
+
+&mmc0 {
+	vmmc-supply = <&reg_vcc3v3>;
+	bus-width = <4>;
+	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+	status = "okay";
+};
+
+&mmc1 {
+	vmmc-supply = <&reg_vcc3v3>;
+	bus-width = <4>;
+	non-removable;
+	status = "okay";
+
+	/*
+	 * Explicitly define the sdio device, so that we can add an ethernet
+	 * alias for it (which e.g. makes u-boot set a mac-address).
+	 */
+	rtl8189ftv: sdio_wifi@1 {
+		reg = <1>;
+	};
+};
+
+/*
+&spi0  {
+	status = "okay";
+
+	flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "mxicy,mx25l1606e", "winbond,w25q128";
+		reg = <0>;
+		spi-max-frequency = <40000000>;
+	};
+};
+*/
+
+&ohci0 {
+	status = "okay";
+};
+
+&ohci1 {
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins_a>;
+	status = "okay";
+};
+
+&usb_otg {
+	dr_mode = "peripheral";
+	status = "okay";
+};
+
+&usbphy {
+	/* USB Type-A ports' VBUS is always on */
+	usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
+	status = "okay";
+};

arch/arm/dts/sun8i-h2-plus-orangepi-r1.dts

@@ -0,0 +1,101 @@
+/*
+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.xyz>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/* Orange Pi R1 is based on Orange Pi Zero design */
+#include "sun8i-h2-plus-orangepi-zero.dts"
+
+/ {
+	model = "Xunlong Orange Pi R1";
+	compatible = "xunlong,orangepi-r1", "allwinner,sun8i-h2-plus";
+
+	/delete-node/ reg_vcc_wifi;
+
+	/*
+	 * Ths pin of this regulator is the same with the Wi-Fi extra
+	 * regulator on the original Zero. However it's used for USB
+	 * Ethernet rather than the Wi-Fi now.
+	 */
+	reg_vcc_usb_eth: reg-vcc-usb-ethernet {
+		compatible = "regulator-fixed";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-name = "vcc-usb-ethernet";
+		enable-active-high;
+		gpio = <&pio 0 20 GPIO_ACTIVE_HIGH>;
+	};
+
+	aliases {
+		ethernet1 = &rtl8189etv;
+	};
+};
+
+/*
+&spi0 {
+	status = "okay";
+
+	flash@0 {
+		compatible = "mxicy,mx25l12805d", "jedec,spi-nor";
+	};
+};
+*/
+
+&ohci1 {
+	/*
+	 * RTL8152B USB-Ethernet adapter is connected to USB1,
+	 * and it's a USB 2.0 device. So the OHCI1 controller
+	 * can be left disabled.
+	 */
+	status = "disabled";
+};
+
+&mmc1 {
+	vmmc-supply = <&reg_vcc3v3>;
+	vqmmc-supply = <&reg_vcc3v3>;
+
+	rtl8189etv: sdio_wifi@1 {
+		reg = <1>;
+	};
+};
+
+&usbphy {
+	usb1_vbus-supply = <&reg_vcc_usb_eth>;
+};

arch/arm/dts/uniphier-ld11.dtsi

@@ -124,7 +124,6 @@
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_uart0>;
 			clocks = <&peri_clk 0>;
-			clock-frequency = <58820000>;
 			resets = <&peri_rst 0>;
 		};
 
@@ -136,7 +135,6 @@
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_uart1>;
 			clocks = <&peri_clk 1>;
-			clock-frequency = <58820000>;
 			resets = <&peri_rst 1>;
 		};
 
@@ -148,7 +146,6 @@
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_uart2>;
 			clocks = <&peri_clk 2>;
-			clock-frequency = <58820000>;
 			resets = <&peri_rst 2>;
 		};
 
@@ -160,7 +157,6 @@
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_uart3>;
 			clocks = <&peri_clk 3>;
-			clock-frequency = <58820000>;
 			resets = <&peri_rst 3>;
 		};
 

arch/arm/dts/uniphier-ld20.dtsi

@@ -230,7 +230,6 @@
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_uart0>;
 			clocks = <&peri_clk 0>;
-			clock-frequency = <58820000>;
 			resets = <&peri_rst 0>;
 		};
 
@@ -242,7 +241,6 @@
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_uart1>;
 			clocks = <&peri_clk 1>;
-			clock-frequency = <58820000>;
 			resets = <&peri_rst 1>;
 		};
 
@@ -254,7 +252,6 @@
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_uart2>;
 			clocks = <&peri_clk 2>;
-			clock-frequency = <58820000>;
 			resets = <&peri_rst 2>;
 		};
 
@@ -266,7 +263,6 @@
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_uart3>;
 			clocks = <&peri_clk 3>;
-			clock-frequency = <58820000>;
 			resets = <&peri_rst 3>;
 		};
 

arch/arm/dts/uniphier-ld4.dtsi

@@ -71,7 +71,6 @@
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_uart0>;
 			clocks = <&peri_clk 0>;
-			clock-frequency = <36864000>;
 			resets = <&peri_rst 0>;
 		};
 
@@ -83,7 +82,6 @@
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_uart1>;
 			clocks = <&peri_clk 1>;
-			clock-frequency = <36864000>;
 			resets = <&peri_rst 1>;
 		};
 
@@ -95,7 +93,6 @@
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_uart2>;
 			clocks = <&peri_clk 2>;
-			clock-frequency = <36864000>;
 			resets = <&peri_rst 2>;
 		};
 
@@ -107,7 +104,6 @@
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_uart3>;
 			clocks = <&peri_clk 3>;
-			clock-frequency = <36864000>;
 			resets = <&peri_rst 3>;
 		};
 

arch/arm/dts/uniphier-pro4.dtsi

@@ -79,7 +79,6 @@
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_uart0>;
 			clocks = <&peri_clk 0>;
-			clock-frequency = <73728000>;
 			resets = <&peri_rst 0>;
 		};
 
@@ -91,7 +90,6 @@
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_uart1>;
 			clocks = <&peri_clk 1>;
-			clock-frequency = <73728000>;
 			resets = <&peri_rst 1>;
 		};
 
@@ -103,7 +101,6 @@
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_uart2>;
 			clocks = <&peri_clk 2>;
-			clock-frequency = <73728000>;
 			resets = <&peri_rst 2>;
 		};
 
@@ -115,7 +112,6 @@
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_uart3>;
 			clocks = <&peri_clk 3>;
-			clock-frequency = <73728000>;
 			resets = <&peri_rst 3>;
 		};
 
@@ -429,7 +425,7 @@
 			pinctrl-0 = <&pinctrl_ether_rgmii>;
 			clock-names = "gio", "ether", "ether-gb", "ether-phy";
 			clocks = <&sys_clk 12>, <&sys_clk 6>, <&sys_clk 7>,
-				<&sys_clk 10>;
+				 <&sys_clk 10>;
 			reset-names = "gio", "ether";
 			resets = <&sys_rst 12>, <&sys_rst 6>;
 			phy-mode = "rgmii";

arch/arm/dts/uniphier-pro5.dtsi

@@ -164,7 +164,6 @@
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_uart0>;
 			clocks = <&peri_clk 0>;
-			clock-frequency = <73728000>;
 			resets = <&peri_rst 0>;
 		};
 
@@ -176,7 +175,6 @@
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_uart1>;
 			clocks = <&peri_clk 1>;
-			clock-frequency = <73728000>;
 			resets = <&peri_rst 1>;
 		};
 
@@ -188,7 +186,6 @@
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_uart2>;
 			clocks = <&peri_clk 2>;
-			clock-frequency = <73728000>;
 			resets = <&peri_rst 2>;
 		};
 
@@ -200,7 +197,6 @@
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_uart3>;
 			clocks = <&peri_clk 3>;
-			clock-frequency = <73728000>;
 			resets = <&peri_rst 3>;
 		};
 

arch/arm/dts/uniphier-pxs2.dtsi

@@ -172,7 +172,6 @@
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_uart0>;
 			clocks = <&peri_clk 0>;
-			clock-frequency = <88900000>;
 			resets = <&peri_rst 0>;
 		};
 
@@ -184,7 +183,6 @@
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_uart1>;
 			clocks = <&peri_clk 1>;
-			clock-frequency = <88900000>;
 			resets = <&peri_rst 1>;
 		};
 
@@ -196,7 +194,6 @@
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_uart2>;
 			clocks = <&peri_clk 2>;
-			clock-frequency = <88900000>;
 			resets = <&peri_rst 2>;
 		};
 
@@ -208,7 +205,6 @@
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_uart3>;
 			clocks = <&peri_clk 3>;
-			clock-frequency = <88900000>;
 			resets = <&peri_rst 3>;
 		};
 

arch/arm/dts/uniphier-pxs3-ref.dts

@@ -75,6 +75,10 @@
 	status = "okay";
 };
 
+&sd {
+	status = "okay";
+};
+
 &eth0 {
 	status = "okay";
 	phy-handle = <&ethphy0>;

arch/arm/dts/uniphier-pxs3.dtsi

@@ -152,7 +152,6 @@
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_uart0>;
 			clocks = <&peri_clk 0>;
-			clock-frequency = <58820000>;
 			resets = <&peri_rst 0>;
 		};
 
@@ -164,7 +163,6 @@
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_uart1>;
 			clocks = <&peri_clk 1>;
-			clock-frequency = <58820000>;
 			resets = <&peri_rst 1>;
 		};
 
@@ -176,7 +174,6 @@
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_uart2>;
 			clocks = <&peri_clk 2>;
-			clock-frequency = <58820000>;
 			resets = <&peri_rst 2>;
 		};
 
@@ -188,7 +185,6 @@
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_uart3>;
 			clocks = <&peri_clk 3>;
-			clock-frequency = <58820000>;
 			resets = <&peri_rst 3>;
 		};
 

arch/arm/dts/uniphier-sld8.dtsi

@@ -71,7 +71,6 @@
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_uart0>;
 			clocks = <&peri_clk 0>;
-			clock-frequency = <80000000>;
 			resets = <&peri_rst 0>;
 		};
 
@@ -83,7 +82,6 @@
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_uart1>;
 			clocks = <&peri_clk 1>;
-			clock-frequency = <80000000>;
 			resets = <&peri_rst 1>;
 		};
 
@@ -95,7 +93,6 @@
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_uart2>;
 			clocks = <&peri_clk 2>;
-			clock-frequency = <80000000>;
 			resets = <&peri_rst 2>;
 		};
 
@@ -107,7 +104,6 @@
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_uart3>;
 			clocks = <&peri_clk 3>;
-			clock-frequency = <80000000>;
 			resets = <&peri_rst 3>;
 		};
 

arch/arm/include/asm/arch-sunxi/clock_sun6i.h

@@ -275,9 +275,13 @@ struct sunxi_ccm_reg {
  * These are EHCI1 - EHCI3 in the datasheet (EHCI0 is for the OTG) we call
  * them 0 - 2 like they were called on older SoCs.
  */
+#define AHB_GATE_OFFSET_USB_OHCI3	31
+#define AHB_GATE_OFFSET_USB_OHCI2	30
+#define AHB_GATE_OFFSET_USB_OHCI1	29
 #define AHB_GATE_OFFSET_USB_OHCI0	28
-#define AHB_GATE_OFFSET_USB_EHCI2	27
-#define AHB_GATE_OFFSET_USB_EHCI1	26
+#define AHB_GATE_OFFSET_USB_EHCI3	27
+#define AHB_GATE_OFFSET_USB_EHCI2	26
+#define AHB_GATE_OFFSET_USB_EHCI1	25
 #define AHB_GATE_OFFSET_USB_EHCI0	24
 #elif defined(CONFIG_MACH_SUN50I)
 #define AHB_GATE_OFFSET_USB_OHCI0	28
@@ -290,7 +294,7 @@ struct sunxi_ccm_reg {
 #define AHB_GATE_OFFSET_USB_EHCI1	27
 #define AHB_GATE_OFFSET_USB_EHCI0	26
 #endif
-#ifdef CONFIG_MACH_SUN50I
+#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUNXI_H3_H5)
 #define AHB_GATE_OFFSET_USB0		23
 #elif !defined(CONFIG_MACH_SUN8I_R40)
 #define AHB_GATE_OFFSET_USB0		24

arch/arm/include/asm/arch-sunxi/cpu_sun4i.h

@@ -63,10 +63,11 @@
 #ifdef CONFIG_SUNXI_GEN_SUN6I
 #if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I)
 #define SUNXI_USBPHY_BASE		0x01c19000
-#define SUNXI_USB0_BASE			0x01c1a000
-#define SUNXI_USB1_BASE			0x01c1b000
-#define SUNXI_USB2_BASE			0x01c1c000
-#define SUNXI_USB3_BASE			0x01c1d000
+#define SUNXI_USB0_BASE			SUNXI_USBPHY_BASE
+#define SUNXI_USB1_BASE			0x01c1a000
+#define SUNXI_USB2_BASE			0x01c1b000
+#define SUNXI_USB3_BASE			0x01c1c000
+#define SUNXI_USB4_BASE			0x01c1d000
 #else
 #define SUNXI_USB0_BASE			0x01c19000
 #define SUNXI_USB1_BASE			0x01c1a000

arch/arm/mach-at91/Kconfig

@@ -197,14 +197,6 @@ config TARGET_SAMA5D4EK
 	select BOARD_EARLY_INIT_F
 	select BOARD_LATE_INIT
 
-config TARGET_MA5D4EVK
-	bool "Aries MA5D4EVK Evaluation Kit"
-	select SAMA5D4
-	select SUPPORT_SPL
-	select DM
-	select DM_SPI
-	select SPI
-
 config TARGET_MEESC
 	bool "Support meesc"
 	select AT91SAM9263
@@ -263,7 +255,6 @@ endchoice
 config SYS_SOC
 	default "at91"
 
-source "board/aries/ma5d4evk/Kconfig"
 source "board/atmel/at91rm9200ek/Kconfig"
 source "board/atmel/at91sam9260ek/Kconfig"
 source "board/atmel/at91sam9261ek/Kconfig"

arch/arm/mach-imx/cache.c

@@ -9,6 +9,34 @@
 #include <asm/io.h>
 #include <asm/mach-imx/sys_proto.h>
 
+static void enable_ca7_smp(void)
+{
+	u32 val;
+
+	/* Read MIDR */
+	asm volatile ("mrc p15, 0, %0, c0, c0, 0\n\t" : "=r"(val));
+	val = (val >> 4);
+	val &= 0xf;
+
+	/* Only set the SMP for Cortex A7 */
+	if (val == 0x7) {
+		/* Read auxiliary control register */
+		asm volatile ("mrc p15, 0, %0, c1, c0, 1\n\t" : "=r"(val));
+
+		if (val & (1 << 6))
+			return;
+
+		/* Enable SMP */
+		val |= (1 << 6);
+
+		/* Write auxiliary control register */
+		asm volatile ("mcr p15, 0, %0, c1, c0, 1\n\t" : : "r"(val));
+
+		DSB;
+		ISB;
+	}
+}
+
 #ifndef CONFIG_SYS_DCACHE_OFF
 void enable_caches(void)
 {
@@ -20,6 +48,9 @@ void enable_caches(void)
 	/* Avoid random hang when download by usb */
 	invalidate_dcache_all();
 
+	/* Set ACTLR.SMP bit for Cortex-A7 */
+	enable_ca7_smp();
+
 	/* Enable D-cache. I-cache is already enabled in start.S */
 	dcache_enable();
 
@@ -31,6 +62,17 @@ void enable_caches(void)
 					IRAM_SIZE,
 					option);
 }
+#else
+void enable_caches(void)
+{
+	/*
+	 * Set ACTLR.SMP bit for Cortex-A7, even if the caches are
+	 * disabled by u-boot
+	 */
+	enable_ca7_smp();
+
+	puts("WARNING: Caches not enabled\n");
+}
 #endif
 
 #ifndef CONFIG_SYS_L2CACHE_OFF

arch/arm/mach-imx/mx5/Kconfig

@@ -8,9 +8,11 @@ config MX5
 config MX51
 	bool
 	select SYS_FSL_ERRATUM_ESDHC_A001
+	select ARM_CORTEX_A8_CVE_2017_5715
 
 config MX53
 	bool
+	select ARM_CORTEX_A8_CVE_2017_5715
 
 choice
 	prompt "MX5 board select"
@@ -27,11 +29,6 @@ config TARGET_KP_IMX53
 	select DM_GPIO
 	select DM_PMIC
 
-config TARGET_M53EVK
-	bool "Support m53evk"
-	select MX53
-	select SUPPORT_SPL
-
 config TARGET_MX51EVK
 	bool "Support mx51evk"
 	select BOARD_LATE_INIT
@@ -81,7 +78,6 @@ endchoice
 config SYS_SOC
 	default "mx5"
 
-source "board/aries/m53evk/Kconfig"
 source "board/beckhoff/mx53cx9020/Kconfig"
 source "board/freescale/mx51evk/Kconfig"
 source "board/freescale/mx53ard/Kconfig"

arch/arm/mach-imx/mx5/Makefile

@@ -9,6 +9,5 @@ obj-y := soc.o clock.o
 obj-y += lowlevel_init.o
 
 # common files for mx53 dram initialization
-obj-$(CONFIG_TARGET_M53EVK)     += mx53_dram.o
 obj-$(CONFIG_TARGET_MX53CX9020) += mx53_dram.o
 obj-$(CONFIG_TARGET_MX53LOCO)   += mx53_dram.o

arch/arm/mach-imx/mx7/soc.c

@@ -280,13 +280,6 @@ const struct boot_mode soc_boot_modes[] = {
 
 void s_init(void)
 {
-#if !defined CONFIG_SPL_BUILD
-	/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
-	asm volatile(
-			"mrc p15, 0, r0, c1, c0, 1\n"
-			"orr r0, r0, #1 << 6\n"
-			"mcr p15, 0, r0, c1, c0, 1\n");
-#endif
 	/* clock configuration. */
 	clock_init();
 

arch/arm/mach-imx/mxs/Kconfig

@@ -50,9 +50,6 @@ config TARGET_APX4DEVKIT
 config TARGET_BG0900
 	bool "Support bg0900"
 
-config TARGET_M28EVK
-	bool "Support m28evk"
-
 config TARGET_MX28EVK
 	bool "Support mx28evk"
 	select BOARD_EARLY_INIT_F
@@ -68,7 +65,6 @@ endchoice
 config SYS_SOC
 	default "mxs"
 
-source "board/aries/m28evk/Kconfig"
 source "board/bluegiga/apx4devkit/Kconfig"
 source "board/freescale/mx28evk/Kconfig"
 source "board/ppcag/bg0900/Kconfig"

arch/arm/mach-omap2/Kconfig

@@ -10,6 +10,7 @@ config OMAP34XX
 	select ARM_ERRATA_454179
 	select ARM_ERRATA_621766
 	select ARM_ERRATA_725233
+	select ARM_CORTEX_A8_CVE_2017_5715
 	select USE_TINY_PRINTF
 	imply NAND_OMAP_GPMC
 	imply SPL_EXT_SUPPORT
@@ -53,6 +54,7 @@ config OMAP54XX
 	bool "OMAP54XX SoC"
 	select ARM_ERRATA_798870
 	select SYS_THUMB_BUILD
+	select ARM_CORTEX_A15_CVE_2017_5715
 	imply NAND_OMAP_ELM
 	imply NAND_OMAP_GPMC
 	imply SPL_DISPLAY_PRINT
@@ -115,6 +117,7 @@ config AM43XX
 config AM33XX
 	bool "AM33XX SoC"
 	select SPECIFY_CONSOLE_INDEX
+	select ARM_CORTEX_A8_CVE_2017_5715
 	imply NAND_OMAP_ELM
 	imply NAND_OMAP_GPMC
 	imply SPL_NAND_AM33XX_BCH

arch/arm/mach-socfpga/Kconfig

@@ -36,10 +36,6 @@ config TARGET_SOCFPGA_CYCLONE5_SOCDK
 	bool "Altera SOCFPGA SoCDK (Cyclone V)"
 	select TARGET_SOCFPGA_CYCLONE5
 
-config TARGET_SOCFPGA_ARIES_MCVEVK
-	bool "Aries MCVEVK (Cyclone V)"
-	select TARGET_SOCFPGA_CYCLONE5
-
 config TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
 	bool "Devboards DBM-SoC1 (Cyclone V)"
 	select TARGET_SOCFPGA_CYCLONE5
@@ -88,7 +84,6 @@ config SYS_BOARD
 	default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
 	default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
 	default "is1" if TARGET_SOCFPGA_IS1
-	default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
 	default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
 	default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
 	default "sr1500" if TARGET_SOCFPGA_SR1500
@@ -98,7 +93,6 @@ config SYS_VENDOR
 	default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
 	default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
 	default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
-	default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
 	default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
 	default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
 	default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
@@ -119,7 +113,6 @@ config SYS_CONFIG_NAME
 	default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
 	default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
 	default "socfpga_is1" if TARGET_SOCFPGA_IS1
-	default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
 	default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
 	default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
 	default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500

arch/arm/mach-sunxi/Kconfig

@@ -84,6 +84,9 @@ config SUNXI_HIGH_SRAM
 	Chips using the latter setup are supposed to select this option to
 	adjust the addresses accordingly.
 
+config SUNXI_A64_TIMER_ERRATUM
+	bool
+
 # Note only one of these may be selected at a time! But hidden choices are
 # not supported by Kconfig
 config SUNXI_GEN_SUN4I
@@ -270,6 +273,7 @@ config MACH_SUN50I
 	select SUNXI_DRAM_DW_32BIT
 	select FIT
 	select SPL_LOAD_FIT
+	select SUNXI_A64_TIMER_ERRATUM
 
 config MACH_SUN50I_H5
 	bool "sun50i (Allwinner H5)"

arch/x86/cpu/coreboot/Kconfig

@@ -10,6 +10,7 @@ config SYS_COREBOOT
 	imply MMC_PCI
 	imply MMC_SDHCI
 	imply MMC_SDHCI_SDMA
+	imply SCSI
 	imply SCSI_AHCI
 	imply SPI_FLASH
 	imply SYS_NS16550

arch/x86/cpu/cpu.c

@@ -193,7 +193,7 @@ void show_boot_progress(int val)
 	outb(val, POST_PORT);
 }
 
-#ifndef CONFIG_SYS_COREBOOT
+#if !defined(CONFIG_SYS_COREBOOT) && !defined(CONFIG_EFI_STUB)
 /*
  * Implement a weak default function for boards that optionally
  * need to clean up the system before jumping to the kernel.

arch/x86/cpu/efi/payload.c

@@ -7,6 +7,7 @@
 #include <common.h>
 #include <efi.h>
 #include <errno.h>
+#include <usb.h>
 #include <asm/post.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -108,11 +109,10 @@ int dram_init_banksize(void)
 	     desc < end && num_banks < CONFIG_NR_DRAM_BANKS;
 	     desc = efi_get_next_mem_desc(map, desc)) {
 		/*
-		 * We only use conventional memory below 4GB, and ignore
+		 * We only use conventional memory and ignore
 		 * anything less than 1MB.
 		 */
 		if (desc->type != EFI_CONVENTIONAL_MEMORY ||
-		    desc->physical_start >= 1ULL << 32 ||
 		    (desc->num_pages << EFI_PAGE_SHIFT) < 1 << 20)
 			continue;
 		gd->bd->bi_dram[num_banks].start = desc->physical_start;
@@ -160,3 +160,11 @@ int reserve_arch(void)
 
 	return 0;
 }
+
+int last_stage_init(void)
+{
+	/* start usb so that usb keyboard can be used as input device */
+	usb_init();
+
+	return 0;
+}

arch/x86/cpu/intel_common/car.S

@@ -239,4 +239,6 @@ _dt_ucode_base_size:
 .globl ucode_base
 ucode_base:	/* Declared in microcode.h */
 	.long	0			/* microcode base */
+.globl ucode_size
+ucode_size:	/* Declared in microcode.h */
 	.long	0			/* microcode size */

arch/x86/cpu/intel_common/microcode.c

@@ -43,8 +43,6 @@ static int microcode_decode_node(const void *blob, int node,
 	update->data = fdt_getprop(blob, node, "data", &update->size);
 	if (!update->data)
 		return -ENOENT;
-	update->data += UCODE_HEADER_LEN;
-	update->size -= UCODE_HEADER_LEN;
 
 	update->header_version = fdtdec_get_int(blob, node,
 						"intel,header-version", 0);
@@ -124,6 +122,7 @@ static void microcode_read_cpu(struct microcode_update *cpu)
 int microcode_update_intel(void)
 {
 	struct microcode_update cpu, update;
+	ulong address;
 	const void *blob = gd->fdt_blob;
 	int skipped;
 	int count;
@@ -167,7 +166,8 @@ int microcode_update_intel(void)
 			skipped++;
 			continue;
 		}
-		wrmsr(MSR_IA32_UCODE_WRITE, (ulong)update.data, 0);
+		address = (ulong)update.data + UCODE_HEADER_LEN;
+		wrmsr(MSR_IA32_UCODE_WRITE, address, 0);
 		rev = microcode_read_rev();
 		debug("microcode: updated to revision 0x%x date=%04x-%02x-%02x\n",
 		      rev, update.date_code & 0xffff,
@@ -178,5 +178,9 @@ int microcode_update_intel(void)
 			return -EFAULT;
 		}
 		count++;
+		if (!ucode_base) {
+			ucode_base = (ulong)update.data;
+			ucode_size = update.size;
+		}
 	} while (1);
 }

arch/x86/cpu/qemu/Kconfig

@@ -7,6 +7,7 @@ config QEMU
 	select ARCH_EARLY_INIT_R
 	imply AHCI_PCI
 	imply E1000
+	imply SCSI
 	imply SCSI_AHCI
 	imply SYS_NS16550
 	imply USB

arch/x86/cpu/qemu/Makefile

@@ -2,6 +2,9 @@
 #
 # Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
 
-obj-y += car.o dram.o
+ifndef CONFIG_$(SPL_)X86_64
+obj-y += car.o
+endif
+obj-y += dram.o
 obj-y += qemu.o
 obj-$(CONFIG_QFW) += cpu.o e820.o

arch/x86/cpu/x86_64/setjmp.S

@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 Intel Corporation
+ *
+ * See arch/x86/include/asm/setjmp.h for jmp_buf format
+ */
+
+#include <linux/linkage.h>
+
+.text
+.align 8
+
+ENTRY(setjmp)
+
+	pop	%rcx
+	movq	%rcx, (%rdi)	/* Return address */
+	movq	%rsp, 8(%rdi)
+	movq	%rbp, 16(%rdi)
+	movq	%rbx, 24(%rdi)
+	movq	%r12, 32(%rdi)
+	movq	%r13, 40(%rdi)
+	movq	%r14, 48(%rdi)
+	movq	%r15, 56(%rdi)
+	xorq	%rax, %rax	/* Direct invocation returns 0 */
+	jmpq	*%rcx
+
+ENDPROC(setjmp)
+
+.align 8
+
+ENTRY(longjmp)
+
+	movq	(%rdi), %rcx	/* Return address */
+	movq	8(%rdi), %rsp
+	movq	16(%rdi), %rbp
+	movq	24(%rdi), %rbx
+	movq	32(%rdi), %r12
+	movq	40(%rdi), %r13
+	movq	48(%rdi), %r14
+	movq	56(%rdi), %r15
+
+	movq	%rsi, %rax	/* Value to be returned by setjmp() */
+	testq	%rax, %rax	/* cannot be 0 in this case */
+	jnz	1f
+	incq	%rax		/* Return 1 instead */
+1:
+	jmpq	*%rcx
+
+ENDPROC(longjmp)

arch/x86/cpu/x86_64/setjmp.c

@@ -1,19 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2016 Google, Inc
- */
-
-#include <common.h>
-#include <asm/setjmp.h>
-
-int setjmp(struct jmp_buf_data *jmp_buf)
-{
-	printf("WARNING: setjmp() is not supported\n");
-
-	return 0;
-}
-
-void longjmp(struct jmp_buf_data *jmp_buf, int val)
-{
-	printf("WARNING: longjmp() is not supported\n");
-}

arch/x86/include/asm/microcode.h

@@ -10,6 +10,7 @@
 
 /* This is a declaration for ucode_base in start.S */
 extern u32 ucode_base;
+extern u32 ucode_size;
 
 /**
  * microcode_update_intel() - Apply microcode updates

arch/x86/include/asm/posix_types.h

@@ -16,7 +16,8 @@ typedef int		__kernel_pid_t;
 typedef unsigned short	__kernel_ipc_pid_t;
 typedef unsigned short	__kernel_uid_t;
 typedef unsigned short	__kernel_gid_t;
-#if CONFIG_IS_ENABLED(X86_64)
+/* checking against __x86_64__ covers both 64-bit EFI stub and 64-bit U-Boot */
+#if defined(__x86_64__)
 typedef unsigned long	__kernel_size_t;
 typedef long		__kernel_ssize_t;
 #else

arch/x86/include/asm/setjmp.h

@@ -8,6 +8,21 @@
 #ifndef __setjmp_h
 #define __setjmp_h
 
+#ifdef CONFIG_X86_64
+
+struct jmp_buf_data {
+	unsigned long __rip;
+	unsigned long __rsp;
+	unsigned long __rbp;
+	unsigned long __rbx;
+	unsigned long __r12;
+	unsigned long __r13;
+	unsigned long __r14;
+	unsigned long __r15;
+};
+
+#else
+
 struct jmp_buf_data {
 	unsigned int __ebx;
 	unsigned int __esp;
@@ -17,6 +32,8 @@ struct jmp_buf_data {
 	unsigned int __eip;
 };
 
+#endif
+
 int setjmp(struct jmp_buf_data *jmp_buf);
 void longjmp(struct jmp_buf_data *jmp_buf, int val);
 

arch/x86/lib/e820.c

@@ -4,6 +4,7 @@
  */
 
 #include <common.h>
+#include <efi_loader.h>
 #include <asm/e820.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -34,3 +35,41 @@ __weak unsigned int install_e820_map(unsigned int max_entries,
 
 	return 4;
 }
+
+#if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_SPL_BUILD)
+void efi_add_known_memory(void)
+{
+	struct e820_entry e820[E820MAX];
+	unsigned int i, num;
+	u64 start, pages;
+	int type;
+
+	num = install_e820_map(ARRAY_SIZE(e820), e820);
+
+	for (i = 0; i < num; ++i) {
+		start = e820[i].addr;
+		pages = ALIGN(e820[i].size, EFI_PAGE_SIZE) >> EFI_PAGE_SHIFT;
+
+		switch (e820[i].type) {
+		case E820_RAM:
+			type = EFI_CONVENTIONAL_MEMORY;
+			break;
+		case E820_RESERVED:
+			type = EFI_RESERVED_MEMORY_TYPE;
+			break;
+		case E820_ACPI:
+			type = EFI_ACPI_RECLAIM_MEMORY;
+			break;
+		case E820_NVS:
+			type = EFI_ACPI_MEMORY_NVS;
+			break;
+		case E820_UNUSABLE:
+		default:
+			type = EFI_UNUSABLE_MEMORY;
+			break;
+		}
+
+		efi_add_memory_map(start, pages, type, false);
+	}
+}
+#endif /* defined(EFI_LOADER) && !defined(CONFIG_SPL_BUILD) */

arch/x86/lib/fsp/fsp_car.S

@@ -102,8 +102,10 @@ temp_ram_init_params:
 _dt_ucode_base_size:
 	/* These next two fields are filled in by ifdtool */
 .globl ucode_base
-ucode_base:	/* Declared in micrcode.h */
+ucode_base:	/* Declared in microcode.h */
 	.long	0			/* microcode base */
+.globl ucode_size
+ucode_size:	/* Declared in microcode.h */
 	.long	0			/* microcode size */
 	.long	CONFIG_SYS_MONITOR_BASE	/* code region base */
 	.long	CONFIG_SYS_MONITOR_LEN	/* code region size */

board/aries/m28evk/Kconfig

@@ -1,15 +0,0 @@
-if TARGET_M28EVK
-
-config SYS_BOARD
-	default "m28evk"
-
-config SYS_VENDOR
-	default "aries"
-
-config SYS_SOC
-	default "mxs"
-
-config SYS_CONFIG_NAME
-	default "m28evk"
-
-endif

board/aries/m28evk/MAINTAINERS

@@ -1,6 +0,0 @@
-M28EVK BOARD
-#M:	Marek Vasut <marek.vasut@gmail.com>
-S:	Orphan (since 2017-07)
-F:	board/aries/m28evk/
-F:	include/configs/m28evk.h
-F:	configs/m28evk_defconfig

board/aries/m28evk/Makefile

@@ -1,10 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-ifndef	CONFIG_SPL_BUILD
-obj-y	:= m28evk.o
-else
-obj-y	:= spl_boot.o
-endif

board/aries/m28evk/README

@@ -1,13 +0,0 @@
-Aries M28EVK
-============
-
-Files of the M28/M28EVK port
-----------------------------
-
-arch/arm/cpu/arm926ejs/mxs/	- The CPU support code for the Freescale i.MX28
-arch/arm/include/asm/arch-mxs/	- Header files for the Freescale i.MX28
-board/aries/m28evk/		- M28EVK board specific files
-include/configs/m28evk.h	- M28EVK configuration file
-
-Follow the instructions from doc/README.mxs to generate a bootable SD card or to
-boot from NAND flash.

board/aries/m28evk/m28evk.c

@@ -1,172 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Aries M28 module
- *
- * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
- * on behalf of DENX Software Engineering GmbH
- */
-
-#include <common.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux-mx28.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-#include <linux/mii.h>
-#include <miiphy.h>
-#include <netdev.h>
-#include <errno.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Functions
- */
-int board_early_init_f(void)
-{
-	/* IO0 clock at 480MHz */
-	mxs_set_ioclk(MXC_IOCLK0, 480000);
-	/* IO1 clock at 480MHz */
-	mxs_set_ioclk(MXC_IOCLK1, 480000);
-
-	/* SSP0 clock at 96MHz */
-	mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
-	/* SSP2 clock at 160MHz */
-	mxs_set_sspclk(MXC_SSPCLK2, 160000, 0);
-
-#ifdef	CONFIG_CMD_USB
-	mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT);
-	mxs_iomux_setup_pad(MX28_PAD_AUART3_TX__GPIO_3_13 |
-			MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP);
-	gpio_direction_output(MX28_PAD_AUART3_TX__GPIO_3_13, 0);
-
-	mxs_iomux_setup_pad(MX28_PAD_AUART3_RX__GPIO_3_12 |
-			MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP);
-	gpio_direction_output(MX28_PAD_AUART3_RX__GPIO_3_12, 0);
-#endif
-
-	return 0;
-}
-
-int board_init(void)
-{
-	/* Adress of boot parameters */
-	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
-	return 0;
-}
-
-int dram_init(void)
-{
-	return mxs_dram_init();
-}
-
-#ifdef	CONFIG_CMD_MMC
-static int m28_mmc_wp(int id)
-{
-	if (id != 0) {
-		printf("MXS MMC: Invalid card selected (card id = %d)\n", id);
-		return 1;
-	}
-
-	return gpio_get_value(MX28_PAD_AUART2_CTS__GPIO_3_10);
-}
-
-int board_mmc_init(bd_t *bis)
-{
-	/* Configure WP as input. */
-	gpio_direction_input(MX28_PAD_AUART2_CTS__GPIO_3_10);
-	/* Turn on the power to the card. */
-	gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0);
-
-	return mxsmmc_initialize(bis, 0, m28_mmc_wp, NULL);
-}
-#endif
-
-#ifdef	CONFIG_CMD_NET
-
-#define	MII_OPMODE_STRAP_OVERRIDE	0x16
-#define	MII_PHY_CTRL1			0x1e
-#define	MII_PHY_CTRL2			0x1f
-
-int fecmxc_mii_postcall(int phy)
-{
-#if	defined(CONFIG_ARIES_M28_V11) || defined(CONFIG_ARIES_M28_V10)
-	/* KZ8031 PHY on old boards. */
-	const uint32_t freq = 0x0080;
-#else
-	/* KZ8021 PHY on new boards. */
-	const uint32_t freq = 0x0000;
-#endif
-
-	miiphy_write("FEC1", phy, MII_BMCR, 0x9000);
-	miiphy_write("FEC1", phy, MII_OPMODE_STRAP_OVERRIDE, 0x0202);
-	if (phy == 3)
-		miiphy_write("FEC1", 3, MII_PHY_CTRL2, 0x8100 | freq);
-	return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
-	struct mxs_clkctrl_regs *clkctrl_regs =
-		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
-	struct eth_device *dev;
-	int ret;
-
-	ret = cpu_eth_init(bis);
-	if (ret)
-		return ret;
-
-	clrsetbits_le32(&clkctrl_regs->hw_clkctrl_enet,
-		CLKCTRL_ENET_TIME_SEL_MASK | CLKCTRL_ENET_CLK_OUT_EN,
-		CLKCTRL_ENET_TIME_SEL_RMII_CLK);
-
-#if !defined(CONFIG_ARIES_M28_V11) && !defined(CONFIG_ARIES_M28_V10)
-	/* Reset the new PHY */
-	gpio_direction_output(MX28_PAD_AUART2_RTS__GPIO_3_11, 0);
-	udelay(10000);
-	gpio_set_value(MX28_PAD_AUART2_RTS__GPIO_3_11, 1);
-	udelay(10000);
-#endif
-
-	ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
-	if (ret) {
-		printf("FEC MXS: Unable to init FEC0\n");
-		return ret;
-	}
-
-	ret = fecmxc_initialize_multi(bis, 1, 3, MXS_ENET1_BASE);
-	if (ret) {
-		printf("FEC MXS: Unable to init FEC1\n");
-		return ret;
-	}
-
-	dev = eth_get_dev_by_name("FEC0");
-	if (!dev) {
-		printf("FEC MXS: Unable to get FEC0 device entry\n");
-		return -EINVAL;
-	}
-
-	ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
-	if (ret) {
-		printf("FEC MXS: Unable to register FEC0 mii postcall\n");
-		return ret;
-	}
-
-	dev = eth_get_dev_by_name("FEC1");
-	if (!dev) {
-		printf("FEC MXS: Unable to get FEC1 device entry\n");
-		return -EINVAL;
-	}
-
-	ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
-	if (ret) {
-		printf("FEC MXS: Unable to register FEC1 mii postcall\n");
-		return ret;
-	}
-
-	return ret;
-}
-
-#endif

board/aries/m28evk/spl_boot.c

@@ -1,205 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * ARIES M28 Boot setup
- *
- * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
- * on behalf of DENX Software Engineering GmbH
- */
-
-#include <common.h>
-#include <config.h>
-#include <asm/io.h>
-#include <asm/arch/iomux-mx28.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/sys_proto.h>
-
-#define	MUX_CONFIG_LED	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
-#define	MUX_CONFIG_LCD	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
-#define	MUX_CONFIG_TSC	(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
-#define	MUX_CONFIG_SSP0	(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP)
-#define	MUX_CONFIG_SSP2	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
-#define	MUX_CONFIG_GPMI	(MXS_PAD_1V8 | MXS_PAD_4MA | MXS_PAD_NOPULL)
-#define	MUX_CONFIG_ENET	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
-#define	MUX_CONFIG_EMI	(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
-
-const iomux_cfg_t iomux_setup[] = {
-	/* LED */
-	MX28_PAD_ENET0_RXD3__GPIO_4_10 | MUX_CONFIG_LED,
-
-	/* framebuffer */
-	MX28_PAD_LCD_D00__LCD_D0 | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_D01__LCD_D1 | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_D02__LCD_D2 | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_D03__LCD_D3 | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_D04__LCD_D4 | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_D05__LCD_D5 | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_D06__LCD_D6 | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_D07__LCD_D7 | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_D08__LCD_D8 | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_D09__LCD_D9 | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_D18__LCD_D18 | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_D19__LCD_D19 | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_D20__LCD_D20 | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_D21__LCD_D21 | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_D22__LCD_D22 | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_D23__LCD_D23 | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD,
-
-	/* UART1 */
-#ifdef	CONFIG_ARIES_M28_V10
-	MX28_PAD_AUART0_CTS__DUART_RX,
-	MX28_PAD_AUART0_RTS__DUART_TX,
-#else
-	MX28_PAD_PWM0__DUART_RX,
-	MX28_PAD_PWM1__DUART_TX,
-#endif
-	MX28_PAD_AUART0_TX__DUART_RTS,
-	MX28_PAD_AUART0_RX__DUART_CTS,
-
-	/* UART2 */
-	MX28_PAD_AUART1_RX__AUART1_RX,
-	MX28_PAD_AUART1_TX__AUART1_TX,
-	MX28_PAD_AUART1_RTS__AUART1_RTS,
-	MX28_PAD_AUART1_CTS__AUART1_CTS,
-
-	/* CAN */
-	MX28_PAD_GPMI_RDY2__CAN0_TX,
-	MX28_PAD_GPMI_RDY3__CAN0_RX,
-
-	/* TSC2007 */
-	MX28_PAD_SAIF0_MCLK__GPIO_3_20 | MUX_CONFIG_TSC,
-
-	/* MMC0 */
-	MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0,
-	MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0,
-	MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0,
-	MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0,
-	MX28_PAD_SSP0_DATA4__SSP0_D4 | MUX_CONFIG_SSP0,
-	MX28_PAD_SSP0_DATA5__SSP0_D5 | MUX_CONFIG_SSP0,
-	MX28_PAD_SSP0_DATA6__SSP0_D6 | MUX_CONFIG_SSP0,
-	MX28_PAD_SSP0_DATA7__SSP0_D7 | MUX_CONFIG_SSP0,
-	MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0,
-	MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
-		(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),
-	MX28_PAD_SSP0_SCK__SSP0_SCK |
-		(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),
-	MX28_PAD_PWM3__GPIO_3_28 | MUX_CONFIG_SSP0 |
-		(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),	/* Power */
-	MX28_PAD_AUART2_CTS__GPIO_3_10,	/* WP */
-
-	/* GPMI NAND */
-	MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI,
-	MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI,
-	MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI,
-	MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI,
-	MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI,
-	MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI,
-	MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI,
-	MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI,
-	MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI,
-	MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI,
-	MX28_PAD_GPMI_RDN__GPMI_RDN |
-		(MXS_PAD_1V8 | MXS_PAD_8MA | MXS_PAD_PULLUP),
-	MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI,
-	MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI,
-	MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI,
-	MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI,
-
-	/* FEC Ethernet */
-	MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,
-	MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET,
-	MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET,
-	MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET,
-	MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET,
-	MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET,
-	MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET,
-	MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET,
-	MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET,
-
-	MX28_PAD_ENET0_COL__ENET1_TX_EN | MUX_CONFIG_ENET,
-	MX28_PAD_ENET0_CRS__ENET1_RX_EN | MUX_CONFIG_ENET,
-	MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MUX_CONFIG_ENET,
-	MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET,
-	MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MUX_CONFIG_ENET,
-	MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET,
-#if !defined(CONFIG_ARIES_M28_V11) && !defined(CONFIG_ARIES_M28_V10)
-	MX28_PAD_AUART2_RTS__GPIO_3_11,	/* PHY reset */
-#endif
-
-	/* I2C */
-	MX28_PAD_I2C0_SCL__I2C0_SCL,
-	MX28_PAD_I2C0_SDA__I2C0_SDA,
-
-	/* EMI */
-	MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
-
-	MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
-
-	/* SPI2 (for flash) */
-	MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2,
-	MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2,
-	MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2,
-	MX28_PAD_SSP2_SS0__SSP2_D3 |
-		(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
-};
-
-void board_init_ll(const uint32_t arg, const uint32_t *resptr)
-{
-	mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
-}

board/aries/m53evk/Kconfig

@@ -1,15 +0,0 @@
-if TARGET_M53EVK
-
-config SYS_BOARD
-	default "m53evk"
-
-config SYS_VENDOR
-	default "aries"
-
-config SYS_SOC
-	default "mx5"
-
-config SYS_CONFIG_NAME
-	default "m53evk"
-
-endif

board/aries/m53evk/MAINTAINERS

@@ -1,6 +0,0 @@
-M53EVK BOARD
-#M:	Marek Vasut <marek.vasut@gmail.com>
-S:	Orphan (since 2017-07)
-F:	board/aries/m53evk/
-F:	include/configs/m53evk.h
-F:	configs/m53evk_defconfig

board/aries/m53evk/Makefile

@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Aries M53EVK
-# Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
-
-obj-y	:= m53evk.o

board/aries/m53evk/imximage.cfg

@@ -1,91 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Aries M53 DRAM init values
- * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
- *
- * Refer doc/README.imximage for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- */
-#include <asm/mach-imx/imximage.cfg>
-
-/* image version */
-IMAGE_VERSION	2
-
-
-/* Boot Offset 0x400, valid for both SD and NAND boot. */
-BOOT_OFFSET	FLASH_OFFSET_STANDARD
-
-/*
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type           Address        Value
- *
- * where:
- *	Addr-type register length (1,2 or 4 bytes)
- *	Address	  absolute address of the register
- *	value	  value to be stored in the register
- */
-DATA 4 0x53fa86f4 0x00000000	 /* GRP_DDRMODE_CTL */
-DATA 4 0x53fa8714 0x00000000	 /* GRP_DDRMODE */
-DATA 4 0x53fa86fc 0x00000000	 /* GRP_DDRPKE */
-DATA 4 0x53fa8724 0x04000000	 /* GRP_DDR_TYPE */
-
-DATA 4 0x53fa872c 0x00300000	 /* GRP_B3DS */
-DATA 4 0x53fa8554 0x00300000	 /* DRAM_DQM3 */
-DATA 4 0x53fa8558 0x00300040	 /* DRAM_SDQS3 */
-
-DATA 4 0x53fa8728 0x00300000	 /* GRP_B2DS */
-DATA 4 0x53fa8560 0x00300000	 /* DRAM_DQM2 */
-DATA 4 0x53fa8568 0x00300040	 /* DRAM_SDQS2 */
-
-DATA 4 0x53fa871c 0x00300000	 /* GRP_B1DS */
-DATA 4 0x53fa8594 0x00300000	 /* DRAM_DQM1 */
-DATA 4 0x53fa8590 0x00300040	 /* DRAM_SDQS1 */
-
-DATA 4 0x53fa8718 0x00300000	 /* GRP_B0DS */
-DATA 4 0x53fa8584 0x00300000	 /* DRAM_DQM0 */
-DATA 4 0x53fa857c 0x00300040	 /* DRAM_SDQS0 */
-
-DATA 4 0x53fa8578 0x00300000	 /* DRAM_SDCLK_0 */
-DATA 4 0x53fa8570 0x00300000	 /* DRAM_SDCLK_1 */
-
-DATA 4 0x53fa8574 0x00300000	 /* DRAM_CAS */
-DATA 4 0x53fa8588 0x00300000	 /* DRAM_RAS */
-DATA 4 0x53fa86f0 0x00300000	 /* GRP_ADDDS */
-DATA 4 0x53fa8720 0x00300000	 /* GRP_CTLDS */
-
-DATA 4 0x53fa8564 0x00300040	 /* DRAM_SDODT1 */
-DATA 4 0x53fa8580 0x00300040	 /* DRAM_SDODT0 */
-
-/* ESDCTL */
-DATA 4 0x63fd9088 0x32383535
-DATA 4 0x63fd9090 0x40383538
-DATA 4 0x63fd907c 0x0136014d
-DATA 4 0x63fd9080 0x01510141
-
-DATA 4 0x63fd9018 0x00011740
-DATA 4 0x63fd9000 0xc3190000
-DATA 4 0x63fd900c 0x555952e3
-DATA 4 0x63fd9010 0xb68e8b63
-DATA 4 0x63fd9014 0x01ff00db
-DATA 4 0x63fd902c 0x000026d2
-DATA 4 0x63fd9030 0x009f0e21
-DATA 4 0x63fd9008 0x12273030
-DATA 4 0x63fd9004 0x0002002d
-DATA 4 0x63fd901c 0x00008032
-DATA 4 0x63fd901c 0x00008033
-DATA 4 0x63fd901c 0x00028031
-DATA 4 0x63fd901c 0x092080b0
-DATA 4 0x63fd901c 0x04008040
-DATA 4 0x63fd901c 0x0000803a
-DATA 4 0x63fd901c 0x0000803b
-DATA 4 0x63fd901c 0x00028039
-DATA 4 0x63fd901c 0x09208138
-DATA 4 0x63fd901c 0x04008048
-DATA 4 0x63fd9020 0x00001800
-DATA 4 0x63fd9040 0x04b80003
-DATA 4 0x63fd9058 0x00022227
-DATA 4 0x63fd901c 0x00000000

board/aries/m53evk/m53evk.c

@@ -1,364 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Aries M53 module
- *
- * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/iomux-mx53.h>
-#include <asm/mach-imx/mx5_video.h>
-#include <asm/spl.h>
-#include <linux/errno.h>
-#include <netdev.h>
-#include <i2c.h>
-#include <mmc.h>
-#include <spl.h>
-#include <fsl_esdhc.h>
-#include <asm/gpio.h>
-#include <usb/ehci-ci.h>
-#include <linux/fb.h>
-#include <ipu_pixfmt.h>
-
-/* Special MXCFB sync flags are here. */
-#include "../drivers/video/mxcfb.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void setup_iomux_uart(void)
-{
-	static const iomux_v3_cfg_t uart_pads[] = {
-		MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
-		MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
-	};
-
-	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
-}
-
-#ifdef CONFIG_USB_EHCI_MX5
-int board_ehci_hcd_init(int port)
-{
-	if (port == 0) {
-		/* USB OTG PWRON */
-		imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_4__GPIO1_4,
-					PAD_CTL_PKE | PAD_CTL_DSE_HIGH));
-		gpio_direction_output(IMX_GPIO_NR(1, 4), 0);
-
-		/* USB OTG Over Current */
-		imx_iomux_v3_setup_pad(MX53_PAD_GPIO_18__GPIO7_13);
-	} else if (port == 1) {
-		/* USB Host PWRON */
-		imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_2__GPIO1_2,
-					PAD_CTL_PKE | PAD_CTL_DSE_HIGH));
-		gpio_direction_output(IMX_GPIO_NR(1, 2), 0);
-
-		/* USB Host Over Current */
-		imx_iomux_v3_setup_pad(MX53_PAD_GPIO_3__USBOH3_USBH1_OC);
-	}
-
-	return 0;
-}
-#endif
-
-static void setup_iomux_fec(void)
-{
-	static const iomux_v3_cfg_t fec_pads[] = {
-		/* MDIO pads */
-		NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
-			PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
-		NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
-
-		/* FEC 0 pads */
-		NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
-				PAD_CTL_HYS | PAD_CTL_PKE),
-		NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
-				PAD_CTL_HYS | PAD_CTL_PKE),
-		NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
-				PAD_CTL_HYS | PAD_CTL_PKE),
-		NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
-		NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
-				PAD_CTL_HYS | PAD_CTL_PKE),
-		NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
-				PAD_CTL_HYS | PAD_CTL_PKE),
-		NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
-		NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
-
-		/* FEC 1 pads */
-		NEW_PAD_CTRL(MX53_PAD_KEY_COL0__FEC_RDATA_3,
-				PAD_CTL_HYS | PAD_CTL_PKE),
-		NEW_PAD_CTRL(MX53_PAD_KEY_ROW0__FEC_TX_ER,
-				PAD_CTL_HYS | PAD_CTL_PKE),
-		NEW_PAD_CTRL(MX53_PAD_KEY_COL1__FEC_RX_CLK,
-				PAD_CTL_HYS | PAD_CTL_PKE),
-		NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__FEC_COL,
-				PAD_CTL_HYS | PAD_CTL_PKE),
-		NEW_PAD_CTRL(MX53_PAD_KEY_COL2__FEC_RDATA_2,
-				PAD_CTL_HYS | PAD_CTL_PKE),
-		NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__FEC_TDATA_2, PAD_CTL_DSE_HIGH),
-		NEW_PAD_CTRL(MX53_PAD_KEY_COL3__FEC_CRS,
-				PAD_CTL_HYS | PAD_CTL_PKE),
-		NEW_PAD_CTRL(MX53_PAD_GPIO_19__FEC_TDATA_3, PAD_CTL_DSE_HIGH),
-	};
-
-	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
-}
-
-#ifdef CONFIG_FSL_ESDHC
-struct fsl_esdhc_cfg esdhc_cfg = {
-	MMC_SDHC1_BASE_ADDR,
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
-	imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
-	gpio_direction_input(IMX_GPIO_NR(1, 1));
-
-	return !gpio_get_value(IMX_GPIO_NR(1, 1));
-}
-
-#define SD_CMD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
-				 PAD_CTL_PUS_100K_UP)
-#define SD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
-				 PAD_CTL_DSE_HIGH)
-
-int board_mmc_init(bd_t *bis)
-{
-	static const iomux_v3_cfg_t sd1_pads[] = {
-		NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
-		NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
-		NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
-		NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
-		NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
-		NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
-		MX53_PAD_EIM_DA13__GPIO3_13,
-
-		MX53_PAD_EIM_EB3__GPIO2_31, /* SD power */
-	};
-
-	esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
-
-	imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
-
-	/* GPIO 2_31 is SD power */
-	gpio_direction_output(IMX_GPIO_NR(2, 31), 0);
-
-	return fsl_esdhc_initialize(bis, &esdhc_cfg);
-}
-#endif
-
-#ifdef CONFIG_VIDEO
-static struct fb_videomode const ampire_wvga = {
-	.name		= "Ampire",
-	.refresh	= 60,
-	.xres		= 800,
-	.yres		= 480,
-	.pixclock	= 29851, /* picosecond (33.5 MHz) */
-	.left_margin	= 89,
-	.right_margin	= 164,
-	.upper_margin	= 23,
-	.lower_margin	= 10,
-	.hsync_len	= 10,
-	.vsync_len	= 10,
-	.sync		= FB_SYNC_CLK_LAT_FALL,
-};
-
-int board_video_skip(void)
-{
-	int ret;
-	ret = ipuv3_fb_init(&ampire_wvga, 1, IPU_PIX_FMT_RGB666);
-	if (ret)
-		printf("Ampire LCD cannot be configured: %d\n", ret);
-	return ret;
-}
-#endif
-
-#define I2C_PAD_CTRL	(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
-			 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
-
-static void setup_iomux_i2c(void)
-{
-	static const iomux_v3_cfg_t i2c_pads[] = {
-		NEW_PAD_CTRL(MX53_PAD_EIM_D16__I2C2_SDA, I2C_PAD_CTRL),
-		NEW_PAD_CTRL(MX53_PAD_EIM_EB2__I2C2_SCL, I2C_PAD_CTRL),
-	};
-
-	imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
-}
-
-static void setup_iomux_video(void)
-{
-	static const iomux_v3_cfg_t lcd_pads[] = {
-		MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0,
-		MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1,
-		MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2,
-		MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3,
-		MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4,
-		MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5,
-		MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6,
-		MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7,
-		MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8,
-		MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9,
-		MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10,
-		MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11,
-		MX53_PAD_EIM_A17__IPU_DISP1_DAT_12,
-		MX53_PAD_EIM_A18__IPU_DISP1_DAT_13,
-		MX53_PAD_EIM_A19__IPU_DISP1_DAT_14,
-		MX53_PAD_EIM_A20__IPU_DISP1_DAT_15,
-		MX53_PAD_EIM_A21__IPU_DISP1_DAT_16,
-		MX53_PAD_EIM_A22__IPU_DISP1_DAT_17,
-		MX53_PAD_EIM_A23__IPU_DISP1_DAT_18,
-		MX53_PAD_EIM_A24__IPU_DISP1_DAT_19,
-		MX53_PAD_EIM_D31__IPU_DISP1_DAT_20,
-		MX53_PAD_EIM_D30__IPU_DISP1_DAT_21,
-		MX53_PAD_EIM_D26__IPU_DISP1_DAT_22,
-		MX53_PAD_EIM_D27__IPU_DISP1_DAT_23,
-		MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK,
-		MX53_PAD_EIM_DA13__IPU_DI1_D0_CS,
-		MX53_PAD_EIM_DA14__IPU_DI1_D1_CS,
-		MX53_PAD_EIM_DA15__IPU_DI1_PIN1,
-		MX53_PAD_EIM_DA11__IPU_DI1_PIN2,
-		MX53_PAD_EIM_DA12__IPU_DI1_PIN3,
-		MX53_PAD_EIM_A25__IPU_DI1_PIN12,
-		MX53_PAD_EIM_DA10__IPU_DI1_PIN15,
-	};
-
-	imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
-}
-
-static void setup_iomux_nand(void)
-{
-	static const iomux_v3_cfg_t nand_pads[] = {
-		NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B,
-				PAD_CTL_DSE_HIGH),
-		NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B,
-				PAD_CTL_DSE_HIGH),
-		NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE,
-				PAD_CTL_DSE_HIGH),
-		NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE,
-				PAD_CTL_DSE_HIGH),
-		NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B,
-				PAD_CTL_PUS_100K_UP),
-		NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0,
-				PAD_CTL_PUS_100K_UP),
-		NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0,
-				PAD_CTL_DSE_HIGH),
-		NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__EMI_NANDF_D_0,
-				PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
-		NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__EMI_NANDF_D_1,
-				PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
-		NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__EMI_NANDF_D_2,
-				PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
-		NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__EMI_NANDF_D_3,
-				PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
-		NEW_PAD_CTRL(MX53_PAD_PATA_DATA4__EMI_NANDF_D_4,
-				PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
-		NEW_PAD_CTRL(MX53_PAD_PATA_DATA5__EMI_NANDF_D_5,
-				PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
-		NEW_PAD_CTRL(MX53_PAD_PATA_DATA6__EMI_NANDF_D_6,
-				PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
-		NEW_PAD_CTRL(MX53_PAD_PATA_DATA7__EMI_NANDF_D_7,
-				PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
-	};
-
-	imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
-}
-
-static void m53_set_clock(void)
-{
-	int ret;
-	const uint32_t ref_clk = MXC_HCLK;
-	const uint32_t dramclk = 400;
-	uint32_t cpuclk;
-
-	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_10__GPIO4_0,
-					    PAD_CTL_DSE_HIGH | PAD_CTL_PKE));
-	gpio_direction_input(IMX_GPIO_NR(4, 0));
-
-	/* GPIO10 selects modules' CPU speed, 1 = 1200MHz ; 0 = 800MHz */
-	cpuclk = gpio_get_value(IMX_GPIO_NR(4, 0)) ? 1200 : 800;
-
-	ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK);
-	if (ret)
-		printf("CPU:   Switch CPU clock to %dMHz failed\n", cpuclk);
-
-	ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK);
-	if (ret) {
-		printf("CPU:   Switch peripheral clock to %dMHz failed\n",
-			dramclk);
-	}
-
-	ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK);
-	if (ret)
-		printf("CPU:   Switch DDR clock to %dMHz failed\n", dramclk);
-}
-
-static void m53_set_nand(void)
-{
-	u32 i;
-
-	/* NAND flash is muxed on ATA pins */
-	setbits_le32(M4IF_BASE_ADDR + 0xc, M4IF_GENP_WEIM_MM_MASK);
-
-	/* Wait for Grant/Ack sequence (see EIM_CSnGCR2:MUX16_BYP_GRANT) */
-	for (i = 0x4; i < 0x94; i += 0x18) {
-		clrbits_le32(WEIM_BASE_ADDR + i,
-			     WEIM_GCR2_MUX16_BYP_GRANT_MASK);
-	}
-
-	mxc_set_clock(0, 33, MXC_NFC_CLK);
-	enable_nfc_clk(1);
-}
-
-int board_early_init_f(void)
-{
-	setup_iomux_uart();
-	setup_iomux_fec();
-	setup_iomux_i2c();
-	setup_iomux_nand();
-	setup_iomux_video();
-
-	m53_set_clock();
-
-	mxc_set_sata_internal_clock();
-
-	/* NAND clock @ 33MHz */
-	m53_set_nand();
-
-	return 0;
-}
-
-int board_init(void)
-{
-	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
-	return 0;
-}
-
-int checkboard(void)
-{
-	puts("Board: Aries M53EVK\n");
-
-	return 0;
-}
-
-/*
- * NAND SPL
- */
-#ifdef CONFIG_SPL_BUILD
-void spl_board_init(void)
-{
-	setup_iomux_nand();
-	m53_set_clock();
-	m53_set_nand();
-}
-
-u32 spl_boot_device(void)
-{
-	return BOOT_DEVICE_NAND;
-}
-#endif

board/aries/ma5d4evk/Kconfig

@@ -1,12 +0,0 @@
-if TARGET_MA5D4EVK
-
-config SYS_BOARD
-	default "ma5d4evk"
-
-config SYS_VENDOR
-	default "aries"
-
-config SYS_CONFIG_NAME
-	default "ma5d4evk"
-
-endif

board/aries/ma5d4evk/MAINTAINERS

@@ -1,6 +0,0 @@
-Aries MA5D4EVK BOARD
-#M:	Marek Vasut <marek.vasut@gmail.com>
-S:	Orphan (since 2017-07)
-F:	board/aries/ma5d4evk/
-F:	include/configs/ma5d4evk.h
-F:	configs/ma5d4evk_defconfig

board/aries/ma5d4evk/Makefile

@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2015 Marek Vasut <marex@denx.de>
-
-obj-y += ma5d4evk.o

board/aries/ma5d4evk/ma5d4evk.c

@@ -1,456 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2015 Marek Vasut <marex@denx.de>
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_rstc.h>
-#include <asm/arch/atmel_mpddrc.h>
-#include <asm/arch/atmel_usba_udc.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/sama5d3_smc.h>
-#include <asm/arch/sama5d4.h>
-#include <atmel_hlcdc.h>
-#include <atmel_mci.h>
-#include <lcd.h>
-#include <mmc.h>
-#include <net.h>
-#include <netdev.h>
-#include <spi.h>
-#include <spi_flash.h>
-#include <spl.h>
-#include <version.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static u8 boot_mode_sf;
-
-/* FIXME gpio code here need to handle through DM_GPIO */
-#ifndef CONFIG_DM_SPI
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
-	return bus == 0 && cs == 0;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
-	at91_set_pio_output(AT91_PIO_PORTC, 3, 0);
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
-	at91_set_pio_output(AT91_PIO_PORTC, 3, 1);
-}
-
-static void ma5d4evk_spi0_hw_init(void)
-{
-	at91_pio3_set_a_periph(AT91_PIO_PORTC, 0, 0);	/* SPI0_MISO */
-	at91_pio3_set_a_periph(AT91_PIO_PORTC, 1, 0);	/* SPI0_MOSI */
-	at91_pio3_set_a_periph(AT91_PIO_PORTC, 2, 0);	/* SPI0_SPCK */
-
-	at91_set_pio_output(AT91_PIO_PORTC, 3, 1);	/* SPI0_CS0 */
-
-	/* Enable clock */
-	at91_periph_clk_enable(ATMEL_ID_SPI0);
-}
-#endif /* CONFIG_DM_SPI */
-
-#ifdef CONFIG_CMD_USB
-static void ma5d4evk_usb_hw_init(void)
-{
-	at91_set_pio_output(AT91_PIO_PORTE, 11, 0);
-	at91_set_pio_output(AT91_PIO_PORTE, 14, 0);
-}
-#endif
-
-#ifdef CONFIG_LCD
-vidinfo_t panel_info = {
-	.vl_col			= 800,
-	.vl_row			= 480,
-	.vl_clk			= 33500000,
-	.vl_bpix		= LCD_BPP,
-	.vl_tft			= 1,
-	.vl_hsync_len		= 10,
-	.vl_left_margin		= 89,
-	.vl_right_margin	= 164,
-	.vl_vsync_len		= 10,
-	.vl_upper_margin	= 23,
-	.vl_lower_margin	= 10,
-	.mmio			= ATMEL_BASE_LCDC,
-};
-
-/* No power up/down pin for the LCD pannel */
-void lcd_enable(void)	{ /* Empty! */ }
-void lcd_disable(void)	{ /* Empty! */ }
-
-unsigned int has_lcdc(void)
-{
-	return 1;
-}
-
-static void ma5d4evk_lcd_hw_init(void)
-{
-	at91_pio3_set_a_periph(AT91_PIO_PORTA, 24, 1);	/* LCDPWM */
-	at91_pio3_set_a_periph(AT91_PIO_PORTA, 25, 0);	/* LCDDISP */
-	at91_pio3_set_a_periph(AT91_PIO_PORTA, 26, 0);	/* LCDVSYNC */
-	at91_pio3_set_a_periph(AT91_PIO_PORTA, 27, 0);	/* LCDHSYNC */
-	at91_pio3_set_a_periph(AT91_PIO_PORTA, 28, 0);	/* LCDDOTCK */
-	at91_pio3_set_a_periph(AT91_PIO_PORTA, 29, 1);	/* LCDDEN */
-
-	at91_pio3_set_a_periph(AT91_PIO_PORTA,  0, 0);	/* LCDD0 */
-	at91_pio3_set_a_periph(AT91_PIO_PORTA,  1, 0);	/* LCDD1 */
-	at91_pio3_set_a_periph(AT91_PIO_PORTA,  2, 0);	/* LCDD2 */
-	at91_pio3_set_a_periph(AT91_PIO_PORTA,  3, 0);	/* LCDD3 */
-	at91_pio3_set_a_periph(AT91_PIO_PORTA,  4, 0);	/* LCDD4 */
-	at91_pio3_set_a_periph(AT91_PIO_PORTA,  5, 0);	/* LCDD5 */
-	at91_pio3_set_a_periph(AT91_PIO_PORTA,  6, 0);	/* LCDD6 */
-	at91_pio3_set_a_periph(AT91_PIO_PORTA,  7, 0);	/* LCDD7 */
-
-	at91_pio3_set_a_periph(AT91_PIO_PORTA,  8, 0);	/* LCDD9 */
-	at91_pio3_set_a_periph(AT91_PIO_PORTA,  9, 0);	/* LCDD8 */
-	at91_pio3_set_a_periph(AT91_PIO_PORTA, 10, 0);	/* LCDD10 */
-	at91_pio3_set_a_periph(AT91_PIO_PORTA, 11, 0);	/* LCDD11 */
-	at91_pio3_set_a_periph(AT91_PIO_PORTA, 12, 0);	/* LCDD12 */
-	at91_pio3_set_a_periph(AT91_PIO_PORTA, 13, 0);	/* LCDD13 */
-	at91_pio3_set_a_periph(AT91_PIO_PORTA, 14, 0);	/* LCDD14 */
-	at91_pio3_set_a_periph(AT91_PIO_PORTA, 15, 0);	/* LCDD15 */
-
-	at91_pio3_set_a_periph(AT91_PIO_PORTA, 16, 0);	/* LCDD16 */
-	at91_pio3_set_a_periph(AT91_PIO_PORTA, 17, 0);	/* LCDD17 */
-	at91_pio3_set_a_periph(AT91_PIO_PORTA, 18, 0);	/* LCDD18 */
-	at91_pio3_set_a_periph(AT91_PIO_PORTA, 19, 0);	/* LCDD19 */
-	at91_pio3_set_a_periph(AT91_PIO_PORTA, 20, 0);	/* LCDD20 */
-	at91_pio3_set_a_periph(AT91_PIO_PORTA, 21, 0);	/* LCDD21 */
-	at91_pio3_set_a_periph(AT91_PIO_PORTA, 22, 0);	/* LCDD22 */
-	at91_pio3_set_a_periph(AT91_PIO_PORTA, 23, 0);	/* LCDD23 */
-
-	/* Enable clock */
-	at91_periph_clk_enable(ATMEL_ID_LCDC);
-}
-
-#endif /* CONFIG_LCD */
-
-#ifdef CONFIG_GENERIC_ATMEL_MCI
-/* On-SoM eMMC */
-void ma5d4evk_mci0_hw_init(void)
-{
-	at91_pio3_set_b_periph(AT91_PIO_PORTC, 5, 1);	/* MCI1 CDA */
-	at91_pio3_set_b_periph(AT91_PIO_PORTC, 6, 1);	/* MCI1 DA0 */
-	at91_pio3_set_b_periph(AT91_PIO_PORTC, 7, 1);	/* MCI1 DA1 */
-	at91_pio3_set_b_periph(AT91_PIO_PORTC, 8, 1);	/* MCI1 DA2 */
-	at91_pio3_set_b_periph(AT91_PIO_PORTC, 9, 1);	/* MCI1 DA3 */
-	at91_pio3_set_b_periph(AT91_PIO_PORTC, 10, 1);	/* MCI1 DA4 */
-	at91_pio3_set_b_periph(AT91_PIO_PORTC, 11, 1);	/* MCI1 DA5 */
-	at91_pio3_set_b_periph(AT91_PIO_PORTC, 12, 1);	/* MCI1 DA6 */
-	at91_pio3_set_b_periph(AT91_PIO_PORTC, 13, 1);	/* MCI1 DA7 */
-	at91_pio3_set_b_periph(AT91_PIO_PORTC, 4, 0);	/* MCI1 CLK */
-
-	/*
-	 * As the mci io internal pull down is too strong, so if the io needs
-	 * external pull up, the pull up resistor will be very small, if so
-	 * the power consumption will increase, so disable the internal pull
-	 * down to save the power.
-	 */
-	at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 5, 0);
-	at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 6, 0);
-	at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 7, 0);
-	at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 8, 0);
-	at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 9, 0);
-	at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 10, 0);
-	at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 11, 0);
-	at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 12, 0);
-	at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 13, 0);
-	at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 4, 0);
-
-	/* Enable clock */
-	at91_periph_clk_enable(ATMEL_ID_MCI0);
-}
-
-/* On-board MicroSD slot */
-void ma5d4evk_mci1_hw_init(void)
-{
-	at91_pio3_set_c_periph(AT91_PIO_PORTE, 19, 1);	/* MCI1 CDA */
-	at91_pio3_set_c_periph(AT91_PIO_PORTE, 20, 1);	/* MCI1 DA0 */
-	at91_pio3_set_c_periph(AT91_PIO_PORTE, 21, 1);	/* MCI1 DA1 */
-	at91_pio3_set_c_periph(AT91_PIO_PORTE, 22, 1);	/* MCI1 DA2 */
-	at91_pio3_set_c_periph(AT91_PIO_PORTE, 23, 1);	/* MCI1 DA3 */
-	at91_pio3_set_c_periph(AT91_PIO_PORTE, 18, 0);	/* MCI1 CLK */
-
-	/*
-	 * As the mci io internal pull down is too strong, so if the io needs
-	 * external pull up, the pull up resistor will be very small, if so
-	 * the power consumption will increase, so disable the internal pull
-	 * down to save the power.
-	 */
-	at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 18, 0);
-	at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 19, 0);
-	at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 20, 0);
-	at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 21, 0);
-	at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 22, 0);
-	at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 23, 0);
-
-	/* Deal with WP pin on the microSD slot. */
-	at91_set_pio_output(AT91_PIO_PORTE, 16, 0);
-	at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 16, 1);
-
-	/* Enable clock */
-	at91_periph_clk_enable(ATMEL_ID_MCI1);
-}
-
-int board_mmc_init(bd_t *bis)
-{
-	int ret;
-	void *mci0 = (void *)ATMEL_BASE_MCI0;
-	void *mci1 = (void *)ATMEL_BASE_MCI1;
-
-	/* De-assert reset on On-SoM eMMC */
-	at91_set_pio_output(AT91_PIO_PORTE, 15, 1);
-	at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 15, 0);
-
-	ret = atmel_mci_init(boot_mode_sf ? mci0 : mci1);
-	if (ret)	/* eMMC init failed, skip it. */
-		at91_set_pio_output(AT91_PIO_PORTE, 15, 0);
-
-	/* Enable the power supply to On-board MicroSD */
-	at91_set_pio_output(AT91_PIO_PORTE, 17, 0);
-	ret = atmel_mci_init(boot_mode_sf ? mci1 : mci0);
-	if (ret)	/* uSD init failed, power it down. */
-		at91_set_pio_output(AT91_PIO_PORTE, 17, 1);
-
-	return 0;
-}
-#endif /* CONFIG_GENERIC_ATMEL_MCI */
-
-#ifdef CONFIG_MACB
-void ma5d4evk_macb0_hw_init(void)
-{
-	at91_pio3_set_a_periph(AT91_PIO_PORTB, 0, 0);	/* ETXCK_EREFCK */
-	at91_pio3_set_a_periph(AT91_PIO_PORTB, 6, 0);	/* ERXDV */
-	at91_pio3_set_a_periph(AT91_PIO_PORTB, 8, 0);	/* ERX0 */
-	at91_pio3_set_a_periph(AT91_PIO_PORTB, 9, 0);	/* ERX1 */
-	at91_pio3_set_a_periph(AT91_PIO_PORTB, 7, 0);	/* ERXER */
-	at91_pio3_set_a_periph(AT91_PIO_PORTB, 2, 0);	/* ETXEN */
-	at91_pio3_set_a_periph(AT91_PIO_PORTB, 12, 0);	/* ETX0 */
-	at91_pio3_set_a_periph(AT91_PIO_PORTB, 13, 0);	/* ETX1 */
-	at91_pio3_set_a_periph(AT91_PIO_PORTB, 17, 0);	/* EMDIO */
-	at91_pio3_set_a_periph(AT91_PIO_PORTB, 16, 0);	/* EMDC */
-
-	/* Enable clock */
-	at91_periph_clk_enable(ATMEL_ID_GMAC0);
-}
-#endif
-
-static void ma5d4evk_serial_hw_init(void)
-{
-	/* USART0 */
-	at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1);	/* TXD */
-	at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 0);	/* RXD */
-	at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 0);	/* RTS */
-	at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 0);	/* CTS */
-	at91_periph_clk_enable(ATMEL_ID_USART0);
-
-	/* USART1 */
-	at91_pio3_set_a_periph(AT91_PIO_PORTD, 17, 1);	/* TXD */
-	at91_pio3_set_a_periph(AT91_PIO_PORTD, 16, 0);	/* RXD */
-	at91_pio3_set_a_periph(AT91_PIO_PORTD, 15, 0);	/* RTS */
-	at91_pio3_set_a_periph(AT91_PIO_PORTD, 14, 0);	/* CTS */
-	at91_periph_clk_enable(ATMEL_ID_USART1);
-}
-
-int board_early_init_f(void)
-{
-	at91_periph_clk_enable(ATMEL_ID_PIOA);
-	at91_periph_clk_enable(ATMEL_ID_PIOB);
-	at91_periph_clk_enable(ATMEL_ID_PIOC);
-	at91_periph_clk_enable(ATMEL_ID_PIOD);
-	at91_periph_clk_enable(ATMEL_ID_PIOE);
-
-	/* Configure LEDs as OFF */
-	at91_set_pio_output(AT91_PIO_PORTD, 28, 0);
-	at91_set_pio_output(AT91_PIO_PORTD, 29, 0);
-	at91_set_pio_output(AT91_PIO_PORTD, 30, 0);
-
-	ma5d4evk_serial_hw_init();
-
-	return 0;
-}
-
-static void board_identify(void)
-{
-	struct spi_flash *sf;
-	sf = spi_flash_probe(CONFIG_SF_DEFAULT_BUS, CONFIG_SF_DEFAULT_CS,
-			     CONFIG_SF_DEFAULT_SPEED, CONFIG_SF_DEFAULT_MODE);
-	boot_mode_sf = (sf != NULL);
-}
-
-int board_init(void)
-{
-	/* adress of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
-#ifndef CONFIG_DM_SPI
-	ma5d4evk_spi0_hw_init();
-#endif
-#ifdef CONFIG_GENERIC_ATMEL_MCI
-	ma5d4evk_mci0_hw_init();
-	ma5d4evk_mci1_hw_init();
-#endif
-#ifdef CONFIG_MACB
-	ma5d4evk_macb0_hw_init();
-#endif
-#ifdef CONFIG_LCD
-	ma5d4evk_lcd_hw_init();
-#endif
-#ifdef CONFIG_CMD_USB
-	ma5d4evk_usb_hw_init();
-#endif
-#ifdef CONFIG_USB_GADGET_ATMEL_USBA
-	at91_udp_hw_init();
-#endif
-
-	board_identify();
-
-	/* Reset CAN controllers */
-	at91_set_pio_output(AT91_PIO_PORTB, 21, 0);
-	udelay(100);
-	at91_set_pio_output(AT91_PIO_PORTB, 21, 1);
-	at91_pio3_set_pio_pulldown(AT91_PIO_PORTB, 21, 0);
-
-	return 0;
-}
-
-int board_late_init(void)
-{
-	env_set("bootmode", boot_mode_sf ? "sf" : "emmc");
-	return 0;
-}
-
-int dram_init(void)
-{
-	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
-				    CONFIG_SYS_SDRAM_SIZE);
-	return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
-	int rc = 0;
-
-#ifdef CONFIG_MACB
-	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC0, 0x00);
-#endif
-
-#ifdef CONFIG_USB_GADGET_ATMEL_USBA
-	usba_udc_probe(&pdata);
-#ifdef CONFIG_USB_ETH_RNDIS
-	usb_eth_initialize(bis);
-#endif
-#endif
-
-	return rc;
-}
-
-/* SPL */
-#ifdef CONFIG_SPL_BUILD
-void spl_board_init(void)
-{
-#ifndef CONFIG_DM_SPI
-	ma5d4evk_spi0_hw_init();
-#endif
-#ifdef CONFIG_GENERIC_ATMEL_MCI
-	ma5d4evk_mci0_hw_init();
-	ma5d4evk_mci1_hw_init();
-#endif
-	board_identify();
-}
-
-void board_boot_order(u32 *spl_boot_list)
-{
-	spl_boot_list[0] = spl_boot_device();
-
-	switch (spl_boot_list[0]) {
-	case BOOT_DEVICE_MMC1:
-	case BOOT_DEVICE_MMC2:
-		spl_boot_list[0] = BOOT_DEVICE_MMC1;
-		break;
-	case BOOT_DEVICE_SPI:
-		break;
-	case BOOT_DEVICE_USB:
-		spl_boot_list[0] = BOOT_DEVICE_MMC2;
-		break;
-	}
-}
-
-static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
-{
-	ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
-
-	ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
-		    ATMEL_MPDDRC_CR_NR_ROW_13 |
-		    ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
-		    ATMEL_MPDDRC_CR_NB_8BANKS |
-		    ATMEL_MPDDRC_CR_NDQS_DISABLED |
-		    ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
-
-	ddr2->rtr = 0x2b0;
-
-	ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
-		      3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
-		      3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
-		      10 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
-		      3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
-		      2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
-		      2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
-		      2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
-
-	ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
-		      200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
-		      25 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
-		      23 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
-
-	ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
-		      2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
-		      3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
-		      2 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
-		      8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
-}
-
-void mem_init(void)
-{
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-	struct atmel_mpddrc_config ddr2;
-
-	ddr2_conf(&ddr2);
-
-	/* enable MPDDR clock */
-	at91_periph_clk_enable(ATMEL_ID_MPDDRC);
-	writel(AT91_PMC_DDR, &pmc->scer);
-
-	/* DDRAM2 Controller initialize */
-	ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
-}
-
-void at91_pmc_init(void)
-{
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-	u32 tmp;
-
-	tmp = AT91_PMC_PLLAR_29 |
-	      AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
-	      AT91_PMC_PLLXR_MUL(87) |
-	      AT91_PMC_PLLXR_DIV(1);
-	at91_plla_init(tmp);
-
-	writel(0x0 << 8, &pmc->pllicpr);
-
-	tmp = AT91_PMC_MCKR_H32MXDIV |
-	      AT91_PMC_MCKR_PLLADIV_2 |
-	      AT91_PMC_MCKR_MDIV_3 |
-	      AT91_PMC_MCKR_CSS_PLLA;
-	at91_mck_init(tmp);
-}
-#endif

board/aries/mcvevk/MAINTAINERS

@@ -1,5 +0,0 @@
-Aries MCVEVK BOARD
-#M:	Marek Vasut <marek.vasut@gmail.com>
-S:	Orphan (since 2017-07)
-F:	include/configs/socfpga_mcvevk.h
-F:	configs/socfpga_mcvevk_defconfig

board/aries/mcvevk/Makefile

@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
-
-obj-y	:= socfpga.o

board/aries/mcvevk/qts/iocsr_config.h

@@ -1,659 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Altera SoCFPGA IOCSR configuration
- */
-
-#ifndef __SOCFPGA_IOCSR_CONFIG_H__
-#define __SOCFPGA_IOCSR_CONFIG_H__
-
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH	764
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH	1719
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH	955
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH	16766
-
-const unsigned long iocsr_scan_chain0_table[] = {
-	0x00000000,
-	0x00000000,
-	0x0FF00000,
-	0xC0000000,
-	0x0000003F,
-	0x00008000,
-	0x00000000,
-	0x18060000,
-	0x00000060,
-	0x00000000,
-	0x00000000,
-	0x00004000,
-	0x0C0300C0,
-	0x00000000,
-	0x0C000000,
-	0x0000C030,
-	0x0000C030,
-	0x00002000,
-	0x06018060,
-	0x06018000,
-	0x06000018,
-	0x00006018,
-	0x01806018,
-	0x00001000,
-};
-
-const unsigned long iocsr_scan_chain1_table[] = {
-	0x000C0300,
-	0x300C0000,
-	0x300000C0,
-	0x000000C0,
-	0x000300C0,
-	0x00008000,
-	0x00060180,
-	0x18060000,
-	0x18000000,
-	0x00000060,
-	0x00018060,
-	0x00004000,
-	0x000300C0,
-	0x0C030000,
-	0x0C000000,
-	0x00000030,
-	0x0000C030,
-	0x00002000,
-	0x00018060,
-	0x06018000,
-	0x01FE0000,
-	0xF8000000,
-	0x00000007,
-	0x00001000,
-	0x0300C030,
-	0x00000000,
-	0x03000000,
-	0x0000000C,
-	0x00000000,
-	0x00000800,
-	0x00006018,
-	0x01806000,
-	0x00000000,
-	0x00000000,
-	0x00001806,
-	0x00000400,
-	0x0000300C,
-	0x00C03000,
-	0x00C00000,
-	0x00000003,
-	0x00000C03,
-	0x00000200,
-	0x00001806,
-	0x00601800,
-	0x80600000,
-	0x80000001,
-	0x00000601,
-	0x00000100,
-	0x00001000,
-	0x00300C00,
-	0xC0300000,
-	0xC0000000,
-	0x00000300,
-	0x00000080,
-};
-
-const unsigned long iocsr_scan_chain2_table[] = {
-	0x300C0300,
-	0x00000000,
-	0x0FF00000,
-	0x00000000,
-	0x0C0300C0,
-	0x00008000,
-	0x00060180,
-	0x00000000,
-	0x18000000,
-	0x00018060,
-	0x06018060,
-	0x00004000,
-	0x200300C0,
-	0x0C030000,
-	0x0C000000,
-	0x00000030,
-	0x0000C030,
-	0x00002000,
-	0x00018060,
-	0x00000000,
-	0x06000000,
-	0x00010018,
-	0x01806018,
-	0x00001000,
-	0x0000C030,
-	0x00000000,
-	0x03000000,
-	0x0000000C,
-	0x00C0300C,
-	0x00000800,
-};
-
-const unsigned long iocsr_scan_chain3_table[] = {
-	0x0C420D80,
-	0x0C3000FF,
-	0x0A804001,
-	0x07900000,
-	0x08020000,
-	0x00100000,
-	0x0A800000,
-	0x07900000,
-	0x08020000,
-	0x00100000,
-	0x20430000,
-	0x0C003001,
-	0x00C00481,
-	0x00000000,
-	0x00000021,
-	0x82000004,
-	0x05400000,
-	0x03C80000,
-	0x04010000,
-	0x00080000,
-	0x05400000,
-	0x03C80000,
-	0x05400000,
-	0x03C80000,
-	0x90218000,
-	0x86001800,
-	0x00600240,
-	0x80090218,
-	0x00000001,
-	0x40000002,
-	0x02A00000,
-	0x01E40000,
-	0x02A00000,
-	0x01E40000,
-	0x02A00000,
-	0x01E40000,
-	0x02A00000,
-	0x01E40000,
-	0x4810C000,
-	0x43000C00,
-	0x00300120,
-	0xC004810C,
-	0x12043000,
-	0x20000300,
-	0x00040000,
-	0x50670000,
-	0x00000010,
-	0x24590000,
-	0x00001000,
-	0xA0000034,
-	0x0D000001,
-	0xC0680A28,
-	0x45034030,
-	0x12481A01,
-	0x80A280D0,
-	0x34030C06,
-	0x01A01450,
-	0x280D0000,
-	0x30C0680A,
-	0x02490340,
-	0xD000001A,
-	0x0680A280,
-	0x10040000,
-	0x00200000,
-	0x10040000,
-	0x00200000,
-	0x15000000,
-	0x0F200000,
-	0x15000000,
-	0x0F200000,
-	0x01FE0000,
-	0x18000000,
-	0x01800902,
-	0x00240860,
-	0x007F8006,
-	0x00000000,
-	0x0A800001,
-	0x07900000,
-	0x0A800000,
-	0x07900000,
-	0x0A800000,
-	0x07900000,
-	0x08020000,
-	0x00100000,
-	0x20430000,
-	0x0C003001,
-	0x00C00481,
-	0x00000FF0,
-	0x4810C000,
-	0x80000C00,
-	0x05400000,
-	0x02480000,
-	0x04000000,
-	0x00080000,
-	0x05400000,
-	0x03C80000,
-	0x05400000,
-	0x03C80000,
-	0x90218000,
-	0x86001800,
-	0x00600240,
-	0x80090218,
-	0x24086001,
-	0x40000600,
-	0x02A00040,
-	0x01E40000,
-	0x02A00000,
-	0x01E40000,
-	0x02A00000,
-	0x01E40000,
-	0x02A00000,
-	0x01E40000,
-	0x4810C000,
-	0x43000C00,
-	0x00300120,
-	0xC004810C,
-	0x12043000,
-	0x20000300,
-	0x00040000,
-	0x50670000,
-	0x00000010,
-	0x24590000,
-	0x00001000,
-	0xA0000034,
-	0x0D000001,
-	0xC0680A28,
-	0x49034030,
-	0x12481A02,
-	0x80A280D0,
-	0x34030C06,
-	0x01A00040,
-	0x280D0002,
-	0x30C0680A,
-	0x02490340,
-	0xD00A281A,
-	0x0680A280,
-	0x10040000,
-	0x00200000,
-	0x10040000,
-	0x00200000,
-	0x15000000,
-	0x0F200000,
-	0x15000000,
-	0x0F200000,
-	0x01FE0000,
-	0x18000000,
-	0x01800902,
-	0x00240860,
-	0x007F8006,
-	0x00000000,
-	0x99300001,
-	0x34343400,
-	0xAA0D4000,
-	0x01C3A800,
-	0xAA0D4000,
-	0x01C3A890,
-	0xAA0D4000,
-	0x01C3A800,
-	0x00040100,
-	0x00000800,
-	0x00000000,
-	0x00001208,
-	0x00482000,
-	0x01000000,
-	0x00000000,
-	0x00410482,
-	0x0006A000,
-	0x0001B400,
-	0x00020000,
-	0x00000400,
-	0x0002A000,
-	0x0001E400,
-	0x5506A000,
-	0x00E1D400,
-	0x00000000,
-	0x2043090C,
-	0x00003001,
-	0x90400000,
-	0x00000000,
-	0x2020C243,
-	0x2A835000,
-	0x0070EA00,
-	0x2A835000,
-	0x0070EA24,
-	0x2A835000,
-	0x0070EA00,
-	0x00010040,
-	0x00000200,
-	0x00000000,
-	0x00000482,
-	0x00120800,
-	0x00002000,
-	0x80000000,
-	0x00104120,
-	0x00000200,
-	0xAC0D5F80,
-	0xFFFFFFFF,
-	0x14F3690D,
-	0x1A041414,
-	0x00D00000,
-	0x18864000,
-	0x49247A06,
-	0x9A28A3D7,
-	0xF511451E,
-	0x0356E388,
-	0x821A0000,
-	0x0000D000,
-	0x05140680,
-	0xD749247A,
-	0x1E9A28A3,
-	0x88F51145,
-	0x00034EE3,
-	0x00080000,
-	0x00001000,
-	0x00080200,
-	0x00001000,
-	0x000A8000,
-	0x00075000,
-	0x541A8000,
-	0x03875001,
-	0x00000000,
-	0x00000010,
-	0x0080C000,
-	0x41000000,
-	0x00003FC2,
-	0x00820000,
-	0xAA0D4000,
-	0x01C3A800,
-	0xAA0D4000,
-	0x01C3A890,
-	0xAA0D4000,
-	0x01C3A800,
-	0x00040000,
-	0x00000800,
-	0x00000000,
-	0x00001208,
-	0x00482000,
-	0x00800000,
-	0x00000000,
-	0x00410482,
-	0x0006A000,
-	0x0001B400,
-	0x00020000,
-	0x00000400,
-	0x00020080,
-	0x00000400,
-	0x5506A000,
-	0x00E1D400,
-	0x00000000,
-	0x0000090C,
-	0x00000010,
-	0x90400000,
-	0x00000000,
-	0x2020C243,
-	0x2A835000,
-	0x0070EA00,
-	0x2A835000,
-	0x0070EA24,
-	0x2A835000,
-	0x0070EA00,
-	0x00015000,
-	0x0000F200,
-	0x00000000,
-	0x00000482,
-	0x86120800,
-	0x00600240,
-	0x80000000,
-	0x00104120,
-	0x00000200,
-	0xAC0D5F80,
-	0xFFFFFFFF,
-	0x14F3690D,
-	0x1A041414,
-	0x00D00000,
-	0x18864000,
-	0x49247A06,
-	0xEBCF23D7,
-	0xF611451E,
-	0x034E9248,
-	0x821A038E,
-	0x0000D000,
-	0x00000680,
-	0xD749247A,
-	0x1E9BCF23,
-	0x88F61145,
-	0x00034EE3,
-	0x00080000,
-	0x00001000,
-	0x00080000,
-	0x00001000,
-	0x000A8000,
-	0x00075000,
-	0x541A8000,
-	0x03875001,
-	0x00000000,
-	0x00000010,
-	0x0080C000,
-	0x41000000,
-	0x00000002,
-	0x00820004,
-	0xAA0D4000,
-	0x01C3A800,
-	0xAA0D4000,
-	0x01C3A890,
-	0xAA0D4000,
-	0x01C3A800,
-	0x00040000,
-	0x00000800,
-	0x00000000,
-	0x00001208,
-	0x00482000,
-	0x00800000,
-	0x00000000,
-	0x00410482,
-	0x0006A000,
-	0x0001B400,
-	0x00020000,
-	0x00000400,
-	0x0002A000,
-	0x0001E400,
-	0x5506A000,
-	0x00E1D400,
-	0x00000000,
-	0x2043090C,
-	0x00003001,
-	0x90400000,
-	0x00000000,
-	0x2020C243,
-	0x2A835000,
-	0x0070EA00,
-	0x2A835000,
-	0x0070EA00,
-	0x2A835000,
-	0x0070EA00,
-	0x00010000,
-	0x00000200,
-	0x00000000,
-	0x00000482,
-	0x00120800,
-	0x00200000,
-	0x80000000,
-	0x00104120,
-	0x00000200,
-	0xAC0D5F80,
-	0xFFFFFFFF,
-	0x14F3690D,
-	0x1A041414,
-	0x00D00000,
-	0x18864000,
-	0x49247A06,
-	0x9A28A3D7,
-	0xF431451E,
-	0x034E9248,
-	0x821A0000,
-	0x0000D000,
-	0x00000680,
-	0xD749247A,
-	0x1E9A28A3,
-	0x88F61145,
-	0x000356E3,
-	0x00080000,
-	0x00001000,
-	0x00080000,
-	0x00001000,
-	0x000A8000,
-	0x00075000,
-	0x541A8000,
-	0x03875001,
-	0x00000000,
-	0x00000010,
-	0x0080C000,
-	0x41000000,
-	0x00000002,
-	0x00820004,
-	0xAA0D4000,
-	0x01C3A800,
-	0xAA0D4000,
-	0x01C3A800,
-	0xAA0D4000,
-	0x01C3A800,
-	0x00040000,
-	0x00000800,
-	0x00000000,
-	0x00001208,
-	0x00482000,
-	0x00800000,
-	0x00000000,
-	0x00410482,
-	0x0006A000,
-	0x0001B400,
-	0x00020000,
-	0x00000400,
-	0x00020000,
-	0x00000400,
-	0x5506A000,
-	0x00E1D400,
-	0x00000000,
-	0x0000090C,
-	0x00001000,
-	0x90400000,
-	0x00000000,
-	0x2020C243,
-	0x2A835000,
-	0x0070EA00,
-	0x2A835000,
-	0x0070EA00,
-	0x2A835000,
-	0x0070EA00,
-	0x00010040,
-	0x00000200,
-	0x00000000,
-	0x00000482,
-	0x00120800,
-	0x00400000,
-	0x80000000,
-	0x00104120,
-	0x00000200,
-	0xAC0D5F80,
-	0xFFFFFFFF,
-	0x14F1690D,
-	0x1A041414,
-	0x00D00000,
-	0x08864000,
-	0x49247A02,
-	0xEBCF23DB,
-	0xF431451E,
-	0x0356E388,
-	0x821A0000,
-	0x0000D000,
-	0x00000680,
-	0xD749247A,
-	0x1EEBCF23,
-	0x88F43E79,
-	0x000356A2,
-	0x00080000,
-	0x00001000,
-	0x00080000,
-	0x00001000,
-	0x000A8000,
-	0x00075000,
-	0x541A8000,
-	0x03875001,
-	0x00000000,
-	0x00000010,
-	0x0080C000,
-	0x41000000,
-	0x00000002,
-	0x00820004,
-	0x00489800,
-	0x801A1A1A,
-	0x00000200,
-	0x80000004,
-	0x00000200,
-	0x80000004,
-	0x00000200,
-	0x00000004,
-	0x00000200,
-	0x00000004,
-	0x00040000,
-	0x10000000,
-	0x00000000,
-	0x00004000,
-	0x00010000,
-	0x40002080,
-	0x00000100,
-	0x40000002,
-	0x00000100,
-	0x00000002,
-	0x00000100,
-	0x40000002,
-	0x00000100,
-	0x00000002,
-	0x00020000,
-	0x00000000,
-	0x00000008,
-	0x00000020,
-	0x00008000,
-	0x20001040,
-	0x00000080,
-	0x20000001,
-	0x00000080,
-	0x20000001,
-	0x00000080,
-	0x20000001,
-	0x00000080,
-	0x00000001,
-	0x00010000,
-	0x04000000,
-	0x00FF0000,
-	0x00000000,
-	0x00004000,
-	0x00000800,
-	0xC0000001,
-	0x00041419,
-	0x40000000,
-	0x04000816,
-	0x000D0000,
-	0x00006800,
-	0x00000340,
-	0xD000001A,
-	0x06800000,
-	0x00340000,
-	0x0001A000,
-	0x00000D00,
-	0x40000068,
-	0x1A000003,
-	0x00D00000,
-	0x00068000,
-	0x00003400,
-	0x000001A0,
-	0x00000401,
-	0x00000008,
-	0x00000401,
-	0x00000008,
-	0x00000401,
-	0x00000008,
-	0x00000401,
-	0x80000008,
-	0x0000007F,
-	0x20000000,
-	0x00000000,
-	0xE0000080,
-	0x0000001F,
-	0x00004000,
-};
-
-
-#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */

board/aries/mcvevk/qts/pinmux_config.h

@@ -1,218 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Altera SoCFPGA PinMux configuration
- */
-
-#ifndef __SOCFPGA_PINMUX_CONFIG_H__
-#define __SOCFPGA_PINMUX_CONFIG_H__
-
-const u8 sys_mgr_init_table[] = {
-	3, /* EMACIO0 */
-	3, /* EMACIO1 */
-	3, /* EMACIO2 */
-	3, /* EMACIO3 */
-	3, /* EMACIO4 */
-	3, /* EMACIO5 */
-	3, /* EMACIO6 */
-	3, /* EMACIO7 */
-	3, /* EMACIO8 */
-	3, /* EMACIO9 */
-	3, /* EMACIO10 */
-	3, /* EMACIO11 */
-	3, /* EMACIO12 */
-	3, /* EMACIO13 */
-	0, /* EMACIO14 */
-	0, /* EMACIO15 */
-	0, /* EMACIO16 */
-	0, /* EMACIO17 */
-	0, /* EMACIO18 */
-	0, /* EMACIO19 */
-	3, /* FLASHIO0 */
-	0, /* FLASHIO1 */
-	3, /* FLASHIO2 */
-	3, /* FLASHIO3 */
-	3, /* FLASHIO4 */
-	3, /* FLASHIO5 */
-	3, /* FLASHIO6 */
-	3, /* FLASHIO7 */
-	0, /* FLASHIO8 */
-	3, /* FLASHIO9 */
-	3, /* FLASHIO10 */
-	3, /* FLASHIO11 */
-	0, /* GENERALIO0 */
-	1, /* GENERALIO1 */
-	1, /* GENERALIO2 */
-	0, /* GENERALIO3 */
-	0, /* GENERALIO4 */
-	1, /* GENERALIO5 */
-	1, /* GENERALIO6 */
-	1, /* GENERALIO7 */
-	1, /* GENERALIO8 */
-	0, /* GENERALIO9 */
-	0, /* GENERALIO10 */
-	0, /* GENERALIO11 */
-	0, /* GENERALIO12 */
-	2, /* GENERALIO13 */
-	2, /* GENERALIO14 */
-	1, /* GENERALIO15 */
-	1, /* GENERALIO16 */
-	1, /* GENERALIO17 */
-	1, /* GENERALIO18 */
-	0, /* GENERALIO19 */
-	0, /* GENERALIO20 */
-	0, /* GENERALIO21 */
-	0, /* GENERALIO22 */
-	0, /* GENERALIO23 */
-	0, /* GENERALIO24 */
-	0, /* GENERALIO25 */
-	0, /* GENERALIO26 */
-	0, /* GENERALIO27 */
-	0, /* GENERALIO28 */
-	0, /* GENERALIO29 */
-	0, /* GENERALIO30 */
-	0, /* GENERALIO31 */
-	0, /* MIXED1IO0 */
-	1, /* MIXED1IO1 */
-	1, /* MIXED1IO2 */
-	1, /* MIXED1IO3 */
-	1, /* MIXED1IO4 */
-	0, /* MIXED1IO5 */
-	0, /* MIXED1IO6 */
-	0, /* MIXED1IO7 */
-	1, /* MIXED1IO8 */
-	1, /* MIXED1IO9 */
-	1, /* MIXED1IO10 */
-	1, /* MIXED1IO11 */
-	0, /* MIXED1IO12 */
-	0, /* MIXED1IO13 */
-	0, /* MIXED1IO14 */
-	1, /* MIXED1IO15 */
-	1, /* MIXED1IO16 */
-	1, /* MIXED1IO17 */
-	1, /* MIXED1IO18 */
-	0, /* MIXED1IO19 */
-	0, /* MIXED1IO20 */
-	0, /* MIXED1IO21 */
-	0, /* MIXED2IO0 */
-	0, /* MIXED2IO1 */
-	0, /* MIXED2IO2 */
-	0, /* MIXED2IO3 */
-	0, /* MIXED2IO4 */
-	0, /* MIXED2IO5 */
-	0, /* MIXED2IO6 */
-	0, /* MIXED2IO7 */
-	0, /* GPLINMUX48 */
-	0, /* GPLINMUX49 */
-	0, /* GPLINMUX50 */
-	0, /* GPLINMUX51 */
-	0, /* GPLINMUX52 */
-	0, /* GPLINMUX53 */
-	0, /* GPLINMUX54 */
-	0, /* GPLINMUX55 */
-	0, /* GPLINMUX56 */
-	0, /* GPLINMUX57 */
-	0, /* GPLINMUX58 */
-	0, /* GPLINMUX59 */
-	0, /* GPLINMUX60 */
-	0, /* GPLINMUX61 */
-	0, /* GPLINMUX62 */
-	0, /* GPLINMUX63 */
-	0, /* GPLINMUX64 */
-	0, /* GPLINMUX65 */
-	0, /* GPLINMUX66 */
-	0, /* GPLINMUX67 */
-	0, /* GPLINMUX68 */
-	0, /* GPLINMUX69 */
-	0, /* GPLINMUX70 */
-	1, /* GPLMUX0 */
-	1, /* GPLMUX1 */
-	1, /* GPLMUX2 */
-	1, /* GPLMUX3 */
-	1, /* GPLMUX4 */
-	1, /* GPLMUX5 */
-	1, /* GPLMUX6 */
-	1, /* GPLMUX7 */
-	1, /* GPLMUX8 */
-	1, /* GPLMUX9 */
-	1, /* GPLMUX10 */
-	1, /* GPLMUX11 */
-	1, /* GPLMUX12 */
-	1, /* GPLMUX13 */
-	1, /* GPLMUX14 */
-	1, /* GPLMUX15 */
-	1, /* GPLMUX16 */
-	1, /* GPLMUX17 */
-	1, /* GPLMUX18 */
-	1, /* GPLMUX19 */
-	1, /* GPLMUX20 */
-	1, /* GPLMUX21 */
-	1, /* GPLMUX22 */
-	1, /* GPLMUX23 */
-	1, /* GPLMUX24 */
-	1, /* GPLMUX25 */
-	1, /* GPLMUX26 */
-	1, /* GPLMUX27 */
-	1, /* GPLMUX28 */
-	1, /* GPLMUX29 */
-	1, /* GPLMUX30 */
-	1, /* GPLMUX31 */
-	1, /* GPLMUX32 */
-	1, /* GPLMUX33 */
-	1, /* GPLMUX34 */
-	1, /* GPLMUX35 */
-	1, /* GPLMUX36 */
-	1, /* GPLMUX37 */
-	1, /* GPLMUX38 */
-	1, /* GPLMUX39 */
-	1, /* GPLMUX40 */
-	1, /* GPLMUX41 */
-	1, /* GPLMUX42 */
-	1, /* GPLMUX43 */
-	1, /* GPLMUX44 */
-	1, /* GPLMUX45 */
-	1, /* GPLMUX46 */
-	1, /* GPLMUX47 */
-	1, /* GPLMUX48 */
-	1, /* GPLMUX49 */
-	1, /* GPLMUX50 */
-	1, /* GPLMUX51 */
-	1, /* GPLMUX52 */
-	1, /* GPLMUX53 */
-	1, /* GPLMUX54 */
-	1, /* GPLMUX55 */
-	1, /* GPLMUX56 */
-	1, /* GPLMUX57 */
-	1, /* GPLMUX58 */
-	1, /* GPLMUX59 */
-	1, /* GPLMUX60 */
-	1, /* GPLMUX61 */
-	1, /* GPLMUX62 */
-	1, /* GPLMUX63 */
-	1, /* GPLMUX64 */
-	1, /* GPLMUX65 */
-	1, /* GPLMUX66 */
-	1, /* GPLMUX67 */
-	1, /* GPLMUX68 */
-	1, /* GPLMUX69 */
-	1, /* GPLMUX70 */
-	0, /* NANDUSEFPGA */
-	0, /* UART0USEFPGA */
-	0, /* RGMII1USEFPGA */
-	0, /* SPIS0USEFPGA */
-	0, /* CAN0USEFPGA */
-	0, /* I2C0USEFPGA */
-	0, /* SDMMCUSEFPGA */
-	0, /* QSPIUSEFPGA */
-	0, /* SPIS1USEFPGA */
-	0, /* RGMII0USEFPGA */
-	1, /* UART1USEFPGA */
-	0, /* CAN1USEFPGA */
-	0, /* USB1USEFPGA */
-	0, /* I2C3USEFPGA */
-	0, /* I2C2USEFPGA */
-	0, /* I2C1USEFPGA */
-	0, /* SPIM1USEFPGA */
-	0, /* USB0USEFPGA */
-	0 /* SPIM0USEFPGA */
-};
-#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */

board/aries/mcvevk/qts/pll_config.h

@@ -1,84 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Altera SoCFPGA Clock and PLL configuration
- */
-
-#ifndef __SOCFPGA_PLL_CONFIG_H__
-#define __SOCFPGA_PLL_CONFIG_H__
-
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1
-
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
-#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
-#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
-
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
-#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
-#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 1
-#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
-#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
-#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
-#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
-
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
-#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
-
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000
-#define CONFIG_HPS_CLK_OSC2_HZ 25000000
-#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
-#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
-#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
-#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
-#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
-#define CONFIG_HPS_CLK_EMAC0_HZ 250000000
-#define CONFIG_HPS_CLK_EMAC1_HZ 1953125
-#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
-#define CONFIG_HPS_CLK_NAND_HZ 50000000
-#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
-#define CONFIG_HPS_CLK_QSPI_HZ 3125000
-#define CONFIG_HPS_CLK_SPIM_HZ 200000000
-#define CONFIG_HPS_CLK_CAN0_HZ 100000000
-#define CONFIG_HPS_CLK_CAN1_HZ 100000000
-#define CONFIG_HPS_CLK_GPIODB_HZ 32000
-#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
-#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
-
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
-#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
-#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
-
-
-#endif /* __SOCFPGA_PLL_CONFIG_H__ */

board/aries/mcvevk/qts/sdram_config.h

@@ -1,343 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/*
- * Altera SoCFPGA SDRAM configuration
- */
-
-#ifndef __SOCFPGA_SDRAM_CONFIG_H__
-#define __SOCFPGA_SDRAM_CONFIG_H__
-
-/* SDRAM configuration */
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR		0x5A56A
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP		0xB00088
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH		0x44555
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP		0x2C011000
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER		0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN			0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN		0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN			0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL			8
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE			2
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS			0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN		1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT		10
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH		2
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS		3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS		10
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS			1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS		15
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH		8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH		32
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN			0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ			0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE			1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL			0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL			6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL			6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW			16
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC			140
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD			5
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD		6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI		1560
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP		6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR		6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR		4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD			4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD			4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS			14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC			20
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP			5
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT		3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT		512
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC			0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE			0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST			0x0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK		3
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES	0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES	8
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0	0x20820820
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32	0x8208208
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0	0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4	0x41041041
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36	0x410410
-#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY		0x3FFD1088
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0	0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32	0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64	0x0101
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0	0x21084210
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32	0x1EF84
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0	0x2020
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14	0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46	0xF800
-#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0		0x200
-#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN		0
-#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP		0x760210
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL			2
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA		0
-#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP		0x980543
-
-/* Sequencer auto configuration */
-#define RW_MGR_ACTIVATE_0_AND_1	0x0D
-#define RW_MGR_ACTIVATE_0_AND_1_WAIT1	0x0E
-#define RW_MGR_ACTIVATE_0_AND_1_WAIT2	0x10
-#define RW_MGR_ACTIVATE_1	0x0F
-#define RW_MGR_CLEAR_DQS_ENABLE	0x49
-#define RW_MGR_GUARANTEED_READ	0x4C
-#define RW_MGR_GUARANTEED_READ_CONT	0x54
-#define RW_MGR_GUARANTEED_WRITE	0x18
-#define RW_MGR_GUARANTEED_WRITE_WAIT0	0x1B
-#define RW_MGR_GUARANTEED_WRITE_WAIT1	0x1F
-#define RW_MGR_GUARANTEED_WRITE_WAIT2	0x19
-#define RW_MGR_GUARANTEED_WRITE_WAIT3	0x1D
-#define RW_MGR_IDLE	0x00
-#define RW_MGR_IDLE_LOOP1	0x7B
-#define RW_MGR_IDLE_LOOP2	0x7A
-#define RW_MGR_INIT_RESET_0_CKE_0	0x6F
-#define RW_MGR_INIT_RESET_1_CKE_0	0x74
-#define RW_MGR_LFSR_WR_RD_BANK_0	0x22
-#define RW_MGR_LFSR_WR_RD_BANK_0_DATA	0x25
-#define RW_MGR_LFSR_WR_RD_BANK_0_DQS	0x24
-#define RW_MGR_LFSR_WR_RD_BANK_0_NOP	0x23
-#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT	0x32
-#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1	0x21
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0	0x36
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA	0x39
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS	0x38
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP	0x37
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT	0x46
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1	0x35
-#define RW_MGR_MRS0_DLL_RESET	0x02
-#define RW_MGR_MRS0_DLL_RESET_MIRR	0x08
-#define RW_MGR_MRS0_USER	0x07
-#define RW_MGR_MRS0_USER_MIRR	0x0C
-#define RW_MGR_MRS1	0x03
-#define RW_MGR_MRS1_MIRR	0x09
-#define RW_MGR_MRS2	0x04
-#define RW_MGR_MRS2_MIRR	0x0A
-#define RW_MGR_MRS3	0x05
-#define RW_MGR_MRS3_MIRR	0x0B
-#define RW_MGR_PRECHARGE_ALL	0x12
-#define RW_MGR_READ_B2B	0x59
-#define RW_MGR_READ_B2B_WAIT1	0x61
-#define RW_MGR_READ_B2B_WAIT2	0x6B
-#define RW_MGR_REFRESH_ALL	0x14
-#define RW_MGR_RETURN	0x01
-#define RW_MGR_SGLE_READ	0x7D
-#define RW_MGR_ZQCL	0x06
-
-/* Sequencer defines configuration */
-#define AFI_RATE_RATIO	1
-#define CALIB_LFIFO_OFFSET	7
-#define CALIB_VFIFO_OFFSET	5
-#define ENABLE_SUPER_QUICK_CALIBRATION	0
-#define IO_DELAY_PER_DCHAIN_TAP	25
-#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP	25
-#define IO_DELAY_PER_OPA_TAP	312
-#define IO_DLL_CHAIN_LENGTH	8
-#define IO_DQDQS_OUT_PHASE_MAX	0
-#define IO_DQS_EN_DELAY_MAX	31
-#define IO_DQS_EN_DELAY_OFFSET	0
-#define IO_DQS_EN_PHASE_MAX	7
-#define IO_DQS_IN_DELAY_MAX	31
-#define IO_DQS_IN_RESERVE	4
-#define IO_DQS_OUT_RESERVE	4
-#define IO_IO_IN_DELAY_MAX	31
-#define IO_IO_OUT1_DELAY_MAX	31
-#define IO_IO_OUT2_DELAY_MAX	0
-#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS	0
-#define MAX_LATENCY_COUNT_WIDTH	5
-#define READ_VALID_FIFO_SIZE	16
-#define REG_FILE_INIT_SEQ_SIGNATURE	0x55550496
-#define RW_MGR_MEM_ADDRESS_MIRRORING	0
-#define RW_MGR_MEM_DATA_MASK_WIDTH	4
-#define RW_MGR_MEM_DATA_WIDTH	32
-#define RW_MGR_MEM_DQ_PER_READ_DQS	8
-#define RW_MGR_MEM_DQ_PER_WRITE_DQS	8
-#define RW_MGR_MEM_IF_READ_DQS_WIDTH	4
-#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH	4
-#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM	1
-#define RW_MGR_MEM_NUMBER_OF_RANKS	1
-#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS	1
-#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS	1
-#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH	4
-#define TINIT_CNTR0_VAL	99
-#define TINIT_CNTR1_VAL	32
-#define TINIT_CNTR2_VAL	32
-#define TRESET_CNTR0_VAL	99
-#define TRESET_CNTR1_VAL	99
-#define TRESET_CNTR2_VAL	10
-
-/* Sequencer ac_rom_init configuration */
-const u32 ac_rom_init[] = {
-	0x20700000,
-	0x20780000,
-	0x10080421,
-	0x10080520,
-	0x10090044,
-	0x100a0008,
-	0x100b0000,
-	0x10380400,
-	0x10080441,
-	0x100804c0,
-	0x100a0024,
-	0x10090010,
-	0x100b0000,
-	0x30780000,
-	0x38780000,
-	0x30780000,
-	0x10680000,
-	0x106b0000,
-	0x10280400,
-	0x10480000,
-	0x1c980000,
-	0x1c9b0000,
-	0x1c980008,
-	0x1c9b0008,
-	0x38f80000,
-	0x3cf80000,
-	0x38780000,
-	0x18180000,
-	0x18980000,
-	0x13580000,
-	0x135b0000,
-	0x13580008,
-	0x135b0008,
-	0x33780000,
-	0x10580008,
-	0x10780000
-};
-
-/* Sequencer inst_rom_init configuration */
-const u32 inst_rom_init[] = {
-	0x80000,
-	0x80680,
-	0x8180,
-	0x8200,
-	0x8280,
-	0x8300,
-	0x8380,
-	0x8100,
-	0x8480,
-	0x8500,
-	0x8580,
-	0x8600,
-	0x8400,
-	0x800,
-	0x8680,
-	0x880,
-	0xa680,
-	0x80680,
-	0x900,
-	0x80680,
-	0x980,
-	0xa680,
-	0x8680,
-	0x80680,
-	0xb68,
-	0xcce8,
-	0xae8,
-	0x8ce8,
-	0xb88,
-	0xec88,
-	0xa08,
-	0xac88,
-	0x80680,
-	0xce00,
-	0xcd80,
-	0xe700,
-	0xc00,
-	0x20ce0,
-	0x20ce0,
-	0x20ce0,
-	0x20ce0,
-	0xd00,
-	0x680,
-	0x680,
-	0x680,
-	0x680,
-	0x60e80,
-	0x61080,
-	0x61080,
-	0x61080,
-	0xa680,
-	0x8680,
-	0x80680,
-	0xce00,
-	0xcd80,
-	0xe700,
-	0xc00,
-	0x30ce0,
-	0x30ce0,
-	0x30ce0,
-	0x30ce0,
-	0xd00,
-	0x680,
-	0x680,
-	0x680,
-	0x680,
-	0x70e80,
-	0x71080,
-	0x71080,
-	0x71080,
-	0xa680,
-	0x8680,
-	0x80680,
-	0x1158,
-	0x6d8,
-	0x80680,
-	0x1168,
-	0x7e8,
-	0x7e8,
-	0x87e8,
-	0x40fe8,
-	0x410e8,
-	0x410e8,
-	0x410e8,
-	0x1168,
-	0x7e8,
-	0x7e8,
-	0xa7e8,
-	0x80680,
-	0x40e88,
-	0x41088,
-	0x41088,
-	0x41088,
-	0x40f68,
-	0x410e8,
-	0x410e8,
-	0x410e8,
-	0xa680,
-	0x40fe8,
-	0x410e8,
-	0x410e8,
-	0x410e8,
-	0x41008,
-	0x41088,
-	0x41088,
-	0x41088,
-	0x1100,
-	0xc680,
-	0x8680,
-	0xe680,
-	0x80680,
-	0x0,
-	0x8000,
-	0xa000,
-	0xc000,
-	0x80000,
-	0x80,
-	0x8080,
-	0xa080,
-	0xc080,
-	0x80080,
-	0x9180,
-	0x8680,
-	0xa680,
-	0x80680,
-	0x40f08,
-	0x80680
-};
-
-#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */

board/aries/mcvevk/socfpga.c

@@ -1,5 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2015 Marek Vasut <marex@denx.de>
- */
-#include <common.h>

board/efi/efi-x86_app/MAINTAINERS

@@ -1,6 +1,6 @@
-EFI-X86 BOARD
+EFI-X86_APP BOARD
 M:	Simon Glass <sjg@chromium.org>
 S:	Maintained
-F:	board/efi/efi-x86/
-F:	include/configs/efi-x86.h
-F:	configs/efi-x86_defconfig
+F:	board/efi/efi-x86_app/
+F:	include/configs/efi-x86_app.h
+F:	configs/efi-x86_app_defconfig

board/efi/efi-x86_payload/Kconfig

@@ -17,6 +17,7 @@ config SYS_TEXT_BASE
 
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
+	select BOARD_EARLY_INIT_R
 	imply SYS_NS16550
 	imply SCSI
 	imply SCSI_AHCI

board/efi/efi-x86_payload/Makefile

@@ -2,4 +2,4 @@
 #
 # Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
 
-obj-y	+= start.o
+obj-y	+= start.o payload.o

board/efi/efi-x86_payload/payload.c

@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <common.h>
+#include <usb.h>
+
+int board_early_init_r(void)
+{
+	/*
+	 * Make sure PCI bus is enumerated so that peripherals on the PCI bus
+	 * can be discovered by their drivers
+	 */
+	pci_init();
+
+	return 0;
+}

board/engicam/common/board.c

@@ -50,8 +50,8 @@ static void setenv_fdt_file(void)
 			env_set("fdt_file", "imx6q-icore-rqs.dtb");
 		else if (is_mx6dl() || is_mx6solo())
 			env_set("fdt_file", "imx6dl-icore-rqs.dtb");
-	} else if (!strcmp(cmp_dtb, "imx6ul-geam-kit"))
-		env_set("fdt_file", "imx6ul-geam-kit.dtb");
+	} else if (!strcmp(cmp_dtb, "imx6ul-geam"))
+		env_set("fdt_file", "imx6ul-geam.dtb");
 	else if (!strcmp(cmp_dtb, "imx6ul-isiot-mmc"))
 		env_set("fdt_file", "imx6ul-isiot-emmc.dtb");
 	else if (!strcmp(cmp_dtb, "imx6ul-isiot-emmc"))

board/engicam/common/spl.c

@@ -43,10 +43,14 @@ int board_fit_config_name_match(const char *name)
                 return 0;
         else if (is_mx6dq() && !strcmp(name, "imx6q-icore-rqs"))
                 return 0;
+        else if (is_mx6dq() && !strcmp(name, "imx6q-icore-mipi"))
+                return 0;
         else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore"))
                 return 0;
         else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore-rqs"))
                 return 0;
+        else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore-mipi"))
+                return 0;
         else
                 return -1;
 }

board/ge/bx50v3/MAINTAINERS

@@ -3,6 +3,7 @@ M:	Martin Donnelly <martin.donnelly@ge.com>
 S:	Maintained
 F:	board/ge/bx50v3/
 F:	include/configs/ge_bx50v3.h
+F:	configs/ge_bx50v3_defconfig
 F:	configs/ge_b450v3_defconfig
 F:	configs/ge_b650v3_defconfig
 F:	configs/ge_b850v3_defconfig

board/k+p/bootscripts/tpcboot.cmd

@@ -23,6 +23,10 @@ setenv mmcroot "/dev/mmcblk${devnum}p2 rootwait rw"
 setenv displayargs ""
 setenv mmcargs "setenv bootargs console=${console} ${smp} root=${mmcroot} \
 	${displayargs}"
+setenv miscadj "
+if test '${boardsoc}' = 'imx53'; then
+       setenv bootargs '${bootargs} di=${dig_in} key1=${key1}';
+fi;"
 setenv boot_fitImage "
 	setenv fdt_conf 'conf@${boardsoc}-${boardname}.dtb';
 	setenv itbcfg "\"#\${fdt_conf}\"";
@@ -39,6 +43,7 @@ if test -e ${devtype} ${devnum}:${distro_bootpart} ${kernel_file}; then
 	if load ${devtype} ${devnum}:${distro_bootpart} ${loadaddr} \
 	   ${kernel_file}; then
 		run mmcargs;
+		run miscadj;
 		run boot_fitImage;
 	fi;
 fi;"
@@ -52,6 +57,7 @@ setenv download_kernel "tftpboot ${loadaddr} ${kernel_file}"
 setenv boot_tftp_kernel "
 if run download_kernel; then
 	run mmcargs;
+	run miscadj;
 	run boot_fitImage;
 fi"
 

board/k+p/kp_imx53/kp_imx53.c

@@ -22,6 +22,8 @@
 #define VBUS_PWR_EN IMX_GPIO_NR(7, 8)
 #define PHY_nRST IMX_GPIO_NR(7, 6)
 #define BOOSTER_OFF IMX_GPIO_NR(2, 23)
+#define LCD_BACKLIGHT IMX_GPIO_NR(1, 1)
+#define KEY1 IMX_GPIO_NR(2, 26)
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -43,18 +45,6 @@ int dram_init_banksize(void)
 	return 0;
 }
 
-u32 get_board_rev(void)
-{
-	struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
-	struct fuse_bank *bank = &iim->bank[0];
-	struct fuse_bank0_regs *fuse =
-		(struct fuse_bank0_regs *)bank->fuse_regs;
-
-	int rev = readl(&fuse->gp[6]);
-
-	return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
-}
-
 #ifdef CONFIG_USB_EHCI_MX5
 int board_ehci_hcd_init(int port)
 {
@@ -189,10 +179,28 @@ void eth_phy_reset(void)
 	udelay(50);
 }
 
+void board_disable_display(void)
+{
+	gpio_request(LCD_BACKLIGHT, "LCD_BACKLIGHT");
+	gpio_direction_output(LCD_BACKLIGHT, 0);
+}
+
+void board_misc_setup(void)
+{
+	gpio_request(KEY1, "KEY1_GPIO");
+	gpio_direction_input(KEY1);
+
+	if (gpio_get_value(KEY1))
+		env_set("key1", "off");
+	else
+		env_set("key1", "on");
+}
+
 int board_late_init(void)
 {
 	int ret = 0;
 
+	board_disable_display();
 	setup_ups();
 
 	if (!power_init())
@@ -207,5 +215,7 @@ int board_late_init(void)
 	show_eeprom();
 	read_board_id();
 
+	board_misc_setup();
+
 	return ret;
 }

board/liebherr/display5/common.c

@@ -34,6 +34,16 @@ void displ5_set_iomux_uart(void)
 	SETUP_IOMUX_PADS(uart_pads);
 }
 
+iomux_v3_cfg_t const misc_pads_spl[] = {
+	/* Emergency recovery pin */
+	MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+void displ5_set_iomux_misc_spl(void)
+{
+	SETUP_IOMUX_PADS(misc_pads_spl);
+}
+
 #ifdef CONFIG_MXC_SPI
 iomux_v3_cfg_t const ecspi_pads[] = {
 	/* SPI3 */

board/liebherr/display5/common.h

@@ -37,5 +37,6 @@ void displ5_set_iomux_ecspi_spl(void);
 void displ5_set_iomux_ecspi(void);
 void displ5_set_iomux_usdhc_spl(void);
 void displ5_set_iomux_usdhc(void);
+void displ5_set_iomux_misc_spl(void);
 
 #endif /* __DISPL5_COMMON_H_ */

board/liebherr/display5/display5.c

@@ -25,6 +25,7 @@
 #include <miiphy.h>
 #include <netdev.h>
 #include <i2c.h>
+#include <environment.h>
 
 #include <dm.h>
 #include <dm/platform_data/serial_mxc.h>
@@ -44,6 +45,7 @@ static bool sw_ids_valid;
 static u32 cpu_id;
 static u32 unit_id;
 
+#define EM_PAD IMX_GPIO_NR(3, 29)
 #define SW0	IMX_GPIO_NR(2, 4)
 #define SW1	IMX_GPIO_NR(2, 5)
 #define SW2	IMX_GPIO_NR(2, 6)
@@ -179,6 +181,9 @@ iomux_v3_cfg_t const misc_pads[] = {
 
 	/* XTALOSC */
 	MX6_PAD_GPIO_3__XTALOSC_REF_CLK_24M | MUX_PAD_CTRL(NO_PAD_CTRL),
+
+	/* Emergency recovery pin */
+	MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 
 #ifdef CONFIG_FSL_ESDHC
@@ -250,6 +255,25 @@ static void setup_iomux_enet(void)
 	gpio_direction_input(IMX_GPIO_NR(1, 28)); /*INT#_GBE*/
 }
 
+static int setup_mac_from_fuse(void)
+{
+	unsigned char enetaddr[6];
+	int ret;
+
+	ret = eth_env_get_enetaddr("ethaddr", enetaddr);
+	if (ret)	/* ethaddr is already set */
+		return 0;
+
+	imx_get_mac_from_fuse(0, enetaddr);
+
+	if (is_valid_ethaddr(enetaddr)) {
+		eth_env_set_enetaddr("ethaddr", enetaddr);
+		return 0;
+	}
+
+	return 0;
+}
+
 int board_eth_init(bd_t *bd)
 {
 	struct phy_device *phydev;
@@ -264,6 +288,8 @@ int board_eth_init(bd_t *bd)
 	if (ret)
 		return ret;
 
+	setup_mac_from_fuse();
+
 	bus = fec_get_miibus(IMX_FEC_BASE, -1);
 	if (!bus)
 		return -ENODEV;
@@ -369,7 +395,22 @@ static inline void setup_boot_modes(void) {}
 
 int misc_init_r(void)
 {
+	int ret;
+
 	setup_boot_modes();
+
+	ret = gpio_request(EM_PAD, "Emergency_PAD");
+	if (ret) {
+		printf("Can't request emergency PAD gpio\n");
+		return ret;
+	}
+
+	ret = gpio_direction_input(EM_PAD);
+	if (ret) {
+		printf("Can't set emergency PAD direction\n");
+		return ret;
+	}
+
 	return 0;
 }
 

board/liebherr/display5/spl.c

@@ -16,10 +16,12 @@
 #include <asm/arch/imx-regs.h>
 #include "asm/arch/iomux.h"
 #include <asm/mach-imx/iomux-v3.h>
+#include <asm/gpio.h>
 #include <environment.h>
 #include <fsl_esdhc.h>
 #include <netdev.h>
 #include <bootcount.h>
+#include <watchdog.h>
 #include "common.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -115,6 +117,49 @@ static void ccgr_init(void)
 	writel(0x000003FF, &ccm->CCGR6);
 }
 
+#ifdef CONFIG_MX6_DDRCAL
+static void spl_dram_print_cal(struct mx6_ddr_sysinfo const *sysinfo)
+{
+	struct mx6_mmdc_calibration calibration = {0};
+
+	mmdc_read_calibration(sysinfo, &calibration);
+
+	debug(".p0_mpdgctrl0\t= 0x%08X\n", calibration.p0_mpdgctrl0);
+	debug(".p0_mpdgctrl1\t= 0x%08X\n", calibration.p0_mpdgctrl1);
+	debug(".p0_mprddlctl\t= 0x%08X\n", calibration.p0_mprddlctl);
+	debug(".p0_mpwrdlctl\t= 0x%08X\n", calibration.p0_mpwrdlctl);
+	debug(".p0_mpwldectrl0\t= 0x%08X\n", calibration.p0_mpwldectrl0);
+	debug(".p0_mpwldectrl1\t= 0x%08X\n", calibration.p0_mpwldectrl1);
+	debug(".p1_mpdgctrl0\t= 0x%08X\n", calibration.p1_mpdgctrl0);
+	debug(".p1_mpdgctrl1\t= 0x%08X\n", calibration.p1_mpdgctrl1);
+	debug(".p1_mprddlctl\t= 0x%08X\n", calibration.p1_mprddlctl);
+	debug(".p1_mpwrdlctl\t= 0x%08X\n", calibration.p1_mpwrdlctl);
+	debug(".p1_mpwldectrl0\t= 0x%08X\n", calibration.p1_mpwldectrl0);
+	debug(".p1_mpwldectrl1\t= 0x%08X\n", calibration.p1_mpwldectrl1);
+}
+
+static void spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo)
+{
+	int ret;
+
+	/* Perform DDR DRAM calibration */
+	udelay(100);
+	ret = mmdc_do_write_level_calibration(sysinfo);
+	if (ret) {
+		printf("DDR: Write level calibration error [%d]\n", ret);
+		return;
+	}
+
+	ret = mmdc_do_dqs_calibration(sysinfo);
+	if (ret) {
+		printf("DDR: DQS calibration error [%d]\n", ret);
+		return;
+	}
+
+	spl_dram_print_cal(sysinfo);
+}
+#endif /* CONFIG_MX6_DDRCAL */
+
 static void spl_dram_init(void)
 {
 	struct mx6_ddr_sysinfo sysinfo = {
@@ -141,6 +186,10 @@ static void spl_dram_init(void)
 
 	mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
 	mx6_dram_cfg(&sysinfo, &mx6_4x256mx16_mmdc_calib, &mt41k128m16jt_125);
+
+#ifdef CONFIG_MX6_DDRCAL
+	spl_dram_perform_cal(&sysinfo);
+#endif
 }
 
 #ifdef CONFIG_SPL_SPI_SUPPORT
@@ -194,10 +243,28 @@ void board_init_f(ulong dummy)
 	/* Clear the BSS. */
 	memset(__bss_start, 0, __bss_end - __bss_start);
 
+	displ5_set_iomux_misc_spl();
+
+	/* Initialize and reset WDT in SPL */
+	hw_watchdog_init();
+	WATCHDOG_RESET();
+
 	/* load/boot image from boot device */
 	board_init_r(NULL, 0);
 }
 
+#define EM_PAD IMX_GPIO_NR(3, 29)
+int board_check_emergency_pad(void)
+{
+	int ret;
+
+	ret = gpio_direction_input(EM_PAD);
+	if (ret)
+		return ret;
+
+	return !gpio_get_value(EM_PAD);
+}
+
 void board_boot_order(u32 *spl_boot_list)
 {
 	/* Default boot sequence SPI -> MMC */
@@ -206,12 +273,19 @@ void board_boot_order(u32 *spl_boot_list)
 	spl_boot_list[2] = BOOT_DEVICE_UART;
 	spl_boot_list[3] = BOOT_DEVICE_NONE;
 
+	/*
+	 * In case of emergency PAD pressed, we always boot
+	 * to proper u-boot and perform recovery tasks there.
+	 */
+	if (board_check_emergency_pad())
+		return;
+
 #ifdef CONFIG_SPL_ENV_SUPPORT
 	/* 'fastboot' */
 	const char *s;
 
-	env_init();
-	env_load();
+	if (env_init() || env_load())
+		return;
 
 	s = env_get("BOOT_FROM");
 	if (s && !bootcount_error() && strcmp(s, "ACTIVE") == 0) {

board/solidrun/mx6cuboxi/mx6cuboxi.c

@@ -57,9 +57,58 @@ DECLARE_GLOBAL_DATA_PTR;
 #define ETH_PHY_RESET	IMX_GPIO_NR(4, 15)
 #define USB_H1_VBUS	IMX_GPIO_NR(1, 0)
 
+enum board_type {
+	CUBOXI          = 0x00,
+	HUMMINGBOARD    = 0x01,
+	HUMMINGBOARD2   = 0x02,
+	UNKNOWN         = 0x03,
+};
+
+#define MEM_STRIDE 0x4000000
+static u32 get_ram_size_stride_test(u32 *base, u32 maxsize)
+{
+        volatile u32 *addr;
+        u32          save[64];
+        u32          cnt;
+        u32          size;
+        int          i = 0;
+
+        /* First save the data */
+        for (cnt = 0; cnt < maxsize; cnt += MEM_STRIDE) {
+                addr = (volatile u32 *)((u32)base + cnt);       /* pointer arith! */
+                sync ();
+                save[i++] = *addr;
+                sync ();
+        }
+
+        /* First write a signature */
+        * (volatile u32 *)base = 0x12345678;
+        for (size = MEM_STRIDE; size < maxsize; size += MEM_STRIDE) {
+                * (volatile u32 *)((u32)base + size) = size;
+                sync ();
+                if (* (volatile u32 *)((u32)base) == size) {	/* We reached the overlapping address */
+                        break;
+                }
+        }
+
+        /* Restore the data */
+        for (cnt = (maxsize - MEM_STRIDE); i > 0; cnt -= MEM_STRIDE) {
+                addr = (volatile u32 *)((u32)base + cnt);       /* pointer arith! */
+                sync ();
+                *addr = save[i--];
+                sync ();
+        }
+
+        return (size);
+}
+
 int dram_init(void)
 {
-	gd->ram_size = imx_ddr_size();
+	u32 max_size = imx_ddr_size();
+
+	gd->ram_size = get_ram_size_stride_test((u32 *) CONFIG_SYS_SDRAM_BASE,
+						(u32)max_size);
+
 	return 0;
 }
 
@@ -77,10 +126,17 @@ static iomux_v3_cfg_t const usdhc2_pads[] = {
 	IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 };
 
-static iomux_v3_cfg_t const hb_cbi_sense[] = {
+static iomux_v3_cfg_t const board_detect[] = {
 	/* These pins are for sensing if it is a CuBox-i or a HummingBoard */
 	IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09  | MUX_PAD_CTRL(UART_PAD_CTRL)),
 	IOMUX_PADS(PAD_EIM_DA4__GPIO3_IO04   | MUX_PAD_CTRL(UART_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08  | MUX_PAD_CTRL(UART_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const som_rev_detect[] = {
+	/* These pins are for sensing if it is a CuBox-i or a HummingBoard */
+	IOMUX_PADS(PAD_CSI0_DAT14__GPIO6_IO00  | MUX_PAD_CTRL(UART_PAD_CTRL)),
+	IOMUX_PADS(PAD_CSI0_DAT18__GPIO6_IO04  | MUX_PAD_CTRL(UART_PAD_CTRL)),
 };
 
 static iomux_v3_cfg_t const usb_pads[] = {
@@ -333,88 +389,110 @@ int board_init(void)
 	return ret;
 }
 
-static bool is_hummingboard(void)
+static enum board_type board_type(void)
 {
-	int val1, val2;
+	int val1, val2, val3;
 
-	SETUP_IOMUX_PADS(hb_cbi_sense);
-
-	gpio_direction_input(IMX_GPIO_NR(4, 9));
-	gpio_direction_input(IMX_GPIO_NR(3, 4));
-
-	val1 = gpio_get_value(IMX_GPIO_NR(4, 9));
-	val2 = gpio_get_value(IMX_GPIO_NR(3, 4));
+	SETUP_IOMUX_PADS(board_detect);
 
 	/*
 	 * Machine selection -
-	 * Machine        val1, val2
-	 * -------------------------
-	 * HB2            x     x
-	 * HB rev 3.x     x     0
-	 * CBi            0     1
-	 * HB             1     1
+	 * Machine      val1, val2, val3
+	 * ----------------------------
+	 * HB2            x     x    0
+	 * HB rev 3.x     x     0    x
+	 * CBi            0     1    x
+	 * HB             1     1    x
 	 */
 
-	if (val2 == 0)
-		return true;
-	else if (val1 == 0)
-		return false;
-	else
-		return true;
-}
-
-static bool is_hummingboard2(void)
-{
-	int val1;
-
-	SETUP_IOMUX_PADS(hb_cbi_sense);
-
 	gpio_direction_input(IMX_GPIO_NR(2, 8));
+	val3 = gpio_get_value(IMX_GPIO_NR(2, 8));
 
-        val1 = gpio_get_value(IMX_GPIO_NR(2, 8));
+	if (val3 == 0)
+		return HUMMINGBOARD2;
 
-	/*
-	 * Machine selection -
-	 * Machine        val1
-	 * -------------------
-	 * HB2            0
-	 * HB rev 3.x     x
-	 * CBi            x
-	 * HB             x
-	 */
+	gpio_direction_input(IMX_GPIO_NR(3, 4));
+	val2 = gpio_get_value(IMX_GPIO_NR(3, 4));
 
-	if (val1 == 0)
+	if (val2 == 0)
+		return HUMMINGBOARD;
+
+	gpio_direction_input(IMX_GPIO_NR(4, 9));
+	val1 = gpio_get_value(IMX_GPIO_NR(4, 9));
+
+	if (val1 == 0) {
+		return CUBOXI;
+	} else {
+		return HUMMINGBOARD;
+	}
+}
+
+static bool is_rev_15_som(void)
+{
+	int val1, val2;
+	SETUP_IOMUX_PADS(som_rev_detect);
+
+	val1 = gpio_get_value(IMX_GPIO_NR(6, 0));
+	val2 = gpio_get_value(IMX_GPIO_NR(6, 4));
+
+	if (val1 == 1 && val2 == 0)
 		return true;
-	else
-		return false;
+
+	return false;
 }
 
 int checkboard(void)
 {
-	if (is_hummingboard2())
-		puts("Board: MX6 Hummingboard2\n");
-	else if (is_hummingboard())
-		puts("Board: MX6 Hummingboard\n");
-	else
-		puts("Board: MX6 Cubox-i\n");
+	switch (board_type()) {
+	case CUBOXI:
+		puts("Board: MX6 Cubox-i");
+		break;
+	case HUMMINGBOARD:
+		puts("Board: MX6 HummingBoard");
+		break;
+	case HUMMINGBOARD2:
+		puts("Board: MX6 HummingBoard2");
+		break;
+	case UNKNOWN:
+	default:
+		puts("Board: Unknown\n");
+		goto out;
+	}
 
+	if (is_rev_15_som())
+		puts(" (som rev 1.5)\n");
+	else
+		puts("\n");
+
+out:
 	return 0;
 }
 
 int board_late_init(void)
 {
 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-	if (is_hummingboard2())
-		env_set("board_name", "HUMMINGBOARD2");
-	else if (is_hummingboard())
-		env_set("board_name", "HUMMINGBOARD");
-	else
+	switch (board_type()) {
+	case CUBOXI:
 		env_set("board_name", "CUBOXI");
+		break;
+	case HUMMINGBOARD:
+		env_set("board_name", "HUMMINGBOARD");
+		break;
+	case HUMMINGBOARD2:
+		env_set("board_name", "HUMMINGBOARD2");
+		break;
+	case UNKNOWN:
+	default:
+		env_set("board_name", "CUBOXI");
+	}
 
 	if (is_mx6dq())
 		env_set("board_rev", "MX6Q");
 	else
 		env_set("board_rev", "MX6DL");
+
+	if (is_rev_15_som())
+		env_set("som_rev", "V15");
 #endif
 
 	return 0;
@@ -590,7 +668,7 @@ static struct mx6_ddr3_cfg mem_ddr_4g = {
 	.density = 4,
 	.width = 16,
 	.banks = 8,
-	.rowaddr = 15,
+	.rowaddr = 16,
 	.coladdr = 10,
 	.pagesz = 2,
 	.trcd = 1375,

board/sunxi/MAINTAINERS

@@ -340,6 +340,11 @@ M:	Icenowy Zheng <icenowy@aosc.xyz>
 S:	Maintained
 F:	configs/orangepi_zero_defconfig
 
+ORANGEPI ZERO PLUS BOARD
+M:	Hauke Mehrtens <hauke@hauke-m.de>
+S:	Maintained
+F:	configs/orangepi_zero_plus_defconfig
+
 ORANGEPI ZERO PLUS 2 BOARD
 M:	Jagan Teki <jagan@amarulasolutions.com>
 S:	Maintained
@@ -355,6 +360,11 @@ M:	Jagan Teki <jagan@amarulasolutions.com>
 S:	Maintained
 F:	configs/orangepi_prime_defconfig
 
+ORANGEPI R1 BOARD
+M:	Hauke Mehrtens <hauke@hauke-m.de>
+S:	Maintained
+F:	configs/orangepi_r1_defconfig
+
 PINE64 BOARDS
 M:	Andre Przywara <andre.przywara@arm.com>
 S:	Maintained

board/synopsys/emdk/README

@@ -0,0 +1,82 @@
+================================================================================
+Useful notes on bulding and using of U-Boot on ARC EM Development Kit (AKA EMDK)
+================================================================================
+
+   BOARD OVERVIEW
+
+   The DesignWare ARC EM Development Kit is FPGA-bases platform for rapid
+   software development on the ARC EM family of processors.
+
+   Since this board is based on FPGA it's possible to load and use different
+   versions of ARC EM CPUs. U-Boot is built to be run on the simplest
+   possible configuration which means the same one binary will work on more
+   advanced configurations as well.
+
+   The board has the following features useful for U-Boot:
+    * On-board 2-channel FTDI TTL-to-USB converter
+      - The first channel is used for serial debug port (which makes it possible
+        to use a serial connection on pretty much any host machine be it
+        Windows, Linux or Mac).
+        On Linux machine typucally FTDI serial port would be /dev/ttyUSB0.
+        There's no HW flow-control and baud-rate is 115200.
+
+      - The second channel is used for built-in Digilent USB JTAG probe.
+        That means no extra hardware is required to access ARC core from a
+        debugger on development host. Both proprietary MetaWare debugger and
+        open source OpenOCD + GDB client are supported.
+
+      - Also with help of this FTDI chip it is possible to reset entire
+        board with help of a special `rff-ftdi-reset` utility, see:
+        https://github.com/foss-for-synopsys-dwc-arc-processors/rff-ftdi-reset
+
+    * Micro SD-card slot
+      - U-Boot expects to see the very first partition on the card formatted as
+        FAT file-system and uses it for keeping its environment in `uboot.env`
+        file. Note uboot.env is not just a text file but it is auto-generated
+        file created by U-Boot on invocation of `saveenv` command.
+        It contains a checksum which makes this saved environment invalid in
+        case of maual modification.
+
+      - There might be more useful files on that first FAT partition like
+        user applications, data files etc.
+
+    * 256 KiB of "ROM"
+      - This so-called "ROM" is a part of FPGA image and even though it
+        might be unlocked for writes its initial content will be restored
+        on the next power-on.
+
+
+   BUILDING U-BOOT
+
+   1. Configure U-Boot:
+      ------------------------->8----------------------
+      make emdk_defconfig
+      ------------------------->8----------------------
+
+   2. To build Elf file (for example to be used with host debugger via JTAG
+      connection to the target board):
+      ------------------------->8----------------------
+      make mdbtrick
+      ------------------------->8----------------------
+
+      This will produce `u-boot` Elf file.
+
+   3. To build binary image to be put in "ROM":
+      ------------------------->8----------------------
+      make u-boot.bin
+      ------------------------->8----------------------
+
+
+   EXECUTING U-BOOT
+
+   1. The EMDK board is supposed to auto-start U-Boot image stored in ROM on
+      power-on. For that make sure VCCIO DIP-switches are all in "off" state.
+
+   2. Though it is possible to load U-Boot as a simple Elf file via JTAG right
+      in "ROM" and start it from the debugger. One important note here we first
+      need to enable writes into "ROM" by writing 1 to 0xf0001000.
+
+      2.1. In case of proprietary MetaWare debugger run:
+      ------------------------->8----------------------
+      mdb -dll=opxdarc.so -OK -preloadexec="eval *(int*)0xf0001000=0" u-boot
+      ------------------------->8----------------------

cmd/Kconfig

@@ -1121,6 +1121,16 @@ config BOOTP_HOSTNAME
 	help
 	  The name may or may not be qualified with the local domain name.
 
+config BOOTP_PREFER_SERVERIP
+	bool "serverip variable takes precedent over DHCP server IP."
+	depends on CMD_BOOTP
+	help
+	  By default a BOOTP/DHCP reply will overwrite the 'serverip' variable.
+
+	  With this option enabled, the 'serverip' variable in the environment
+	  takes precedence over DHCP server IP and will only be set by the DHCP
+	  server if not already set in the environment.
+
 config BOOTP_SUBNETMASK
 	bool "Request & store 'netmask' from BOOTP/DHCP server"
 	default y
@@ -1239,6 +1249,11 @@ config CMD_PXE
 	help
 	  Boot image via network using PXE protocol
 
+config CMD_WOL
+	bool "wol"
+	help
+	  Wait for wake-on-lan Magic Packet
+
 endif
 
 menu "Misc commands"

cmd/Makefile

@@ -100,6 +100,7 @@ obj-$(CONFIG_CMD_PCI) += pci.o
 endif
 obj-y += pcmcia.o
 obj-$(CONFIG_CMD_PXE) += pxe.o
+obj-$(CONFIG_CMD_WOL) += wol.o
 obj-$(CONFIG_CMD_QFW) += qfw.o
 obj-$(CONFIG_CMD_READ) += read.o
 obj-$(CONFIG_CMD_REGINFO) += reginfo.o

cmd/bootefi.c

@@ -61,6 +61,11 @@ efi_status_t efi_init_obj_list(void)
 	if (ret != EFI_SUCCESS)
 		goto out;
 #endif
+#ifdef CONFIG_GENERATE_ACPI_TABLE
+	ret = efi_acpi_register();
+	if (ret != EFI_SUCCESS)
+		goto out;
+#endif
 #ifdef CONFIG_GENERATE_SMBIOS_TABLE
 	ret = efi_smbios_register();
 	if (ret != EFI_SUCCESS)

cmd/efi.c

@@ -83,7 +83,7 @@ void *efi_build_mem_table(struct efi_entry_memmap *map, int size, bool skip_bs)
 	prev = NULL;
 	addr = 0;
 	dest = base;
-	end = base + count;
+	end = (struct efi_mem_desc *)((ulong)base + count * map->desc_size);
 	for (desc = base; desc < end; desc = efi_get_next_mem_desc(map, desc)) {
 		bool merge = true;
 		int type = desc->type;

cmd/net.c

@@ -183,6 +183,8 @@ static int netboot_common(enum proto_t proto, cmd_tbl_t *cmdtp, int argc,
 	int   size;
 	ulong addr;
 
+	net_boot_file_name_explicit = false;
+
 	/* pre-set load_addr */
 	s = env_get("loadaddr");
 	if (s != NULL)
@@ -199,15 +201,18 @@ static int netboot_common(enum proto_t proto, cmd_tbl_t *cmdtp, int argc,
 		 * mis-interpreted as a valid number.
 		 */
 		addr = simple_strtoul(argv[1], &end, 16);
-		if (end == (argv[1] + strlen(argv[1])))
+		if (end == (argv[1] + strlen(argv[1]))) {
 			load_addr = addr;
-		else
+		} else {
+			net_boot_file_name_explicit = true;
 			copy_filename(net_boot_file_name, argv[1],
 				      sizeof(net_boot_file_name));
+		}
 		break;
 
 	case 3:
 		load_addr = simple_strtoul(argv[1], NULL, 16);
+		net_boot_file_name_explicit = true;
 		copy_filename(net_boot_file_name, argv[2],
 			      sizeof(net_boot_file_name));
 
@@ -220,6 +225,7 @@ static int netboot_common(enum proto_t proto, cmd_tbl_t *cmdtp, int argc,
 			printf("Invalid address/size\n");
 			return CMD_RET_USAGE;
 		}
+		net_boot_file_name_explicit = true;
 		copy_filename(net_boot_file_name, argv[3],
 			      sizeof(net_boot_file_name));
 		break;

cmd/wol.c

@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018
+ * Lothar Felte, lothar.felten@gmail.com
+ */
+
+/*
+ * Wake-on-LAN support
+ */
+#include <common.h>
+#include <command.h>
+#include <net.h>
+
+#if defined(CONFIG_CMD_WOL)
+void wol_set_timeout(ulong);
+
+int do_wol(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	/* Validate arguments */
+	if (argc < 2)
+		return CMD_RET_USAGE;
+	wol_set_timeout(simple_strtol(argv[1], NULL, 10) * 1000);
+	if (net_loop(WOL) < 0)
+		return CMD_RET_FAILURE;
+	return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(
+	wol,	2,	1,	do_wol,
+	"wait for an incoming wake-on-lan packet",
+	"Timeout"
+);
+#endif

common/board_r.c

@@ -596,7 +596,7 @@ static int initr_pcmcia(void)
 }
 #endif
 
-#if defined(CONFIG_IDE)
+#if defined(CONFIG_IDE) && !defined(CONFIG_BLK)
 static int initr_ide(void)
 {
 	puts("IDE:   ");
@@ -826,7 +826,7 @@ static init_fnc_t init_sequence_r[] = {
 #if defined(CONFIG_CMD_PCMCIA) && !defined(CONFIG_IDE)
 	initr_pcmcia,
 #endif
-#if defined(CONFIG_IDE)
+#if defined(CONFIG_IDE) && !defined(CONFIG_BLK)
 	initr_ide,
 #endif
 #ifdef CONFIG_LAST_STAGE_INIT

common/spl/Kconfig

@@ -152,7 +152,8 @@ config SPL_DISPLAY_PRINT
 
 config SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
 	bool "MMC raw mode: by sector"
-	default y if ARCH_SUNXI || ARCH_DAVINCI || ARCH_UNIPHIER ||ARCH_MX6 || \
+	default y if ARCH_SUNXI || ARCH_DAVINCI || ARCH_UNIPHIER || \
+		     ARCH_MX6 || ARCH_MX7 || \
 		     ARCH_ROCKCHIP || ARCH_MVEBU ||  ARCH_SOCFPGA || \
 		     ARCH_AT91 || ARCH_ZYNQ || ARCH_KEYSTONE || OMAP34XX || \
 		     OMAP44XX || OMAP54XX || AM33XX || AM43XX
@@ -165,7 +166,7 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
 	depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
 	default 0x50 if ARCH_SUNXI
 	default 0x75 if ARCH_DAVINCI
-	default 0x8a if ARCH_MX6
+	default 0x8a if ARCH_MX6 || ARCH_MX7
 	default 0x100 if ARCH_UNIPHIER
 	default 0x140 if ARCH_MVEBU
 	default 0x200 if ARCH_SOCFPGA || ARCH_AT91