Prepare v2020.04

Signed-off-by: Tom Rini <trini@konsulko.com>

Kconfig

@@ -299,6 +299,11 @@ config ERR_PTR_OFFSET
 	  pointer values - up to 'MAX_ERRNO' bytes below this value must be
 	  unused/invalid addresses.
 
+config PLATFORM_ELFENTRY
+	string
+	default "__start" if MIPS
+	default "_start"
+
 endmenu		# General setup
 
 menu "Boot images"

Makefile

@@ -3,7 +3,7 @@
 VERSION = 2020
 PATCHLEVEL = 04
 SUBLEVEL =
-EXTRAVERSION = -rc4
+EXTRAVERSION =
 NAME =
 
 # *DOCUMENTATION*
@@ -1647,18 +1647,17 @@ OBJCOPYFLAGS_u-boot-img-spl-at-end.bin := -I binary -O binary \
 u-boot-img-spl-at-end.bin: u-boot.img spl/u-boot-spl.bin FORCE
 	$(call if_changed,pad_cat)
 
-# Create a new ELF from a raw binary file.
-ifndef PLATFORM_ELFENTRY
-  PLATFORM_ELFENTRY = "_start"
-endif
 quiet_cmd_u-boot-elf ?= LD      $@
 	cmd_u-boot-elf ?= $(LD) u-boot-elf.o -o $@ \
-	--defsym=$(PLATFORM_ELFENTRY)=$(CONFIG_SYS_TEXT_BASE) \
+	-T u-boot-elf.lds --defsym=$(CONFIG_PLATFORM_ELFENTRY)=$(CONFIG_SYS_TEXT_BASE) \
 	-Ttext=$(CONFIG_SYS_TEXT_BASE)
-u-boot.elf: u-boot.bin
+u-boot.elf: u-boot.bin u-boot-elf.lds
 	$(Q)$(OBJCOPY) -I binary $(PLATFORM_ELFFLAGS) $< u-boot-elf.o
 	$(call if_changed,u-boot-elf)
 
+u-boot-elf.lds: arch/u-boot-elf.lds prepare FORCE
+	$(call if_changed_dep,cpp_lds)
+
 # MediaTek's ARM-based u-boot needs a header to contains its load address
 # which is parsed by the BootROM.
 # If the SPL build is enabled, the header will be added to the spl binary,

arch/arc/include/asm/io.h

@@ -9,6 +9,12 @@
 #include <linux/types.h>
 #include <asm/byteorder.h>
 
+/*
+ * Compiler barrier. It prevents compiler from reordering instructions before
+ * and after it. It doesn't prevent HW (CPU) from any reordering though.
+ */
+#define __comp_b()		asm volatile("" : : : "memory")
+
 #ifdef __ARCHS__
 
 /*
@@ -45,8 +51,8 @@
 #define __iormb()		rmb()
 #define __iowmb()		wmb()
 #else
-#define __iormb()		asm volatile("" : : : "memory")
-#define __iowmb()		asm volatile("" : : : "memory")
+#define __iormb()		__comp_b()
+#define __iowmb()		__comp_b()
 #endif
 
 static inline void sync(void)
@@ -54,31 +60,47 @@ static inline void sync(void)
 	/* Not yet implemented */
 }
 
-#define __arch_getb(a)		(*(unsigned char *)(a))
-#define __arch_getw(a)		(*(unsigned short *)(a))
-#define __arch_getl(a)		(*(unsigned int *)(a))
-#define __arch_getq(a)		(*(unsigned long long *)(a))
+/*
+ * We must use 'volatile' in C-version read/write IO accessors implementation
+ * to avoid merging several reads (writes) into one read (write), or optimizing
+ * them out by compiler.
+ * We must use compiler barriers before and after operation (read or write) so
+ * it won't be reordered by compiler.
+ */
+#define __arch_getb(a)		({ u8  __v; __comp_b(); __v = *(volatile u8  *)(a); __comp_b(); __v; })
+#define __arch_getw(a)		({ u16 __v; __comp_b(); __v = *(volatile u16 *)(a); __comp_b(); __v; })
+#define __arch_getl(a)		({ u32 __v; __comp_b(); __v = *(volatile u32 *)(a); __comp_b(); __v; })
+#define __arch_getq(a)		({ u64 __v; __comp_b(); __v = *(volatile u64 *)(a); __comp_b(); __v; })
 
-#define __arch_putb(v, a)	(*(unsigned char *)(a) = (v))
-#define __arch_putw(v, a)	(*(unsigned short *)(a) = (v))
-#define __arch_putl(v, a)	(*(unsigned int *)(a) = (v))
-#define __arch_putq(v, a)	(*(unsigned long long *)(a) = (v))
+#define __arch_putb(v, a)	({ __comp_b(); *(volatile u8  *)(a) = (v); __comp_b(); })
+#define __arch_putw(v, a)	({ __comp_b(); *(volatile u16 *)(a) = (v); __comp_b(); })
+#define __arch_putl(v, a)	({ __comp_b(); *(volatile u32 *)(a) = (v); __comp_b(); })
+#define __arch_putq(v, a)	({ __comp_b(); *(volatile u64 *)(a) = (v); __comp_b(); })
 
-#define __raw_writeb(v, a)	__arch_putb(v, a)
-#define __raw_writew(v, a)	__arch_putw(v, a)
-#define __raw_writel(v, a)	__arch_putl(v, a)
-#define __raw_writeq(v, a)	__arch_putq(v, a)
 
-#define __raw_readb(a)		__arch_getb(a)
-#define __raw_readw(a)		__arch_getw(a)
-#define __raw_readl(a)		__arch_getl(a)
-#define __raw_readq(a)		__arch_getq(a)
+/*
+ * We add memory barriers for __raw_readX / __raw_writeX accessors same way as
+ * it is done for readX and writeX accessors as lots of U-boot driver uses
+ * __raw_readX / __raw_writeX instead of proper accessor with barrier.
+ */
+#define __raw_writeb(v, c)	({ __iowmb(); __arch_putb(v, c); })
+#define __raw_writew(v, c)	({ __iowmb(); __arch_putw(v, c); })
+#define __raw_writel(v, c)	({ __iowmb(); __arch_putl(v, c); })
+#define __raw_writeq(v, c)	({ __iowmb(); __arch_putq(v, c); })
+
+#define __raw_readb(c)		({ u8  __v = __arch_getb(c); __iormb(); __v; })
+#define __raw_readw(c)		({ u16 __v = __arch_getw(c); __iormb(); __v; })
+#define __raw_readl(c)		({ u32 __v = __arch_getl(c); __iormb(); __v; })
+#define __raw_readq(c)		({ u64 __v = __arch_getq(c); __iormb(); __v; })
+
 
 static inline void __raw_writesb(unsigned long addr, const void *data,
 				 int bytelen)
 {
 	u8 *buf = (uint8_t *)data;
 
+	__iowmb();
+
 	while (bytelen--)
 		__arch_putb(*buf++, addr);
 }
@@ -88,6 +110,8 @@ static inline void __raw_writesw(unsigned long addr, const void *data,
 {
 	u16 *buf = (uint16_t *)data;
 
+	__iowmb();
+
 	while (wordlen--)
 		__arch_putw(*buf++, addr);
 }
@@ -97,6 +121,8 @@ static inline void __raw_writesl(unsigned long addr, const void *data,
 {
 	u32 *buf = (uint32_t *)data;
 
+	__iowmb();
+
 	while (longlen--)
 		__arch_putl(*buf++, addr);
 }
@@ -107,6 +133,8 @@ static inline void __raw_readsb(unsigned long addr, void *data, int bytelen)
 
 	while (bytelen--)
 		*buf++ = __arch_getb(addr);
+
+	__iormb();
 }
 
 static inline void __raw_readsw(unsigned long addr, void *data, int wordlen)
@@ -115,6 +143,8 @@ static inline void __raw_readsw(unsigned long addr, void *data, int wordlen)
 
 	while (wordlen--)
 		*buf++ = __arch_getw(addr);
+
+	__iormb();
 }
 
 static inline void __raw_readsl(unsigned long addr, void *data, int longlen)
@@ -123,6 +153,8 @@ static inline void __raw_readsl(unsigned long addr, void *data, int longlen)
 
 	while (longlen--)
 		*buf++ = __arch_getl(addr);
+
+	__iormb();
 }
 
 /*
@@ -130,21 +162,15 @@ static inline void __raw_readsl(unsigned long addr, void *data, int longlen)
  * ordering rules but do not guarantee any ordering relative to Normal memory
  * accesses.
  */
-#define readb_relaxed(c)	({ u8  __r = __raw_readb(c); __r; })
-#define readw_relaxed(c)	({ u16 __r = le16_to_cpu((__force __le16) \
-						__raw_readw(c)); __r; })
-#define readl_relaxed(c)	({ u32 __r = le32_to_cpu((__force __le32) \
-						__raw_readl(c)); __r; })
-#define readq_relaxed(c)	({ u64 __r = le64_to_cpu((__force __le64) \
-						__raw_readq(c)); __r; })
+#define readb_relaxed(c)	({ u8  __r = __arch_getb(c); __r; })
+#define readw_relaxed(c)	({ u16 __r = le16_to_cpu((__force __le16)__arch_getw(c)); __r; })
+#define readl_relaxed(c)	({ u32 __r = le32_to_cpu((__force __le32)__arch_getl(c)); __r; })
+#define readq_relaxed(c)	({ u64 __r = le64_to_cpu((__force __le64)__arch_getq(c)); __r; })
 
-#define writeb_relaxed(v, c)	((void)__raw_writeb((v), (c)))
-#define writew_relaxed(v, c)	((void)__raw_writew((__force u16) \
-						    cpu_to_le16(v), (c)))
-#define writel_relaxed(v, c)	((void)__raw_writel((__force u32) \
-						    cpu_to_le32(v), (c)))
-#define writeq_relaxed(v, c)	((void)__raw_writeq((__force u64) \
-						    cpu_to_le64(v), (c)))
+#define writeb_relaxed(v, c)	((void)__arch_putb((v), (c)))
+#define writew_relaxed(v, c)	((void)__arch_putw((__force u16)cpu_to_le16(v), (c)))
+#define writel_relaxed(v, c)	((void)__arch_putl((__force u32)cpu_to_le32(v), (c)))
+#define writeq_relaxed(v, c)	((void)__arch_putq((__force u64)cpu_to_le64(v), (c)))
 
 /*
  * MMIO can also get buffered/optimized in micro-arch, so barriers needed

arch/arm/cpu/armv8/cpu.c

@@ -32,6 +32,8 @@ void sdelay(unsigned long loops)
 			  "b.ne 1b" : "=r" (loops) : "0"(loops) : "cc");
 }
 
+void __weak board_cleanup_before_linux(void){}
+
 int cleanup_before_linux(void)
 {
 	/*
@@ -40,6 +42,9 @@ int cleanup_before_linux(void)
 	 *
 	 * disable interrupt and turn off caches etc ...
 	 */
+
+	board_cleanup_before_linux();
+
 	disable_interrupts();
 
 	/*

arch/arm/dts/Makefile

@@ -180,7 +180,8 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
 	tegra210-e2220-1170.dtb \
 	tegra210-p2371-0000.dtb \
 	tegra210-p2371-2180.dtb \
-	tegra210-p2571.dtb
+	tegra210-p2571.dtb \
+	tegra210-p3450-0000.dtb
 
 dtb-$(CONFIG_ARCH_MVEBU) +=			\
 	armada-3720-db.dtb			\

arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi

@@ -4,125 +4,133 @@
  */
 
 &mu {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };
 
 &clk {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };
 
 &iomuxc {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };
 
 &pd_lsio {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };
 
 &pd_lsio_gpio0 {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };
 
 &pd_lsio_gpio1 {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };
 
 &pd_lsio_gpio2 {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };
 
 &pd_lsio_gpio3 {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };
 
 &pd_lsio_gpio4 {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };
 
 &pd_lsio_gpio5 {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };
 
 &pd_lsio_gpio6 {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };
 
 &pd_lsio_gpio7 {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
+};
+
+&pd_dma {
+	u-boot,dm-pre-proper;
+};
+
+&pd_dma_lpuart1 {
+	u-boot,dm-pre-proper;
 };
 
 &pd_conn {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };
 
 &pd_conn_sdch0 {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };
 
 &pd_conn_sdch1 {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };
 
 &pd_conn_sdch2 {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };
 
 &gpio0 {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };
 
 &gpio1 {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };
 
 &gpio2 {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };
 
 &gpio3 {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };
 
 &gpio4 {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };
 
 &gpio5 {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };
 
 &gpio6 {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };
 
 &gpio7 {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };
 
 &lpuart0 {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };
 
 &lpuart1 {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };
 
 &lpuart2 {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };
 
 &lpuart3 {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };
 
 &usdhc1 {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };
 
 &usdhc2 {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };
 
 &usdhc3 {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };

arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi

@@ -5,113 +5,125 @@
 
 &{/imx8qx-pm} {
 
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };
 
 &mu {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };
 
 &clk {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };
 
 &iomuxc {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };
 
 &pd_lsio {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };
 
 &pd_lsio_gpio0 {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };
 
 &pd_lsio_gpio1 {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };
 
 &pd_lsio_gpio2 {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };
 
 &pd_lsio_gpio3 {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };
 
 &pd_lsio_gpio4 {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };
 
 &pd_lsio_gpio5 {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };
 
 &pd_lsio_gpio6 {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };
 
 &pd_lsio_gpio7 {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
+};
+
+&pd_dma {
+	u-boot,dm-pre-proper;
+};
+
+&pd_dma_lpuart0 {
+	u-boot,dm-pre-proper;
+};
+
+&pd_dma_lpuart3 {
+	u-boot,dm-pre-proper;
 };
 
 &pd_conn {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };
 
 &pd_conn_sdch0 {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };
 
 &pd_conn_sdch1 {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };
 
 &pd_conn_sdch2 {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };
 
 &gpio0 {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };
 
 &gpio1 {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };
 
 &gpio2 {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };
 
 &gpio3 {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };
 
 &gpio4 {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };
 
 &gpio5 {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };
 
 &gpio6 {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };
 
 &gpio7 {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };
 
 &lpuart3 {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };
 
 &usdhc1 {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };
 
 &usdhc2 {
-	u-boot,dm-spl;
+	u-boot,dm-pre-proper;
 };

arch/arm/dts/r8a7792-blanche-u-boot.dts

@@ -8,6 +8,10 @@
 #include "r8a7792-blanche.dts"
 #include "r8a7792-u-boot.dtsi"
 
+&iic3 {
+	status = "okay";
+};
+
 &scif0 {
 	u-boot,dm-pre-reloc;
 };

arch/arm/dts/r8a7792.dtsi

@@ -444,6 +444,23 @@
 			status = "disabled";
 		};
 
+		iic3: i2c@e60b0000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "renesas,iic-r8a7792",
+				     "renesas,rcar-gen2-iic",
+				     "renesas,rmobile-iic";
+			reg = <0 0xe60b0000 0 0x425>;
+			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 926>;
+			dmas = <&dmac0 0x77>, <&dmac0 0x78>,
+			       <&dmac1 0x77>, <&dmac1 0x78>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+			resets = <&cpg 926>;
+			status = "disabled";
+		};
+
 		dmac0: dma-controller@e6700000 {
 			compatible = "renesas,dmac-r8a7792",
 				     "renesas,rcar-dmac";

arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi

@@ -37,3 +37,6 @@
 	u-boot,dm-pre-reloc;
 };
 
+&qspi {
+	status = "okay";
+};

arch/arm/dts/stm32mp157-pinctrl.dtsi

@@ -288,6 +288,57 @@
 				};
 			};
 
+			ethernet0_rgmii_pins_b: rgmii-1 {
+				pins1 {
+					pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
+						 <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
+						 <STM32_PINMUX('B', 12, AF11)>, /* ETH_RGMII_TXD0 */
+						 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
+						 <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
+						 <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
+						 <STM32_PINMUX('G', 11, AF11)>, /* ETH_RGMII_TX_CTL */
+						 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
+					bias-disable;
+					drive-push-pull;
+					slew-rate = <2>;
+				};
+				pins2 {
+					pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
+					bias-disable;
+					drive-push-pull;
+					slew-rate = <0>;
+				};
+				pins3 {
+					pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
+						 <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
+						 <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */
+						 <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
+						 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
+						 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
+					bias-disable;
+				};
+			};
+
+			ethernet0_rgmii_pins_sleep_b: rgmii-sleep-1 {
+				pins1 {
+					pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
+						 <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
+						 <STM32_PINMUX('B', 12, ANALOG)>, /* ETH_RGMII_TXD0 */
+						 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
+						 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
+						 <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
+						 <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
+						 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
+						 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
+						 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
+						 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
+						 <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */
+						 <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
+						 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
+						 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
+				};
+			};
+
 			fmc_pins_a: fmc-0 {
 				pins1 {
 					pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
@@ -832,6 +883,30 @@
 				};
 			};
 
+			sdmmc1_dir_pins_b: sdmmc1-dir-1 {
+				pins1 {
+					pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
+						 <STM32_PINMUX('E', 14, AF8)>, /* SDMMC1_D123DIR */
+						 <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
+					slew-rate = <1>;
+					drive-push-pull;
+					bias-pull-up;
+				};
+				pins2{
+					pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
+					bias-pull-up;
+				};
+			};
+
+			sdmmc1_dir_sleep_pins_b: sdmmc1-dir-sleep-1 {
+				pins {
+					pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */
+						 <STM32_PINMUX('E', 14, ANALOG)>, /* SDMMC1_D123DIR */
+						 <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
+						 <STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */
+				};
+			};
+
 			sdmmc2_b4_pins_a: sdmmc2-b4-0 {
 				pins1 {
 					pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
@@ -907,6 +982,27 @@
 				};
 			};
 
+			sdmmc2_d47_pins_b: sdmmc2-d47-1 {
+				pins {
+					pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
+						 <STM32_PINMUX('A', 15, AF9)>, /* SDMMC2_D5 */
+						 <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
+						 <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
+					slew-rate = <1>;
+					drive-push-pull;
+					bias-pull-up;
+				};
+			};
+
+			sdmmc2_d47_sleep_pins_b: sdmmc2-d47-sleep-1 {
+				pins {
+					pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
+						 <STM32_PINMUX('A', 15, ANALOG)>, /* SDMMC2_D5 */
+						 <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */
+						 <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */
+				};
+			};
+
 			spdifrx_pins_a: spdifrx-0 {
 				pins {
 					pinmux = <STM32_PINMUX('G', 12, AF8)>; /* SPDIF_IN1 */

arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi

@@ -150,9 +150,12 @@
 	};
 };
 
-&sdmmc1_dir_pins_a {
+&sdmmc1_dir_pins_b {
 	u-boot,dm-spl;
-	pins {
+	pins1 {
+		u-boot,dm-spl;
+	};
+	pins2 {
 		u-boot,dm-spl;
 	};
 };
@@ -171,7 +174,7 @@
 	};
 };
 
-&sdmmc2_d47_pins_a {
+&sdmmc2_d47_pins_b {
 	u-boot,dm-spl;
 	pins {
 		u-boot,dm-spl;

arch/arm/dts/stm32mp157a-avenger96.dts

@@ -16,10 +16,12 @@
 	compatible = "arrow,stm32mp157a-avenger96", "st,stm32mp157";
 
 	aliases {
+		eeprom0 = &eeprom0;
 		ethernet0 = &ethernet0;
 		mmc0 = &sdmmc1;
 		serial0 = &uart4;
 		serial1 = &uart7;
+		spi0 = &qspi;
 	};
 
 	chosen {
@@ -76,16 +78,42 @@
 			default-state = "off";
 		};
 	};
+
+	sd_switch: regulator-sd_switch {
+		compatible = "regulator-gpio";
+		regulator-name = "sd_switch";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <2900000>;
+		regulator-type = "voltage";
+		regulator-always-on;
+
+		gpios = <&gpioi 5 GPIO_ACTIVE_HIGH>;
+		gpios-states = <0>;
+		states = <1800000 0x1>,
+			 <2900000 0x0>;
+	};
+
+	/* Enpirion EP3A8LQI U2 on the DHCOR */
+	vdd_io: regulator-buck-io {
+		compatible = "regulator-fixed";
+		regulator-name = "buck-io";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vdd>;
+	};
 };
 
 &ethernet0 {
 	status = "okay";
-	pinctrl-0 = <&ethernet0_rgmii_pins_a>;
-	pinctrl-1 = <&ethernet0_rgmii_pins_sleep_a>;
+	pinctrl-0 = <&ethernet0_rgmii_pins_b>;
+	pinctrl-1 = <&ethernet0_rgmii_pins_sleep_b>;
 	pinctrl-names = "default", "sleep";
 	phy-mode = "rgmii";
 	max-speed = <1000>;
 	phy-handle = <&phy0>;
+	phy-reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>;
 
 	mdio0 {
 		#address-cells = <1>;
@@ -151,7 +179,7 @@
 
 			vddcore: buck1 {
 				regulator-name = "vddcore";
-				regulator-min-microvolt = <1200000>;
+				regulator-min-microvolt = <800000>;
 				regulator-max-microvolt = <1350000>;
 				regulator-always-on;
 				regulator-initial-mode = <0>;
@@ -169,8 +197,8 @@
 
 			vdd: buck3 {
 				regulator-name = "vdd";
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
+				regulator-min-microvolt = <2900000>;
+				regulator-max-microvolt = <2900000>;
 				regulator-always-on;
 				st,mask_reset;
 				regulator-initial-mode = <0>;
@@ -252,6 +280,7 @@
 				regulator-name = "vbus_otg";
 				interrupts = <IT_OCP_OTG 0>;
 				interrupt-parent = <&pmic>;
+				regulator-active-discharge = <1>;
 			};
 
 			vbus_sw: pwr_sw2 {
@@ -274,6 +303,12 @@
 			status = "disabled";
 		};
 	};
+
+	eeprom0: eeprom@53 {
+		compatible = "atmel,24c02";
+		reg = <0x53>;
+		pagesize = <16>;
+	};
 };
 
 &iwdg2 {
@@ -282,10 +317,29 @@
 };
 
 &pwr_regulators {
-	vdd-supply = <&vdd>;
+	vdd-supply = <&vdd_io>;
 	vdd_3v3_usbfs-supply = <&vdd_usb>;
 };
 
+&qspi {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
+	pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>;
+	reg = <0x58003000 0x1000>, <0x70000000 0x200000>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+
+	flash0: spi-flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-rx-bus-width = <4>;
+		spi-max-frequency = <108000000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+	};
+};
+
 &rng1 {
 	status = "okay";
 };
@@ -296,21 +350,23 @@
 
 &sdmmc1 {
 	pinctrl-names = "default", "opendrain", "sleep";
-	pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
-	pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
-	pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
-	broken-cd;
+	pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>;
+	pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_b>;
+	pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_b>;
+	disable-wp;
 	st,sig-dir;
 	st,neg-edge;
 	st,use-ckin;
+	sd-uhs-sdr104;
 	bus-width = <4>;
 	vmmc-supply = <&vdd_sd>;
+	vqmmc-supply = <&sd_switch>;
 	status = "okay";
 };
 
 &sdmmc2 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
+	pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_b>;
 	non-removable;
 	no-sd;
 	no-sdio;

arch/arm/dts/stm32mp15xx-dhcom.dtsi

@@ -10,6 +10,10 @@
 #include <dt-bindings/mfd/st,stpmic1.h>
 
 / {
+	aliases {
+		eeprom0 = &eeprom0;
+	};
+
 	memory@c0000000 {
 		device_type = "memory";
 		reg = <0xC0000000 0x40000000>;
@@ -187,7 +191,7 @@
 		};
 	};
 
-	eeprom@50 {
+	eeprom0: eeprom@50 {
 		compatible = "atmel,24c02";
 		reg = <0x50>;
 		pagesize = <16>;

arch/arm/dts/tegra210-p2371-2180.dts

@@ -12,6 +12,8 @@
 
 	aliases {
 		i2c0 = "/i2c@7000d000";
+		i2c2 = "/i2c@7000c400";
+		i2c3 = "/i2c@7000c500";
 		mmc0 = "/sdhci@700b0600";
 		mmc1 = "/sdhci@700b0000";
 		usb0 = "/usb@7d000000";
@@ -85,6 +87,16 @@
 		non-removable;
 	};
 
+	i2c@7000c400 {
+		status = "okay";
+		clock-frequency = <400000>;
+	};
+
+	i2c@7000c500 {
+		status = "okay";
+		clock-frequency = <400000>;
+	};
+
 	i2c@7000d000 {
 		status = "okay";
 		clock-frequency = <400000>;

arch/arm/dts/tegra210-p3450-0000.dts

@@ -0,0 +1,147 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  (C) Copyright 2019-2020 NVIDIA Corporation <www.nvidia.com>
+ */
+/dts-v1/;
+
+#include "tegra210.dtsi"
+
+/ {
+	model = "NVIDIA Jetson Nano Developer Kit";
+	compatible = "nvidia,p3450-0000", "nvidia,tegra210";
+
+	chosen {
+		stdout-path = &uarta;
+	};
+
+	aliases {
+		ethernet = "/pcie@1003000/pci@2,0/ethernet@0,0";
+		i2c0 = "/i2c@7000d000";
+		i2c2 = "/i2c@7000c400";
+		i2c3 = "/i2c@7000c500";
+		i2c4 = "/i2c@7000c700";
+		mmc0 = "/sdhci@700b0600";
+		mmc1 = "/sdhci@700b0000";
+		spi0 = "/spi@70410000";
+		usb0 = "/usb@7d000000";
+	};
+
+	memory {
+		reg = <0x0 0x80000000 0x0 0xc0000000>;
+	};
+
+	pcie@1003000 {
+		status = "okay";
+
+		pci@1,0 {
+			status = "okay";
+		};
+
+		pci@2,0 {
+			status = "okay";
+
+			ethernet@0,0 {
+				reg = <0x000000 0 0 0 0>;
+				local-mac-address = [ 00 00 00 00 00 00 ];
+			};
+		};
+	};
+
+	serial@70006000 {
+		status = "okay";
+	};
+
+	padctl@7009f000 {
+		pinctrl-0 = <&padctl_default>;
+		pinctrl-names = "default";
+
+		padctl_default: pinmux {
+			xusb {
+				nvidia,lanes = "otg-1", "otg-2";
+				nvidia,function = "xusb";
+				nvidia,iddq = <0>;
+			};
+
+			usb3 {
+				nvidia,lanes = "pcie-5", "pcie-6";
+				nvidia,function = "usb3";
+				nvidia,iddq = <0>;
+			};
+
+			pcie-x1 {
+				nvidia,lanes = "pcie-0";
+				nvidia,function = "pcie-x1";
+				nvidia,iddq = <0>;
+			};
+
+			pcie-x4 {
+				nvidia,lanes = "pcie-1", "pcie-2",
+					       "pcie-3", "pcie-4";
+				nvidia,function = "pcie-x4";
+				nvidia,iddq = <0>;
+			};
+
+			sata {
+				nvidia,lanes = "sata-0";
+				nvidia,function = "sata";
+				nvidia,iddq = <0>;
+			};
+		};
+	};
+
+	sdhci@700b0000 {
+		status = "okay";
+		cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
+		power-gpios = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
+		bus-width = <4>;
+	};
+
+	sdhci@700b0600 {
+		status = "okay";
+		bus-width = <8>;
+		non-removable;
+	};
+
+	i2c@7000c400 {
+		status = "okay";
+		clock-frequency = <400000>;
+	};
+
+	i2c@7000c500 {
+		status = "okay";
+		clock-frequency = <400000>;
+	};
+
+	i2c@7000c700 {
+		status = "okay";
+		clock-frequency = <400000>;
+	};
+
+	i2c@7000d000 {
+		status = "okay";
+		clock-frequency = <400000>;
+	};
+
+	spi@70410000 {
+		status = "okay";
+		spi-max-frequency = <80000000>;
+	};
+
+	usb@7d000000 {
+		status = "okay";
+		dr_mode = "peripheral";
+	};
+
+	clocks {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		clk32k_in: clock@0 {
+			compatible = "fixed-clock";
+			reg = <0>;
+			#clock-cells = <0>;
+			clock-frequency = <32768>;
+		};
+	};
+};

arch/arm/include/asm/arch-rockchip/vop_rk3288.h

@@ -85,6 +85,16 @@ enum {
 	LB_RGB_1280X8 = 0x5
 };
 
+#if defined(CONFIG_ROCKCHIP_RK3399)
+enum vop_modes {
+	VOP_MODE_EDP = 0,
+	VOP_MODE_MIPI,
+	VOP_MODE_HDMI,
+	VOP_MODE_MIPI1,
+	VOP_MODE_DP,
+	VOP_MODE_NONE,
+};
+#else
 enum vop_modes {
 	VOP_MODE_EDP = 0,
 	VOP_MODE_HDMI,
@@ -94,6 +104,7 @@ enum vop_modes {
 	VOP_MODE_AUTO_DETECT,
 	VOP_MODE_UNKNOWN,
 };
+#endif
 
 /* VOP_VERSION_INFO */
 #define M_FPGA_VERSION (0xffff << 16)

arch/arm/include/asm/arch-tegra/tegra_mmc.h

@@ -2,7 +2,7 @@
 /*
  * (C) Copyright 2009 SAMSUNG Electronics
  * Minkyu Kang <mk7.kang@samsung.com>
- * Portions Copyright (C) 2011-2012 NVIDIA Corporation
+ * Portions Copyright (C) 2011-2012,2019 NVIDIA Corporation
  */
 
 #ifndef __TEGRA_MMC_H_
@@ -52,7 +52,7 @@ struct tegra_mmc {
 	unsigned char	admaerr;	/* offset 54h */
 	unsigned char	res4[3];	/* RESERVED, offset 55h-57h */
 	unsigned long	admaaddr;	/* offset 58h-5Fh */
-	unsigned char	res5[0xa0];	/* RESERVED, offset 60h-FBh */
+	unsigned char	res5[0x9c];	/* RESERVED, offset 60h-FBh */
 	unsigned short	slotintstatus;	/* offset FCh */
 	unsigned short	hcver;		/* HOST Version */
 	unsigned int	venclkctl;	/* _VENDOR_CLOCK_CNTRL_0,    100h */
@@ -127,11 +127,23 @@ struct tegra_mmc {
 
 #define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE			(1 << 1)
 
-/* SDMMC1/3 settings from section 24.6 of T30 TRM */
+/* SDMMC1/3 settings from SDMMCx Initialization Sequence of TRM */
 #define MEMCOMP_PADCTRL_VREF	7
-#define AUTO_CAL_ENABLED	(1 << 29)
+#define AUTO_CAL_ENABLE		(1 << 29)
+#define AUTO_CAL_ACTIVE		(1 << 31)
+#define AUTO_CAL_START		(1 << 31)
+#if defined(CONFIG_TEGRA210)
+#define AUTO_CAL_PD_OFFSET	(0x7D << 8)
+#define AUTO_CAL_PU_OFFSET	(0 << 0)
+#define IO_TRIM_BYPASS_MASK	(1 << 2)
+#define TRIM_VAL_SHIFT		24
+#define TRIM_VAL_MASK		(0x1F << TRIM_VAL_SHIFT)
+#define TAP_VAL_SHIFT		16
+#define TAP_VAL_MASK		(0xFF << TAP_VAL_SHIFT)
+#else
 #define AUTO_CAL_PD_OFFSET	(0x70 << 8)
 #define AUTO_CAL_PU_OFFSET	(0x62 << 0)
+#endif
 
 #endif	/* __ASSEMBLY__ */
 #endif	/* __TEGRA_MMC_H_ */

arch/arm/include/asm/arch-tegra/xusb-padctl.h

@@ -16,6 +16,7 @@ struct tegra_xusb_phy;
 struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type);
 
 void tegra_xusb_padctl_init(void);
+void tegra_xusb_padctl_exit(void);
 int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy);
 int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy);
 int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy);

arch/arm/mach-imx/mkimage_fit_atf.sh

@@ -116,8 +116,8 @@ if [ -f $BL32 ]; then
 cat << __CONF_SECTION_EOF
 		config@$cnt {
 			description = "$(basename $dtname .dtb)";
-			firmware = "atf@1";
-			loadables = "uboot@1", "tee@1";
+			firmware = "uboot@1";
+			loadables = "atf@1", "tee@1";
 			fdt = "fdt@$cnt";
 		};
 __CONF_SECTION_EOF
@@ -125,8 +125,8 @@ else
 cat << __CONF_SECTION1_EOF
 		config@$cnt {
 			description = "$(basename $dtname .dtb)";
-			firmware = "atf@1";
-			loadables = "uboot@1";
+			firmware = "uboot@1";
+			loadables = "atf@1";
 			fdt = "fdt@$cnt";
 		};
 __CONF_SECTION1_EOF

arch/arm/mach-rockchip/Kconfig

@@ -229,6 +229,7 @@ config ROCKCHIP_RK3399
 	select DM_PMIC
 	select DM_REGULATOR_FIXED
 	select BOARD_LATE_INIT
+	imply PRE_CONSOLE_BUFFER
 	imply ROCKCHIP_COMMON_BOARD
 	imply ROCKCHIP_SDRAM_COMMON
 	imply SPL_ROCKCHIP_COMMON_BOARD

arch/arm/mach-snapdragon/misc.c

@@ -41,7 +41,7 @@ void msm_generate_mac_addr(u8 *mac)
 	int i;
 	char sn[9];
 
-	snprintf(sn, 8, "%08x", msm_board_serial());
+	snprintf(sn, 9, "%08x", msm_board_serial());
 
 	/* fill in the mac with serialno, use locally adminstrated pool */
 	mac[0] = 0x02;

arch/arm/mach-socfpga/include/mach/base_addr_a10.h

@@ -47,4 +47,6 @@
 #define SOCFPGA_SDR_FIREWALL_L3_ADDRESS		0xffd13400
 #define SOCFPGA_NOC_FW_H2F_SCR_OFST		0xffd13500
 
+#define SOCFPGA_PHYS_OCRAM_SIZE			0x40000
+
 #endif /* _SOCFPGA_A10_BASE_HARDWARE_H_ */

arch/arm/mach-socfpga/include/mach/base_addr_ac5.h

@@ -59,4 +59,6 @@
 #define SOCFPGA_DMANONSECURE_ADDRESS	0xffe00000
 #define SOCFPGA_DMASECURE_ADDRESS	0xffe01000
 
+#define SOCFPGA_PHYS_OCRAM_SIZE		0x10000
+
 #endif /* _SOCFPGA_BASE_ADDRS_H_ */

arch/arm/mach-socfpga/spl_a10.c

@@ -33,6 +33,38 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define BOOTROM_SHARED_MEM_SIZE		0x800	/* 2KB */
+#define BOOTROM_SHARED_MEM_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					 SOCFPGA_PHYS_OCRAM_SIZE - \
+					 BOOTROM_SHARED_MEM_SIZE)
+#define RST_STATUS_SHARED_ADDR		(BOOTROM_SHARED_MEM_ADDR + 0x438)
+static u32 rst_mgr_status __section(.data);
+
+/*
+ * Bootrom will clear the status register in reset manager and stores the
+ * reset status value in shared memory. Bootrom stores shared data at last
+ * 2KB of onchip RAM.
+ * This function save reset status provided by BootROM to rst_mgr_status.
+ * More information about reset status register value can be found in reset
+ * manager register description.
+ * When running in debugger without Bootrom, r0 to r3 are random values.
+ * So, skip save the value when r0 is not BootROM shared data address.
+ *
+ * r0 - Contains the pointer to the shared memory block. The shared
+ *	memory block is located in the top 2 KB of on-chip RAM.
+ * r1 - contains the length of the shared memory.
+ * r2 - unused and set to 0x0.
+ * r3 - points to the version block.
+ */
+void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2,
+		      unsigned long r3)
+{
+	if (r0 == BOOTROM_SHARED_MEM_ADDR)
+		rst_mgr_status = readl(RST_STATUS_SHARED_ADDR);
+
+	save_boot_params_ret();
+}
+
 u32 spl_boot_device(void)
 {
 	const u32 bsel = readl(socfpga_get_sysmgr_addr() + SYSMGR_A10_BOOTINFO);

arch/arm/mach-tegra/board2.c

@@ -181,6 +181,12 @@ int board_init(void)
 	return nvidia_board_init();
 }
 
+void board_cleanup_before_linux(void)
+{
+	/* power down UPHY PLL */
+	tegra_xusb_padctl_exit();
+}
+
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 static void __gpio_early_init(void)
 {
@@ -211,6 +217,31 @@ int board_early_init_f(void)
 		arch_timer_init();
 #endif
 
+#if defined(CONFIG_DISABLE_SDMMC1_EARLY)
+	/*
+	 * Turn off (reset/disable) SDMMC1 on Nano here, before GPIO INIT.
+	 * We do this because earlier bootloaders have enabled power to
+	 * SDMMC1 on Nano, and toggling power-gpio (PZ3) in pinmux_init()
+	 * results in power being back-driven into the SD-card and SDMMC1
+	 * HW, which is 'bad' as per the HW team.
+	 *
+	 * From the HW team: "LDO2 from the PMIC has already been set to 3.3v in
+	 * nvtboot/CBoot on Nano (for SD-card boot). So when U-Boot's GPIO_INIT
+	 * table sets PZ3 to OUT0 as per the pinmux spreadsheet, it turns off
+	 * the loadswitch. When PZ3 is 0 and not driving, essentially the SDCard
+	 * voltage turns off. Since the SDCard voltage is no longer there, the
+	 * SDMMC CLK/DAT lines are backdriving into what essentially is a
+	 * powered-off SDCard, that's why the voltage drops from 3.3V to ~1.6V"
+	 *
+	 * Note that this can probably be removed when we change over to storing
+	 * all BL components on QSPI on Nano, and U-Boot then becomes the first
+	 * one to turn on SDMMC1 power. Another fix would be to have CBoot
+	 * disable power/gate SDMMC1 off before handing off to U-Boot/kernel.
+	 */
+	reset_set_enable(PERIPH_ID_SDMMC1, 1);
+	clock_set_enable(PERIPH_ID_SDMMC1, 0);
+#endif	/* CONFIG_DISABLE_SDMMC1_EARLY */
+
 	pinmux_init();
 	board_init_uart_f();
 

arch/arm/mach-tegra/tegra210/Kconfig

@@ -35,6 +35,12 @@ config TARGET_P2571
 	help
 	  P2571 is a P2530 married to a P1963 I/O board
 
+config TARGET_P3450_0000
+	bool "NVIDIA Jetson Nano Developer Kit"
+	select BOARD_LATE_INIT
+	help
+	  P3450-0000 is a P3448 CPU board married to a P3449 I/O board.
+
 endchoice
 
 config SYS_SOC
@@ -44,5 +50,6 @@ source "board/nvidia/e2220-1170/Kconfig"
 source "board/nvidia/p2371-0000/Kconfig"
 source "board/nvidia/p2371-2180/Kconfig"
 source "board/nvidia/p2571/Kconfig"
+source "board/nvidia/p3450-0000/Kconfig"
 
 endif

arch/arm/mach-tegra/tegra210/Makefile

@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2013-2015
+# (C) Copyright 2013-2020
 # NVIDIA Corporation <www.nvidia.com>
 #
 # SPDX-License-Identifier:     GPL-2.0+
@@ -7,6 +7,5 @@
 
 obj-y	+= clock.o
 obj-y	+= funcmux.o
-obj-y	+= pinmux.o
 obj-y	+= xusb-padctl.o
 obj-y	+= ../xusb-padctl-common.o

arch/arm/mach-tegra/tegra210/clock.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * (C) Copyright 2013-2015
+ * (C) Copyright 2013-2020
  * NVIDIA Corporation <www.nvidia.com>
  */
 
@@ -333,7 +333,7 @@ static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
 	TYPE(PERIPHC_DMIC3,	CLOCK_TYPE_NONE),
 	TYPE(PERIPHC_APE,	CLOCK_TYPE_NONE),
 	TYPE(PERIPHC_QSPI,	CLOCK_TYPE_PC01C00_C42C41TC40),
-	TYPE(PERIPHC_VI_I2C,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_VI_I2C,	CLOCK_TYPE_PC2CC3M_T16),
 	TYPE(PERIPHC_USB2_HSIC_TRK, CLOCK_TYPE_NONE),
 	TYPE(PERIPHC_PEX_SATA_USB_RX_BYP, CLOCK_TYPE_NONE),
 
@@ -739,7 +739,7 @@ int get_periph_clock_info(enum periph_id periph_id, int *mux_bits,
 	if (!clock_periph_id_isvalid(periph_id))
 		return -1;
 
-	internal_id = periph_id_to_internal_id[periph_id];
+	internal_id = INTERNAL_ID(periph_id_to_internal_id[periph_id]);
 	if (!periphc_internal_id_isvalid(internal_id))
 		return -1;
 
@@ -765,7 +765,7 @@ enum clock_id get_periph_clock_id(enum periph_id periph_id, int source)
 	if (!clock_periph_id_isvalid(periph_id))
 		return CLOCK_ID_NONE;
 
-	internal_id = periph_id_to_internal_id[periph_id];
+	internal_id = INTERNAL_ID(periph_id_to_internal_id[periph_id]);
 	if (!periphc_internal_id_isvalid(internal_id))
 		return CLOCK_ID_NONE;
 
@@ -1235,25 +1235,6 @@ int tegra_plle_enable(void)
 	value &= ~PLLE_SS_CNTL_INTERP_RESET;
 	writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
 
-	/* 7. Enable HW power sequencer for PLLE */
-
-	value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
-	value &= ~PLLE_MISC_IDDQ_SWCTL;
-	writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
-
-	value = readl(NV_PA_CLK_RST_BASE + PLLE_AUX);
-	value &= ~PLLE_AUX_SS_SWCTL;
-	value &= ~PLLE_AUX_ENABLE_SWCTL;
-	value |= PLLE_AUX_SS_SEQ_INCLUDE;
-	value |= PLLE_AUX_USE_LOCKDET;
-	writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX);
-
-	/* 8. Wait 1 us */
-
-	udelay(1);
-	value |= PLLE_AUX_SEQ_ENABLE;
-	writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX);
-
 	return 0;
 }
 

arch/arm/mach-tegra/tegra210/pinmux.c

@@ -1,194 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/pinmux.h>
-
-#define PIN(pin, f0, f1, f2, f3)	\
-	{				\
-		.funcs = {		\
-			PMUX_FUNC_##f0,	\
-			PMUX_FUNC_##f1,	\
-			PMUX_FUNC_##f2,	\
-			PMUX_FUNC_##f3,	\
-		},			\
-	}
-
-#define PIN_RESERVED {}
-
-static const struct pmux_pingrp_desc tegra210_pingroups[] = {
-	/*  pin,                  f0,         f1,     f2,    f3 */
-	/* Offset 0x3000 */
-	PIN(SDMMC1_CLK_PM0,       SDMMC1,     RSVD1,  RSVD2, RSVD3),
-	PIN(SDMMC1_CMD_PM1,       SDMMC1,     SPI3,   RSVD2, RSVD3),
-	PIN(SDMMC1_DAT3_PM2,      SDMMC1,     SPI3,   RSVD2, RSVD3),
-	PIN(SDMMC1_DAT2_PM3,      SDMMC1,     SPI3,   RSVD2, RSVD3),
-	PIN(SDMMC1_DAT1_PM4,      SDMMC1,     SPI3,   RSVD2, RSVD3),
-	PIN(SDMMC1_DAT0_PM5,      SDMMC1,     RSVD1,  RSVD2, RSVD3),
-	PIN_RESERVED,
-	/* Offset 0x301c */
-	PIN(SDMMC3_CLK_PP0,       SDMMC3,     RSVD1,  RSVD2, RSVD3),
-	PIN(SDMMC3_CMD_PP1,       SDMMC3,     RSVD1,  RSVD2, RSVD3),
-	PIN(SDMMC3_DAT0_PP5,      SDMMC3,     RSVD1,  RSVD2, RSVD3),
-	PIN(SDMMC3_DAT1_PP4,      SDMMC3,     RSVD1,  RSVD2, RSVD3),
-	PIN(SDMMC3_DAT2_PP3,      SDMMC3,     RSVD1,  RSVD2, RSVD3),
-	PIN(SDMMC3_DAT3_PP2,      SDMMC3,     RSVD1,  RSVD2, RSVD3),
-	PIN_RESERVED,
-	/* Offset 0x3038 */
-	PIN(PEX_L0_RST_N_PA0,     PE0,        RSVD1,  RSVD2, RSVD3),
-	PIN(PEX_L0_CLKREQ_N_PA1,  PE0,        RSVD1,  RSVD2, RSVD3),
-	PIN(PEX_WAKE_N_PA2,       PE,         RSVD1,  RSVD2, RSVD3),
-	PIN(PEX_L1_RST_N_PA3,     PE1,        RSVD1,  RSVD2, RSVD3),
-	PIN(PEX_L1_CLKREQ_N_PA4,  PE1,        RSVD1,  RSVD2, RSVD3),
-	PIN(SATA_LED_ACTIVE_PA5,  SATA,       RSVD1,  RSVD2, RSVD3),
-	PIN(SPI1_MOSI_PC0,        SPI1,       RSVD1,  RSVD2, RSVD3),
-	PIN(SPI1_MISO_PC1,        SPI1,       RSVD1,  RSVD2, RSVD3),
-	PIN(SPI1_SCK_PC2,         SPI1,       RSVD1,  RSVD2, RSVD3),
-	PIN(SPI1_CS0_PC3,         SPI1,       RSVD1,  RSVD2, RSVD3),
-	PIN(SPI1_CS1_PC4,         SPI1,       RSVD1,  RSVD2, RSVD3),
-	PIN(SPI2_MOSI_PB4,        SPI2,       DTV,    RSVD2, RSVD3),
-	PIN(SPI2_MISO_PB5,        SPI2,       DTV,    RSVD2, RSVD3),
-	PIN(SPI2_SCK_PB6,         SPI2,       DTV,    RSVD2, RSVD3),
-	PIN(SPI2_CS0_PB7,         SPI2,       DTV,    RSVD2, RSVD3),
-	PIN(SPI2_CS1_PDD0,        SPI2,       RSVD1,  RSVD2, RSVD3),
-	PIN(SPI4_MOSI_PC7,        SPI4,       RSVD1,  RSVD2, RSVD3),
-	PIN(SPI4_MISO_PD0,        SPI4,       RSVD1,  RSVD2, RSVD3),
-	PIN(SPI4_SCK_PC5,         SPI4,       RSVD1,  RSVD2, RSVD3),
-	PIN(SPI4_CS0_PC6,         SPI4,       RSVD1,  RSVD2, RSVD3),
-	PIN(QSPI_SCK_PEE0,        QSPI,       RSVD1,  RSVD2, RSVD3),
-	PIN(QSPI_CS_N_PEE1,       QSPI,       RSVD1,  RSVD2, RSVD3),
-	PIN(QSPI_IO0_PEE2,        QSPI,       RSVD1,  RSVD2, RSVD3),
-	PIN(QSPI_IO1_PEE3,        QSPI,       RSVD1,  RSVD2, RSVD3),
-	PIN(QSPI_IO2_PEE4,        QSPI,       RSVD1,  RSVD2, RSVD3),
-	PIN(QSPI_IO3_PEE5,        QSPI,       RSVD1,  RSVD2, RSVD3),
-	PIN_RESERVED,
-	/* Offset 0x30a4 */
-	PIN(DMIC1_CLK_PE0,        DMIC1,      I2S3,   RSVD2, RSVD3),
-	PIN(DMIC1_DAT_PE1,        DMIC1,      I2S3,   RSVD2, RSVD3),
-	PIN(DMIC2_CLK_PE2,        DMIC2,      I2S3,   RSVD2, RSVD3),
-	PIN(DMIC2_DAT_PE3,        DMIC2,      I2S3,   RSVD2, RSVD3),
-	PIN(DMIC3_CLK_PE4,        DMIC3,      I2S5A,  RSVD2, RSVD3),
-	PIN(DMIC3_DAT_PE5,        DMIC3,      I2S5A,  RSVD2, RSVD3),
-	PIN(GEN1_I2C_SCL_PJ1,     I2C1,       RSVD1,  RSVD2, RSVD3),
-	PIN(GEN1_I2C_SDA_PJ0,     I2C1,       RSVD1,  RSVD2, RSVD3),
-	PIN(GEN2_I2C_SCL_PJ2,     I2C2,       RSVD1,  RSVD2, RSVD3),
-	PIN(GEN2_I2C_SDA_PJ3,     I2C2,       RSVD1,  RSVD2, RSVD3),
-	PIN(GEN3_I2C_SCL_PF0,     I2C3,       RSVD1,  RSVD2, RSVD3),
-	PIN(GEN3_I2C_SDA_PF1,     I2C3,       RSVD1,  RSVD2, RSVD3),
-	PIN(CAM_I2C_SCL_PS2,      I2C3,       I2CVI,  RSVD2, RSVD3),
-	PIN(CAM_I2C_SDA_PS3,      I2C3,       I2CVI,  RSVD2, RSVD3),
-	PIN(PWR_I2C_SCL_PY3,      I2CPMU,     RSVD1,  RSVD2, RSVD3),
-	PIN(PWR_I2C_SDA_PY4,      I2CPMU,     RSVD1,  RSVD2, RSVD3),
-	PIN(UART1_TX_PU0,         UARTA,      RSVD1,  RSVD2, RSVD3),
-	PIN(UART1_RX_PU1,         UARTA,      RSVD1,  RSVD2, RSVD3),
-	PIN(UART1_RTS_PU2,        UARTA,      RSVD1,  RSVD2, RSVD3),
-	PIN(UART1_CTS_PU3,        UARTA,      RSVD1,  RSVD2, RSVD3),
-	PIN(UART2_TX_PG0,         UARTB,      I2S4A,  SPDIF, UART),
-	PIN(UART2_RX_PG1,         UARTB,      I2S4A,  SPDIF, UART),
-	PIN(UART2_RTS_PG2,        UARTB,      I2S4A,  RSVD2, UART),
-	PIN(UART2_CTS_PG3,        UARTB,      I2S4A,  RSVD2, UART),
-	PIN(UART3_TX_PD1,         UARTC,      SPI4,   RSVD2, RSVD3),
-	PIN(UART3_RX_PD2,         UARTC,      SPI4,   RSVD2, RSVD3),
-	PIN(UART3_RTS_PD3,        UARTC,      SPI4,   RSVD2, RSVD3),
-	PIN(UART3_CTS_PD4,        UARTC,      SPI4,   RSVD2, RSVD3),
-	PIN(UART4_TX_PI4,         UARTD,      UART,   RSVD2, RSVD3),
-	PIN(UART4_RX_PI5,         UARTD,      UART,   RSVD2, RSVD3),
-	PIN(UART4_RTS_PI6,        UARTD,      UART,   RSVD2, RSVD3),
-	PIN(UART4_CTS_PI7,        UARTD,      UART,   RSVD2, RSVD3),
-	PIN(DAP1_FS_PB0,          I2S1,       RSVD1,  RSVD2, RSVD3),
-	PIN(DAP1_DIN_PB1,         I2S1,       RSVD1,  RSVD2, RSVD3),
-	PIN(DAP1_DOUT_PB2,        I2S1,       RSVD1,  RSVD2, RSVD3),
-	PIN(DAP1_SCLK_PB3,        I2S1,       RSVD1,  RSVD2, RSVD3),
-	PIN(DAP2_FS_PAA0,         I2S2,       RSVD1,  RSVD2, RSVD3),
-	PIN(DAP2_DIN_PAA2,        I2S2,       RSVD1,  RSVD2, RSVD3),
-	PIN(DAP2_DOUT_PAA3,       I2S2,       RSVD1,  RSVD2, RSVD3),
-	PIN(DAP2_SCLK_PAA1,       I2S2,       RSVD1,  RSVD2, RSVD3),
-	PIN(DAP4_FS_PJ4,          I2S4B,      RSVD1,  RSVD2, RSVD3),
-	PIN(DAP4_DIN_PJ5,         I2S4B,      RSVD1,  RSVD2, RSVD3),
-	PIN(DAP4_DOUT_PJ6,        I2S4B,      RSVD1,  RSVD2, RSVD3),
-	PIN(DAP4_SCLK_PJ7,        I2S4B,      RSVD1,  RSVD2, RSVD3),
-	PIN(CAM1_MCLK_PS0,        EXTPERIPH3, RSVD1,  RSVD2, RSVD3),
-	PIN(CAM2_MCLK_PS1,        EXTPERIPH3, RSVD1,  RSVD2, RSVD3),
-	PIN(JTAG_RTCK,            JTAG,       RSVD1,  RSVD2, RSVD3),
-	PIN(CLK_32K_IN,           CLK,        RSVD1,  RSVD2, RSVD3),
-	PIN(CLK_32K_OUT_PY5,      SOC,        BLINK,  RSVD2, RSVD3),
-	PIN(BATT_BCL,             BCL,        RSVD1,  RSVD2, RSVD3),
-	PIN(CLK_REQ,              SYS,        RSVD1,  RSVD2, RSVD3),
-	PIN(CPU_PWR_REQ,          CPU,        RSVD1,  RSVD2, RSVD3),
-	PIN(PWR_INT_N,            PMI,        RSVD1,  RSVD2, RSVD3),
-	PIN(SHUTDOWN,             SHUTDOWN,   RSVD1,  RSVD2, RSVD3),
-	PIN(CORE_PWR_REQ,         CORE,       RSVD1,  RSVD2, RSVD3),
-	PIN(AUD_MCLK_PBB0,        AUD,        RSVD1,  RSVD2, RSVD3),
-	PIN(DVFS_PWM_PBB1,        RSVD0,      CLDVFS, SPI3,  RSVD3),
-	PIN(DVFS_CLK_PBB2,        RSVD0,      CLDVFS, SPI3,  RSVD3),
-	PIN(GPIO_X1_AUD_PBB3,     RSVD0,      RSVD1,  SPI3,  RSVD3),
-	PIN(GPIO_X3_AUD_PBB4,     RSVD0,      RSVD1,  SPI3,  RSVD3),
-	PIN(PCC7,                 RSVD0,      RSVD1,  RSVD2, RSVD3),
-	PIN(HDMI_CEC_PCC0,        CEC,        RSVD1,  RSVD2, RSVD3),
-	PIN(HDMI_INT_DP_HPD_PCC1, DP,         RSVD1,  RSVD2, RSVD3),
-	PIN(SPDIF_OUT_PCC2,       SPDIF,      RSVD1,  RSVD2, RSVD3),
-	PIN(SPDIF_IN_PCC3,        SPDIF,      RSVD1,  RSVD2, RSVD3),
-	PIN(USB_VBUS_EN0_PCC4,    USB,        RSVD1,  RSVD2, RSVD3),
-	PIN(USB_VBUS_EN1_PCC5,    USB,        RSVD1,  RSVD2, RSVD3),
-	PIN(DP_HPD0_PCC6,         DP,         RSVD1,  RSVD2, RSVD3),
-	PIN(WIFI_EN_PH0,          RSVD0,      RSVD1,  RSVD2, RSVD3),
-	PIN(WIFI_RST_PH1,         RSVD0,      RSVD1,  RSVD2, RSVD3),
-	PIN(WIFI_WAKE_AP_PH2,     RSVD0,      RSVD1,  RSVD2, RSVD3),
-	PIN(AP_WAKE_BT_PH3,       RSVD0,      UARTB,  SPDIF, RSVD3),
-	PIN(BT_RST_PH4,           RSVD0,      UARTB,  SPDIF, RSVD3),
-	PIN(BT_WAKE_AP_PH5,       RSVD0,      RSVD1,  RSVD2, RSVD3),
-	PIN(AP_WAKE_NFC_PH7,      RSVD0,      RSVD1,  RSVD2, RSVD3),
-	PIN(NFC_EN_PI0,           RSVD0,      RSVD1,  RSVD2, RSVD3),
-	PIN(NFC_INT_PI1,          RSVD0,      RSVD1,  RSVD2, RSVD3),
-	PIN(GPS_EN_PI2,           RSVD0,      RSVD1,  RSVD2, RSVD3),
-	PIN(GPS_RST_PI3,          RSVD0,      RSVD1,  RSVD2, RSVD3),
-	PIN(CAM_RST_PS4,          VGP1,       RSVD1,  RSVD2, RSVD3),
-	PIN(CAM_AF_EN_PS5,        VIMCLK,     VGP2,   RSVD2, RSVD3),
-	PIN(CAM_FLASH_EN_PS6,     VIMCLK,     VGP3,   RSVD2, RSVD3),
-	PIN(CAM1_PWDN_PS7,        VGP4,       RSVD1,  RSVD2, RSVD3),
-	PIN(CAM2_PWDN_PT0,        VGP5,       RSVD1,  RSVD2, RSVD3),
-	PIN(CAM1_STROBE_PT1,      VGP6,       RSVD1,  RSVD2, RSVD3),
-	PIN(LCD_TE_PY2,           DISPLAYA,   RSVD1,  RSVD2, RSVD3),
-	PIN(LCD_BL_PWM_PV0,       DISPLAYA,   PWM0,   SOR0,  RSVD3),
-	PIN(LCD_BL_EN_PV1,        RSVD0,      RSVD1,  RSVD2, RSVD3),
-	PIN(LCD_RST_PV2,          RSVD0,      RSVD1,  RSVD2, RSVD3),
-	PIN(LCD_GPIO1_PV3,        DISPLAYB,   RSVD1,  RSVD2, RSVD3),
-	PIN(LCD_GPIO2_PV4,        DISPLAYB,   PWM1,   RSVD2, SOR1),
-	PIN(AP_READY_PV5,         RSVD0,      RSVD1,  RSVD2, RSVD3),
-	PIN(TOUCH_RST_PV6,        RSVD0,      RSVD1,  RSVD2, RSVD3),
-	PIN(TOUCH_CLK_PV7,        TOUCH,      RSVD1,  RSVD2, RSVD3),
-	PIN(MODEM_WAKE_AP_PX0,    RSVD0,      RSVD1,  RSVD2, RSVD3),
-	PIN(TOUCH_INT_PX1,        RSVD0,      RSVD1,  RSVD2, RSVD3),
-	PIN(MOTION_INT_PX2,       RSVD0,      RSVD1,  RSVD2, RSVD3),
-	PIN(ALS_PROX_INT_PX3,     RSVD0,      RSVD1,  RSVD2, RSVD3),
-	PIN(TEMP_ALERT_PX4,       RSVD0,      RSVD1,  RSVD2, RSVD3),
-	PIN(BUTTON_POWER_ON_PX5,  RSVD0,      RSVD1,  RSVD2, RSVD3),
-	PIN(BUTTON_VOL_UP_PX6,    RSVD0,      RSVD1,  RSVD2, RSVD3),
-	PIN(BUTTON_VOL_DOWN_PX7,  RSVD0,      RSVD1,  RSVD2, RSVD3),
-	PIN(BUTTON_SLIDE_SW_PY0,  RSVD0,      RSVD1,  RSVD2, RSVD3),
-	PIN(BUTTON_HOME_PY1,      RSVD0,      RSVD1,  RSVD2, RSVD3),
-	PIN(PA6,                  SATA,       RSVD1,  RSVD2, RSVD3),
-	PIN(PE6,                  RSVD0,      I2S5A,  PWM2,  RSVD3),
-	PIN(PE7,                  RSVD0,      I2S5A,  PWM3,  RSVD3),
-	PIN(PH6,                  RSVD0,      RSVD1,  RSVD2, RSVD3),
-	PIN(PK0,                  IQC0,       I2S5B,  RSVD2, RSVD3),
-	PIN(PK1,                  IQC0,       I2S5B,  RSVD2, RSVD3),
-	PIN(PK2,                  IQC0,       I2S5B,  RSVD2, RSVD3),
-	PIN(PK3,                  IQC0,       I2S5B,  RSVD2, RSVD3),
-	PIN(PK4,                  IQC1,       RSVD1,  RSVD2, RSVD3),
-	PIN(PK5,                  IQC1,       RSVD1,  RSVD2, RSVD3),
-	PIN(PK6,                  IQC1,       RSVD1,  RSVD2, RSVD3),
-	PIN(PK7,                  IQC1,       RSVD1,  RSVD2, RSVD3),
-	PIN(PL0,                  RSVD0,      RSVD1,  RSVD2, RSVD3),
-	PIN(PL1,                  SOC,        RSVD1,  RSVD2, RSVD3),
-	PIN(PZ0,                  VIMCLK2,    RSVD1,  RSVD2, RSVD3),
-	PIN(PZ1,                  VIMCLK2,    SDMMC1, RSVD2, RSVD3),
-	PIN(PZ2,                  SDMMC3,     CCLA,   RSVD2, RSVD3),
-	PIN(PZ3,                  SDMMC3,     RSVD1,  RSVD2, RSVD3),
-	PIN(PZ4,                  SDMMC1,     RSVD1,  RSVD2, RSVD3),
-	PIN(PZ5,                  SOC,        RSVD1,  RSVD2, RSVD3),
-};
-const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra210_pingroups;

arch/arm/mach-tegra/tegra210/xusb-padctl.c

@@ -170,6 +170,17 @@ static int phy_unprepare(struct tegra_xusb_phy *phy)
 	return tegra_xusb_padctl_disable(phy->padctl);
 }
 
+#define XUSB_PADCTL_USB3_PAD_MUX 0x28
+#define  XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE (1 << 0)
+#define  XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK0 (1 << 1)
+#define  XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK1 (1 << 2)
+#define  XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK2 (1 << 3)
+#define  XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK3 (1 << 4)
+#define  XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK4 (1 << 5)
+#define  XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK5 (1 << 6)
+#define  XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK6 (1 << 7)
+#define  XUSB_PADCTL_USB3_PAD_MUX_FORCE_SATA_PAD_IDDQ_DISABLE_MASK0 (1 << 8)
+
 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1 0x360
 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV_MASK (0xff << 20)
 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV(x) (((x) & 0xff) << 20)
@@ -366,31 +377,6 @@ static int pcie_phy_enable(struct tegra_xusb_phy *phy)
 	value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN;
 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
 
-	value = readl(NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
-	value &= ~CLK_RST_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL;
-	value &= ~CLK_RST_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL;
-	value |= CLK_RST_XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET;
-	value |= CLK_RST_XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ;
-	writel(value, NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
-
-	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
-	value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD;
-	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
-
-	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
-	value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_OVRD;
-	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
-
-	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
-	value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_OVRD;
-	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
-
-	udelay(1);
-
-	value = readl(NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
-	value |= CLK_RST_XUSBIO_PLL_CFG0_SEQ_ENABLE;
-	writel(value, NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
-
 	debug("< %s()\n", __func__);
 	return 0;
 }
@@ -454,3 +440,35 @@ void tegra_xusb_padctl_init(void)
 	ret = tegra_xusb_process_nodes(nodes, count, &tegra210_socdata);
 	debug("%s: done, ret=%d\n", __func__, ret);
 }
+
+void tegra_xusb_padctl_exit(void)
+{
+	u32 value;
+
+	debug("> %s\n", __func__);
+
+	value = padctl_readl(&padctl, XUSB_PADCTL_USB3_PAD_MUX);
+	value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE;
+	value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK0;
+	value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK1;
+	value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK2;
+	value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK3;
+	value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK4;
+	value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK5;
+	value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK6;
+	value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_SATA_PAD_IDDQ_DISABLE_MASK0;
+	padctl_writel(&padctl, value, XUSB_PADCTL_USB3_PAD_MUX);
+
+	value = padctl_readl(&padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
+	value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_IDDQ;
+	value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP_MASK;
+	value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP(3);
+	value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_ENABLE;
+	padctl_writel(&padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
+
+	reset_set_enable(PERIPH_ID_PEX_USB_UPHY, 1);
+	while (padctl.enable)
+		tegra_xusb_padctl_disable(&padctl);
+
+	debug("< %s()\n", __func__);
+}

arch/arm/mach-tegra/xusb-padctl-dummy.c

@@ -36,3 +36,7 @@ int __weak tegra_xusb_phy_unprepare(struct tegra_xusb_phy *phy)
 void __weak tegra_xusb_padctl_init(void)
 {
 }
+
+void __weak tegra_xusb_padctl_exit(void)
+{
+}

arch/mips/config.mk

@@ -36,7 +36,6 @@ CONFIG_STANDALONE_LOAD_ADDR	?= 0xffffffff80200000
 endif
 
 PLATFORM_CPPFLAGS += -D__MIPS__
-PLATFORM_ELFENTRY = "__start"
 PLATFORM_ELFFLAGS += -B mips $(OBJCOPYFLAGS)
 
 #

arch/mips/cpu/time.c

@@ -13,7 +13,7 @@ unsigned long notrace timer_read_counter(void)
 	return read_c0_count();
 }
 
-ulong notrace get_tbclk(void)
+ulong notrace __weak get_tbclk(void)
 {
 	return CONFIG_SYS_MIPS_TIMER_FREQ;
 }

arch/mips/lib/Makefile

@@ -11,5 +11,6 @@ obj-y	+= stack.o
 obj-y	+= traps.o
 
 obj-$(CONFIG_CMD_BOOTM) += bootm.o
+obj-$(CONFIG_CMD_GO) += boot.o
 
 lib-$(CONFIG_USE_PRIVATE_LIBGCC) += ashldi3.o ashrdi3.o lshrdi3.o

arch/mips/lib/boot.c

@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Stefan Roese <sr@denx.de>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <cpu_func.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+unsigned long do_go_exec(ulong (*entry)(int, char * const []),
+			 int argc, char * const argv[])
+{
+	/*
+	 * Flush cache before jumping to application. Let's flush the
+	 * whole SDRAM area, since we don't know the size of the image
+	 * that was loaded.
+	 */
+	flush_cache(gd->bd->bi_memstart, gd->ram_top - gd->bd->bi_memstart);
+
+	return entry(argc, argv);
+}

arch/mips/lib/cache.c

@@ -141,7 +141,7 @@ ops_done:
 	instruction_hazard_barrier();
 }
 
-void flush_dcache_range(ulong start_addr, ulong stop)
+void __weak flush_dcache_range(ulong start_addr, ulong stop)
 {
 	unsigned long lsize = dcache_line_size();
 	unsigned long slsize = scache_line_size();

arch/mips/mach-mscc/cpu.c

@@ -7,6 +7,7 @@
 
 #include <asm/io.h>
 #include <asm/types.h>
+#include <asm/mipsregs.h>
 
 #include <mach/tlb.h>
 #include <mach/ddr.h>
@@ -53,7 +54,6 @@ void vcoreiii_tlb_init(void)
 		   MMU_REGIO_RW);
 #endif
 
-#if  CONFIG_SYS_TEXT_BASE == MSCC_FLASH_TO
 	/*
 	 * If U-Boot is located in NOR then we want to be able to use
 	 * the data cache in order to boot in a decent duration
@@ -71,9 +71,10 @@ void vcoreiii_tlb_init(void)
 	create_tlb(tlbix++, MSCC_DDR_TO, MSCC_RAM_TLB_SIZE, MMU_REGIO_RW,
 		   MSCC_ATTRIB2);
 
-	/* Enable caches by clearing the bit ERL, which is set on reset */
-	write_c0_status(read_c0_status() & ~BIT(2));
-#endif /* CONFIG_SYS_TEXT_BASE */
+	/* Enable mapping (using TLB) kuseg by clearing the bit ERL,
+	 * which is set on reset.
+	 */
+	write_c0_status(read_c0_status() & ~ST0_ERL);
 }
 
 int mach_cpu_init(void)

arch/mips/mach-mscc/dram.c

@@ -31,7 +31,7 @@ static inline int vcoreiii_train_bytelane(void)
 
 int vcoreiii_ddr_init(void)
 {
-	int res;
+	register int res;
 
 	if (!(readl(BASE_CFG + ICPU_MEMCTRL_STAT)
 	      & ICPU_MEMCTRL_STAT_INIT_DONE)) {
@@ -40,20 +40,19 @@ int vcoreiii_ddr_init(void)
 		if (hal_vcoreiii_init_dqs() || vcoreiii_train_bytelane())
 			hal_vcoreiii_ddr_failed();
 	}
-#if (CONFIG_SYS_TEXT_BASE != 0x20000000)
+
 	res = dram_check();
 	if (res == 0)
 		hal_vcoreiii_ddr_verified();
 	else
 		hal_vcoreiii_ddr_failed();
 
-	/* Clear boot-mode and read-back to activate/verify */
+	/*  Remap DDR to kuseg: Clear boot-mode */
 	clrbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
 		     ICPU_GENERAL_CTRL_BOOT_MODE_ENA);
+	/* - and read-back to activate/verify */
 	readl(BASE_CFG + ICPU_GENERAL_CTRL);
-#else
-	res = 0;
-#endif
+
 	return res;
 }
 
@@ -66,9 +65,6 @@ int print_cpuinfo(void)
 
 int dram_init(void)
 {
-	while (vcoreiii_ddr_init())
-		;
-
 	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
 	return 0;
 }

arch/mips/mach-mscc/include/mach/ddr.h

@@ -435,16 +435,12 @@ static inline void hal_vcoreiii_ddr_failed(void)
 	reset = KSEG0ADDR(_machine_restart);
 	icache_lock((void *)reset, 128);
 	asm volatile ("jr %0"::"r" (reset));
-
-	panic("DDR init failed\n");
 }
 #else				/* JR2 || ServalT */
 static inline void hal_vcoreiii_ddr_failed(void)
 {
 	writel(0, BASE_CFG + ICPU_RESET);
 	writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_CFG + PERF_SOFT_RST);
-
-	panic("DDR init failed\n");
 }
 #endif
 

arch/mips/mach-mscc/lowlevel_init.S

@@ -8,6 +8,7 @@
 
     .set noreorder
     .extern     vcoreiii_tlb_init
+    .extern     vcoreiii_ddr_init
 #ifdef CONFIG_SOC_LUTON
     .extern     pll_init
 #endif
@@ -17,14 +18,28 @@ LEAF(lowlevel_init)
 	 * As we have no stack yet, we can assume the restricted
 	 * luxury of the sX-registers without saving them
 	 */
-	move	s0,ra
+
+	/* Modify ra/s0 such we return to physical NOR location */
+	li	t0, 0x0fffffff
+	li	t1, CONFIG_SYS_TEXT_BASE
+	and	s0, ra, t0
+	add	s0, s0, t1
 
 	jal	vcoreiii_tlb_init
 	 nop
+
 #ifdef CONFIG_SOC_LUTON
 	jal	pll_init
 	 nop
 #endif
+
+	/* Initialize DDR controller to enable stack/gd/heap */
+0:
+	jal	vcoreiii_ddr_init
+	 nop
+	bnez	v0, 0b		/* Retry on error */
+	 nop
+
 	jr	s0
 	 nop
 	END(lowlevel_init)

arch/powerpc/dts/gdsys/mpc8308.dtsi

@@ -17,6 +17,7 @@
 /dts-v1/;
 
 #include <dt-bindings/memory/mpc83xx-sdram.h>
+#include <dt-bindings/clk/mpc83xx-clk.h>
 
 / {
 	compatible = "fsl,mpc8308rdb";
@@ -50,6 +51,11 @@
 		};
 	};
 
+	socclocks: clocks {
+		compatible = "fsl,mpc8308-clk";
+		#clock-cells = <1>;
+	};
+
 	board_lbc: localbus@e0005000 {
 		#address-cells = <2>;
 		#size-cells = <1>;
@@ -173,6 +179,7 @@
 			reg = <0x7000 0x1000>;
 			interrupts = <16 0x8>;
 			interrupt-parent = <&ipic>;
+			clocks = <&socclocks MPC83XX_CLK_CSB>;
 			mode = "cpu";
 		};
 

arch/u-boot-elf.lds

@@ -0,0 +1,9 @@
+ENTRY(CONFIG_PLATFORM_ELFENTRY)
+SECTIONS
+{
+	. = CONFIG_PLATFORM_ELFENTRY;
+
+	.data : {
+		*(.data*)
+	}
+}

arch/x86/include/asm/arch-tangier/acpi/southcluster.asl

@@ -240,6 +240,21 @@ Device (PCI0)
             Return (STA_VISIBLE)
         }
 
+        Name (SSCN, Package ()
+        {
+            0x02F8, 0x037B, Zero,
+        })
+
+        Name (FMCN, Package ()
+        {
+            0x0087, 0x010A, Zero,
+        })
+
+        Name (HSCN, Package ()
+        {
+            0x0008, 0x0020, Zero,
+        })
+
         Name (RBUF, ResourceTemplate()
         {
             FixedDMA(0x0009, 0x0000, Width32bit, )
@@ -260,6 +275,21 @@ Device (PCI0)
         {
             Return (STA_VISIBLE)
         }
+
+        Name (SSCN, Package ()
+        {
+            0x02F8, 0x037B, Zero,
+        })
+
+        Name (FMCN, Package ()
+        {
+            0x0087, 0x010A, Zero,
+        })
+
+        Name (HSCN, Package ()
+        {
+            0x0008, 0x0020, Zero,
+        })
     }
 
     Device (GPIO)
@@ -291,6 +321,53 @@ Device (PCI0)
         }
     }
 
+    Device (DWC3)
+    {
+        Name (_ADR, 0x00110000)
+        Name (_DEP, Package ()
+        {
+            ^IPC1.PMIC
+        })
+
+        Method (_STA, 0, NotSerialized)
+        {
+            Return (STA_VISIBLE)
+        }
+
+        Device (RHUB)
+        {
+            Name (_ADR, Zero)
+
+            /* GPLD: Generate Port Location Data (PLD) */
+            Method (GPLD, 1, Serialized) {
+                Name (PCKG, Package () {
+                    Buffer (0x14) {}
+                })
+
+                /* REV: Revision 0x02 for ACPI 5.0 */
+                CreateField (DerefOf (Index (PCKG, Zero)), Zero, 0x07, REV)
+                Store (0x0002, REV)
+
+                /* VISI: Port visibility to user per port */
+                CreateField (DerefOf (Index (PCKG, Zero)), 0x40, One, VISI)
+                Store (Arg0, VISI)
+
+                /* VOFF: Vertical offset is not supplied */
+                CreateField (DerefOf (Index (PCKG, Zero)), 0x80, 0x10, VOFF)
+                Store (0xFFFF, VOFF)
+
+                /* HOFF: Horizontal offset is not supplied */
+                CreateField (DerefOf (Index (PCKG, Zero)), 0x90, 0x10, HOFF)
+                Store (0xFFFF, HOFF)
+
+                Return (PCKG)
+            }
+
+            Device (HS01) { Name (_ADR, 1) }
+            Device (SS01) { Name (_ADR, 2) }
+        }
+    }
+
     Device (PWM0)
     {
         Name (_ADR, 0x00170000)

arch/x86/lib/acpi_table.c

@@ -109,14 +109,11 @@ static void acpi_add_table(struct acpi_rsdp *rsdp, void *table)
 {
 	int i, entries_num;
 	struct acpi_rsdt *rsdt;
-	struct acpi_xsdt *xsdt = NULL;
+	struct acpi_xsdt *xsdt;
 
 	/* The RSDT is mandatory while the XSDT is not */
 	rsdt = (struct acpi_rsdt *)rsdp->rsdt_address;
 
-	if (rsdp->xsdt_address)
-		xsdt = (struct acpi_xsdt *)((u32)rsdp->xsdt_address);
-
 	/* This should always be MAX_ACPI_TABLES */
 	entries_num = ARRAY_SIZE(rsdt->entry);
 
@@ -135,30 +132,34 @@ static void acpi_add_table(struct acpi_rsdp *rsdp, void *table)
 
 	/* Fix RSDT length or the kernel will assume invalid entries */
 	rsdt->header.length = sizeof(struct acpi_table_header) +
-				(sizeof(u32) * (i + 1));
+				sizeof(u32) * (i + 1);
 
 	/* Re-calculate checksum */
 	rsdt->header.checksum = 0;
 	rsdt->header.checksum = table_compute_checksum((u8 *)rsdt,
 			rsdt->header.length);
 
+	/* The RSDT is mandatory while the XSDT is not */
+	if (!rsdp->xsdt_address)
+		return;
+
 	/*
 	 * And now the same thing for the XSDT. We use the same index as for
 	 * now we want the XSDT and RSDT to always be in sync in U-Boot
 	 */
-	if (xsdt) {
-		/* Add table to the XSDT */
-		xsdt->entry[i] = (u64)(u32)table;
+	xsdt = (struct acpi_xsdt *)((u32)rsdp->xsdt_address);
 
-		/* Fix XSDT length */
-		xsdt->header.length = sizeof(struct acpi_table_header) +
-			(sizeof(u64) * (i + 1));
+	/* Add table to the XSDT */
+	xsdt->entry[i] = (u64)(u32)table;
 
-		/* Re-calculate checksum */
-		xsdt->header.checksum = 0;
-		xsdt->header.checksum = table_compute_checksum((u8 *)xsdt,
-				xsdt->header.length);
-	}
+	/* Fix XSDT length */
+	xsdt->header.length = sizeof(struct acpi_table_header) +
+				sizeof(u64) * (i + 1);
+
+	/* Re-calculate checksum */
+	xsdt->header.checksum = 0;
+	xsdt->header.checksum = table_compute_checksum((u8 *)xsdt,
+			xsdt->header.length);
 }
 
 static void acpi_create_facs(struct acpi_facs *facs)

board/dhelectronics/dh_stm32mp1/board.c

@@ -78,22 +78,21 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int setup_mac_address(void)
 {
-	struct udevice *dev;
-	ofnode eeprom;
 	unsigned char enetaddr[6];
-	int ret;
+	struct udevice *dev;
+	int off, ret;
 
 	ret = eth_env_get_enetaddr("ethaddr", enetaddr);
 	if (ret)	/* ethaddr is already set */
 		return 0;
 
-	eeprom = ofnode_path("/soc/i2c@5c002000/eeprom@50");
-	if (!ofnode_valid(eeprom)) {
-		printf("Invalid hardware path to EEPROM!\n");
-		return -ENODEV;
+	off = fdt_path_offset(gd->fdt_blob, "eeprom0");
+	if (off < 0) {
+		printf("%s: No eeprom0 path offset\n", __func__);
+		return off;
 	}
 
-	ret = uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, eeprom, &dev);
+	ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
 	if (ret) {
 		printf("Cannot find EEPROM!\n");
 		return ret;

board/nvidia/e2220-1170/e2220-1170.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * (C) Copyright 2013-2015
+ * (C) Copyright 2013-2019
  * NVIDIA Corporation <www.nvidia.com>
  */
 
@@ -9,7 +9,6 @@
 #include <asm/arch/gpio.h>
 #include <asm/arch/pinmux.h>
 #include "../p2571/max77620_init.h"
-#include "pinmux-config-e2220-1170.h"
 
 void pin_mux_mmc(void)
 {
@@ -30,21 +29,3 @@ void pin_mux_mmc(void)
 	if (ret)
 		printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret);
 }
-
-/*
- * Routine: pinmux_init
- * Description: Do individual peripheral pinmux configs
- */
-void pinmux_init(void)
-{
-	pinmux_clear_tristate_input_clamping();
-
-	gpio_config_table(e2220_1170_gpio_inits,
-			  ARRAY_SIZE(e2220_1170_gpio_inits));
-
-	pinmux_config_pingrp_table(e2220_1170_pingrps,
-				   ARRAY_SIZE(e2220_1170_pingrps));
-
-	pinmux_config_drvgrp_table(e2220_1170_drvgrps,
-				   ARRAY_SIZE(e2220_1170_drvgrps));
-}

board/nvidia/e2220-1170/pinmux-config-e2220-1170.h

@@ -1,276 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
- */
-
-/*
- * THIS FILE IS AUTO-GENERATED - DO NOT EDIT!
- *
- * To generate this file, use the tegra-pinmux-scripts tool available from
- * https://github.com/NVIDIA/tegra-pinmux-scripts
- * Run "board-to-uboot.py e2220-1170".
- */
-
-#ifndef _PINMUX_CONFIG_E2220_1170_H_
-#define _PINMUX_CONFIG_E2220_1170_H_
-
-#define GPIO_INIT(_port, _gpio, _init)			\
-	{						\
-		.gpio	= TEGRA_GPIO(_port, _gpio),	\
-		.init	= TEGRA_GPIO_INIT_##_init,	\
-	}
-
-static const struct tegra_gpio_config e2220_1170_gpio_inits[] = {
-	/*        port, pin, init_val */
-	GPIO_INIT(A,    5,   IN),
-	GPIO_INIT(A,    6,   IN),
-	GPIO_INIT(B,    4,   IN),
-	GPIO_INIT(E,    6,   IN),
-	GPIO_INIT(G,    2,   OUT0),
-	GPIO_INIT(G,    3,   OUT0),
-	GPIO_INIT(H,    0,   OUT0),
-	GPIO_INIT(H,    1,   OUT0),
-	GPIO_INIT(H,    2,   IN),
-	GPIO_INIT(H,    3,   OUT0),
-	GPIO_INIT(H,    4,   OUT0),
-	GPIO_INIT(H,    5,   IN),
-	GPIO_INIT(H,    6,   OUT0),
-	GPIO_INIT(H,    7,   OUT0),
-	GPIO_INIT(I,    0,   OUT0),
-	GPIO_INIT(I,    1,   IN),
-	GPIO_INIT(I,    2,   OUT0),
-	GPIO_INIT(I,    3,   OUT0),
-	GPIO_INIT(K,    0,   IN),
-	GPIO_INIT(K,    1,   OUT0),
-	GPIO_INIT(K,    2,   OUT0),
-	GPIO_INIT(K,    3,   OUT0),
-	GPIO_INIT(K,    4,   IN),
-	GPIO_INIT(K,    5,   OUT0),
-	GPIO_INIT(K,    6,   IN),
-	GPIO_INIT(K,    7,   OUT0),
-	GPIO_INIT(L,    0,   OUT0),
-	GPIO_INIT(S,    4,   OUT0),
-	GPIO_INIT(S,    5,   OUT0),
-	GPIO_INIT(S,    6,   OUT0),
-	GPIO_INIT(S,    7,   OUT0),
-	GPIO_INIT(T,    0,   OUT0),
-	GPIO_INIT(T,    1,   OUT0),
-	GPIO_INIT(V,    1,   OUT0),
-	GPIO_INIT(V,    2,   OUT0),
-	GPIO_INIT(V,    3,   IN),
-	GPIO_INIT(V,    5,   OUT0),
-	GPIO_INIT(V,    6,   OUT0),
-	GPIO_INIT(X,    0,   IN),
-	GPIO_INIT(X,    1,   IN),
-	GPIO_INIT(X,    2,   IN),
-	GPIO_INIT(X,    3,   IN),
-	GPIO_INIT(X,    4,   IN),
-	GPIO_INIT(X,    5,   IN),
-	GPIO_INIT(X,    6,   IN),
-	GPIO_INIT(X,    7,   IN),
-	GPIO_INIT(Y,    0,   IN),
-	GPIO_INIT(Y,    1,   IN),
-	GPIO_INIT(Z,    0,   IN),
-	GPIO_INIT(Z,    4,   OUT0),
-	GPIO_INIT(BB,   2,   OUT0),
-	GPIO_INIT(BB,   3,   OUT0),
-	GPIO_INIT(BB,   4,   IN),
-	GPIO_INIT(CC,   1,   IN),
-	GPIO_INIT(CC,   5,   OUT0),
-	GPIO_INIT(CC,   6,   IN),
-	GPIO_INIT(CC,   7,   OUT0),
-};
-
-#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv)	\
-	{							\
-		.pingrp		= PMUX_PINGRP_##_pingrp,	\
-		.func		= PMUX_FUNC_##_mux,		\
-		.pull		= PMUX_PULL_##_pull,		\
-		.tristate	= PMUX_TRI_##_tri,		\
-		.io		= PMUX_PIN_##_io,		\
-		.od		= PMUX_PIN_OD_##_od,		\
-		.e_io_hv	= PMUX_PIN_E_IO_HV_##_e_io_hv,	\
-		.lock		= PMUX_PIN_LOCK_DEFAULT,	\
-	}
-
-static const struct pmux_pingrp_config e2220_1170_pingrps[] = {
-	/*     pingrp,               mux,        pull,   tri,      e_input, od,      e_io_hv */
-	PINCFG(PEX_L0_RST_N_PA0,     PE0,        NORMAL, NORMAL,   OUTPUT,  DISABLE, NORMAL),
-	PINCFG(PEX_L0_CLKREQ_N_PA1,  PE0,        UP,     NORMAL,   INPUT,   DISABLE, NORMAL),
-	PINCFG(PEX_WAKE_N_PA2,       PE,         UP,     NORMAL,   INPUT,   DISABLE, NORMAL),
-	PINCFG(PEX_L1_RST_N_PA3,     PE1,        NORMAL, NORMAL,   OUTPUT,  DISABLE, NORMAL),
-	PINCFG(PEX_L1_CLKREQ_N_PA4,  PE1,        UP,     NORMAL,   INPUT,   DISABLE, NORMAL),
-	PINCFG(SATA_LED_ACTIVE_PA5,  DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(PA6,                  DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(DAP1_FS_PB0,          I2S1,       NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(DAP1_DIN_PB1,         I2S1,       NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(DAP1_DOUT_PB2,        I2S1,       NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(DAP1_SCLK_PB3,        I2S1,       NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SPI2_MOSI_PB4,        DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SPI2_MISO_PB5,        RSVD2,      DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(SPI2_SCK_PB6,         RSVD2,      DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(SPI2_CS0_PB7,         RSVD2,      DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(SPI1_MOSI_PC0,        SPI1,       NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(SPI1_MISO_PC1,        SPI1,       NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SPI1_SCK_PC2,         SPI1,       NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(SPI1_CS0_PC3,         SPI1,       NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(SPI1_CS1_PC4,         SPI1,       NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(SPI4_SCK_PC5,         SPI4,       NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(SPI4_CS0_PC6,         SPI4,       NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(SPI4_MOSI_PC7,        SPI4,       NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(SPI4_MISO_PD0,        SPI4,       NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(UART3_TX_PD1,         UARTC,      NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(UART3_RX_PD2,         UARTC,      NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(UART3_RTS_PD3,        UARTC,      NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(UART3_CTS_PD4,        UARTC,      NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(DMIC1_CLK_PE0,        DMIC1,      NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(DMIC1_DAT_PE1,        DMIC1,      NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(DMIC2_CLK_PE2,        DMIC2,      NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(DMIC2_DAT_PE3,        DMIC2,      NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(DMIC3_CLK_PE4,        DMIC3,      NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(DMIC3_DAT_PE5,        DMIC3,      NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(PE6,                  DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(PE7,                  PWM3,       NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(GEN3_I2C_SCL_PF0,     I2C3,       NORMAL, NORMAL,   INPUT,   DISABLE, NORMAL),
-	PINCFG(GEN3_I2C_SDA_PF1,     I2C3,       NORMAL, NORMAL,   INPUT,   DISABLE, NORMAL),
-	PINCFG(UART2_TX_PG0,         UART,       NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(UART2_RX_PG1,         UART,       UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(UART2_RTS_PG2,        DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(UART2_CTS_PG3,        DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(WIFI_EN_PH0,          DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(WIFI_RST_PH1,         DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(WIFI_WAKE_AP_PH2,     DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(AP_WAKE_BT_PH3,       DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(BT_RST_PH4,           DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(BT_WAKE_AP_PH5,       DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(PH6,                  DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(AP_WAKE_NFC_PH7,      DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(NFC_EN_PI0,           DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(NFC_INT_PI1,          DEFAULT,    NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(GPS_EN_PI2,           DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(GPS_RST_PI3,          DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(UART4_TX_PI4,         UARTD,      NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(UART4_RX_PI5,         UARTD,      NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(UART4_RTS_PI6,        UARTD,      NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(UART4_CTS_PI7,        UARTD,      NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(GEN1_I2C_SDA_PJ0,     I2C1,       NORMAL, NORMAL,   INPUT,   DISABLE, NORMAL),
-	PINCFG(GEN1_I2C_SCL_PJ1,     I2C1,       NORMAL, NORMAL,   INPUT,   DISABLE, NORMAL),
-	PINCFG(GEN2_I2C_SCL_PJ2,     I2C2,       NORMAL, NORMAL,   INPUT,   DISABLE, NORMAL),
-	PINCFG(GEN2_I2C_SDA_PJ3,     I2C2,       NORMAL, NORMAL,   INPUT,   DISABLE, NORMAL),
-	PINCFG(DAP4_FS_PJ4,          I2S4B,      NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(DAP4_DIN_PJ5,         I2S4B,      NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(DAP4_DOUT_PJ6,        I2S4B,      NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(DAP4_SCLK_PJ7,        I2S4B,      NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(PK0,                  DEFAULT,    NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(PK1,                  DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(PK2,                  DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(PK3,                  DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(PK4,                  DEFAULT,    NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(PK5,                  DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(PK6,                  DEFAULT,    NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(PK7,                  DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(PL0,                  DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(PL1,                  SOC,        UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SDMMC1_CLK_PM0,       SDMMC1,     NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SDMMC1_CMD_PM1,       SDMMC1,     UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SDMMC1_DAT3_PM2,      SDMMC1,     UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SDMMC1_DAT2_PM3,      SDMMC1,     UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SDMMC1_DAT1_PM4,      SDMMC1,     UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SDMMC1_DAT0_PM5,      SDMMC1,     UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SDMMC3_CLK_PP0,       SDMMC3,     NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SDMMC3_CMD_PP1,       SDMMC3,     UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SDMMC3_DAT3_PP2,      SDMMC3,     UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SDMMC3_DAT2_PP3,      SDMMC3,     UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SDMMC3_DAT1_PP4,      SDMMC3,     UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SDMMC3_DAT0_PP5,      SDMMC3,     UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(CAM1_MCLK_PS0,        EXTPERIPH3, NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(CAM2_MCLK_PS1,        EXTPERIPH3, NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(CAM_I2C_SCL_PS2,      I2CVI,      NORMAL, NORMAL,   INPUT,   DISABLE, NORMAL),
-	PINCFG(CAM_I2C_SDA_PS3,      I2CVI,      NORMAL, NORMAL,   INPUT,   DISABLE, NORMAL),
-	PINCFG(CAM_RST_PS4,          DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(CAM_AF_EN_PS5,        DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(CAM_FLASH_EN_PS6,     DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(CAM1_PWDN_PS7,        DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(CAM2_PWDN_PT0,        DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(CAM1_STROBE_PT1,      DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(UART1_TX_PU0,         UARTA,      NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(UART1_RX_PU1,         UARTA,      UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(UART1_RTS_PU2,        UARTA,      NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(UART1_CTS_PU3,        UARTA,      UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(LCD_BL_PWM_PV0,       PWM0,       NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(LCD_BL_EN_PV1,        DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(LCD_RST_PV2,          DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(LCD_GPIO1_PV3,        DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(LCD_GPIO2_PV4,        PWM1,       NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(AP_READY_PV5,         DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(TOUCH_RST_PV6,        DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(TOUCH_CLK_PV7,        TOUCH,      NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(MODEM_WAKE_AP_PX0,    DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(TOUCH_INT_PX1,        DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(MOTION_INT_PX2,       DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(ALS_PROX_INT_PX3,     DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(TEMP_ALERT_PX4,       DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(BUTTON_POWER_ON_PX5,  DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(BUTTON_VOL_UP_PX6,    DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(BUTTON_VOL_DOWN_PX7,  DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(BUTTON_SLIDE_SW_PY0,  DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(BUTTON_HOME_PY1,      DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(LCD_TE_PY2,           DISPLAYA,   DOWN,   NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(PWR_I2C_SCL_PY3,      I2CPMU,     NORMAL, NORMAL,   INPUT,   DISABLE, NORMAL),
-	PINCFG(PWR_I2C_SDA_PY4,      I2CPMU,     NORMAL, NORMAL,   INPUT,   DISABLE, NORMAL),
-	PINCFG(CLK_32K_OUT_PY5,      SOC,        UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(PZ0,                  DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(PZ1,                  SDMMC1,     UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(PZ2,                  SDMMC3,     UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(PZ3,                  SDMMC3,     UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(PZ4,                  DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(PZ5,                  SOC,        UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(DAP2_FS_PAA0,         I2S2,       NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(DAP2_SCLK_PAA1,       I2S2,       NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(DAP2_DIN_PAA2,        I2S2,       NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(DAP2_DOUT_PAA3,       I2S2,       NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(AUD_MCLK_PBB0,        AUD,        NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(DVFS_PWM_PBB1,        CLDVFS,     NORMAL, TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(DVFS_CLK_PBB2,        DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(GPIO_X1_AUD_PBB3,     DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(GPIO_X3_AUD_PBB4,     DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(HDMI_CEC_PCC0,        CEC,        NORMAL, NORMAL,   INPUT,   DISABLE, HIGH),
-	PINCFG(HDMI_INT_DP_HPD_PCC1, DEFAULT,    DOWN,   NORMAL,   INPUT,   DISABLE, NORMAL),
-	PINCFG(SPDIF_OUT_PCC2,       SPDIF,      NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(SPDIF_IN_PCC3,        SPDIF,      NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(USB_VBUS_EN0_PCC4,    USB,        NORMAL, NORMAL,   INPUT,   DISABLE, HIGH),
-	PINCFG(USB_VBUS_EN1_PCC5,    DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, NORMAL),
-	PINCFG(DP_HPD0_PCC6,         DEFAULT,    DOWN,   NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(PCC7,                 DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, NORMAL),
-	PINCFG(SPI2_CS1_PDD0,        RSVD1,      DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(QSPI_SCK_PEE0,        QSPI,       NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(QSPI_CS_N_PEE1,       QSPI,       NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(QSPI_IO0_PEE2,        QSPI,       NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(QSPI_IO1_PEE3,        QSPI,       NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(QSPI_IO2_PEE4,        QSPI,       NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(QSPI_IO3_PEE5,        QSPI,       NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(CORE_PWR_REQ,         CORE,       NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(CPU_PWR_REQ,          CPU,        NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(PWR_INT_N,            PMI,        UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(CLK_32K_IN,           CLK,        NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(JTAG_RTCK,            JTAG,       NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(CLK_REQ,              SYS,        NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(SHUTDOWN,             SHUTDOWN,   NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-};
-
-#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
-	{						\
-		.drvgrp = PMUX_DRVGRP_##_drvgrp,	\
-		.slwf   = _slwf,			\
-		.slwr   = _slwr,			\
-		.drvup  = _drvup,			\
-		.drvdn  = _drvdn,			\
-		.lpmd   = PMUX_LPMD_##_lpmd,		\
-		.schmt  = PMUX_SCHMT_##_schmt,		\
-		.hsm    = PMUX_HSM_##_hsm,		\
-	}
-
-static const struct pmux_drvgrp_config e2220_1170_drvgrps[] = {
-};
-
-#endif /* PINMUX_CONFIG_E2220_1170_H */

board/nvidia/p2371-0000/p2371-0000.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * (C) Copyright 2013-2015
+ * (C) Copyright 2013-2019
  * NVIDIA Corporation <www.nvidia.com>
  */
 
@@ -9,7 +9,6 @@
 #include <asm/arch/gpio.h>
 #include <asm/arch/pinmux.h>
 #include "../p2571/max77620_init.h"
-#include "pinmux-config-p2371-0000.h"
 
 void pin_mux_mmc(void)
 {
@@ -30,21 +29,3 @@ void pin_mux_mmc(void)
 	if (ret)
 		printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret);
 }
-
-/*
- * Routine: pinmux_init
- * Description: Do individual peripheral pinmux configs
- */
-void pinmux_init(void)
-{
-	pinmux_clear_tristate_input_clamping();
-
-	gpio_config_table(p2371_0000_gpio_inits,
-			  ARRAY_SIZE(p2371_0000_gpio_inits));
-
-	pinmux_config_pingrp_table(p2371_0000_pingrps,
-				   ARRAY_SIZE(p2371_0000_pingrps));
-
-	pinmux_config_drvgrp_table(p2371_0000_drvgrps,
-				   ARRAY_SIZE(p2371_0000_drvgrps));
-}

board/nvidia/p2371-0000/pinmux-config-p2371-0000.h

@@ -1,267 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
- */
-
-/*
- * THIS FILE IS AUTO-GENERATED - DO NOT EDIT!
- *
- * To generate this file, use the tegra-pinmux-scripts tool available from
- * https://github.com/NVIDIA/tegra-pinmux-scripts
- * Run "board-to-uboot.py p2371-0000".
- */
-
-#ifndef _PINMUX_CONFIG_P2371_0000_H_
-#define _PINMUX_CONFIG_P2371_0000_H_
-
-#define GPIO_INIT(_port, _gpio, _init)			\
-	{						\
-		.gpio	= TEGRA_GPIO(_port, _gpio),	\
-		.init	= TEGRA_GPIO_INIT_##_init,	\
-	}
-
-static const struct tegra_gpio_config p2371_0000_gpio_inits[] = {
-	/*        port, pin, init_val */
-	GPIO_INIT(A,    5,   IN),
-	GPIO_INIT(E,    4,   OUT0),
-	GPIO_INIT(E,    6,   IN),
-	GPIO_INIT(G,    0,   IN),
-	GPIO_INIT(G,    3,   OUT0),
-	GPIO_INIT(H,    0,   OUT0),
-	GPIO_INIT(H,    2,   IN),
-	GPIO_INIT(H,    3,   OUT0),
-	GPIO_INIT(H,    4,   OUT0),
-	GPIO_INIT(H,    5,   IN),
-	GPIO_INIT(H,    6,   OUT0),
-	GPIO_INIT(H,    7,   OUT0),
-	GPIO_INIT(I,    0,   OUT0),
-	GPIO_INIT(I,    1,   IN),
-	GPIO_INIT(I,    2,   OUT0),
-	GPIO_INIT(I,    3,   OUT0),
-	GPIO_INIT(K,    4,   IN),
-	GPIO_INIT(K,    5,   OUT0),
-	GPIO_INIT(K,    6,   IN),
-	GPIO_INIT(K,    7,   OUT0),
-	GPIO_INIT(L,    0,   OUT0),
-	GPIO_INIT(S,    4,   OUT0),
-	GPIO_INIT(S,    5,   OUT0),
-	GPIO_INIT(S,    6,   OUT0),
-	GPIO_INIT(S,    7,   OUT0),
-	GPIO_INIT(T,    0,   OUT0),
-	GPIO_INIT(T,    1,   OUT0),
-	GPIO_INIT(V,    1,   OUT0),
-	GPIO_INIT(V,    2,   OUT0),
-	GPIO_INIT(V,    5,   OUT0),
-	GPIO_INIT(V,    6,   OUT0),
-	GPIO_INIT(V,    7,   OUT1),
-	GPIO_INIT(X,    0,   IN),
-	GPIO_INIT(X,    1,   IN),
-	GPIO_INIT(X,    2,   IN),
-	GPIO_INIT(X,    3,   IN),
-	GPIO_INIT(X,    4,   IN),
-	GPIO_INIT(X,    5,   IN),
-	GPIO_INIT(X,    6,   IN),
-	GPIO_INIT(X,    7,   IN),
-	GPIO_INIT(Y,    1,   IN),
-	GPIO_INIT(Z,    0,   IN),
-	GPIO_INIT(Z,    4,   OUT0),
-	GPIO_INIT(BB,   2,   OUT0),
-	GPIO_INIT(BB,   3,   OUT0),
-	GPIO_INIT(CC,   1,   IN),
-	GPIO_INIT(CC,   6,   IN),
-	GPIO_INIT(CC,   7,   OUT0),
-};
-
-#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv)	\
-	{							\
-		.pingrp		= PMUX_PINGRP_##_pingrp,	\
-		.func		= PMUX_FUNC_##_mux,		\
-		.pull		= PMUX_PULL_##_pull,		\
-		.tristate	= PMUX_TRI_##_tri,		\
-		.io		= PMUX_PIN_##_io,		\
-		.od		= PMUX_PIN_OD_##_od,		\
-		.e_io_hv	= PMUX_PIN_E_IO_HV_##_e_io_hv,	\
-		.lock		= PMUX_PIN_LOCK_DEFAULT,	\
-	}
-
-static const struct pmux_pingrp_config p2371_0000_pingrps[] = {
-	/*     pingrp,               mux,        pull,   tri,      e_input, od,      e_io_hv */
-	PINCFG(PEX_L0_RST_N_PA0,     PE0,        NORMAL, NORMAL,   OUTPUT,  DISABLE, HIGH),
-	PINCFG(PEX_L0_CLKREQ_N_PA1,  PE0,        NORMAL, NORMAL,   INPUT,   DISABLE, HIGH),
-	PINCFG(PEX_WAKE_N_PA2,       PE,         NORMAL, NORMAL,   INPUT,   DISABLE, HIGH),
-	PINCFG(PEX_L1_RST_N_PA3,     PE1,        NORMAL, NORMAL,   OUTPUT,  DISABLE, HIGH),
-	PINCFG(PEX_L1_CLKREQ_N_PA4,  PE1,        NORMAL, NORMAL,   INPUT,   DISABLE, HIGH),
-	PINCFG(SATA_LED_ACTIVE_PA5,  DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(PA6,                  RSVD1,      DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(DAP1_FS_PB0,          I2S1,       NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(DAP1_DIN_PB1,         I2S1,       NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(DAP1_DOUT_PB2,        I2S1,       NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(DAP1_SCLK_PB3,        I2S1,       NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SPI2_MOSI_PB4,        RSVD2,      DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(SPI2_MISO_PB5,        RSVD2,      DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(SPI2_SCK_PB6,         RSVD2,      DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(SPI2_CS0_PB7,         RSVD2,      DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(SPI1_MOSI_PC0,        SPI1,       DOWN,   NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SPI1_MISO_PC1,        SPI1,       DOWN,   NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SPI1_SCK_PC2,         SPI1,       DOWN,   NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SPI1_CS0_PC3,         SPI1,       UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SPI1_CS1_PC4,         SPI1,       UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SPI4_SCK_PC5,         SPI4,       NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(SPI4_CS0_PC6,         SPI4,       NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(SPI4_MOSI_PC7,        SPI4,       NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(SPI4_MISO_PD0,        SPI4,       NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(UART3_TX_PD1,         UARTC,      NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(UART3_RX_PD2,         UARTC,      UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(UART3_RTS_PD3,        UARTC,      NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(UART3_CTS_PD4,        UARTC,      UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(DMIC1_CLK_PE0,        DMIC1,      NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(DMIC1_DAT_PE1,        DMIC1,      DOWN,   NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(DMIC2_CLK_PE2,        DMIC2,      NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(DMIC2_DAT_PE3,        DMIC2,      DOWN,   NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(DMIC3_CLK_PE4,        DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(DMIC3_DAT_PE5,        RSVD2,      DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(PE6,                  DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(PE7,                  PWM3,       NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(GEN3_I2C_SCL_PF0,     I2C3,       NORMAL, NORMAL,   INPUT,   DISABLE, NORMAL),
-	PINCFG(GEN3_I2C_SDA_PF1,     I2C3,       NORMAL, NORMAL,   INPUT,   DISABLE, NORMAL),
-	PINCFG(UART2_TX_PG0,         DEFAULT,    NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(UART2_RX_PG1,         UARTB,      DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(UART2_RTS_PG2,        RSVD2,      DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(UART2_CTS_PG3,        DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(WIFI_EN_PH0,          DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(WIFI_RST_PH1,         RSVD0,      DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(WIFI_WAKE_AP_PH2,     DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(AP_WAKE_BT_PH3,       DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(BT_RST_PH4,           DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(BT_WAKE_AP_PH5,       DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(PH6,                  DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(AP_WAKE_NFC_PH7,      DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(NFC_EN_PI0,           DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(NFC_INT_PI1,          DEFAULT,    NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(GPS_EN_PI2,           DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(GPS_RST_PI3,          DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(UART4_TX_PI4,         UARTD,      NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(UART4_RX_PI5,         UARTD,      NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(UART4_RTS_PI6,        UARTD,      NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(UART4_CTS_PI7,        UARTD,      NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(GEN1_I2C_SDA_PJ0,     I2C1,       NORMAL, NORMAL,   INPUT,   DISABLE, NORMAL),
-	PINCFG(GEN1_I2C_SCL_PJ1,     I2C1,       NORMAL, NORMAL,   INPUT,   DISABLE, NORMAL),
-	PINCFG(GEN2_I2C_SCL_PJ2,     I2C2,       NORMAL, NORMAL,   INPUT,   DISABLE, HIGH),
-	PINCFG(GEN2_I2C_SDA_PJ3,     I2C2,       NORMAL, NORMAL,   INPUT,   DISABLE, HIGH),
-	PINCFG(DAP4_FS_PJ4,          I2S4B,      NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(DAP4_DIN_PJ5,         I2S4B,      NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(DAP4_DOUT_PJ6,        I2S4B,      NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(DAP4_SCLK_PJ7,        I2S4B,      NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(PK0,                  I2S5B,      UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(PK1,                  I2S5B,      UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(PK2,                  I2S5B,      UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(PK3,                  I2S5B,      UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(PK4,                  DEFAULT,    NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(PK5,                  DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(PK6,                  DEFAULT,    NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(PK7,                  DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(PL0,                  DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(PL1,                  SOC,        UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SDMMC1_CLK_PM0,       SDMMC1,     NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SDMMC1_CMD_PM1,       SDMMC1,     UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SDMMC1_DAT3_PM2,      SDMMC1,     UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SDMMC1_DAT2_PM3,      SDMMC1,     UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SDMMC1_DAT1_PM4,      SDMMC1,     UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SDMMC1_DAT0_PM5,      SDMMC1,     UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SDMMC3_CLK_PP0,       SDMMC3,     NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SDMMC3_CMD_PP1,       SDMMC3,     UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SDMMC3_DAT3_PP2,      SDMMC3,     UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SDMMC3_DAT2_PP3,      SDMMC3,     UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SDMMC3_DAT1_PP4,      SDMMC3,     UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SDMMC3_DAT0_PP5,      SDMMC3,     UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(CAM1_MCLK_PS0,        EXTPERIPH3, NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(CAM2_MCLK_PS1,        EXTPERIPH3, NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(CAM_I2C_SCL_PS2,      I2CVI,      NORMAL, NORMAL,   INPUT,   DISABLE, NORMAL),
-	PINCFG(CAM_I2C_SDA_PS3,      I2CVI,      NORMAL, NORMAL,   INPUT,   DISABLE, NORMAL),
-	PINCFG(CAM_RST_PS4,          DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(CAM_AF_EN_PS5,        DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(CAM_FLASH_EN_PS6,     DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(CAM1_PWDN_PS7,        DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(CAM2_PWDN_PT0,        DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(CAM1_STROBE_PT1,      DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(UART1_TX_PU0,         UARTA,      NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(UART1_RX_PU1,         UARTA,      UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(UART1_RTS_PU2,        UARTA,      NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(UART1_CTS_PU3,        UARTA,      UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(LCD_BL_PWM_PV0,       PWM0,       NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(LCD_BL_EN_PV1,        DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(LCD_RST_PV2,          DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(LCD_GPIO1_PV3,        RSVD1,      DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(LCD_GPIO2_PV4,        PWM1,       NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(AP_READY_PV5,         DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(TOUCH_RST_PV6,        DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(TOUCH_CLK_PV7,        DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(MODEM_WAKE_AP_PX0,    DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(TOUCH_INT_PX1,        DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(MOTION_INT_PX2,       DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(ALS_PROX_INT_PX3,     DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(TEMP_ALERT_PX4,       DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(BUTTON_POWER_ON_PX5,  DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(BUTTON_VOL_UP_PX6,    DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(BUTTON_VOL_DOWN_PX7,  DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(BUTTON_SLIDE_SW_PY0,  RSVD0,      DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(BUTTON_HOME_PY1,      DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(LCD_TE_PY2,           DISPLAYA,   DOWN,   NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(PWR_I2C_SCL_PY3,      I2CPMU,     NORMAL, NORMAL,   INPUT,   DISABLE, NORMAL),
-	PINCFG(PWR_I2C_SDA_PY4,      I2CPMU,     NORMAL, NORMAL,   INPUT,   DISABLE, NORMAL),
-	PINCFG(CLK_32K_OUT_PY5,      SOC,        UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(PZ0,                  DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(PZ1,                  SDMMC1,     UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(PZ2,                  RSVD2,      DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(PZ3,                  RSVD1,      DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(PZ4,                  DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(PZ5,                  SOC,        UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(DAP2_FS_PAA0,         I2S2,       NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(DAP2_SCLK_PAA1,       I2S2,       NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(DAP2_DIN_PAA2,        I2S2,       NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(DAP2_DOUT_PAA3,       I2S2,       NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(AUD_MCLK_PBB0,        AUD,        NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(DVFS_PWM_PBB1,        CLDVFS,     NORMAL, TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(DVFS_CLK_PBB2,        DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(GPIO_X1_AUD_PBB3,     DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(GPIO_X3_AUD_PBB4,     RSVD0,      DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(HDMI_CEC_PCC0,        CEC,        NORMAL, NORMAL,   INPUT,   DISABLE, HIGH),
-	PINCFG(HDMI_INT_DP_HPD_PCC1, DEFAULT,    DOWN,   NORMAL,   INPUT,   DISABLE, NORMAL),
-	PINCFG(SPDIF_OUT_PCC2,       RSVD1,      DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(SPDIF_IN_PCC3,        RSVD1,      DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(USB_VBUS_EN0_PCC4,    USB,        NORMAL, NORMAL,   INPUT,   DISABLE, HIGH),
-	PINCFG(USB_VBUS_EN1_PCC5,    RSVD1,      DOWN,   TRISTATE, OUTPUT,  DISABLE, NORMAL),
-	PINCFG(DP_HPD0_PCC6,         DEFAULT,    DOWN,   NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(PCC7,                 DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, NORMAL),
-	PINCFG(SPI2_CS1_PDD0,        RSVD1,      DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(QSPI_SCK_PEE0,        RSVD1,      DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(QSPI_CS_N_PEE1,       RSVD1,      DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(QSPI_IO0_PEE2,        RSVD1,      DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(QSPI_IO1_PEE3,        RSVD1,      DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(QSPI_IO2_PEE4,        RSVD1,      DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(QSPI_IO3_PEE5,        RSVD1,      DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(CORE_PWR_REQ,         CORE,       NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(CPU_PWR_REQ,          CPU,        NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(PWR_INT_N,            PMI,        UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(CLK_32K_IN,           CLK,        NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(JTAG_RTCK,            JTAG,       NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(CLK_REQ,              SYS,        NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(SHUTDOWN,             SHUTDOWN,   NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-};
-
-#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
-	{						\
-		.drvgrp = PMUX_DRVGRP_##_drvgrp,	\
-		.slwf   = _slwf,			\
-		.slwr   = _slwr,			\
-		.drvup  = _drvup,			\
-		.drvdn  = _drvdn,			\
-		.lpmd   = PMUX_LPMD_##_lpmd,		\
-		.schmt  = PMUX_SCHMT_##_schmt,		\
-		.hsm    = PMUX_HSM_##_hsm,		\
-	}
-
-static const struct pmux_drvgrp_config p2371_0000_drvgrps[] = {
-};
-
-#endif /* PINMUX_CONFIG_P2371_0000_H */

board/nvidia/p2371-2180/p2371-2180.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * (C) Copyright 2013-2015
+ * (C) Copyright 2013-2019
  * NVIDIA Corporation <www.nvidia.com>
  */
 
@@ -13,7 +13,6 @@
 #include <asm/arch/pinmux.h>
 #include <asm/arch-tegra/cboot.h>
 #include "../p2571/max77620_init.h"
-#include "pinmux-config-p2371-2180.h"
 
 void pin_mux_mmc(void)
 {
@@ -57,24 +56,6 @@ void pin_mux_mmc(void)
 	}
 }
 
-/*
- * Routine: pinmux_init
- * Description: Do individual peripheral pinmux configs
- */
-void pinmux_init(void)
-{
-	pinmux_clear_tristate_input_clamping();
-
-	gpio_config_table(p2371_2180_gpio_inits,
-			  ARRAY_SIZE(p2371_2180_gpio_inits));
-
-	pinmux_config_pingrp_table(p2371_2180_pingrps,
-				   ARRAY_SIZE(p2371_2180_pingrps));
-
-	pinmux_config_drvgrp_table(p2371_2180_drvgrps,
-				   ARRAY_SIZE(p2371_2180_drvgrps));
-}
-
 #ifdef CONFIG_PCI_TEGRA
 int tegra_pcie_board_init(void)
 {

board/nvidia/p2371-2180/pinmux-config-p2371-2180.h

@@ -1,278 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
- */
-
-/*
- * THIS FILE IS AUTO-GENERATED - DO NOT EDIT!
- *
- * To generate this file, use the tegra-pinmux-scripts tool available from
- * https://github.com/NVIDIA/tegra-pinmux-scripts
- * Run "board-to-uboot.py p2371-2180".
- */
-
-#ifndef _PINMUX_CONFIG_P2371_2180_H_
-#define _PINMUX_CONFIG_P2371_2180_H_
-
-#define GPIO_INIT(_port, _gpio, _init)			\
-	{						\
-		.gpio	= TEGRA_GPIO(_port, _gpio),	\
-		.init	= TEGRA_GPIO_INIT_##_init,	\
-	}
-
-static const struct tegra_gpio_config p2371_2180_gpio_inits[] = {
-	/*        port, pin, init_val */
-	GPIO_INIT(A,    5,   IN),
-	GPIO_INIT(B,    0,   IN),
-	GPIO_INIT(B,    1,   IN),
-	GPIO_INIT(B,    2,   IN),
-	GPIO_INIT(B,    3,   IN),
-	GPIO_INIT(C,    0,   IN),
-	GPIO_INIT(C,    1,   IN),
-	GPIO_INIT(C,    2,   IN),
-	GPIO_INIT(C,    3,   IN),
-	GPIO_INIT(C,    4,   IN),
-	GPIO_INIT(E,    4,   IN),
-	GPIO_INIT(E,    5,   IN),
-	GPIO_INIT(E,    6,   IN),
-	GPIO_INIT(H,    0,   OUT0),
-	GPIO_INIT(H,    1,   OUT0),
-	GPIO_INIT(H,    2,   IN),
-	GPIO_INIT(H,    3,   OUT0),
-	GPIO_INIT(H,    4,   OUT0),
-	GPIO_INIT(H,    5,   IN),
-	GPIO_INIT(H,    6,   IN),
-	GPIO_INIT(H,    7,   IN),
-	GPIO_INIT(I,    0,   OUT0),
-	GPIO_INIT(I,    1,   IN),
-	GPIO_INIT(I,    2,   OUT0),
-	GPIO_INIT(K,    4,   IN),
-	GPIO_INIT(K,    5,   OUT0),
-	GPIO_INIT(K,    6,   IN),
-	GPIO_INIT(K,    7,   IN),
-	GPIO_INIT(L,    1,   IN),
-	GPIO_INIT(S,    4,   OUT0),
-	GPIO_INIT(S,    5,   OUT0),
-	GPIO_INIT(S,    6,   OUT0),
-	GPIO_INIT(S,    7,   OUT0),
-	GPIO_INIT(T,    0,   OUT0),
-	GPIO_INIT(T,    1,   OUT0),
-	GPIO_INIT(U,    2,   IN),
-	GPIO_INIT(U,    3,   IN),
-	GPIO_INIT(V,    1,   OUT0),
-	GPIO_INIT(V,    2,   OUT0),
-	GPIO_INIT(V,    3,   IN),
-	GPIO_INIT(V,    5,   OUT0),
-	GPIO_INIT(V,    6,   OUT0),
-	GPIO_INIT(X,    0,   IN),
-	GPIO_INIT(X,    1,   IN),
-	GPIO_INIT(X,    2,   IN),
-	GPIO_INIT(X,    3,   IN),
-	GPIO_INIT(X,    4,   IN),
-	GPIO_INIT(X,    5,   IN),
-	GPIO_INIT(X,    6,   IN),
-	GPIO_INIT(X,    7,   IN),
-	GPIO_INIT(Y,    0,   IN),
-	GPIO_INIT(Y,    1,   IN),
-	GPIO_INIT(Z,    0,   IN),
-	GPIO_INIT(Z,    2,   IN),
-	GPIO_INIT(Z,    3,   OUT0),
-	GPIO_INIT(BB,   0,   IN),
-	GPIO_INIT(BB,   2,   OUT0),
-	GPIO_INIT(BB,   3,   IN),
-	GPIO_INIT(CC,   1,   IN),
-};
-
-#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv)	\
-	{							\
-		.pingrp		= PMUX_PINGRP_##_pingrp,	\
-		.func		= PMUX_FUNC_##_mux,		\
-		.pull		= PMUX_PULL_##_pull,		\
-		.tristate	= PMUX_TRI_##_tri,		\
-		.io		= PMUX_PIN_##_io,		\
-		.od		= PMUX_PIN_OD_##_od,		\
-		.e_io_hv	= PMUX_PIN_E_IO_HV_##_e_io_hv,	\
-		.lock		= PMUX_PIN_LOCK_DEFAULT,	\
-	}
-
-static const struct pmux_pingrp_config p2371_2180_pingrps[] = {
-	/*     pingrp,               mux,        pull,   tri,      e_input, od,      e_io_hv */
-	PINCFG(PEX_L0_RST_N_PA0,     PE0,        NORMAL, NORMAL,   OUTPUT,  DISABLE, HIGH),
-	PINCFG(PEX_L0_CLKREQ_N_PA1,  PE0,        NORMAL, NORMAL,   INPUT,   DISABLE, HIGH),
-	PINCFG(PEX_WAKE_N_PA2,       PE,         NORMAL, NORMAL,   INPUT,   DISABLE, HIGH),
-	PINCFG(PEX_L1_RST_N_PA3,     PE1,        NORMAL, NORMAL,   OUTPUT,  DISABLE, HIGH),
-	PINCFG(PEX_L1_CLKREQ_N_PA4,  PE1,        NORMAL, NORMAL,   INPUT,   DISABLE, HIGH),
-	PINCFG(SATA_LED_ACTIVE_PA5,  DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(PA6,                  SATA,       NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(DAP1_FS_PB0,          DEFAULT,    DOWN,   NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(DAP1_DIN_PB1,         DEFAULT,    DOWN,   NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(DAP1_DOUT_PB2,        DEFAULT,    DOWN,   NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(DAP1_SCLK_PB3,        DEFAULT,    DOWN,   NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SPI2_MOSI_PB4,        SPI2,       NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SPI2_MISO_PB5,        SPI2,       NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SPI2_SCK_PB6,         SPI2,       NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SPI2_CS0_PB7,         SPI2,       UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SPI1_MOSI_PC0,        DEFAULT,    DOWN,   NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SPI1_MISO_PC1,        DEFAULT,    DOWN,   NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SPI1_SCK_PC2,         DEFAULT,    DOWN,   NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SPI1_CS0_PC3,         DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SPI1_CS1_PC4,         DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SPI4_SCK_PC5,         SPI4,       DOWN,   NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SPI4_CS0_PC6,         SPI4,       UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SPI4_MOSI_PC7,        SPI4,       DOWN,   NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SPI4_MISO_PD0,        SPI4,       DOWN,   NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(UART3_TX_PD1,         UARTC,      NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(UART3_RX_PD2,         UARTC,      UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(UART3_RTS_PD3,        UARTC,      NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(UART3_CTS_PD4,        UARTC,      UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(DMIC1_CLK_PE0,        I2S3,       NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(DMIC1_DAT_PE1,        I2S3,       NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(DMIC2_CLK_PE2,        I2S3,       NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(DMIC2_DAT_PE3,        I2S3,       NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(DMIC3_CLK_PE4,        DEFAULT,    DOWN,   NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(DMIC3_DAT_PE5,        DEFAULT,    DOWN,   NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(PE6,                  DEFAULT,    DOWN,   NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(PE7,                  PWM3,       NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(GEN3_I2C_SCL_PF0,     I2C3,       NORMAL, NORMAL,   INPUT,   DISABLE, NORMAL),
-	PINCFG(GEN3_I2C_SDA_PF1,     I2C3,       NORMAL, NORMAL,   INPUT,   DISABLE, NORMAL),
-	PINCFG(UART2_TX_PG0,         UARTB,      NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(UART2_RX_PG1,         UARTB,      UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(UART2_RTS_PG2,        UARTB,      NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(UART2_CTS_PG3,        UARTB,      UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(WIFI_EN_PH0,          DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(WIFI_RST_PH1,         DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(WIFI_WAKE_AP_PH2,     DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(AP_WAKE_BT_PH3,       DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(BT_RST_PH4,           DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(BT_WAKE_AP_PH5,       DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(PH6,                  DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(AP_WAKE_NFC_PH7,      DEFAULT,    DOWN,   NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(NFC_EN_PI0,           DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(NFC_INT_PI1,          DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(GPS_EN_PI2,           DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(GPS_RST_PI3,          RSVD0,      DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(UART4_TX_PI4,         UARTD,      NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(UART4_RX_PI5,         UARTD,      NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(UART4_RTS_PI6,        UARTD,      NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(UART4_CTS_PI7,        UARTD,      NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(GEN1_I2C_SDA_PJ0,     I2C1,       NORMAL, NORMAL,   INPUT,   DISABLE, NORMAL),
-	PINCFG(GEN1_I2C_SCL_PJ1,     I2C1,       NORMAL, NORMAL,   INPUT,   DISABLE, NORMAL),
-	PINCFG(GEN2_I2C_SCL_PJ2,     I2C2,       NORMAL, NORMAL,   INPUT,   DISABLE, HIGH),
-	PINCFG(GEN2_I2C_SDA_PJ3,     I2C2,       NORMAL, NORMAL,   INPUT,   DISABLE, HIGH),
-	PINCFG(DAP4_FS_PJ4,          I2S4B,      NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(DAP4_DIN_PJ5,         I2S4B,      NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(DAP4_DOUT_PJ6,        I2S4B,      NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(DAP4_SCLK_PJ7,        I2S4B,      NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(PK0,                  I2S5B,      NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(PK1,                  I2S5B,      NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(PK2,                  I2S5B,      NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(PK3,                  I2S5B,      NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(PK4,                  DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(PK5,                  DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(PK6,                  DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(PK7,                  DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(PL0,                  RSVD0,      DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(PL1,                  DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SDMMC1_CLK_PM0,       SDMMC1,     NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SDMMC1_CMD_PM1,       SDMMC1,     UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SDMMC1_DAT3_PM2,      SDMMC1,     UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SDMMC1_DAT2_PM3,      SDMMC1,     UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SDMMC1_DAT1_PM4,      SDMMC1,     UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SDMMC1_DAT0_PM5,      SDMMC1,     UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SDMMC3_CLK_PP0,       SDMMC3,     NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SDMMC3_CMD_PP1,       SDMMC3,     UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SDMMC3_DAT3_PP2,      SDMMC3,     UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SDMMC3_DAT2_PP3,      SDMMC3,     UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SDMMC3_DAT1_PP4,      SDMMC3,     UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SDMMC3_DAT0_PP5,      SDMMC3,     UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(CAM1_MCLK_PS0,        EXTPERIPH3, NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(CAM2_MCLK_PS1,        EXTPERIPH3, NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(CAM_I2C_SCL_PS2,      I2CVI,      NORMAL, NORMAL,   INPUT,   DISABLE, NORMAL),
-	PINCFG(CAM_I2C_SDA_PS3,      I2CVI,      NORMAL, NORMAL,   INPUT,   DISABLE, NORMAL),
-	PINCFG(CAM_RST_PS4,          DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(CAM_AF_EN_PS5,        DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(CAM_FLASH_EN_PS6,     DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(CAM1_PWDN_PS7,        DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(CAM2_PWDN_PT0,        DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(CAM1_STROBE_PT1,      DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(UART1_TX_PU0,         UARTA,      NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(UART1_RX_PU1,         UARTA,      UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(UART1_RTS_PU2,        DEFAULT,    DOWN,   NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(UART1_CTS_PU3,        DEFAULT,    DOWN,   NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(LCD_BL_PWM_PV0,       PWM0,       NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(LCD_BL_EN_PV1,        DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(LCD_RST_PV2,          DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(LCD_GPIO1_PV3,        DEFAULT,    NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(LCD_GPIO2_PV4,        PWM1,       NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(AP_READY_PV5,         DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(TOUCH_RST_PV6,        DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(TOUCH_CLK_PV7,        TOUCH,      NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(MODEM_WAKE_AP_PX0,    DEFAULT,    DOWN,   NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(TOUCH_INT_PX1,        DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(MOTION_INT_PX2,       DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(ALS_PROX_INT_PX3,     DEFAULT,    DOWN,   NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(TEMP_ALERT_PX4,       DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(BUTTON_POWER_ON_PX5,  DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(BUTTON_VOL_UP_PX6,    DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(BUTTON_VOL_DOWN_PX7,  DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(BUTTON_SLIDE_SW_PY0,  DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(BUTTON_HOME_PY1,      DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(LCD_TE_PY2,           DISPLAYA,   DOWN,   NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(PWR_I2C_SCL_PY3,      I2CPMU,     NORMAL, NORMAL,   INPUT,   DISABLE, NORMAL),
-	PINCFG(PWR_I2C_SDA_PY4,      I2CPMU,     NORMAL, NORMAL,   INPUT,   DISABLE, NORMAL),
-	PINCFG(CLK_32K_OUT_PY5,      SOC,        UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(PZ0,                  DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(PZ1,                  SDMMC1,     UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(PZ2,                  DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(PZ3,                  DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(PZ4,                  SDMMC1,     UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(PZ5,                  SOC,        UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(DAP2_FS_PAA0,         I2S2,       NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(DAP2_SCLK_PAA1,       I2S2,       NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(DAP2_DIN_PAA2,        I2S2,       NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(DAP2_DOUT_PAA3,       I2S2,       NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(AUD_MCLK_PBB0,        DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(DVFS_PWM_PBB1,        CLDVFS,     NORMAL, TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(DVFS_CLK_PBB2,        DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(GPIO_X1_AUD_PBB3,     DEFAULT,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(GPIO_X3_AUD_PBB4,     RSVD0,      DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(HDMI_CEC_PCC0,        CEC,        NORMAL, NORMAL,   INPUT,   DISABLE, HIGH),
-	PINCFG(HDMI_INT_DP_HPD_PCC1, DEFAULT,    DOWN,   NORMAL,   INPUT,   DISABLE, NORMAL),
-	PINCFG(SPDIF_OUT_PCC2,       RSVD1,      DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(SPDIF_IN_PCC3,        RSVD1,      DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(USB_VBUS_EN0_PCC4,    USB,        NORMAL, NORMAL,   INPUT,   DISABLE, HIGH),
-	PINCFG(USB_VBUS_EN1_PCC5,    USB,        NORMAL, NORMAL,   INPUT,   DISABLE, HIGH),
-	PINCFG(DP_HPD0_PCC6,         DP,         DOWN,   NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(PCC7,                 RSVD0,      DOWN,   TRISTATE, OUTPUT,  DISABLE, NORMAL),
-	PINCFG(SPI2_CS1_PDD0,        SPI2,       UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(QSPI_SCK_PEE0,        RSVD1,      DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(QSPI_CS_N_PEE1,       RSVD1,      DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(QSPI_IO0_PEE2,        RSVD1,      DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(QSPI_IO1_PEE3,        RSVD1,      DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(QSPI_IO2_PEE4,        RSVD1,      DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(QSPI_IO3_PEE5,        RSVD1,      DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(CORE_PWR_REQ,         CORE,       NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(CPU_PWR_REQ,          CPU,        NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(PWR_INT_N,            PMI,        UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(CLK_32K_IN,           CLK,        NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(JTAG_RTCK,            JTAG,       NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(CLK_REQ,              RSVD1,      DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(SHUTDOWN,             SHUTDOWN,   NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-};
-
-#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
-	{						\
-		.drvgrp = PMUX_DRVGRP_##_drvgrp,	\
-		.slwf   = _slwf,			\
-		.slwr   = _slwr,			\
-		.drvup  = _drvup,			\
-		.drvdn  = _drvdn,			\
-		.lpmd   = PMUX_LPMD_##_lpmd,		\
-		.schmt  = PMUX_SCHMT_##_schmt,		\
-		.hsm    = PMUX_HSM_##_hsm,		\
-	}
-
-static const struct pmux_drvgrp_config p2371_2180_drvgrps[] = {
-};
-
-#endif /* PINMUX_CONFIG_P2371_2180_H */

board/nvidia/p2571/p2571.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * (C) Copyright 2013-2015
+ * (C) Copyright 2013-2019
  * NVIDIA Corporation <www.nvidia.com>
  */
 
@@ -10,7 +10,6 @@
 #include <asm/arch/pinmux.h>
 #include <asm/gpio.h>
 #include "max77620_init.h"
-#include "pinmux-config-p2571.h"
 
 void pin_mux_mmc(void)
 {
@@ -32,24 +31,6 @@ void pin_mux_mmc(void)
 		printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret);
 }
 
-/*
- * Routine: pinmux_init
- * Description: Do individual peripheral pinmux configs
- */
-void pinmux_init(void)
-{
-	pinmux_clear_tristate_input_clamping();
-
-	gpio_config_table(p2571_gpio_inits,
-			  ARRAY_SIZE(p2571_gpio_inits));
-
-	pinmux_config_pingrp_table(p2571_pingrps,
-				   ARRAY_SIZE(p2571_pingrps));
-
-	pinmux_config_drvgrp_table(p2571_drvgrps,
-				   ARRAY_SIZE(p2571_drvgrps));
-}
-
 /*
  * Routine: start_cpu_fan
  * Description: Enable/start PWM CPU fan on P2571

board/nvidia/p2571/pinmux-config-p2571.h

@@ -1,242 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
- */
-
-/*
- * THIS FILE IS AUTO-GENERATED - DO NOT EDIT!
- *
- * To generate this file, use the tegra-pinmux-scripts tool available from
- * https://github.com/NVIDIA/tegra-pinmux-scripts
- * Run "board-to-uboot.py p2571".
- */
-
-#ifndef _PINMUX_CONFIG_P2571_H_
-#define _PINMUX_CONFIG_P2571_H_
-
-#define GPIO_INIT(_port, _gpio, _init)			\
-	{						\
-		.gpio	= TEGRA_GPIO(_port, _gpio),	\
-		.init	= TEGRA_GPIO_INIT_##_init,	\
-	}
-
-static const struct tegra_gpio_config p2571_gpio_inits[] = {
-	/*        port, pin, init_val */
-	GPIO_INIT(A,    0,   IN),
-	GPIO_INIT(A,    5,   IN),
-	GPIO_INIT(D,    4,   IN),
-	GPIO_INIT(E,    4,   OUT0),
-	GPIO_INIT(G,    0,   IN),
-	GPIO_INIT(H,    0,   OUT0),
-	GPIO_INIT(H,    2,   IN),
-	GPIO_INIT(H,    3,   OUT0),
-	GPIO_INIT(H,    4,   OUT0),
-	GPIO_INIT(H,    5,   IN),
-	GPIO_INIT(I,    0,   OUT0),
-	GPIO_INIT(I,    1,   IN),
-	GPIO_INIT(V,    1,   OUT0),
-	GPIO_INIT(V,    6,   OUT1),
-	GPIO_INIT(X,    4,   IN),
-	GPIO_INIT(X,    6,   IN),
-	GPIO_INIT(X,    7,   IN),
-	GPIO_INIT(Y,    1,   IN),
-	GPIO_INIT(Z,    0,   IN),
-	GPIO_INIT(Z,    4,   OUT0),
-	GPIO_INIT(BB,   2,   OUT0),
-	GPIO_INIT(CC,   1,   IN),
-	GPIO_INIT(CC,   3,   IN),
-};
-
-#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv)	\
-	{							\
-		.pingrp		= PMUX_PINGRP_##_pingrp,	\
-		.func		= PMUX_FUNC_##_mux,		\
-		.pull		= PMUX_PULL_##_pull,		\
-		.tristate	= PMUX_TRI_##_tri,		\
-		.io		= PMUX_PIN_##_io,		\
-		.od		= PMUX_PIN_OD_##_od,		\
-		.e_io_hv	= PMUX_PIN_E_IO_HV_##_e_io_hv,	\
-		.lock		= PMUX_PIN_LOCK_DEFAULT,	\
-	}
-
-static const struct pmux_pingrp_config p2571_pingrps[] = {
-	/*     pingrp,               mux,      pull,   tri,      e_input, od,      e_io_hv */
-	PINCFG(PEX_L0_RST_N_PA0,     DEFAULT,  UP,     NORMAL,   INPUT,   DISABLE, NORMAL),
-	PINCFG(PEX_L0_CLKREQ_N_PA1,  RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, NORMAL),
-	PINCFG(PEX_WAKE_N_PA2,       RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, NORMAL),
-	PINCFG(PEX_L1_RST_N_PA3,     RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, NORMAL),
-	PINCFG(PEX_L1_CLKREQ_N_PA4,  RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, NORMAL),
-	PINCFG(SATA_LED_ACTIVE_PA5,  DEFAULT,  UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(PA6,                  RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(DAP1_FS_PB0,          RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(DAP1_DIN_PB1,         RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(DAP1_DOUT_PB2,        RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(DAP1_SCLK_PB3,        RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(SPI2_MOSI_PB4,        RSVD2,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(SPI2_MISO_PB5,        RSVD2,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(SPI2_SCK_PB6,         RSVD2,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(SPI2_CS0_PB7,         RSVD2,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(SPI1_MOSI_PC0,        RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(SPI1_MISO_PC1,        RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(SPI1_SCK_PC2,         RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(SPI1_CS0_PC3,         RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(SPI1_CS1_PC4,         RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(SPI4_SCK_PC5,         RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(SPI4_CS0_PC6,         RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(SPI4_MOSI_PC7,        RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(SPI4_MISO_PD0,        RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(UART3_TX_PD1,         RSVD2,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(UART3_RX_PD2,         RSVD2,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(UART3_RTS_PD3,        RSVD2,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(UART3_CTS_PD4,        DEFAULT,  NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(DMIC1_CLK_PE0,        I2S3,     NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(DMIC1_DAT_PE1,        I2S3,     NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(DMIC2_CLK_PE2,        I2S3,     NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(DMIC2_DAT_PE3,        I2S3,     NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(DMIC3_CLK_PE4,        DEFAULT,  NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(DMIC3_DAT_PE5,        RSVD2,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(PE6,                  RSVD0,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(PE7,                  PWM3,     NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(GEN3_I2C_SCL_PF0,     I2C3,     NORMAL, NORMAL,   INPUT,   DISABLE, NORMAL),
-	PINCFG(GEN3_I2C_SDA_PF1,     I2C3,     NORMAL, NORMAL,   INPUT,   DISABLE, NORMAL),
-	PINCFG(UART2_TX_PG0,         DEFAULT,  NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(UART2_RX_PG1,         UARTB,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(UART2_RTS_PG2,        RSVD2,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(UART2_CTS_PG3,        RSVD2,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(WIFI_EN_PH0,          DEFAULT,  NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(WIFI_RST_PH1,         RSVD0,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(WIFI_WAKE_AP_PH2,     DEFAULT,  UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(AP_WAKE_BT_PH3,       DEFAULT,  NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(BT_RST_PH4,           DEFAULT,  NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(BT_WAKE_AP_PH5,       DEFAULT,  UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(PH6,                  RSVD0,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(AP_WAKE_NFC_PH7,      RSVD0,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(NFC_EN_PI0,           DEFAULT,  NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(NFC_INT_PI1,          DEFAULT,  NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(GPS_EN_PI2,           RSVD0,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(GPS_RST_PI3,          RSVD0,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(UART4_TX_PI4,         UARTD,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(UART4_RX_PI5,         UARTD,    NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(UART4_RTS_PI6,        UARTD,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(UART4_CTS_PI7,        UARTD,    NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(GEN1_I2C_SDA_PJ0,     I2C1,     NORMAL, NORMAL,   INPUT,   DISABLE, NORMAL),
-	PINCFG(GEN1_I2C_SCL_PJ1,     I2C1,     NORMAL, NORMAL,   INPUT,   DISABLE, NORMAL),
-	PINCFG(GEN2_I2C_SCL_PJ2,     I2C2,     NORMAL, NORMAL,   INPUT,   DISABLE, HIGH),
-	PINCFG(GEN2_I2C_SDA_PJ3,     I2C2,     NORMAL, NORMAL,   INPUT,   DISABLE, HIGH),
-	PINCFG(DAP4_FS_PJ4,          RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(DAP4_DIN_PJ5,         RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(DAP4_DOUT_PJ6,        RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(DAP4_SCLK_PJ7,        RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(PK0,                  RSVD2,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(PK1,                  RSVD2,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(PK2,                  RSVD2,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(PK3,                  RSVD2,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(PK4,                  RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(PK5,                  RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(PK6,                  RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(PK7,                  RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(PL0,                  RSVD0,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(PL1,                  RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(SDMMC1_CLK_PM0,       SDMMC1,   NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SDMMC1_CMD_PM1,       SDMMC1,   UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SDMMC1_DAT3_PM2,      SDMMC1,   UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SDMMC1_DAT2_PM3,      SDMMC1,   UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SDMMC1_DAT1_PM4,      SDMMC1,   UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SDMMC1_DAT0_PM5,      SDMMC1,   UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SDMMC3_CLK_PP0,       SDMMC3,   NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SDMMC3_CMD_PP1,       SDMMC3,   UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SDMMC3_DAT3_PP2,      SDMMC3,   UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SDMMC3_DAT2_PP3,      SDMMC3,   UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SDMMC3_DAT1_PP4,      SDMMC3,   UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(SDMMC3_DAT0_PP5,      SDMMC3,   UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(CAM1_MCLK_PS0,        RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(CAM2_MCLK_PS1,        RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(CAM_I2C_SCL_PS2,      I2CVI,    NORMAL, NORMAL,   INPUT,   DISABLE, NORMAL),
-	PINCFG(CAM_I2C_SDA_PS3,      I2CVI,    NORMAL, NORMAL,   INPUT,   DISABLE, NORMAL),
-	PINCFG(CAM_RST_PS4,          RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(CAM_AF_EN_PS5,        RSVD2,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(CAM_FLASH_EN_PS6,     RSVD2,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(CAM1_PWDN_PS7,        RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(CAM2_PWDN_PT0,        RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(CAM1_STROBE_PT1,      RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(UART1_TX_PU0,         UARTA,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(UART1_RX_PU1,         UARTA,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(UART1_RTS_PU2,        UARTA,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(UART1_CTS_PU3,        UARTA,    UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(LCD_BL_PWM_PV0,       PWM0,     NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(LCD_BL_EN_PV1,        DEFAULT,  NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(LCD_RST_PV2,          RSVD0,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(LCD_GPIO1_PV3,        RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(LCD_GPIO2_PV4,        PWM1,     NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(AP_READY_PV5,         RSVD0,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(TOUCH_RST_PV6,        DEFAULT,  NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(TOUCH_CLK_PV7,        RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(MODEM_WAKE_AP_PX0,    RSVD0,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(TOUCH_INT_PX1,        RSVD0,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(MOTION_INT_PX2,       RSVD0,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(ALS_PROX_INT_PX3,     RSVD0,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(TEMP_ALERT_PX4,       DEFAULT,  UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(BUTTON_POWER_ON_PX5,  RSVD0,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(BUTTON_VOL_UP_PX6,    DEFAULT,  UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(BUTTON_VOL_DOWN_PX7,  DEFAULT,  UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(BUTTON_SLIDE_SW_PY0,  RSVD0,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(BUTTON_HOME_PY1,      DEFAULT,  UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(LCD_TE_PY2,           RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(PWR_I2C_SCL_PY3,      I2CPMU,   NORMAL, NORMAL,   INPUT,   DISABLE, NORMAL),
-	PINCFG(PWR_I2C_SDA_PY4,      I2CPMU,   NORMAL, NORMAL,   INPUT,   DISABLE, NORMAL),
-	PINCFG(CLK_32K_OUT_PY5,      SOC,      UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(PZ0,                  DEFAULT,  UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(PZ1,                  SDMMC1,   UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(PZ2,                  RSVD2,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(PZ3,                  RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(PZ4,                  DEFAULT,  NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(PZ5,                  SOC,      UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(DAP2_FS_PAA0,         I2S2,     NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(DAP2_SCLK_PAA1,       I2S2,     NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(DAP2_DIN_PAA2,        I2S2,     NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(DAP2_DOUT_PAA3,       I2S2,     NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(AUD_MCLK_PBB0,        AUD,      NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(DVFS_PWM_PBB1,        CLDVFS,   NORMAL, TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(DVFS_CLK_PBB2,        DEFAULT,  NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(GPIO_X1_AUD_PBB3,     RSVD0,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(GPIO_X3_AUD_PBB4,     RSVD0,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(HDMI_CEC_PCC0,        CEC,      NORMAL, NORMAL,   INPUT,   DISABLE, HIGH),
-	PINCFG(HDMI_INT_DP_HPD_PCC1, DEFAULT,  DOWN,   NORMAL,   INPUT,   DISABLE, NORMAL),
-	PINCFG(SPDIF_OUT_PCC2,       RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(SPDIF_IN_PCC3,        DEFAULT,  NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(USB_VBUS_EN0_PCC4,    USB,      NORMAL, NORMAL,   INPUT,   DISABLE, HIGH),
-	PINCFG(USB_VBUS_EN1_PCC5,    USB,      NORMAL, NORMAL,   INPUT,   DISABLE, HIGH),
-	PINCFG(DP_HPD0_PCC6,         RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(PCC7,                 RSVD0,    DOWN,   TRISTATE, OUTPUT,  DISABLE, NORMAL),
-	PINCFG(SPI2_CS1_PDD0,        RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(QSPI_SCK_PEE0,        RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(QSPI_CS_N_PEE1,       RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(QSPI_IO0_PEE2,        RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(QSPI_IO1_PEE3,        RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(QSPI_IO2_PEE4,        RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(QSPI_IO3_PEE5,        RSVD1,    DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(CORE_PWR_REQ,         CORE,     NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(CPU_PWR_REQ,          CPU,      NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(PWR_INT_N,            PMI,      UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(CLK_32K_IN,           CLK,      NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
-	PINCFG(JTAG_RTCK,            JTAG,     NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(CLK_REQ,              SYS,      NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-	PINCFG(SHUTDOWN,             SHUTDOWN, NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
-};
-
-#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
-	{						\
-		.drvgrp = PMUX_DRVGRP_##_drvgrp,	\
-		.slwf   = _slwf,			\
-		.slwr   = _slwr,			\
-		.drvup  = _drvup,			\
-		.drvdn  = _drvdn,			\
-		.lpmd   = PMUX_LPMD_##_lpmd,		\
-		.schmt  = PMUX_SCHMT_##_schmt,		\
-		.hsm    = PMUX_HSM_##_hsm,		\
-	}
-
-static const struct pmux_drvgrp_config p2571_drvgrps[] = {
-};
-
-#endif /* PINMUX_CONFIG_P2571_H */

board/nvidia/p3450-0000/Kconfig

@@ -0,0 +1,12 @@
+if TARGET_P3450_0000
+
+config SYS_BOARD
+	default "p3450-0000"
+
+config SYS_VENDOR
+	default "nvidia"
+
+config SYS_CONFIG_NAME
+	default "p3450-0000"
+
+endif

board/nvidia/p3450-0000/MAINTAINERS

@@ -0,0 +1,6 @@
+P3450-0000 BOARD
+M:	Tom Warren <twarren@nvidia.com>
+S:	Maintained
+F:	board/nvidia/p3450-0000/
+F:	include/configs/p3450-0000.h
+F:	configs/p3450-0000_defconfig

board/nvidia/p3450-0000/Makefile

@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2018
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= p3450-0000.o

board/nvidia/p3450-0000/p3450-0000.c

@@ -0,0 +1,178 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018-2019
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <i2c.h>
+#include <linux/libfdt.h>
+#include <pca953x.h>
+#include <asm/arch-tegra/cboot.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/pinmux.h>
+#include "../p2571/max77620_init.h"
+
+void pin_mux_mmc(void)
+{
+	struct udevice *dev;
+	uchar val;
+	int ret;
+
+	/* Turn on MAX77620 LDO2 to 3.3V for SD card power */
+	debug("%s: Set LDO2 for VDDIO_SDMMC_AP power to 3.3V\n", __func__);
+	ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev);
+	if (ret) {
+		printf("%s: Cannot find MAX77620 I2C chip\n", __func__);
+		return;
+	}
+	/* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
+	val = 0xF2;
+	ret = dm_i2c_write(dev, MAX77620_CNFG1_L2_REG, &val, 1);
+	if (ret)
+		printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret);
+
+	/* Disable LDO4 discharge */
+	ret = dm_i2c_read(dev, MAX77620_CNFG2_L4_REG, &val, 1);
+	if (ret) {
+		printf("i2c_read 0 0x3c 0x2c failed: %d\n", ret);
+	} else {
+		val &= ~BIT(1); /* ADE */
+		ret = dm_i2c_write(dev, MAX77620_CNFG2_L4_REG, &val, 1);
+		if (ret)
+			printf("i2c_write 0 0x3c 0x2c failed: %d\n", ret);
+	}
+
+	/* Set MBLPD */
+	ret = dm_i2c_read(dev, MAX77620_CNFGGLBL1_REG, &val, 1);
+	if (ret) {
+		printf("i2c_write 0 0x3c 0x00 failed: %d\n", ret);
+	} else {
+		val |= BIT(6); /* MBLPD */
+		ret = dm_i2c_write(dev, MAX77620_CNFGGLBL1_REG, &val, 1);
+		if (ret)
+			printf("i2c_write 0 0x3c 0x00 failed: %d\n", ret);
+	}
+}
+
+#ifdef CONFIG_PCI_TEGRA
+int tegra_pcie_board_init(void)
+{
+	struct udevice *dev;
+	uchar val;
+	int ret;
+
+	/* Turn on MAX77620 LDO1 to 1.05V for PEX power */
+	debug("%s: Set LDO1 for PEX power to 1.05V\n", __func__);
+	ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev);
+	if (ret) {
+		printf("%s: Cannot find MAX77620 I2C chip\n", __func__);
+		return -1;
+	}
+	/* 0xCA for 1.05v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
+	val = 0xCA;
+	ret = dm_i2c_write(dev, MAX77620_CNFG1_L1_REG, &val, 1);
+	if (ret)
+		printf("i2c_write 0 0x3c 0x25 failed: %d\n", ret);
+
+	return 0;
+}
+#endif /* PCI */
+
+static void ft_mac_address_setup(void *fdt)
+{
+	const void *cboot_fdt = (const void *)cboot_boot_x0;
+	uint8_t mac[ETH_ALEN], local_mac[ETH_ALEN];
+	const char *path;
+	int offset, err;
+
+	err = cboot_get_ethaddr(cboot_fdt, local_mac);
+	if (err < 0)
+		memset(local_mac, 0, ETH_ALEN);
+
+	path = fdt_get_alias(fdt, "ethernet");
+	if (!path)
+		return;
+
+	debug("ethernet alias found: %s\n", path);
+
+	offset = fdt_path_offset(fdt, path);
+	if (offset < 0) {
+		printf("ethernet alias points to absent node %s\n", path);
+		return;
+	}
+
+	if (is_valid_ethaddr(local_mac)) {
+		err = fdt_setprop(fdt, offset, "local-mac-address", local_mac,
+				  ETH_ALEN);
+		if (!err)
+			debug("Local MAC address set: %pM\n", local_mac);
+	}
+
+	if (eth_env_get_enetaddr("ethaddr", mac)) {
+		if (memcmp(local_mac, mac, ETH_ALEN) != 0) {
+			err = fdt_setprop(fdt, offset, "mac-address", mac,
+					  ETH_ALEN);
+			if (!err)
+				debug("MAC address set: %pM\n", mac);
+		}
+	}
+}
+
+static int ft_copy_carveout(void *dst, const void *src, const char *node)
+{
+	struct fdt_memory fb;
+	int err;
+
+	err = fdtdec_get_carveout(src, node, "memory-region", 0, &fb);
+	if (err < 0) {
+		if (err != -FDT_ERR_NOTFOUND)
+			printf("failed to get carveout for %s: %d\n", node,
+			       err);
+
+		return err;
+	}
+
+	err = fdtdec_set_carveout(dst, node, "memory-region", 0, "framebuffer",
+				  &fb);
+	if (err < 0) {
+		printf("failed to set carveout for %s: %d\n", node, err);
+		return err;
+	}
+
+	return 0;
+}
+
+static void ft_carveout_setup(void *fdt)
+{
+	const void *cboot_fdt = (const void *)cboot_boot_x0;
+	static const char * const nodes[] = {
+		"/host1x@50000000/dc@54200000",
+		"/host1x@50000000/dc@54240000",
+	};
+	unsigned int i;
+	int err;
+
+	for (i = 0; i < ARRAY_SIZE(nodes); i++) {
+		printf("copying carveout for %s...\n", nodes[i]);
+
+		err = ft_copy_carveout(fdt, cboot_fdt, nodes[i]);
+		if (err < 0) {
+			if (err != -FDT_ERR_NOTFOUND)
+				printf("failed to copy carveout for %s: %d\n",
+				       nodes[i], err);
+
+			continue;
+		}
+	}
+}
+
+int ft_board_setup(void *fdt, bd_t *bd)
+{
+	ft_mac_address_setup(fdt);
+	ft_carveout_setup(fdt);
+
+	return 0;
+}

board/renesas/blanche/blanche.c

@@ -20,6 +20,7 @@
 #include <dm.h>
 #include <dm/platform_data/serial_sh.h>
 #include <env.h>
+#include <hang.h>
 #include <i2c.h>
 #include <linux/errno.h>
 #include <malloc.h>
@@ -313,6 +314,7 @@ int board_init(void)
 }
 
 /* Added for BLANCHE(R-CarV2H board) */
+#ifndef CONFIG_DM_ETH
 int board_eth_init(bd_t *bis)
 {
 	int rc = 0;
@@ -337,6 +339,7 @@ int board_eth_init(bd_t *bis)
 
 	return rc;
 }
+#endif
 
 int dram_init(void)
 {
@@ -355,4 +358,23 @@ int dram_init_banksize(void)
 
 void reset_cpu(ulong addr)
 {
+	struct udevice *dev;
+	const u8 pmic_bus = 6;
+	const u8 pmic_addr = 0x58;
+	u8 data;
+	int ret;
+
+	ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
+	if (ret)
+		hang();
+
+	ret = dm_i2c_read(dev, 0x13, &data, 1);
+	if (ret)
+		hang();
+
+	data |= BIT(1);
+
+	ret = dm_i2c_write(dev, 0x13, &data, 1);
+	if (ret)
+		hang();
 }

board/toradex/colibri_imx6/colibri_imx6.c

@@ -354,12 +354,15 @@ int board_phy_config(struct phy_device *phydev)
 int setup_fec(void)
 {
 	int ret;
+	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 
 	/* provide the PHY clock from the i.MX 6 */
 	ret = enable_fec_anatop_clock(0, ENET_50MHZ);
 	if (ret)
 		return ret;
 
+	setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
+
 	return 0;
 }
 

cmd/bootefi.c

@@ -199,7 +199,8 @@ static void efi_carve_out_dt_rsv(void *fdt)
 			 * The /reserved-memory node may have children with
 			 * a size instead of a reg property.
 			 */
-			if (addr != FDT_ADDR_T_NONE)
+			if (addr != FDT_ADDR_T_NONE &&
+			    fdtdec_get_is_enabled(fdt, subnode))
 				efi_reserve_memory(addr, size);
 			subnode = fdt_next_subnode(fdt, subnode);
 		}

cmd/dm.c

@@ -41,7 +41,7 @@ static int do_dm_dump_devres(cmd_tbl_t *cmdtp, int flag, int argc,
 }
 
 static int do_dm_dump_drivers(cmd_tbl_t *cmdtp, int flag, int argc,
-			       char * const argv[])
+			      char * const argv[])
 {
 	dm_dump_drivers();
 
@@ -94,5 +94,5 @@ U_BOOT_CMD(
 	"tree          Dump driver model tree ('*' = activated)\n"
 	"dm uclass        Dump list of instances for each uclass\n"
 	"dm devres        Dump list of device resources for each device\n"
-	"dm drivers       Dump list of drivers and their compatible strings\n"
+	"dm drivers       Dump list of drivers and their compatible strings"
 );

cmd/efidebug.c

@@ -489,10 +489,12 @@ static int do_efi_show_memmap(cmd_tbl_t *cmdtp, int flag,
 
 		printf("%-16s %.*llx-%.*llx", type,
 		       EFI_PHYS_ADDR_WIDTH,
-		       (u64)map_to_sysmem((void *)map->physical_start),
+		       (u64)map_to_sysmem((void *)(uintptr_t)
+					  map->physical_start),
 		       EFI_PHYS_ADDR_WIDTH,
-		       (u64)map_to_sysmem((void *)map->physical_start +
-					  map->num_pages * EFI_PAGE_SIZE));
+		       (u64)map_to_sysmem((void *)(uintptr_t)
+					  (map->physical_start +
+					   map->num_pages * EFI_PAGE_SIZE)));
 
 		print_memory_attributes(map->attribute);
 		putc('\n');

cmd/mmc.c

@@ -264,7 +264,7 @@ static int do_mmcrpmb(cmd_tbl_t *cmdtp, int flag,
 		return CMD_RET_FAILURE;
 
 	if (!(mmc->version & MMC_VERSION_MMC)) {
-		printf("It is not a EMMC device\n");
+		printf("It is not an eMMC device\n");
 		return CMD_RET_FAILURE;
 	}
 	if (mmc->version < MMC_VERSION_4_41) {
@@ -718,7 +718,7 @@ static int do_mmc_boot_resize(cmd_tbl_t *cmdtp, int flag,
 		return CMD_RET_FAILURE;
 
 	if (IS_SD(mmc)) {
-		printf("It is not a EMMC device\n");
+		printf("It is not an eMMC device\n");
 		return CMD_RET_FAILURE;
 	}
 

common/Kconfig

@@ -568,6 +568,7 @@ config PRE_CON_BUF_ADDR
 	default 0x2f000000 if ARCH_SUNXI && MACH_SUN9I
 	default 0x4f000000 if ARCH_SUNXI && !MACH_SUN9I
 	default 0x0f000000 if ROCKCHIP_RK3288
+	default 0x0f200000 if ROCKCHIP_RK3399
 	help
 	  This sets the start address of the pre-console buffer. This must
 	  be in available memory and is accessed before relocation and

common/bootm.c

@@ -819,7 +819,8 @@ void __weak switch_to_non_secure_mode(void)
 #else /* USE_HOSTCC */
 
 #if defined(CONFIG_FIT_SIGNATURE)
-static int bootm_host_load_image(const void *fit, int req_image_type)
+static int bootm_host_load_image(const void *fit, int req_image_type,
+				 int cfg_noffset)
 {
 	const char *fit_uname_config = NULL;
 	ulong data, len;
@@ -831,6 +832,7 @@ static int bootm_host_load_image(const void *fit, int req_image_type)
 	void *load_buf;
 	int ret;
 
+	fit_uname_config = fdt_get_name(fit, cfg_noffset, NULL);
 	memset(&images, '\0', sizeof(images));
 	images.verify = 1;
 	noffset = fit_image_load(&images, (ulong)fit,
@@ -878,7 +880,7 @@ int bootm_host_load_images(const void *fit, int cfg_noffset)
 	for (i = 0; i < ARRAY_SIZE(image_types); i++) {
 		int ret;
 
-		ret = bootm_host_load_image(fit, image_types[i]);
+		ret = bootm_host_load_image(fit, image_types[i], cfg_noffset);
 		if (!err && ret && ret != -ENOENT)
 			err = ret;
 	}

common/image-cipher.c

@@ -88,7 +88,7 @@ static int fit_image_setup_decrypt(struct image_cipher_info *info,
 		return -1;
 	}
 
-	info->keyname = fdt_getprop(fit, cipher_noffset, "key-name-hint", NULL);
+	info->keyname = fdt_getprop(fit, cipher_noffset, FIT_KEY_HINT, NULL);
 	if (!info->keyname) {
 		printf("Can't get key name\n");
 		return -1;

common/image-fit.c

@@ -168,7 +168,7 @@ static void fit_image_print_data(const void *fit, int noffset, const char *p,
 	int value_len;
 	char *algo;
 	const char *padding;
-	int required;
+	bool required;
 	int ret, i;
 
 	debug("%s  %s node:    '%s'\n", p, type,
@@ -179,8 +179,8 @@ static void fit_image_print_data(const void *fit, int noffset, const char *p,
 		return;
 	}
 	printf("%s", algo);
-	keyname = fdt_getprop(fit, noffset, "key-name-hint", NULL);
-	required = fdt_getprop(fit, noffset, "required", NULL) != NULL;
+	keyname = fdt_getprop(fit, noffset, FIT_KEY_HINT, NULL);
+	required = fdt_getprop(fit, noffset, FIT_KEY_REQUIRED, NULL) != NULL;
 	if (keyname)
 		printf(":%s", keyname);
 	if (required)
@@ -1712,24 +1712,6 @@ int fit_conf_find_compat(const void *fit, const void *fdt)
 	return best_match_offset;
 }
 
-/**
- * fit_conf_get_node - get node offset for configuration of a given unit name
- * @fit: pointer to the FIT format image header
- * @conf_uname: configuration node unit name
- *
- * fit_conf_get_node() finds a configuration (within the '/configurations'
- * parent node) of a provided unit name. If configuration is found its node
- * offset is returned to the caller.
- *
- * When NULL is provided in second argument fit_conf_get_node() will search
- * for a default configuration node instead. Default configuration node unit
- * name is retrieved from FIT_DEFAULT_PROP property of the '/configurations'
- * node.
- *
- * returns:
- *     configuration node offset when found (>=0)
- *     negative number on failure (FDT_ERR_* code)
- */
 int fit_conf_get_node(const void *fit, const char *conf_uname)
 {
 	int noffset, confs_noffset;
@@ -1969,7 +1951,7 @@ int fit_image_load(bootm_headers_t *images, ulong addr,
 		fit_uname = fit_get_name(fit, noffset, NULL);
 	}
 	if (noffset < 0) {
-		puts("Could not find subimage node\n");
+		printf("Could not find subimage node type '%s'\n", prop_name);
 		bootstage_error(bootstage_id + BOOTSTAGE_SUB_SUBNODE);
 		return -ENOENT;
 	}
@@ -2007,7 +1989,8 @@ int fit_image_load(bootm_headers_t *images, ulong addr,
 		fit_image_check_os(fit, noffset, IH_OS_LINUX) ||
 		fit_image_check_os(fit, noffset, IH_OS_U_BOOT) ||
 		fit_image_check_os(fit, noffset, IH_OS_OPENRTOS) ||
-		fit_image_check_os(fit, noffset, IH_OS_EFI);
+		fit_image_check_os(fit, noffset, IH_OS_EFI) ||
+		fit_image_check_os(fit, noffset, IH_OS_VXWORKS);
 
 	/*
 	 * If either of the checks fail, we should report an error, but

common/image-sig.c

@@ -229,7 +229,7 @@ static int fit_image_setup_verify(struct image_sign_info *info,
 		padding_name = RSA_DEFAULT_PADDING_NAME;
 
 	memset(info, '\0', sizeof(*info));
-	info->keyname = fdt_getprop(fit, noffset, "key-name-hint", NULL);
+	info->keyname = fdt_getprop(fit, noffset, FIT_KEY_HINT, NULL);
 	info->fit = (void *)fit;
 	info->node_offset = noffset;
 	info->name = algo_name;
@@ -340,7 +340,8 @@ int fit_image_verify_required_sigs(const void *fit, int image_noffset,
 		const char *required;
 		int ret;
 
-		required = fdt_getprop(sig_blob, noffset, "required", NULL);
+		required = fdt_getprop(sig_blob, noffset, FIT_KEY_REQUIRED,
+				       NULL);
 		if (!required || strcmp(required, "image"))
 			continue;
 		ret = fit_image_verify_sig(fit, image_noffset, data, size,
@@ -359,20 +360,39 @@ int fit_image_verify_required_sigs(const void *fit, int image_noffset,
 	return 0;
 }
 
-int fit_config_check_sig(const void *fit, int noffset, int required_keynode,
-			 char **err_msgp)
+/**
+ * fit_config_check_sig() - Check the signature of a config
+ *
+ * @fit: FIT to check
+ * @noffset: Offset of configuration node (e.g. /configurations/conf-1)
+ * @required_keynode:	Offset in the control FDT of the required key node,
+ *			if any. If this is given, then the configuration wil not
+ *			pass verification unless that key is used. If this is
+ *			-1 then any signature will do.
+ * @conf_noffset: Offset of the configuration subnode being checked (e.g.
+ *	 /configurations/conf-1/kernel)
+ * @err_msgp:		In the event of an error, this will be pointed to a
+ *			help error string to display to the user.
+ * @return 0 if all verified ok, <0 on error
+ */
+static int fit_config_check_sig(const void *fit, int noffset,
+				int required_keynode, int conf_noffset,
+				char **err_msgp)
 {
 	char * const exc_prop[] = {"data"};
 	const char *prop, *end, *name;
 	struct image_sign_info info;
 	const uint32_t *strings;
+	const char *config_name;
 	uint8_t *fit_value;
 	int fit_value_len;
+	bool found_config;
 	int max_regions;
 	int i, prop_len;
 	char path[200];
 	int count;
 
+	config_name = fit_get_name(fit, conf_noffset, NULL);
 	debug("%s: fdt=%p, conf='%s', sig='%s'\n", __func__, gd_fdt_blob(),
 	      fit_get_name(fit, noffset, NULL),
 	      fit_get_name(gd_fdt_blob(), required_keynode, NULL));
@@ -413,9 +433,20 @@ int fit_config_check_sig(const void *fit, int noffset, int required_keynode,
 	char *node_inc[count];
 
 	debug("Hash nodes (%d):\n", count);
+	found_config = false;
 	for (name = prop, i = 0; name < end; name += strlen(name) + 1, i++) {
 		debug("   '%s'\n", name);
 		node_inc[i] = (char *)name;
+		if (!strncmp(FIT_CONFS_PATH, name, strlen(FIT_CONFS_PATH)) &&
+		    name[sizeof(FIT_CONFS_PATH) - 1] == '/' &&
+		    !strcmp(name + sizeof(FIT_CONFS_PATH), config_name)) {
+			debug("      (found config node %s)", config_name);
+			found_config = true;
+		}
+	}
+	if (!found_config) {
+		*err_msgp = "Selected config not in hashed nodes";
+		return -1;
 	}
 
 	/*
@@ -483,7 +514,7 @@ static int fit_config_verify_sig(const void *fit, int conf_noffset,
 		if (!strncmp(name, FIT_SIG_NODENAME,
 			     strlen(FIT_SIG_NODENAME))) {
 			ret = fit_config_check_sig(fit, noffset, sig_offset,
-						   &err_msg);
+						   conf_noffset, &err_msg);
 			if (ret) {
 				puts("- ");
 			} else {
@@ -499,13 +530,14 @@ static int fit_config_verify_sig(const void *fit, int conf_noffset,
 		goto error;
 	}
 
-	return verified ? 0 : -EPERM;
+	if (verified)
+		return 0;
 
 error:
 	printf(" error!\n%s for '%s' hash node in '%s' config node\n",
 	       err_msg, fit_get_name(fit, noffset, NULL),
 	       fit_get_name(fit, conf_noffset, NULL));
-	return -1;
+	return -EPERM;
 }
 
 int fit_config_verify_required_sigs(const void *fit, int conf_noffset,
@@ -526,7 +558,8 @@ int fit_config_verify_required_sigs(const void *fit, int conf_noffset,
 		const char *required;
 		int ret;
 
-		required = fdt_getprop(sig_blob, noffset, "required", NULL);
+		required = fdt_getprop(sig_blob, noffset, FIT_KEY_REQUIRED,
+				       NULL);
 		if (!required || strcmp(required, "conf"))
 			continue;
 		ret = fit_config_verify_sig(fit, conf_noffset, sig_blob,

common/spl/spl_fit.c

@@ -646,10 +646,6 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
 
 		if (!spl_fit_image_get_os(fit, node, &os_type))
 			debug("Loadable is %s\n", genimg_get_os_name(os_type));
-#if CONFIG_IS_ENABLED(FIT_IMAGE_TINY)
-		else
-			os_type = IH_OS_U_BOOT;
-#endif
 
 		if (os_type == IH_OS_U_BOOT) {
 			spl_fit_append_fdt(&image_info, info, sector,

common/usb.c

@@ -172,6 +172,12 @@ int usb_detect_change(void)
 	return change;
 }
 
+/* Lock or unlock async schedule on the controller */
+__weak int usb_lock_async(struct usb_device *dev, int lock)
+{
+	return 0;
+}
+
 /*
  * disables the asynch behaviour of the control message. This is used for data
  * transfers that uses the exclusiv access to the control and bulk messages.

common/usb_storage.c

@@ -1157,6 +1157,7 @@ static unsigned long usb_stor_read(struct blk_desc *block_dev, lbaint_t blknr,
 	ss = (struct us_data *)udev->privptr;
 
 	usb_disable_asynch(1); /* asynch transfer not allowed */
+	usb_lock_async(udev, 1);
 	srb->lun = block_dev->lun;
 	buf_addr = (uintptr_t)buffer;
 	start = blknr;
@@ -1195,6 +1196,7 @@ retry_it:
 	debug("usb_read: end startblk " LBAF ", blccnt %x buffer %lx\n",
 	      start, smallblks, buf_addr);
 
+	usb_lock_async(udev, 0);
 	usb_disable_asynch(0); /* asynch transfer allowed */
 	if (blkcnt >= ss->max_xfer_blk)
 		debug("\n");
@@ -1239,6 +1241,7 @@ static unsigned long usb_stor_write(struct blk_desc *block_dev, lbaint_t blknr,
 	ss = (struct us_data *)udev->privptr;
 
 	usb_disable_asynch(1); /* asynch transfer not allowed */
+	usb_lock_async(udev, 1);
 
 	srb->lun = block_dev->lun;
 	buf_addr = (uintptr_t)buffer;
@@ -1280,6 +1283,7 @@ retry_it:
 	debug("usb_write: end startblk " LBAF ", blccnt %x buffer %lx\n",
 	      start, smallblks, buf_addr);
 
+	usb_lock_async(udev, 0);
 	usb_disable_asynch(0); /* asynch transfer allowed */
 	if (blkcnt >= ss->max_xfer_blk)
 		debug("\n");

configs/blanche_defconfig

@@ -24,7 +24,6 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PCI=y
 CONFIG_CMD_SDRAM=y
-CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
@@ -53,7 +52,7 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SMC911X=y
 CONFIG_SMC911X_BASE=0x18000000
@@ -68,6 +67,7 @@ CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_SCIF_CONSOLE=y
 CONFIG_SPI=y
+CONFIG_DM_SPI=y
 CONFIG_SH_QSPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y

configs/e2220-1170_defconfig

@@ -43,3 +43,4 @@ CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
+CONFIG_BOOTP_PREFER_SERVERIP=y

configs/nanopc-t4-rk3399_defconfig

@@ -52,5 +52,12 @@ CONFIG_USB_ETHER_ASIX88179=y
 CONFIG_USB_ETHER_MCS7830=y
 CONFIG_USB_ETHER_RTL8152=y
 CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_USB_KEYBOARD=y
 CONFIG_SPL_TINY_MEMSET=y
 CONFIG_ERRNO_STR=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_BPP16=y
+CONFIG_VIDEO_BPP32=y
+CONFIG_DISPLAY=y
+CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_DISPLAY_ROCKCHIP_HDMI=y

configs/nanopi-m4-rk3399_defconfig

@@ -52,5 +52,12 @@ CONFIG_USB_ETHER_ASIX88179=y
 CONFIG_USB_ETHER_MCS7830=y
 CONFIG_USB_ETHER_RTL8152=y
 CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_USB_KEYBOARD=y
 CONFIG_SPL_TINY_MEMSET=y
 CONFIG_ERRNO_STR=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_BPP16=y
+CONFIG_VIDEO_BPP32=y
+CONFIG_DISPLAY=y
+CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_DISPLAY_ROCKCHIP_HDMI=y

configs/nanopi-neo4-rk3399_defconfig

@@ -52,5 +52,12 @@ CONFIG_USB_ETHER_ASIX88179=y
 CONFIG_USB_ETHER_MCS7830=y
 CONFIG_USB_ETHER_RTL8152=y
 CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_USB_KEYBOARD=y
 CONFIG_SPL_TINY_MEMSET=y
 CONFIG_ERRNO_STR=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_BPP16=y
+CONFIG_VIDEO_BPP32=y
+CONFIG_DISPLAY=y
+CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_DISPLAY_ROCKCHIP_HDMI=y

configs/p2371-0000_defconfig

@@ -44,3 +44,4 @@ CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
+CONFIG_BOOTP_PREFER_SERVERIP=y

configs/p2371-2180_defconfig

@@ -52,3 +52,4 @@ CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
+CONFIG_BOOTP_PREFER_SERVERIP=y

configs/p2571_defconfig

@@ -44,3 +44,4 @@ CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
+CONFIG_BOOTP_PREFER_SERVERIP=y

configs/p2771-0000-000_defconfig

@@ -36,3 +36,5 @@ CONFIG_TEGRA186_POWER_DOMAIN=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_POSITION_INDEPENDENT=y
+CONFIG_BOOTP_PREFER_SERVERIP=y

configs/p2771-0000-500_defconfig

@@ -36,3 +36,5 @@ CONFIG_TEGRA186_POWER_DOMAIN=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_POSITION_INDEPENDENT=y
+CONFIG_BOOTP_PREFER_SERVERIP=y

configs/p3450-0000_defconfig

@@ -0,0 +1,64 @@
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_SYS_TEXT_BASE=0x80080000
+CONFIG_TEGRA210=y
+CONFIG_TARGET_P3450_0000=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_CONSOLE_MUX=y
+CONFIG_SYS_STDIO_DEREGISTER=y
+CONFIG_SYS_PROMPT="Tegra210 (P3450-0000) # "
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_LIVE=y
+CONFIG_DEFAULT_DEVICE_TREE="tegra210-p3450-0000"
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+CONFIG_SYS_I2C_TEGRA=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_USE_4K_SECTORS=y
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=24000000
+CONFIG_RTL8169=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCI_TEGRA=y
+CONFIG_SYS_NS16550=y
+CONFIG_TEGRA114_SPI=y
+CONFIG_TEGRA210_QSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_TEGRA=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="NVIDIA"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0955
+CONFIG_USB_GADGET_PRODUCT_NUM=0x701a
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+# CONFIG_ENV_IS_IN_MMC is not set
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_ENV_OFFSET=0xFFFFE000
+CONFIG_BOOTP_PREFER_SERVERIP=y
+CONFIG_POSITION_INDEPENDENT=y
+CONFIG_DISABLE_SDMMC1_EARLY=y

configs/roc-pc-rk3399_defconfig

@@ -59,3 +59,9 @@ CONFIG_USB_ETHER_SMSC95XX=y
 CONFIG_USB_KEYBOARD=y
 CONFIG_SPL_TINY_MEMSET=y
 CONFIG_ERRNO_STR=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_BPP16=y
+CONFIG_VIDEO_BPP32=y
+CONFIG_DISPLAY=y
+CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_DISPLAY_ROCKCHIP_HDMI=y

configs/rock960-rk3399_defconfig

@@ -58,5 +58,12 @@ CONFIG_USB_ETHER_ASIX88179=y
 CONFIG_USB_ETHER_MCS7830=y
 CONFIG_USB_ETHER_RTL8152=y
 CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_USB_KEYBOARD=y
 CONFIG_SPL_TINY_MEMSET=y
 CONFIG_ERRNO_STR=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_BPP16=y
+CONFIG_VIDEO_BPP32=y
+CONFIG_DISPLAY=y
+CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_DISPLAY_ROCKCHIP_HDMI=y

configs/vexpress_ca9x4_defconfig

@@ -34,4 +34,4 @@ CONFIG_SMC911X_32_BIT=y
 CONFIG_BAUDRATE=38400
 CONFIG_CONS_INDEX=0
 CONFIG_OF_LIBFDT=y
-# CONFIG_EFI_LOADER is not set
+CONFIG_DEFAULT_FDT_FILE="vexpress-v2p-ca9.dtb"

doc/board/emulation/qemu-mips.rst

@@ -25,37 +25,45 @@ Example usage
 
 Using u-boot.bin as ROM (replaces Qemu monitor):
 
-32 bit, big endian::
+32 bit, big endian
 
-   # make qemu_mips
-   # qemu-system-mips -M mips -bios u-boot.bin -nographic
+.. code-block:: bash
 
-32 bit, little endian::
+   make qemu_mips
+   qemu-system-mips -M mips -bios u-boot.bin -nographic
 
-   # make qemu_mipsel
-   # qemu-system-mipsel -M mips -bios u-boot.bin -nographic
+32 bit, little endian
 
-64 bit, big endian::
+.. code-block:: bash
 
-   # make qemu_mips64
-   # qemu-system-mips64 -cpu MIPS64R2-generic -M mips -bios u-boot.bin -nographic
+   make qemu_mipsel
+   qemu-system-mipsel -M mips -bios u-boot.bin -nographic
 
-64 bit, little endian::
+64 bit, big endian
 
-   # make qemu_mips64el
-   # qemu-system-mips64el -cpu MIPS64R2-generic -M mips -bios u-boot.bin -nographic
+.. code-block:: bash
+
+   make qemu_mips64
+   qemu-system-mips64 -cpu MIPS64R2-generic -M mips -bios u-boot.bin -nographic
+
+64 bit, little endian
+
+.. code-block:: bash
+
+   make qemu_mips64el
+   qemu-system-mips64el -cpu MIPS64R2-generic -M mips -bios u-boot.bin -nographic
 
 or using u-boot.bin from emulated flash:
 
-if you use a qemu version after commit 4224
+if you use a QEMU version after commit 4224
 
-.. code-block:: none
+.. code-block:: bash
 
-   create image:
-   # dd of=flash bs=1k count=4k if=/dev/zero
-   # dd of=flash bs=1k conv=notrunc if=u-boot.bin
-   start it (see above):
-   # qemu-system-mips[64][el] [-cpu MIPS64R2-generic] -M mips -pflash flash -nographic
+   # create image:
+   dd of=flash bs=1k count=4k if=/dev/zero
+   dd of=flash bs=1k conv=notrunc if=u-boot.bin
+   # start it (see above):
+   qemu-system-mips[64][el] [-cpu MIPS64R2-generic] -M mips -pflash flash -nographic
 
 Download kernel + initrd
 ^^^^^^^^^^^^^^^^^^^^^^^^
@@ -75,61 +83,63 @@ you can downland::
 Generate uImage
 ^^^^^^^^^^^^^^^
 
-.. code-block:: none
+.. code-block:: bash
 
-   # tools/mkimage -A mips -O linux -T kernel -C gzip -a 0x80010000 -e 0x80245650 -n "Linux 2.6.24.y" -d vmlinux.bin.gz uImage
+   tools/mkimage -A mips -O linux -T kernel -C gzip -a 0x80010000 -e 0x80245650 -n "Linux 2.6.24.y" -d vmlinux.bin.gz uImage
 
 Copy uImage to Flash
 ^^^^^^^^^^^^^^^^^^^^
 
-.. code-block:: none
+.. code-block:: bash
 
-   # dd if=uImage bs=1k conv=notrunc seek=224 of=flash
+   dd if=uImage bs=1k conv=notrunc seek=224 of=flash
 
 Generate Ide Disk
 ^^^^^^^^^^^^^^^^^
 
-.. code-block:: none
+.. code-block:: bash
 
-   # dd of=ide bs=1k cout=100k if=/dev/zero
+   dd of=ide bs=1k count=100k if=/dev/zero
 
-   # sfdisk -C 261 -d ide
-   # partition table of ide
+   # Create partion table
+   sudo sfdisk ide << EOF
+   label: dos
+   label-id: 0x6fe3a999
+   device: image
    unit: sectors
-
-        ide1 : start=       63, size=    32067, Id=83
-        ide2 : start=    32130, size=    32130, Id=83
-        ide3 : start=    64260, size=  4128705, Id=83
-        ide4 : start=        0, size=        0, Id= 0
+   image1 : start=       63, size=    32067, Id=83
+   image2 : start=    32130, size=    32130, Id=83
+   image3 : start=    64260, size=  4128705, Id=83
+   EOF
 
 Copy to ide
 ^^^^^^^^^^^
 
-.. code-block:: none
+.. code-block:: bash
 
-   # dd if=uImage bs=512 conv=notrunc seek=63 of=ide
+   dd if=uImage bs=512 conv=notrunc seek=63 of=ide
 
 Generate ext2 on part 2 on Copy uImage and initrd.gz
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-.. code-block:: none
+.. code-block:: bash
 
    # Attached as loop device ide offset = 32130 * 512
-   # losetup -o 16450560 -f ide
+   sudo losetup -o 16450560 /dev/loop0 ide
    # Format as ext2 ( arg2 : nb blocks)
-   # mke2fs /dev/loop0 16065
-   # losetup -d /dev/loop0
+   sudo mkfs.ext2 /dev/loop0 16065
+   sudo losetup -d /dev/loop0
    # Mount and copy uImage and initrd.gz to it
-   # mount -o loop,offset=16450560 -t ext2 ide /mnt
-   # mkdir /mnt/boot
-   # cp {initrd.gz,uImage} /mnt/boot/
+   sudo mount -o loop,offset=16450560 -t ext2 ide /mnt
+   sudo mkdir /mnt/boot
+   cp {initrd.gz,uImage} /mnt/boot/
    # Umount it
-   # umount /mnt
+   sudo umount /mnt
 
 Set Environment
 ^^^^^^^^^^^^^^^
 
-.. code-block:: none
+.. code-block:: bash
 
    setenv rd_start 0x80800000
    setenv rd_size 2663940
@@ -157,9 +167,11 @@ Set Environment
    setenv addmisc 'setenv bootargs ${bootargs} console=ttyS0,${baudrate} rd_start=${rd_start} rd_size=${rd_size} ethaddr=${ethaddr}'
    setenv bootcmd 'run boot_tftp_flash'
 
-Now you can boot from flash, ide, ide+ext2 and tfp::
+Now you can boot from flash, ide, ide+ext2 and tfp
 
-   # qemu-system-mips -M mips -pflash flash -monitor null -nographic -net nic -net user -tftp `pwd` -hda ide
+.. code-block:: bash
+
+   qemu-system-mips -M mips -pflash flash -monitor null -nographic -net nic -net user -tftp `pwd` -hda ide
 
 
 How to debug U-Boot
@@ -168,9 +180,9 @@ How to debug U-Boot
 In order to debug U-Boot you need to start qemu with gdb server support (-s)
 and waiting the connection to start the CPU (-S)
 
-.. code-block:: none
+.. code-block:: bash
 
-   # qemu-system-mips -S -s -M mips -pflash flash -monitor null -nographic -net nic -net user -tftp `pwd` -hda ide
+   qemu-system-mips -S -s -M mips -pflash flash -monitor null -nographic -net nic -net user -tftp `pwd` -hda ide
 
 in an other console you start gdb
 
@@ -182,7 +194,7 @@ by connecting to the gdb server localhost:1234
 
 .. code-block:: none
 
-   # mipsel-unknown-linux-gnu-gdb u-boot
+   $ mipsel-unknown-linux-gnu-gdb u-boot
    GNU gdb 6.6
    Copyright (C) 2006 Free Software Foundation, Inc.
    GDB is free software, covered by the GNU General Public License, and you are

doc/board/toradex/verdin-imx8mm.rst

@@ -18,31 +18,22 @@ Get and Build the ARM Trusted Firmware (Trusted Firmware A)
 .. code-block:: bash
 
     $ echo "Downloading and building TF-A..."
-    $ git clone -b imx_4.14.98_2.3.0 \
-      https://source.codeaurora.org/external/imx/imx-atf
-    $ cd imx-atf
-
-Please edit ``plat/imx/imx8mm/include/platform_def.h`` so it contains proper
-values for UART configuration and BL31 base address (correct values listed
-below):
-
-.. code-block:: bash
-
-    #define BL31_BASE                   0x910000
-    #define IMX_BOOT_UART_BASE          0x30860000
-    #define DEBUG_CONSOLE               1
+    $ git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git
+    $ cd trusted-firmware-a
 
 Then build ATF (TF-A):
 
 .. code-block:: bash
 
-    $ make PLAT=imx8mm bl31
+    $ make PLAT=imx8mm IMX_BOOT_UART_BASE=0x30860000 bl31
+    $ cp build/imx8mm/release/bl31.bin ../
 
 Get the DDR Firmware
 --------------------
 
 .. code-block:: bash
 
+    $ cd ..
     $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.4.1.bin
     $ chmod +x firmware-imx-8.4.1.bin
     $ ./firmware-imx-8.4.1.bin
@@ -53,6 +44,7 @@ Build U-Boot
 .. code-block:: bash
 
     $ export CROSS_COMPILE=aarch64-linux-gnu-
+    $ export ATF_LOAD_ADDR=0x920000
     $ make verdin-imx8mm_defconfig
     $ make flash.bin
 
@@ -89,12 +81,6 @@ Output:
     U-Boot SPL 2020.01-00187-gd411d164e5 (Jan 26 2020 - 04:47:26 +0100)
     Normal Boot
     Trying to boot from MMC1
-    NOTICE:  Configuring TZASC380
-    NOTICE:  RDC off
-    NOTICE:  BL31: v2.0(release):rel_imx_4.14.98_2.3.0-0-g09c5cc994-dirty
-    NOTICE:  BL31: Built : 01:11:41, Jan 25 2020
-    NOTICE:  sip svc init
-
 
     U-Boot 2020.01-00187-gd411d164e5 (Jan 26 2020 - 04:47:26 +0100)
 

doc/device-tree-bindings/gpio/fsl,mpc83xx-spisel-boot.txt

@@ -0,0 +1,22 @@
+MPC83xx SPISEL_BOOT gpio controller
+
+Provide access to MPC83xx SPISEL_BOOT signal as a gpio to allow it to be
+easily bound as a SPI controller chip select.
+
+The SPISEL_BOOT signal is always an output.
+
+Required properties:
+
+- compatible: must be "fsl,mpc83xx-spisel-boot" or "fsl,mpc8309-spisel-boot".
+- reg: must point to the SPI_CS register in the SoC register map.
+- ngpios: number of gpios provided by driver, normally 1.
+
+Example:
+
+	spisel_boot: spisel_boot@14c {
+		compatible = "fsl,mpc8309-spisel-boot";
+		reg = <0x14c 0x04>;
+		#gpio-cells = <2>;
+		device_type = "gpio";
+		ngpios = <1>;
+	};

drivers/clk/altera/clk-arria10.c

@@ -274,6 +274,8 @@ static int socfpga_a10_clk_bind(struct udevice *dev)
 static int socfpga_a10_clk_probe(struct udevice *dev)
 {
 	struct socfpga_a10_clk_platdata *plat = dev_get_platdata(dev);
+	struct socfpga_a10_clk_platdata *pplat;
+	struct udevice *pdev;
 	const void *fdt = gd->fdt_blob;
 	int offset = dev_of_offset(dev);
 
@@ -281,6 +283,21 @@ static int socfpga_a10_clk_probe(struct udevice *dev)
 
 	socfpga_a10_handoff_workaround(dev);
 
+	if (!fdt_node_check_compatible(fdt, offset, "altr,clk-mgr")) {
+		plat->regs = devfdt_get_addr(dev);
+	} else {
+		pdev = dev_get_parent(dev);
+		if (!pdev)
+			return -ENODEV;
+
+		pplat = dev_get_platdata(pdev);
+		if (!pplat)
+			return -EINVAL;
+
+		plat->ctl_reg = dev_read_u32_default(dev, "reg", 0x0);
+		plat->regs = pplat->regs;
+	}
+
 	if (!fdt_node_check_compatible(fdt, offset,
 				       "altr,socfpga-a10-pll-clock")) {
 		/* Main PLL has 3 upstream clock */
@@ -304,29 +321,8 @@ static int socfpga_a10_clk_probe(struct udevice *dev)
 static int socfpga_a10_ofdata_to_platdata(struct udevice *dev)
 {
 	struct socfpga_a10_clk_platdata *plat = dev_get_platdata(dev);
-	struct socfpga_a10_clk_platdata *pplat;
-	struct udevice *pdev;
-	const void *fdt = gd->fdt_blob;
 	unsigned int divreg[3], gatereg[2];
-	int ret, offset = dev_of_offset(dev);
-	u32 regs;
-
-	regs = dev_read_u32_default(dev, "reg", 0x0);
-
-	if (!fdt_node_check_compatible(fdt, offset, "altr,clk-mgr")) {
-		plat->regs = devfdt_get_addr(dev);
-	} else {
-		pdev = dev_get_parent(dev);
-		if (!pdev)
-			return -ENODEV;
-
-		pplat = dev_get_platdata(pdev);
-		if (!pplat)
-			return -EINVAL;
-
-		plat->ctl_reg = regs;
-		plat->regs = pplat->regs;
-	}
+	int ret;
 
 	plat->type = SOCFPGA_A10_CLK_UNKNOWN_CLK;
 

drivers/clk/renesas/clk-rcar-gen2.c

@@ -291,7 +291,8 @@ int gen2_clk_probe(struct udevice *dev)
 	if (ret < 0)
 		return ret;
 
-	rst_base = fdtdec_get_addr(gd->fdt_blob, ret, "reg");
+	rst_base = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, ret, "reg",
+						      0, NULL, false);
 	if (rst_base == FDT_ADDR_T_NONE)
 		return -EINVAL;
 

drivers/clk/rockchip/clk_rk3399.c

@@ -994,6 +994,13 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
 	case DCLK_VOP1:
 		ret = rk3399_vop_set_clk(priv->cru, clk->id, rate);
 		break;
+	case ACLK_VOP1:
+	case HCLK_VOP1:
+		/**
+		 * assigned-clocks handling won't require for vopl, so
+		 * return 0 to satisfy clk_set_defaults during device probe.
+		 */
+		return 0;
 	case SCLK_DDRCLK:
 		ret = rk3399_ddr_set_clk(priv->cru, rate);
 		break;

drivers/core/dump.c

@@ -107,11 +107,16 @@ void dm_dump_drivers(void)
 	puts("Driver                Compatible\n");
 	puts("--------------------------------\n");
 	for (entry = d; entry < d + n_ents; entry++) {
-		for (match = entry->of_match; match->compatible; match++)
-			printf("%-20.20s  %s\n",
-			       match == entry->of_match ? entry->name : "",
-			       match->compatible);
-		if (match == entry->of_match)
-			printf("%-20.20s\n", entry->name);
+		match = entry->of_match;
+
+		printf("%-20.20s", entry->name);
+		if (match) {
+			printf("  %s", match->compatible);
+			match++;
+		}
+		printf("\n");
+
+		for (; match && match->compatible; match++)
+			printf("%-20.20s  %s\n", "", match->compatible);
 	}
 }

drivers/ddr/fsl/mpc85xx_ddr_gen3.c

@@ -370,8 +370,6 @@ step2:
 	debug("Setting DEBUG_3[21] to 0x%08x\n", in_be32(&ddr->debug[2]));
 
 #endif	/* part 1 of the workaound */
-	/* Always start in self-refresh, clear after MEM_EN */
-	setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR);
 
 	/*
 	 * 500 painful micro-seconds must elapse between
@@ -384,6 +382,8 @@ step2:
 
 #ifdef CONFIG_DEEP_SLEEP
 	if (is_warm_boot()) {
+		/* enter self-refresh */
+		setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR);
 		/* do board specific memory setup */
 		board_mem_sleep_setup();
 		temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
@@ -395,10 +395,6 @@ step2:
 	out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
 	asm volatile("sync;isync");
 
-	/* Exit self-refresh after DDR conf as some ddr memories can fail. */
-	clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR);
-	asm volatile("sync;isync");
-
 	total_gb_size_per_controller = 0;
 	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 		if (!(regs->cs[i].config & 0x80000000))
@@ -548,4 +544,9 @@ step2:
 		clrbits_be32(&ddr->sdram_cfg, 0x2);
 	}
 #endif /* CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 */
+#ifdef CONFIG_DEEP_SLEEP
+	if (is_warm_boot())
+		/* exit self-refresh */
+		clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR);
+#endif
 }

drivers/gpio/Kconfig

@@ -423,6 +423,14 @@ config MPC8XXX_GPIO
 	  value setting, the open-drain feature, which can configure individual
 	  GPIOs to work as open-drain outputs, is supported.
 
+config MPC83XX_SPISEL_BOOT
+	bool "Freescale MPC83XX SPISEL_BOOT driver"
+	depends on DM_GPIO && ARCH_MPC830X
+	help
+	  GPIO driver to set/clear dedicated SPISEL_BOOT output on MPC83XX.
+
+	  This pin is typically used as spi chip select to a spi nor flash.
+
 config MT7621_GPIO
 	bool "MediaTek MT7621 GPIO driver"
 	depends on DM_GPIO && SOC_MT7628

drivers/gpio/Makefile

@@ -40,6 +40,7 @@ obj-$(CONFIG_DM644X_GPIO)	+= da8xx_gpio.o
 obj-$(CONFIG_ALTERA_PIO)	+= altera_pio.o
 obj-$(CONFIG_MPC83XX_GPIO)	+= mpc83xx_gpio.o
 obj-$(CONFIG_MPC8XXX_GPIO)	+= mpc8xxx_gpio.o
+obj-$(CONFIG_MPC83XX_SPISEL_BOOT)	+= mpc83xx_spisel_boot.o
 obj-$(CONFIG_SH_GPIO_PFC)	+= sh_pfc.o
 obj-$(CONFIG_OMAP_GPIO)	+= omap_gpio.o
 obj-$(CONFIG_DB8500_GPIO)	+= db8500_gpio.o

drivers/gpio/mpc83xx_spisel_boot.c

@@ -0,0 +1,148 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019 DEIF A/S
+ *
+ * GPIO driver to set/clear SPISEL_BOOT pin on mpc83xx.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <mapmem.h>
+#include <asm/gpio.h>
+
+struct mpc83xx_spisel_boot {
+	u32 __iomem *spi_cs;
+	ulong addr;
+	uint gpio_count;
+	ulong type;
+};
+
+static u32 gpio_mask(uint gpio)
+{
+	return (1U << (31 - (gpio)));
+}
+
+static int mpc83xx_spisel_boot_direction_input(struct udevice *dev, uint gpio)
+{
+	return -EINVAL;
+}
+
+static int mpc83xx_spisel_boot_set_value(struct udevice *dev, uint gpio, int value)
+{
+	struct mpc83xx_spisel_boot *data = dev_get_priv(dev);
+
+	debug("%s: gpio=%d, value=%u, gpio_mask=0x%08x\n", __func__,
+	      gpio, value, gpio_mask(gpio));
+
+	if (value)
+		setbits_be32(data->spi_cs, gpio_mask(gpio));
+	else
+		clrbits_be32(data->spi_cs, gpio_mask(gpio));
+
+	return 0;
+}
+
+static int mpc83xx_spisel_boot_direction_output(struct udevice *dev, uint gpio, int value)
+{
+	return 0;
+}
+
+static int mpc83xx_spisel_boot_get_value(struct udevice *dev, uint gpio)
+{
+	struct mpc83xx_spisel_boot *data = dev_get_priv(dev);
+
+	return !!(in_be32(data->spi_cs) & gpio_mask(gpio));
+}
+
+static int mpc83xx_spisel_boot_get_function(struct udevice *dev, uint gpio)
+{
+	return GPIOF_OUTPUT;
+}
+
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+static int mpc83xx_spisel_boot_ofdata_to_platdata(struct udevice *dev)
+{
+	struct mpc8xxx_gpio_plat *plat = dev_get_platdata(dev);
+	fdt_addr_t addr;
+	u32 reg[2];
+
+	dev_read_u32_array(dev, "reg", reg, 2);
+	addr = dev_translate_address(dev, reg);
+
+	plat->addr = addr;
+	plat->size = reg[1];
+	plat->ngpios = dev_read_u32_default(dev, "ngpios", 1);
+
+	return 0;
+}
+#endif
+
+static int mpc83xx_spisel_boot_platdata_to_priv(struct udevice *dev)
+{
+	struct mpc83xx_spisel_boot *priv = dev_get_priv(dev);
+	struct mpc8xxx_gpio_plat *plat = dev_get_platdata(dev);
+	unsigned long size = plat->size;
+	ulong driver_data = dev_get_driver_data(dev);
+
+	if (size == 0)
+		size = 0x04;
+
+	priv->addr = plat->addr;
+	priv->spi_cs = map_sysmem(plat->addr, size);
+
+	if (!priv->spi_cs)
+		return -ENOMEM;
+
+	priv->gpio_count = plat->ngpios;
+
+	priv->type = driver_data;
+
+	return 0;
+}
+
+static int mpc83xx_spisel_boot_probe(struct udevice *dev)
+{
+	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+	struct mpc83xx_spisel_boot *data = dev_get_priv(dev);
+	char name[32], *str;
+
+	mpc83xx_spisel_boot_platdata_to_priv(dev);
+
+	snprintf(name, sizeof(name), "MPC@%lx_", data->addr);
+	str = strdup(name);
+
+	if (!str)
+		return -ENOMEM;
+
+	uc_priv->bank_name = str;
+	uc_priv->gpio_count = data->gpio_count;
+
+	return 0;
+}
+
+static const struct dm_gpio_ops mpc83xx_spisel_boot_ops = {
+	.direction_input	= mpc83xx_spisel_boot_direction_input,
+	.direction_output	= mpc83xx_spisel_boot_direction_output,
+	.get_value		= mpc83xx_spisel_boot_get_value,
+	.set_value		= mpc83xx_spisel_boot_set_value,
+	.get_function		= mpc83xx_spisel_boot_get_function,
+};
+
+static const struct udevice_id mpc83xx_spisel_boot_ids[] = {
+	{ .compatible = "fsl,mpc8309-spisel-boot" },
+	{ .compatible = "fsl,mpc83xx-spisel-boot" },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(spisel_boot_mpc83xx) = {
+	.name	= "spisel_boot_mpc83xx",
+	.id	= UCLASS_GPIO,
+	.ops	= &mpc83xx_spisel_boot_ops,
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+	.ofdata_to_platdata = mpc83xx_spisel_boot_ofdata_to_platdata,
+	.platdata_auto_alloc_size = sizeof(struct mpc8xxx_gpio_plat),
+	.of_match = mpc83xx_spisel_boot_ids,
+#endif
+	.probe	= mpc83xx_spisel_boot_probe,
+	.priv_auto_alloc_size = sizeof(struct mpc83xx_spisel_boot),
+};

drivers/gpio/mpc8xxx_gpio.c

@@ -57,27 +57,6 @@ static inline u32 mpc8xxx_gpio_get_dir(struct ccsr_gpio *base, u32 mask)
 	return in_be32(&base->gpdir) & mask;
 }
 
-static inline void mpc8xxx_gpio_set_in(struct ccsr_gpio *base, u32 gpios)
-{
-	clrbits_be32(&base->gpdat, gpios);
-	/* GPDIR register 0 -> input */
-	clrbits_be32(&base->gpdir, gpios);
-}
-
-static inline void mpc8xxx_gpio_set_low(struct ccsr_gpio *base, u32 gpios)
-{
-	clrbits_be32(&base->gpdat, gpios);
-	/* GPDIR register 1 -> output */
-	setbits_be32(&base->gpdir, gpios);
-}
-
-static inline void mpc8xxx_gpio_set_high(struct ccsr_gpio *base, u32 gpios)
-{
-	setbits_be32(&base->gpdat, gpios);
-	/* GPDIR register 1 -> output */
-	setbits_be32(&base->gpdir, gpios);
-}
-
 static inline int mpc8xxx_gpio_open_drain_val(struct ccsr_gpio *base, u32 mask)
 {
 	return in_be32(&base->gpodr) & mask;
@@ -100,22 +79,32 @@ static inline void mpc8xxx_gpio_open_drain_off(struct ccsr_gpio *base,
 static int mpc8xxx_gpio_direction_input(struct udevice *dev, uint gpio)
 {
 	struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
+	u32 mask = gpio_mask(gpio);
+
+	/* GPDIR register 0 -> input */
+	clrbits_be32(&data->base->gpdir, mask);
 
-	mpc8xxx_gpio_set_in(data->base, gpio_mask(gpio));
 	return 0;
 }
 
 static int mpc8xxx_gpio_set_value(struct udevice *dev, uint gpio, int value)
 {
 	struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
+	struct ccsr_gpio *base = data->base;
+	u32 mask = gpio_mask(gpio);
+	u32 gpdir;
 
 	if (value) {
-		data->dat_shadow |= gpio_mask(gpio);
-		mpc8xxx_gpio_set_high(data->base, gpio_mask(gpio));
+		data->dat_shadow |= mask;
 	} else {
-		data->dat_shadow &= ~gpio_mask(gpio);
-		mpc8xxx_gpio_set_low(data->base, gpio_mask(gpio));
+		data->dat_shadow &= ~mask;
 	}
+
+	gpdir = in_be32(&base->gpdir);
+	gpdir |= gpio_mask(gpio);
+	out_be32(&base->gpdat, gpdir & data->dat_shadow);
+	out_be32(&base->gpdir, gpdir);
+
 	return 0;
 }
 

drivers/mmc/tegra_mmc.c

@@ -3,7 +3,7 @@
  * (C) Copyright 2009 SAMSUNG Electronics
  * Minkyu Kang <mk7.kang@samsung.com>
  * Jaehoon Chung <jh80.chung@samsung.com>
- * Portions Copyright 2011-2016 NVIDIA Corporation
+ * Portions Copyright 2011-2019 NVIDIA Corporation
  */
 
 #include <bouncebuf.h>
@@ -15,6 +15,9 @@
 #include <asm/io.h>
 #include <asm/arch-tegra/tegra_mmc.h>
 #include <linux/err.h>
+#if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA210)
+#include <asm/arch/clock.h>
+#endif
 
 struct tegra_mmc_plat {
 	struct mmc_config cfg;
@@ -30,6 +33,7 @@ struct tegra_mmc_priv {
 	struct gpio_desc wp_gpio;	/* Write Protect GPIO */
 	unsigned int version;	/* SDHCI spec. version */
 	unsigned int clock;	/* Current clock (MHz) */
+	int mmc_id;		/* peripheral id */
 };
 
 static void tegra_mmc_set_power(struct tegra_mmc_priv *priv,
@@ -372,6 +376,25 @@ static void tegra_mmc_change_clock(struct tegra_mmc_priv *priv, uint clock)
 
 	rate = clk_set_rate(&priv->clk, clock);
 	div = (rate + clock - 1) / clock;
+
+#if defined(CONFIG_TEGRA210)
+	if (priv->mmc_id == PERIPH_ID_SDMMC1 && clock <= 400000) {
+		/* clock_adjust_periph_pll_div() chooses a 'bad' clock
+		 * on SDMMC1 T210, so skip it here and force a clock
+		 * that's been spec'd in the table in the TRM for
+		 * card-detect (400KHz).
+		 */
+		uint effective_rate = clock_adjust_periph_pll_div(priv->mmc_id,
+				CLOCK_ID_PERIPH, 24727273, NULL);
+		div = 62;
+
+		debug("%s: WAR: Using SDMMC1 clock of %u, div %d to achieve %dHz card clock ...\n",
+		      __func__, effective_rate, div, clock);
+	} else {
+		clock_adjust_periph_pll_div(priv->mmc_id, CLOCK_ID_PERIPH,
+					    clock, &div);
+	}
+#endif
 	debug("div = %d\n", div);
 
 	writew(0, &priv->reg->clkcon);
@@ -446,16 +469,19 @@ static int tegra_mmc_set_ios(struct udevice *dev)
 
 static void tegra_mmc_pad_init(struct tegra_mmc_priv *priv)
 {
-#if defined(CONFIG_TEGRA30)
+#if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA210)
 	u32 val;
+	u16 clk_con;
+	int timeout;
+	int id = priv->mmc_id;
 
-	debug("%s: sdmmc address = %08x\n", __func__, (unsigned int)priv->reg);
+	debug("%s: sdmmc address = %p, id = %d\n", __func__,
+		priv->reg, id);
 
 	/* Set the pad drive strength for SDMMC1 or 3 only */
-	if (priv->reg != (void *)0x78000000 &&
-	    priv->reg != (void *)0x78000400) {
+	if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) {
 		debug("%s: settings are only valid for SDMMC1/SDMMC3!\n",
-		      __func__);
+			__func__);
 		return;
 	}
 
@@ -464,11 +490,65 @@ static void tegra_mmc_pad_init(struct tegra_mmc_priv *priv)
 	val |= MEMCOMP_PADCTRL_VREF;
 	writel(val, &priv->reg->sdmemcmppadctl);
 
+	/* Disable SD Clock Enable before running auto-cal as per TRM */
+	clk_con = readw(&priv->reg->clkcon);
+	debug("%s: CLOCK_CONTROL = 0x%04X\n", __func__, clk_con);
+	clk_con &= ~TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
+	writew(clk_con, &priv->reg->clkcon);
+
 	val = readl(&priv->reg->autocalcfg);
 	val &= 0xFFFF0000;
-	val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED;
+	val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET;
 	writel(val, &priv->reg->autocalcfg);
-#endif
+	val |= AUTO_CAL_START | AUTO_CAL_ENABLE;
+	writel(val, &priv->reg->autocalcfg);
+	debug("%s: AUTO_CAL_CFG = 0x%08X\n", __func__, val);
+	udelay(1);
+	timeout = 100;				/* 10 mSec max (100*100uS) */
+	do {
+		val = readl(&priv->reg->autocalsts);
+		udelay(100);
+	} while ((val & AUTO_CAL_ACTIVE) && --timeout);
+	val = readl(&priv->reg->autocalsts);
+	debug("%s: Final AUTO_CAL_STATUS = 0x%08X, timeout = %d\n",
+	      __func__, val, timeout);
+
+	/* Re-enable SD Clock Enable when auto-cal is done */
+	clk_con |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
+	writew(clk_con, &priv->reg->clkcon);
+	clk_con = readw(&priv->reg->clkcon);
+	debug("%s: final CLOCK_CONTROL = 0x%04X\n", __func__, clk_con);
+
+	if (timeout == 0) {
+		printf("%s: Warning: Autocal timed out!\n", __func__);
+		/* TBD: Set CFG2TMC_SDMMC1_PAD_CAL_DRV* regs here */
+	}
+
+#if defined(CONFIG_TEGRA210)
+	u32 tap_value, trim_value;
+
+	/* Set tap/trim values for SDMMC1/3 @ <48MHz here */
+	val = readl(&priv->reg->venspictl);	/* aka VENDOR_SYS_SW_CNTL */
+	val &= IO_TRIM_BYPASS_MASK;
+	if (id == PERIPH_ID_SDMMC1) {
+		tap_value = 4;			/* default */
+		if (val)
+			tap_value = 3;
+		trim_value = 2;
+	} else {				/* SDMMC3 */
+		tap_value = 3;
+		trim_value = 3;
+	}
+
+	val = readl(&priv->reg->venclkctl);
+	val &= ~TRIM_VAL_MASK;
+	val |= (trim_value << TRIM_VAL_SHIFT);
+	val &= ~TAP_VAL_MASK;
+	val |= (tap_value << TAP_VAL_SHIFT);
+	writel(val, &priv->reg->venclkctl);
+	debug("%s: VENDOR_CLOCK_CNTRL = 0x%08X\n", __func__, val);
+#endif	/* T210 */
+#endif	/* T30/T210 */
 }
 
 static void tegra_mmc_reset(struct tegra_mmc_priv *priv, struct mmc *mmc)
@@ -514,6 +594,13 @@ static int tegra_mmc_init(struct udevice *dev)
 	unsigned int mask;
 	debug(" tegra_mmc_init called\n");
 
+#if defined(CONFIG_TEGRA210)
+	priv->mmc_id = clock_decode_periph_id(dev);
+	if (priv->mmc_id == PERIPH_ID_NONE) {
+		printf("%s: Missing/invalid peripheral ID\n", __func__);
+		return -EINVAL;
+	}
+#endif
 	tegra_mmc_reset(priv, mmc);
 
 #if defined(CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK)

drivers/mtd/spi/spi-nor-ids.c

@@ -147,6 +147,7 @@ const struct flash_info spi_nor_ids[] = {
 	{ INFO("mx25l6405d",  0xc22017, 0, 64 * 1024, 128, SECT_4K) },
 	{ INFO("mx25u2033e",  0xc22532, 0, 64 * 1024,   4, SECT_4K) },
 	{ INFO("mx25u1635e",  0xc22535, 0, 64 * 1024,  32, SECT_4K) },
+	{ INFO("mx25u3235f",  0xc22536, 0, 4 * 1024,  1024, SECT_4K) },
 	{ INFO("mx25u6435f",  0xc22537, 0, 64 * 1024, 128, SECT_4K) },
 	{ INFO("mx25l12805d", 0xc22018, 0, 64 * 1024, 256, 0) },
 	{ INFO("mx25l12855e", 0xc22618, 0, 64 * 1024, 256, 0) },