Prepare v2020.07

Signed-off-by: Tom Rini <trini@konsulko.com>

.azure-pipelines.yml

@@ -2,7 +2,7 @@ variables:
   windows_vm: vs2017-win2016
   ubuntu_vm: ubuntu-18.04
   macos_vm: macOS-10.15
-  ci_runner_image: trini/u-boot-gitlab-ci-runner:bionic-20200403-27Apr2020
+  ci_runner_image: trini/u-boot-gitlab-ci-runner:bionic-20200526-18Jun2020
   # Add '-u 0' options for Azure pipelines, otherwise we get "permission
   # denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer",
   # since our $(ci_runner_image) user is not root.

.gitlab-ci.yml

@@ -2,7 +2,7 @@
 
 # Grab our configured image.  The source for this is found at:
 # https://gitlab.denx.de/u-boot/gitlab-ci-runner
-image: trini/u-boot-gitlab-ci-runner:bionic-20200403-27Apr2020
+image: trini/u-boot-gitlab-ci-runner:bionic-20200526-18Jun2020
 
 # We run some tests in different order, to catch some failures quicker.
 stages:

Kconfig

@@ -146,7 +146,7 @@ config SYS_MALLOC_F_LEN
 	default 0x2000 if (ARCH_IMX8 || ARCH_IMX8M || ARCH_MX7 || \
 			   ARCH_MX7ULP || ARCH_MX6 || ARCH_MX5 || \
 			   ARCH_LS1012A || ARCH_LS1021A || ARCH_LS1043A || \
-			   ARCH_LS1046A)
+			   ARCH_LS1046A || ARCH_QEMU)
 	default 0x400
 	help
 	  Before relocation, memory is very limited on many platforms. Still,

MAINTAINERS

@@ -145,6 +145,7 @@ F:	drivers/power/domain/meson-gx-pwrc-vpu.c
 F:	drivers/video/meson/
 F:	include/configs/meson64.h
 F:	include/configs/meson64_android.h
+F:	doc/board/amlogic/
 N:	meson
 
 ARM BROADCOM BCM283X
@@ -877,6 +878,7 @@ M:	Sughosh Ganu <sughosh.ganu@linaro.org>
 R:	Heinrich Schuchardt <xypron.glpk@gmx.de>
 S:	Maintained
 F:	cmd/rng.c
+F:	doc/api/rng.rst
 F:	drivers/rng/
 F:	drivers/virtio/virtio_rng.c
 F:	include/rng.h

Makefile

@@ -3,7 +3,7 @@
 VERSION = 2020
 PATCHLEVEL = 07
 SUBLEVEL =
-EXTRAVERSION = -rc4
+EXTRAVERSION =
 NAME =
 
 # *DOCUMENTATION*

arch/arm/Kconfig

@@ -873,11 +873,11 @@ config ARCH_MX7ULP
 config ARCH_MX7
 	bool "Freescale MX7"
 	select ARCH_MISC_INIT
-	select BOARD_EARLY_INIT_F
 	select CPU_V7A
 	select SYS_FSL_HAS_SEC if IMX_HAB
 	select SYS_FSL_SEC_COMPAT_4
 	select SYS_FSL_SEC_LE
+	imply BOARD_EARLY_INIT_F
 	imply MXC_GPIO
 	imply SYS_THUMB_BUILD
 
@@ -1905,7 +1905,6 @@ source "board/hisilicon/hikey/Kconfig"
 source "board/hisilicon/hikey960/Kconfig"
 source "board/hisilicon/poplar/Kconfig"
 source "board/isee/igep003x/Kconfig"
-source "board/phytec/pcm051/Kconfig"
 source "board/silica/pengwyn/Kconfig"
 source "board/spear/spear300/Kconfig"
 source "board/spear/spear310/Kconfig"

arch/arm/dts/ca-presidio-engboard.dts

@@ -10,11 +10,9 @@
    #size-cells = <1>;
 
 	mmc0: mmc@f4400000 {
-		compatible = "snps,dw-cortina";
+		compatible = "cortina,ca-mmc";
 		reg = <0x0 0xf4400000 0x1000>;
 		bus-width = <4>;
-		io_ds = <0x77>;
-		fifo-mode;
 		sd_dll_ctrl = <0xf43200e8>;
 		io_drv_ctrl = <0xf432004c>;
 	};

arch/arm/dts/fsl-imx8qm.dtsi

@@ -21,13 +21,14 @@
 	aliases {
 		ethernet0 = &fec1;
 		ethernet1 = &fec2;
-		gpio0 = &gpio1;
-		gpio1 = &gpio2;
-		gpio2 = &gpio3;
-		gpio3 = &gpio4;
-		gpio4 = &gpio5;
-		gpio5 = &gpio6;
-		gpio6 = &gpio7;
+		gpio0 = &gpio0;
+		gpio1 = &gpio1;
+		gpio2 = &gpio2;
+		gpio3 = &gpio3;
+		gpio4 = &gpio4;
+		gpio5 = &gpio5;
+		gpio6 = &gpio6;
+		gpio7 = &gpio7;
 		serial0 = &lpuart0;
 		serial1 = &lpuart1;
 		serial2 = &lpuart2;

arch/arm/dts/imx53-m53menlo.dts

@@ -86,8 +86,19 @@
 &fec {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_fec>;
+	phy-handle = <&ethphy0>;
 	phy-mode = "rmii";
 	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+		};
+	};
 };
 
 &i2c1 {

arch/arm/dts/imx6q-tbs2910.dts

@@ -107,7 +107,18 @@
 	pinctrl-0 = <&pinctrl_enet>;
 	phy-mode = "rgmii-id";
 	phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
+	phy-handle = <&phy>;
 	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		phy: ethernet-phy@4 {
+			reg = <4>;
+			qca,clk-out-frequency = <125000000>;
+		};
+	};
 };
 
 &hdmi {

arch/arm/dts/imx6qdl-hummingboard2-emmc-som-v15-u-boot.dtsi

@@ -34,3 +34,11 @@
 &usdhc1 {
 	status = "disabled";
 };
+
+&usdhc2 {
+	u-boot,dm-pre-reloc;
+};
+
+&usdhc3 {
+	u-boot,dm-pre-reloc;
+};

arch/arm/dts/imx6qdl-sabreauto.dtsi

@@ -281,7 +281,7 @@
 &fec {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_enet>;
-	phy-mode = "rgmii";
+	phy-mode = "rgmii-id";
 	interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
 			      <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
 	fsl,err006687-workaround-present;

arch/arm/dts/imx6qdl-sabresd.dtsi

@@ -204,7 +204,7 @@
 &fec {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_enet>;
-	phy-mode = "rgmii";
+	phy-mode = "rgmii-id";
 	phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
 	status = "okay";
 };

arch/arm/dts/imx6qdl-sr-som.dtsi

@@ -53,10 +53,21 @@
 &fec {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_microsom_enet_ar8035>;
+	phy-handle = <&phy>;
 	phy-mode = "rgmii-id";
 	phy-reset-duration = <2>;
 	phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
 	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		phy: ethernet-phy@0 {
+			reg = <0>;
+			qca,clk-out-frequency = <125000000>;
+		};
+	};
 };
 
 &iomuxc {

arch/arm/dts/imxrt1050.dtsi

@@ -147,12 +147,12 @@
 		};
 
 		lcdif: lcdif@402b8000 {
-		    compatible = "fsl,imxrt-lcdif";
-		    reg = <0x402b8000 0x10000>;
-		    interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
-		    clocks = <&clks IMXRT1050_CLK_LCDIF>;
-		    clock-names = "per";
-		    status = "disabled";
+			compatible = "fsl,imxrt-lcdif";
+			reg = <0x402b8000 0x4000>;
+			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clks IMXRT1050_CLK_LCDIF>;
+			clock-names = "per";
+			status = "disabled";
 		};
 	};
 };

arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi

@@ -68,3 +68,7 @@
 &portc {
 	bank-name = "portc";
 };
+
+&i2c0 {
+	i2c-scl-falling-time-ns = <300>;
+};

arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi

@@ -20,6 +20,21 @@
 		st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
 		st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
 	};
+
+	firmware {
+		optee {
+			compatible = "linaro,optee-tz";
+			method = "smc";
+		};
+	};
+
+	reserved-memory {
+		optee@de000000 {
+			reg = <0xde000000 0x02000000>;
+			no-map;
+		};
+	};
+
 	led {
 		red {
 			label = "error";
@@ -156,6 +171,8 @@
 
 &sdmmc1 {
 	u-boot,dm-spl;
+	broken-cd;
+	/delete-property/ cd-gpios;
 };
 
 &sdmmc1_b4_pins_a {

arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi

@@ -21,6 +21,20 @@
 		st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
 	};
 
+	firmware {
+		optee {
+			compatible = "linaro,optee-tz";
+			method = "smc";
+		};
+	};
+
+	reserved-memory {
+		optee@fe000000 {
+			reg = <0xfe000000 0x02000000>;
+			no-map;
+		};
+	};
+
 	led {
 		red {
 			label = "error";
@@ -153,6 +167,8 @@
 
 &sdmmc1 {
 	u-boot,dm-spl;
+	broken-cd;
+	/delete-property/ cd-gpios;
 };
 
 &sdmmc1_b4_pins_a {

arch/arm/dts/stm32mp157c-ed1.dts

@@ -70,11 +70,6 @@
 			reg = <0xe8000000 0x8000000>;
 			no-map;
 		};
-
-		optee@fe000000 {
-			reg = <0xfe000000 0x02000000>;
-			no-map;
-		};
 	};
 
 	aliases {

arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi

@@ -273,6 +273,9 @@
 
 &sdmmc1 {
 	u-boot,dm-spl;
+	broken-cd;
+	/delete-property/ cd-gpios;
+	/delete-property/ disable-wp;
 };
 
 &sdmmc1_b4_pins_a {

arch/arm/dts/stm32mp15xx-dkx.dtsi

@@ -58,11 +58,6 @@
 			reg = <0xd4000000 0x4000000>;
 			no-map;
 		};
-
-		optee@de000000 {
-			reg = <0xde000000 0x02000000>;
-			no-map;
-		};
 	};
 
 	led {

arch/arm/dts/tegra186.dtsi

@@ -335,4 +335,9 @@
 			status = "disabled";
 		};
 	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
 };

arch/arm/dts/tegra210.dtsi

@@ -867,6 +867,11 @@
 		};
 	};
 
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
 	timer {
 		compatible = "arm,armv8-timer";
 		interrupts = <GIC_PPI 13

arch/arm/include/asm/arch-mx7/imx-regs.h

@@ -274,6 +274,7 @@ struct src {
 
 #define SRC_DDRC_RCR_DDRC_CORE_RST_OFFSET	1
 #define SRC_DDRC_RCR_DDRC_CORE_RST_MASK		(1 << 1)
+#define SRC_DDRC_RCR_DDRC_PRST_MASK		(1 << 0)
 
 /* GPR0 Bit Fields */
 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_MASK     0x1u

arch/arm/include/asm/arch-mx7/mx7-ddr.h

@@ -39,7 +39,9 @@ struct ddrc {
 	u32 dramtmg8;		/* 0x0120 */
 	u32 reserved7[0x17];
 	u32 zqctl0;		/* 0x0180 */
-	u32 reserved8[0x03];
+	u32 zqctl1;		/* 0x0184 */
+	u32 zqctl2;		/* 0x0188 */
+	u32 zqstat;		/* 0x018c */
 	u32 dfitmg0;		/* 0x0190 */
 	u32 dfitmg1;		/* 0x0194 */
 	u32 reserved9[0x02];

arch/arm/mach-imx/Kconfig

@@ -23,7 +23,7 @@ config IMX_RDC
 
 config IMX_BOOTAUX
 	bool "Support boot auxiliary core"
-	depends on ARCH_MX7 || ARCH_MX6 || ARCH_VF610
+	depends on ARCH_MX7 || ARCH_MX6 || ARCH_VF610 || ARCH_IMX8M
 	help
 	  bootaux [addr] to boot auxiliary core.
 

arch/arm/mach-imx/mkimage_fit_atf.sh

@@ -62,6 +62,23 @@ cat << __HEADER_EOF
 			compression = "none";
 			load = <$BL33_LOAD_ADDR>;
 		};
+__HEADER_EOF
+
+cnt=1
+for dtname in $*
+do
+	cat << __FDT_IMAGE_EOF
+		fdt@$cnt {
+			description = "$(basename $dtname .dtb)";
+			data = /incbin/("$dtname");
+			type = "flat_dt";
+			compression = "none";
+		};
+__FDT_IMAGE_EOF
+cnt=$((cnt+1))
+done
+
+cat << __HEADER_EOF
 		atf@1 {
 			description = "ARM Trusted Firmware";
 			os = "arm-trusted-firmware";
@@ -88,20 +105,6 @@ cat << __HEADER_EOF
 __HEADER_EOF
 fi
 
-cnt=1
-for dtname in $*
-do
-	cat << __FDT_IMAGE_EOF
-		fdt@$cnt {
-			description = "$(basename $dtname .dtb)";
-			data = /incbin/("$dtname");
-			type = "flat_dt";
-			compression = "none";
-		};
-__FDT_IMAGE_EOF
-cnt=$((cnt+1))
-done
-
 cat << __CONF_HEADER_EOF
 	};
 	configurations {

arch/arm/mach-imx/mx7/Kconfig

@@ -16,6 +16,13 @@ config MX7D
 	select ROM_UNIFIED_SECTIONS
 	imply CMD_FUSE
 
+config SYS_TEXT_BASE
+	default 0x87800000
+
+config SPL_TEXT_BASE
+	depends on SPL
+	default 0x00912000
+
 choice
 	prompt "MX7 board select"
 	optional

arch/arm/mach-imx/mx7/ddr.c

@@ -13,6 +13,7 @@
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/mx7-ddr.h>
 #include <common.h>
+#include <linux/delay.h>
 
 /*
  * Routine: mx7_dram_cfg
@@ -37,8 +38,23 @@ void mx7_dram_cfg(struct ddrc *ddrc_regs_val, struct ddrc_mp *ddrc_mp_val,
 		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
 	int i;
 
-	/* Assert DDR Controller preset and DDR PHY reset */
-	writel(SRC_DDRC_RCR_DDRC_CORE_RST_MASK, &src_regs->ddrc_rcr);
+	/*
+	 * iMX7D RM 9.2.4.9.3 Power removal flow Table 9-11. Re-enabling power
+	 * row 2 says "Reset controller / PHY by driving core_ddrc_rst = 0 ,
+	 * aresetn_n = 0, presetn = 0. That means reset everything.
+	 */
+	writel(SRC_DDRC_RCR_DDRC_CORE_RST_MASK | SRC_DDRC_RCR_DDRC_PRST_MASK,
+	       &src_regs->ddrc_rcr);
+
+	/*
+	 * iMX7D RM 6.2.7.26 SRC_DDRC_RCR says wait 30 cycles (of unknown).
+	 * If we assume this is 30 cycles at 100 MHz (about the rate of a
+	 * DRAM bus), that's 300 nS, so waiting 10 uS is more then plenty.
+	 */
+	udelay(10);
+
+	/* De-assert DDR Controller 'preset' and DDR PHY reset */
+	clrbits_le32(&src_regs->ddrc_rcr, SRC_DDRC_RCR_DDRC_PRST_MASK);
 
 	/* DDR controller configuration */
 	writel(ddrc_regs_val->mstr, &ddrc_regs->mstr);
@@ -58,6 +74,7 @@ void mx7_dram_cfg(struct ddrc *ddrc_regs_val, struct ddrc_mp *ddrc_mp_val,
 	writel(ddrc_regs_val->dramtmg5, &ddrc_regs->dramtmg5);
 	writel(ddrc_regs_val->dramtmg8, &ddrc_regs->dramtmg8);
 	writel(ddrc_regs_val->zqctl0, &ddrc_regs->zqctl0);
+	writel(ddrc_regs_val->zqctl1, &ddrc_regs->zqctl1);
 	writel(ddrc_regs_val->dfitmg0, &ddrc_regs->dfitmg0);
 	writel(ddrc_regs_val->dfitmg1, &ddrc_regs->dfitmg1);
 	writel(ddrc_regs_val->dfiupd0, &ddrc_regs->dfiupd0);
@@ -71,7 +88,7 @@ void mx7_dram_cfg(struct ddrc *ddrc_regs_val, struct ddrc_mp *ddrc_mp_val,
 	writel(ddrc_regs_val->odtcfg, &ddrc_regs->odtcfg);
 	writel(ddrc_regs_val->odtmap, &ddrc_regs->odtmap);
 
-	/* De-assert DDR Controller preset and DDR PHY reset */
+	/* De-assert DDR Controller 'core_ddrc_rstn' and 'aresetn' */
 	clrbits_le32(&src_regs->ddrc_rcr, SRC_DDRC_RCR_DDRC_CORE_RST_MASK);
 
 	/* PHY configuration */

arch/arm/mach-omap2/omap3/Kconfig

@@ -181,7 +181,6 @@ source "board/isee/igep00x0/Kconfig"
 source "board/overo/Kconfig"
 source "board/logicpd/zoom1/Kconfig"
 source "board/ti/am3517crane/Kconfig"
-source "board/pandora/Kconfig"
 source "board/corscience/tricorder/Kconfig"
 source "board/logicpd/omap3som/Kconfig"
 source "board/nokia/rx51/Kconfig"

arch/arm/mach-rockchip/rk3188/rk3188.c

@@ -77,15 +77,32 @@ int arch_cpu_init(void)
 		     BYPASSSEL_MASK | BYPASSDMEN_MASK,
 		     1 << BYPASSSEL_SHIFT | 1 << BYPASSDMEN_SHIFT);
 #endif
+	return 0;
+}
+#endif
+
+__weak int rk3188_board_late_init(void)
+{
+	return 0;
+}
+
+int rk_board_late_init(void)
+{
+	struct rk3188_grf *grf;
+
+	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+	if (IS_ERR(grf)) {
+		pr_err("grf syscon returned %ld\n", PTR_ERR(grf));
+		return 0;
+	}
 
 	/* enable noc remap to mimic legacy loaders */
 	rk_clrsetreg(&grf->soc_con0,
 		     NOC_REMAP_MASK << NOC_REMAP_SHIFT,
 		     NOC_REMAP_MASK << NOC_REMAP_SHIFT);
 
-	return 0;
+	return rk3188_board_late_init();
 }
-#endif
 
 #ifdef CONFIG_SPL_BUILD
 static int setup_led(void)

arch/arm/mach-socfpga/misc_s10.c

@@ -68,7 +68,7 @@ static u32 socfpga_phymode_setup(u32 gmac_index, const char *phymode)
 		return -EINVAL;
 
 	clrsetbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC0 +
-			gmac_index,
+			(gmac_index * sizeof(u32)),
 			SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, modereg);
 
 	return 0;

arch/arm/mach-stm32mp/fdt.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
 /*
- * Copyright (C) 2019, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2019-2020, STMicroelectronics - All Rights Reserved
  */
 
 #include <common.h>
@@ -224,19 +224,23 @@ static void stm32_fdt_disable_optee(void *blob)
 {
 	int off, node;
 
+	/* Delete "optee" firmware node */
 	off = fdt_node_offset_by_compatible(blob, -1, "linaro,optee-tz");
 	if (off >= 0 && fdtdec_get_is_enabled(blob, off))
-		fdt_status_disabled(blob, off);
+		fdt_del_node(blob, off);
 
-	/* Disabled "optee@..." reserved-memory node */
+	/* Delete "optee@..." reserved-memory node */
 	off = fdt_path_offset(blob, "/reserved-memory/");
 	if (off < 0)
 		return;
 	for (node = fdt_first_subnode(blob, off);
 	     node >= 0;
 	     node = fdt_next_subnode(blob, node)) {
-		if (!strncmp(fdt_get_name(blob, node, NULL), "optee@", 6))
-			fdt_status_disabled(blob, node);
+		if (strncmp(fdt_get_name(blob, node, NULL), "optee@", 6))
+			continue;
+
+		if (fdt_del_node(blob, node))
+			printf("Failed to remove optee reserved-memory node\n");
 	}
 }
 

arch/riscv/Kconfig

@@ -273,4 +273,7 @@ config STACK_SIZE_SHIFT
 	int
 	default 14
 
+config OF_BOARD_FIXUP
+	default y if OF_SEPARATE
+
 endmenu

arch/riscv/cpu/fu540/Makefile

@@ -8,4 +8,5 @@ obj-y += spl.o
 else
 obj-y += dram.o
 obj-y += cpu.o
+obj-y += cache.o
 endif

arch/riscv/cpu/fu540/cache.c

@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 SiFive, Inc
+ *
+ * Authors:
+ *   Pragnesh Patel <pragnesh.patel@sifive.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+
+/* Register offsets */
+#define L2_CACHE_CONFIG	0x000
+#define L2_CACHE_ENABLE	0x008
+
+#define MASK_NUM_WAYS	GENMASK(15, 8)
+#define NUM_WAYS_SHIFT	8
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int cache_enable_ways(void)
+{
+	const void *blob = gd->fdt_blob;
+	int node = (-FDT_ERR_NOTFOUND);
+	fdt_addr_t base;
+	u32 config;
+	u32 ways;
+
+	volatile u32 *enable;
+
+	node = fdt_node_offset_by_compatible(blob, -1,
+					     "sifive,fu540-c000-ccache");
+
+	if (node < 0)
+		return node;
+
+	base = fdtdec_get_addr(blob, node, "reg");
+	if (base == FDT_ADDR_T_NONE)
+		return FDT_ADDR_T_NONE;
+
+	config = readl((volatile u32 *)base + L2_CACHE_CONFIG);
+	ways = (config & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT;
+
+	enable = (volatile u32 *)(base + L2_CACHE_ENABLE);
+
+	/* memory barrier */
+	mb();
+	(*enable) = ways - 1;
+	/* memory barrier */
+	mb();
+	return 0;
+}

arch/riscv/dts/fu540-c000-u-boot.dtsi

@@ -27,7 +27,7 @@
 			clocks = <&prci PRCI_CLK_COREPLL>;
 			u-boot,dm-spl;
 			cpu2_intc: interrupt-controller {
-				 u-boot,dm-spl;
+				u-boot,dm-spl;
 			};
 		};
 		cpu3: cpu@3 {
@@ -50,7 +50,7 @@
 		u-boot,dm-spl;
 		otp: otp@10070000 {
 			compatible = "sifive,fu540-c000-otp";
-			reg = <0x0 0x10070000 0x0 0x0FFF>;
+			reg = <0x0 0x10070000 0x0 0x1000>;
 			fuse-count = <0x1000>;
 		};
 		clint@2000000 {
@@ -63,7 +63,7 @@
 			compatible = "sifive,fu540-c000-ddr";
 			reg = <0x0 0x100b0000 0x0 0x0800
 			       0x0 0x100b2000 0x0 0x2000
-			       0x0 0x100b8000 0x0 0x0fff>;
+			       0x0 0x100b8000 0x0 0x1000>;
 			clocks = <&prci PRCI_CLK_DDRPLL>;
 			clock-frequency = <933333324>;
 			u-boot,dm-spl;
@@ -87,3 +87,7 @@
 	assigned-clocks = <&prci PRCI_CLK_GEMGXLPLL>;
 	assigned-clock-rates = <125000000>;
 };
+
+&l2cache {
+	status = "okay";
+};

arch/riscv/include/asm/arch-fu540/cache.h

@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020 SiFive, Inc.
+ *
+ * Authors:
+ *   Pragnesh Patel <pragnesh.patel@sifve.com>
+ */
+
+#ifndef _CACHE_SIFIVE_H
+#define _CACHE_SIFIVE_H
+
+int cache_enable_ways(void);
+
+#endif /* _CACHE_SIFIVE_H */

arch/riscv/lib/Makefile

@@ -20,7 +20,9 @@ obj-$(CONFIG_SBI) += sbi.o
 obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
 endif
 obj-y	+= interrupts.o
+ifeq ($(CONFIG_$(SPL_)SYSRESET),)
 obj-y	+= reset.o
+endif
 obj-y   += setjmp.o
 obj-$(CONFIG_$(SPL_)SMP) += smp.o
 obj-$(CONFIG_SPL_BUILD)	+= spl.o

arch/riscv/lib/fdt_fixup.c

@@ -4,6 +4,8 @@
  *
  */
 
+#define LOG_CATEGORY LOGC_ARCH
+
 #include <common.h>
 #include <fdt_support.h>
 #include <log.h>
@@ -37,18 +39,30 @@ int riscv_fdt_copy_resv_mem_node(const void *src, void *dst)
 
 	offset = fdt_path_offset(src, "/reserved-memory");
 	if (offset < 0) {
-		printf("No reserved memory region found in source FDT\n");
+		log_debug("No reserved memory region found in source FDT\n");
 		return 0;
 	}
 
+	/*
+	 * Extend the FDT by the following estimated size:
+	 *
+	 * Each PMP memory region entry occupies 64 bytes.
+	 * With 16 PMP memory regions we need 64 * 16 = 1024 bytes.
+	 */
+	err = fdt_open_into(dst, dst, fdt_totalsize(dst) + 1024);
+	if (err < 0) {
+		printf("Device Tree can't be expanded to accommodate new node");
+		return err;
+	}
+
 	fdt_for_each_subnode(node, src, offset) {
 		name = fdt_get_name(src, node, NULL);
 
-		addr = fdtdec_get_addr_size_auto_noparent(src, node,
-							  "reg", 0, &size,
-							  false);
+		addr = fdtdec_get_addr_size_auto_parent(src, offset, node,
+							"reg", 0, &size,
+							false);
 		if (addr == FDT_ADDR_T_NONE) {
-			debug("failed to read address/size for %s\n", name);
+			log_debug("failed to read address/size for %s\n", name);
 			continue;
 		}
 		strncpy(basename, name, max_len);
@@ -62,8 +76,8 @@ int riscv_fdt_copy_resv_mem_node(const void *src, void *dst)
 		pmp_mem.end = addr + size - 1;
 		err = fdtdec_add_reserved_memory(dst, basename, &pmp_mem,
 						 &phandle);
-		if (err < 0) {
-			printf("failed to add reserved memory: %d\n", err);
+		if (err < 0 && err != -FDT_ERR_EXISTS) {
+			log_err("failed to add reserved memory: %d\n", err);
 			return err;
 		}
 		if (!fdt_getprop(src, node, "no-map", NULL))
@@ -82,10 +96,9 @@ int riscv_fdt_copy_resv_mem_node(const void *src, void *dst)
  * @fdt: Pointer to the device tree in which reserved memory node needs to be
  *	 added.
  *
- * In RISC-V, any board compiled with OF_SEPARATE needs to copy the reserved
- * memory node from the device tree provided by the firmware to the device tree
- * used by U-Boot. This is a common function that individual board fixup
- * functions can invoke.
+ * In RISC-V, any board needs to copy the reserved memory node from the device
+ * tree provided by the firmware to the device tree used by U-Boot. This is a
+ * common function that individual board fixup functions can invoke.
  *
  * Return: 0 on success or error otherwise.
  */
@@ -95,6 +108,11 @@ int riscv_board_reserved_mem_fixup(void *fdt)
 	void *src_fdt_addr;
 
 	src_fdt_addr = map_sysmem(gd->arch.firmware_fdt_addr, 0);
+
+	/* avoid the copy if we are using the same device tree */
+	if (src_fdt_addr == fdt)
+		return 0;
+
 	err = riscv_fdt_copy_resv_mem_node(src_fdt_addr, fdt);
 	if (err < 0)
 		return err;
@@ -109,7 +127,7 @@ int board_fix_fdt(void *fdt)
 
 	err = riscv_board_reserved_mem_fixup(fdt);
 	if (err < 0) {
-		printf("failed to fixup DT for reserved memory: %d\n", err);
+		log_err("failed to fixup DT for reserved memory: %d\n", err);
 		return err;
 	}
 
@@ -127,14 +145,14 @@ int arch_fixup_fdt(void *blob)
 	size = fdt_totalsize(blob);
 	err  = fdt_open_into(blob, blob, size + 32);
 	if (err < 0) {
-		printf("Device Tree can't be expanded to accommodate new node");
+		log_err("Device Tree can't be expanded to accommodate new node");
 		return err;
 	}
 	chosen_offset = fdt_path_offset(blob, "/chosen");
 	if (chosen_offset < 0) {
 		err = fdt_add_subnode(blob, 0, "chosen");
 		if (err < 0) {
-			printf("chosen node can not be added\n");
+			log_err("chosen node cannot be added\n");
 			return err;
 		}
 	}

arch/sandbox/dts/test.dts

@@ -343,6 +343,26 @@
 			#gpio-cells = <1>;
 			gpio-bank-name = "a";
 			sandbox,gpio-count = <20>;
+			hog_input_active_low {
+				gpio-hog;
+				input;
+				gpios = <0 GPIO_ACTIVE_LOW>;
+			};
+			hog_input_active_high {
+				gpio-hog;
+				input;
+				gpios = <1 GPIO_ACTIVE_HIGH>;
+			};
+			hog_output_low {
+				gpio-hog;
+				output-low;
+				gpios = <2 GPIO_ACTIVE_HIGH>;
+			};
+			hog_output_high {
+				gpio-hog;
+				output-high;
+				gpios = <3 GPIO_ACTIVE_HIGH>;
+			};
 		};
 
 		gpio_b: extra-gpios {

board/advantech/imx8qm_rom7720_a1/README

@@ -29,6 +29,17 @@ $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin
 $ chmod +x firmware-imx-8.0.bin
 $ ./firmware-imx-8.0.bin
 
+Or use this to avoid running random scripts from the internet,
+but note that you must agree to the license the script displays:
+
+$ dd if=imx-sc-firmware-1.1.bin of=imx-sc-firmware-1.1.tar.bz2 bs=37185 skip=1
+$ tar -xf imx-sc-firmware-1.1.tar.bz2
+$ cp imx-sc-firmware-1.1/mx8qm-val-scfw-tcm.bin $(builddir)
+
+$ dd if=firmware-imx-8.0.bin of=firmware-imx-8.0.tar.bz2 bs=37180 skip=1
+$ tar -xf firmware-imx-8.0.tar.bz2
+$ cp firmware-imx-8.0/firmware/seco/mx8qm-ahab-container.img $(builddir)
+
 Build U-Boot
 ============
 

board/amlogic/p200/MAINTAINERS

@@ -7,3 +7,6 @@ F:	board/amlogic/p200/
 F:	configs/nanopi-k2_defconfig
 F:	configs/odroid-c2_defconfig
 F:	configs/p200_defconfig
+F:	doc/board/amlogic/p200.rst
+F:	doc/board/amlogic/nanopi-k2.rst
+F:	doc/board/amlogic/odroid-c2.rst

board/amlogic/p200/README.nanopi-k2

@@ -1,98 +0,0 @@
-U-Boot for NanoPi-K2
-====================
-
-NanoPi-K2 is a single board computer manufactured by FriendlyElec
-with the following specifications:
-
- - Amlogic S905 ARM Cortex-A53 quad-core SoC @ 1.5GHz
- - ARM Mali 450 GPU
- - 2GB DDR3 SDRAM
- - Gigabit Ethernet
- - HDMI 2.0 4K/60Hz display
- - 40-pin GPIO header
- - 4 x USB 2.0 Host, 1 x USB OTG
- - eMMC, microSD
- - Infrared receiver
-
-Schematics are available on the manufacturer website.
-
-Currently the u-boot port supports the following devices:
- - serial
- - eMMC, microSD
- - Ethernet
-
-u-boot compilation
-==================
-
- > export CROSS_COMPILE=aarch64-none-elf-
- > make nanopi-k2_defconfig
- > make
-
-Image creation
-==============
-
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
-
- > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
- > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
- > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
- > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
- > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
- > git clone https://github.com/BayLibre/u-boot.git -b libretech-cc amlogic-u-boot
- > git clone https://github.com/friendlyarm/u-boot.git -b nanopi-k2-v2015.01 amlogic-u-boot
- > cd amlogic-u-boot
- > sed -i 's/aarch64-linux-gnu-/aarch64-none-elf-/' Makefile
- > sed -i 's/arm-linux-/arm-none-eabi-/' arch/arm/cpu/armv8/gxb/firmware/scp_task/Makefile
- > make nanopi-k2_defconfig
- > make
- > export FIPDIR=$PWD/fip
-
-Go back to mainline U-Boot source tree then :
- > mkdir fip
-
- > cp $FIPDIR/gxb/bl2.bin fip/
- > cp $FIPDIR/gxb/acs.bin fip/
- > cp $FIPDIR/gxb/bl21.bin fip/
- > cp $FIPDIR/gxb/bl30.bin fip/
- > cp $FIPDIR/gxb/bl301.bin fip/
- > cp $FIPDIR/gxb/bl31.img fip/
- > cp u-boot.bin fip/bl33.bin
-
- > $FIPDIR/blx_fix.sh \
-	fip/bl30.bin \
-	fip/zero_tmp \
-	fip/bl30_zero.bin \
-	fip/bl301.bin \
-	fip/bl301_zero.bin \
-	fip/bl30_new.bin \
-	bl30
-
- > $FIPDIR/fip_create \
-	 --bl30 fip/bl30_new.bin \
-	 --bl31 fip/bl31.img \
-	 --bl33 fip/bl33.bin \
-	 fip/fip.bin
-
- > python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
-
- > $FIPDIR/blx_fix.sh \
-	fip/bl2_acs.bin \
-	fip/zero_tmp \
-	fip/bl2_zero.bin \
-	fip/bl21.bin \
-	fip/bl21_zero.bin \
-	fip/bl2_new.bin \
-	bl2
-
- > cat fip/bl2_new.bin fip/fip.bin > fip/boot_new.bin
-
- > $FIPDIR/gxb/aml_encrypt_gxb --bootsig \
-		--input fip/boot_new.bin
-		--output fip/u-boot.bin
-
-and then write the image to SD with:
-
- > DEV=/dev/your_sd_device
- > dd if=fip/u-boot.bin of=$DEV conv=fsync,notrunc bs=512 seek=1

board/amlogic/p200/README.p200

@@ -1,102 +0,0 @@
-U-Boot for Amlogic P200
-=======================
-
-P200 is a reference board manufactured by Amlogic with the following
-specifications:
-
- - Amlogic S905 ARM Cortex-A53 quad-core SoC @ 1.5GHz
- - ARM Mali 450 GPU
- - 2GB DDR3 SDRAM
- - Gigabit Ethernet
- - HDMI 2.0 4K/60Hz display
- - 2 x USB 2.0 Host
- - eMMC, microSD
- - Infrared receiver
- - SDIO WiFi Module
- - CVBS+Stereo Audio Jack
-
-Schematics are available from Amlogic on demand.
-
-Currently the u-boot port supports the following devices:
- - serial
- - eMMC, microSD
- - Ethernet
- - I2C
- - Regulators
- - Reset controller
- - Clock controller
- - USB Host
- - ADC
-
-u-boot compilation
-==================
-
- > export CROSS_COMPILE=aarch64-none-elf-
- > make p200_defconfig
- > make
-
-Image creation
-==============
-
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
-
- > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
- > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
- > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
- > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
- > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
- > git clone https://github.com/BayLibre/u-boot.git -b n-amlogic-openlinux-20170606 amlogic-u-boot
- > cd amlogic-u-boot
- > make gxb_p200_v1_defconfig
- > make
- > export FIPDIR=$PWD/fip
-
-Go back to mainline U-boot source tree then :
- > mkdir fip
-
- > cp $FIPDIR/gxl/bl2.bin fip/
- > cp $FIPDIR/gxl/acs.bin fip/
- > cp $FIPDIR/gxl/bl21.bin fip/
- > cp $FIPDIR/gxl/bl30.bin fip/
- > cp $FIPDIR/gxl/bl301.bin fip/
- > cp $FIPDIR/gxl/bl31.img fip/
- > cp u-boot.bin fip/bl33.bin
-
- > $FIPDIR/blx_fix.sh \
-	fip/bl30.bin \
-	fip/zero_tmp \
-	fip/bl30_zero.bin \
-	fip/bl301.bin \
-	fip/bl301_zero.bin \
-	fip/bl30_new.bin \
-	bl30
-
- > $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
-
- > $FIPDIR/blx_fix.sh \
-	fip/bl2_acs.bin \
-	fip/zero_tmp \
-	fip/bl2_zero.bin \
-	fip/bl21.bin \
-	fip/bl21_zero.bin \
-	fip/bl2_new.bin \
-	bl2
-
- > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin
- > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img
- > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin
- > $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
- > $FIPDIR/gxl/aml_encrypt_gxl --bootmk \
-		--output fip/u-boot.bin \
-		--bl2 fip/bl2.n.bin.sig \
-		--bl30 fip/bl30_new.bin.enc \
-		--bl31 fip/bl31.img.enc \
-		--bl33 fip/bl33.bin.enc
-
-and then write the image to SD with:
-
- > DEV=/dev/your_sd_device
- > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444

board/amlogic/p201/MAINTAINERS

@@ -4,3 +4,4 @@ S:	Maintained
 L:	u-boot-amlogic@groups.io
 F:	board/amlogic/p201/
 F:	configs/p201_defconfig
+F:	doc/board/amlogic/p201.rst

board/amlogic/p201/README.p201

@@ -1,102 +0,0 @@
-U-Boot for Amlogic P201
-=======================
-
-P201 is a reference board manufactured by Amlogic with the following
-specifications:
-
- - Amlogic S905 ARM Cortex-A53 quad-core SoC @ 1.5GHz
- - ARM Mali 450 GPU
- - 2GB DDR3 SDRAM
- - 10/100 Ethernet
- - HDMI 2.0 4K/60Hz display
- - 2 x USB 2.0 Host
- - eMMC, microSD
- - Infrared receiver
- - SDIO WiFi Module
- - CVBS+Stereo Audio Jack
-
-Schematics are available from Amlogic on demand.
-
-Currently the u-boot port supports the following devices:
- - serial
- - eMMC, microSD
- - Ethernet
- - I2C
- - Regulators
- - Reset controller
- - Clock controller
- - USB Host
- - ADC
-
-u-boot compilation
-==================
-
- > export CROSS_COMPILE=aarch64-none-elf-
- > make p201_defconfig
- > make
-
-Image creation
-==============
-
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
-
- > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
- > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
- > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
- > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
- > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
- > git clone https://github.com/BayLibre/u-boot.git -b n-amlogic-openlinux-20170606 amlogic-u-boot
- > cd amlogic-u-boot
- > make gxb_p201_v1_defconfig
- > make
- > export FIPDIR=$PWD/fip
-
-Go back to mainline U-boot source tree then :
- > mkdir fip
-
- > cp $FIPDIR/gxl/bl2.bin fip/
- > cp $FIPDIR/gxl/acs.bin fip/
- > cp $FIPDIR/gxl/bl21.bin fip/
- > cp $FIPDIR/gxl/bl30.bin fip/
- > cp $FIPDIR/gxl/bl301.bin fip/
- > cp $FIPDIR/gxl/bl31.img fip/
- > cp u-boot.bin fip/bl33.bin
-
- > $FIPDIR/blx_fix.sh \
-	fip/bl30.bin \
-	fip/zero_tmp \
-	fip/bl30_zero.bin \
-	fip/bl301.bin \
-	fip/bl301_zero.bin \
-	fip/bl30_new.bin \
-	bl30
-
- > $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
-
- > $FIPDIR/blx_fix.sh \
-	fip/bl2_acs.bin \
-	fip/zero_tmp \
-	fip/bl2_zero.bin \
-	fip/bl21.bin \
-	fip/bl21_zero.bin \
-	fip/bl2_new.bin \
-	bl2
-
- > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin
- > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img
- > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin
- > $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
- > $FIPDIR/gxl/aml_encrypt_gxl --bootmk \
-		--output fip/u-boot.bin \
-		--bl2 fip/bl2.n.bin.sig \
-		--bl30 fip/bl30_new.bin.enc \
-		--bl31 fip/bl31.img.enc \
-		--bl33 fip/bl33.bin.enc
-
-and then write the image to SD with:
-
- > DEV=/dev/your_sd_device
- > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444

board/amlogic/p212/MAINTAINERS

@@ -8,3 +8,7 @@ F:	configs/khadas-vim_defconfig
 F:	configs/libretech-ac_defconfig
 F:	configs/libretech-cc_defconfig
 F:	configs/p212_defconfig
+F:	doc/board/amlogic/p212.rst
+F:	doc/board/amlogic/libretech-ac.rst
+F:	doc/board/amlogic/libretech-cc.rst
+F:	doc/board/amlogic/khadas-vim.rst

board/amlogic/p212/README.khadas-vim

@@ -1,101 +0,0 @@
-U-Boot for Khadas VIM
-=======================
-
-Khadas VIM is an Open Source DIY Box manufactured by Shenzhen Wesion
-Technology Co., Ltd with the following specifications:
-
- - Amlogic S905X ARM Cortex-A53 quad-core SoC @ 1.5GHz
- - ARM Mali 450 GPU
- - 2GB DDR3 SDRAM
- - 10/100 Ethernet
- - HDMI 2.0 4K/60Hz display
- - 40-pin GPIO header
- - 2 x USB 2.0 Host, 1 x USB 2.0 Type-C OTG
- - 8GB/16GBeMMC
- - microSD
- - SDIO Wifi Module, Bluetooth
- - Two channels IR receiver
-
-Currently the u-boot port supports the following devices:
- - serial
- - eMMC, microSD
- - Ethernet
- - I2C
- - Regulators
- - Reset controller
- - Clock controller
- - USB Host
- - ADC
-
-U-Boot compilation
-==================
-
- > export CROSS_COMPILE=aarch64-none-elf-
- > make khadas-vim_defconfig
- > make
-
-Image creation
-==============
-
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
-
- > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
- > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
- > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
- > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
- > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
- > git clone https://github.com/khadas/u-boot -b Vim vim-u-boot
- > cd vim-u-boot
- > make kvim_defconfig
- > make CROSS_COMPILE=aarch64-none-elf-
- > export FIPDIR=$PWD/fip
-
-Go back to mainline U-Boot source tree then :
- > mkdir fip
-
- > cp $FIPDIR/gxl/bl2.bin fip/
- > cp $FIPDIR/gxl/acs.bin fip/
- > cp $FIPDIR/gxl/bl21.bin fip/
- > cp $FIPDIR/gxl/bl30.bin fip/
- > cp $FIPDIR/gxl/bl301.bin fip/
- > cp $FIPDIR/gxl/bl31.img fip/
- > cp u-boot.bin fip/bl33.bin
-
- > $FIPDIR/blx_fix.sh \
-	fip/bl30.bin \
-	fip/zero_tmp \
-	fip/bl30_zero.bin \
-	fip/bl301.bin \
-	fip/bl301_zero.bin \
-	fip/bl30_new.bin \
-	bl30
-
- > python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
-
- > $FIPDIR/blx_fix.sh \
-	fip/bl2_acs.bin \
-	fip/zero_tmp \
-	fip/bl2_zero.bin \
-	fip/bl21.bin \
-	fip/bl21_zero.bin \
-	fip/bl2_new.bin \
-	bl2
-
- > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin
- > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img
- > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin
- > $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
- > $FIPDIR/gxl/aml_encrypt_gxl --bootmk \
-		--output fip/u-boot.bin \
-		--bl2 fip/bl2.n.bin.sig \
-		--bl30 fip/bl30_new.bin.enc \
-		--bl31 fip/bl31.img.enc \
-		--bl33 fip/bl33.bin.enc
-
-and then write the image to SD with:
-
- > DEV=/dev/your_sd_device
- > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444

board/amlogic/p212/README.libretech-ac

@@ -1,102 +0,0 @@
-U-Boot for LibreTech AC
-=======================
-
-LibreTech AC is a single board computer manufactured by Libre Technology
-with the following specifications:
-
- - Amlogic S805X ARM Cortex-A53 quad-core SoC @ 1.2GHz
- - ARM Mali 450 GPU
- - 512MiB DDR4 SDRAM
- - 10/100 Ethernet
- - HDMI 2.0 4K/60Hz display
- - 40-pin GPIO header
- - 4 x USB 2.0 Host
- - eMMC, SPI NOR Flash
- - Infrared receiver
-
-Schematics are available on the manufacturer website.
-
-Currently the U-Boot port supports the following devices:
- - serial
- - eMMC
- - Ethernet
- - USB
-
-U-Boot compilation
-==================
-
- > export CROSS_COMPILE=aarch64-none-elf-
- > make libretech-ac_defconfig
- > make
-
-Image creation
-==============
-
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
-
- > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
- > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
- > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
- > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
- > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
- > git clone https://github.com/BayLibre/u-boot.git -b libretech-ac amlogic-u-boot
- > cd amlogic-u-boot
- > wget https://raw.githubusercontent.com/BayLibre/u-boot/libretech-cc/fip/blx_fix.sh
- > make libretech_ac_defconfig
- > make
- > export UBOOTDIR=$PWD
-
-Download the latest Amlogic Buildroot package, and extract it :
- > wget http://openlinux2.amlogic.com:8000/ARM/filesystem/Linux_BSP/buildroot_openlinux_kernel_4.9_fbdev_20180418.tar.gz
- > tar xfz buildroot_openlinux_kernel_4.9_fbdev_20180418.tar.gz buildroot_openlinux_kernel_4.9_fbdev_20180418/bootloader
- > export BRDIR=$PWD/buildroot_openlinux_kernel_4.9_fbdev_20180418
-
-Go back to mainline U-Boot source tree then :
- > mkdir fip
-
- > cp $UBOOTDIR/build/scp_task/bl301.bin fip/
- > cp $UBOOTDIR/build/board/amlogic/libretech_ac/firmware/bl21.bin fip/
- > cp $UBOOTDIR/build/board/amlogic/libretech_ac/firmware/acs.bin fip/
- > cp $BRDIR/bootloader/uboot-repo/bl2/bin/gxl/bl2.bin fip/
- > cp $BRDIR/bootloader/uboot-repo/bl30/bin/gxl/bl30.bin fip/
- > cp $BRDIR/bootloader/uboot-repo/bl31/bin/gxl/bl31.img fip/
- > cp u-boot.bin fip/bl33.bin
-
- > sh $UBOOTDIR/blx_fix.sh \
-	fip/bl30.bin \
-	fip/zero_tmp \
-	fip/bl30_zero.bin \
-	fip/bl301.bin \
-	fip/bl301_zero.bin \
-	fip/bl30_new.bin \
-	bl30
-
- > $BRDIR/bootloader/uboot-repo/fip/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
-
- > sh $UBOOTDIR/blx_fix.sh \
-	fip/bl2_acs.bin \
-	fip/zero_tmp \
-	fip/bl2_zero.bin \
-	fip/bl21.bin \
-	fip/bl21_zero.bin \
-	fip/bl2_new.bin \
-	bl2
-
- > $BRDIR/bootloader/uboot-repo/fip/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin
- > $BRDIR/bootloader/uboot-repo/fip/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img
- > $BRDIR/bootloader/uboot-repo/fip/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin
- > $BRDIR/bootloader/uboot-repo/fip/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
- > $BRDIR/bootloader/uboot-repo/fip/gxl/aml_encrypt_gxl --bootmk \
-		--output fip/u-boot.bin \
-		--bl2 fip/bl2.n.bin.sig \
-		--bl30 fip/bl30_new.bin.enc \
-		--bl31 fip/bl31.img.enc \
-		--bl33 fip/bl33.bin.enc
-
-and then write the image to SD with:
-
- > DEV=/dev/your_sd_device
- > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444

board/amlogic/p212/README.libretech-cc

@@ -1,134 +0,0 @@
-U-Boot for LibreTech CC
-=======================
-
-LibreTech CC is a single board computer manufactured by Libre Technology
-with the following specifications:
-
- - Amlogic S905X ARM Cortex-A53 quad-core SoC @ 1.5GHz
- - ARM Mali 450 GPU
- - 2GB DDR3 SDRAM
- - 10/100 Ethernet
- - HDMI 2.0 4K/60Hz display
- - 40-pin GPIO header
- - 4 x USB 2.0 Host
- - eMMC, microSD
- - Infrared receiver
-
-Schematics are available on the manufacturer website.
-
-Currently the U-Boot port supports the following devices:
- - serial
- - eMMC, microSD
- - Ethernet
- - I2C
- - Regulators
- - Reset controller
- - Clock controller
- - USB Host
- - ADC
-
-U-Boot compilation
-==================
-
- > export CROSS_COMPILE=aarch64-none-elf-
- > make libretech-cc_defconfig
- > make
-
-Image creation
-==============
-
-To boot the system, u-boot must be combined with several earlier stage
-bootloaders:
-
-* bl2.bin: vendor-provided binary blob
-* bl21.bin: built from vendor u-boot source
-* bl30.bin: vendor-provided binary blob
-* bl301.bin: built from vendor u-boot source
-* bl31.bin: vendor-provided binary blob
-* acs.bin: built from vendor u-boot source
-
-These binaries and the tools required below have been collected and prebuilt
-for convenience at <https://github.com/BayLibre/u-boot/releases/>
-
-Download and extract the libretech-cc release from there, and set FIPDIR to
-point to the `fip` subdirectory.
-
- > export FIPDIR=/path/to/extracted/fip
-
-Alternatively, you can obtain the original vendor u-boot tree which
-contains the required blobs and sources, and build yourself.
-Note that old compilers are required for this to build. The compilers here
-are suggested by Amlogic, and they are 32-bit x86 binaries.
-
- > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
- > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
- > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
- > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
- > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
- > git clone https://github.com/BayLibre/u-boot.git -b libretech-cc amlogic-u-boot
- > cd amlogic-u-boot
- > make libretech_cc_defconfig
- > make
- > export FIPDIR=$PWD/fip
-
-Once you have the binaries available (either through the prebuilt download,
-or having built the vendor u-boot yourself), you can then proceed to glue
-everything together. Go back to mainline U-Boot source tree then :
-
- > mkdir fip
-
- > cp $FIPDIR/gxl/bl2.bin fip/
- > cp $FIPDIR/gxl/acs.bin fip/
- > cp $FIPDIR/gxl/bl21.bin fip/
- > cp $FIPDIR/gxl/bl30.bin fip/
- > cp $FIPDIR/gxl/bl301.bin fip/
- > cp $FIPDIR/gxl/bl31.img fip/
- > cp u-boot.bin fip/bl33.bin
-
- > $FIPDIR/blx_fix.sh \
-	fip/bl30.bin \
-	fip/zero_tmp \
-	fip/bl30_zero.bin \
-	fip/bl301.bin \
-	fip/bl301_zero.bin \
-	fip/bl30_new.bin \
-	bl30
-
- > $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
-
- > $FIPDIR/blx_fix.sh \
-	fip/bl2_acs.bin \
-	fip/zero_tmp \
-	fip/bl2_zero.bin \
-	fip/bl21.bin \
-	fip/bl21_zero.bin \
-	fip/bl2_new.bin \
-	bl2
-
- > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin
- > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img
- > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin
- > $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
- > $FIPDIR/gxl/aml_encrypt_gxl --bootmk \
-		--output fip/u-boot.bin \
-		--bl2 fip/bl2.n.bin.sig \
-		--bl30 fip/bl30_new.bin.enc \
-		--bl31 fip/bl31.img.enc \
-		--bl33 fip/bl33.bin.enc
-
-and then write the image to SD with:
-
- > DEV=/dev/your_sd_device
- > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
-
-Note that Amlogic provides aml_encrypt_gxl as a 32-bit x86 binary with no
-source code. Should you prefer to avoid that, there are open source reverse
-engineered versions available:
-
-1. gxlimg <https://github.com/repk/gxlimg>, which comes with a handy
-   Makefile that automates the whole process.
-2. meson-tools <https://github.com/afaerber/meson-tools>
-
-However, these community-developed alternatives are not endorsed by or
-supported by Amlogic.

board/amlogic/p212/README.p212

@@ -1,102 +0,0 @@
-U-Boot for Amlogic P212
-=======================
-
-P212 is a reference board manufactured by Amlogic with the following
-specifications:
-
- - Amlogic S905X ARM Cortex-A53 quad-core SoC @ 1.5GHz
- - ARM Mali 450 GPU
- - 2GB DDR3 SDRAM
- - 10/100 Ethernet
- - HDMI 2.0 4K/60Hz display
- - 2 x USB 2.0 Host
- - eMMC, microSD
- - Infrared receiver
- - SDIO WiFi Module
- - CVBS+Stereo Audio Jack
-
-Schematics are available from Amlogic on demand.
-
-Currently the u-boot port supports the following devices:
- - serial
- - eMMC, microSD
- - Ethernet
- - I2C
- - Regulators
- - Reset controller
- - Clock controller
- - USB Host
- - ADC
-
-u-boot compilation
-==================
-
- > export CROSS_COMPILE=aarch64-none-elf-
- > make p212_defconfig
- > make
-
-Image creation
-==============
-
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
-
- > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
- > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
- > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
- > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
- > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
- > git clone https://github.com/BayLibre/u-boot.git -b n-amlogic-openlinux-20170606 amlogic-u-boot
- > cd amlogic-u-boot
- > make gxl_p212_v1_defconfig
- > make
- > export FIPDIR=$PWD/fip
-
-Go back to mainline U-boot source tree then :
- > mkdir fip
-
- > cp $FIPDIR/gxl/bl2.bin fip/
- > cp $FIPDIR/gxl/acs.bin fip/
- > cp $FIPDIR/gxl/bl21.bin fip/
- > cp $FIPDIR/gxl/bl30.bin fip/
- > cp $FIPDIR/gxl/bl301.bin fip/
- > cp $FIPDIR/gxl/bl31.img fip/
- > cp u-boot.bin fip/bl33.bin
-
- > $FIPDIR/blx_fix.sh \
-	fip/bl30.bin \
-	fip/zero_tmp \
-	fip/bl30_zero.bin \
-	fip/bl301.bin \
-	fip/bl301_zero.bin \
-	fip/bl30_new.bin \
-	bl30
-
- > $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
-
- > $FIPDIR/blx_fix.sh \
-	fip/bl2_acs.bin \
-	fip/zero_tmp \
-	fip/bl2_zero.bin \
-	fip/bl21.bin \
-	fip/bl21_zero.bin \
-	fip/bl2_new.bin \
-	bl2
-
- > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin
- > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img
- > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin
- > $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
- > $FIPDIR/gxl/aml_encrypt_gxl --bootmk \
-		--output fip/u-boot.bin \
-		--bl2 fip/bl2.n.bin.sig \
-		--bl30 fip/bl30_new.bin.enc \
-		--bl31 fip/bl31.img.enc \
-		--bl33 fip/bl33.bin.enc
-
-and then write the image to SD with:
-
- > DEV=/dev/your_sd_device
- > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444

board/amlogic/q200/MAINTAINERS

@@ -7,3 +7,4 @@ F:	include/configs/q200.h
 F:	configs/khadas-vim2_defconfig
 F:	configs/libretech-s905d-pc_defconfig
 F:	configs/libretech-s912-pc_defconfig
+F:	doc/board/amlogic/khadas-vim2.rst

board/amlogic/q200/README.khadas-vim2

@@ -1,102 +0,0 @@
-U-Boot for Khadas VIM2
-=======================
-
-Khadas VIM2 is an Open Source DIY Box manufactured by Shenzhen Wesion
-Technology Co., Ltd with the following specifications:
-
- - Amlogic S912 ARM Cortex-A53 octo-core SoC @ 1.5GHz
- - ARM Mali T860 GPU
- - 2/3GB DDR4 SDRAM
- - 10/100/1000 Ethernet
- - HDMI 2.0 4K/60Hz display
- - 40-pin GPIO header
- - 2 x USB 2.0 Host, 1 x USB 2.0 Type-C OTG
- - 16GB/32GB/64GB eMMC
- - 2MB SPI Flash
- - microSD
- - SDIO Wifi Module, Bluetooth
- - Two channels IR receiver
-
-Currently the u-boot port supports the following devices:
- - serial
- - eMMC, microSD
- - Ethernet
- - I2C
- - Regulators
- - Reset controller
- - Clock controller
- - USB Host
- - ADC
-
-U-Boot compilation
-==================
-
- > export CROSS_COMPILE=aarch64-none-elf-
- > make khadas-vim2_defconfig
- > make
-
-Image creation
-==============
-
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
-
- > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
- > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
- > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
- > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
- > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
- > git clone https://github.com/khadas/u-boot -b khadas-vim-v2015.01 vim-u-boot
- > cd vim-u-boot
- > make kvim2_defconfig
- > make
- > export FIPDIR=$PWD/fip
-
-Go back to mainline U-Boot source tree then :
- > mkdir fip
-
- > cp $FIPDIR/gxl/bl2.bin fip/
- > cp $FIPDIR/gxl/acs.bin fip/
- > cp $FIPDIR/gxl/bl21.bin fip/
- > cp $FIPDIR/gxl/bl30.bin fip/
- > cp $FIPDIR/gxl/bl301.bin fip/
- > cp $FIPDIR/gxl/bl31.img fip/
- > cp u-boot.bin fip/bl33.bin
-
- > $FIPDIR/blx_fix.sh \
-	fip/bl30.bin \
-	fip/zero_tmp \
-	fip/bl30_zero.bin \
-	fip/bl301.bin \
-	fip/bl301_zero.bin \
-	fip/bl30_new.bin \
-	bl30
-
- > python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
-
- > $FIPDIR/blx_fix.sh \
-	fip/bl2_acs.bin \
-	fip/zero_tmp \
-	fip/bl2_zero.bin \
-	fip/bl21.bin \
-	fip/bl21_zero.bin \
-	fip/bl2_new.bin \
-	bl2
-
- > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin
- > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img
- > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin
- > $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
- > $FIPDIR/gxl/aml_encrypt_gxl --bootmk \
-		--output fip/u-boot.bin \
-		--bl2 fip/bl2.n.bin.sig \
-		--bl30 fip/bl30_new.bin.enc \
-		--bl31 fip/bl31.img.enc \
-		--bl33 fip/bl33.bin.enc
-
-and then write the image to SD with:
-
- > DEV=/dev/your_sd_device
- > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444

board/amlogic/q200/README.q200

@@ -1,101 +0,0 @@
-U-Boot for Amlogic Q200
-=======================
-
-Q200 is a reference board manufactured by Amlogic with the following
-specifications:
-
- - Amlogic S912 ARM Cortex-A53 octo-core SoC @ 1.5GHz
- - ARM Mali T860 GPU
- - 2/3GB DDR4 SDRAM
- - 10/100/1000 Ethernet
- - HDMI 2.0 4K/60Hz display
- - 2 x USB 2.0 Host, 1 x USB 2.0 Device
- - 16GB/32GB/64GB eMMC
- - 2MB SPI Flash
- - microSD
- - SDIO Wifi Module, Bluetooth
- - IR receiver
-
-Currently the u-boot port supports the following devices:
- - serial
- - eMMC, microSD
- - Ethernet
- - I2C
- - Regulators
- - Reset controller
- - Clock controller
- - USB Host
- - ADC
-
-U-Boot compilation
-==================
-
- > export CROSS_COMPILE=aarch64-none-elf-
- > make khadas-vim2_defconfig
- > make
-
-Image creation
-==============
-
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
-
- > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
- > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
- > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
- > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
- > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
- > git clone https://github.com/BayLibre/u-boot.git -b n-amlogic-openlinux-20170606 amlogic-u-boot
- > cd amlogic-u-boot
- > make gxm_q200_v1_defconfig
- > make
- > export FIPDIR=$PWD/fip
-
-Go back to mainline U-Boot source tree then :
- > mkdir fip
-
- > cp $FIPDIR/gxl/bl2.bin fip/
- > cp $FIPDIR/gxl/acs.bin fip/
- > cp $FIPDIR/gxl/bl21.bin fip/
- > cp $FIPDIR/gxl/bl30.bin fip/
- > cp $FIPDIR/gxl/bl301.bin fip/
- > cp $FIPDIR/gxl/bl31.img fip/
- > cp u-boot.bin fip/bl33.bin
-
- > $FIPDIR/blx_fix.sh \
-	fip/bl30.bin \
-	fip/zero_tmp \
-	fip/bl30_zero.bin \
-	fip/bl301.bin \
-	fip/bl301_zero.bin \
-	fip/bl30_new.bin \
-	bl30
-
- > python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
-
- > $FIPDIR/blx_fix.sh \
-	fip/bl2_acs.bin \
-	fip/zero_tmp \
-	fip/bl2_zero.bin \
-	fip/bl21.bin \
-	fip/bl21_zero.bin \
-	fip/bl2_new.bin \
-	bl2
-
- > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin
- > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img
- > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin
- > $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
- > $FIPDIR/gxl/aml_encrypt_gxl --bootmk \
-		--output fip/u-boot.bin \
-		--bl2 fip/bl2.n.bin.sig \
-		--bl30 fip/bl30_new.bin.enc \
-		--bl31 fip/bl31.img.enc \
-		--bl33 fip/bl33.bin.enc
-
-and then write the image to SD with:
-
- > DEV=/dev/your_sd_device
- > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444

board/amlogic/s400/MAINTAINERS

@@ -5,3 +5,4 @@ L:	u-boot-amlogic@groups.io
 F:	board/amlogic/s400/
 F:	include/configs/s400.h
 F:	configs/s400_defconfig
+F:	doc/board/amlogic/s400.rst

board/amlogic/s400/README

@@ -1,109 +0,0 @@
-U-Boot for Amlogic S400
-=======================
-
-S400 is a reference board manufactured by Amlogic with the following
-specifications:
-
- - Amlogic A113DX ARM Cortex-A53 quad-core SoC @ 1.2GHz
- - 1GB DDR4 SDRAM
- - 10/100 Ethernet
- - 2 x USB 2.0 Host
- - eMMC
- - Infrared receiver
- - SDIO WiFi Module
- - MIPI DSI Connector
- - Audio HAT Connector
- - PCI-E M.2 Connectors
-
-Schematics are available from Amlogic on demand.
-
-Currently the u-boot port supports the following devices:
- - serial
- - eMMC
- - Ethernet
- - I2C
- - Regulators
- - Reset controller
- - Clock controller
- - USB Host
- - ADC
-
-u-boot compilation
-==================
-
- > export CROSS_COMPILE=aarch64-none-elf-
- > make s400_defconfig
- > make
-
-Image creation
-==============
-
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
-
- > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
- > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
- > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
- > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
- > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
- > git clone https://github.com/BayLibre/u-boot.git -b n-amlogic-openlinux-20170606 amlogic-u-boot
- > cd amlogic-u-boot
- > make axg_s400_v1_defconfig
- > make
- > export FIPDIR=$PWD/fip
-
-Go back to mainline U-boot source tree then :
- > mkdir fip
-
- > cp $FIPDIR/axg/bl2.bin fip/
- > cp $FIPDIR/axg/acs.bin fip/
- > cp $FIPDIR/axg/bl21.bin fip/
- > cp $FIPDIR/axg/bl30.bin fip/
- > cp $FIPDIR/axg/bl301.bin fip/
- > cp $FIPDIR/axg/bl31.img fip/
- > cp u-boot.bin fip/bl33.bin
-
- > $FIPDIR/blx_fix.sh \
-	fip/bl30.bin \
-	fip/zero_tmp \
-	fip/bl30_zero.bin \
-	fip/bl301.bin \
-	fip/bl301_zero.bin \
-	fip/bl30_new.bin \
-	bl30
-
- > $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
-
- > $FIPDIR/blx_fix.sh \
-	fip/bl2_acs.bin \
-	fip/zero_tmp \
-	fip/bl2_zero.bin \
-	fip/bl21.bin \
-	fip/bl21_zero.bin \
-	fip/bl2_new.bin \
-	bl2
-
- > $FIPDIR/axg/aml_encrypt_axg --bl3sig --input fip/bl30_new.bin \
-					--output fip/bl30_new.bin.enc \
-					--level v3 --type bl30
- > $FIPDIR/axg/aml_encrypt_axg --bl3sig --input fip/bl31.img \
-					--output fip/bl31.img.enc \
-					--level v3 --type bl31
- > $FIPDIR/axg/aml_encrypt_axg --bl3sig --input fip/bl33.bin --compress lz4 \
-					--output fip/bl33.bin.enc \
-					--level v3 --type bl33
- > $FIPDIR/axg/aml_encrypt_axg --bl2sig --input fip/bl2_new.bin \
-					--output fip/bl2.n.bin.sig
- > $FIPDIR/axg/aml_encrypt_axg --bootmk \
-		--output fip/u-boot.bin \
-		--bl2 fip/bl2.n.bin.sig \
-		--bl30 fip/bl30_new.bin.enc \
-		--bl31 fip/bl31.img.enc \
-		--bl33 fip/bl33.bin.enc --level v3
-
-and then write the image to SD with:
-
- > DEV=/dev/your_sd_device
- > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444

board/amlogic/sei510/MAINTAINERS

@@ -5,3 +5,4 @@ L:	u-boot-amlogic@groups.io
 F:	board/amlogic/sei510/
 F:	configs/sei510_defconfig
 F:	include/configs/sei510.h
+F:	doc/board/amlogic/sei510.rst

board/amlogic/sei510/README

@@ -1,122 +0,0 @@
-U-Boot for Amlogic SEI510
-=======================
-
-SEI510 is a customer board manufactured by SEI Robotics with the following
-specifications:
-
- - Amlogic S905X2 ARM Cortex-A53 quad-core SoC
- - 2GB DDR4 SDRAM
- - 10/100 Ethernet (Internal PHY)
- - 1 x USB 3.0 Host
- - eMMC
- - SDcard
- - Infrared receiver
- - SDIO WiFi Module
-
-Currently the u-boot port supports the following devices:
- - serial
- - Ethernet
- - Regulators
- - Clock controller
-
-u-boot compilation
-==================
-
- > export CROSS_COMPILE=aarch64-none-elf-
- > make sei510_defconfig
- > make
-
-Image creation
-==============
-
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
-
- > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
- > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
- > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
- > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
- > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
- > git clone https://github.com/BayLibre/u-boot.git -b buildroot-openlinux-20180418 amlogic-u-boot
- > cd amlogic-u-boot
- > make g12a_u200_v1_defconfig
- > make
- > export UBOOTDIR=$PWD
-
-Download the latest Amlogic Buildroot package, and extract it :
- > wget http://openlinux2.amlogic.com:8000/ARM/filesystem/Linux_BSP/buildroot_openlinux_kernel_4.9_fbdev_20180706.tar.gz
- > tar xfz buildroot_openlinux_kernel_4.9_fbdev_20180706.tar.gz buildroot_openlinux_kernel_4.9_fbdev_20180706/bootloader
- > export BRDIR=$PWD/buildroot_openlinux_kernel_4.9_fbdev_20180706
- > export FIPDIR=$BRDIR/bootloader/uboot-repo/fip
-
-Go back to mainline U-Boot source tree then :
- > mkdir fip
-
- > wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh
- > cp $UBOOTDIR/build/scp_task/bl301.bin fip/
- > cp $UBOOTDIR/build/board/amlogic/g12a_u200_v1/firmware/acs.bin fip/
- > cp $BRDIR/bootloader/uboot-repo/bl2/bin/g12a/bl2.bin fip/
- > cp $BRDIR/bootloader/uboot-repo/bl30/bin/g12a/bl30.bin fip/
- > cp $BRDIR/bootloader/uboot-repo/bl31_1.3/bin/g12a/bl31.img fip/
- > cp $FIPDIR/g12a/ddr3_1d.fw fip/
- > cp $FIPDIR/g12a/ddr4_1d.fw fip/
- > cp $FIPDIR/g12a/ddr4_2d.fw fip/
- > cp $FIPDIR/g12a/diag_lpddr4.fw fip/
- > cp $FIPDIR/g12a/lpddr4_1d.fw fip/
- > cp $FIPDIR/g12a/lpddr4_2d.fw fip/
- > cp $FIPDIR/g12a/piei.fw fip/
- > cp u-boot.bin fip/bl33.bin
-
- > sh fip/blx_fix.sh \
-	fip/bl30.bin \
-	fip/zero_tmp \
-	fip/bl30_zero.bin \
-	fip/bl301.bin \
-	fip/bl301_zero.bin \
-	fip/bl30_new.bin \
-	bl30
-
- > sh fip/blx_fix.sh \
-	fip/bl2.bin \
-	fip/zero_tmp \
-	fip/bl2_zero.bin \
-	fip/acs.bin \
-	fip/bl21_zero.bin \
-	fip/bl2_new.bin \
-	bl2
-
- > $FIPDIR/g12a/aml_encrypt_g12a --bl30sig --input fip/bl30_new.bin \
-					--output fip/bl30_new.bin.g12a.enc \
-					--level v3
- > $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl30_new.bin.g12a.enc \
-					--output fip/bl30_new.bin.enc \
-					--level v3 --type bl30
- > $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl31.img \
-					--output fip/bl31.img.enc \
-					--level v3 --type bl31
- > $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl33.bin --compress lz4 \
-					--output fip/bl33.bin.enc \
-					--level v3 --type bl33
- > $FIPDIR/g12a/aml_encrypt_g12a --bl2sig --input fip/bl2_new.bin \
-					--output fip/bl2.n.bin.sig
- > $FIPDIR/g12a/aml_encrypt_g12a --bootmk \
-		--output fip/u-boot.bin \
-		--bl2 fip/bl2.n.bin.sig \
-		--bl30 fip/bl30_new.bin.enc \
-		--bl31 fip/bl31.img.enc \
-		--bl33 fip/bl33.bin.enc \
-		--ddrfw1 fip/ddr4_1d.fw \
-		--ddrfw2 fip/ddr4_2d.fw \
-		--ddrfw3 fip/ddr3_1d.fw \
-		--ddrfw4 fip/piei.fw \
-		--ddrfw5 fip/lpddr4_1d.fw \
-		--ddrfw6 fip/lpddr4_2d.fw \
-		--ddrfw7 fip/diag_lpddr4.fw \
-		--level v3
-
-and then write the image to SD with:
-
- > DEV=/dev/your_sd_device
- > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444

board/amlogic/sei610/MAINTAINERS

@@ -5,3 +5,4 @@ L:	u-boot-amlogic@groups.io
 F:	board/amlogic/sei610/
 F:	configs/sei610_defconfig
 F:	include/configs/sei610.h
+F:	doc/board/amlogic/sei610.rst

board/amlogic/sei610/README

@@ -1,118 +0,0 @@
-U-Boot for Amlogic SEI610
-=========================
-
-SEI610 is a customer board manufactured by SEI Robotics with the following
-specifications:
-
- - Amlogic S905X3 ARM Cortex-A55 quad-core SoC
- - 2GB DDR4 SDRAM
- - 10/100 Ethernet (Internal PHY)
- - 1 x USB 3.0 Host
- - 1 x USB Type-C DRD
- - 1 x FTDI USB Serial Debug Interface
- - eMMC
- - SDcard
- - Infrared receiver
- - SDIO WiFi Module
-
-u-boot compilation
-==================
-
- > export CROSS_COMPILE=aarch64-none-elf-
- > make sei610_defconfig
- > make
-
-Image creation
-==============
-
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
-
- > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
- > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
- > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
- > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
- > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
- > git clone https://github.com/BayLibre/u-boot.git -b buildroot-openlinux-4.9-g12a-201904 amlogic-u-boot
- > cd amlogic-u-boot
- > make sm1_ac200_v1_defconfig
- > make
- > export UBOOTDIR=$PWD
-
-Download the latest Amlogic Buildroot package, and extract it :
- > wget http://openlinux2.amlogic.com:8000/ARM/filesystem/buildroot-openlinux-A113-201901.tgz
- > tar xfz buildroot-openlinux-A113-201901.tgz buildroot-openlinux-A113-201901/bootloader
- > export BRDIR=$PWD/buildroot-openlinux-A113-201901
- > export FIPDIR=$BRDIR/bootloader/uboot-repo/fip
-
-Go back to mainline U-Boot source tree then :
- > mkdir fip
-
- > wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh
- > cp $UBOOTDIR/build/scp_task/bl301.bin fip/
- > cp $UBOOTDIR/build/board/amlogic/g12a_u200_v1/firmware/acs.bin fip/
- > cp $BRDIR/bootloader/uboot-repo/bl2/bin/g12a/bl2.bin fip/
- > cp $BRDIR/bootloader/uboot-repo/bl30/bin/g12a/bl30.bin fip/
- > cp $BRDIR/bootloader/uboot-repo/bl31_1.3/bin/g12a/bl31.img fip/
- > cp $FIPDIR/g12a/ddr3_1d.fw fip/
- > cp $FIPDIR/g12a/ddr4_1d.fw fip/
- > cp $FIPDIR/g12a/ddr4_2d.fw fip/
- > cp $FIPDIR/g12a/diag_lpddr4.fw fip/
- > cp $FIPDIR/g12a/lpddr4_1d.fw fip/
- > cp $FIPDIR/g12a/lpddr4_2d.fw fip/
- > cp $FIPDIR/g12a/piei.fw fip/
- > cp u-boot.bin fip/bl33.bin
-
- > sh fip/blx_fix.sh \
-	fip/bl30.bin \
-	fip/zero_tmp \
-	fip/bl30_zero.bin \
-	fip/bl301.bin \
-	fip/bl301_zero.bin \
-	fip/bl30_new.bin \
-	bl30
-
- > sh fip/blx_fix.sh \
-	fip/bl2.bin \
-	fip/zero_tmp \
-	fip/bl2_zero.bin \
-	fip/acs.bin \
-	fip/bl21_zero.bin \
-	fip/bl2_new.bin \
-	bl2
-
- > $FIPDIR/g12a/aml_encrypt_g12a --bl30sig --input fip/bl30_new.bin \
-					--output fip/bl30_new.bin.g12a.enc \
-					--level v3
- > $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl30_new.bin.g12a.enc \
-					--output fip/bl30_new.bin.enc \
-					--level v3 --type bl30
- > $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl31.img \
-					--output fip/bl31.img.enc \
-					--level v3 --type bl31
- > $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl33.bin --compress lz4 \
-					--output fip/bl33.bin.enc \
-					--level v3 --type bl33
- > $FIPDIR/g12a/aml_encrypt_g12a --bl2sig --input fip/bl2_new.bin \
-					--output fip/bl2.n.bin.sig
- > $FIPDIR/g12a/aml_encrypt_g12a --bootmk \
-		--output fip/u-boot.bin \
-		--bl2 fip/bl2.n.bin.sig \
-		--bl30 fip/bl30_new.bin.enc \
-		--bl31 fip/bl31.img.enc \
-		--bl33 fip/bl33.bin.enc \
-		--ddrfw1 fip/ddr4_1d.fw \
-		--ddrfw2 fip/ddr4_2d.fw \
-		--ddrfw3 fip/ddr3_1d.fw \
-		--ddrfw4 fip/piei.fw \
-		--ddrfw5 fip/lpddr4_1d.fw \
-		--ddrfw6 fip/lpddr4_2d.fw \
-		--ddrfw7 fip/diag_lpddr4.fw \
-		--level v3
-
-and then write the image to SD with:
-
- > DEV=/dev/your_sd_device
- > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444

board/amlogic/u200/MAINTAINERS

@@ -4,3 +4,4 @@ S:	Maintained
 L:	u-boot-amlogic@groups.io
 F:	board/amlogic/u200/
 F:	configs/u200_defconfig
+F:	doc/board/amlogic/u200.rst

board/amlogic/u200/README

@@ -1,127 +0,0 @@
-U-Boot for Amlogic U200
-=======================
-
-U200 is a reference board manufactured by Amlogic with the following
-specifications:
-
- - Amlogic S905D2 ARM Cortex-A53 quad-core SoC
- - 2GB DDR4 SDRAM
- - 10/100 Ethernet (Internal PHY)
- - 1 x USB 3.0 Host
- - eMMC
- - SDcard
- - Infrared receiver
- - SDIO WiFi Module
- - MIPI DSI Connector
- - Audio HAT Connector
- - PCI-E M.2 Connector
-
-Schematics are available from Amlogic on demand.
-
-Currently the u-boot port supports the following devices:
- - serial
- - Ethernet
- - Regulators
- - Clock controller
-
-u-boot compilation
-==================
-
- > export CROSS_COMPILE=aarch64-none-elf-
- > make u200_defconfig
- > make
-
-Image creation
-==============
-
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
-
- > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
- > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
- > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
- > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
- > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
- > git clone https://github.com/BayLibre/u-boot.git -b buildroot-openlinux-20180418 amlogic-u-boot
- > cd amlogic-u-boot
- > make g12a_u200_v1_defconfig
- > make
- > export UBOOTDIR=$PWD
-
-Download the latest Amlogic Buildroot package, and extract it :
- > wget http://openlinux2.amlogic.com:8000/ARM/filesystem/Linux_BSP/buildroot_openlinux_kernel_4.9_fbdev_20180706.tar.gz
- > tar xfz buildroot_openlinux_kernel_4.9_fbdev_20180706.tar.gz buildroot_openlinux_kernel_4.9_fbdev_20180706/bootloader
- > export BRDIR=$PWD/buildroot_openlinux_kernel_4.9_fbdev_20180706
- > export FIPDIR=$BRDIR/bootloader/uboot-repo/fip
-
-Go back to mainline U-Boot source tree then :
- > mkdir fip
-
- > wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh
- > cp $UBOOTDIR/build/scp_task/bl301.bin fip/
- > cp $UBOOTDIR/build/board/amlogic/g12a_u200_v1/firmware/acs.bin fip/
- > cp $BRDIR/bootloader/uboot-repo/bl2/bin/g12a/bl2.bin fip/
- > cp $BRDIR/bootloader/uboot-repo/bl30/bin/g12a/bl30.bin fip/
- > cp $BRDIR/bootloader/uboot-repo/bl31_1.3/bin/g12a/bl31.img fip/
- > cp $FIPDIR/g12a/ddr3_1d.fw fip/
- > cp $FIPDIR/g12a/ddr4_1d.fw fip/
- > cp $FIPDIR/g12a/ddr4_2d.fw fip/
- > cp $FIPDIR/g12a/diag_lpddr4.fw fip/
- > cp $FIPDIR/g12a/lpddr4_1d.fw fip/
- > cp $FIPDIR/g12a/lpddr4_2d.fw fip/
- > cp $FIPDIR/g12a/piei.fw fip/
- > cp u-boot.bin fip/bl33.bin
-
- > sh fip/blx_fix.sh \
-	fip/bl30.bin \
-	fip/zero_tmp \
-	fip/bl30_zero.bin \
-	fip/bl301.bin \
-	fip/bl301_zero.bin \
-	fip/bl30_new.bin \
-	bl30
-
- > sh fip/blx_fix.sh \
-	fip/bl2.bin \
-	fip/zero_tmp \
-	fip/bl2_zero.bin \
-	fip/acs.bin \
-	fip/bl21_zero.bin \
-	fip/bl2_new.bin \
-	bl2
-
- > $FIPDIR/g12a/aml_encrypt_g12a --bl30sig --input fip/bl30_new.bin \
-					--output fip/bl30_new.bin.g12a.enc \
-					--level v3
- > $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl30_new.bin.g12a.enc \
-					--output fip/bl30_new.bin.enc \
-					--level v3 --type bl30
- > $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl31.img \
-					--output fip/bl31.img.enc \
-					--level v3 --type bl31
- > $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl33.bin --compress lz4 \
-					--output fip/bl33.bin.enc \
-					--level v3 --type bl33
- > $FIPDIR/g12a/aml_encrypt_g12a --bl2sig --input fip/bl2_new.bin \
-					--output fip/bl2.n.bin.sig
- > $FIPDIR/g12a/aml_encrypt_g12a --bootmk \
-		--output fip/u-boot.bin \
-		--bl2 fip/bl2.n.bin.sig \
-		--bl30 fip/bl30_new.bin.enc \
-		--bl31 fip/bl31.img.enc \
-		--bl33 fip/bl33.bin.enc \
-		--ddrfw1 fip/ddr4_1d.fw \
-		--ddrfw2 fip/ddr4_2d.fw \
-		--ddrfw3 fip/ddr3_1d.fw \
-		--ddrfw4 fip/piei.fw \
-		--ddrfw5 fip/lpddr4_1d.fw \
-		--ddrfw6 fip/lpddr4_2d.fw \
-		--ddrfw7 fip/diag_lpddr4.fw \
-		--level v3
-
-and then write the image to SD with:
-
- > DEV=/dev/your_sd_device
- > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444

board/amlogic/w400/MAINTAINERS

@@ -6,3 +6,7 @@ F:	board/amlogic/w400/
 F:	configs/khadas-vim3_defconfig
 F:	configs/khadas-vim3l_defconfig
 F:	configs/odroid-n2_defconfig
+F:	doc/board/amlogic/w400.rst
+F:	doc/board/amlogic/khadas-vim3.rst
+F:	doc/board/amlogic/khadas-vim3l.rst
+F:	doc/board/amlogic/odroid-n2.rst

board/amlogic/w400/README.khadas-vim3

@@ -1,131 +0,0 @@
-U-Boot for Khadas VIM3
-======================
-
-Khadas VIM3 is a single board computer manufactured by Shenzhen Wesion
-Technology Co., Ltd. with the following specifications:
-
- - Amlogic A311D Arm Cortex-A53 dual-core + Cortex-A73 quad-core SoC
- - 4GB LPDDR4 SDRAM
- - Gigabit Ethernet
- - HDMI 2.1 display
- - 40-pin GPIO header
- - 1 x USB 3.0 Host, 1 x USB 2.0 Host
- - eMMC, microSD
- - M.2
- - Infrared receiver
-
-Schematics are available on the manufacturer website.
-
-Currently the U-Boot port supports the following devices:
- - serial
- - eMMC, microSD
- - Ethernet
- - I2C
- - Regulators
- - Reset controller
- - Clock controller
- - ADC
-
-u-boot compilation
-==================
-
- > export CROSS_COMPILE=aarch64-none-elf-
- > make khadas-vim3_defconfig
- > make
-
-Image creation
-==============
-
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
-
- > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
- > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
- > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
- > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
- > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
-
- > DIR=vim3-u-boot
- > git clone --depth 1 \
-       https://github.com/khadas/u-boot.git -b khadas-vims-v2015.01 \
-       $DIR
-
- > cd vim3-u-boot
- > make kvim3_defconfig
- > make
- > export UBOOTDIR=$PWD
-
- Go back to mainline U-Boot source tree then :
- > mkdir fip
-
- > cp $UBOOTDIR/build/scp_task/bl301.bin fip/
- > cp $UBOOTDIR/build/board/khadas/kvim3/firmware/acs.bin fip/
- > cp $UBOOTDIR/fip/g12b/bl2.bin fip/
- > cp $UBOOTDIR/fip/g12b/bl30.bin fip/
- > cp $UBOOTDIR/fip/g12b/bl31.img fip/
- > cp $UBOOTDIR/fip/g12b/ddr3_1d.fw fip/
- > cp $UBOOTDIR/fip/g12b/ddr4_1d.fw fip/
- > cp $UBOOTDIR/fip/g12b/ddr4_2d.fw fip/
- > cp $UBOOTDIR/fip/g12b/diag_lpddr4.fw fip/
- > cp $UBOOTDIR/fip/g12b/lpddr3_1d.fw fip/
- > cp $UBOOTDIR/fip/g12b/lpddr4_1d.fw fip/
- > cp $UBOOTDIR/fip/g12b/lpddr4_2d.fw fip/
- > cp $UBOOTDIR/fip/g12b/piei.fw fip/
- > cp $UBOOTDIR/fip/g12b/aml_ddr.fw fip/
- > cp u-boot.bin fip/bl33.bin
-
- > sh fip/blx_fix.sh \
-	fip/bl30.bin \
-	fip/zero_tmp \
-	fip/bl30_zero.bin \
-	fip/bl301.bin \
-	fip/bl301_zero.bin \
-	fip/bl30_new.bin \
-	bl30
-
- > sh fip/blx_fix.sh \
-	fip/bl2.bin \
-	fip/zero_tmp \
-	fip/bl2_zero.bin \
-	fip/acs.bin \
-	fip/bl21_zero.bin \
-	fip/bl2_new.bin \
-	bl2
-
- > $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl30sig --input fip/bl30_new.bin \
-					--output fip/bl30_new.bin.g12a.enc \
-					--level v3
- > $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl30_new.bin.g12a.enc \
-					--output fip/bl30_new.bin.enc \
-					--level v3 --type bl30
- > $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl31.img \
-					--output fip/bl31.img.enc \
-					--level v3 --type bl31
- > $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl33.bin --compress lz4 \
-					--output fip/bl33.bin.enc \
-					--level v3 --type bl33 --compress lz4
- > $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl2sig --input fip/bl2_new.bin \
-					--output fip/bl2.n.bin.sig
- > $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bootmk \
-		--output fip/u-boot.bin \
-		--bl2 fip/bl2.n.bin.sig \
-		--bl30 fip/bl30_new.bin.enc \
-		--bl31 fip/bl31.img.enc \
-		--bl33 fip/bl33.bin.enc \
-		--ddrfw1 fip/ddr4_1d.fw \
-		--ddrfw2 fip/ddr4_2d.fw \
-		--ddrfw3 fip/ddr3_1d.fw \
-		--ddrfw4 fip/piei.fw \
-		--ddrfw5 fip/lpddr4_1d.fw \
-		--ddrfw6 fip/lpddr4_2d.fw \
-		--ddrfw7 fip/diag_lpddr4.fw \
-		--ddrfw8 fip/aml_ddr.fw \
-		--ddrfw9 fip/lpddr3_1d.fw \
-		--level v3
-
-and then write the image to SD with:
-
- > DEV=/dev/your_sd_device
- > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444

board/amlogic/w400/README.khadas-vim3l

@@ -1,131 +0,0 @@
-U-Boot for Khadas VIM3L
-=======================
-
-Khadas VIM3L is a single board computer manufactured by Shenzhen Wesion
-Technology Co., Ltd. with the following specifications:
-
- - Amlogic S905D3 Arm Cortex-A55 quad-core SoC
- - 2GB LPDDR4 SDRAM
- - Gigabit Ethernet
- - HDMI 2.1 display
- - 40-pin GPIO header
- - 1 x USB 3.0 Host, 1 x USB 2.0 Host
- - eMMC, microSD
- - M.2
- - Infrared receiver
-
-Schematics are available on the manufacturer website.
-
-Currently the U-Boot port supports the following devices:
- - serial
- - eMMC, microSD
- - Ethernet
- - I2C
- - Regulators
- - Reset controller
- - Clock controller
- - ADC
-
-u-boot compilation
-==================
-
- > export CROSS_COMPILE=aarch64-none-elf-
- > make khadas-vim3l_defconfig
- > make
-
-Image creation
-==============
-
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
-
- > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
- > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
- > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
- > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
- > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
-
- > DIR=vim3l-u-boot
- > git clone --depth 1 \
-       https://github.com/khadas/u-boot.git -b khadas-vims-v2015.01 \
-       $DIR
-
- > cd vim3l-u-boot
- > make kvim3l_defconfig
- > make
- > export UBOOTDIR=$PWD
-
- Go back to mainline U-Boot source tree then :
- > mkdir fip
-
- > cp $UBOOTDIR/build/scp_task/bl301.bin fip/
- > cp $UBOOTDIR/build/board/khadas/kvim3l/firmware/acs.bin fip/
- > cp $UBOOTDIR/fip/g12a/bl2.bin fip/
- > cp $UBOOTDIR/fip/g12a/bl30.bin fip/
- > cp $UBOOTDIR/fip/g12a/bl31.img fip/
- > cp $UBOOTDIR/fip/g12a/ddr3_1d.fw fip/
- > cp $UBOOTDIR/fip/g12a/ddr4_1d.fw fip/
- > cp $UBOOTDIR/fip/g12a/ddr4_2d.fw fip/
- > cp $UBOOTDIR/fip/g12a/diag_lpddr4.fw fip/
- > cp $UBOOTDIR/fip/g12a/lpddr3_1d.fw fip/
- > cp $UBOOTDIR/fip/g12a/lpddr4_1d.fw fip/
- > cp $UBOOTDIR/fip/g12a/lpddr4_2d.fw fip/
- > cp $UBOOTDIR/fip/g12a/piei.fw fip/
- > cp $UBOOTDIR/fip/g12a/aml_ddr.fw fip/
- > cp u-boot.bin fip/bl33.bin
-
- > sh fip/blx_fix.sh \
-	fip/bl30.bin \
-	fip/zero_tmp \
-	fip/bl30_zero.bin \
-	fip/bl301.bin \
-	fip/bl301_zero.bin \
-	fip/bl30_new.bin \
-	bl30
-
- > sh fip/blx_fix.sh \
-	fip/bl2.bin \
-	fip/zero_tmp \
-	fip/bl2_zero.bin \
-	fip/acs.bin \
-	fip/bl21_zero.bin \
-	fip/bl2_new.bin \
-	bl2
-
- > $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl30sig --input fip/bl30_new.bin \
-					--output fip/bl30_new.bin.g12a.enc \
-					--level v3
- > $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl30_new.bin.g12a.enc \
-					--output fip/bl30_new.bin.enc \
-					--level v3 --type bl30
- > $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl31.img \
-					--output fip/bl31.img.enc \
-					--level v3 --type bl31
- > $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl33.bin --compress lz4 \
-					--output fip/bl33.bin.enc \
-					--level v3 --type bl33 --compress lz4
- > $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl2sig --input fip/bl2_new.bin \
-					--output fip/bl2.n.bin.sig
- > $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bootmk \
-		--output fip/u-boot.bin \
-		--bl2 fip/bl2.n.bin.sig \
-		--bl30 fip/bl30_new.bin.enc \
-		--bl31 fip/bl31.img.enc \
-		--bl33 fip/bl33.bin.enc \
-		--ddrfw1 fip/ddr4_1d.fw \
-		--ddrfw2 fip/ddr4_2d.fw \
-		--ddrfw3 fip/ddr3_1d.fw \
-		--ddrfw4 fip/piei.fw \
-		--ddrfw5 fip/lpddr4_1d.fw \
-		--ddrfw6 fip/lpddr4_2d.fw \
-		--ddrfw7 fip/diag_lpddr4.fw \
-		--ddrfw8 fip/aml_ddr.fw \
-		--ddrfw9 fip/lpddr3_1d.fw \
-		--level v3
-
-and then write the image to SD with:
-
- > DEV=/dev/your_sd_device
- > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444

board/amlogic/w400/README.odroid-n2

@@ -1,129 +0,0 @@
-U-Boot for ODROID-N2
-====================
-
-ODROID-N2 is a single board computer manufactured by Hardkernel
-Co. Ltd with the following specifications:
-
- - Amlogic S922X ARM Cortex-A53 dual-core + Cortex-A73 quad-core SoC
- - 4GB DDR4 SDRAM
- - Gigabit Ethernet
- - HDMI 2.1 4K/60Hz display
- - 40-pin GPIO header
- - 4 x USB 3.0 Host, 1 x USB OTG
- - eMMC, microSD
- - Infrared receiver
-
-Schematics are available on the manufacturer website.
-
-Currently the u-boot port supports the following devices:
- - serial
- - eMMC, microSD
- - Ethernet
- - I2C
- - Regulators
- - Reset controller
- - Clock controller
- - ADC
-
-u-boot compilation
-==================
-
- > export CROSS_COMPILE=aarch64-none-elf-
- > make odroid-n2_defconfig
- > make
-
-Image creation
-==============
-
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
-
- > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
- > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
- > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
- > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
- > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
-
- > DIR=odroid-n2
- > git clone --depth 1 \
-       https://github.com/hardkernel/u-boot.git -b odroidn2-v2015.01 \
-       $DIR
-
- > cd odroid-n2
- > make odroidn2_defconfig
- > make
- > export UBOOTDIR=$PWD
-
- Go back to mainline U-Boot source tree then :
- > mkdir fip
-
- > wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh
- > cp $UBOOTDIR/build/scp_task/bl301.bin fip/
- > cp $UBOOTDIR/build/board/hardkernel/odroidn2/firmware/acs.bin fip/
- > cp $UBOOTDIR/fip/g12b/bl2.bin fip/
- > cp $UBOOTDIR/fip/g12b/bl30.bin fip/
- > cp $UBOOTDIR/fip/g12b/bl31.img fip/
- > cp $UBOOTDIR/fip/g12b/ddr3_1d.fw fip/
- > cp $UBOOTDIR/fip/g12b/ddr4_1d.fw fip/
- > cp $UBOOTDIR/fip/g12b/ddr4_2d.fw fip/
- > cp $UBOOTDIR/fip/g12b/diag_lpddr4.fw fip/
- > cp $UBOOTDIR/fip/g12b/lpddr4_1d.fw fip/
- > cp $UBOOTDIR/fip/g12b/lpddr4_2d.fw fip/
- > cp $UBOOTDIR/fip/g12b/piei.fw fip/
- > cp $UBOOTDIR/fip/g12b/aml_ddr.fw fip/
- > cp u-boot.bin fip/bl33.bin
-
- > sh fip/blx_fix.sh \
-	fip/bl30.bin \
-	fip/zero_tmp \
-	fip/bl30_zero.bin \
-	fip/bl301.bin \
-	fip/bl301_zero.bin \
-	fip/bl30_new.bin \
-	bl30
-
- > sh fip/blx_fix.sh \
-	fip/bl2.bin \
-	fip/zero_tmp \
-	fip/bl2_zero.bin \
-	fip/acs.bin \
-	fip/bl21_zero.bin \
-	fip/bl2_new.bin \
-	bl2
-
- > $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl30sig --input fip/bl30_new.bin \
-					--output fip/bl30_new.bin.g12a.enc \
-					--level v3
- > $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl30_new.bin.g12a.enc \
-					--output fip/bl30_new.bin.enc \
-					--level v3 --type bl30
- > $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl31.img \
-					--output fip/bl31.img.enc \
-					--level v3 --type bl31
- > $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl33.bin --compress lz4 \
-					--output fip/bl33.bin.enc \
-					--level v3 --type bl33 --compress lz4
- > $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl2sig --input fip/bl2_new.bin \
-					--output fip/bl2.n.bin.sig
- > $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bootmk \
-		--output fip/u-boot.bin \
-		--bl2 fip/bl2.n.bin.sig \
-		--bl30 fip/bl30_new.bin.enc \
-		--bl31 fip/bl31.img.enc \
-		--bl33 fip/bl33.bin.enc \
-		--ddrfw1 fip/ddr4_1d.fw \
-		--ddrfw2 fip/ddr4_2d.fw \
-		--ddrfw3 fip/ddr3_1d.fw \
-		--ddrfw4 fip/piei.fw \
-		--ddrfw5 fip/lpddr4_1d.fw \
-		--ddrfw6 fip/lpddr4_2d.fw \
-		--ddrfw7 fip/diag_lpddr4.fw \
-		--ddrfw8 fip/aml_ddr.fw \
-		--level v3
-
-and then write the image to SD with:
-
- > DEV=/dev/your_sd_device
- > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444

board/amlogic/w400/README.w400

@@ -1,129 +0,0 @@
-U-Boot for Amlogic W400
-=======================
-
-U200 is a reference board manufactured by Amlogic with the following
-specifications:
-
- - Amlogic S922X ARM Cortex-A53 dual-core + Cortex-A73 quad-core SoC
- - 2GB DDR4 SDRAM
- - 10/100 Ethernet (Internal PHY)
- - 1 x USB 3.0 Host
- - eMMC
- - SDcard
- - Infrared receiver
- - SDIO WiFi Module
- - MIPI DSI Connector
- - Audio HAT Connector
- - PCI-E M.2 Connector
-
-Schematics are available from Amlogic on demand.
-
-Currently the u-boot port supports the following devices:
- - serial
- - Ethernet
- - Regulators
- - Clock controller
-
-u-boot compilation
-==================
-
- > export CROSS_COMPILE=aarch64-none-elf-
- > make w400_defconfig
- > make
-
-Image creation
-==============
-
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
-
- > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
- > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
- > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
- > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
- > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
- > git clone https://github.com/BayLibre/u-boot.git -b buildroot-openlinux-20180418 amlogic-u-boot
- > cd amlogic-u-boot
- > make g12b_w400_v1_defconfig
- > make
- > export UBOOTDIR=$PWD
-
-Download the latest Amlogic Buildroot package, and extract it :
- > wget http://openlinux2.amlogic.com:8000/ARM/filesystem/Linux_BSP/buildroot_openlinux_kernel_4.9_fbdev_20180706.tar.gz
- > tar xfz buildroot_openlinux_kernel_4.9_fbdev_20180706.tar.gz buildroot_openlinux_kernel_4.9_fbdev_20180706/bootloader
- > export BRDIR=$PWD/buildroot_openlinux_kernel_4.9_fbdev_20180706
- > export FIPDIR=$BRDIR/bootloader/uboot-repo/fip
-
-Go back to mainline U-Boot source tree then :
- > mkdir fip
-
- > wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh
- > cp $UBOOTDIR/build/scp_task/bl301.bin fip/
- > cp $UBOOTDIR/build/board/amlogic/g12b_w400_v1/firmware/acs.bin fip/
- > cp $BRDIR/bootloader/uboot-repo/bl2/bin/g12b/bl2.bin fip/
- > cp $BRDIR/bootloader/uboot-repo/bl30/bin/g12b/bl30.bin fip/
- > cp $BRDIR/bootloader/uboot-repo/bl31_1.3/bin/g12b/bl31.img fip/
- > cp $FIPDIR/g12b/ddr3_1d.fw fip/
- > cp $FIPDIR/g12b/ddr4_1d.fw fip/
- > cp $FIPDIR/g12b/ddr4_2d.fw fip/
- > cp $FIPDIR/g12b/diag_lpddr4.fw fip/
- > cp $FIPDIR/g12b/lpddr4_1d.fw fip/
- > cp $FIPDIR/g12b/lpddr4_2d.fw fip/
- > cp $FIPDIR/g12b/piei.fw fip/
- > cp $FIPDIR/g12b/aml_ddr.fw fip/
- > cp u-boot.bin fip/bl33.bin
-
- > sh fip/blx_fix.sh \
-	fip/bl30.bin \
-	fip/zero_tmp \
-	fip/bl30_zero.bin \
-	fip/bl301.bin \
-	fip/bl301_zero.bin \
-	fip/bl30_new.bin \
-	bl30
-
- > sh fip/blx_fix.sh \
-	fip/bl2.bin \
-	fip/zero_tmp \
-	fip/bl2_zero.bin \
-	fip/acs.bin \
-	fip/bl21_zero.bin \
-	fip/bl2_new.bin \
-	bl2
-
- > $FIPDIR/g12b/aml_encrypt_g12b --bl30sig --input fip/bl30_new.bin \
-					--output fip/bl30_new.bin.g12a.enc \
-					--level v3
- > $FIPDIR/g12b/aml_encrypt_g12b --bl3sig --input fip/bl30_new.bin.g12a.enc \
-					--output fip/bl30_new.bin.enc \
-					--level v3 --type bl30
- > $FIPDIR/g12b/aml_encrypt_g12b --bl3sig --input fip/bl31.img \
-					--output fip/bl31.img.enc \
-					--level v3 --type bl31
- > $FIPDIR/g12b/aml_encrypt_g12b --bl3sig --input fip/bl33.bin --compress lz4 \
-					--output fip/bl33.bin.enc \
-					--level v3 --type bl33
- > $FIPDIR/g12b/aml_encrypt_g12b --bl2sig --input fip/bl2_new.bin \
-					--output fip/bl2.n.bin.sig
- > $FIPDIR/g12b/aml_encrypt_g12b --bootmk \
-		--output fip/u-boot.bin \
-		--bl2 fip/bl2.n.bin.sig \
-		--bl30 fip/bl30_new.bin.enc \
-		--bl31 fip/bl31.img.enc \
-		--bl33 fip/bl33.bin.enc \
-		--ddrfw1 fip/ddr4_1d.fw \
-		--ddrfw2 fip/ddr4_2d.fw \
-		--ddrfw3 fip/ddr3_1d.fw \
-		--ddrfw4 fip/piei.fw \
-		--ddrfw5 fip/lpddr4_1d.fw \
-		--ddrfw6 fip/lpddr4_2d.fw \
-		--ddrfw7 fip/diag_lpddr4.fw \
-		--ddrfw8 fip/aml_ddr.fw \
-		--level v3
-
-and then write the image to SD with:
-
- > DEV=/dev/your_sd_device
- > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444

board/boundary/nitrogen6x/nitrogen6x.c

@@ -25,7 +25,6 @@
 #include <asm/mach-imx/spi.h>
 #include <asm/mach-imx/boot_mode.h>
 #include <asm/mach-imx/video.h>
-#include <mmc.h>
 #include <fsl_esdhc_imx.h>
 #include <micrel.h>
 #include <miiphy.h>
@@ -161,26 +160,6 @@ static iomux_v3_cfg_t const usdhc2_pads[] = {
 	IOMUX_PAD_CTRL(SD2_DAT3__SD2_DATA3, USDHC_PAD_CTRL),
 };
 
-static iomux_v3_cfg_t const usdhc3_pads[] = {
-	IOMUX_PAD_CTRL(SD3_CLK__SD3_CLK, USDHC_PAD_CTRL),
-	IOMUX_PAD_CTRL(SD3_CMD__SD3_CMD, USDHC_PAD_CTRL),
-	IOMUX_PAD_CTRL(SD3_DAT0__SD3_DATA0, USDHC_PAD_CTRL),
-	IOMUX_PAD_CTRL(SD3_DAT1__SD3_DATA1, USDHC_PAD_CTRL),
-	IOMUX_PAD_CTRL(SD3_DAT2__SD3_DATA2, USDHC_PAD_CTRL),
-	IOMUX_PAD_CTRL(SD3_DAT3__SD3_DATA3, USDHC_PAD_CTRL),
-	IOMUX_PAD_CTRL(SD3_DAT5__GPIO7_IO00, NO_PAD_CTRL), /* CD */
-};
-
-static iomux_v3_cfg_t const usdhc4_pads[] = {
-	IOMUX_PAD_CTRL(SD4_CLK__SD4_CLK, USDHC_PAD_CTRL),
-	IOMUX_PAD_CTRL(SD4_CMD__SD4_CMD, USDHC_PAD_CTRL),
-	IOMUX_PAD_CTRL(SD4_DAT0__SD4_DATA0, USDHC_PAD_CTRL),
-	IOMUX_PAD_CTRL(SD4_DAT1__SD4_DATA1, USDHC_PAD_CTRL),
-	IOMUX_PAD_CTRL(SD4_DAT2__SD4_DATA2, USDHC_PAD_CTRL),
-	IOMUX_PAD_CTRL(SD4_DAT3__SD4_DATA3, USDHC_PAD_CTRL),
-	IOMUX_PAD_CTRL(NANDF_D6__GPIO2_IO06, NO_PAD_CTRL), /* CD */
-};
-
 static iomux_v3_cfg_t const enet_pads1[] = {
 	IOMUX_PAD_CTRL(ENET_MDIO__ENET_MDIO, ENET_PAD_CTRL),
 	IOMUX_PAD_CTRL(ENET_MDC__ENET_MDC, ENET_PAD_CTRL),
@@ -305,57 +284,6 @@ int board_ehci_power(int port, int on)
 
 #endif
 
-#ifdef CONFIG_FSL_ESDHC_IMX
-static struct fsl_esdhc_cfg usdhc_cfg[2] = {
-	{USDHC3_BASE_ADDR},
-	{USDHC4_BASE_ADDR},
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
-	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
-	int gp_cd = (cfg->esdhc_base == USDHC3_BASE_ADDR) ? IMX_GPIO_NR(7, 0) :
-			IMX_GPIO_NR(2, 6);
-
-	gpio_direction_input(gp_cd);
-	return !gpio_get_value(gp_cd);
-}
-
-int board_mmc_init(bd_t *bis)
-{
-	int ret;
-	u32 index = 0;
-
-	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-	usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
-
-	usdhc_cfg[0].max_bus_width = 4;
-	usdhc_cfg[1].max_bus_width = 4;
-
-	for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
-		switch (index) {
-		case 0:
-			SETUP_IOMUX_PADS(usdhc3_pads);
-			break;
-		case 1:
-		       SETUP_IOMUX_PADS(usdhc4_pads);
-		       break;
-		default:
-		       printf("Warning: you configured more USDHC controllers"
-			       "(%d) then supported by the board (%d)\n",
-			       index + 1, CONFIG_SYS_FSL_USDHC_NUM);
-		       return -EINVAL;
-		}
-
-		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
-		if (ret)
-			return ret;
-	}
-
-	return 0;
-}
-#endif
-
 #ifdef CONFIG_MXC_SPI
 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 {

board/dhelectronics/dh_imx6/dh_imx6.c

@@ -142,8 +142,6 @@ int board_init(void)
 	/* Enable eim_slow clocks */
 	setbits_le32(&mxc_ccm->CCGR6, 0x1 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET);
 
-	setup_dhcom_mac_from_fuse();
-
 	setup_fec_clock();
 
 	return 0;
@@ -189,6 +187,8 @@ int board_late_init(void)
 	u32 hw_code;
 	char buf[16];
 
+	setup_dhcom_mac_from_fuse();
+
 	hw_code = board_get_hwcode();
 
 	switch (get_cpu_type()) {

board/freescale/imx8mp_evk/README

@@ -0,0 +1,41 @@
+U-Boot for the NXP i.MX8MP EVK board
+
+Quick Start
+===========
+- Build the ARM Trusted firmware binary
+- Get the firmware-imx package
+- Build U-Boot
+- Boot
+
+Get and Build the ARM Trusted firmware
+======================================
+Note: $(srctree) is the U-Boot source directory
+Get ATF from: https://source.codeaurora.org/external/imx/imx-atf
+branch: imx_5.4.3_2.0.0
+$ make PLAT=imx8mp bl31
+$ sudo cp build/imx8mp/release/bl31.bin $(srctree)
+
+Get the ddr firmware
+====================
+$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.7.bin
+$ chmod +x firmware-imx-8.7.bin
+$ ./firmware-imx-8.7
+$ sudo cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_1d_dmem_201904.bin $(srctree)/lpddr4_pmu_train_1d_dmem.bin
+$ sudo cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_1d_imem_201904.bin $(srctree)/lpddr4_pmu_train_1d_imem.bin
+$ sudo cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_2d_dmem_201904.bin $(srctree)/lpddr4_pmu_train_2d_dmem.bin
+$ sudo cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_2d_imem_201904.bin $(srctree)/lpddr4_pmu_train_2d_imem.bin
+
+Build U-Boot
+============
+$ export CROSS_COMPILE=aarch64-poky-linux-
+$ make imx8mp_evk_defconfig
+$ export ATF_LOAD_ADDR=0x960000
+$ make flash.bin
+
+Burn the flash.bin to the MicroSD card at offset 32KB
+$sudo dd if=flash.bin of=/dev/sd[x] bs=1K seek=32; sync
+
+Boot
+====
+Set Boot switch to SD boot
+Use /dev/ttyUSB2 for U-Boot console

board/freescale/imx8mp_evk/spl.c

@@ -29,11 +29,6 @@
 #include <mmc.h>
 #include <asm/arch/ddr.h>
 
-#include <dm/uclass.h>
-#include <dm/device.h>
-#include <dm/uclass-internal.h>
-#include <dm/device-internal.h>
-
 DECLARE_GLOBAL_DATA_PTR;
 
 int spl_board_boot_device(enum boot_device boot_dev_spl)
@@ -48,16 +43,7 @@ void spl_dram_init(void)
 
 void spl_board_init(void)
 {
-	struct udevice *dev;
-	int ret;
-
 	puts("Normal Boot\n");
-
-	ret = uclass_get_device_by_name(UCLASS_CLK,
-					"clock-controller@30380000",
-					&dev);
-	if (ret < 0)
-		printf("Failed to find clock node. Check device tree\n");
 }
 
 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
@@ -118,6 +104,7 @@ int board_fit_config_name_match(const char *name)
 }
 #endif
 
+/* Do not use BSS area in this phase */
 void board_init_f(ulong dummy)
 {
 	int ret;
@@ -128,19 +115,14 @@ void board_init_f(ulong dummy)
 
 	board_early_init_f();
 
-	timer_init();
-
-	preloader_console_init();
-
-	/* Clear the BSS. */
-	memset(__bss_start, 0, __bss_end - __bss_start);
-
-	ret = spl_init();
+	ret = spl_early_init();
 	if (ret) {
 		debug("spl_init() failed: %d\n", ret);
 		hang();
 	}
 
+	preloader_console_init();
+
 	enable_tzc380();
 
 	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
@@ -149,6 +131,4 @@ void board_init_f(ulong dummy)
 
 	/* DDR initialization */
 	spl_dram_init();
-
-	board_init_r(NULL, 0);
 }

board/freescale/p1010rdb/README.P1010RDB-PA

@@ -88,7 +88,7 @@ Note: 1 stands for 'on', 0 stands for 'off'
 Setting of hwconfig
 ===================
 If FlexCAN or TDM is needed, please set "fsl_p1010mux:tdm_can=can" or
-"fsl_p1010mux:tdm_can=tdm" explicitly in u-booot prompt as below for example:
+"fsl_p1010mux:tdm_can=tdm" explicitly in u-boot prompt as below for example:
 setenv hwconfig "fsl_p1010mux:tdm_can=tdm;usb1:dr_mode=host,phy_type=utmi"
 By default, don't set fsl_p1010mux:tdm_can, in this case, spi chip selection
 is set to spi-flash instead of to SLIC/TDM/DAC and tdm_can_sel is set to TDM

board/menlo/m53menlo/m53menlo.c

@@ -353,24 +353,28 @@ int board_late_init(void)
 
 	ret = splash_screen_prepare();
 	if (ret < 0)
-		return ret;
+		goto splasherr;
 
 	len = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE;
 	ret = gunzip(dst + 2, CONFIG_SYS_VIDEO_LOGO_MAX_SIZE - 2,
 		     (uchar *)addr, &len);
 	if (ret) {
 		printf("Error: no valid bmp or bmp.gz image at %lx\n", addr);
-		free(dst);
-		return ret;
+		goto splasherr;
 	}
 
 	ret = uclass_get_device(UCLASS_VIDEO, 0, &dev);
 	if (ret)
-		return ret;
+		goto splasherr;
 
 	ret = video_bmp_display(dev, (ulong)dst + 2, xpos, ypos, true);
 	if (ret)
-		return ret;
+		goto splasherr;
+
+	return 0;
+
+splasherr:
+	free(dst);
 #endif
 	return 0;
 }

board/pandora/Kconfig

@@ -1,9 +0,0 @@
-if TARGET_OMAP3_PANDORA
-
-config SYS_BOARD
-	default "pandora"
-
-config SYS_CONFIG_NAME
-	default "omap3_pandora"
-
-endif

board/pandora/MAINTAINERS

@@ -1,6 +0,0 @@
-PANDORA BOARD
-M:	Grazvydas Ignotas <notasas@gmail.com>
-S:	Maintained
-F:	board/pandora/
-F:	include/configs/omap3_pandora.h
-F:	configs/omap3_pandora_defconfig

board/pandora/Makefile

@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y	:= pandora.o

board/pandora/pandora.c

@@ -1,149 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2008
- * Grazvydas Ignotas <notasas@gmail.com>
- *
- * Derived from Beagle Board, 3430 SDP, and OMAP3EVM code by
- *	Richard Woodruff <r-woodruff2@ti.com>
- *	Syed Mohammed Khasim <khasim@ti.com>
- *	Sunil Kumar <sunilsaini05@gmail.com>
- *	Shashi Ranjan <shashiranjanmca05@gmail.com>
- *
- * (C) Copyright 2004-2008
- * Texas Instruments, <www.ti.com>
- */
-#include <common.h>
-#include <dm.h>
-#include <init.h>
-#include <ns16550.h>
-#include <twl4030.h>
-#include <asm/io.h>
-#include <asm/gpio.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/mach-types.h>
-#include <linux/delay.h>
-#include "pandora.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define TWL4030_BB_CFG_BBCHEN		(1 << 4)
-#define TWL4030_BB_CFG_BBSEL_3200MV	(3 << 2)
-#define TWL4030_BB_CFG_BBISEL_500UA	2
-
-#define CONTROL_WKUP_CTRL		0x48002a5c
-#define GPIO_IO_PWRDNZ			(1 << 6)
-#define PBIASLITEVMODE1			(1 << 8)
-
-static const struct ns16550_platdata pandora_serial = {
-	.base = OMAP34XX_UART3,
-	.reg_shift = 2,
-	.clock = V_NS16550_CLK,
-	.fcr = UART_FCR_DEFVAL,
-};
-
-U_BOOT_DEVICE(pandora_uart) = {
-	"ns16550_serial",
-	&pandora_serial
-};
-
-/*
- * Routine: board_init
- * Description: Early hardware init.
- */
-int board_init(void)
-{
-	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
-	/* board id for Linux */
-	gd->bd->bi_arch_number = MACH_TYPE_OMAP3_PANDORA;
-	/* boot param addr */
-	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
-
-	return 0;
-}
-
-static void set_output_gpio(unsigned int gpio, int value)
-{
-	int ret;
-
-	ret = gpio_request(gpio, "");
-	if (ret != 0) {
-		printf("could not request GPIO %u\n", gpio);
-		return;
-	}
-	ret = gpio_direction_output(gpio, value);
-	if (ret != 0)
-		printf("could not set GPIO %u to %d\n", gpio, value);
-}
-
-/*
- * Routine: misc_init_r
- * Description: Configure board specific parts
- */
-int misc_init_r(void)
-{
-	t2_t *t2_base = (t2_t *)T2_BASE;
-	u32 pbias_lite;
-
-	twl4030_led_init(TWL4030_LED_LEDEN_LEDBON);
-
-	/* set up dual-voltage GPIOs to 1.8V */
-	pbias_lite = readl(&t2_base->pbias_lite);
-	pbias_lite &= ~PBIASLITEVMODE1;
-	pbias_lite |= PBIASLITEPWRDNZ1;
-	writel(pbias_lite, &t2_base->pbias_lite);
-	if (get_cpu_family() == CPU_OMAP36XX)
-		writel(readl(CONTROL_WKUP_CTRL) | GPIO_IO_PWRDNZ,
-			CONTROL_WKUP_CTRL);
-
-	/* make sure audio and BT chips are in powerdown state */
-	set_output_gpio(14, 0);
-	set_output_gpio(15, 0);
-	set_output_gpio(118, 0);
-
-	/* enable USB supply */
-	set_output_gpio(164, 1);
-
-	/* wifi needs a short pulse to enter powersave state */
-	set_output_gpio(23, 1);
-	udelay(5000);
-	gpio_direction_output(23, 0);
-
-	/* Enable battery backup capacitor (3.2V, 0.5mA charge current) */
-	twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER,
-		TWL4030_PM_RECEIVER_BB_CFG,
-		TWL4030_BB_CFG_BBCHEN | TWL4030_BB_CFG_BBSEL_3200MV |
-		TWL4030_BB_CFG_BBISEL_500UA);
-
-	omap_die_id_display();
-
-	return 0;
-}
-
-/*
- * Routine: set_muxconf_regs
- * Description: Setting up the configuration Mux registers specific to the
- *		hardware. Many pins need to be moved from protect to primary
- *		mode.
- */
-void set_muxconf_regs(void)
-{
-	MUX_PANDORA();
-	if (get_cpu_family() == CPU_OMAP36XX) {
-		MUX_PANDORA_3730();
-	}
-}
-
-#ifdef CONFIG_MMC
-int board_mmc_init(bd_t *bis)
-{
-	return omap_mmc_init(0, 0, 0, -1, -1);
-}
-
-void board_mmc_power_init(void)
-{
-	twl4030_power_mmc_init(0);
-}
-#endif

board/pandora/pandora.h

@@ -1,391 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2008
- * Grazvydas Ignotas <notasas@gmail.com>
- */
-#ifndef _PANDORA_H_
-#define _PANDORA_H_
-
-const omap3_sysinfo sysinfo = {
-	DDR_STACKED,
-	"OMAP3 Pandora",
-	"NAND",
-};
-
-/*
- * IEN  - Input Enable
- * IDIS - Input Disable
- * PTD  - Pull type Down
- * PTU  - Pull type Up
- * DIS  - Pull type selection is inactive
- * EN	- Pull type selection is active
- * M0	- Mode 0
- * The commented string gives the final mux configuration for that pin
- */
-#define MUX_PANDORA() \
- /*SDRC*/\
-	MUX_VAL(CP(SDRC_D0),		(IEN  | PTD | DIS | M0)) /*SDRC_D0*/\
-	MUX_VAL(CP(SDRC_D1),		(IEN  | PTD | DIS | M0)) /*SDRC_D1*/\
-	MUX_VAL(CP(SDRC_D2),		(IEN  | PTD | DIS | M0)) /*SDRC_D2*/\
-	MUX_VAL(CP(SDRC_D3),		(IEN  | PTD | DIS | M0)) /*SDRC_D3*/\
-	MUX_VAL(CP(SDRC_D4),		(IEN  | PTD | DIS | M0)) /*SDRC_D4*/\
-	MUX_VAL(CP(SDRC_D5),		(IEN  | PTD | DIS | M0)) /*SDRC_D5*/\
-	MUX_VAL(CP(SDRC_D6),		(IEN  | PTD | DIS | M0)) /*SDRC_D6*/\
-	MUX_VAL(CP(SDRC_D7),		(IEN  | PTD | DIS | M0)) /*SDRC_D7*/\
-	MUX_VAL(CP(SDRC_D8),		(IEN  | PTD | DIS | M0)) /*SDRC_D8*/\
-	MUX_VAL(CP(SDRC_D9),		(IEN  | PTD | DIS | M0)) /*SDRC_D9*/\
-	MUX_VAL(CP(SDRC_D10),		(IEN  | PTD | DIS | M0)) /*SDRC_D10*/\
-	MUX_VAL(CP(SDRC_D11),		(IEN  | PTD | DIS | M0)) /*SDRC_D11*/\
-	MUX_VAL(CP(SDRC_D12),		(IEN  | PTD | DIS | M0)) /*SDRC_D12*/\
-	MUX_VAL(CP(SDRC_D13),		(IEN  | PTD | DIS | M0)) /*SDRC_D13*/\
-	MUX_VAL(CP(SDRC_D14),		(IEN  | PTD | DIS | M0)) /*SDRC_D14*/\
-	MUX_VAL(CP(SDRC_D15),		(IEN  | PTD | DIS | M0)) /*SDRC_D15*/\
-	MUX_VAL(CP(SDRC_D16),		(IEN  | PTD | DIS | M0)) /*SDRC_D16*/\
-	MUX_VAL(CP(SDRC_D17),		(IEN  | PTD | DIS | M0)) /*SDRC_D17*/\
-	MUX_VAL(CP(SDRC_D18),		(IEN  | PTD | DIS | M0)) /*SDRC_D18*/\
-	MUX_VAL(CP(SDRC_D19),		(IEN  | PTD | DIS | M0)) /*SDRC_D19*/\
-	MUX_VAL(CP(SDRC_D20),		(IEN  | PTD | DIS | M0)) /*SDRC_D20*/\
-	MUX_VAL(CP(SDRC_D21),		(IEN  | PTD | DIS | M0)) /*SDRC_D21*/\
-	MUX_VAL(CP(SDRC_D22),		(IEN  | PTD | DIS | M0)) /*SDRC_D22*/\
-	MUX_VAL(CP(SDRC_D23),		(IEN  | PTD | DIS | M0)) /*SDRC_D23*/\
-	MUX_VAL(CP(SDRC_D24),		(IEN  | PTD | DIS | M0)) /*SDRC_D24*/\
-	MUX_VAL(CP(SDRC_D25),		(IEN  | PTD | DIS | M0)) /*SDRC_D25*/\
-	MUX_VAL(CP(SDRC_D26),		(IEN  | PTD | DIS | M0)) /*SDRC_D26*/\
-	MUX_VAL(CP(SDRC_D27),		(IEN  | PTD | DIS | M0)) /*SDRC_D27*/\
-	MUX_VAL(CP(SDRC_D28),		(IEN  | PTD | DIS | M0)) /*SDRC_D28*/\
-	MUX_VAL(CP(SDRC_D29),		(IEN  | PTD | DIS | M0)) /*SDRC_D29*/\
-	MUX_VAL(CP(SDRC_D30),		(IEN  | PTD | DIS | M0)) /*SDRC_D30*/\
-	MUX_VAL(CP(SDRC_D31),		(IEN  | PTD | DIS | M0)) /*SDRC_D31*/\
-	MUX_VAL(CP(SDRC_CLK),		(IEN  | PTD | DIS | M0)) /*SDRC_CLK*/\
-	MUX_VAL(CP(SDRC_DQS0),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS0*/\
-	MUX_VAL(CP(SDRC_DQS1),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS1*/\
-	MUX_VAL(CP(SDRC_DQS2),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS2*/\
-	MUX_VAL(CP(SDRC_DQS3),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS3*/\
- /*GPMC*/\
-	MUX_VAL(CP(GPMC_A1),		(IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
-	MUX_VAL(CP(GPMC_A2),		(IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
-	MUX_VAL(CP(GPMC_A3),		(IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
-	MUX_VAL(CP(GPMC_A4),		(IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
-	MUX_VAL(CP(GPMC_A5),		(IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
-	MUX_VAL(CP(GPMC_A6),		(IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
-	MUX_VAL(CP(GPMC_A7),		(IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
-	MUX_VAL(CP(GPMC_A8),		(IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
-	MUX_VAL(CP(GPMC_A9),		(IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
-	MUX_VAL(CP(GPMC_A10),		(IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
-	MUX_VAL(CP(GPMC_D0),		(IEN  | PTD | DIS | M0)) /*GPMC_D0*/\
-	MUX_VAL(CP(GPMC_D1),		(IEN  | PTD | DIS | M0)) /*GPMC_D1*/\
-	MUX_VAL(CP(GPMC_D2),		(IEN  | PTD | DIS | M0)) /*GPMC_D2*/\
-	MUX_VAL(CP(GPMC_D3),		(IEN  | PTD | DIS | M0)) /*GPMC_D3*/\
-	MUX_VAL(CP(GPMC_D4),		(IEN  | PTD | DIS | M0)) /*GPMC_D4*/\
-	MUX_VAL(CP(GPMC_D5),		(IEN  | PTD | DIS | M0)) /*GPMC_D5*/\
-	MUX_VAL(CP(GPMC_D6),		(IEN  | PTD | DIS | M0)) /*GPMC_D6*/\
-	MUX_VAL(CP(GPMC_D7),		(IEN  | PTD | DIS | M0)) /*GPMC_D7*/\
-	MUX_VAL(CP(GPMC_D8),		(IEN  | PTD | DIS | M0)) /*GPMC_D8*/\
-	MUX_VAL(CP(GPMC_D9),		(IEN  | PTD | DIS | M0)) /*GPMC_D9*/\
-	MUX_VAL(CP(GPMC_D10),		(IEN  | PTD | DIS | M0)) /*GPMC_D10*/\
-	MUX_VAL(CP(GPMC_D11),		(IEN  | PTD | DIS | M0)) /*GPMC_D11*/\
-	MUX_VAL(CP(GPMC_D12),		(IEN  | PTD | DIS | M0)) /*GPMC_D12*/\
-	MUX_VAL(CP(GPMC_D13),		(IEN  | PTD | DIS | M0)) /*GPMC_D13*/\
-	MUX_VAL(CP(GPMC_D14),		(IEN  | PTD | DIS | M0)) /*GPMC_D14*/\
-	MUX_VAL(CP(GPMC_D15),		(IEN  | PTD | DIS | M0)) /*GPMC_D15*/\
-	MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS0*/\
-	MUX_VAL(CP(GPMC_NCS1),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS1*/\
-	MUX_VAL(CP(GPMC_CLK),		(IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
-	MUX_VAL(CP(GPMC_NADV_ALE),	(IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
-	MUX_VAL(CP(GPMC_NOE),		(IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
-	MUX_VAL(CP(GPMC_NWE),		(IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
-	MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
-	MUX_VAL(CP(GPMC_NWP),		(IEN  | PTD | DIS | M0)) /*GPMC_nWP*/\
-	MUX_VAL(CP(GPMC_WAIT0),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT0*/\
-	MUX_VAL(CP(GPMC_WAIT1),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT1*/\
- /*DSS*/\
-	MUX_VAL(CP(DSS_PCLK),		(IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
-	MUX_VAL(CP(DSS_HSYNC),		(IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
-	MUX_VAL(CP(DSS_VSYNC),		(IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
-	MUX_VAL(CP(DSS_ACBIAS),		(IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
-	MUX_VAL(CP(DSS_DATA0),		(IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
-	MUX_VAL(CP(DSS_DATA1),		(IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
-	MUX_VAL(CP(DSS_DATA2),		(IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
-	MUX_VAL(CP(DSS_DATA3),		(IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
-	MUX_VAL(CP(DSS_DATA4),		(IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
-	MUX_VAL(CP(DSS_DATA5),		(IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
-	MUX_VAL(CP(DSS_DATA6),		(IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
-	MUX_VAL(CP(DSS_DATA7),		(IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
-	MUX_VAL(CP(DSS_DATA8),		(IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
-	MUX_VAL(CP(DSS_DATA9),		(IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
-	MUX_VAL(CP(DSS_DATA10),		(IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
-	MUX_VAL(CP(DSS_DATA11),		(IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
-	MUX_VAL(CP(DSS_DATA12),		(IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
-	MUX_VAL(CP(DSS_DATA13),		(IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
-	MUX_VAL(CP(DSS_DATA14),		(IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
-	MUX_VAL(CP(DSS_DATA15),		(IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
-	MUX_VAL(CP(DSS_DATA16),		(IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
-	MUX_VAL(CP(DSS_DATA17),		(IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
-	MUX_VAL(CP(DSS_DATA18),		(IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
-	MUX_VAL(CP(DSS_DATA19),		(IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
-	MUX_VAL(CP(DSS_DATA20),		(IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
-	MUX_VAL(CP(DSS_DATA21),		(IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
-	MUX_VAL(CP(DSS_DATA22),		(IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
-	MUX_VAL(CP(DSS_DATA23),		(IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
- /*GPIO based game buttons*/\
-	MUX_VAL(CP(CAM_XCLKA),		(IEN  | PTD | DIS | M4)) /*GPIO_96 - LEFT*/\
-	MUX_VAL(CP(CAM_PCLK),		(IEN  | PTD | DIS | M4)) /*GPIO_97 - L2*/\
-	MUX_VAL(CP(CAM_FLD),		(IEN  | PTD | DIS | M4)) /*GPIO_98 - RIGHT*/\
-	MUX_VAL(CP(CAM_D0),		(IEN  | PTD | DIS | M4)) /*GPIO_99 - MENU*/\
-	MUX_VAL(CP(CAM_D1),		(IEN  | PTD | DIS | M4)) /*GPIO_100 - START*/\
-	MUX_VAL(CP(CAM_D2),		(IEN  | PTD | DIS | M4)) /*GPIO_101 - Y*/\
-	MUX_VAL(CP(CAM_D3),		(IEN  | PTD | DIS | M4)) /*GPIO_102 - L1*/\
-	MUX_VAL(CP(CAM_D4),		(IEN  | PTD | DIS | M4)) /*GPIO_103 - DOWN*/\
-	MUX_VAL(CP(CAM_D5),		(IEN  | PTD | DIS | M4)) /*GPIO_104 - SELECT*/\
-	MUX_VAL(CP(CAM_D6),		(IEN  | PTD | DIS | M4)) /*GPIO_105 - R1*/\
-	MUX_VAL(CP(CAM_D7),		(IEN  | PTD | DIS | M4)) /*GPIO_106 - B*/\
-	MUX_VAL(CP(CAM_D8),		(IEN  | PTD | DIS | M4)) /*GPIO_107 - R2*/\
-	MUX_VAL(CP(CAM_D10),		(IEN  | PTD | DIS | M4)) /*GPIO_109 - X*/\
-	MUX_VAL(CP(CAM_D11),		(IEN  | PTD | DIS | M4)) /*GPIO_110 - UP*/\
-	MUX_VAL(CP(CAM_XCLKB),		(IEN  | PTD | DIS | M4)) /*GPIO_111 - A*/\
- /*Audio Interface To External DAC (Headphone, Speakers)*/\
-	MUX_VAL(CP(MCBSP2_FSX),		(IDIS | PTD | DIS | M0)) /*McBSP2_FSX*/\
-	MUX_VAL(CP(MCBSP2_CLKX),	(IDIS | PTD | DIS | M0)) /*McBSP2_CLKX*/\
-	MUX_VAL(CP(MCBSP2_DX),		(IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
-	MUX_VAL(CP(MCBSP_CLKS),		(IEN  | PTD | DIS | M0)) /*McBSP_CLKS*/\
-	MUX_VAL(CP(MCBSP2_DR),		(IDIS | PTD | DIS | M4)) /*GPIO_118*/\
-								 /* - nPOWERDOWN_DAC*/\
- /*Expansion card 1*/\
-	MUX_VAL(CP(MMC1_CLK),		(IDIS | PTU | EN  | M0)) /*MMC1_CLK*/\
-	MUX_VAL(CP(MMC1_CMD),		(IEN  | PTU | EN  | M0)) /*MMC1_CMD*/\
-	MUX_VAL(CP(MMC1_DAT0),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT0*/\
-	MUX_VAL(CP(MMC1_DAT1),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT1*/\
-	MUX_VAL(CP(MMC1_DAT2),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT2*/\
-	MUX_VAL(CP(MMC1_DAT3),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT3*/\
-	MUX_VAL(CP(MMC1_DAT4),		(IEN  | PTD | DIS | M4)) /*GPIO_126 - MMC1_WP*/\
- /*Expansion card 2*/\
-	MUX_VAL(CP(MMC2_CLK),		(IDIS | PTD | DIS | M0)) /*MMC2_CLK*/\
-	MUX_VAL(CP(MMC2_CMD),		(IEN  | PTU | EN  | M0)) /*MMC2_CMD*/\
-	MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT0*/\
-	MUX_VAL(CP(MMC2_DAT1),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT1*/\
-	MUX_VAL(CP(MMC2_DAT2),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT2*/\
-	MUX_VAL(CP(MMC2_DAT3),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT3*/\
-	MUX_VAL(CP(MMC2_DAT4),		(IDIS | PTD | DIS | M1)) /*MMC2_DIR_DAT0*/\
-	MUX_VAL(CP(MMC2_DAT5),		(IDIS | PTD | DIS | M1)) /*MMC2_DIR_DAT1*/\
-	MUX_VAL(CP(MMC2_DAT6),		(IDIS | PTD | DIS | M1)) /*MMC2_DIR_CMD */\
-	MUX_VAL(CP(MMC2_DAT7),		(IEN  | PTU | EN  | M1)) /*MMC2_CLKIN*/\
-	MUX_VAL(CP(MMC1_DAT5),		(IEN  | PTD | DIS | M4)) /*GPIO_127 - MMC2_WP*/\
- /*SDIO Interface to WIFI Module*/\
-	MUX_VAL(CP(ETK_CLK_ES2),	(IEN  | PTD | DIS | M2)) /*MMC3_CLK*/\
-	MUX_VAL(CP(ETK_CTL_ES2),	(IEN  | PTU | EN  | M2)) /*MMC3_CMD*/\
-	MUX_VAL(CP(ETK_D4_ES2),		(IEN  | PTU | EN  | M2)) /*MMC3_DAT0*/\
-	MUX_VAL(CP(ETK_D5_ES2),		(IEN  | PTU | EN  | M2)) /*MMC3_DAT1*/\
-	MUX_VAL(CP(ETK_D6_ES2),		(IEN  | PTU | EN  | M2)) /*MMC3_DAT2*/\
-	MUX_VAL(CP(ETK_D3_ES2),		(IEN  | PTU | EN  | M2)) /*MMC3_DAT3*/\
- /*Audio Interface To Bluetooth chip*/\
-	MUX_VAL(CP(MCBSP3_DX),		(IDIS | PTD | DIS | M0)) /*McBSP3_DX*/\
-	MUX_VAL(CP(MCBSP3_DR),		(IEN  | PTD | DIS | M0)) /*McBSP3_DR*/\
-	MUX_VAL(CP(MCBSP3_CLKX),	(IEN  | PTD | DIS | M0)) /*McBSP3_CLKX*/\
-	MUX_VAL(CP(MCBSP3_FSX),		(IEN  | PTD | DIS | M0)) /*McBSP3_FSX*/\
- /*Digital Interface to Bluetooth (UART)*/\
-	MUX_VAL(CP(UART1_TX),		(IDIS | PTD | DIS | M0)) /*UART1_TX*/\
-	MUX_VAL(CP(UART1_RTS),		(IDIS | PTD | DIS | M0)) /*UART1_RTS*/\
-	MUX_VAL(CP(UART1_CTS),		(IEN  | PTU | EN  | M0)) /*UART1_CTS*/\
-	MUX_VAL(CP(UART1_RX),		(IEN  | PTD | DIS | M0)) /*UART1_RX*/\
- /*Audio Interface to Triton2 chip (TPS65950)*/\
-	MUX_VAL(CP(MCBSP4_CLKX),	(IEN  | PTD | DIS | M0)) /*McBSP4_CLKX*/\
-	MUX_VAL(CP(MCBSP4_DR),		(IEN  | PTD | DIS | M0)) /*McBSP4_DR*/\
-	MUX_VAL(CP(MCBSP4_DX),		(IDIS | PTD | DIS | M0)) /*McBSP4_DX*/\
-	MUX_VAL(CP(MCBSP4_FSX),		(IEN  | PTD | DIS | M0)) /*McBSP4_FSX*/\
- /*GPIO definitions for muxed pins on AV connector*/\
-	MUX_VAL(CP(UART2_CTS),		(IEN  | PTD | EN  | M4)) /*GPIO_144,*/\
-								 /*UART2_CTS*/\
-	MUX_VAL(CP(UART2_RTS),		(IEN  | PTD | EN  | M4)) /*GPIO_145,*/\
-								 /*UART2_RTS*/\
-	MUX_VAL(CP(UART2_TX),		(IEN  | PTD | EN  | M4)) /*GPIO_146,*/\
-								 /*UART2_TX*/\
-	MUX_VAL(CP(UART2_RX),		(IEN  | PTD | EN  | M4)) /*GPIO_147,*/\
-								 /*UART2_RX*/\
- /*Serial Interface (Peripheral boot, Linux console, on AV connector)*/\
- /*RX pulled up to avoid noise when nothing is connected to serial port*/\
-	MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTU | EN  | M0)) /*UART3_RX*/\
-	MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M0)) /*UART3_TX*/\
- /*LEDs (Controlled by OMAP)*/\
-	MUX_VAL(CP(MMC1_DAT6),		(IDIS | PTD | DIS | M4)) /*GPIO_128*/\
-								 /* - LED_MMC1*/\
-	MUX_VAL(CP(MMC1_DAT7),		(IDIS | PTD | DIS | M4)) /*GPIO_129*/\
-								 /* - LED_MMC2*/\
-	MUX_VAL(CP(MCBSP1_DX),		(IDIS | PTD | DIS | M4)) /*GPIO_158*/\
-								 /* - LED_BT*/\
-	MUX_VAL(CP(MCBSP1_DR),		(IDIS | PTD | DIS | M4)) /*GPIO_159*/\
-								 /* - LED_WIFI*/\
- /*Switches*/\
-	MUX_VAL(CP(MCSPI1_CS2),		(IEN  | PTD | DIS | M4)) /*GPIO_176*/\
-								 /* - nHOLD_SWITCH*/\
-	MUX_VAL(CP(CAM_D9),		(IEN  | PTD | DIS | M4)) /*GPIO_108*/\
-								 /* - nLID_SWITCH*/\
- /*External IRQs*/\
-	MUX_VAL(CP(CAM_HS),		(IEN  | PTD | DIS | M4)) /*GPIO_94*/\
-								 /* - nTOUCH_IRQ*/\
-	MUX_VAL(CP(ETK_D7_ES2),		(IEN  | PTD | DIS | M4)) /*GPIO_21*/\
-								 /* - WIFI_IRQ*/\
-	MUX_VAL(CP(MCBSP1_FSX),		(IEN  | PTD | DIS | M4)) /*GPIO_161*/\
-								 /* - nIRQ_NUB1*/\
-	MUX_VAL(CP(MCBSP1_CLKX),	(IEN  | PTD | DIS | M4)) /*GPIO_162*/\
-								 /* - nIRQ_NUB2*/\
- /*Various other stuff*/\
-	MUX_VAL(CP(UART3_CTS_RCTX),	(IEN  | PTD | DIS | M4)) /*GPIO_163*/\
-								 /* - nOC_USB5*/\
-	MUX_VAL(CP(ETK_D8_ES2),		(IEN  | PTD | DIS | M4)) /*GPIO_22*/\
-								 /* - MSECURE*/\
-	MUX_VAL(CP(CSI2_DY1),		(IEN  | PTD | DIS | M4)) /*GPIO_115*/\
-								 /* - POP_OVERHEAT*/\
- /*External Resets and Enables*/\
-	MUX_VAL(CP(ETK_D0_ES2),		(IDIS | PTD | DIS | M4)) /*GPIO_14*/\
-								 /* - nHDPHN_SHUTDOWN*/\
-	MUX_VAL(CP(ETK_D1_ES2),		(IDIS | PTD | DIS | M4)) /*GPIO_15*/\
-								 /* - nBT_SHUTDOWN*/\
-	MUX_VAL(CP(ETK_D9_ES2),		(IDIS | PTD | DIS | M4)) /*GPIO_23*/\
-								 /* - nWIFI_RESET*/\
-	MUX_VAL(CP(MCBSP1_FSR),		(IDIS | PTU | DIS | M4)) /*GPIO_157*/\
-								 /* - nLCD_RESET*/\
-	MUX_VAL(CP(MCBSP1_CLKR),	(IDIS | PTD | DIS | M4)) /*GPIO_156*/\
-								 /* - RESET_NUBS*/\
-	MUX_VAL(CP(UART3_RTS_SD),	(IDIS | PTD | DIS | M4)) /*GPIO_164*/\
-								 /* - EN_USB_5V*/\
- /*Spare GPIOs*/\
-	MUX_VAL(CP(GPMC_NCS7),		(IEN  | PTD | EN  | M4)) /*GPIO_58*/\
-	MUX_VAL(CP(GPMC_WAIT2),		(IEN  | PTD | EN  | M4)) /*GPIO_64*/\
-	MUX_VAL(CP(GPMC_WAIT3),		(IEN  | PTD | EN  | M4)) /*GPIO_65*/\
-	MUX_VAL(CP(CAM_VS),		(IEN  | PTU | EN  | M4)) /*GPIO_95*/\
-	MUX_VAL(CP(CAM_WEN),		(IEN  | PTD | EN  | M4)) /*GPIO_167*/\
-	MUX_VAL(CP(HDQ_SIO),		(IEN  | PTD | EN  | M4)) /*GPIO_170*/\
- /*HS USB OTG Port (connects to HSUSB0)*/\
-	MUX_VAL(CP(HSUSB0_CLK),		(IEN  | PTD | DIS | M0)) /*HSUSB0_CLK*/\
-	MUX_VAL(CP(HSUSB0_STP),		(IDIS | PTU | EN  | M0)) /*HSUSB0_STP*/\
-	MUX_VAL(CP(HSUSB0_DIR),		(IEN  | PTD | DIS | M0)) /*HSUSB0_DIR*/\
-	MUX_VAL(CP(HSUSB0_NXT),		(IEN  | PTD | DIS | M0)) /*HSUSB0_NXT*/\
-	MUX_VAL(CP(HSUSB0_DATA0),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
-	MUX_VAL(CP(HSUSB0_DATA1),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
-	MUX_VAL(CP(HSUSB0_DATA2),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
-	MUX_VAL(CP(HSUSB0_DATA3),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
-	MUX_VAL(CP(HSUSB0_DATA4),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
-	MUX_VAL(CP(HSUSB0_DATA5),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
-	MUX_VAL(CP(HSUSB0_DATA6),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
-	MUX_VAL(CP(HSUSB0_DATA7),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
- /*I2C Ports*/\
-	MUX_VAL(CP(I2C1_SCL),		(IEN  | PTU | EN  | M0)) /*I2C1_SCL - T2_CTRL*/\
-	MUX_VAL(CP(I2C1_SDA),		(IEN  | PTU | EN  | M0)) /*I2C1_SDA - T2_CTRL*/\
-	MUX_VAL(CP(I2C3_SCL),		(IEN  | PTU | EN  | M0)) /*I2C3_SCL - NUBS*/\
-	MUX_VAL(CP(I2C3_SDA),		(IEN  | PTU | EN  | M0)) /*I2C3_SDA - NUBS*/\
-	MUX_VAL(CP(I2C4_SCL),		(IEN  | PTU | EN  | M0)) /*I2C4_SCL - T2_SR*/\
-	MUX_VAL(CP(I2C4_SDA),		(IEN  | PTU | EN  | M0)) /*I2C4_SDA - T2_SR*/\
- /*Serial Interface (Touch, LCD control)*/\
-	MUX_VAL(CP(MCSPI1_CLK),		(IEN  | PTD | DIS | M0)) /*McSPI1_CLK*/\
-	MUX_VAL(CP(MCSPI1_SIMO),	(IEN  | PTD | DIS | M0)) /*McSPI1_SIMO*/\
-	MUX_VAL(CP(MCSPI1_SOMI),	(IEN  | PTD | DIS | M0)) /*McSPI1_SOMI*/\
-	MUX_VAL(CP(MCSPI1_CS0),		(IDIS | PTU | EN  | M0)) /*McSPI1_CS0 - TOUCH*/\
-	MUX_VAL(CP(MCSPI1_CS1),		(IDIS | PTU | EN  | M0)) /*McSPI1_CS1 - LCD*/\
- /*HS USB HOST Port (connects to HSUSB2)*/\
-	MUX_VAL(CP(ETK_D10_ES2),	(IDIS | PTD | DIS | M3)) /*USB_HOST_CLK*/\
-	MUX_VAL(CP(ETK_D11_ES2),	(IDIS | PTU | EN  | M3)) /*USB_HOST_STP*/\
-	MUX_VAL(CP(ETK_D12_ES2),	(IEN  | PTD | DIS | M3)) /*USB_HOST_DIR*/\
-	MUX_VAL(CP(ETK_D13_ES2),	(IEN  | PTD | DIS | M3)) /*USB_HOST_NXT*/\
-	MUX_VAL(CP(ETK_D14_ES2),	(IEN  | PTD | DIS | M3)) /*USB_HOST_D0*/\
-	MUX_VAL(CP(ETK_D15_ES2),	(IEN  | PTD | DIS | M3)) /*USB_HOST_D1*/\
-	MUX_VAL(CP(MCSPI1_CS3),		(IEN  | PTD | DIS | M3)) /*USB_HOST_D2*/\
-	MUX_VAL(CP(MCSPI2_CS1),		(IEN  | PTD | DIS | M3)) /*USB_HOST_D3*/\
-	MUX_VAL(CP(MCSPI2_SIMO),	(IEN  | PTD | DIS | M3)) /*USB_HOST_D4*/\
-	MUX_VAL(CP(MCSPI2_SOMI),	(IEN  | PTD | DIS | M3)) /*USB_HOST_D5*/\
-	MUX_VAL(CP(MCSPI2_CS0),		(IEN  | PTD | DIS | M3)) /*USB_HOST_D6*/\
-	MUX_VAL(CP(MCSPI2_CLK),		(IEN  | PTD | DIS | M3)) /*USB_HOST_D7*/\
-	MUX_VAL(CP(ETK_D2_ES2),		(IDIS | PTD | DIS | M4)) /*GPIO_16*/\
-								 /* - nRESET_USB_HOST*/\
- /*Control and debug */\
-	MUX_VAL(CP(SYS_32K),		(IEN  | PTD | DIS | M0)) /*SYS_32K*/\
-	MUX_VAL(CP(SYS_CLKREQ),		(IEN  | PTD | DIS | M0)) /*SYS_CLKREQ*/\
-	MUX_VAL(CP(SYS_NIRQ),		(IEN  | PTU | EN  | M0)) /*SYS_nIRQ*/\
-	MUX_VAL(CP(SYS_BOOT0),		(IEN  | PTD | DIS | M4)) /*GPIO_2*/\
-	MUX_VAL(CP(SYS_BOOT1),		(IEN  | PTD | DIS | M4)) /*GPIO_3*/\
-	MUX_VAL(CP(SYS_BOOT2),		(IEN  | PTD | DIS | M4)) /*GPIO_4*/\
-	MUX_VAL(CP(SYS_BOOT3),		(IEN  | PTD | DIS | M4)) /*GPIO_5*/\
-	MUX_VAL(CP(SYS_BOOT4),		(IEN  | PTD | DIS | M4)) /*GPIO_6*/\
-	MUX_VAL(CP(SYS_BOOT5),		(IEN  | PTD | DIS | M4)) /*GPIO_7*/\
-	MUX_VAL(CP(SYS_BOOT6),		(IEN  | PTD | DIS | M4)) /*GPIO_8*/\
-	MUX_VAL(CP(SYS_OFF_MODE),	(IEN  | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
- /*JTAG*/\
-	MUX_VAL(CP(JTAG_NTRST),		(IEN  | PTD | DIS | M0)) /*JTAG_NTRST*/\
-	MUX_VAL(CP(JTAG_TCK),		(IEN  | PTD | DIS | M0)) /*JTAG_TCK*/\
-	MUX_VAL(CP(JTAG_TMS),		(IEN  | PTD | DIS | M0)) /*JTAG_TMS*/\
-	MUX_VAL(CP(JTAG_TDI),		(IEN  | PTD | DIS | M0)) /*JTAG_TDI*/\
-	MUX_VAL(CP(JTAG_EMU0),		(IEN  | PTD | DIS | M0)) /*JTAG_EMU0*/\
-	MUX_VAL(CP(JTAG_EMU1),		(IEN  | PTD | DIS | M0)) /*JTAG_EMU1*/\
- /*Die to Die stuff*/\
-	MUX_VAL(CP(D2D_MCAD1),		(IEN  | PTD | EN  | M0)) /*d2d_mcad1*/\
-	MUX_VAL(CP(D2D_MCAD2),		(IEN  | PTD | EN  | M0)) /*d2d_mcad2*/\
-	MUX_VAL(CP(D2D_MCAD3),		(IEN  | PTD | EN  | M0)) /*d2d_mcad3*/\
-	MUX_VAL(CP(D2D_MCAD4),		(IEN  | PTD | EN  | M0)) /*d2d_mcad4*/\
-	MUX_VAL(CP(D2D_MCAD5),		(IEN  | PTD | EN  | M0)) /*d2d_mcad5*/\
-	MUX_VAL(CP(D2D_MCAD6),		(IEN  | PTD | EN  | M0)) /*d2d_mcad6*/\
-	MUX_VAL(CP(D2D_MCAD7),		(IEN  | PTD | EN  | M0)) /*d2d_mcad7*/\
-	MUX_VAL(CP(D2D_MCAD8),		(IEN  | PTD | EN  | M0)) /*d2d_mcad8*/\
-	MUX_VAL(CP(D2D_MCAD9),		(IEN  | PTD | EN  | M0)) /*d2d_mcad9*/\
-	MUX_VAL(CP(D2D_MCAD10),		(IEN  | PTD | EN  | M0)) /*d2d_mcad10*/\
-	MUX_VAL(CP(D2D_MCAD11),		(IEN  | PTD | EN  | M0)) /*d2d_mcad11*/\
-	MUX_VAL(CP(D2D_MCAD12),		(IEN  | PTD | EN  | M0)) /*d2d_mcad12*/\
-	MUX_VAL(CP(D2D_MCAD13),		(IEN  | PTD | EN  | M0)) /*d2d_mcad13*/\
-	MUX_VAL(CP(D2D_MCAD14),		(IEN  | PTD | EN  | M0)) /*d2d_mcad14*/\
-	MUX_VAL(CP(D2D_MCAD15),		(IEN  | PTD | EN  | M0)) /*d2d_mcad15*/\
-	MUX_VAL(CP(D2D_MCAD16),		(IEN  | PTD | EN  | M0)) /*d2d_mcad16*/\
-	MUX_VAL(CP(D2D_MCAD17),		(IEN  | PTD | EN  | M0)) /*d2d_mcad17*/\
-	MUX_VAL(CP(D2D_MCAD18),		(IEN  | PTD | EN  | M0)) /*d2d_mcad18*/\
-	MUX_VAL(CP(D2D_MCAD19),		(IEN  | PTD | EN  | M0)) /*d2d_mcad19*/\
-	MUX_VAL(CP(D2D_MCAD20),		(IEN  | PTD | EN  | M0)) /*d2d_mcad20*/\
-	MUX_VAL(CP(D2D_MCAD21),		(IEN  | PTD | EN  | M0)) /*d2d_mcad21*/\
-	MUX_VAL(CP(D2D_MCAD22),		(IEN  | PTD | EN  | M0)) /*d2d_mcad22*/\
-	MUX_VAL(CP(D2D_MCAD23),		(IEN  | PTD | EN  | M0)) /*d2d_mcad23*/\
-	MUX_VAL(CP(D2D_MCAD24),		(IEN  | PTD | EN  | M0)) /*d2d_mcad24*/\
-	MUX_VAL(CP(D2D_MCAD25),		(IEN  | PTD | EN  | M0)) /*d2d_mcad25*/\
-	MUX_VAL(CP(D2D_MCAD26),		(IEN  | PTD | EN  | M0)) /*d2d_mcad26*/\
-	MUX_VAL(CP(D2D_MCAD27),		(IEN  | PTD | EN  | M0)) /*d2d_mcad27*/\
-	MUX_VAL(CP(D2D_MCAD28),		(IEN  | PTD | EN  | M0)) /*d2d_mcad28*/\
-	MUX_VAL(CP(D2D_MCAD29),		(IEN  | PTD | EN  | M0)) /*d2d_mcad29*/\
-	MUX_VAL(CP(D2D_MCAD30),		(IEN  | PTD | EN  | M0)) /*d2d_mcad30*/\
-	MUX_VAL(CP(D2D_MCAD31),		(IEN  | PTD | EN  | M0)) /*d2d_mcad31*/\
-	MUX_VAL(CP(D2D_MCAD32),		(IEN  | PTD | EN  | M0)) /*d2d_mcad32*/\
-	MUX_VAL(CP(D2D_MCAD33),		(IEN  | PTD | EN  | M0)) /*d2d_mcad33*/\
-	MUX_VAL(CP(D2D_MCAD34),		(IEN  | PTD | EN  | M0)) /*d2d_mcad34*/\
-	MUX_VAL(CP(D2D_MCAD35),		(IEN  | PTD | EN  | M0)) /*d2d_mcad35*/\
-	MUX_VAL(CP(D2D_MCAD36),		(IEN  | PTD | EN  | M0)) /*d2d_mcad36*/\
-	MUX_VAL(CP(D2D_CLK26MI),	(IEN  | PTD | DIS | M0)) /*d2d_clk26mi*/\
-	MUX_VAL(CP(D2D_NRESPWRON),	(IEN  | PTD | EN  | M0)) /*d2d_nrespwron*/\
-	MUX_VAL(CP(D2D_NRESWARM),	(IEN  | PTU | EN  | M0)) /*d2d_nreswarm*/\
-	MUX_VAL(CP(D2D_ARM9NIRQ),	(IEN  | PTD | DIS | M0)) /*d2d_arm9nirq*/\
-	MUX_VAL(CP(D2D_UMA2P6FIQ),	(IEN  | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
-	MUX_VAL(CP(D2D_SPINT),		(IEN  | PTD | EN  | M0)) /*d2d_spint*/\
-	MUX_VAL(CP(D2D_FRINT),		(IEN  | PTD | EN  | M0)) /*d2d_frint*/\
-	MUX_VAL(CP(D2D_DMAREQ0),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq0*/\
-	MUX_VAL(CP(D2D_DMAREQ1),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq1*/\
-	MUX_VAL(CP(D2D_DMAREQ2),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq2*/\
-	MUX_VAL(CP(D2D_DMAREQ3),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq3*/\
-	MUX_VAL(CP(D2D_N3GTRST),	(IEN  | PTD | DIS | M0)) /*d2d_n3gtrst*/\
-	MUX_VAL(CP(D2D_N3GTDI),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtdi*/\
-	MUX_VAL(CP(D2D_N3GTDO),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtdo*/\
-	MUX_VAL(CP(D2D_N3GTMS),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtms*/\
-	MUX_VAL(CP(D2D_N3GTCK),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtck*/\
-	MUX_VAL(CP(D2D_N3GRTCK),	(IEN  | PTD | DIS | M0)) /*d2d_n3grtck*/\
-	MUX_VAL(CP(D2D_MSTDBY),		(IEN  | PTU | EN  | M0)) /*d2d_mstdby*/\
-	MUX_VAL(CP(D2D_SWAKEUP),	(IEN  | PTD | EN  | M0)) /*d2d_swakeup*/\
-	MUX_VAL(CP(D2D_IDLEREQ),	(IEN  | PTD | DIS | M0)) /*d2d_idlereq*/\
-	MUX_VAL(CP(D2D_IDLEACK),	(IEN  | PTU | EN  | M0)) /*d2d_idleack*/\
-	MUX_VAL(CP(D2D_MWRITE),		(IEN  | PTD | DIS | M0)) /*d2d_mwrite*/\
-	MUX_VAL(CP(D2D_SWRITE),		(IEN  | PTD | DIS | M0)) /*d2d_swrite*/\
-	MUX_VAL(CP(D2D_MREAD),		(IEN  | PTD | DIS | M0)) /*d2d_mread*/\
-	MUX_VAL(CP(D2D_SREAD),		(IEN  | PTD | DIS | M0)) /*d2d_sread*/\
-	MUX_VAL(CP(D2D_MBUSFLAG),	(IEN  | PTD | DIS | M0)) /*d2d_mbusflag*/\
-	MUX_VAL(CP(D2D_SBUSFLAG),	(IEN  | PTD | DIS | M0)) /*d2d_sbusflag*/\
-	MUX_VAL(CP(SDRC_CKE0),		(IDIS | PTU | EN  | M0)) /*sdrc_cke0*/\
-	MUX_VAL(CP(SDRC_CKE1),		(IDIS | PTU | EN  | M0)) /*sdrc_cke1*/
-
-#define MUX_PANDORA_3730() \
-	MUX_VAL(CP(GPIO126),		(IEN  | PTD | DIS | M4)) /*GPIO_126 - MMC1_WP*/\
-	MUX_VAL(CP(GPIO127),		(IEN  | PTD | DIS | M4)) /*GPIO_127 - MMC2_WP*/\
-	MUX_VAL(CP(GPIO128),		(IDIS | PTD | DIS | M4)) /*GPIO_128 - LED_MMC1*/\
-	MUX_VAL(CP(GPIO129),		(IDIS | PTD | DIS | M4)) /*GPIO_129 - LED_MMC2*/
-
-#endif

board/phytec/pcm051/Kconfig

@@ -1,15 +0,0 @@
-if TARGET_PCM051
-
-config SYS_BOARD
-	default "pcm051"
-
-config SYS_VENDOR
-	default "phytec"
-
-config SYS_SOC
-	default "am33xx"
-
-config SYS_CONFIG_NAME
-	default "pcm051"
-
-endif

board/phytec/pcm051/MAINTAINERS

@@ -1,7 +0,0 @@
-PCM051 BOARD
-M:	Lars Poeschel <poeschel@lemonage.de>
-S:	Maintained
-F:	board/phytec/pcm051/
-F:	include/configs/pcm051.h
-F:	configs/pcm051_rev1_defconfig
-F:	configs/pcm051_rev3_defconfig

board/phytec/pcm051/Makefile

@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Makefile
-#
-# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
-
-ifdef CONFIG_SPL_BUILD
-obj-y	+= mux.o
-endif
-
-obj-y	+= board.o

board/phytec/pcm051/board.c

@@ -1,258 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * board.c
- *
- * Board functions for Phytec phyCORE-AM335x (pcm051) based boards
- *
- * Copyright (C) 2013 Lemonage Software GmbH
- * Author Lars Poeschel <poeschel@lemonage.de>
- */
-
-#include <common.h>
-#include <env.h>
-#include <errno.h>
-#include <init.h>
-#include <net.h>
-#include <spl.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/omap.h>
-#include <asm/arch/ddr_defs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/io.h>
-#include <asm/emif.h>
-#include <asm/gpio.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <cpsw.h>
-#include "board.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* MII mode defines */
-#define RMII_RGMII2_MODE_ENABLE	0x49
-
-static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
-
-#ifdef CONFIG_SPL_BUILD
-
-/* DDR RAM defines */
-#define DDR_CLK_MHZ		303 /* DDR_DPLL_MULT value */
-
-#define OSC	(V_OSCK/1000000)
-const struct dpll_params dpll_ddr = {
-		DDR_CLK_MHZ, OSC-1, 1, -1, -1, -1, -1};
-
-const struct dpll_params *get_dpll_ddr_params(void)
-{
-	return &dpll_ddr;
-}
-
-#ifdef CONFIG_REV1
-const struct ctrl_ioregs ioregs = {
-	.cm0ioctl		= MT41J256M8HX15E_IOCTRL_VALUE,
-	.cm1ioctl		= MT41J256M8HX15E_IOCTRL_VALUE,
-	.cm2ioctl		= MT41J256M8HX15E_IOCTRL_VALUE,
-	.dt0ioctl		= MT41J256M8HX15E_IOCTRL_VALUE,
-	.dt1ioctl		= MT41J256M8HX15E_IOCTRL_VALUE,
-};
-
-static const struct ddr_data ddr3_data = {
-	.datardsratio0 = MT41J256M8HX15E_RD_DQS,
-	.datawdsratio0 = MT41J256M8HX15E_WR_DQS,
-	.datafwsratio0 = MT41J256M8HX15E_PHY_FIFO_WE,
-	.datawrsratio0 = MT41J256M8HX15E_PHY_WR_DATA,
-};
-
-static const struct cmd_control ddr3_cmd_ctrl_data = {
-	.cmd0csratio = MT41J256M8HX15E_RATIO,
-	.cmd0iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
-
-	.cmd1csratio = MT41J256M8HX15E_RATIO,
-	.cmd1iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
-
-	.cmd2csratio = MT41J256M8HX15E_RATIO,
-	.cmd2iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
-};
-
-static struct emif_regs ddr3_emif_reg_data = {
-	.sdram_config = MT41J256M8HX15E_EMIF_SDCFG,
-	.ref_ctrl = MT41J256M8HX15E_EMIF_SDREF,
-	.sdram_tim1 = MT41J256M8HX15E_EMIF_TIM1,
-	.sdram_tim2 = MT41J256M8HX15E_EMIF_TIM2,
-	.sdram_tim3 = MT41J256M8HX15E_EMIF_TIM3,
-	.zq_config = MT41J256M8HX15E_ZQ_CFG,
-	.emif_ddr_phy_ctlr_1 = MT41J256M8HX15E_EMIF_READ_LATENCY |
-				PHY_EN_DYN_PWRDN,
-};
-
-void sdram_init(void)
-{
-	config_ddr(DDR_CLK_MHZ, &ioregs, &ddr3_data,
-		   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
-}
-#else
-const struct ctrl_ioregs ioregs = {
-	.cm0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
-	.cm1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
-	.cm2ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
-	.dt0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
-	.dt1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
-};
-
-static const struct ddr_data ddr3_data = {
-	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
-	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
-	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
-	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
-};
-
-static const struct cmd_control ddr3_cmd_ctrl_data = {
-	.cmd0csratio = MT41K256M16HA125E_RATIO,
-	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
-
-	.cmd1csratio = MT41K256M16HA125E_RATIO,
-	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
-
-	.cmd2csratio = MT41K256M16HA125E_RATIO,
-	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
-};
-
-static struct emif_regs ddr3_emif_reg_data = {
-	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
-	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
-	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
-	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
-	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
-	.zq_config = MT41K256M16HA125E_ZQ_CFG,
-	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY |
-				PHY_EN_DYN_PWRDN,
-};
-
-void sdram_init(void)
-{
-	config_ddr(DDR_CLK_MHZ, &ioregs, &ddr3_data,
-		   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
-}
-#endif
-
-void set_uart_mux_conf(void)
-{
-	enable_uart0_pin_mux();
-}
-
-void set_mux_conf_regs(void)
-{
-	/* Initalize the board header */
-	enable_i2c0_pin_mux();
-	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
-
-	enable_board_pin_mux();
-}
-#endif
-
-/*
- * Basic board specific setup.  Pinmux has been handled already.
- */
-int board_init(void)
-{
-	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
-
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
-	return 0;
-}
-
-#ifdef CONFIG_DRIVER_TI_CPSW
-static void cpsw_control(int enabled)
-{
-	/* VTP can be added here */
-
-	return;
-}
-
-static struct cpsw_slave_data cpsw_slaves[] = {
-	{
-		.slave_reg_ofs	= 0x208,
-		.sliver_reg_ofs	= 0xd80,
-		.phy_addr	= 0,
-		.phy_if		= PHY_INTERFACE_MODE_RGMII,
-	},
-	{
-		.slave_reg_ofs	= 0x308,
-		.sliver_reg_ofs	= 0xdc0,
-		.phy_addr	= 1,
-		.phy_if		= PHY_INTERFACE_MODE_RGMII,
-	},
-};
-
-static struct cpsw_platform_data cpsw_data = {
-	.mdio_base		= CPSW_MDIO_BASE,
-	.cpsw_base		= CPSW_BASE,
-	.mdio_div		= 0xff,
-	.channels		= 8,
-	.cpdma_reg_ofs		= 0x800,
-	.slaves			= 1,
-	.slave_data		= cpsw_slaves,
-	.ale_reg_ofs		= 0xd00,
-	.ale_entries		= 1024,
-	.host_port_reg_ofs	= 0x108,
-	.hw_stats_reg_ofs	= 0x900,
-	.bd_ram_ofs		= 0x2000,
-	.mac_control		= (1 << 5),
-	.control		= cpsw_control,
-	.host_port_num		= 0,
-	.version		= CPSW_CTRL_VERSION_2,
-};
-#endif
-
-#if defined(CONFIG_DRIVER_TI_CPSW) || \
-	(defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET))
-int board_eth_init(bd_t *bis)
-{
-	int rv, n = 0;
-#ifdef CONFIG_DRIVER_TI_CPSW
-	uint8_t mac_addr[6];
-	uint32_t mac_hi, mac_lo;
-
-	if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
-		printf("<ethaddr> not set. Reading from E-fuse\n");
-		/* try reading mac address from efuse */
-		mac_lo = readl(&cdev->macid0l);
-		mac_hi = readl(&cdev->macid0h);
-		mac_addr[0] = mac_hi & 0xFF;
-		mac_addr[1] = (mac_hi & 0xFF00) >> 8;
-		mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
-		mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
-		mac_addr[4] = mac_lo & 0xFF;
-		mac_addr[5] = (mac_lo & 0xFF00) >> 8;
-
-		if (is_valid_ethaddr(mac_addr))
-			eth_env_set_enetaddr("ethaddr", mac_addr);
-		else
-			goto try_usbether;
-	}
-
-	writel(RMII_RGMII2_MODE_ENABLE, &cdev->miisel);
-
-	rv = cpsw_register(&cpsw_data);
-	if (rv < 0)
-		printf("Error %d registering CPSW switch\n", rv);
-	else
-		n += rv;
-try_usbether:
-#endif
-
-#if defined(CONFIG_USB_ETHER) && !defined(CONFIG_SPL_BUILD)
-	rv = usb_eth_initialize(bis);
-	if (rv < 0)
-		printf("Error %d registering USB_ETHER\n", rv);
-	else
-		n += rv;
-#endif
-	return n;
-}
-#endif

board/phytec/pcm051/board.h

@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * board.h
- *
- * Phytec phyCORE-AM335x (pcm051) boards information header
- *
- * Copyright (C) 2013, Lemonage Software GmbH
- * Author Lars Poeschel <poeschel@lemonage.de>
- */
-
-#ifndef _BOARD_H_
-#define _BOARD_H_
-
-/*
- * We have three pin mux functions that must exist.  We must be able to enable
- * uart0, for initial output and i2c0 to read the main EEPROM.  We then have a
- * main pinmux function that can be overridden to enable all other pinmux that
- * is required on the board.
- */
-void enable_uart0_pin_mux(void);
-void enable_i2c0_pin_mux(void);
-void enable_board_pin_mux(void);
-void enable_cbmux_pin_mux(void);
-#endif

board/phytec/pcm051/mux.c

@@ -1,127 +0,0 @@
-/*
- * mux.c
- *
- * Copyright (C) 2013 Lemonage Software GmbH
- * Author Lars Poeschel <poeschel@lemonage.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <common.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/mux.h>
-#include <asm/io.h>
-#include "board.h"
-
-static struct module_pin_mux uart0_pin_mux[] = {
-	{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* UART0_RXD */
-	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},		/* UART0_TXD */
-	{-1},
-};
-
-#ifdef CONFIG_MMC
-static struct module_pin_mux mmc0_pin_mux[] = {
-	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT3 */
-	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT2 */
-	{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT1 */
-	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT0 */
-	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CLK */
-	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CMD */
-	{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)},	/* MMC0_CD */
-	{-1},
-};
-#endif
-
-#ifdef CONFIG_I2C
-static struct module_pin_mux i2c0_pin_mux[] = {
-	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
-			PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
-	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
-			PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
-	{-1},
-};
-#endif
-
-#ifdef CONFIG_SPI
-static struct module_pin_mux spi0_pin_mux[] = {
-	{OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)},	/* SPI0_SCLK */
-	{OFFSET(spi0_d0), (MODE(0) | RXACTIVE |
-			PULLUDEN | PULLUP_EN)},			/* SPI0_D0 */
-	{OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)},	/* SPI0_D1 */
-	{OFFSET(spi0_cs0), (MODE(0) | RXACTIVE |
-			PULLUDEN | PULLUP_EN)},			/* SPI0_CS0 */
-	{-1},
-};
-#endif
-
-static struct module_pin_mux rmii1_pin_mux[] = {
-	{OFFSET(mii1_crs), MODE(1) | RXACTIVE},     /* RMII1_CRS */
-	{OFFSET(mii1_rxerr), MODE(1) | RXACTIVE},   /* RMII1_RXERR */
-	{OFFSET(mii1_txen), MODE(1)},               /* RMII1_TXEN */
-	{OFFSET(mii1_txd1), MODE(1)},               /* RMII1_TXD1 */
-	{OFFSET(mii1_txd0), MODE(1)},               /* RMII1_TXD0 */
-	{OFFSET(mii1_rxd1), MODE(1) | RXACTIVE},    /* RMII1_RXD1 */
-	{OFFSET(mii1_rxd0), MODE(1) | RXACTIVE},    /* RMII1_RXD0 */
-	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
-	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},    /* MDIO_CLK */
-	{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REFCLK */
-	{-1},
-};
-
-static struct module_pin_mux cbmux_pin_mux[] = {
-	{OFFSET(uart0_ctsn), MODE(7) | RXACTIVE | PULLDOWN_EN}, /* JP3 */
-	{OFFSET(uart0_rtsn), MODE(7) | RXACTIVE | PULLUP_EN},	/* JP4 */
-	{-1},
-};
-
-#ifdef CONFIG_MTD_RAW_NAND
-static struct module_pin_mux nand_pin_mux[] = {
-	{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD0 */
-	{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD1 */
-	{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD2 */
-	{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD3 */
-	{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD4 */
-	{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD5 */
-	{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD6 */
-	{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD7 */
-	{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
-	{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)},	/* NAND_WPN */
-	{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)},	/* NAND_CS0 */
-	{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
-	{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)},	/* NAND_OE */
-	{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)},	/* NAND_WEN */
-	{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)},	/* NAND_BE_CLE */
-	{-1},
-};
-#endif
-
-void enable_uart0_pin_mux(void)
-{
-	configure_module_pin_mux(uart0_pin_mux);
-}
-
-void enable_i2c0_pin_mux(void)
-{
-	configure_module_pin_mux(i2c0_pin_mux);
-}
-
-void enable_board_pin_mux()
-{
-	configure_module_pin_mux(rmii1_pin_mux);
-	configure_module_pin_mux(mmc0_pin_mux);
-	configure_module_pin_mux(cbmux_pin_mux);
-#ifdef CONFIG_MTD_RAW_NAND
-	configure_module_pin_mux(nand_pin_mux);
-#endif
-#ifdef CONFIG_SPI
-	configure_module_pin_mux(spi0_pin_mux);
-#endif
-}

board/sifive/fu540/Kconfig

@@ -65,5 +65,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	imply SMP
 	imply MISC
 	imply SIFIVE_OTP
+	imply SYSRESET
+	imply SYSRESET_GPIO
 
 endif

board/sifive/fu540/fu540.c

@@ -15,6 +15,7 @@
 #include <linux/io.h>
 #include <misc.h>
 #include <spl.h>
+#include <asm/arch/cache.h>
 
 /*
  * This define is a value used for error/unknown serial.
@@ -114,7 +115,14 @@ int misc_init_r(void)
 
 int board_init(void)
 {
-	/* For now nothing to do here. */
+	int ret;
+
+	/* enable all cache ways */
+	ret = cache_enable_ways();
+	if (ret) {
+		debug("%s: could not enable cache ways\n", __func__);
+		return ret;
+	}
 
 	return 0;
 }

board/solidrun/mx6cuboxi/mx6cuboxi.c

@@ -17,7 +17,6 @@
 #include <image.h>
 #include <init.h>
 #include <log.h>
-#include <net.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/iomux.h>
@@ -33,8 +32,6 @@
 #include <mmc.h>
 #include <fsl_esdhc_imx.h>
 #include <malloc.h>
-#include <miiphy.h>
-#include <netdev.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/io.h>
 #include <asm/arch/sys_proto.h>
@@ -52,16 +49,6 @@ DECLARE_GLOBAL_DATA_PTR;
 	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
-#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
-	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
-#define ENET_PAD_CTRL_PD  (PAD_CTL_PUS_100K_DOWN |		\
-	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
-#define ENET_PAD_CTRL_CLK  ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
-	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
-
-#define ETH_PHY_RESET	IMX_GPIO_NR(4, 15)
 #define USB_H1_VBUS	IMX_GPIO_NR(1, 0)
 
 enum board_type {
@@ -167,180 +154,11 @@ static void setup_iomux_uart(void)
 	SETUP_IOMUX_PADS(uart1_pads);
 }
 
-static struct fsl_esdhc_cfg usdhc_cfg = {
-	.esdhc_base = USDHC2_BASE_ADDR,
-	.max_bus_width = 4,
-};
-
-static struct fsl_esdhc_cfg emmc_cfg = {
-	.esdhc_base = USDHC3_BASE_ADDR,
-	.max_bus_width = 8,
-};
-
 int board_mmc_get_env_dev(int devno)
 {
 	return devno;
 }
 
-#define USDHC2_CD_GPIO  IMX_GPIO_NR(1, 4)
-
-int board_mmc_getcd(struct mmc *mmc)
-{
-	struct fsl_esdhc_cfg *cfg = mmc->priv;
-	int ret = 0;
-
-	switch (cfg->esdhc_base) {
-	case USDHC2_BASE_ADDR:
-		ret = !gpio_get_value(USDHC2_CD_GPIO);
-		break;
-	case USDHC3_BASE_ADDR:
-		ret = (mmc_get_op_cond(mmc) < 0) ? 0 : 1; /* eMMC/uSDHC3 has no CD GPIO */
-		break;
-	}
-
-	return ret;
-}
-
-static int mmc_init_spl(bd_t *bis)
-{
-	struct src *psrc = (struct src *)SRC_BASE_ADDR;
-	unsigned reg = readl(&psrc->sbmr1) >> 11;
-
-	/*
-	 * Upon reading BOOT_CFG register the following map is done:
-	 * Bit 11 and 12 of BOOT_CFG register can determine the current
-	 * mmc port
-	 * 0x1                  SD2
-	 * 0x2                  SD3
-	 */
-	switch (reg & 0x3) {
-	case 0x1:
-		SETUP_IOMUX_PADS(usdhc2_pads);
-		usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-		gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk;
-		return fsl_esdhc_initialize(bis, &usdhc_cfg);
-	case 0x2:
-		SETUP_IOMUX_PADS(usdhc3_pads);
-		emmc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-		gd->arch.sdhc_clk = emmc_cfg.sdhc_clk;
-		return fsl_esdhc_initialize(bis, &emmc_cfg);
-	}
-
-	return -ENODEV;
-}
-
-int board_mmc_init(bd_t *bis)
-{
-	if (IS_ENABLED(CONFIG_SPL_BUILD))
-		return mmc_init_spl(bis);
-
-	return 0;
-}
-
-static iomux_v3_cfg_t const enet_pads[] = {
-	IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-	IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-	/* AR8035 reset */
-	IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
-	/* AR8035 interrupt */
-	IOMUX_PADS(PAD_DI0_PIN2__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
-	/* GPIO16 -> AR8035 25MHz */
-	IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK	  | MUX_PAD_CTRL(NO_PAD_CTRL)),
-	IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC	  | MUX_PAD_CTRL(NO_PAD_CTRL)),
-	IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-	IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-	IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-	IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-	IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-	/* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
-	IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK)),
-	IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-	IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
-	IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
-	IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-	IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-	IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
-	IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
-	IOMUX_PADS(PAD_ENET_RXD1__GPIO1_IO26 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
-};
-
-static void setup_iomux_enet(void)
-{
-	struct gpio_desc desc;
-	int ret;
-
-	SETUP_IOMUX_PADS(enet_pads);
-
-	ret = dm_gpio_lookup_name("GPIO4_15", &desc);
-	if (ret) {
-		printf("%s: phy reset lookup failed\n", __func__);
-		return;
-	}
-
-	ret = dm_gpio_request(&desc, "phy-reset");
-	if (ret) {
-		printf("%s: phy reset request failed\n", __func__);
-		return;
-	}
-
-	gpio_direction_output(ETH_PHY_RESET, 0);
-	mdelay(10);
-	gpio_set_value(ETH_PHY_RESET, 1);
-	udelay(100);
-
-	gpio_free_list_nodev(&desc, 1);
-}
-
-int board_phy_config(struct phy_device *phydev)
-{
-	if (phydev->drv->config)
-		phydev->drv->config(phydev);
-
-	return 0;
-}
-
-/* On Cuboxi Ethernet PHY can be located at addresses 0x0 or 0x4 */
-#define ETH_PHY_MASK	((1 << 0x0) | (1 << 0x4))
-
-int board_eth_init(bd_t *bis)
-{
-	struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
-	struct mii_dev *bus;
-	struct phy_device *phydev;
-
-	int ret = enable_fec_anatop_clock(0, ENET_25MHZ);
-	if (ret)
-		return ret;
-
-	/* set gpr1[ENET_CLK_SEL] */
-	setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
-
-	setup_iomux_enet();
-
-	bus = fec_get_miibus(IMX_FEC_BASE, -1);
-	if (!bus)
-		return -EINVAL;
-
-	phydev = phy_find_by_mask(bus, ETH_PHY_MASK, PHY_INTERFACE_MODE_RGMII);
-	if (!phydev) {
-		ret = -EINVAL;
-		goto free_bus;
-	}
-
-	debug("using phy at address %d\n", phydev->addr);
-	ret = fec_probe(bis, -1, IMX_FEC_BASE, bus, phydev);
-	if (ret)
-		goto free_phydev;
-
-	return 0;
-
-free_phydev:
-	free(phydev);
-free_bus:
-	free(bus);
-	return ret;
-}
-
 #ifdef CONFIG_VIDEO_IPUV3
 static void do_enable_hdmi(struct display_info_t const *dev)
 {
@@ -433,6 +251,21 @@ static int setup_display(void)
 }
 #endif /* CONFIG_VIDEO_IPUV3 */
 
+static int setup_fec(void)
+{
+	struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	int ret;
+
+	ret = enable_fec_anatop_clock(0, ENET_25MHZ);
+	if (ret)
+		return ret;
+
+	/* set gpr1[ENET_CLK_SEL] */
+	setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
+
+	return 0;
+}
+
 int board_early_init_f(void)
 {
 	setup_iomux_uart();
@@ -440,6 +273,8 @@ int board_early_init_f(void)
 #ifdef CONFIG_CMD_SATA
 	setup_sata();
 #endif
+	setup_fec();
+
 	return 0;
 }
 
@@ -629,6 +464,54 @@ int board_fit_config_name_match(const char *name)
 	return strcmp(name, tmp_name);
 }
 
+void board_boot_order(u32 *spl_boot_list)
+{
+	struct src *psrc = (struct src *)SRC_BASE_ADDR;
+	unsigned int reg = readl(&psrc->sbmr1) >> 11;
+	u32 boot_mode = imx6_src_get_boot_mode() & IMX6_BMODE_MASK;
+	unsigned int bmode = readl(&src_base->sbmr2);
+
+	/* If bmode is serial or USB phy is active, return serial */
+	if (((bmode >> 24) & 0x03) == 0x01 || is_usbotg_phy_active()) {
+		spl_boot_list[0] = BOOT_DEVICE_BOARD;
+		return;
+	}
+
+	switch (boot_mode >> IMX6_BMODE_SHIFT) {
+	case IMX6_BMODE_SD:
+	case IMX6_BMODE_ESD:
+	case IMX6_BMODE_MMC:
+	case IMX6_BMODE_EMMC:
+		/*
+		 * Upon reading BOOT_CFG register the following map is done:
+		 * Bit 11 and 12 of BOOT_CFG register can determine the current
+		 * mmc port
+		 * 0x1                  SD2
+		 * 0x2                  SD3
+		 */
+
+		reg &= 0x3; /* Only care about bottom 2 bits */
+		switch (reg) {
+		case 1:
+			SETUP_IOMUX_PADS(usdhc2_pads);
+			spl_boot_list[0] = BOOT_DEVICE_MMC1;
+			break;
+		case 2:
+			SETUP_IOMUX_PADS(usdhc3_pads);
+			spl_boot_list[0] = BOOT_DEVICE_MMC2;
+			break;
+		}
+		break;
+	default:
+		/* By default use USB downloader */
+		spl_boot_list[0] = BOOT_DEVICE_BOARD;
+		break;
+	}
+
+	/* As a last resort, use serial downloader */
+	spl_boot_list[1] = BOOT_DEVICE_BOARD;
+}
+
 #ifdef CONFIG_SPL_BUILD
 #include <asm/arch/mx6-ddr.h>
 static const struct mx6dq_iomux_ddr_regs mx6q_ddr_ioregs = {

board/toradex/colibri_t20/MAINTAINERS

@@ -1,5 +1,5 @@
 COLIBRI_T20
-M:	Lucas Stach <dev@lynxeye.de>
+M:	Igor Opaniuk <igor.opaniuk@toradex.com>
 S:	Maintained
 F:	board/toradex/colibri_t20/
 F:	include/configs/colibri_t20.h

board/wandboard/README

@@ -37,3 +37,13 @@ as the mx6 processor)
 - Connect the serial cable to the host PC
 
 - Power up the board and U-Boot messages will appear in the serial console.
+
+Debug UART
+----------
+
+The following settings provide a debug UART for the Wandboard:
+
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_MXC=y
+CONFIG_DEBUG_UART_BASE=0x02020000
+CONFIG_DEBUG_UART_CLOCK=80000000

cmd/bootefi.c

@@ -189,16 +189,20 @@ static void efi_carve_out_dt_rsv(void *fdt)
 	if (nodeoffset >= 0) {
 		subnode = fdt_first_subnode(fdt, nodeoffset);
 		while (subnode >= 0) {
+			fdt_addr_t fdt_addr;
+			fdt_size_t fdt_size;
+
 			/* check if this subnode has a reg property */
-			addr = fdtdec_get_addr_size(fdt, subnode, "reg",
-						    (fdt_size_t *)&size);
+			fdt_addr = fdtdec_get_addr_size_auto_parent(
+						fdt, nodeoffset, subnode,
+						"reg", 0, &fdt_size, false);
 			/*
 			 * The /reserved-memory node may have children with
 			 * a size instead of a reg property.
 			 */
-			if (addr != FDT_ADDR_T_NONE &&
+			if (fdt_addr != FDT_ADDR_T_NONE &&
 			    fdtdec_get_is_enabled(fdt, subnode))
-				efi_reserve_memory(addr, size);
+				efi_reserve_memory(fdt_addr, fdt_size);
 			subnode = fdt_next_subnode(fdt, subnode);
 		}
 	}

cmd/booti.c

@@ -141,7 +141,7 @@ static char booti_help_text[] =
 	"\tspecifying the size of a RAW initrd.\n"
 	"\tCurrently only booting from gz, bz2, lzma and lz4 compression\n"
 	"\ttypes are supported. In order to boot from any of these compressed\n"
-	"\timages, user have to set kernel_comp_addr_r and kernel_comp_size enviornment\n"
+	"\timages, user have to set kernel_comp_addr_r and kernel_comp_size environment\n"
 	"\tvariables beforehand.\n"
 #if defined(CONFIG_OF_LIBFDT)
 	"\tSince booting a Linux kernel requires a flat device-tree, a\n"

cmd/mmc.c

@@ -8,6 +8,7 @@
 #include <blk.h>
 #include <command.h>
 #include <console.h>
+#include <memalign.h>
 #include <mmc.h>
 #include <part.h>
 #include <sparse_format.h>
@@ -56,7 +57,8 @@ static void print_mmcinfo(struct mmc *mmc)
 	if (!IS_SD(mmc) && mmc->version >= MMC_VERSION_4_41) {
 		bool has_enh = (mmc->part_support & ENHNCD_SUPPORT) != 0;
 		bool usr_enh = has_enh && (mmc->part_attr & EXT_CSD_ENH_USR);
-		u8 wp, ext_csd[MMC_MAX_BLOCK_LEN];
+		ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
+		u8 wp;
 		int ret;
 
 #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
@@ -1004,7 +1006,7 @@ U_BOOT_CMD(
 	"mmc part - lists available partition on current mmc device\n"
 	"mmc dev [dev] [part] - show or set current mmc device [partition]\n"
 	"mmc list - lists available devices\n"
-	"mmc wp - power on write protect booot partitions\n"
+	"mmc wp - power on write protect boot partitions\n"
 #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
 	"mmc hwpartition [args...] - does hardware partitioning\n"
 	"  arguments (sizes in 512-byte blocks):\n"

common/spl/spl_opensbi.c

@@ -56,7 +56,7 @@ void spl_invoke_opensbi(struct spl_image_info *spl_image)
 	/* Find U-Boot image in /fit-images */
 	ret = spl_opensbi_find_uboot_node(spl_image->fdt_addr, &uboot_node);
 	if (ret) {
-		pr_err("Can't find U-Boot node, %d", ret);
+		pr_err("Can't find U-Boot node, %d\n", ret);
 		hang();
 	}
 

common/splash.c

@@ -59,7 +59,7 @@ static struct splash_location default_splash_locations[] = {
 static int splash_video_logo_load(void)
 {
 	char *splashimage;
-	u32 bmp_load_addr;
+	ulong bmp_load_addr;
 
 	splashimage = env_get("splashimage");
 	if (!splashimage)

configs/B4420QDS_NAND_defconfig

@@ -4,10 +4,10 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x140000
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_B4420QDS=y
 CONFIG_SYS_CUSTOM_LDSCRIPT=y

configs/B4860QDS_NAND_defconfig

@@ -4,10 +4,10 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x140000
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_B4860QDS=y
 CONFIG_SYS_CUSTOM_LDSCRIPT=y

configs/BSC9131RDB_NAND_SYSCLK100_defconfig

@@ -2,9 +2,9 @@ CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0x00201000
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_OFFSET=0xE0000
+CONFIG_SPL_TEXT_BASE=0xFFFFE000
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFFFFE000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_BSC9131RDB=y
 CONFIG_SYS_CUSTOM_LDSCRIPT=y

configs/BSC9131RDB_NAND_defconfig

@@ -2,9 +2,9 @@ CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0x00201000
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_OFFSET=0xE0000
+CONFIG_SPL_TEXT_BASE=0xFFFFE000
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFFFFE000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_BSC9131RDB=y
 CONFIG_SYS_CUSTOM_LDSCRIPT=y

configs/BSC9132QDS_NAND_DDRCLK100_defconfig

@@ -2,9 +2,9 @@ CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0x00201000
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_OFFSET=0xE0000
+CONFIG_SPL_TEXT_BASE=0xFFFFE000
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0xFFFFE000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_BSC9132QDS=y
 CONFIG_SYS_CUSTOM_LDSCRIPT=y