Prepare v2022.01

Signed-off-by: Tom Rini <trini@konsulko.com>

.mailmap

@@ -20,6 +20,8 @@ Allen Martin <amartin@nvidia.com>
 Andreas Bießmann <andreas.devel@googlemail.com>
 Andreas Bießmann <andreas@biessmann.org>
 Aneesh V <aneesh@ti.com>
+Anup Patel <anup@brainfault.org> <anup.patel@wdc.com>
+Atish Patra <atishp@atishpatra.org> <atish.patra@wdc.com>
 Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@bootlin.com>
 Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@free-electrons.com>
 Dirk Behme <dirk.behme@googlemail.com>

Makefile

@@ -3,7 +3,7 @@
 VERSION = 2022
 PATCHLEVEL = 01
 SUBLEVEL =
-EXTRAVERSION = -rc4
+EXTRAVERSION =
 NAME =
 
 # *DOCUMENTATION*
@@ -1315,6 +1315,7 @@ cmd_binman = $(srctree)/tools/binman/binman $(if $(BINMAN_DEBUG),-D) \
 		-a tpl-bss-pad=$(if $(CONFIG_TPL_SEPARATE_BSS),,1) \
 		-a spl-dtb=$(CONFIG_SPL_OF_REAL) \
 		-a tpl-dtb=$(CONFIG_TPL_OF_REAL) \
+		$(if $(BINMAN_FAKE_EXT_BLOBS),--fake-ext-blobs) \
 		$(BINMAN_$(@F))
 
 OBJCOPYFLAGS_u-boot.ldr.hex := -I binary -O ihex

arch/arm/dts/Makefile

@@ -78,8 +78,9 @@ dtb-$(CONFIG_MACH_S700) += \
 dtb-$(CONFIG_ROCKCHIP_PX30) += \
 	px30-evb.dtb \
 	px30-firefly.dtb \
-	px30-px30-core-ctouch2.dtb \
-	px30-px30-core-edimm2.2.dtb \
+	px30-engicam-px30-core-ctouch2.dtb \
+	px30-engicam-px30-core-ctouch2-of10.dtb \
+	px30-engicam-px30-core-edimm2.2.dtb \
 	rk3326-odroid-go2.dtb
 
 dtb-$(CONFIG_ROCKCHIP_RK3036) += \

arch/arm/dts/imx6qdl-udoo.dtsi

@@ -4,7 +4,7 @@
  *
  * Author: Fabio Estevam <fabio.estevam@freescale.com>
  */
-
+#include <dt-bindings/gpio/gpio.h>
 / {
 	aliases {
 		backlight = &backlight;
@@ -226,6 +226,7 @@
 				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
 				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
 				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
+				MX6QDL_PAD_SD3_DAT5__GPIO7_IO00		0x1b0b0
 			>;
 		};
 
@@ -304,7 +305,7 @@
 &usdhc3 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_usdhc3>;
-	non-removable;
+	cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
 	status = "okay";
 };
 

arch/arm/dts/imx6sx-udoo-neo-u-boot.dtsi

@@ -1,7 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-
-/ {
-	aliases {
-		mmc0 = &usdhc2;
-	};
-};

arch/arm/dts/imx8mm-cl-iot-gate-optee-u-boot.dtsi

@@ -3,74 +3,50 @@
  * Copyright 2019 NXP
  */
 
+#include "imx8mm-u-boot.dtsi"
+
 / {
-	binman: binman {
-		multiple-images;
-	};
-
-	wdt-reboot {
-		compatible = "wdt-reboot";
-		wdt = <&wdog1>;
-		u-boot,dm-spl;
-	};
-
 	firmware {
 		optee {
 			compatible = "linaro,optee-tz";
 			method = "smc";
 		};
 	};
+
+	wdt-reboot {
+		compatible = "wdt-reboot";
+		u-boot,dm-spl;
+		wdt = <&wdog1>;
+	};
 };
 
-&{/soc@0} {
-	u-boot,dm-pre-reloc;
+&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b} {
 	u-boot,dm-spl;
 };
 
-&clk {
-	u-boot,dm-spl;
-	u-boot,dm-pre-reloc;
-	/delete-property/ assigned-clocks;
-	/delete-property/ assigned-clock-parents;
-	/delete-property/ assigned-clock-rates;
-};
-
-&osc_24m {
-	u-boot,dm-spl;
-	u-boot,dm-pre-reloc;
-};
-
-&aips1 {
-	u-boot,dm-spl;
-	u-boot,dm-pre-reloc;
-};
-
-&aips2 {
+&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b/regulators} {
 	u-boot,dm-spl;
 };
 
-&aips3 {
-	u-boot,dm-spl;
+&binman_fip {
+	arch = "arm64";
+	compression = "none";
+	description = "Trusted Firmware FIP";
+	load = <0x40310000>;
+	type = "firmware";
+
+	fip_blob {
+		filename = "fip.bin";
+		type = "blob-ext";
+	};
 };
 
-&iomuxc {
-	u-boot,dm-spl;
+&binman_configuration {
+	loadables = "atf", "fip";
 };
 
-&pinctrl_uart3 {
-	u-boot,dm-spl;
-};
-
-&pinctrl_usdhc2_gpio {
-	u-boot,dm-spl;
-};
-
-&pinctrl_usdhc2 {
-	u-boot,dm-spl;
-};
-
-&pinctrl_usdhc3 {
-	u-boot,dm-spl;
+&fec1 {
+	phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
 };
 
 &gpio1 {
@@ -93,6 +69,38 @@
 	u-boot,dm-spl;
 };
 
+&i2c1 {
+	u-boot,dm-spl;
+};
+
+&i2c2 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_i2c2 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_pmic {
+	u-boot,dm-spl;
+};
+
+&pinctrl_uart3 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_gpio {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+	u-boot,dm-spl;
+};
+
 &uart3 {
 	u-boot,dm-spl;
 };
@@ -109,147 +117,6 @@
 	u-boot,dm-spl;
 };
 
-&i2c1 {
-	u-boot,dm-spl;
-};
-
-&i2c2 {
-	u-boot,dm-spl;
-};
-
-&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b} {
-	u-boot,dm-spl;
-};
-
-&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b/regulators} {
-	u-boot,dm-spl;
-};
-
-&pinctrl_i2c2 {
-	u-boot,dm-spl;
-};
-
-&pinctrl_pmic {
-	u-boot,dm-spl;
-};
-
-&fec1 {
-	phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
-};
-
 &wdog1 {
 	u-boot,dm-spl;
 };
-
-&binman {
-	u-boot-spl-ddr {
-		filename = "u-boot-spl-ddr.bin";
-		pad-byte = <0xff>;
-		align-size = <4>;
-		align = <4>;
-
-		u-boot-spl {
-			align-end = <4>;
-		};
-
-		blob_1: blob-ext@1 {
-			filename = "lpddr4_pmu_train_1d_imem.bin";
-			size = <0x8000>;
-		};
-
-		blob_2: blob-ext@2 {
-			filename = "lpddr4_pmu_train_1d_dmem.bin";
-			size = <0x4000>;
-		};
-
-		blob_3: blob-ext@3 {
-			filename = "lpddr4_pmu_train_2d_imem.bin";
-			size = <0x8000>;
-		};
-
-		blob_4: blob-ext@4 {
-			filename = "lpddr4_pmu_train_2d_dmem.bin";
-			size = <0x4000>;
-		};
-	};
-
-	flash {
-		mkimage {
-			args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x7e1000";
-
-			blob {
-				filename = "u-boot-spl-ddr.bin";
-			};
-		};
-	};
-
-	itb {
-		filename = "u-boot.itb";
-
-		fit {
-			description = "Configuration to load ATF before U-Boot";
-			#address-cells = <1>;
-			fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
-
-			images {
-				uboot {
-					description = "U-Boot (64-bit)";
-					type = "standalone";
-					arch = "arm64";
-					compression = "none";
-					load = <CONFIG_SYS_TEXT_BASE>;
-
-					uboot_blob: blob-ext {
-						filename = "u-boot-nodtb.bin";
-					};
-				};
-
-				atf {
-					description = "ARM Trusted Firmware";
-					type = "firmware";
-					arch = "arm64";
-					compression = "none";
-					load = <0x920000>;
-					entry = <0x920000>;
-
-					atf_blob: blob-ext {
-						filename = "bl2.bin";
-					};
-				};
-
-				fip {
-					description = "Trusted Firmware FIP";
-					type = "firmware";
-					arch = "arm64";
-					compression = "none";
-					load = <0x40310000>;
-
-					fip_blob: blob-ext{
-						filename = "fip.bin";
-					};
-				};
-
-				fdt {
-					description = "NAME";
-					type = "flat_dt";
-					compression = "none";
-
-					uboot_fdt_blob: blob-ext {
-						filename = "u-boot.dtb";
-					};
-				};
-			};
-
-			configurations {
-				default = "conf";
-
-				conf {
-					description = "NAME";
-					firmware = "uboot";
-					loadables = "atf", "fip";
-					fdt = "fdt";
-				};
-			};
-		};
-	};
-};

arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi

@@ -3,74 +3,33 @@
  * Copyright 2019 NXP
  */
 
+#include "imx8mm-u-boot.dtsi"
+
 / {
-	binman: binman {
-		multiple-images;
-	};
-
-	wdt-reboot {
-		compatible = "wdt-reboot";
-		wdt = <&wdog1>;
-		u-boot,dm-spl;
-	};
-
 	firmware {
 		optee {
 			compatible = "linaro,optee-tz";
 			method = "smc";
 		};
 	};
+
+	wdt-reboot {
+		compatible = "wdt-reboot";
+		u-boot,dm-spl;
+		wdt = <&wdog1>;
+	};
 };
 
-&{/soc@0} {
-	u-boot,dm-pre-reloc;
+&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b} {
 	u-boot,dm-spl;
 };
 
-&clk {
-	u-boot,dm-spl;
-	u-boot,dm-pre-reloc;
-	/delete-property/ assigned-clocks;
-	/delete-property/ assigned-clock-parents;
-	/delete-property/ assigned-clock-rates;
-};
-
-&osc_24m {
-	u-boot,dm-spl;
-	u-boot,dm-pre-reloc;
-};
-
-&aips1 {
-	u-boot,dm-spl;
-	u-boot,dm-pre-reloc;
-};
-
-&aips2 {
+&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b/regulators} {
 	u-boot,dm-spl;
 };
 
-&aips3 {
-	u-boot,dm-spl;
-};
-
-&iomuxc {
-	u-boot,dm-spl;
-};
-
-&pinctrl_uart3 {
-	u-boot,dm-spl;
-};
-
-&pinctrl_usdhc2_gpio {
-	u-boot,dm-spl;
-};
-
-&pinctrl_usdhc2 {
-	u-boot,dm-spl;
-};
-
-&pinctrl_usdhc3 {
-	u-boot,dm-spl;
+&fec1 {
+	phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
 };
 
 &gpio1 {
@@ -93,6 +52,38 @@
 	u-boot,dm-spl;
 };
 
+&i2c1 {
+	u-boot,dm-spl;
+};
+
+&i2c2 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_i2c2 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_pmic {
+	u-boot,dm-spl;
+};
+
+&pinctrl_uart3 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_gpio {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+	u-boot,dm-spl;
+};
+
 &uart3 {
 	u-boot,dm-spl;
 };
@@ -109,135 +100,6 @@
 	u-boot,dm-spl;
 };
 
-&i2c1 {
-	u-boot,dm-spl;
-};
-
-&i2c2 {
-	u-boot,dm-spl;
-};
-
-&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b} {
-	u-boot,dm-spl;
-};
-
-&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b/regulators} {
-	u-boot,dm-spl;
-};
-
-&pinctrl_i2c2 {
-	u-boot,dm-spl;
-};
-
-&pinctrl_pmic {
-	u-boot,dm-spl;
-};
-
-&fec1 {
-	phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
-};
-
 &wdog1 {
 	u-boot,dm-spl;
 };
-
-&binman {
-	u-boot-spl-ddr {
-		filename = "u-boot-spl-ddr.bin";
-		pad-byte = <0xff>;
-		align-size = <4>;
-		align = <4>;
-
-		u-boot-spl {
-			align-end = <4>;
-		};
-
-		blob_1: blob-ext@1 {
-			filename = "lpddr4_pmu_train_1d_imem.bin";
-			size = <0x8000>;
-		};
-
-		blob_2: blob-ext@2 {
-			filename = "lpddr4_pmu_train_1d_dmem.bin";
-			size = <0x4000>;
-		};
-
-		blob_3: blob-ext@3 {
-			filename = "lpddr4_pmu_train_2d_imem.bin";
-			size = <0x8000>;
-		};
-
-		blob_4: blob-ext@4 {
-			filename = "lpddr4_pmu_train_2d_dmem.bin";
-			size = <0x4000>;
-		};
-	};
-
-	flash {
-		mkimage {
-			args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x7e1000";
-
-			blob {
-				filename = "u-boot-spl-ddr.bin";
-			};
-		};
-	};
-
-	itb {
-		filename = "u-boot.itb";
-
-		fit {
-			description = "Configuration to load ATF before U-Boot";
-			#address-cells = <1>;
-			fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
-
-			images {
-				uboot {
-					description = "U-Boot (64-bit)";
-					type = "standalone";
-					arch = "arm64";
-					compression = "none";
-					load = <CONFIG_SYS_TEXT_BASE>;
-
-					uboot_blob: blob-ext {
-						filename = "u-boot-nodtb.bin";
-					};
-				};
-
-				atf {
-					description = "ARM Trusted Firmware";
-					type = "firmware";
-					arch = "arm64";
-					compression = "none";
-					load = <0x920000>;
-					entry = <0x920000>;
-
-					atf_blob: blob-ext {
-						filename = "bl31.bin";
-					};
-				};
-
-				fdt {
-					description = "NAME";
-					type = "flat_dt";
-					compression = "none";
-
-					uboot_fdt_blob: blob-ext {
-						filename = "u-boot.dtb";
-					};
-				};
-			};
-
-			configurations {
-				default = "conf";
-
-				conf {
-					description = "NAME";
-					firmware = "uboot";
-					loadables = "atf";
-					fdt = "fdt";
-				};
-			};
-		};
-	};
-};

arch/arm/dts/imx8mm-evk-u-boot.dtsi

@@ -6,10 +6,6 @@
 #include "imx8mm-u-boot.dtsi"
 
 / {
-	binman: binman {
-		multiple-images;
-	};
-
 	wdt-reboot {
 		compatible = "wdt-reboot";
 		wdt = <&wdog1>;
@@ -116,122 +112,3 @@
 &wdog1 {
 	u-boot,dm-spl;
 };
-
-&binman {
-	 u-boot-spl-ddr {
-		filename = "u-boot-spl-ddr.bin";
-		pad-byte = <0xff>;
-		align-size = <4>;
-		align = <4>;
-
-		u-boot-spl {
-			align-end = <4>;
-		};
-
-		blob_1: blob-ext@1 {
-			filename = "lpddr4_pmu_train_1d_imem.bin";
-			size = <0x8000>;
-		};
-
-		blob_2: blob-ext@2 {
-			filename = "lpddr4_pmu_train_1d_dmem.bin";
-			size = <0x4000>;
-		};
-
-		blob_3: blob-ext@3 {
-			filename = "lpddr4_pmu_train_2d_imem.bin";
-			size = <0x8000>;
-		};
-
-		blob_4: blob-ext@4 {
-			filename = "lpddr4_pmu_train_2d_dmem.bin";
-			size = <0x4000>;
-		};
-	};
-
-
-	spl {
-		filename = "spl.bin";
-
-		mkimage {
-			args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x7e1000";
-
-			blob {
-				filename = "u-boot-spl-ddr.bin";
-			};
-		};
-	};
-
-	itb {
-		filename = "u-boot.itb";
-
-		fit {
-			description = "Configuration to load ATF before U-Boot";
-			#address-cells = <1>;
-			fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
-
-			images {
-				uboot {
-					description = "U-Boot (64-bit)";
-					type = "standalone";
-					arch = "arm64";
-					compression = "none";
-					load = <CONFIG_SYS_TEXT_BASE>;
-
-					uboot_blob: blob-ext {
-						filename = "u-boot-nodtb.bin";
-					};
-				};
-
-				atf {
-					description = "ARM Trusted Firmware";
-					type = "firmware";
-					arch = "arm64";
-					compression = "none";
-					load = <0x920000>;
-					entry = <0x920000>;
-
-					atf_blob: blob-ext {
-						filename = "bl31.bin";
-					};
-				};
-
-				fdt {
-					description = "NAME";
-					type = "flat_dt";
-					compression = "none";
-
-					uboot_fdt_blob: blob-ext {
-						filename = "u-boot.dtb";
-					};
-				};
-			};
-
-			configurations {
-				default = "conf";
-
-				conf {
-					description = "NAME";
-					firmware = "uboot";
-					loadables = "atf";
-					fdt = "fdt";
-				};
-			};
-		};
-	};
-
-	imx-boot {
-		filename = "flash.bin";
-		pad-byte = <0x00>;
-
-		spl: blob-ext@1 {
-			offset = <0x0>;
-			filename = "spl.bin";
-		};
-
-		uboot: blob-ext@2 {
-			offset = <0x57c00>;
-			filename = "u-boot.itb";
-		};
-	};
-};

arch/arm/dts/imx8mm-kontron-n801x-s-u-boot.dtsi

@@ -11,10 +11,6 @@
 		usb1 = &usbotg2;
 	};
 
-	binman: binman {
-		multiple-images;
-	};
-
 	wdt-reboot {
 		compatible = "wdt-reboot";
 		wdt = <&wdog1>;
@@ -130,145 +126,3 @@
 &wdog1 {
 	u-boot,dm-spl;
 };
-
-&binman {
-	u-boot-spl-ddr {
-		filename = "u-boot-spl-ddr.bin";
-		pad-byte = <0xff>;
-		align-size = <4>;
-		align = <4>;
-
-		u-boot-spl {
-			align-end = <4>;
-		};
-
-		blob_1: blob-ext@1 {
-			filename = "lpddr4_pmu_train_1d_imem.bin";
-			size = <0x8000>;
-		};
-
-		blob_2: blob-ext@2 {
-			filename = "lpddr4_pmu_train_1d_dmem.bin";
-			size = <0x4000>;
-		};
-
-		blob_3: blob-ext@3 {
-			filename = "lpddr4_pmu_train_2d_imem.bin";
-			size = <0x8000>;
-		};
-
-		blob_4: blob-ext@4 {
-			filename = "lpddr4_pmu_train_2d_dmem.bin";
-			size = <0x4000>;
-		};
-	};
-
-	spl {
-		filename = "spl.bin";
-
-		mkimage {
-			args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x7e1000";
-
-			blob {
-				filename = "u-boot-spl-ddr.bin";
-			};
-		};
-	};
-
-	itb {
-		filename = "u-boot.itb";
-
-		fit {
-			description = "Configuration to load ATF before U-Boot";
-			#address-cells = <1>;
-			fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
-
-			images {
-				uboot {
-					description = "U-Boot (64-bit)";
-					type = "standalone";
-					arch = "arm64";
-					compression = "none";
-					load = <CONFIG_SYS_TEXT_BASE>;
-
-					uboot_blob: blob-ext {
-						filename = "u-boot-nodtb.bin";
-					};
-				};
-
-				atf {
-					description = "ARM Trusted Firmware";
-					type = "firmware";
-					arch = "arm64";
-					compression = "none";
-					load = <0x920000>;
-					entry = <0x920000>;
-
-					atf_blob: blob-ext {
-						filename = "bl31.bin";
-					};
-				};
-
-				fdt {
-					description = "NAME";
-					type = "flat_dt";
-					compression = "none";
-
-					uboot_fdt_blob: blob-ext {
-						filename = "u-boot.dtb";
-					};
-				};
-			};
-
-			configurations {
-				default = "conf";
-
-				conf {
-					description = "NAME";
-					firmware = "uboot";
-					loadables = "atf";
-					fdt = "fdt";
-				};
-			};
-		};
-	};
-
-	imx-boot {
-		filename = "flash.bin";
-		pad-byte = <0x00>;
-
-		spl: blob-ext@1 {
-			offset = <0x0>;
-			filename = "spl.bin";
-		};
-
-		uboot: blob-ext@2 {
-			offset = <0x57c00>;
-			filename = "u-boot.itb";
-		};
-	};
-
-	u-boot-update {
-		filename = "firmware-update.itb";
-
-		fit {
-			description = "Configuration for firmware update file";
-
-			images {
-				flash-bin {
-					description = "U-Boot flash image";
-					type = "firmware";
-					os = "u-boot";
-					arch = "arm";
-					compress = "none";
-					load = <0>; /* unused */
-
-					blob {
-						filename = "flash.bin";
-					};
-
-				};
-			};
-		};
-	};
-};

arch/arm/dts/imx8mm-u-boot.dtsi

@@ -3,14 +3,20 @@
  * Copyright (C) 2020 Jagan Teki <jagan@amarulasolutions.com>
  */
 
+/ {
+	binman: binman {
+		multiple-images;
+	};
+};
+
 &{/soc@0} {
 	u-boot,dm-pre-reloc;
 	u-boot,dm-spl;
 };
 
 &aips1 {
-	u-boot,dm-spl;
 	u-boot,dm-pre-reloc;
+	u-boot,dm-spl;
 };
 
 &aips2 {
@@ -21,9 +27,146 @@
 	u-boot,dm-spl;
 };
 
+&binman {
+	u-boot-spl-ddr {
+		align = <4>;
+		align-size = <4>;
+		filename = "u-boot-spl-ddr.bin";
+		pad-byte = <0xff>;
+
+		u-boot-spl {
+			align-end = <4>;
+			filename = "u-boot-spl.bin";
+		};
+
+		1d-imem {
+			filename = "lpddr4_pmu_train_1d_imem.bin";
+			size = <0x8000>;
+			type = "blob-ext";
+		};
+
+		1d_dmem {
+			filename = "lpddr4_pmu_train_1d_dmem.bin";
+			size = <0x4000>;
+			type = "blob-ext";
+		};
+
+		2d_imem {
+			filename = "lpddr4_pmu_train_2d_imem.bin";
+			size = <0x8000>;
+			type = "blob-ext";
+		};
+
+		2d_dmem {
+			filename = "lpddr4_pmu_train_2d_dmem.bin";
+			size = <0x4000>;
+			type = "blob-ext";
+		};
+	};
+
+	spl {
+		filename = "spl.bin";
+
+		mkimage {
+			args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x7e1000";
+
+			blob {
+				filename = "u-boot-spl-ddr.bin";
+			};
+		};
+	};
+
+	itb {
+		filename = "u-boot.itb";
+
+		fit {
+			description = "Configuration to load ATF before U-Boot";
+			fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
+			fit,fdt-list = "of-list";
+			#address-cells = <1>;
+
+			images {
+				uboot {
+					arch = "arm64";
+					compression = "none";
+					description = "U-Boot (64-bit)";
+					load = <CONFIG_SYS_TEXT_BASE>;
+					type = "standalone";
+
+					uboot_blob {
+						filename = "u-boot-nodtb.bin";
+						type = "blob-ext";
+					};
+				};
+
+				atf {
+					arch = "arm64";
+					compression = "none";
+					description = "ARM Trusted Firmware";
+					entry = <0x920000>;
+					load = <0x920000>;
+					type = "firmware";
+
+					atf_blob {
+						filename = "bl31.bin";
+						type = "blob-ext";
+					};
+				};
+
+				binman_fip: fip {
+					arch = "arm64";
+					compression = "none";
+					description = "Trusted Firmware FIP";
+					load = <0x40310000>;
+					type = "firmware";
+				};
+
+				@fdt-SEQ {
+					compression = "none";
+					description = "NAME";
+					type = "flat_dt";
+
+					uboot_fdt_blob {
+						filename = "u-boot.dtb";
+						type = "blob-ext";
+					};
+				};
+			};
+
+			configurations {
+				default = "@config-DEFAULT-SEQ";
+
+				binman_configuration: @config-SEQ {
+					description = "NAME";
+					fdt = "fdt-SEQ";
+					firmware = "uboot";
+					loadables = "atf";
+				};
+			};
+		};
+	};
+
+	imx-boot {
+		filename = "flash.bin";
+		pad-byte = <0x00>;
+
+		spl {
+			filename = "spl.bin";
+			offset = <0x0>;
+			type = "blob-ext";
+		};
+
+		binman_uboot: uboot {
+			filename = "u-boot.itb";
+			offset = <0x57c00>;
+			type = "blob-ext";
+		};
+	};
+};
+
 &clk {
-	u-boot,dm-spl;
 	u-boot,dm-pre-reloc;
+	u-boot,dm-spl;
 	/delete-property/ assigned-clocks;
 	/delete-property/ assigned-clock-parents;
 	/delete-property/ assigned-clock-rates;
@@ -34,6 +177,6 @@
 };
 
 &osc_24m {
-	u-boot,dm-spl;
 	u-boot,dm-pre-reloc;
+	u-boot,dm-spl;
 };

arch/arm/dts/imx8mm-verdin-u-boot.dtsi

@@ -6,10 +6,6 @@
 #include "imx8mm-u-boot.dtsi"
 
 / {
-	binman: binman {
-		multiple-images;
-	};
-
 	firmware {
 		optee {
 			compatible = "linaro,optee-tz";
@@ -100,120 +96,6 @@
 	u-boot,dm-spl;
 };
 
-&binman {
-	 u-boot-spl-ddr {
-		filename = "u-boot-spl-ddr.bin";
-		pad-byte = <0xff>;
-		align-size = <4>;
-		align = <4>;
-
-		u-boot-spl {
-			align-end = <4>;
-		};
-
-		blob_1: blob-ext@1 {
-			filename = "lpddr4_pmu_train_1d_imem.bin";
-			size = <0x8000>;
-		};
-
-		blob_2: blob-ext@2 {
-			filename = "lpddr4_pmu_train_1d_dmem.bin";
-			size = <0x4000>;
-		};
-
-		blob_3: blob-ext@3 {
-			filename = "lpddr4_pmu_train_2d_imem.bin";
-			size = <0x8000>;
-		};
-
-		blob_4: blob-ext@4 {
-			filename = "lpddr4_pmu_train_2d_dmem.bin";
-			size = <0x4000>;
-		};
-	};
-
-	spl {
-		filename = "spl.bin";
-
-		mkimage {
-			args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x7e1000";
-
-			blob {
-				filename = "u-boot-spl-ddr.bin";
-			};
-		};
-	};
-
-	itb {
-		filename = "u-boot.itb";
-
-		fit {
-			description = "Configuration to load ATF before U-Boot";
-			#address-cells = <1>;
-			fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
-
-			images {
-				uboot {
-					description = "U-Boot (64-bit)";
-					type = "standalone";
-					arch = "arm64";
-					compression = "none";
-					load = <CONFIG_SYS_TEXT_BASE>;
-
-					uboot_blob: blob-ext {
-						filename = "u-boot-nodtb.bin";
-					};
-				};
-
-				atf {
-					description = "ARM Trusted Firmware";
-					type = "firmware";
-					arch = "arm64";
-					compression = "none";
-					load = <0x920000>;
-					entry = <0x920000>;
-
-					atf_blob: blob-ext {
-						filename = "bl31.bin";
-					};
-				};
-
-				fdt {
-					description = "NAME";
-					type = "flat_dt";
-					compression = "none";
-
-					uboot_fdt_blob: blob-ext {
-						filename = "u-boot.dtb";
-					};
-				};
-			};
-
-			configurations {
-				default = "conf";
-
-				conf {
-					description = "NAME";
-					firmware = "uboot";
-					loadables = "atf";
-					fdt = "fdt";
-				};
-			};
-		};
-	};
-
-	imx-boot {
-		filename = "flash.bin";
-		pad-byte = <0x00>;
-
-		spl: blob-ext@1 {
-			offset = <0x0>;
-			filename = "spl.bin";
-		};
-
-		uboot: blob-ext@2 {
-			offset = <0x5fc00>;
-			filename = "u-boot.itb";
-		};
-	};
+&binman_uboot {
+	offset = <0x5fc00>;
 };

arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi

@@ -4,6 +4,10 @@
  */
 
 / {
+	binman: binman {
+		multiple-images;
+	};
+
 	wdt-reboot {
 		compatible = "wdt-reboot";
 		wdt = <&wdog1>;
@@ -40,6 +44,9 @@
 &clk {
 	u-boot,dm-spl;
 	u-boot,dm-pre-reloc;
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-parents;
+	/delete-property/ assigned-clock-rates;
 };
 
 &gpio1 {
@@ -99,6 +106,10 @@
 	u-boot,off-on-delay-us = <20000>;
 };
 
+&uart2 {
+	u-boot,dm-spl;
+};
+
 &usdhc1 {
 	u-boot,dm-spl;
 	sd-uhs-sdr104;
@@ -120,3 +131,122 @@
 &wdog1 {
 	u-boot,dm-spl;
 };
+
+&binman {
+	 u-boot-spl-ddr {
+		filename = "u-boot-spl-ddr.bin";
+		pad-byte = <0xff>;
+		align-size = <4>;
+		align = <4>;
+
+		u-boot-spl {
+			align-end = <4>;
+		};
+
+		blob_1: blob-ext@1 {
+			filename = "lpddr4_pmu_train_1d_imem.bin";
+			size = <0x8000>;
+		};
+
+		blob_2: blob-ext@2 {
+			filename = "lpddr4_pmu_train_1d_dmem.bin";
+			size = <0x4000>;
+		};
+
+		blob_3: blob-ext@3 {
+			filename = "lpddr4_pmu_train_2d_imem.bin";
+			size = <0x8000>;
+		};
+
+		blob_4: blob-ext@4 {
+			filename = "lpddr4_pmu_train_2d_dmem.bin";
+			size = <0x4000>;
+		};
+	};
+
+
+	spl {
+		filename = "spl.bin";
+
+		mkimage {
+			args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x912000";
+
+			blob {
+				filename = "u-boot-spl-ddr.bin";
+			};
+		};
+	};
+
+	itb {
+		filename = "u-boot.itb";
+
+		fit {
+			description = "Configuration to load ATF before U-Boot";
+			#address-cells = <1>;
+			fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
+
+			images {
+				uboot {
+					description = "U-Boot (64-bit)";
+					type = "standalone";
+					arch = "arm64";
+					compression = "none";
+					load = <CONFIG_SYS_TEXT_BASE>;
+
+					uboot_blob: blob-ext {
+						filename = "u-boot-nodtb.bin";
+					};
+				};
+
+				atf {
+					description = "ARM Trusted Firmware";
+					type = "firmware";
+					arch = "arm64";
+					compression = "none";
+					load = <0x960000>;
+					entry = <0x960000>;
+
+					atf_blob: blob-ext {
+						filename = "bl31.bin";
+					};
+				};
+
+				fdt {
+					description = "NAME";
+					type = "flat_dt";
+					compression = "none";
+
+					uboot_fdt_blob: blob-ext {
+						filename = "u-boot.dtb";
+					};
+				};
+			};
+
+			configurations {
+				default = "conf";
+
+				conf {
+					description = "NAME";
+					firmware = "uboot";
+					loadables = "atf";
+					fdt = "fdt";
+				};
+			};
+		};
+	};
+
+	imx-boot {
+		filename = "flash.bin";
+		pad-byte = <0x00>;
+
+		spl: blob-ext@1 {
+			offset = <0x0>;
+			filename = "spl.bin";
+		};
+
+		uboot: blob-ext@2 {
+			offset = <0x58000>;
+			filename = "u-boot.itb";
+		};
+	};
+};

arch/arm/dts/imx8mq-evk-u-boot.dtsi

@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
 
+#include "imx8mq-u-boot.dtsi"
+
 &usdhc1 {
 	mmc-hs400-1_8v;
 };

arch/arm/dts/imx8mq-phanbell-u-boot.dtsi

@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
 
+#include "imx8mq-u-boot.dtsi"
+
 &reg_usdhc2_vmmc {
 	u-boot,off-on-delay-us = <20000>;
 };

arch/arm/dts/imx8mq-pico-pi.dts

@@ -9,6 +9,7 @@
 /dts-v1/;
 
 #include "imx8mq.dtsi"
+#include "imx8mq-u-boot.dtsi"
 
 / {
 	model = "TechNexion PICO-PI-8M";

arch/arm/dts/imx8mq-u-boot.dtsi

@@ -0,0 +1,139 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 NXP
+ */
+
+/ {
+	binman: binman {
+		multiple-images;
+	};
+
+};
+
+&binman {
+	u-boot-spl-ddr {
+		filename = "u-boot-spl-ddr.bin";
+		pad-byte = <0xff>;
+		align-size = <4>;
+		align = <4>;
+
+		u-boot-spl {
+			align-end = <4>;
+		};
+
+		blob_1: blob-ext@1 {
+			filename = "lpddr4_pmu_train_1d_imem.bin";
+			size = <0x8000>;
+		};
+
+		blob_2: blob-ext@2 {
+			filename = "lpddr4_pmu_train_1d_dmem.bin";
+			size = <0x4000>;
+		};
+
+		blob_3: blob-ext@3 {
+			filename = "lpddr4_pmu_train_2d_imem.bin";
+			size = <0x8000>;
+		};
+
+		blob_4: blob-ext@4 {
+			filename = "lpddr4_pmu_train_2d_dmem.bin";
+			size = <0x4000>;
+		};
+	};
+
+	signed_hdmi {
+		filename = "signed_hdmi.bin";
+
+		blob_5: blob-ext@5 {
+			filename = "signed_hdmi_imx8m.bin";
+		};
+	};
+
+	spl {
+		filename = "spl.bin";
+
+		mkimage {
+			args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x7e1000";
+
+			blob {
+				filename = "u-boot-spl-ddr.bin";
+			};
+
+		};
+
+	};
+
+	itb {
+		filename = "u-boot.itb";
+
+		fit {
+			description = "Configuration to load ATF before U-Boot";
+			#address-cells = <1>;
+			fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
+
+			images {
+				uboot {
+					description = "U-Boot (64-bit)";
+					type = "standalone";
+					arch = "arm64";
+					compression = "none";
+					load = <CONFIG_SYS_TEXT_BASE>;
+
+					uboot_blob: blob-ext {
+						filename = "u-boot-nodtb.bin";
+					};
+				};
+
+				atf {
+					description = "ARM Trusted Firmware";
+					type = "firmware";
+					arch = "arm64";
+					compression = "none";
+					load = <0x910000>;
+					entry = <0x910000>;
+
+					atf_blob: blob-ext {
+						filename = "bl31.bin";
+					};
+				};
+
+				fdt {
+					description = "NAME";
+					type = "flat_dt";
+					compression = "none";
+
+					uboot_fdt_blob: blob-ext {
+						filename = "u-boot.dtb";
+					};
+				};
+			};
+
+			configurations {
+				default = "conf";
+
+				conf {
+					description = "NAME";
+					firmware = "uboot";
+					loadables = "atf";
+					fdt = "fdt";
+				};
+			};
+		};
+	};
+
+	imx-boot {
+		filename = "flash.bin";
+		pad-byte = <0x00>;
+
+		spl: blob-ext@1 {
+			offset = <0x0>;
+			filename = "spl.bin";
+		};
+
+		uboot: blob-ext@2 {
+			offset = <0x57c00>;
+			filename = "u-boot.itb";
+		};
+	};
+};

arch/arm/dts/phycore-imx8mm-u-boot.dtsi

@@ -7,10 +7,6 @@
 #include "imx8mm-u-boot.dtsi"
 
 / {
-	binman: binman {
-		multiple-images;
-	};
-
 	wdt-reboot {
 		compatible = "wdt-reboot";
 		wdt = <&wdog1>;
@@ -73,121 +69,3 @@
 &wdog1 {
 	u-boot,dm-spl;
 };
-
-&binman {
-	u-boot-spl-ddr {
-		filename = "u-boot-spl-ddr.bin";
-		pad-byte = <0xff>;
-		align-size = <4>;
-		align = <4>;
-
-		u-boot-spl {
-			align-end = <4>;
-		};
-
-		blob_1: blob-ext@1 {
-			filename = "lpddr4_pmu_train_1d_imem.bin";
-			size = <0x8000>;
-		};
-
-		blob_2: blob-ext@2 {
-			filename = "lpddr4_pmu_train_1d_dmem.bin";
-			size = <0x4000>;
-		};
-
-		blob_3: blob-ext@3 {
-			filename = "lpddr4_pmu_train_2d_imem.bin";
-			size = <0x8000>;
-		};
-
-		blob_4: blob-ext@4 {
-			filename = "lpddr4_pmu_train_2d_dmem.bin";
-			size = <0x4000>;
-		};
-	};
-
-	spl {
-		filename = "spl.bin";
-
-		mkimage {
-			args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x7e1000";
-
-			blob {
-				filename = "u-boot-spl-ddr.bin";
-			};
-		};
-	};
-
-	itb {
-		filename = "u-boot.itb";
-
-		fit {
-			description = "Configuration to load ATF before U-Boot";
-			#address-cells = <1>;
-			fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
-
-			images {
-				uboot {
-					description = "U-Boot (64-bit)";
-					type = "standalone";
-					arch = "arm64";
-					compression = "none";
-					load = <CONFIG_SYS_TEXT_BASE>;
-
-					uboot_blob: blob-ext {
-						filename = "u-boot-nodtb.bin";
-					};
-				};
-
-				atf {
-					description = "ARM Trusted Firmware";
-					type = "firmware";
-					arch = "arm64";
-					compression = "none";
-					load = <0x920000>;
-					entry = <0x920000>;
-
-					atf_blob: blob-ext {
-						filename = "bl31.bin";
-					};
-				};
-
-				fdt {
-					description = "NAME";
-					type = "flat_dt";
-					compression = "none";
-
-					uboot_fdt_blob: blob-ext {
-						filename = "u-boot.dtb";
-					};
-				};
-			};
-
-			configurations {
-				default = "conf";
-
-				conf {
-					description = "NAME";
-					firmware = "uboot";
-					loadables = "atf";
-					fdt = "fdt";
-				};
-			};
-		};
-	};
-
-	imx-boot {
-		filename = "flash.bin";
-		pad-byte = <0x00>;
-
-		spl: blob-ext@1 {
-			filename = "spl.bin";
-			offset = <0x0>;
-		};
-
-		uboot: blob-ext@2 {
-			filename = "u-boot.itb";
-			offset = <0x57c00>;
-		};
-	};
-};

arch/arm/dts/px30-engicam-common.dtsi

@@ -6,6 +6,11 @@
  */
 
 / {
+	aliases {
+		mmc1 = &sdmmc;
+		mmc2 = &sdio;
+	};
+
 	vcc5v0_sys: vcc5v0-sys {
 		compatible = "regulator-fixed";
 		regulator-name = "vcc5v0_sys";	/* +5V */
@@ -14,6 +19,63 @@
 		regulator-min-microvolt = <5000000>;
 		regulator-max-microvolt = <5000000>;
 	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&xin32k>;
+		clock-names = "ext_clock";
+		post-power-on-delay-ms = <80>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_enable_h>;
+	};
+
+	vcc3v3_btreg: vcc3v3-btreg {
+		compatible = "regulator-gpio";
+		enable-active-high;
+		pinctrl-names = "default";
+		pinctrl-0 = <&bt_enable_h>;
+		regulator-name = "btreg-gpio-supply";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+		states = <3300000 0x0>;
+	};
+
+	vcc3v3_rf_aux_mod: vcc3v3-rf-aux-mod {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_rf_aux_mod";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	xin32k: xin32k {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+		clock-output-names = "xin32k";
+	};
+};
+
+&sdio {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	bus-width = <4>;
+	clock-frequency = <50000000>;
+	cap-sdio-irq;
+	cap-sd-highspeed;
+	keep-power-in-suspend;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	non-removable;
+	sd-uhs-sdr104;
+	status = "okay";
+
+	brcmf: wifi@1 {
+		compatible = "brcm,bcm4329-fmac";
+		reg = <1>;
+	};
 };
 
 &gmac {
@@ -25,6 +87,10 @@
 	status = "okay";
 };
 
+&pwm0 {
+	status = "okay";
+};
+
 &sdmmc {
 	cap-sd-highspeed;
 	card-detect-delay = <800>;
@@ -33,7 +99,31 @@
 	status = "okay";
 };
 
+&u2phy {
+	status = "okay";
+
+	u2phy_host: host-port {
+		status = "okay";
+	};
+
+	u2phy_otg: otg-port {
+		status = "okay";
+	};
+};
+
 &uart2 {
 	pinctrl-0 = <&uart2m1_xfer>;
 	status = "okay";
 };
+
+&usb20_otg {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};

arch/arm/dts/px30-engicam-ctouch2.dtsi

@@ -6,3 +6,25 @@
  */
 
 #include "px30-engicam-common.dtsi"
+
+&pinctrl {
+	bt {
+		bt_enable_h: bt-enable-h {
+			rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	sdio-pwrseq {
+		wifi_enable_h: wifi-enable-h {
+			rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&sdio_pwrseq {
+	reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+};
+
+&vcc3v3_btreg {
+	enable-gpio = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>;
+};

arch/arm/dts/px30-engicam-edimm2.2.dtsi

@@ -5,3 +5,62 @@
  */
 
 #include "px30-engicam-common.dtsi"
+
+/ {
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		pwms = <&pwm0 0 25000 0>;
+	};
+
+	panel {
+		compatible = "yes-optoelectronics,ytc700tlag-05-201c";
+		backlight = <&backlight>;
+		data-mapping = "vesa-24";
+		power-supply = <&vcc3v3_lcd>;
+
+		port {
+			panel_in_lvds: endpoint {
+				remote-endpoint = <&lvds_out_panel>;
+			};
+		};
+	};
+};
+
+&display_subsystem {
+	status = "okay";
+};
+
+&dsi_dphy {
+	status = "okay";
+};
+
+/* LVDS_B(secondary) */
+&lvds {
+	status = "okay";
+
+	ports {
+		port@1 {
+			reg = <1>;
+
+			lvds_out_panel: endpoint {
+				remote-endpoint = <&panel_in_lvds>;
+			};
+		};
+	};
+};
+
+&vopb {
+	status = "okay";
+};
+
+&vopb_mmu {
+	status = "okay";
+};
+
+&vopl {
+	status = "okay";
+};
+
+&vopl_mmu {
+	status = "okay";
+};

arch/arm/dts/px30-engicam-px30-core-ctouch2-of10.dts

@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2020 Amarula Solutions(India)
+ */
+
+/dts-v1/;
+#include "px30.dtsi"
+#include "px30-engicam-ctouch2.dtsi"
+#include "px30-engicam-px30-core.dtsi"
+
+/ {
+	model = "Engicam PX30.Core C.TOUCH 2.0 10.1\" Open Frame";
+	compatible = "engicam,px30-core-ctouch2-of10", "engicam,px30-core",
+		     "rockchip,px30";
+
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		pwms = <&pwm0 0 25000 0>;
+	};
+
+	chosen {
+		stdout-path = "serial2:115200n8";
+	};
+
+	panel {
+		compatible = "ampire,am-1280800n3tzqw-t00h";
+		backlight = <&backlight>;
+		power-supply = <&vcc3v3_lcd>;
+		data-mapping = "vesa-24";
+
+		port {
+			panel_in_lvds: endpoint {
+				remote-endpoint = <&lvds_out_panel>;
+			};
+		};
+	};
+};
+
+&display_subsystem {
+	status = "okay";
+};
+
+&dsi_dphy {
+	status = "okay";
+};
+
+&lvds {
+	status = "okay";
+
+	ports {
+		port@1 {
+			reg = <1>;
+
+			lvds_out_panel: endpoint {
+				remote-endpoint = <&panel_in_lvds>;
+			};
+		};
+	};
+};
+
+&vopb {
+	status = "okay";
+};
+
+&vopb_mmu {
+	status = "okay";
+};
+
+&vopl {
+	status = "okay";
+};
+
+&vopl_mmu {
+	status = "okay";
+};

arch/arm/dts/px30-engicam-px30-core-ctouch2.dts

@@ -9,11 +9,11 @@
 /dts-v1/;
 #include "px30.dtsi"
 #include "px30-engicam-ctouch2.dtsi"
-#include "px30-px30-core.dtsi"
+#include "px30-engicam-px30-core.dtsi"
 
 / {
 	model = "Engicam PX30.Core C.TOUCH 2.0";
-	compatible = "engicam,px30-core-ctouch2", "engicam,px30-px30-core",
+	compatible = "engicam,px30-core-ctouch2", "engicam,px30-core",
 		     "rockchip,px30";
 
 	chosen {

arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts

@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2020 Amarula Solutions(India)
+ */
+
+/dts-v1/;
+#include "px30.dtsi"
+#include "px30-engicam-edimm2.2.dtsi"
+#include "px30-engicam-px30-core.dtsi"
+
+/ {
+	model = "Engicam PX30.Core EDIMM2.2 Starter Kit";
+	compatible = "engicam,px30-core-edimm2.2", "engicam,px30-core",
+		     "rockchip,px30";
+
+	chosen {
+		stdout-path = "serial2:115200n8";
+	};
+};
+
+&pinctrl {
+	bt {
+		bt_enable_h: bt-enable-h {
+			rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	sdio-pwrseq {
+		wifi_enable_h: wifi-enable-h {
+			rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&sdio_pwrseq {
+	reset-gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_LOW>;
+};
+
+&vcc3v3_btreg {
+	enable-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>;
+};

arch/arm/dts/px30-engicam-px30-core.dtsi

@@ -10,7 +10,11 @@
 #include <dt-bindings/pinctrl/rockchip.h>
 
 / {
-	compatible = "engicam,px30-px30-core", "rockchip,px30";
+	compatible = "engicam,px30-core", "rockchip,px30";
+
+	aliases {
+		mmc0 = &emmc;
+	};
 };
 
 &cpu0 {
@@ -192,6 +196,11 @@
 				};
 			};
 
+			vcc3v3_lcd: SWITCH_REG1 {
+				regulator-boot-on;
+				regulator-name = "vcc3v3_lcd";
+			};
+
 			vcc5v0_host: SWITCH_REG2 {
 				regulator-name = "vcc5v0_host";
 				regulator-always-on;

arch/arm/dts/px30-evb.dts

@@ -13,8 +13,14 @@
 	model = "Rockchip PX30 EVB";
 	compatible = "rockchip,px30-evb", "rockchip,px30";
 
+	aliases {
+		mmc0 = &sdmmc;
+		mmc1 = &sdio;
+		mmc2 = &emmc;
+	};
+
 	chosen {
-		stdout-path = "serial2:115200n8";
+		stdout-path = "serial5:115200n8";
 	};
 
 	adc-keys {
@@ -108,6 +114,10 @@
 	cpu-supply = <&vdd_arm>;
 };
 
+&csi_dphy {
+	status = "okay";
+};
+
 &display_subsystem {
 	status = "okay";
 };
@@ -126,22 +136,15 @@
 	};
 
 	panel@0 {
-		compatible = "sitronix,st7703";
+		compatible = "xinpeng,xpp055c272";
 		reg = <0>;
 		backlight = <&backlight>;
 		iovcc-supply = <&vcc_1v8>;
 		vci-supply = <&vcc3v3_lcd>;
 
-		ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			port@0 {
-				reg = <0>;
-
-				mipi_in_panel: endpoint {
-					remote-endpoint = <&mipi_out_panel>;
-				};
+		port {
+			mipi_in_panel: endpoint {
+				remote-endpoint = <&mipi_out_panel>;
 			};
 		};
 	};
@@ -152,7 +155,6 @@
 };
 
 &emmc {
-	bus-width = <8>;
 	cap-mmc-highspeed;
 	mmc-hs200-1_8v;
 	non-removable;
@@ -171,6 +173,11 @@
 	status = "okay";
 };
 
+&gpu {
+	mali-supply = <&vdd_log>;
+	status = "okay";
+};
+
 &i2c0 {
 	status = "okay";
 
@@ -388,6 +395,73 @@
 	};
 };
 
+&i2c1 {
+	status = "okay";
+
+	sensor@d {
+		compatible = "asahi-kasei,ak8963";
+		reg = <0x0d>;
+		gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
+		vdd-supply = <&vcc3v0_pmu>;
+		mount-matrix = "1", /* x0 */
+			       "0", /* y0 */
+			       "0", /* z0 */
+			       "0", /* x1 */
+			       "1", /* y1 */
+			       "0", /* z1 */
+			       "0", /* x2 */
+			       "0", /* y2 */
+			       "1"; /* z2 */
+	};
+
+	touchscreen@14 {
+		compatible = "goodix,gt1151";
+		reg = <0x14>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA5 IRQ_TYPE_LEVEL_LOW>;
+		irq-gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+		reset-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
+		VDDIO-supply = <&vcc3v3_lcd>;
+	};
+
+	sensor@4c {
+		compatible = "fsl,mma7660";
+		reg = <0x4c>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PB7 IRQ_TYPE_LEVEL_LOW>;
+	};
+};
+
+&i2c2 {
+	status = "okay";
+
+	clock-frequency = <100000>;
+
+	/* These are relatively safe rise/fall times; TODO: measure */
+	i2c-scl-falling-time-ns = <50>;
+	i2c-scl-rising-time-ns = <300>;
+
+	ov5695: ov5695@36 {
+		compatible = "ovti,ov5695";
+		reg = <0x36>;
+		avdd-supply = <&vcc2v8_dvp>;
+		clocks = <&cru SCLK_CIF_OUT>;
+		clock-names = "xvclk";
+		dvdd-supply = <&vcc1v5_dvp>;
+		dovdd-supply = <&vcc1v8_dvp>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&cif_clkout_m0>;
+		reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
+
+		port {
+			ucam_out: endpoint {
+				remote-endpoint = <&mipi_in_ucam>;
+				data-lanes = <1 2>;
+			};
+		};
+	};
+};
+
 &i2s1_2ch {
 	status = "okay";
 };
@@ -403,6 +477,24 @@
 	vccio6-supply = <&vccio_flash>;
 };
 
+&isp {
+	status = "okay";
+
+	ports {
+		port@0 {
+			mipi_in_ucam: endpoint@0 {
+				reg = <0>;
+				data-lanes = <1 2>;
+				remote-endpoint = <&ucam_out>;
+			};
+		};
+	};
+};
+
+&isp_mmu {
+	status = "okay";
+};
+
 &pinctrl {
 	headphone {
 		hp_det: hp-det {
@@ -464,7 +556,6 @@
 };
 
 &sdmmc {
-	bus-width = <4>;
 	cap-mmc-highspeed;
 	cap-sd-highspeed;
 	card-detect-delay = <800>;
@@ -474,10 +565,10 @@
 	sd-uhs-sdr104;
 	vmmc-supply = <&vcc_sd>;
 	vqmmc-supply = <&vccio_sd>;
+	status = "okay";
 };
 
 &sdio {
-	bus-width = <4>;
 	cap-sd-highspeed;
 	keep-power-in-suspend;
 	non-removable;
@@ -486,13 +577,27 @@
 	status = "okay";
 };
 
-&uart1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart1_xfer &uart1_cts>;
+&tsadc {
+	rockchip,hw-tshut-mode = <1>;
+	rockchip,hw-tshut-polarity = <1>;
 	status = "okay";
 };
 
-&uart2 {
+&u2phy {
+	status = "okay";
+
+	u2phy_host: host-port {
+		status = "okay";
+	};
+
+	u2phy_otg: otg-port {
+		status = "okay";
+	};
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1_xfer &uart1_cts>;
 	status = "okay";
 };
 

arch/arm/dts/px30-px30-core-edimm2.2.dts

@@ -1,21 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
- * Copyright (c) 2020 Engicam srl
- * Copyright (c) 2020 Amarula Solutions(India)
- */
-
-/dts-v1/;
-#include "px30.dtsi"
-#include "px30-engicam-edimm2.2.dtsi"
-#include "px30-px30-core.dtsi"
-
-/ {
-	model = "Engicam PX30.Core EDIMM2.2 Starter Kit";
-	compatible = "engicam,px30-core-edimm2.2", "engicam,px30-px30-core",
-		     "rockchip,px30";
-
-	chosen {
-		stdout-path = "serial2:115200n8";
-	};
-};

arch/arm/dts/px30-u-boot.dtsi

@@ -13,6 +13,12 @@
 		u-boot,spl-boot-order = &emmc, &sdmmc;
 	};
 
+	dmc {
+		u-boot,dm-pre-reloc;
+		compatible = "rockchip,px30-dmc", "syscon";
+		reg = <0x0 0xff2a0000 0x0 0x1000>;
+	};
+
 	rng: rng@ff0b0000 {
 		compatible = "rockchip,cryptov2-rng";
 		reg = <0x0 0xff0b0000 0x0 0x4000>;
@@ -20,10 +26,6 @@
 	};
 };
 
-&dmc {
-	u-boot,dm-pre-reloc;
-};
-
 &uart2 {
 	clock-frequency = <24000000>;
 	u-boot,dm-pre-reloc;
@@ -62,10 +64,14 @@
 
 &cru {
 	u-boot,dm-pre-reloc;
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-rates;
 };
 
 &pmucru {
 	u-boot,dm-pre-reloc;
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-rates;
 };
 
 &saradc {

arch/arm/dts/px30.dtsi

@@ -110,7 +110,7 @@
 		};
 	};
 
-	cpu0_opp_table: cpu0-opp-table {
+	cpu0_opp_table: opp-table-0 {
 		compatible = "operating-points-v2";
 		opp-shared;
 
@@ -143,7 +143,7 @@
 	};
 
 	arm-pmu {
-		compatible = "arm,cortex-a53-pmu";
+		compatible = "arm,cortex-a35-pmu";
 		interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
@@ -151,11 +151,6 @@
 		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 	};
 
-	dmc: dmc {
-		compatible = "rockchip,px30-dmc", "syscon";
-		reg = <0x0 0xff2a0000 0x0 0x1000>;
-	};
-
 	display_subsystem: display-subsystem {
 		compatible = "rockchip,display-subsystem";
 		ports = <&vopb_out>, <&vopl_out>;
@@ -249,28 +244,31 @@
 			#size-cells = <0>;
 
 			/* These power domains are grouped by VD_LOGIC */
-			pd_usb@PX30_PD_USB {
+			power-domain@PX30_PD_USB {
 				reg = <PX30_PD_USB>;
 				clocks = <&cru HCLK_HOST>,
 					 <&cru HCLK_OTG>,
 					 <&cru SCLK_OTG_ADP>;
 				pm_qos = <&qos_usb_host>, <&qos_usb_otg>;
+				#power-domain-cells = <0>;
 			};
-			pd_sdcard@PX30_PD_SDCARD {
+			power-domain@PX30_PD_SDCARD {
 				reg = <PX30_PD_SDCARD>;
 				clocks = <&cru HCLK_SDMMC>,
 					 <&cru SCLK_SDMMC>;
 				pm_qos = <&qos_sdmmc>;
+				#power-domain-cells = <0>;
 			};
-			pd_gmac@PX30_PD_GMAC {
+			power-domain@PX30_PD_GMAC {
 				reg = <PX30_PD_GMAC>;
 				clocks = <&cru ACLK_GMAC>,
 					 <&cru PCLK_GMAC>,
 					 <&cru SCLK_MAC_REF>,
 					 <&cru SCLK_GMAC_RX_TX>;
 				pm_qos = <&qos_gmac>;
+				#power-domain-cells = <0>;
 			};
-			pd_mmc_nand@PX30_PD_MMC_NAND {
+			power-domain@PX30_PD_MMC_NAND {
 				reg = <PX30_PD_MMC_NAND>;
 				clocks =  <&cru HCLK_NANDC>,
 					  <&cru HCLK_EMMC>,
@@ -282,15 +280,17 @@
 					  <&cru SCLK_SFC>;
 				pm_qos = <&qos_emmc>, <&qos_nand>,
 					 <&qos_sdio>, <&qos_sfc>;
+				#power-domain-cells = <0>;
 			};
-			pd_vpu@PX30_PD_VPU {
+			power-domain@PX30_PD_VPU {
 				reg = <PX30_PD_VPU>;
 				clocks = <&cru ACLK_VPU>,
 					 <&cru HCLK_VPU>,
 					 <&cru SCLK_CORE_VPU>;
 				pm_qos = <&qos_vpu>, <&qos_vpu_r128>;
+				#power-domain-cells = <0>;
 			};
-			pd_vo@PX30_PD_VO {
+			power-domain@PX30_PD_VO {
 				reg = <PX30_PD_VO>;
 				clocks = <&cru ACLK_RGA>,
 					 <&cru ACLK_VOPB>,
@@ -305,8 +305,9 @@
 					 <&cru SCLK_VOPB_PWM>;
 				pm_qos = <&qos_rga_rd>, <&qos_rga_wr>,
 					 <&qos_vop_m0>, <&qos_vop_m1>;
+				#power-domain-cells = <0>;
 			};
-			pd_vi@PX30_PD_VI {
+			power-domain@PX30_PD_VI {
 				reg = <PX30_PD_VI>;
 				clocks = <&cru ACLK_CIF>,
 					 <&cru ACLK_ISP>,
@@ -316,11 +317,13 @@
 				pm_qos = <&qos_isp_128>, <&qos_isp_rd>,
 					 <&qos_isp_wr>, <&qos_isp_m1>,
 					 <&qos_vip>;
+				#power-domain-cells = <0>;
 			};
-			pd_gpu@PX30_PD_GPU {
+			power-domain@PX30_PD_GPU {
 				reg = <PX30_PD_GPU>;
 				clocks = <&cru SCLK_GPU>;
 				pm_qos = <&qos_gpu>;
+				#power-domain-cells = <0>;
 			};
 		};
 	};
@@ -605,7 +608,7 @@
 	};
 
 	wdt: watchdog@ff1e0000 {
-		compatible = "snps,dw-wdt";
+		compatible = "rockchip,px30-wdt", "snps,dw-wdt";
 		reg = <0x0 0xff1e0000 0x0 0x100>;
 		clocks = <&cru PCLK_WDT_NS>;
 		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
@@ -708,21 +711,15 @@
 		clock-names = "pclk", "timer";
 	};
 
-	amba {
-		compatible = "simple-bus";
-		#address-cells = <2>;
-		#size-cells = <2>;
-		ranges;
-
-		dmac: dmac@ff240000 {
-			compatible = "arm,pl330", "arm,primecell";
-			reg = <0x0 0xff240000 0x0 0x4000>;
-			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cru ACLK_DMAC>;
-			clock-names = "apb_pclk";
-			#dma-cells = <1>;
-		};
+	dmac: dmac@ff240000 {
+		compatible = "arm,pl330", "arm,primecell";
+		reg = <0x0 0xff240000 0x0 0x4000>;
+		interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+		arm,pl330-periph-burst;
+		clocks = <&cru ACLK_DMAC>;
+		clock-names = "apb_pclk";
+		#dma-cells = <1>;
 	};
 
 	tsadc: tsadc@ff280000 {
@@ -738,9 +735,9 @@
 		rockchip,grf = <&grf>;
 		rockchip,hw-tshut-temp = <120000>;
 		pinctrl-names = "init", "default", "sleep";
-		pinctrl-0 = <&tsadc_otp_gpio>;
+		pinctrl-0 = <&tsadc_otp_pin>;
 		pinctrl-1 = <&tsadc_otp_out>;
-		pinctrl-2 = <&tsadc_otp_gpio>;
+		pinctrl-2 = <&tsadc_otp_pin>;
 		#thermal-sensor-cells = <1>;
 		status = "disabled";
 	};
@@ -789,6 +786,16 @@
 		rockchip,grf = <&grf>;
 		#clock-cells = <1>;
 		#reset-cells = <1>;
+
+		assigned-clocks = <&cru PLL_NPLL>,
+			<&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
+			<&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
+			<&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>;
+
+		assigned-clock-rates = <1188000000>,
+			<200000000>, <200000000>,
+			<150000000>, <150000000>,
+			<100000000>, <200000000>;
 	};
 
 	pmucru: clock-controller@ff2bc000 {
@@ -799,6 +806,13 @@
 		rockchip,grf = <&grf>;
 		#clock-cells = <1>;
 		#reset-cells = <1>;
+
+		assigned-clocks =
+			<&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>,
+			<&pmucru SCLK_WIFI_PMU>;
+		assigned-clock-rates =
+			<1200000000>, <100000000>,
+			<26000000>;
 	};
 
 	usb2phy_grf: syscon@ff2c0000 {
@@ -808,7 +822,7 @@
 		#address-cells = <1>;
 		#size-cells = <1>;
 
-		u2phy: usb2-phy@100 {
+		u2phy: usb2phy@100 {
 			compatible = "rockchip,px30-usb2phy";
 			reg = <0x100 0x20>;
 			clocks = <&pmucru SCLK_USBPHY_REF>;
@@ -850,6 +864,19 @@
 		status = "disabled";
 	};
 
+	csi_dphy: phy@ff2f0000 {
+		compatible = "rockchip,px30-csi-dphy";
+		reg = <0x0 0xff2f0000 0x0 0x4000>;
+		clocks = <&cru PCLK_MIPICSIPHY>;
+		clock-names = "pclk";
+		#phy-cells = <0>;
+		power-domains = <&power PX30_PD_VI>;
+		resets = <&cru SRST_MIPICSIPHY_P>;
+		reset-names = "apb";
+		rockchip,grf = <&grf>;
+		status = "disabled";
+	};
+
 	usb20_otg: usb@ff300000 {
 		compatible = "rockchip,px30-usb", "rockchip,rk3066-usb",
 			     "snps,dwc2";
@@ -861,7 +888,6 @@
 		g-np-tx-fifo-size = <16>;
 		g-rx-fifo-size = <280>;
 		g-tx-fifo-size = <256 128 128 64 32 16>;
-		g-use-dma;
 		phys = <&u2phy_otg>;
 		phy-names = "usb2-phy";
 		power-domains = <&power PX30_PD_USB>;
@@ -873,7 +899,6 @@
 		reg = <0x0 0xff340000 0x0 0x10000>;
 		interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&cru HCLK_HOST>;
-		clock-names = "usbhost";
 		phys = <&u2phy_host>;
 		phy-names = "usb";
 		power-domains = <&power PX30_PD_USB>;
@@ -885,7 +910,6 @@
 		reg = <0x0 0xff350000 0x0 0x10000>;
 		interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&cru HCLK_HOST>;
-		clock-names = "usbhost";
 		phys = <&u2phy_host>;
 		phy-names = "usb";
 		power-domains = <&power PX30_PD_USB>;
@@ -915,13 +939,14 @@
 		status = "disabled";
 	};
 
-	sdmmc: dwmmc@ff370000 {
+	sdmmc: mmc@ff370000 {
 		compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
 		reg = <0x0 0xff370000 0x0 0x4000>;
 		interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 			 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
-		clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
+		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+		bus-width = <4>;
 		fifo-depth = <0x100>;
 		max-frequency = <150000000>;
 		pinctrl-names = "default";
@@ -930,13 +955,14 @@
 		status = "disabled";
 	};
 
-	sdio: dwmmc@ff380000 {
+	sdio: mmc@ff380000 {
 		compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
 		reg = <0x0 0xff380000 0x0 0x4000>;
 		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 			 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
-		clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
+		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+		bus-width = <4>;
 		fifo-depth = <0x100>;
 		max-frequency = <150000000>;
 		pinctrl-names = "default";
@@ -945,13 +971,14 @@
 		status = "disabled";
 	};
 
-	emmc: dwmmc@ff390000 {
+	emmc: mmc@ff390000 {
 		compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
 		reg = <0x0 0xff390000 0x0 0x4000>;
 		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 			 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
-		clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
+		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+		bus-width = <8>;
 		fifo-depth = <0x100>;
 		max-frequency = <150000000>;
 		pinctrl-names = "default";
@@ -960,18 +987,54 @@
 		status = "disabled";
 	};
 
-	sfc: sfc@ff3a0000 {
+	sfc: spi@ff3a0000 {
 		compatible = "rockchip,sfc";
 		reg = <0x0 0xff3a0000 0x0 0x4000>;
 		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
 		clock-names = "clk_sfc", "hclk_sfc";
-		pinctrl-names = "default";
 		pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
+		pinctrl-names = "default";
 		power-domains = <&power PX30_PD_MMC_NAND>;
 		status = "disabled";
 	};
 
+	nfc: nand-controller@ff3b0000 {
+		compatible = "rockchip,px30-nfc";
+		reg = <0x0 0xff3b0000 0x0 0x4000>;
+		interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
+		clock-names = "ahb", "nfc";
+		assigned-clocks = <&cru SCLK_NANDC>;
+		assigned-clock-rates = <150000000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0
+			     &flash_rdn &flash_rdy &flash_wrn &flash_dqs>;
+		power-domains = <&power PX30_PD_MMC_NAND>;
+		status = "disabled";
+	};
+
+	gpu_opp_table: opp-table-1 {
+		compatible = "operating-points-v2";
+
+		opp-200000000 {
+			opp-hz = /bits/ 64 <200000000>;
+			opp-microvolt = <950000>;
+		};
+		opp-300000000 {
+			opp-hz = /bits/ 64 <300000000>;
+			opp-microvolt = <975000>;
+		};
+		opp-400000000 {
+			opp-hz = /bits/ 64 <400000000>;
+			opp-microvolt = <1050000>;
+		};
+		opp-480000000 {
+			opp-hz = /bits/ 64 <480000000>;
+			opp-microvolt = <1125000>;
+		};
+	};
+
 	gpu: gpu@ff400000 {
 		compatible = "rockchip,px30-mali", "arm,mali-bifrost";
 		reg = <0x0 0xff400000 0x0 0x4000>;
@@ -982,9 +1045,32 @@
 		clocks = <&cru SCLK_GPU>;
 		#cooling-cells = <2>;
 		power-domains = <&power PX30_PD_GPU>;
+		operating-points-v2 = <&gpu_opp_table>;
 		status = "disabled";
 	};
 
+	vpu: video-codec@ff442000 {
+		compatible = "rockchip,px30-vpu";
+		reg = <0x0 0xff442000 0x0 0x800>;
+		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "vepu", "vdpu";
+		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+		clock-names = "aclk", "hclk";
+		iommus = <&vpu_mmu>;
+		power-domains = <&power PX30_PD_VPU>;
+	};
+
+	vpu_mmu: iommu@ff442800 {
+		compatible = "rockchip,iommu";
+		reg = <0x0 0xff442800 0x0 0x100>;
+		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+		clock-names = "aclk", "iface";
+		#iommu-cells = <0>;
+		power-domains = <&power PX30_PD_VPU>;
+	};
+
 	dsi: dsi@ff450000 {
 		compatible = "rockchip,px30-mipi-dsi";
 		reg = <0x0 0xff450000 0x0 0x10000>;
@@ -1034,7 +1120,6 @@
 		reset-names = "axi", "ahb", "dclk";
 		iommus = <&vopb_mmu>;
 		power-domains = <&power PX30_PD_VO>;
-		rockchip,grf = <&grf>;
 		status = "disabled";
 
 		vopb_out: port {
@@ -1057,7 +1142,6 @@
 		compatible = "rockchip,iommu";
 		reg = <0x0 0xff460f00 0x0 0x100>;
 		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "vopb_mmu";
 		clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>;
 		clock-names = "aclk", "iface";
 		power-domains = <&power PX30_PD_VO>;
@@ -1076,7 +1160,6 @@
 		reset-names = "axi", "ahb", "dclk";
 		iommus = <&vopl_mmu>;
 		power-domains = <&power PX30_PD_VO>;
-		rockchip,grf = <&grf>;
 		status = "disabled";
 
 		vopl_out: port {
@@ -1098,8 +1181,7 @@
 	vopl_mmu: iommu@ff470f00 {
 		compatible = "rockchip,iommu";
 		reg = <0x0 0xff470f00 0x0 0x100>;
-		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "vopl_mmu";
+		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>;
 		clock-names = "aclk", "iface";
 		power-domains = <&power PX30_PD_VO>;
@@ -1107,103 +1189,144 @@
 		status = "disabled";
 	};
 
+	isp: isp@ff4a0000 {
+		compatible = "rockchip,px30-cif-isp"; /*rk3326-rkisp1*/
+		reg = <0x0 0xff4a0000 0x0 0x8000>;
+		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "isp", "mi", "mipi";
+		clocks = <&cru SCLK_ISP>,
+			 <&cru ACLK_ISP>,
+			 <&cru HCLK_ISP>,
+			 <&cru PCLK_ISP>;
+		clock-names = "isp", "aclk", "hclk", "pclk";
+		iommus = <&isp_mmu>;
+		phys = <&csi_dphy>;
+		phy-names = "dphy";
+		power-domains = <&power PX30_PD_VI>;
+		status = "disabled";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+		};
+	};
+
+	isp_mmu: iommu@ff4a8000 {
+		compatible = "rockchip,iommu";
+		reg = <0x0 0xff4a8000 0x0 0x100>;
+		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
+		clock-names = "aclk", "iface";
+		power-domains = <&power PX30_PD_VI>;
+		rockchip,disable-mmu-reset;
+		#iommu-cells = <0>;
+	};
+
 	qos_gmac: qos@ff518000 {
-		compatible = "syscon";
+		compatible = "rockchip,px30-qos", "syscon";
 		reg = <0x0 0xff518000 0x0 0x20>;
 	};
 
 	qos_gpu: qos@ff520000 {
-		compatible = "syscon";
+		compatible = "rockchip,px30-qos", "syscon";
 		reg = <0x0 0xff520000 0x0 0x20>;
 	};
 
 	qos_sdmmc: qos@ff52c000 {
-		compatible = "syscon";
+		compatible = "rockchip,px30-qos", "syscon";
 		reg = <0x0 0xff52c000 0x0 0x20>;
 	};
 
 	qos_emmc: qos@ff538000 {
-		compatible = "syscon";
+		compatible = "rockchip,px30-qos", "syscon";
 		reg = <0x0 0xff538000 0x0 0x20>;
 	};
 
 	qos_nand: qos@ff538080 {
-		compatible = "syscon";
+		compatible = "rockchip,px30-qos", "syscon";
 		reg = <0x0 0xff538080 0x0 0x20>;
 	};
 
 	qos_sdio: qos@ff538100 {
-		compatible = "syscon";
+		compatible = "rockchip,px30-qos", "syscon";
 		reg = <0x0 0xff538100 0x0 0x20>;
 	};
 
 	qos_sfc: qos@ff538180 {
-		compatible = "syscon";
+		compatible = "rockchip,px30-qos", "syscon";
 		reg = <0x0 0xff538180 0x0 0x20>;
 	};
 
 	qos_usb_host: qos@ff540000 {
-		compatible = "syscon";
+		compatible = "rockchip,px30-qos", "syscon";
 		reg = <0x0 0xff540000 0x0 0x20>;
 	};
 
 	qos_usb_otg: qos@ff540080 {
-		compatible = "syscon";
+		compatible = "rockchip,px30-qos", "syscon";
 		reg = <0x0 0xff540080 0x0 0x20>;
 	};
 
 	qos_isp_128: qos@ff548000 {
-		compatible = "syscon";
+		compatible = "rockchip,px30-qos", "syscon";
 		reg = <0x0 0xff548000 0x0 0x20>;
 	};
 
 	qos_isp_rd: qos@ff548080 {
-		compatible = "syscon";
+		compatible = "rockchip,px30-qos", "syscon";
 		reg = <0x0 0xff548080 0x0 0x20>;
 	};
 
 	qos_isp_wr: qos@ff548100 {
-		compatible = "syscon";
+		compatible = "rockchip,px30-qos", "syscon";
 		reg = <0x0 0xff548100 0x0 0x20>;
 	};
 
 	qos_isp_m1: qos@ff548180 {
-		compatible = "syscon";
+		compatible = "rockchip,px30-qos", "syscon";
 		reg = <0x0 0xff548180 0x0 0x20>;
 	};
 
 	qos_vip: qos@ff548200 {
-		compatible = "syscon";
+		compatible = "rockchip,px30-qos", "syscon";
 		reg = <0x0 0xff548200 0x0 0x20>;
 	};
 
 	qos_rga_rd: qos@ff550000 {
-		compatible = "syscon";
+		compatible = "rockchip,px30-qos", "syscon";
 		reg = <0x0 0xff550000 0x0 0x20>;
 	};
 
 	qos_rga_wr: qos@ff550080 {
-		compatible = "syscon";
+		compatible = "rockchip,px30-qos", "syscon";
 		reg = <0x0 0xff550080 0x0 0x20>;
 	};
 
 	qos_vop_m0: qos@ff550100 {
-		compatible = "syscon";
+		compatible = "rockchip,px30-qos", "syscon";
 		reg = <0x0 0xff550100 0x0 0x20>;
 	};
 
 	qos_vop_m1: qos@ff550180 {
-		compatible = "syscon";
+		compatible = "rockchip,px30-qos", "syscon";
 		reg = <0x0 0xff550180 0x0 0x20>;
 	};
 
 	qos_vpu: qos@ff558000 {
-		compatible = "syscon";
+		compatible = "rockchip,px30-qos", "syscon";
 		reg = <0x0 0xff558000 0x0 0x20>;
 	};
 
 	qos_vpu_r128: qos@ff558080 {
-		compatible = "syscon";
+		compatible = "rockchip,px30-qos", "syscon";
 		reg = <0x0 0xff558080 0x0 0x20>;
 	};
 
@@ -1215,7 +1338,7 @@
 		#size-cells = <2>;
 		ranges;
 
-		gpio0: gpio0@ff040000 {
+		gpio0: gpio@ff040000 {
 			compatible = "rockchip,gpio-bank";
 			reg = <0x0 0xff040000 0x0 0x100>;
 			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
@@ -1227,7 +1350,7 @@
 			#interrupt-cells = <2>;
 		};
 
-		gpio1: gpio1@ff250000 {
+		gpio1: gpio@ff250000 {
 			compatible = "rockchip,gpio-bank";
 			reg = <0x0 0xff250000 0x0 0x100>;
 			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
@@ -1239,7 +1362,7 @@
 			#interrupt-cells = <2>;
 		};
 
-		gpio2: gpio2@ff260000 {
+		gpio2: gpio@ff260000 {
 			compatible = "rockchip,gpio-bank";
 			reg = <0x0 0xff260000 0x0 0x100>;
 			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
@@ -1251,7 +1374,7 @@
 			#interrupt-cells = <2>;
 		};
 
-		gpio3: gpio3@ff270000 {
+		gpio3: gpio@ff270000 {
 			compatible = "rockchip,gpio-bank";
 			reg = <0x0 0xff270000 0x0 0x100>;
 			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
@@ -1375,7 +1498,7 @@
 		};
 
 		tsadc {
-			tsadc_otp_gpio: tsadc-otp-gpio {
+			tsadc_otp_pin: tsadc-otp-pin {
 				rockchip,pins =
 					<0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
 			};
@@ -1938,7 +2061,7 @@
 			};
 		};
 
-		serial_flash {
+		sfc {
 			sfc_bus4: sfc-bus4 {
 				rockchip,pins =
 					<1 RK_PA0 3 &pcfg_pull_none>,

arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi

@@ -16,6 +16,18 @@
 		serial2 = &uart2;
 		spi0 = &sfc;
 	};
+
+	dmc {
+		u-boot,dm-pre-reloc;
+		compatible = "rockchip,px30-dmc", "syscon";
+		reg = <0x0 0xff2a0000 0x0 0x1000>;
+	};
+
+	rng: rng@ff0b0000 {
+		compatible = "rockchip,cryptov2-rng";
+		reg = <0x0 0xff0b0000 0x0 0x4000>;
+		status = "okay";
+	};
 };
 
 /* U-Boot clk driver for px30 cannot set GPU_CLK */
@@ -32,10 +44,6 @@
 		<100000000>, <17000000>;
 };
 
-&dmc {
-	u-boot,dm-pre-reloc;
-};
-
 &gpio0 {
 	u-boot,dm-pre-reloc;
 };
@@ -80,7 +88,7 @@
 	u-boot,dm-pre-reloc;
 };
 
-&{/sfc@ff3a0000/flash@0} {
+&{/spi@ff3a0000/flash@0} {
 	u-boot,dm-pre-reloc;
 };
 

arch/arm/dts/rk3326-odroid-go2.dts

@@ -14,14 +14,12 @@
 	model = "ODROID-GO Advance";
 	compatible = "hardkernel,rk3326-odroid-go2", "rockchip,rk3326";
 
-	chosen {
-		stdout-path = "serial2:115200n8";
+	aliases {
+		mmc0 = &sdmmc;
 	};
 
-	backlight: backlight {
-		compatible = "pwm-backlight";
-		power-supply = <&vcc_bl>;
-		pwms = <&pwm1 0 25000 0>;
+	chosen {
+		stdout-path = "serial2:115200n8";
 	};
 
 	adc-joystick {
@@ -33,21 +31,27 @@
 
 		axis@0 {
 			reg = <0>;
-			abs-range = <172 772>;
-			abs-fuzz = <10>;
 			abs-flat = <10>;
+			abs-fuzz = <10>;
+			abs-range = <172 772>;
 			linux,code = <ABS_X>;
 		};
 
 		axis@1 {
 			reg = <1>;
-			abs-range = <278 815>;
-			abs-fuzz = <10>;
 			abs-flat = <10>;
+			abs-fuzz = <10>;
+			abs-range = <278 815>;
 			linux,code = <ABS_Y>;
 		};
 	};
 
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		power-supply = <&vcc_bl>;
+		pwms = <&pwm1 0 25000 0>;
+	};
+
 	gpio-keys {
 		compatible = "gpio-keys";
 		pinctrl-names = "default";
@@ -163,26 +167,27 @@
 
 	rk817-sound {
 		compatible = "simple-audio-card";
+		simple-audio-card,name = "Analog";
 		simple-audio-card,format = "i2s";
-		simple-audio-card,name = "rockchip,rk817-codec";
+		simple-audio-card,hp-det-gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
 		simple-audio-card,mclk-fs = <256>;
 		simple-audio-card,widgets =
 			"Microphone", "Mic Jack",
-			"Headphone", "Headphone Jack";
+			"Headphone", "Headphones",
+			"Speaker", "Speaker";
 		simple-audio-card,routing =
-			"MIC_IN", "Mic Jack",
-			"Headphone Jack", "HPOL",
-			"Headphone Jack", "HPOR";
-		simple-audio-card,hp-det-gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>;
-		simple-audio-card,codec-hp-det = <1>;
+			"MICL", "Mic Jack",
+			"Headphones", "HPOL",
+			"Headphones", "HPOR",
+			"Speaker", "SPKO";
+
+		simple-audio-card,codec {
+			sound-dai = <&rk817>;
+		};
 
 		simple-audio-card,cpu {
 			sound-dai = <&i2s1_2ch>;
 		};
-
-		simple-audio-card,codec {
-			sound-dai = <&rk817_codec>;
-		};
 	};
 
 	vccsys: vccsys {
@@ -202,7 +207,8 @@
 		gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
 		enable-active-high;
 		regulator-always-on;
-		vin-supply = <&vccsys>;
+		regulator-boot-on;
+		vin-supply = <&usb_midu>;
 	};
 };
 
@@ -259,6 +265,7 @@
 		backlight = <&backlight>;
 		iovcc-supply = <&vcc_lcd>;
 		reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
+		rotation = <270>;
 		vdd-supply = <&vcc_lcd>;
 
 		port {
@@ -289,16 +296,14 @@
 		reg = <0x20>;
 		interrupt-parent = <&gpio0>;
 		interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
-		pinctrl-names = "default", "pmic-sleep",
-				"pmic-power-off", "pmic-reset";
-		pinctrl-0 = <&pmic_int>;
-		pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
-		pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
-		pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>;
-		rockchip,system-power-controller;
+		clock-output-names = "rk808-clkout1", "xin32k";
+		clock-names = "mclk";
+		clocks = <&cru SCLK_I2S1_OUT>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int>, <&i2s1_2ch_mclk>;
 		wakeup-source;
 		#clock-cells = <1>;
-		clock-output-names = "rk808-clkout1", "xin32k";
+		#sound-dai-cells = <0>;
 
 		vcc1-supply = <&vccsys>;
 		vcc2-supply = <&vccsys>;
@@ -307,53 +312,7 @@
 		vcc5-supply = <&vccsys>;
 		vcc6-supply = <&vccsys>;
 		vcc7-supply = <&vccsys>;
-
-		pinctrl_rk8xx: pinctrl_rk8xx {
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			rk817_ts_gpio1: rk817_ts_gpio1 {
-				pins = "gpio_ts";
-				function = "pin_fun1";
-				/* output-low; */
-				/* input-enable; */
-			};
-
-			rk817_gt_gpio2: rk817_gt_gpio2 {
-				pins = "gpio_gt";
-				function = "pin_fun1";
-			};
-
-			rk817_pin_ts: rk817_pin_ts {
-				pins = "gpio_ts";
-				function = "pin_fun0";
-			};
-
-			rk817_pin_gt: rk817_pin_gt {
-				pins = "gpio_gt";
-				function = "pin_fun0";
-			};
-
-			rk817_slppin_null: rk817_slppin_null {
-				pins = "gpio_slp";
-				function = "pin_fun0";
-			};
-
-			rk817_slppin_slp: rk817_slppin_slp {
-				pins = "gpio_slp";
-				function = "pin_fun1";
-			};
-
-			rk817_slppin_pwrdn: rk817_slppin_pwrdn {
-				pins = "gpio_slp";
-				function = "pin_fun2";
-			};
-
-			rk817_slppin_rst: rk817_slppin_rst {
-				pins = "gpio_slp";
-				function = "pin_fun3";
-			};
-		};
+		vcc8-supply = <&vccsys>;
 
 		regulators {
 			vdd_logic: DCDC_REG1 {
@@ -503,66 +462,18 @@
 					regulator-suspend-microvolt = <3000000>;
 				};
 			};
-		};
 
-		battery {
-			compatible = "rk817,battery";
-			ocv_table = <3500 3625 3685 3697 3718 3735 3748
-			3760 3774 3788 3802 3816 3834 3853
-			3877 3908 3946 3975 4018 4071 4106>;
-
-			/* KPL605475 Battery Spec */
-			/*
-				Capacity : 3.7V 3000mA
-				Normal Voltage = 3.7V
-				Cut-Off Voltage : 3.1V
-				Internal Impedance : 180 mOhm
-				Charging Voltage : 4.2V
-				Charging Voltage Max : 4.25V
-				Sample resister : 10 mohm
-			*/
-			design_capacity = <3000>;
-			design_qmax = <3000>;
-			bat_res = <180>;
-			sleep_enter_current = <300>;
-			sleep_exit_current = <300>;
-			sleep_filter_current = <100>;
-			power_off_thresd = <3500>;
-			zero_algorithm_vol = <3700>;
-			max_soc_offset = <60>;
-			monitor_sec = <5>;
-			virtual_power = <0>;
-			sample_res = <10>;
-		};
-
-		charger {
-			compatible = "rk817,charger";
-			min_input_voltage = <4500>;
-			max_input_current = <1500>;
-			max_chrg_current = <2000>;
-			max_chrg_voltage = <4200>;
-			chrg_term_mode = <0>;
-			chrg_finish_cur = <300>;
-			virtual_power = <0>;
-			sample_res = <10>;
-
-			/* P.C.B rev0.2 DC Detect & Charger Status LED GPIO */
-			dc_det_gpio  = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
-			chg_led_gpio = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
-
-			extcon = <&u2phy>;
+			usb_midu: BOOST {
+				regulator-name = "usb_midu";
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5400000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
 		};
 
 		rk817_codec: codec {
-			#sound-dai-cells = <0>;
-			compatible = "rockchip,rk817-codec";
-			clocks = <&cru SCLK_I2S1_OUT>;
-			clock-names = "mclk";
-			pinctrl-names = "default";
-			pinctrl-0 = <&i2s1_2ch_mclk>;
-			hp-volume = <20>;
-			spk-volume = <3>;
-			status = "okay";
+			rockchip,mic-in-differential;
 		};
 	};
 };
@@ -604,7 +515,6 @@
 };
 
 &sdmmc {
-	bus-width = <4>;
 	cap-sd-highspeed;
 	card-detect-delay = <200>;
 	cd-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_LOW>; /*[> CD GPIO <]*/

arch/arm/dts/rk3399-u-boot.dtsi

@@ -88,6 +88,10 @@
 	u-boot,dm-pre-reloc;
 };
 
+&emmc_phy {
+	u-boot,dm-pre-reloc;
+};
+
 &grf {
 	u-boot,dm-pre-reloc;
 };

arch/arm/dts/rk3568-u-boot.dtsi

@@ -9,6 +9,10 @@
 		mmc1 = &sdmmc0;
 	};
 
+	chosen {
+		u-boot,spl-boot-order = &sdhci, &sdmmc0;
+	};
+
 	dmc: dmc {
 		compatible = "rockchip,rk3568-dmc";
 		u-boot,dm-pre-reloc;
@@ -35,3 +39,16 @@
 	u-boot,dm-pre-reloc;
 	status = "okay";
 };
+
+&sdmmc0 {
+	u-boot,dm-spl;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	u-boot,dm-spl;
+	mmc-hs200-1_8v;
+	status = "okay";
+};
+

arch/arm/mach-imx/imx8m/Kconfig

@@ -36,13 +36,15 @@ config TARGET_IMX8MQ_CM
 
 config TARGET_IMX8MQ_EVK
 	bool "imx8mq_evk"
+	select BINMAN
 	select IMX8MQ
 	select IMX8M_LPDDR4
 
 config TARGET_IMX8MQ_PHANBELL
-        bool "imx8mq_phanbell"
-        select IMX8MQ
-        select IMX8M_LPDDR4
+	bool "imx8mq_phanbell"
+	select BINMAN
+	select IMX8MQ
+	select IMX8M_LPDDR4
 
 config TARGET_IMX8MM_EVK
 	bool "imx8mm LPDDR4 EVK board"
@@ -71,6 +73,7 @@ config TARGET_IMX8MM_ICORE_MX8MM
 
 config TARGET_IMX8MM_VENICE
 	bool "Support Gateworks Venice iMX8M Mini module"
+	select BINMAN
 	select IMX8MM
 	select SUPPORT_SPL
 	select IMX8M_LPDDR4
@@ -105,6 +108,7 @@ config TARGET_IMX8MP_EVK
 
 config TARGET_PICO_IMX8MQ
 	bool "Support Technexion Pico iMX8MQ"
+	select BINMAN
 	select IMX8MQ
 	select IMX8M_LPDDR4
 
@@ -117,12 +121,14 @@ config TARGET_VERDIN_IMX8MM
 
 config TARGET_IMX8MM_BEACON
 	bool "imx8mm Beacon Embedded devkit"
+	select BINMAN
 	select IMX8MM
 	select SUPPORT_SPL
 	select IMX8M_LPDDR4
 
 config TARGET_IMX8MN_BEACON
 	bool "imx8mn Beacon Embedded devkit"
+	select BINMAN
 	select IMX8MN
 	select SUPPORT_SPL
 	select IMX8M_LPDDR4

arch/arm/mach-imx/imx8m/imximage.cfg

@@ -1,17 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright 2018 NXP
+ * Copyright 2018-2021 NXP
  */
 
 #define __ASSEMBLY__
 
 FIT
 BOOT_FROM	sd
-SIGNED_HDMI	signed_hdmi_imx8m.bin
-LOADER		spl/u-boot-spl-ddr.bin	0x7E1000
-SECOND_LOADER	u-boot.itb		0x40200000 0x60000
-
-DDR_FW lpddr4_pmu_train_1d_imem.bin
-DDR_FW lpddr4_pmu_train_1d_dmem.bin
-DDR_FW lpddr4_pmu_train_2d_imem.bin
-DDR_FW lpddr4_pmu_train_2d_dmem.bin
+SIGNED_HDMI	signed_hdmi.bin
+LOADER		u-boot-spl-ddr.bin	0x7e1000

arch/arm/mach-imx/mx6/Kconfig

@@ -588,6 +588,7 @@ config TARGET_UDOO
 	depends on MX6QDL
 	select BOARD_LATE_INIT
 	select SUPPORT_SPL
+	imply CMD_DM
 
 config TARGET_UDOO_NEO
 	bool "UDOO Neo"

arch/arm/mach-rockchip/Kconfig

@@ -261,6 +261,8 @@ config ROCKCHIP_RK3399
 config ROCKCHIP_RK3568
 	bool "Support Rockchip RK3568"
 	select ARM64
+	select SUPPORT_SPL
+	select SPL
 	select CLK
 	select PINCTRL
 	select RAM

arch/arm/mach-rockchip/boot_mode.c

@@ -95,7 +95,7 @@ int setup_boot_mode(void)
 	switch (boot_mode) {
 	case BOOT_FASTBOOT:
 		debug("%s: enter fastboot!\n", __func__);
-		env_set("preboot", "setenv preboot; fastboot usb0");
+		env_set("preboot", "setenv preboot; fastboot usb 0");
 		break;
 	case BOOT_UMS:
 		debug("%s: enter UMS!\n", __func__);

arch/arm/mach-rockchip/px30/Kconfig

@@ -27,6 +27,14 @@ config TARGET_PX30_CORE
 	  * PX30.Core needs to mount on top of CTOUCH2.0 for creating complete
 	    PX30.Core C.TOUCH Carrier board.
 
+	  PX30.Core CTOUCH2-OF10:
+	  * PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.
+	  * CTOUCH2.0 is a general purpose Carrier board with capacitive
+	    touch interface support.
+	  * 10.1" OF is a capacitive touch 10.1" Open Frame panel solutions.
+	  * PX30.Core needs to mount on top of C.TOUCH 2.0 carrier with pluged
+            10.1" OF for creating complete PX30.Core C.TOUCH 2.0 10.1" Open Frame.
+
 config ROCKCHIP_BOOT_MODE_REG
 	default 0xff010200
 

arch/arm/mach-rockchip/rk3568/rk3568.c

@@ -11,9 +11,18 @@
 #include <asm/arch-rockchip/hardware.h>
 #include <dt-bindings/clock/rk3568-cru.h>
 
-#define PMUGRF_BASE		0xfdc20000
-#define GRF_BASE		0xfdc60000
-
+#define PMUGRF_BASE			0xfdc20000
+#define GRF_BASE			0xfdc60000
+#define GRF_GPIO1B_DS_2			0x218
+#define GRF_GPIO1B_DS_3			0x21c
+#define GRF_GPIO1C_DS_0			0x220
+#define GRF_GPIO1C_DS_1			0x224
+#define GRF_GPIO1C_DS_2			0x228
+#define GRF_GPIO1C_DS_3			0x22c
+#define SGRF_BASE			0xFDD18000
+#define SGRF_SOC_CON4			0x10
+#define EMMC_HPROT_SECURE_CTRL		0x03
+#define SDMMC0_HPROT_SECURE_CTRL	0x01
 /* PMU_GRF_GPIO0D_IOMUX_L */
 enum {
 	GPIO0D1_SHIFT		= 4,
@@ -81,5 +90,17 @@ void board_debug_uart_init(void)
 
 int arch_cpu_init(void)
 {
+#ifdef CONFIG_SPL_BUILD
+	/* Set the emmc sdmmc0 to secure */
+	rk_clrreg(SGRF_BASE + SGRF_SOC_CON4, (EMMC_HPROT_SECURE_CTRL << 11
+		| SDMMC0_HPROT_SECURE_CTRL << 4));
+	/* set the emmc driver strength to level 2 */
+	writel(0x3f3f0707, GRF_BASE + GRF_GPIO1B_DS_2);
+	writel(0x3f3f0707, GRF_BASE + GRF_GPIO1B_DS_3);
+	writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_0);
+	writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_1);
+	writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_2);
+	writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_3);
+#endif
 	return 0;
 }

board/beacon/imx8mm/Kconfig

@@ -10,7 +10,7 @@ config SYS_CONFIG_NAME
 	default "imx8mm_beacon"
 
 config IMX_CONFIG
-	default "arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg"
+	default "board/beacon/imx8mm/imximage-8mm-lpddr4.cfg"
 
 source "board/freescale/common/Kconfig"
 

board/beacon/imx8mm/README

@@ -12,8 +12,8 @@ Get and Build the ARM Trusted firmware
 Note: $(srctree) is U-Boot source directory
 
 $ git clone https://source.codeaurora.org/external/imx/imx-atf
-$ git checkout imx_4.19.35_1.0.0
-$ make PLAT=imx8mm bl31 ARCH=arm CROSS_COMPILE=aarch64-linux-gnu-
+$ git checkout imx_5.4.70_2.3.0
+$ make PLAT=imx8mm bl31 CROSS_COMPILE=aarch64-linux-gnu-
 $ cp build/imx8mm/release/bl31.bin $(srctree)
 
 Get the DDR firmware
@@ -26,7 +26,7 @@ $ cp firmware-imx-8.5/firmware/ddr/synopsys/lpddr4*.bin $(srctree)
 Build U-Boot
 ============
 $ make imx8mm_beacon_defconfig
-$ make flash.bin CROSS_COMPILE=aarch64-linux-gnu- ATF_LOAD_ADDR=0x920000
+$ make flash.bin CROSS_COMPILE=aarch64-linux-gnu-
 
 Burn U-Boot to microSD Card
 ===========================

board/beacon/imx8mm/imximage-8mm-lpddr4.cfg

@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
+
+#define __ASSEMBLY__
+
+BOOT_FROM	sd
+LOADER		u-boot-spl-ddr.bin	0x7E1000

board/beacon/imx8mn/Kconfig

@@ -16,7 +16,7 @@ config IMX8MN_BEACON_2GB_LPDDR
 	bool "Enable 2GB LPDDR"
 
 config IMX_CONFIG
-	default "arch/arm/mach-imx/imx8m/imximage-8mn-lpddr4.cfg"
+	default "board/beacon/imx8mn/imximage-8mn-lpddr4.cfg"
 
 source "board/freescale/common/Kconfig"
 

board/beacon/imx8mn/imximage-8mn-lpddr4.cfg

@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
+
+#define __ASSEMBLY__
+
+ROM_VERSION	v2
+BOOT_FROM	sd
+LOADER		u-boot-spl-ddr.bin	0x912000

board/compulab/imx8mm-cl-iot-gate/imximage-8mm-lpddr4.cfg

@@ -6,4 +6,4 @@
 #define __ASSEMBLY__
 
 BOOT_FROM	sd
-LOADER		mkimage.flash.mkimage	0x7E1000
+LOADER		u-boot-spl-ddr.bin	0x7e1000

board/engicam/px30_core/MAINTAINERS

@@ -4,6 +4,12 @@ M:	Suniel Mahesh <sunil@amarulasolutions.com>
 S:	Maintained
 F:	configs/px30-core-ctouch2-px30_defconfig
 
+PX30-Core-CTOUCH2.0-OF10
+M:	Jagan Teki <jagan@amarulasolutions.com>
+M:	Suniel Mahesh <sunil@amarulasolutions.com>
+S:	Maintained
+F:	configs/px30-core-ctouch2-of10-px30_defconfig
+
 PX30-Core-EDIMM2.2
 M:	Jagan Teki <jagan@amarulasolutions.com>
 M:	Suniel Mahesh <sunil@amarulasolutions.com>

board/gateworks/venice/Kconfig

@@ -10,6 +10,5 @@ config SYS_CONFIG_NAME
 	default "imx8mm_venice"
 
 config IMX_CONFIG
-	default "arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg"
-
+	default "board/gateworks/venice/imximage-8mm-lpddr4.cfg"
 endif

board/gateworks/venice/README

@@ -25,7 +25,7 @@ $ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4*.bin .
 Build U-Boot
 ============
 $ make imx8mm_venice_defconfig
-$ make flash.bin CROSS_COMPILE=aarch64-linux-gnu- ATF_LOAD_ADDR=0x920000
+$ make CROSS_COMPILE=aarch64-linux-gnu-
 
 Update eMMC
 ===========

board/gateworks/venice/imximage-8mm-lpddr4.cfg

@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 Gateworks Corporation
+ */
+
+#define __ASSEMBLY__
+
+BOOT_FROM	sd
+LOADER		u-boot-spl-ddr.bin	0x7E1000

board/sifive/unleashed/unleashed.c

@@ -117,7 +117,7 @@ int misc_init_r(void)
 void *board_fdt_blob_setup(int *err)
 {
 	*err = 0;
-	if (IS_ENABLED(CONFIG_OF_SEPARATE)) {
+	if (IS_ENABLED(CONFIG_OF_SEPARATE) || IS_ENABLED(CONFIG_OF_BOARD)) {
 		if (gd->arch.firmware_fdt_addr)
 			return (ulong *)(uintptr_t)gd->arch.firmware_fdt_addr;
 	}

board/sifive/unmatched/unmatched.c

@@ -14,7 +14,7 @@
 void *board_fdt_blob_setup(int *err)
 {
 	*err = 0;
-	if (IS_ENABLED(CONFIG_OF_SEPARATE)) {
+	if (IS_ENABLED(CONFIG_OF_SEPARATE) || IS_ENABLED(CONFIG_OF_BOARD)) {
 		if (gd->arch.firmware_fdt_addr)
 			return (ulong *)(uintptr_t)gd->arch.firmware_fdt_addr;
 	}

board/theobroma-systems/lion_rk3368/MAINTAINERS

@@ -1,5 +1,5 @@
 LION-RK3368 (RK3368-uQ7 system-on-module)
-M:	Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
+M:	Quentin Schulz <quentin.schulz@theobroma-systems.com>
 M:	Klaus Goger <klaus.goger@theobroma-systems.com>
 S:	Maintained
 F:	board/theobroma-systems/lion_rk3368

board/theobroma-systems/puma_rk3399/MAINTAINERS

@@ -1,5 +1,5 @@
 PUMA-RK3399
-M:	Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
+M:	Quentin Schulz <quentin.schulz@theobroma-systems.com>
 M:	Klaus Goger <klaus.goger@theobroma-systems.com>
 S:	Maintained
 F:	board/theobroma-systems/puma_rk3399

board/theobroma-systems/puma_rk3399/README

@@ -26,25 +26,17 @@ RK3399-Q7 features:
 
 Here is the step-by-step to boot to U-Boot on rk3399.
 
-Get the Source and build ATF/Cortex-M0 binaries
-===============================================
+Get the Source and build ATF binary
+===================================
 
-  > git clone git://git.theobroma-systems.com/arm-trusted-firmware.git
-  > git clone git://git.theobroma-systems.com/rk3399-cortex-m0.git
+  > git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git
 
 Compile the ATF
 ===============
 
-  > cd arm-trusted-firmware
+  > cd trusted-firmware-a
   > make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 bl31
-  > cp build/rk3399/release/bl31.bin ../u-boot/bl31-rk3399.bin
-
-Compile the M0 firmware
-=======================
-
-  > cd ../rk3399-cortex-m0
-  > make CROSS_COMPILE=arm-cortex_m0-eabi-
-  > cp rk3399m0.bin ../u-boot
+  > cp build/rk3399/release/bl31/bl31.elf ../u-boot/bl31.elf
 
 Compile the U-Boot
 ==================
@@ -55,23 +47,22 @@ Compile the U-Boot
 Package the image
 =================
 
-Creating a SPL image for SD-Card/eMMC
-  > tools/mkimage -n rk3399 -T rksd -d spl/u-boot-spl.bin spl_mmc.img
-Creating a SPL image for SPI-NOR
-  > tools/mkimage -n rk3399 -T rkspi -d spl/u-boot-spl.bin spl_nor.img
-Create the FIT image containing U-Boot proper, ATF, M0 Firmware, devicetree
-  > make CROSS_COMPILE=aarch64-linux-gnu-
+The SPL image for SD-Card/eMMC is readily available in idbloader.img at the
+root of U-Boot after compilation.
+
+Creating an SPL image for SPI-NOR:
+  > tools/mkimage -n rk3399 -T rkspi -d spl/u-boot-spl.bin idbloader-spi.img
 
 Flash the image
 ===============
 
 Copy the SPL to offset 32k for SD/eMMC, offset 0 for NOR-Flash and the FIT
-image to offset 256k card.
+image to offset 256k.
 
 SD-Card
 -------
 
-  > dd if=spl_mmc.img of=/dev/sdb seek=64
+  > dd if=idbloader.img of=/dev/sdb seek=64
   > dd if=u-boot.itb of=/dev/sdb seek=512
 
 eMMC
@@ -84,24 +75,27 @@ help of the Rockchip loader binary.
   > cd rkdeveloptool
   > autoreconf -i && ./configure && make
   > git clone https://github.com/rockchip-linux/rkbin.git
-  > ./rkdeveloptool db rkbin/rk33/rk3399_loader_v1.08.106.bin
-  > ./rkdeveloptool wl 64 ../spl_mmc.img
+  > cd rkbin
+  > ./tools/boot_merger RKBOOT/RK3399MINIALL.ini
+  > cd ..
+  > ./rkdeveloptool db rkbin/rk3399_loader_v1.25.126.bin
+  > ./rkdeveloptool wl 64 ../idbloader.img
   > ./rkdeveloptool wl 512 ../u-boot.itb
 
 NOR-Flash
 ---------
 
-Writing the SPI NOR Flash requires a running U-Boot. For the sake of simplicity
-we assume you have a SD-Card with a partition containing the required files
-ready.
+rkdeveloptool allows to flash the on-board SPI via the USB OTG interface with
+help of the Rockchip loader binary.
 
-  > load mmc 1:1 ${kernel_addr_r} spl_nor.img
-  > sf probe
-  > sf erase 0 +$filesize
-  > sf write $kernel_addr_r 0 ${filesize}
-  > load mmc 1:1 ${kernel_addr_r} u-boot.itb
-  > sf erase 0x40000 +$filesize
-  > sf write $kernel_addr_r 0x40000 ${filesize}
-
-
-Reboot the system and you should see a U-Boot console on UART0 (115200n8).
+  > git clone https://github.com/rockchip-linux/rkdeveloptool
+  > cd rkdeveloptool
+  > autoreconf -i && ./configure && make
+  > git clone https://github.com/rockchip-linux/rkbin.git
+  > cd rkbin
+  > ./tools/boot_merger RKBOOT/RK3399MINIALL_SPINOR.ini
+  > cd ..
+  > ./rkdeveloptool db rkbin/rk3399_loader_spinor_v1.25.114.bin
+  > ./rkdeveloptool ef
+  > ./rkdeveloptool wl 0 ../idbloader-spi.img
+  > ./rkdeveloptool wl 512 ../u-boot.itb

board/udoo/neo/neo.c

@@ -19,6 +19,8 @@
 #include <asm/mach-imx/iomux-v3.h>
 #include <dm.h>
 #include <env.h>
+#include <mmc.h>
+#include <fsl_esdhc_imx.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/io.h>
 #include <asm/mach-imx/mxc_i2c.h>
@@ -73,6 +75,8 @@ enum {
 #define BOARD_DETECT_PAD_CFG (MUX_PAD_CTRL(BOARD_DETECT_PAD_CTRL) |	\
 	MUX_MODE_SION)
 
+#define OCRAM_START	0x8f8000
+
 int dram_init(void)
 {
 	gd->ram_size = imx_ddr_size();
@@ -214,19 +218,25 @@ static iomux_v3_cfg_t const uart1_pads[] = {
 	MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	/* CD pin */
+	MX6_PAD_SD1_DATA0__GPIO6_IO_2 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* Power */
+	MX6_PAD_SD1_CMD__GPIO6_IO_1 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
 static iomux_v3_cfg_t const phy_control_pads[] = {
 	/* 25MHz Ethernet PHY Clock */
 	MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M |
 	MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
 };
 
-static iomux_v3_cfg_t const board_recognition_pads[] = {
-	/*Connected to R184*/
-	MX6_PAD_NAND_READY_B__GPIO4_IO_13 | BOARD_DETECT_PAD_CFG,
-	/*Connected to R185*/
-	MX6_PAD_NAND_ALE__GPIO4_IO_0 | BOARD_DETECT_PAD_CFG,
-};
-
 static iomux_v3_cfg_t const wdog_b_pad = {
 	MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL),
 };
@@ -249,6 +259,7 @@ static int setup_fec(void)
 					 ARRAY_SIZE(phy_control_pads));
 
 	/* Reset PHY */
+	gpio_request(IMX_GPIO_NR(2, 1), "enet_rst");
 	gpio_direction_output(IMX_GPIO_NR(2, 1) , 0);
 	udelay(10000);
 	gpio_set_value(IMX_GPIO_NR(2, 1), 1);
@@ -280,15 +291,97 @@ int board_init(void)
 					 ARRAY_SIZE(peri_3v3_pads));
 
 	/* Active high for ncp692 */
+	gpio_request(IMX_GPIO_NR(4, 16), "ncp692");
 	gpio_direction_output(IMX_GPIO_NR(4, 16) , 1);
 
 #ifdef CONFIG_SYS_I2C_MXC
 	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 #endif
 
+	setup_fec();
+
 	return 0;
 }
 
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	return 0;
+}
+
+static struct fsl_esdhc_cfg usdhc_cfg[1] = {
+	{USDHC2_BASE_ADDR},
+};
+
+#define USDHC2_PWR_GPIO IMX_GPIO_NR(6, 1)
+#define USDHC2_CD_GPIO	IMX_GPIO_NR(6, 2)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	return !gpio_get_value(USDHC2_CD_GPIO);
+}
+
+int board_mmc_init(struct bd_info *bis)
+{
+	SETUP_IOMUX_PADS(usdhc2_pads);
+	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+	usdhc_cfg[0].max_bus_width = 4;
+	gpio_request(IMX_GPIO_NR(6, 1), "usdhc2_pwr");
+	gpio_request(IMX_GPIO_NR(6, 2), "usdhc2_cd");
+	gpio_direction_input(USDHC2_CD_GPIO);
+	gpio_direction_output(USDHC2_PWR_GPIO, 1);
+
+	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+
+static char *board_string(int type)
+{
+	switch (type) {
+	case UDOO_NEO_TYPE_BASIC:
+		return "BASIC";
+	case UDOO_NEO_TYPE_BASIC_KS:
+		return "BASICKS";
+	case UDOO_NEO_TYPE_FULL:
+		return "FULL";
+	case UDOO_NEO_TYPE_EXTENDED:
+		return "EXTENDED";
+	}
+	return "UNDEFINED";
+}
+
+/* Override the default implementation, DT model is not accurate */
+int show_board_info(void)
+{
+	int *board_type = (int *)OCRAM_START;
+
+	printf("Board: UDOO Neo %s\n", board_string(*board_type));
+	return 0;
+}
+
+int board_late_init(void)
+{
+	int *board_type = (int *)OCRAM_START;
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	env_set("board_name", board_string(*board_type));
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+
+#include <linux/libfdt.h>
+#include <asm/arch/mx6-ddr.h>
+
+static const iomux_v3_cfg_t board_recognition_pads[] = {
+	/*Connected to R184*/
+	MX6_PAD_NAND_READY_B__GPIO4_IO_13 | BOARD_DETECT_PAD_CFG,
+	/*Connected to R185*/
+	MX6_PAD_NAND_ALE__GPIO4_IO_0 | BOARD_DETECT_PAD_CFG,
+};
+
 static int get_board_value(void)
 {
 	int r184, r185;
@@ -296,6 +389,8 @@ static int get_board_value(void)
 	imx_iomux_v3_setup_multiple_pads(board_recognition_pads,
 					 ARRAY_SIZE(board_recognition_pads));
 
+	gpio_request(IMX_GPIO_NR(4, 13), "r184");
+	gpio_request(IMX_GPIO_NR(4, 0), "r185");
 	gpio_direction_input(IMX_GPIO_NR(4, 13));
 	gpio_direction_input(IMX_GPIO_NR(4, 0));
 
@@ -315,49 +410,6 @@ static int get_board_value(void)
 	return (r184 << 1) + r185;
 }
 
-int board_early_init_f(void)
-{
-	setup_iomux_uart();
-	setup_fec();
-
-	return 0;
-}
-
-static char *board_string(void)
-{
-	switch (get_board_value()) {
-	case UDOO_NEO_TYPE_BASIC:
-		return "BASIC";
-	case UDOO_NEO_TYPE_BASIC_KS:
-		return "BASICKS";
-	case UDOO_NEO_TYPE_FULL:
-		return "FULL";
-	case UDOO_NEO_TYPE_EXTENDED:
-		return "EXTENDED";
-	}
-	return "UNDEFINED";
-}
-
-int checkboard(void)
-{
-	printf("Board: UDOO Neo %s\n", board_string());
-	return 0;
-}
-
-int board_late_init(void)
-{
-#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-	env_set("board_name", board_string());
-#endif
-
-	return 0;
-}
-
-#ifdef CONFIG_SPL_BUILD
-
-#include <linux/libfdt.h>
-#include <asm/arch/mx6-ddr.h>
-
 static const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = {
 	.dram_dqm0 = 0x00000028,
 	.dram_dqm1 = 0x00000028,
@@ -453,7 +505,7 @@ static void ccgr_init(void)
 
 static void spl_dram_init(void)
 {
-	int board = get_board_value();
+	int *board_type = (int *)OCRAM_START;
 
 	struct mx6_ddr_sysinfo sysinfo = {
 		.dsize = 1, /* width of data bus: 1 = 32 bits */
@@ -470,8 +522,11 @@ static void spl_dram_init(void)
 		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
 	};
 
+	*board_type = get_board_value();
+
 	mx6sx_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs);
-	if (board == UDOO_NEO_TYPE_BASIC || board == UDOO_NEO_TYPE_BASIC_KS)
+	if (*board_type == UDOO_NEO_TYPE_BASIC ||
+	    *board_type == UDOO_NEO_TYPE_BASIC_KS)
 		mx6_dram_cfg(&sysinfo, &neo_basic_mmcd_calib,
 			     &neo_basic_mem_ddr);
 	else

board/udoo/udoo.c

@@ -90,6 +90,14 @@ int mx6_rgmii_rework(struct phy_device *phydev)
 
 static void setup_iomux_enet(void)
 {
+	gpio_request(IMX_GPIO_NR(2, 31), "eth_power");
+	gpio_request(IMX_GPIO_NR(3, 23), "eth_phy_reset");
+	gpio_request(IMX_GPIO_NR(6, 24), "strap1");
+	gpio_request(IMX_GPIO_NR(6, 25), "strap2");
+	gpio_request(IMX_GPIO_NR(6, 27), "strap3");
+	gpio_request(IMX_GPIO_NR(6, 28), "strap4");
+	gpio_request(IMX_GPIO_NR(6, 29), "strap5");
+
 	gpio_direction_output(IMX_GPIO_NR(2, 31), 1); /* Power supply on */
 
 	gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* assert PHY rst */

board/udoo/udoo_spl.c

@@ -254,4 +254,39 @@ void board_init_f(ulong dummy)
 	/* DDR initialization */
 	spl_dram_init();
 }
+
+#define USDHC3_CD_GPIO		IMX_GPIO_NR(7, 0)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |		\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+	{USDHC3_BASE_ADDR},
+};
+
+static const iomux_v3_cfg_t usdhc3_pads[] = {
+	IOMUX_PADS(PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00  | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	return !gpio_get_value(USDHC3_CD_GPIO);
+}
+
+int board_mmc_init(struct bd_info *bis)
+{
+	SETUP_IOMUX_PADS(usdhc3_pads);
+	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+	usdhc_cfg[0].max_bus_width = 4;
+	gpio_direction_input(USDHC3_CD_GPIO);
+
+	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
 #endif

cmd/Kconfig

@@ -1814,6 +1814,13 @@ config CMD_RNG
 	help
 	  Print bytes from the hardware random number generator.
 
+config CMD_KASLRSEED
+	bool "kaslrseed"
+	depends on DM_RNG
+	help
+	  Set the kaslr-seed in the chosen node with entropy provided by a
+	  hardware random number generator.
+
 config CMD_SLEEP
 	bool "sleep"
 	default y

cmd/Makefile

@@ -131,6 +131,7 @@ obj-$(CONFIG_CMD_REGINFO) += reginfo.o
 obj-$(CONFIG_CMD_REISER) += reiser.o
 obj-$(CONFIG_CMD_REMOTEPROC) += remoteproc.o
 obj-$(CONFIG_CMD_RNG) += rng.o
+obj-$(CONFIG_CMD_KASLRSEED) += kaslrseed.o
 obj-$(CONFIG_CMD_ROCKUSB) += rockusb.o
 obj-$(CONFIG_CMD_RTC) += rtc.o
 obj-$(CONFIG_SANDBOX) += host.o

cmd/kaslrseed.c

@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * The 'kaslrseed' command takes bytes from the hardware random number
+ * generator and uses them to set the kaslr-seed value in the chosen node.
+ *
+ * Copyright (c) 2021, Chris Morgan <macromorgan@hotmail.com>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <dm.h>
+#include <hexdump.h>
+#include <malloc.h>
+#include <rng.h>
+#include <fdt_support.h>
+
+static int do_kaslr_seed(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	size_t n = 0x8;
+	struct udevice *dev;
+	u64 *buf;
+	int nodeoffset;
+	int ret = CMD_RET_SUCCESS;
+
+	if (uclass_get_device(UCLASS_RNG, 0, &dev) || !dev) {
+		printf("No RNG device\n");
+		return CMD_RET_FAILURE;
+	}
+
+	buf = malloc(n);
+	if (!buf) {
+		printf("Out of memory\n");
+		return CMD_RET_FAILURE;
+	}
+
+	if (dm_rng_read(dev, buf, n)) {
+		printf("Reading RNG failed\n");
+		return CMD_RET_FAILURE;
+	}
+
+	if (!working_fdt) {
+		printf("No FDT memory address configured. Please configure\n"
+		       "the FDT address via \"fdt addr <address>\" command.\n"
+		       "Aborting!\n");
+		return CMD_RET_FAILURE;
+	}
+
+	ret = fdt_check_header(working_fdt);
+	if (ret < 0) {
+		printf("fdt_chosen: %s\n", fdt_strerror(ret));
+		return CMD_RET_FAILURE;
+	}
+
+	nodeoffset = fdt_find_or_add_subnode(working_fdt, 0, "chosen");
+	if (nodeoffset < 0) {
+		printf("Reading chosen node failed\n");
+		return CMD_RET_FAILURE;
+	}
+
+	ret = fdt_setprop(working_fdt, nodeoffset, "kaslr-seed", buf, sizeof(buf));
+	if (ret < 0) {
+		printf("Unable to set kaslr-seed on chosen node: %s\n", fdt_strerror(ret));
+		return CMD_RET_FAILURE;
+	}
+
+	free(buf);
+
+	return ret;
+}
+
+#ifdef CONFIG_SYS_LONGHELP
+static char kaslrseed_help_text[] =
+	"[n]\n"
+	"  - append random bytes to chosen kaslr-seed node\n";
+#endif
+
+U_BOOT_CMD(
+	kaslrseed, 1, 0, do_kaslr_seed,
+	"feed bytes from the hardware random number generator to the kaslr-seed",
+	kaslrseed_help_text
+);

configs/evb-rk3568_defconfig

@@ -2,21 +2,43 @@ CONFIG_ARM=y
 CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_SYS_TEXT_BASE=0x00a00000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
-CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb"
 CONFIG_ROCKCHIP_RK3568=y
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
 CONFIG_TARGET_EVB_RK3568=y
 CONFIG_DEBUG_UART_BASE=0xFE660000
 CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb"
 CONFIG_DEBUG_UART=y
 CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_CRC32_SUPPORT=y
+CONFIG_SPL_ATF=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
 # CONFIG_CMD_SETEXPR is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
 CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
 CONFIG_MISC=y
@@ -30,6 +52,7 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
 CONFIG_REGULATOR_PWM=y
 CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
 CONFIG_DM_RESET=y
 CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2

configs/imx8mm_beacon_defconfig

@@ -21,7 +21,7 @@ CONFIG_SYS_LOAD_ADDR=0x40480000
 CONFIG_FIT=y
 CONFIG_FIT_EXTERNAL_OFFSET=0x3000
 CONFIG_SPL_LOAD_FIT=y
-CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_DEFAULT_FDT_FILE="imx8mm-beacon-kit.dtb"
 CONFIG_SPL_BOARD_INIT=y

configs/imx8mm_venice_defconfig

@@ -25,7 +25,7 @@ CONFIG_SYS_LOAD_ADDR=0x40480000
 CONFIG_FIT=y
 CONFIG_FIT_EXTERNAL_OFFSET=0x3000
 CONFIG_SPL_LOAD_FIT=y
-CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_SYSTEM_SETUP=y
 # CONFIG_USE_BOOTCOMMAND is not set
@@ -56,7 +56,7 @@ CONFIG_CMD_EXT4_WRITE=y
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_LIST="imx8mm-venice-gw71xx-0x imx8mm-venice-gw72xx-0x imx8mm-venice-gw73xx-0x imx8mm-venice-gw7901 imx8mm-venice-gw7902"
+CONFIG_OF_LIST="imx8mm-venice imx8mm-venice-gw71xx-0x imx8mm-venice-gw72xx-0x imx8mm-venice-gw73xx-0x imx8mm-venice-gw7901 imx8mm-venice-gw7902"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y

configs/imx8mn_beacon_2g_defconfig

@@ -26,7 +26,7 @@ CONFIG_SYS_LOAD_ADDR=0x40480000
 CONFIG_FIT=y
 CONFIG_FIT_EXTERNAL_OFFSET=0x3000
 CONFIG_SPL_LOAD_FIT=y
-CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_DEFAULT_FDT_FILE="imx8mn-beacon-kit.dtb"
 CONFIG_ARCH_MISC_INIT=y

configs/imx8mn_beacon_defconfig

@@ -25,7 +25,7 @@ CONFIG_SYS_LOAD_ADDR=0x40480000
 CONFIG_FIT=y
 CONFIG_FIT_EXTERNAL_OFFSET=0x3000
 CONFIG_SPL_LOAD_FIT=y
-CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_DEFAULT_FDT_FILE="imx8mn-beacon-kit.dtb"
 CONFIG_ARCH_MISC_INIT=y
@@ -34,6 +34,7 @@ CONFIG_SPL_BOOTROM_SUPPORT=y
 CONFIG_SPL_SEPARATE_BSS=y
 CONFIG_SPL_I2C=y
 CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="u-boot=> "
 # CONFIG_BOOTM_NETBSD is not set
@@ -60,7 +61,6 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent interrupts"
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
@@ -103,6 +103,7 @@ CONFIG_PHY_GIGE=y
 CONFIG_FEC_MXC=y
 CONFIG_MII=y
 CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
 CONFIG_PINCTRL_IMX8M=y
 CONFIG_DM_PMIC=y
 # CONFIG_SPL_PMIC_CHILDREN is not set
@@ -119,7 +120,9 @@ CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_NXP_FSPI=y
 CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
 CONFIG_SYSRESET_PSCI=y
+CONFIG_SYSRESET_WATCHDOG=y
 CONFIG_DM_THERMAL=y
 CONFIG_USB=y
 # CONFIG_SPL_DM_USB is not set
@@ -131,3 +134,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
 CONFIG_CI_UDC=y
 CONFIG_SDP_LOADADDR=0x0
 CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_IMX_WATCHDOG=y

configs/imx8mq_evk_defconfig

@@ -24,7 +24,7 @@ CONFIG_SYS_LOAD_ADDR=0x40480000
 CONFIG_FIT=y
 CONFIG_FIT_EXTERNAL_OFFSET=0x3000
 CONFIG_SPL_LOAD_FIT=y
-CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_BOARD_LATE_INIT=y
 CONFIG_SPL_BOARD_INIT=y

configs/imx8mq_phanbell_defconfig

@@ -24,7 +24,7 @@ CONFIG_SYS_LOAD_ADDR=0x40480000
 CONFIG_FIT=y
 CONFIG_FIT_EXTERNAL_OFFSET=0x3000
 CONFIG_SPL_LOAD_FIT=y
-CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
 CONFIG_SD_BOOT=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SPL_BOARD_INIT=y

configs/nitrogen6dl2g_defconfig

@@ -68,6 +68,8 @@ CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_FEC_MXC=y
 CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
 CONFIG_MXC_UART=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y

configs/nitrogen6dl_defconfig

@@ -68,6 +68,8 @@ CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_FEC_MXC=y
 CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
 CONFIG_MXC_UART=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y

configs/nitrogen6q2g_defconfig

@@ -70,6 +70,8 @@ CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_FEC_MXC=y
 CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
 CONFIG_MXC_UART=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y

configs/nitrogen6q_defconfig

@@ -70,6 +70,8 @@ CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_FEC_MXC=y
 CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
 CONFIG_MXC_UART=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y

configs/nitrogen6s1g_defconfig

@@ -68,6 +68,8 @@ CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_FEC_MXC=y
 CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
 CONFIG_MXC_UART=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y

configs/nitrogen6s_defconfig

@@ -68,6 +68,8 @@ CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_FEC_MXC=y
 CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
 CONFIG_MXC_UART=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y

configs/pico-imx8mq_defconfig

@@ -23,7 +23,7 @@ CONFIG_SYS_LOAD_ADDR=0x40480000
 CONFIG_FIT=y
 CONFIG_FIT_EXTERNAL_OFFSET=0x3000
 CONFIG_SPL_LOAD_FIT=y
-CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_BOARD_LATE_INIT=y
 CONFIG_SPL_BOARD_INIT=y

configs/px30-core-ctouch2-of10-px30_defconfig

@@ -0,0 +1,108 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEFAULT_DEVICE_TREE="px30-engicam-px30-core-ctouch2-of10"
+CONFIG_SPL_TEXT_BASE=0x00000000
+CONFIG_ROCKCHIP_PX30=y
+CONFIG_TARGET_PX30_CORE=y
+CONFIG_DEBUG_UART_CHANNEL=1
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_DEBUG_UART_BASE=0xFF160000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
+CONFIG_SYS_LOAD_ADDR=0x800800
+# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/px30-engicam-px30-core-ctouch2-of10.dtb"
+# CONFIG_CONSOLE_MUX is not set
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_MISC_INIT_R=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+# CONFIG_TPL_BANNER_PRINT is not set
+CONFIG_SPL_ATF=y
+# CONFIG_TPL_FRAMEWORK is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_LZMADEC is not set
+# CONFIG_CMD_UNZIP is not set
+CONFIG_CMD_GPT=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_FASTBOOT_BUF_ADDR=0x800800
+CONFIG_FASTBOOT_BUF_SIZE=0x04000000
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_ROCKCHIP_OTP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_TPL_RAM=y
+CONFIG_ROCKCHIP_SDRAM_COMMON=y
+CONFIG_DM_RESET=y
+CONFIG_DM_RNG=y
+CONFIG_RNG_ROCKCHIP=y
+# CONFIG_SPECIFY_CONSOLE_INDEX is not set
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_SOUND=y
+CONFIG_SYSRESET=y
+CONFIG_DM_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_DM_VIDEO=y
+CONFIG_DISPLAY=y
+CONFIG_LCD=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_TPL_TINY_MEMSET=y
+CONFIG_LZO=y
+CONFIG_ERRNO_STR=y

configs/px30-core-ctouch2-px30_defconfig

@@ -6,7 +6,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
-CONFIG_DEFAULT_DEVICE_TREE="px30-px30-core-ctouch2"
+CONFIG_DEFAULT_DEVICE_TREE="px30-engicam-px30-core-ctouch2"
 CONFIG_SPL_TEXT_BASE=0x00000000
 CONFIG_ROCKCHIP_PX30=y
 CONFIG_TARGET_PX30_CORE=y
@@ -23,7 +23,7 @@ CONFIG_SYS_LOAD_ADDR=0x800800
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
-CONFIG_DEFAULT_FDT_FILE="rockchip/px30-px30-core-ctouch2.dtb"
+CONFIG_DEFAULT_FDT_FILE="rockchip/px30-engicam-px30-core-ctouch2.dtb"
 # CONFIG_CONSOLE_MUX is not set
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y

configs/px30-core-edimm2.2-px30_defconfig

@@ -6,7 +6,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
-CONFIG_DEFAULT_DEVICE_TREE="px30-px30-core-edimm2.2"
+CONFIG_DEFAULT_DEVICE_TREE="px30-engicam-px30-core-edimm2.2"
 CONFIG_SPL_TEXT_BASE=0x00000000
 CONFIG_ROCKCHIP_PX30=y
 CONFIG_TARGET_PX30_CORE=y
@@ -23,7 +23,7 @@ CONFIG_SYS_LOAD_ADDR=0x800800
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
-CONFIG_DEFAULT_FDT_FILE="rockchip/px30-px30-core-edimm2.2.dtb"
+CONFIG_DEFAULT_FDT_FILE="rockchip/px30-engicam-px30-core-edimm2.2.dtb"
 # CONFIG_CONSOLE_MUX is not set
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y

configs/rock-pi-4-rk3399_defconfig

@@ -31,6 +31,7 @@ CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_ROCKCHIP_GPIO=y
+CONFIG_ROCKCHIP_EFUSE=y
 CONFIG_SYS_I2C_ROCKCHIP=y
 CONFIG_MISC=y
 CONFIG_MMC_DW=y

configs/rock-pi-4c-rk3399_defconfig

@@ -31,6 +31,7 @@ CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_ROCKCHIP_GPIO=y
+CONFIG_ROCKCHIP_EFUSE=y
 CONFIG_SYS_I2C_ROCKCHIP=y
 CONFIG_MISC=y
 CONFIG_MMC_DW=y

configs/udoo_defconfig

@@ -7,7 +7,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x60000
+CONFIG_ENV_OFFSET=0xC0000
 CONFIG_MX6QDL=y
 CONFIG_TARGET_UDOO=y
 CONFIG_DM_GPIO=y
@@ -35,6 +35,7 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=2
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DM=y
 CONFIG_BOUNCE_BUFFER=y

configs/udoo_neo_defconfig

@@ -27,6 +27,7 @@ CONFIG_SPL_FS_EXT4=y
 CONFIG_SPL_WATCHDOG=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_PINMUX is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_CACHE=y
@@ -35,6 +36,7 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_BOUNCE_BUFFER=y
 CONFIG_SYS_I2C_LEGACY=y
@@ -45,12 +47,18 @@ CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ8XXX=y
 CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_FEC_MXC=y
-CONFIG_RGMII=y
 CONFIG_MII=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
 CONFIG_POWER_LEGACY=y
 CONFIG_POWER_I2C=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_ANATOP=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
 CONFIG_MXC_UART=y
 CONFIG_IMX_THERMAL=y

doc/README.rockchip

@@ -81,30 +81,19 @@ Building
 
    - Compile ATF
 
-     For Puma board.
+     => git clone https://github.com/ARM-software/arm-trusted-firmware.git
+     => cd arm-trusted-firmware
 
-	=> git clone git://git.theobroma-systems.com/arm-trusted-firmware.git
-	=> cd arm-trusted-firmware
-	=> make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 bl31
+     (export cross compiler path for Cortex-M0 MCU likely arm-none-eabi-)
+     => make realclean
+     => make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399
 
-	(export bl31.bin)
-	=> export BL31=/path/to/arm-trusted-firmware/build/rk3399/release/bl31/bl31.bin
-
-     For rest of rk3399 boards.
-
-	=> git clone https://github.com/ARM-software/arm-trusted-firmware.git
-	=> cd arm-trusted-firmware
-
-	(export cross compiler path for Cortex-M0 MCU likely arm-none-eabi-)
-	=> make realclean
-	=> make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399
-
-	(export bl31.elf)
-	=> export BL31=/path/to/arm-trusted-firmware/build/rk3399/release/bl31/bl31.elf
+    (export bl31.elf)
+    => export BL31=/path/to/arm-trusted-firmware/build/rk3399/release/bl31/bl31.elf
 
    - Compile PMU M0 firmware
 
-     This is optional for most of the rk3399 boards and required only for Puma board.
+     This is optional for most of the rk3399 boards.
 
      => git clone git://git.theobroma-systems.com/rk3399-cortex-m0.git
      => cd rk3399-cortex-m0

doc/board/nxp/imx8mq_evk.rst

@@ -43,7 +43,7 @@ Build U-Boot
 
    $ export CROSS_COMPILE=aarch64-poky-linux-
    $ make imx8mq_evk_defconfig
-   $ make flash.bin
+   $ make
 
 Burn the flash.bin to MicroSD card offset 33KB:
 

doc/develop/uefi/uefi.rst

@@ -248,9 +248,9 @@ OP-TEE Build instructions
     $ export ARCH=arm
     $ CROSS_COMPILE32=arm-linux-gnueabihf- make -j32 CFG_ARM64_core=y \
         PLATFORM=<myboard> CFG_STMM_PATH=BL32_AP_MM.fd CFG_RPMB_FS=y \
-        CFG_RPMB_FS_DEV_ID=0 CFG_CORE_HEAP_SIZE=524288 CFG_RPMB_WRITE_KEY=1 \
-        CFG_CORE_HEAP_SIZE=524288 CFG_CORE_DYN_SHM=y CFG_RPMB_TESTKEY=y \
-        CFG_REE_FS=n CFG_CORE_ARM64_PA_BITS=48  CFG_TEE_CORE_LOG_LEVEL=1 \
+        CFG_RPMB_FS_DEV_ID=0 CFG_CORE_HEAP_SIZE=524288 CFG_RPMB_WRITE_KEY=y \
+        CFG_CORE_DYN_SHM=y CFG_RPMB_TESTKEY=y CFG_REE_FS=n \
+        CFG_CORE_ARM64_PA_BITS=48 CFG_TEE_CORE_LOG_LEVEL=1 \
         CFG_TEE_TA_LOG_LEVEL=1 CFG_SCTLR_ALIGNMENT_CHECK=n
 
 U-Boot Build instructions

drivers/clk/clk-uclass.c

@@ -846,17 +846,13 @@ void devm_clk_put(struct udevice *dev, struct clk *clk)
 
 int clk_uclass_post_probe(struct udevice *dev)
 {
-	int ret;
-
 	/*
 	 * when a clock provider is probed. Call clk_set_defaults()
 	 * also after the device is probed. This takes care of cases
 	 * where the DT is used to setup default parents and rates
 	 * using assigned-clocks
 	 */
-	ret = clk_set_defaults(dev, CLK_DEFAULTS_POST);
-	if (ret)
-		return log_ret(ret);
+	clk_set_defaults(dev, CLK_DEFAULTS_POST);
 
 	return 0;
 }

drivers/mtd/spi/Kconfig

@@ -129,12 +129,6 @@ config SPI_FLASH_UNLOCK_ALL
 	 For legacy reasons, this option default to y. But if you intend to
 	 actually use the software protection bits you should say n here.
 
-config SF_DUAL_FLASH
-	bool "SPI DUAL flash memory support"
-	help
-	  Enable this option to support two flash memories connected to a single
-	  controller. Currently Xilinx Zynq qspi supports this.
-
 config SPI_FLASH_ATMEL
 	bool "Atmel SPI flash support"
 	help

drivers/mtd/spi/spi-nor-ids.c

@@ -355,6 +355,11 @@ const struct flash_info spi_nor_ids[] = {
 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
 			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
 	},
+	{
+		INFO("w25q01jv", 0xef4021, 0, 64 * 1024, 2048,
+			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+	},
 	{ INFO("w25q80", 0xef5014, 0, 64 * 1024,  16, SECT_4K) },
 	{ INFO("w25q80bl", 0xef4014, 0, 64 * 1024,  16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{ INFO("w25q16cl", 0xef4015, 0, 64 * 1024,  32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },

drivers/power/pmic/Kconfig

@@ -128,6 +128,20 @@ config DM_PMIC_FAN53555
 	  The driver implements read/write operations for use with the FAN53555
 	  regulator driver and binds the regulator driver to its node.
 
+config SPL_DM_PMIC_FAN53555
+	bool "Enable support for OnSemi FAN53555 in SPL"
+	depends on SPL_DM_REGULATOR && SPL_DM_I2C
+	select SPL_DM_REGULATOR_FAN53555
+	help
+	  This config enables implementation of driver-model PMIC
+	  uclass features for the FAN53555 regulator. The FAN53555 is
+	  a (family of) single-output regulators that supports
+	  transitioning between two different output voltages based on
+	  an voltage selection pin.
+
+	  The driver implements read/write operations for use with the FAN53555
+	  regulator driver and binds the regulator driver to its node.
+
 config DM_PMIC_MP5416
 	bool "Enable Driver Model for PMIC MP5416"
 	help

drivers/power/pmic/Makefile

@@ -4,7 +4,7 @@
 # Lukasz Majewski <l.majewski@samsung.com>
 
 obj-$(CONFIG_$(SPL_TPL_)DM_PMIC) += pmic-uclass.o
-obj-$(CONFIG_DM_PMIC_FAN53555) += fan53555.o
+obj-$(CONFIG_$(SPL_)DM_PMIC_FAN53555) += fan53555.o
 obj-$(CONFIG_$(SPL_)DM_PMIC_DA9063) += da9063.o
 obj-$(CONFIG_DM_PMIC_MAX77686) += max77686.o
 obj-$(CONFIG_DM_PMIC_MAX8998) += max8998.o

drivers/spi/cadence_qspi_apb.c

@@ -858,6 +858,14 @@ cadence_qspi_apb_indirect_read_execute(struct cadence_spi_plat *plat,
 	writel(CQSPI_REG_INDIRECTRD_DONE,
 	       plat->regbase + CQSPI_REG_INDIRECTRD);
 
+	/* Check indirect done status */
+	ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTRD,
+				CQSPI_REG_INDIRECTRD_DONE, 0, 10, 0);
+	if (ret) {
+		printf("Indirect read clear completion error (%i)\n", ret);
+		goto failrd;
+	}
+
 	return 0;
 
 failrd:
@@ -1012,6 +1020,15 @@ cadence_qspi_apb_indirect_write_execute(struct cadence_spi_plat *plat,
 	/* Clear indirect completion status */
 	writel(CQSPI_REG_INDIRECTWR_DONE,
 	       plat->regbase + CQSPI_REG_INDIRECTWR);
+
+	/* Check indirect done status */
+	ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTWR,
+				CQSPI_REG_INDIRECTWR_DONE, 0, 10, 0);
+	if (ret) {
+		printf("Indirect write clear completion error (%i)\n", ret);
+		goto failwr;
+	}
+
 	if (bounce_buf)
 		free(bounce_buf);
 	return 0;

drivers/sysreset/sysreset_watchdog.c

@@ -20,9 +20,16 @@ static int wdt_reboot_request(struct udevice *dev, enum sysreset_t type)
 	struct wdt_reboot_plat *plat = dev_get_plat(dev);
 	int ret;
 
-	ret = wdt_expire_now(plat->wdt, 0);
-	if (ret)
-		return ret;
+	switch (type) {
+	case SYSRESET_COLD:
+	case SYSRESET_WARM:
+		ret = wdt_expire_now(plat->wdt, 0);
+		if (ret)
+			return ret;
+		break;
+	default:
+		return -ENOSYS;
+	}
 
 	return -EINPROGRESS;
 }

drivers/usb/gadget/dwc2_udc_otg.c

@@ -655,6 +655,7 @@ static int dwc2_ep_enable(struct usb_ep *_ep,
 		return -ESHUTDOWN;
 	}
 
+	_ep->desc = desc;
 	ep->stopped = 0;
 	ep->desc = desc;
 	ep->pio_irqs = 0;
@@ -695,6 +696,7 @@ static int dwc2_ep_disable(struct usb_ep *_ep)
 	/* Nuke all pending requests */
 	nuke(ep, -ESHUTDOWN);
 
+	_ep->desc = NULL;
 	ep->desc = 0;
 	ep->stopped = 1;
 

drivers/video/mxsfb.c

@@ -89,7 +89,7 @@ static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
 	}
 
 	ret = clk_get_by_name(dev, "axi", &clk);
-	if (!ret) {
+	if (ret < 0) {
 		debug("%s: Failed to get mxs axi clk: %d\n", __func__, ret);
 	} else {
 		ret = clk_enable(&clk);
@@ -100,7 +100,7 @@ static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
 	}
 
 	ret = clk_get_by_name(dev, "disp_axi", &clk);
-	if (!ret) {
+	if (ret < 0) {
 		debug("%s: Failed to get mxs disp_axi clk: %d\n", __func__, ret);
 	} else {
 		ret = clk_enable(&clk);

include/configs/rk3568_common.h

@@ -16,6 +16,12 @@
 #define CONFIG_IRAM_BASE		0xfdcc0000
 
 #define CONFIG_SYS_INIT_SP_ADDR		0x00c00000
+
+#define CONFIG_SPL_STACK		0x00400000
+#define CONFIG_SPL_MAX_SIZE		0x20000
+#define CONFIG_SPL_BSS_START_ADDR	0x4000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x4000
+
 #define CONFIG_SYS_BOOTM_LEN		(64 << 20)	/* 64M */
 
 #define CONFIG_SYS_SDRAM_BASE		0

include/configs/udoo.h

@@ -28,7 +28,7 @@
 	"fdt_addr=0x18000000\0" \
 	"fdt_addr_r=0x18000000\0" \
 	"ip_dyn=yes\0" \
-	"mmcdev=0\0" \
+	"mmcdev=2\0" \
 	"mmcrootfstype=ext4\0" \
 	"findfdt="\
 		"if test ${board_rev} = MX6Q; then " \
@@ -44,7 +44,7 @@
 	BOOTENV
 
 #define BOOT_TARGET_DEVICES(func) \
-	func(MMC, mmc, 0) \
+	func(MMC, mmc, 2) \
 	func(SATA, sata, 0) \
 	func(DHCP, dhcp, na)
 

include/configs/udoo_neo.h

@@ -29,7 +29,7 @@
 	"fdt_addr=0x83000000\0" \
 	"fdt_addr_r=0x83000000\0" \
 	"ip_dyn=yes\0" \
-	"mmcdev=0\0" \
+	"mmcdev=1\0" \
 	"mmcrootfstype=ext4\0" \
 	"findfdt="\
 		"if test $board_name = BASIC; then " \
@@ -49,7 +49,8 @@
 	BOOTENV
 
 #define BOOT_TARGET_DEVICES(func) \
-	func(MMC, mmc, 0) \
+	func(MMC, mmc, 1) \
+	func(USB, usb, 0) \
 	func(DHCP, dhcp, na)
 
 #include <config_distro_bootcmd.h>

include/efi.h

@@ -321,7 +321,7 @@ struct efi_info_hdr {
  * struct efi_entry_hdr - Header for a table entry
  *
  * @type:	enum eft_entry_t
- * @size	size of entry bytes excluding header and padding
+ * @size:	size of entry bytes excluding header and padding
  * @addr:	address of this entry (0 if it follows the header )
  * @link:	size of entry including header and padding
  * @spare1:	Spare space for expansion

include/tee.h

@@ -39,6 +39,7 @@
 #define TEE_SUCCESS			0x00000000
 #define TEE_ERROR_STORAGE_NOT_AVAILABLE	0xf0100003
 #define TEE_ERROR_GENERIC		0xffff0000
+#define TEE_ERROR_EXCESS_DATA		0xffff0004
 #define TEE_ERROR_BAD_PARAMETERS	0xffff0006
 #define TEE_ERROR_ITEM_NOT_FOUND	0xffff0008
 #define TEE_ERROR_NOT_IMPLEMENTED	0xffff0009

lib/aes/aes-encrypt.c

@@ -2,6 +2,9 @@
 /*
  * Copyright (c) 2019,Softathome
  */
+
+#define OPENSSL_API_COMPAT 0x10101000L
+
 #include "mkimage.h"
 #include <stdio.h>
 #include <string.h>

lib/ecdsa/ecdsa-libcrypto.c

@@ -18,6 +18,8 @@
  * Copyright (c) 2020,2021, Alexandru Gagniuc <mr.nuke.me@gmail.com>
  */
 
+#define OPENSSL_API_COMPAT 0x10101000L
+
 #include <u-boot/ecdsa.h>
 #include <u-boot/fdt-libcrypto.h>
 #include <openssl/ssl.h>