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438 Commits

Author SHA1 Message Date
Tom Rini
e092e32502 Prepare v2022.07
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-11 09:42:58 -04:00
Tom Rini
b960d654cb requirements: Move to atomicwrites==1.4.1
As explained upstream:
https://github.com/untitaker/python-atomicwrites/issues/61 there is no
longer a 1.3.0 version but the API is unchanged.  Move to 1.4.1.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-08 15:43:23 -04:00
Fabio Estevam
c519b82e7c imx8mq_phanbell: Remove custom CONFIG_SYS_MALLOC_F_LEN
Currently, the imx8mq_phanbell board fails to boot.

Remove the custom CONFIG_SYS_MALLOC_F_LEN setting in favor of the
generic one done via the main Kconfig.

Since commit b598957206 ("Kconfig: Fix SYS_MALLOC_F_LEN for i.MX8MQ")
the default SYS_MALLOC_F_LEN value for i.MX8MQ is 0x2000.

With such default value, the board boots again.

Signed-off-by: Fabio Estevam <festevam@denx.de>
2022-07-08 13:27:23 -04:00
Tom Rini
2d2c61ff04 Merge tag 'efi-2022-07-rc7' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request efi-2022-07-rc7

UEFI:

* correct verification of signed UEFI binaries
2022-07-06 09:17:08 -04:00
AKASHI Takahiro
8fb9dbdea7 test/py: efi_secboot: add a test for a forged signed image
In this test case, a image binary, helloworld.efi.signed, is willfully
modified to print a corrupted message while the signature itself is
unchanged.

This binary must be rejected under secure boot mode.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
2022-07-05 14:37:16 +02:00
AKASHI Takahiro
634f6b2fb1 efi_loader: image_loader: add a missing digest verification for signed PE image
At the last step of PE image authentication, an image's hash value must be
compared with a message digest stored as the content (of SpcPeImageData type)
of pkcs7's contentInfo.

Fixes: commit 4540dabdca ("efi_loader: image_loader: support image authentication")
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
2022-07-05 14:37:16 +02:00
AKASHI Takahiro
b72d09fa7d efi_loader: image_loader: replace EFI_PRINT with log macros
Now We are migrating from EFI_PRINT() to log macro's.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
2022-07-05 14:37:16 +02:00
AKASHI Takahiro
b330140659 efi_loader: signature: export efi_hash_regions()
This function is used to calculate a message digest as part of
authentication process in a later patch.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
2022-07-05 14:37:16 +02:00
AKASHI Takahiro
b124efc09f lib: crypto: add mscode_parser
In MS authenticode, pkcs7 should have data in its contentInfo field.
This data is tagged with SpcIndirectData type and, for a signed PE image,
provides a image's message digest as SpcPeImageData.

This parser is used in image authentication to parse the field and
retrieve a message digest.

Imported from linux v5.19-rc, crypto/asymmetric_keys/mscode*.
Checkpatch.pl generates tones of warnings, but those are not fixed
for the sake of maintainability (importing from another source).

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
2022-07-05 14:37:16 +02:00
Tom Rini
0cc846dafc Prepare v2022.07-rc6
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-04 08:18:33 -04:00
Tom Rini
d98a6a95bd configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-04 08:15:34 -04:00
Andre Przywara
9125b4b021 usb: host: ehci-generic: Fix error check
Commit 81755b8c20 ("usb: host: ehci-generic: Make resets and clocks
optional") improved the error check to cover the reset property being
optional. However this was using the wrong error variable for the
check, so would now never fail.

Use the correct error variable for checking the result of
reset_get_bulk(), to actually report genuine errors.

Fixes: 81755b8c20 ("usb: host: ehci-generic: Make resets and clocks optional")
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-07-04 08:00:36 -04:00
Tom Rini
730fc474b1 Merge tag 'efi-2022-07-rc6' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request for efi-2022-07-rc6

UEFI:

* Fix EFI_IO_BLOCK_PROTOCOL: read correct blocks on partitions

Other:

* Honor CONFIG_SYS_64BIT_LBA in the disk uclass
2022-07-02 09:55:26 -04:00
Tom Rini
6cae9aeeab Merge branch '2022-07-01-additional-critical-fixes-and-updates'
- Update some MAINTAINERS entries, fix a regression on FIT images
2022-07-02 09:54:46 -04:00
Paul Barbieri
7a85f32413 EFI: Fix ReadBlocks API reading incorrect sector for UCLASS_PARTITION devices
The requsted partition disk sector incorrectly has the parition start
sector added in twice for UCLASS_PARTITION devices. The efi_disk_rw_blocks()
routine adds the diskobj->offset to the requested lba. When the device
is a UCLASS_PARTITION, the dev_read() or dev_write() routine is called
which adds part-gpt_part_info.start. This causes I/O to the wrong sector.

Takahiro Akashi suggested removing the offset field from the efi_disk_obj
structure since disk-uclass.c handles the partition start biasing. Device
types other than UCLASS_PARTITION set the diskobj->offset field to zero
which makes the field unnecessary. This change removes the offset field
from the structure and removes all references from the code which is
isolated to the lib/efi_loader/efi_disk.c module.

This change also adds a test for the EFI ReadBlocks() API in the EFI
selftest code. There is already a test for reading a FAT file. The new
test uses ReadBlocks() to read the same "disk" block and compare it to
the data read from the file system API.

Signed-Off-by: Paul Barbieri <plb365@gmail.com>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Cc: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-07-02 14:19:12 +02:00
Heinrich Schuchardt
054de212ce disk: honor CONFIG_SYS_64BIT_LBA
Without the patch for qemu-x86_defconfig:

* sizeof(lbaint_t) = 4 in dev_read()
* sizeof(lbaint_t) = 8 in blkcache_read()

CONFIG_SYS_64BIT_LBA is defined in common.h via
include/configs/x86-common.h:22.

We have to include common.h before including blk.h.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-07-02 14:19:09 +02:00
Joel Stanley
c5e2442033 image: fit: Use stack allocation macro
The documentation above the DEFINE_ALIGN_BUFFER says it's for use
outside functions, but we're inside one.

Instead use ALLOC_CACHE_ALIGN_BUFFER, the stack based macro, which also
includes the cache alignment.

Fixes: b583348ca8 ("image: fit: Align hash output buffers")
Signed-off-by: Joel Stanley <joel@jms.id.au>
Tested-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Sean Anderson <sean.anderson@seco.com>
2022-07-01 16:01:25 -04:00
Michael Trimarchi
975918f6a1 MAINTAINERS: Add Dario and Michael as NAND maintainers
Both of us are working on NAND subsystem on several architectures and
we have boards and projects to improve the subsystem in uboot. The idea
is to guarantee quick feedback on patches sent on mailing list and most
of the time the possibilities to test them.

Cc: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Acked-by: Tom Rini <trini@konsulko.com>
2022-07-01 16:00:54 -04:00
Hannes Schmelzer
04b26c9896 board/BuR/*: replace maintainer of BuR boards
Since I'm leaving the company with end of June, the maintainership will
be transferred to Wolfgang Wallner.

Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2022-07-01 16:00:36 -04:00
Tom Rini
936d468b7b chameleonv3: Add MAINTAINERS file
This file was missing, add.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-01 15:55:54 -04:00
Tom Rini
9fcc2fb3fe Merge commit 'ef5ba2cef4a08b68caaa9215fcac142d3025bbf7' of https://github.com/tienfong/uboot_mainline 2022-07-01 09:14:32 -04:00
Tom Rini
085fea0b65 Merge tag 'u-boot-amlogic-20220701' of https://source.denx.de/u-boot/custodians/u-boot-amlogic
- search dtb for meson-axg-usb-ctrl on board axg
2022-07-01 09:13:58 -04:00
Teik Heng Chong
ef5ba2cef4 drivers: clk: Update license for Intel N5X device
All the source code of clk-mem-n5x.c and clk-n5x.c are from Intel,
update the license to use both GPL2.0 and BSD-3 Clause because this
copy of code may used for open source and internal project.

Signed-off-by: Teik Heng Chong <teik.heng.chong@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2022-07-01 15:00:39 +08:00
Paweł Anikiel
e26ecebc68 socfpga: arria10: Allow dcache_enable before relocation
Before relocating to SDRAM, the ECC is initialized by clearing the
whole SDRAM. In order to speed this up, dcache_enable is used (see
sdram_init_ecc_bits).

Since commit 503eea4519 ("arm: cp15: update DACR value to activate
access control"), this no longer works, because running code in OCRAM
with the XN bit set causes a page fault. Override dram_bank_mmu_setup
to disable XN in the OCRAM and setup DRAM dcache before relocation.

Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-07-01 14:57:15 +08:00
Paweł Anikiel
5c53d9c0d9 socfpga: arria10: Wait for fifo empty after writing bitstream
For some reason, on the Mercury+ AA1 module, calling
fpgamgr_wait_early_user_mode immediately after writing the peripheral
bitstream leaves the fpga in a broken state (ddr calibration hangs).
Adding a delay before the first sync word is written seems to fix this.
Inspecting the fpgamgr registers before and after the delay,
imgcfg_FifoEmpty is the only bit that changes. Waiting for this bit
(instead of a hardcoded delay) also fixes the issue.

Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-07-01 14:57:14 +08:00
Paweł Anikiel
8b1eee3730 socfpga: arria10: Improve bitstream loading speed
Apply some optimizations to speed up bitstream loading
(both for full and split periph/core bitstreams):

 * Change the size of the first fs read, so that all the subsequent
   reads are aligned to a specific value (called MAX_FIRST_LOAD_SIZE).
   This value was chosen so that in subsequent reads the fat fs driver
   doesn't have to allocate a temporary buffer in get_contents
   (assuming 8KiB clusters).

 * Change the buffer size to a larger value when reading to ddr
   (but not too large, because large transfers cause a stack overflow
   in the dwmmc driver).

Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-07-01 14:57:14 +08:00
Paweł Anikiel
aea0e80a9f socfpga: arria10: Replace delays with busy waiting in cm_full_cfg
Using udelay while the clocks aren't fully configured causes the timer
system to save the wrong clock rate. Use sdelay and wait_on_value
instead (the values used in these functions were found experimentally).

Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2022-07-01 14:57:14 +08:00
Paweł Anikiel
9ebca7095b sysreset: socfpga: Use parent device for reading base address
This driver is a child of the rstmgr driver, both of which share the
same devicetree node. As a result, passing the child's udevice pointer
to dev_read_addr_ptr results in a failure of reading the #address-cells
property. Use the parent udevice pointer instead.

Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-07-01 14:57:14 +08:00
Paweł Anikiel
73d88cf971 misc: atsha204a: Increase wake delay by tWHI
From the ATSHA204A datasheet (document DS40002025A):

Wake: If SDA is held low for a period greater than tWLO, the device
exits low-power mode and, after a delay of tWHI, is ready to receive
I2C commands.

tWHI value can be found in table 7-2.

Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-07-01 14:57:14 +08:00
Paweł Anikiel
61298270c5 config: Add Chameleonv3 config
Add defconfig and Kconfig files for Google Chameleon V3 board

Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-07-01 14:57:14 +08:00
Paweł Anikiel
813c800107 board: Add Chameleonv3 board dir
Add board directory for Google Chameleon V3 board

Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-07-01 14:57:14 +08:00
Paweł Anikiel
8566b3682f arm: dts: Add Chameleonv3 devicetrees
Add devicetrees for Google Chameleon V3 board

Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-07-01 14:57:14 +08:00
Paweł Anikiel
882c00edeb arm: dts: Add Chameleonv3 handoff headers
Add handoff headers for the Google Chameleonv3 variants: 480-2 and
270-3. Both files were generated using qts-filter-a10.sh.

Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-07-01 14:57:14 +08:00
Paweł Anikiel
e21b8ac3f1 arm: dts: Add Mercury+ AA1 devicetrees
Devicetree headers for Mercury+ AA1 module

Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-07-01 14:57:13 +08:00
Tom Rini
33938636f0 Merge tag 'u-boot-rockchip-20220630' of https://source.denx.de/u-boot/custodians/u-boot-rockchip
- Fix for rk3328 nonopi-r2s boot env;
- Fix for rk8xx pmic boot on power plug-in;
- Fix for tee.bin support in fit image;
- rk3288 board dts update or fix;
- Some rk3399 board fix;
2022-06-30 22:36:41 -04:00
Andrea Scian
05dcb5be50 mtd: mxs_nand_spl: fix nand_command protocol violation
mxs_nand_command() implementation assume that it's working with a
LP NAND, which is a common case nowadays and thus uses two bytes
for column address.

However this is wrong for NAND_CMD_READID and NAND_CMD_PARAM, which
expects only one byte of column address, even for LP NANDs.
This leads to ONFI detection problem with some NAND manufacturer (like
Winbond) but not with others (like Samsung and Spansion)

We fix this with a simple workaround to avoid the 2nd byte column address
for those two commands.

Also align the code with nand_base to support 16 bit devices.

Tested on an iMX6SX device with:
* Winbond W29N04GVSIAA
* Spansion S34ML04G100TF100
* Samsung K9F4G08U00

Tested on imx8mn device with:
* Windbond W29N04GV

Signed-off-by: Andrea Scian <andrea.scian@dave.eu>
CC: Stefano Babic <sbabic@denx.de>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-06-29 09:26:44 -04:00
Peter Robinson
fce1e9bba2 rockchip: pinebook-pro: sync PBP dtb to 5.18
Sync the pinebook pro to upstream 5.18, in particular this brings
brings in a fix so the DP is disabled so Linux will actually boot.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-06-29 11:43:05 +08:00
Peter Robinson
1ed1827fb3 rockchip: rockpro64: enable leds
The Rockpro64 has some GPIO leds so let's enable them so the
user gets some output in early boot.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-06-29 11:42:54 +08:00
Peter Robinson
26f7842bd4 rockchip: pinebook-pro: minor SPI flash fixes
Set a default offset for environment so it doesn't write it to
unexpected locations, drop unneeded mtd config option.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-06-29 11:42:44 +08:00
Chris Morgan
30975fb73d rockchip: Add option to prevent booting on power plug-in
For Rockchip boards with the all rk8xx series PMICs (excluding the
rk808), it is sometimes desirable to not boot whenever the device is
plugged in. An example would be for the Odroid Go Advance.

This provides a configurable option to check the PMIC says it was
powered because of a plug-in event. If the value is 1 and this option
is selected, the device shuts down shortly after printing a message
to console stating the reason why it's shutting down. Powering up the
board with the power button is not affected.

This patch parallels the work done in the following patch series:
https://lore.kernel.org/u-boot/20220121133732.2397273-1-andre.przywara@arm.com/

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-06-29 11:42:10 +08:00
Chris Morgan
ad607512f5 power: pmic: rk8xx: Support sysreset shutdown method
Add support for sysreset shutdown for this PMIC. The values were pulled
from the various datasheets, but for now it has only been tested on
the rk817 (for an Odroid Go Advance).

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-06-29 11:42:10 +08:00
Jerome Forissier
348310233d mach-rockchip: make_fit_atf.py: support OP-TEE tee.bin v1 format
This commit adds support for the OP-TEE 'tee.bin' v1 format for Rockchip
platforms.

Since OP-TEE 3.8.0, tee.bin contains meta-data in a proprietary format
in addition to the ELF data. They are essential information for proper
initialization of the TEE core, such as the size of the memory region
covered by the TEE or a compact representation of runtime relocation
data when ASLR is enabled.

With OP-TEE 3.8.0 onwards, 'tee.elf' MUST NOT be used and 'tee.bin'
MUST be used instead. Ignoring this recommendation can lead to crashes
as described in [3].

Link: [1] 5dd1570ac5
Link: [2] https://github.com/OP-TEE/optee_os/blob/3.17.0/scripts/gen_tee_bin.py#L275-L302
Link: [3] https://github.com/OP-TEE/optee_os/issues/4542
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2022-06-29 11:32:35 +08:00
Emmanuel Vadot
743ce226bd rockchip: rk3328: nanopi-r2s: Use the sdcard for the env
The NanoPi-R2S doesn't have eMMC so use the sdcard as the device
to save the environment variables

Signed-off-by: Emmanuel Vadot <manu@FreeBSD.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-06-29 11:30:15 +08:00
Johan Jonker
6f0037f305 arm: dts: rockchip: rk3288: move dma-controller nodes
In order to better compare the Linux rk3288.dtsi version
with the u-boot version move the dma-controller nodes
to the DT root.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-06-29 11:29:52 +08:00
Johan Jonker
e0bf010ab9 arm: dts: rockchip: rk3288: sort mipi hdmi lvds and dp nodes
In order to better compare the Linux rk3288.dtsi version
with the u-boot version sort the mipi,hdmi,lvds and dp nodes.

Changed:
  Rename mipi_dsi label.
  Rename dp nodename.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-06-29 11:29:03 +08:00
Johan Jonker
170447466c arm: dts: rockchip: rk3288: bulk convert gpios to their constant counterparts
Bulk convert rk3288 DT gpios to their constant counterparts.

Partial Linux sync for the rk3288.dtsi file.

ARM: dts: rockchip: bulk convert gpios to their constant counterparts
https://lore.kernel.org/all/20190402121852.14442-1-heiko@sntech.de/

sed -i -f script.sed rk3288.dtsi

================================

/rockchip,pins *=/bcheck
b # to end of script
:append-next-line
N
:check
/^[^;]*$/bappend-next-line
s/<RK_GPIO\([0-9]\) /<\1 /g
s/<\([^ ][^ ]*  *\)0 /<\1RK_PA0 /g
s/<\([^ ][^ ]*  *\)1 /<\1RK_PA1 /g
s/<\([^ ][^ ]*  *\)2 /<\1RK_PA2 /g
s/<\([^ ][^ ]*  *\)3 /<\1RK_PA3 /g
s/<\([^ ][^ ]*  *\)4 /<\1RK_PA4 /g
s/<\([^ ][^ ]*  *\)5 /<\1RK_PA5 /g
s/<\([^ ][^ ]*  *\)6 /<\1RK_PA6 /g
s/<\([^ ][^ ]*  *\)7 /<\1RK_PA7 /g
s/<\([^ ][^ ]*  *\)8 /<\1RK_PB0 /g
s/<\([^ ][^ ]*  *\)9 /<\1RK_PB1 /g
s/<\([^ ][^ ]*  *\)10 /<\1RK_PB2 /g
s/<\([^ ][^ ]*  *\)11 /<\1RK_PB3 /g
s/<\([^ ][^ ]*  *\)12 /<\1RK_PB4 /g
s/<\([^ ][^ ]*  *\)13 /<\1RK_PB5 /g
s/<\([^ ][^ ]*  *\)14 /<\1RK_PB6 /g
s/<\([^ ][^ ]*  *\)15 /<\1RK_PB7 /g
s/<\([^ ][^ ]*  *\)16 /<\1RK_PC0 /g
s/<\([^ ][^ ]*  *\)17 /<\1RK_PC1 /g
s/<\([^ ][^ ]*  *\)18 /<\1RK_PC2 /g
s/<\([^ ][^ ]*  *\)19 /<\1RK_PC3 /g
s/<\([^ ][^ ]*  *\)20 /<\1RK_PC4 /g
s/<\([^ ][^ ]*  *\)21 /<\1RK_PC5 /g
s/<\([^ ][^ ]*  *\)22 /<\1RK_PC6 /g
s/<\([^ ][^ ]*  *\)23 /<\1RK_PC7 /g
s/<\([^ ][^ ]*  *\)24 /<\1RK_PD0 /g
s/<\([^ ][^ ]*  *\)25 /<\1RK_PD1 /g
s/<\([^ ][^ ]*  *\)26 /<\1RK_PD2 /g
s/<\([^ ][^ ]*  *\)27 /<\1RK_PD3 /g
s/<\([^ ][^ ]*  *\)28 /<\1RK_PD4 /g
s/<\([^ ][^ ]*  *\)29 /<\1RK_PD5 /g
s/<\([^ ][^ ]*  *\)30 /<\1RK_PD6 /g
s/<\([^ ][^ ]*  *\)31 /<\1RK_PD7 /g
s/<\([^ ][^ ]*  *[^ ][^ ]*  *\)0 /<\1RK_FUNC_GPIO /g
s/<\([^ ][^ ]*  *[^ ][^ ]*  *\)RK_FUNC_\([1-9]\) /<\1\2 /g

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-06-29 11:28:38 +08:00
Johan Jonker
196e0c6223 arm: dts: rockchip: remove usb-phy fallback string for rk3188
With the conversion of rockchip-usb-phy.yaml a long time used fallback
string for rk3066a/rk3188 was added. The linux driver doesn't do much with
the GRF phy address range, however the u-boot driver rockchip_usb2_phy.c
does. The bits in GRF_UOC0_CON2 for rk3066a/rk3188 and rk3288 for example
don't match. Remove the usb-phy fallback string for rk3188
to prevent possible strange side effects.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-06-29 11:28:16 +08:00
Johan Jonker
e0479b71ed rockchip: board: change condition board_usb_init() in function
Change define condition in board_usb_init() function
to allow rk3066/rk3188 to use the USB PHY driver.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-06-29 11:28:16 +08:00
Johan Jonker
42a2f7a46d rockchip: usb: phy: add rk3066/rk3188 support
Add rk3066a/rk3188 support to rockchip_usb2_phy.c
They don't have completely identical usb phy registers,
so separate comapatible strings and data.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-06-29 11:28:15 +08:00
Paweł Jarosz
8fb5595525 rockchip: usb: gadget: add rk3066 product id
Product id of rk3066 usb otg is 0x300a.

Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-06-29 11:28:15 +08:00
Johan Jonker
43c084ccbc rockchip: include: configs: remove unused configs for tag and size
The configs ROCKCHIP_CHIP_TAG and ROCKCHIP_MAX_INIT_SIZE were
originally added with rksd.c, rkspi.c and rkcommon.c in mind,
but are no longer in use and replaced by struct spl_info,
so remove unused configs for tag and size.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-06-29 11:27:56 +08:00
Simon Glass
cd92fff72e phycore-rk3288: Avoid enabling partition support in SPL
This is not needed or used, and adds code size. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-06-29 11:27:28 +08:00
Tom Rini
a063429c17 Merge branch '2022-06-28-assorted-fixes'
- Fix a squashfs security issue, an i2c access security issue and fix
  NAND booting on imx8mn_bsh_smm_s2
2022-06-28 17:02:25 -04:00
Dario Binacchi
0c4db621e2 configs: imx8mn_bsh_smm_s2: add mtdparts to bootargs
Passing the mtdparts environment variable to the Linux kernel is
required to properly mount the UBI rootfs.

Co-developed-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-06-28 15:51:56 -04:00
Dario Binacchi
bede82f750 configs: imx8mn_bsh_smm_s2: remove console from bootargs
The Linux kernel device tree already specifies the device to be used for
boot console output with a stdout-path property under /chosen.

Co-developed-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-06-28 15:51:56 -04:00
Dario Binacchi
592e04cde5 configs: imx8mn_bsh_smm_s2: add UBI commands
imx8mn_bsh_smm_s2 uses ubifs rootfs, UBI commands are required to flash
it.

Co-developed-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-06-28 15:51:56 -04:00
Dario Binacchi
93899d0746 configs: imx8mn_bsh_smm_s2: add NAND driver
It allows to boot from NAND.

Co-developed-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-06-28 15:51:56 -04:00
Miquel Raynal
7f7fb9937c fs/squashfs: Use kcalloc when relevant
A crafted squashfs image could embed a huge number of empty metadata
blocks in order to make the amount of malloc()'d memory overflow and be
much smaller than expected. Because of this flaw, any random code
positioned at the right location in the squashfs image could be memcpy'd
from the squashfs structures into U-Boot code location while trying to
access the rearmost blocks, before being executed.

In order to prevent this vulnerability from being exploited in eg. a
secure boot environment, let's add a check over the amount of data
that is going to be allocated. Such a check could look like:

if (!elem_size || n > SIZE_MAX / elem_size)
	return NULL;

The right way to do it would be to enhance the calloc() implementation
but this is quite an impacting change for such a small fix. Another
solution would be to add the check before the malloc call in the
squashfs implementation, but this does not look right. So for now, let's
use the kcalloc() compatibility function from Linux, which has this
check.

Fixes: c510061303 ("fs/squashfs: new filesystem")
Reported-by: Tatsuhiko Yasumatsu <Tatsuhiko.Yasumatsu@sony.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Tested-by: Tatsuhiko Yasumatsu <Tatsuhiko.Yasumatsu@sony.com>
2022-06-28 15:51:56 -04:00
Nicolas Iooss
8f8c04bf1e i2c: fix stack buffer overflow vulnerability in i2c md command
When running "i2c md 0 0 80000100", the function do_i2c_md parses the
length into an unsigned int variable named length. The value is then
moved to a signed variable:

    int nbytes = length;
    #define DISP_LINE_LEN 16
    int linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes;
    ret = dm_i2c_read(dev, addr, linebuf, linebytes);

On systems where integers are 32 bits wide, 0x80000100 is a negative
value to "nbytes > DISP_LINE_LEN" is false and linebytes gets assigned
0x80000100 instead of 16.

The consequence is that the function which reads from the i2c device
(dm_i2c_read or i2c_read) is called with a 16-byte stack buffer to fill
but with a size parameter which is too large. In some cases, this could
trigger a crash. But with some i2c drivers, such as drivers/i2c/nx_i2c.c
(used with "nexell,s5pxx18-i2c" bus), the size is actually truncated to
a 16-bit integer. This is because function i2c_transfer expects an
unsigned short length. In such a case, an attacker who can control the
response of an i2c device can overwrite the return address of a function
and execute arbitrary code through Return-Oriented Programming.

Fix this issue by using unsigned integers types in do_i2c_md. While at
it, make also alen unsigned, as signed sizes can cause vulnerabilities
when people forgot to check that they can be negative.

Signed-off-by: Nicolas Iooss <nicolas.iooss+uboot@ledger.fr>
Reviewed-by: Heiko Schocher <hs@denx.de>
2022-06-28 15:51:56 -04:00
Tom Rini
b75fd37037 Merge tag 'u-boot-imx-20220628' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
Fixes for 2022.07

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/12541
2022-06-28 11:10:23 -04:00
Fabio Estevam
b5023254b8 kontron-sl-mx8mm: Add CAAM support
Add CAAM support, which is required when enabling HAB secure boot.

Select CONFIG_SPL_DRIVERS_MISC so that CONFIG_IMX_HAB could
build successfully, if selected.

Signed-off-by: Fabio Estevam <festevam@denx.de>
Acked-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2022-06-28 15:24:31 +02:00
Francesco Dolcini
66af2c3e95 board: apalis_imx6: DDR init using mx6_dram_cfg()
Do DDR initialization using the procedural mx6_dram_cfg() instead of
programming the MMDC using a raw list of register/value pairs, this
solves some rare boot failures on specific "bad" modules.

Calibration values, DDR geometry are unchanged, memory timings are
updated according to the relevant memory datasheet, no changes on
the power consumption.

For IT temperature range SKUs CL is decreased from 8 to 7 and tFAW
value is increased, for commercial temperature range SKUs some
changes on ODT parameters.

This change was validated over a range of different apalis-imx6 SoM, on
the whole working temperature range with weeks of continuous testing.

Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-06-28 15:24:31 +02:00
Frieder Schrempf
1af2d4697a imx: kontron-sl-mx8mm: Enable PCA9450 regulator driver and fix SD card access
Currently accessing the SD card on USDHC2 fails with:

=> mmc dev 1
Card did not respond to voltage select! : -110

This is due to the fact that UHS modes are enabled in the defconfig
and the devicetree, but the referenced LDO5 regulator (reg_nvcc_sd)
is not available to switch the data lines from 3.3V to 1.8V mode.

By enabling the regulator driver the vqmmc-supply is now available
and the SD card works also in high speed modes:

=> mmc dev 1
switch to partitions #0, OK
mmc1 is current device

Please note that the board has a GPIO connected to the SD_VSEL signal
of the PMIC. As the driver uses the LDO5CTRL_H register to set the
voltage, we need to make sure that this GPIO (GPIO01_IO4) is set to
a high level.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Tested-by: Fabio Estevam <festevam@denx.de>
2022-06-28 15:24:31 +02:00
Frieder Schrempf
2add051175 pmic: pca9450: Add optional SD_VSEL GPIO for LDO5
LDO5 has two separate control registers. LDO5CTRL_L is used if the
input signal SD_VSEL is low and LDO5CTRL_H if it is high.
The current driver implementation only uses LDO5CTRL_H. To make this
work on boards that have SD_VSEL connected to a GPIO, we add support
for specifying an optional GPIO and setting it to high at probe time.

In the future we might also want to add support for boards that have
SD_VSEL set to a fixed low level. In this case we need to change the
driver to be able to use the LDO5CTRL_L register.

This is a port of the same change in the Linux kernel:
8c67a11bae88 ("regulator: pca9450: Add SD_VSEL GPIO for LDO5")

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Tested-by: Fabio Estevam <festevam@denx.de>
2022-06-28 15:24:31 +02:00
Francesco Dolcini
6b5ecb8293 mx6: ddr: Fix disabling on-die termination
In case rtt_nom is set to 0 keep ODT disabled (MMDC MPODTCTRL = 0).
No changes required for DDR MR1 Rtt_Nom impedance register, 0 value is
already handled correctly.

No board is currently affected by this change (rtt_nom != 0 on all i.MX6
ddr3 boards), this will be used by a follow-up change.

Fixes: fe0f7f7842 ("mx6: add mmdc configuration for MX6Q/MX6DL")
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-06-28 15:24:31 +02:00
Francesco Dolcini
d4cd19ded8 toradex: apalis/colibri_imx6: Fix CLKO1/CLKO2 output
Set CLK01 and CLK02 to 24MHz and enable it in CCM_CCOSR register.

This clock is used by both the audio codec (CLKO1) and by the CSI camera
(CLKO2) and is expected to be 24MHz.

Despite the wrong 16.5MHz there was no real issue because of the wrong
frequency since Linux reconfigures the clocks afterward, however this
was triggering an issue with noise coming from the SGTL5000 audio codec.

The problem is that the SGTL5000 does not have a reset pin and after it
is configured if the input MCLK clock is disabled it produces a constant
noise on its output, this was happening on software reboot.

Forcing the clock to be enabled in U-Boot prevent the problem by making
sure that the clock is always available, without this change as soon as
Linux was changing the clock tree (setting clk_out_sel=1 without setting
clko2_en=1) the noise would start till the actual clock was enabled
(clko2_en=1) during the SGTL5000 driver probe.

Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-06-28 15:24:31 +02:00
Marek Vasut
b70c34224e ARM: imx: Switch Data Modul i.MX8M Mini eDM SBC to USB251x Hub driver
Replace the ad-hoc I2C register programming scripted in board
environment with U-Boot DM driver.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-06-28 15:24:31 +02:00
Andrejs Cainikovs
0543a1ed27 imx8m: fixup thermal trips
Fixup thermal trips in Linux device tree according to SoC thermal
grade.

Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Tested-by: Adam Ford <aford173@gmail.com>
2022-06-28 13:35:09 +02:00
Tom Rini
bfa9306e14 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi
The main attraction are two regressions, plus a fix
for a long standing bug:
- Fix USB support on boards with a switched VBUS regulator.
- Fix failing boot due to env loading on boards without MMC (CHIP).
- Fix PSCI CPU_OFF operation on R40 boards.
The rest are smaller fixes, and the forgotten DT sync for sun4i boards.
2022-06-26 21:06:08 -04:00
qianfan Zhao
47ca7b574f sunxi: psci: Fix sunxi_power_switch on sun8i-r40 platform
linux system will die if we offline one of the cpu on R40 based board:
eg: echo 0 > /sys/devices/system/cpu/cpu3/online

The reason is that the R40 version of sunxi_cpu_set_power always passes
0 for the CPU number, so we turn off CPU0, regardless of what CPU the
CPU_OFF request came for.

Fix this by passing the proper CPU number, as there are proper power
clamp registers for every of the four cores.

Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-06-26 11:22:54 +01:00
Samuel Holland
e008e5132f sunxi: fix initial environment loading without MMC
Commit e42dad4168 ("sunxi: use boot source for determining environment
location") changed our implementation of env_get_location() and enabled
it for every board, even those without MMC support (like the C.H.I.P.
boards). However the default fallback location of ENVL_FAT requires MMC
support compiled in, so the board hangs when trying to initially load
the environment.

Change the algorithm to only return configured environment locations,
and improve the fallback algorithm on the way.

The env_init() routine calling this function here does not behave well
if the return value is ENVL_UNKNOWN on the very first call: it will make
U-Boot proper silently hang very early.
Work around this issue by making sure we return some configured (dummy)
environment location when prio is 0. This for instance happens when
booting via FEL.

This fixes U-Boot loading on the C.H.I.P. boards.

Fixes: e42dad4168 ("sunxi: use boot source for determining environment location")
Reported-by: Chris Morgan <macroalpha82@gmail.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
[Andre: fix FEL boot case by not returning ENVL_UNKNOWN when prio==0]
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-06-26 11:22:54 +01:00
Samuel Holland
33112ae021 clk: sunxi: Add additional RTC compatible strings
Compatible strings for some new RTC hardware variants were added to
the binding. Add them to the driver in preparation for supporting
those new SoCs.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-06-26 11:22:53 +01:00
Samuel Holland
957a3b9820 gpio: sunxi: Fix build with CONFIG_SPL_SERIAL=n
This driver uses simple_strtol(), so it needs SPL_STRTO. Before commit
88ca8e2695 ("disk: Add an option for partitions in SPL"), SPL_STRTO
was always selected indirectly. Now it is not, so select it here.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-06-26 11:22:53 +01:00
Samuel Holland
006ef34bd4 ARM: dts: sun4i: Sync from Linux v5.18-rc1
Copy the devicetree source for the A10 SoC and all existing boards
verbatim from the Linux v5.18-rc1 tag.

The previous version of this change was only partially applied.

Fixes: 4746694cba ("ARM: dts: sun4i: Sync from Linux v5.18-rc1")
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-06-26 11:22:53 +01:00
Andre Przywara
3c0b9adb89 sunxi: usb: convert PHY GPIO functions to DM
The Allwinner USB PHY driver is still using the legacy GPIO interface,
which is now implemented by the DM_GPIO compat functions.
Those seem to have some design flaws, as setting the direction, then
later setting the value will not work, if the DM_GPIO driver is
implementing set_flags.

Fix this by using the dm_ version of the direct GPIO interface, which
uses struct gpio_desc structs to handle requested GPIOs, and actually
keeps the flags we set earlier.

This fixes USB operation on boards which need to toggle the VBUS supply
via a GPIO, like the Teres-I laptop or the BananaPi M2 Berry board.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reported-by: Milan P. Stanić <mps@arvanta.net>
Reviewed-by: Samuel Holland <samuel@sholland.org>
2022-06-26 11:22:53 +01:00
Tom Rini
7596797085 Merge tag 'video-20220625' of https://source.denx.de/u-boot/custodians/u-boot-video
- fix building sandbox with NO_SDL=1
 - fix stb TrueType to check return value of STBTT_malloc()
 - remove not required DM_REGULATOR test in stm32 dsi driver
2022-06-25 08:38:00 -04:00
Patrick Delaunay
5bc6f8c2a9 video: stm32: remove test on CONFIG_DM_REGULATOR
The tests on CONFIG_DM_REGULATOR, added to avoid compilation issues, can
now be removed, they are no more needed since the commit 16cc5ad0b4
("power: regulator: add dummy helper").

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-06-25 08:18:42 +02:00
Bin Meng
5f71b2f105 driver: video: Check allocated pointers
The codes that call STBTT_malloc() / stbtt__new_active() do not check
the return value at present which may cause segfault.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2022-06-25 08:10:21 +02:00
Andrew Scull
c527e3f52d sandbox: sdl: Add stub sandbox_sdl_remove_display()
Building the sandbox with NO_SDL=1 resulted in an undefined reference to
'sandbox_sdl_remove_display'. Resolve this by adding a stub
implementation to match the stubs of the other similar functions.

Signed-off-by: Andrew Scull <ascull@google.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-06-25 07:54:20 +02:00
Tom Rini
625756083e Merge branch '2022-06-23-important-fixes'
- Apple NVMe updates to support macOS 13 changes, kontron-sl-mx8mm dts
  changes to fix some problems.
2022-06-23 11:27:04 -04:00
Frieder Schrempf
c0b71a1731 imx: kontron-sl-mx8mm: Remove deprecated phy-mode property
This was previously needed, but U-Boot is now capable of parsing
the new "phy-connection-type" property that is already used in
the main devicetree.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-06-23 08:25:02 -04:00
Frieder Schrempf
fecfe77c48 imx: kontron-sl-mx8mm: Sync dts files and fix ethernet
This syncs the devicetree files with the latest Linux kernel (5.19-rc2).
This also fixes the currently broken ethernet support:

Before:

  Net:   Could not get PHY for FEC0: addr 0

After:

  Net:   eth0: ethernet@30be0000

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-06-23 08:24:49 -04:00
Janne Grunau
942b54b4ee arm: apple: Increase RTKit timeouts
Timeouts are not expected to happen and are handled as fatal errors.
Increase all timeouts to 1 second as defensive measure to avoid relying
on the timing behaviour of certain firmware versions or configurations.

Signed-off-by: Janne Grunau <j@jannau.net>
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
Tested-by: Mark Kettenis <kettenis@openbsd.org>
2022-06-23 08:24:49 -04:00
Janne Grunau
a30f60ca0b MAINTAINERS: Add nvme_apple to Apple SoC section
Signed-off-by: Janne Grunau <j@jannau.net>
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
2022-06-23 08:24:49 -04:00
Janne Grunau
e44d59c6ad arm: apple: nvme: Add SART support and RTKit buffer management
The NVMe firmware in the macOS 13 beta blocks or crashes with u-boot's
current minimal RTKit implementation. It does not provide buffers for
the firmware's buffer requests. The ANS2 firmware included in macOS 11
and 12 tolerates this. The firmware included in the first macOS 13 beta
requires buffers for the crashlog and ioreport endpoints to function.

In the case of the NVMe the buffers are physical memory. Access to
physical memory is guarded by what Apple calls SART.
Import m1n1's SART driver (exclusively used for the NVMe controller).
Implement buffer management helpers for RTKit. These are generic since
other devices (none in u-boot so far) require different handling.

Signed-off-by: Janne Grunau <j@jannau.net>
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
Tested-by: Mark Kettenis <kettenis@openbsd.org>
2022-06-23 08:24:49 -04:00
Tom Rini
568a226f87 Prepare v2022.07-rc5
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-20 14:30:36 -04:00
Tom Rini
700cff2328 Merge tag 'efi-2022-07-rc5-2' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request for efi-2020-07-rc5-2

Documentation:

* man-pages for booti and printenv

UEFI

* correct return value for printenv -e command
* initialize console size late
2022-06-19 11:30:29 -04:00
Heinrich Schuchardt
68edbed454 efi_loader: initialize console size late
If CONFIG_VIDEO_DM=n we query the display size from the serial console.
Especially when using a remote console the response can be so late that
it interferes with autoboot.

Only query the console size when running an EFI binary.

Add debug output showing the determined console size.

Reported-by: Fabio Estevam <festevam@gmail.com>
Fixes: a57ad20d07 ("efi_loader: split efi_init_obj_list() into two stages")
Fixes: a9bf024b29 ("efi_loader: disk: a helper function to create efi_disk objects from udevice")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Tested-by: Fabio Estevam <festevam@denx.de>
Tested-by: Heiko Thiery <heiko.thiery@gmail.com>
2022-06-19 15:53:09 +02:00
Heinrich Schuchardt
e05bd68ed5 test: work around for EFI terminal size probing
When the UEFI sub-system is initialized it sends an escape sequence to the
serial console to determine the terminal size. This stops the
run_command_list() function of the console emulation from recognizing the
U-Boot command line prompt.

Add a 'print -e' command as first command in the command list to work
around this issue.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-06-19 15:53:09 +02:00
Heinrich Schuchardt
a872b18a0f cmd: correct return value for printenv -e
If printenv -e is executed and the specified variable is not found, the
return value $? of the command should be 1 (false).

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-06-19 15:53:09 +02:00
Heinrich Schuchardt
eaa268589e doc: man-page for the printenv command
Privide a man-page for the printenv command.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-06-19 15:53:09 +02:00
Heinrich Schuchardt
a8a349d743 doc: man-page for bootz command
Provide a man-page for the bootz command.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-06-19 15:53:09 +02:00
Tom Rini
aad77c215c Merge tag 'u-boot-stm32-20220617' of https://source.denx.de/u-boot/custodians/u-boot-stm
- Fix the stm32prog command for stm32mp platform
- Add stm32mp15x DHCOR based DRC Compact board
2022-06-17 09:41:11 -04:00
Tom Rini
f0843e0c0a Merge commit '32e0379143b433e29d76404f5f4c279067e48853' of https://github.com/tienfong/uboot_mainline 2022-06-17 09:35:28 -04:00
Tom Rini
ee4b80a6e2 Merge branch '2022-06-16-assorted-bugfixes'
- A wide array of regression fixes and minor updates
2022-06-17 09:13:50 -04:00
Dinesh Maniyam
32e0379143 ddr: altera: soc64: Integer fix overflow that caused DDR size mismatched
Convert the constant integer to 'phys_size_t' to avoid overflow
when calculating the SDRAM size.

Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2022-06-17 16:27:05 +08:00
Dinesh Maniyam
d192adafeb drivers: cache: ncore: Disable snoop filter
There is hardware bug in NCORE CCU IP and it is causing an issue in the
coherent directory tracking of outstanding cache lines.
The workaround is disabling snoop filter.

Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2022-06-17 16:27:05 +08:00
Dinesh Maniyam
5474fb894c arm: dts: socfpga: stratix10: Add freeze controller node
The freeze controller is required for FPGA partial reconfig.
This node is disable on default.
Enable this node via u-boot fdt command when needed.

Signed-off-by: Yau Wai Gan <yau.wai.gan@intel.com>
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2022-06-17 16:27:05 +08:00
Dinesh Maniyam
7f85330782 arm: dts: socfpga: agilex: Add freeze controller node
The freeze controller is required for FPGA partial reconfig.
This node is disable on default.
Enable this node via u-boot fdt command when needed.

Signed-off-by: Yau Wai Gan <yau.wai.gan@intel.com>
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2022-06-17 16:27:04 +08:00
Dinesh Maniyam
373c1428a0 arch: arm: socfpga: timer_s10: Override udelay for secure section
Override __udelay() as 'always inlined' function so that PSCI code
run in '__secure' section can call this delay function as well.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2022-06-17 16:26:52 +08:00
Marek Vasut
4f71c80b0d ARM: dts: stm32: Add DHCOR based DRC Compact board
Add DT for DH DRC Compact unit, which is a universal controller device.
The system has two ethernet ports, one CAN, RS485 and RS232, USB, uSD
card slot, eMMC and SDIO Wi-Fi.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-06-17 09:31:19 +02:00
Marek Vasut
cb6d857db2 ARM: dts: stm32: Add alternate pinmux for SPI2 pins
Add another mux option for SPI2 pins, this is used on DRC Compact board.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-06-17 09:31:19 +02:00
Marek Vasut
3577cc0632 ARM: dts: stm32: Add alternate pinmux for CAN1 pins
Add another mux option for CAN1 pins, this is used on DRC Compact board.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-06-17 09:31:19 +02:00
Marek Vasut
9b87f12953 ARM: dts: stm32: Add alternate pinmux for UART5 pins
Add another mux option for UART5 pins, this is used on DRC Compact board.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-06-17 09:31:18 +02:00
Marek Vasut
fb6284b5af ARM: dts: stm32: Add alternate pinmux for UART4 pins
Add another mux option for UART4 pins, this is used on DRC Compact board.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-06-17 09:31:18 +02:00
Marek Vasut
40beedb052 ARM: dts: stm32: Add alternate pinmux for UART3 pins
Add another mux option for UART3 pins, this is used on DRC Compact board.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-06-17 09:31:18 +02:00
Patrick Delaunay
8b91f28bc8 stm32mp: stm32prog: fix the last character of dfu_alt_add third parameter
The third parameter of dfu_alt_add(), the string description of alternate,
is build in stm32prog_alt_add() with a unnecessary character ';' at the
end of the string.

This separator was required in the first implementation of
dfu_alt_add() but is no more needed in the current implementation;
this separator is managed only in dfu_config_interfaces() which call
dfu_alt_add() for this parameter without this separator.

And since the commit 53b406369e ("DFU: Check the number of arguments
and argument string strictly"), this added character cause an error when
the stm32prog command is executed because the third parameter of
dfu_alt_add() must be a string with a numerical value; 's' must be NULL
in the result of call in dfu_fill_entity_mmc():
  third_arg = simple_strtoul(argv[2], &s, 0);

Fixes: 53b406369e ("DFU: Check the number of arguments and argument string strictly")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-06-17 09:30:19 +02:00
Marek Vasut
3c07d639ed net: Fix discuss discard typo
Replace discuss with discard, that is what happens with packet with
incorrect checksum. Fix the typo.

Fixes: 4b37fd146b ("Convert CONFIG_UDP_CHECKSUM to Kconfig")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
2022-06-16 18:51:07 -04:00
Peng Fan
7e41abad9b tools: binman: install btool
btool is needed after install binman to system.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2022-06-16 15:22:55 -04:00
Corentin LABBE
2f51f946e3 board: ti: am335x: eth_cpsw should depend on CONFIG_NET
The origin of this patch is the breaking of am335x-hs boot
due to commit e41651fffd ("dm: Support parent devices with of-platdata")
HS boards have less SRAM for SPL and so this commit increased memory usage beyond am335x limit.
This commit added 10 driver binding pass and am335x boot only if one pass is done.
SPL try to do more than one pass due to eth_cpsw failing.
Since HS SPL does not need network (and NET is already disabled in config),
the easiest fix is to "remove" eth_cpsw from SPL by testing if NET is enabled.

Signed-off-by: Corentin LABBE <clabbe@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Andrew Davis <afd@ti.com>
2022-06-16 15:22:55 -04:00
Andre Przywara
ce9c579e2b armv8: always use current exception level for TCR_ELx access
Currently get_tcr() takes an "el" parameter, to select the proper
version of the TCR_ELx system register.
This is problematic in case of the Apple M1, since it runs with
HCR_EL2.E2H fixed to 1, so TCR_EL2 is actually using the TCR_EL1 layout,
and we get the wrong version.

For U-Boot's purposes the only sensible choice here is the current
exception level, and indeed most callers treat it like that, so let's
remove that parameter and read the current EL inside the function.
This allows us to check for the E2H bit, and pretend it's EL1 in this
case.

There are two callers which don't care about the EL, and they pass 0,
which looks wrong, but is irrelevant in these two cases, since we don't
use the return value there. So the change cannot affect those two.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
Tested-by: Mark Kettenis <kettenis@openbsd.org>
2022-06-16 15:22:55 -04:00
Heiko Thiery
b11b5afa6a arm64: dts: imx8mq-kontron-pitx-imx8m-u-boot.dtsi: disable assigned clocks
With the move to use DM_CLK the boards uart stops working. The used
properties are not supported by the imx8mq clock driver. Thus
the correct baudrate cannot be selected. Remove this properties here and
the board can start with working uart. Keep it in the main dts because
linux handles these porperties fine.

Signed-off-by: Heiko Thiery <heiko.thiery@gmail.com>
2022-06-16 15:22:55 -04:00
Andre Przywara
81755b8c20 usb: host: ehci-generic: Make resets and clocks optional
The generic EHCI binding does not *require* resets and clocks
properties, and indeed for instance the Allwinner A20 SoCs does not
need or define any resets in its DT.

Don't easily give up if clk_get_bulk() or reset_get_bulk() return an
error, but check if that is due to the DT simply having no entries for
either of them.

This fixes USB operation on all boards with an Allwinner A10 or A20 SoC,
which were reporting an error after commit ba96176ab7:
=======================
Bus usb@1c14000: ehci_generic usb@1c14000: Failed to get resets (err=-2)
probe failed, error -2
=======================

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-06-16 15:22:55 -04:00
Miquel Raynal
2ac0baab4a fs/squashfs: sqfs_read: Prevent arbitrary code execution
Following Jincheng's report, an out-of-band write leading to arbitrary
code execution is possible because on one side the squashfs logic
accepts directory names up to 65535 bytes (u16), while U-Boot fs logic
accepts directory names up to 255 bytes long.

Prevent such an exploit from happening by capping directory name sizes
to 255. Use a define for this purpose so that developers can link the
limitation to its source and eventually kill it some day by dynamically
allocating this array (if ever desired).

Link: https://lore.kernel.org/all/CALO=DHFB+yBoXxVr5KcsK0iFdg+e7ywko4-e+72kjbcS8JBfPw@mail.gmail.com
Reported-by: Jincheng Wang <jc.w4ng@gmail.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Tested-by: Jincheng Wang <jc.w4ng@gmail.com>
2022-06-16 15:22:55 -04:00
Tom Rini
e744bf3a4b odroid_xu3: Fix board environment variable
When migrating CONFIG_CONS_INDEX to Kconfig, on this platform we changed
what "board" evaluated to in the environment.  This in turn meant that
we would no longer try and find the correct fdtfile via the normal
distro boot logic.  Fix this by overriding board in the default
environment, as done on other platforms where CONFIG_SYS_BOARD is not
what we want to be in the board environment variable.

Fixes: f76750d111 ("Convert CONFIG_CONS_INDEX et al to Kconfig")
Reported-by: Gabriel Hojda <ghojda@yo2urs.ro>
Tested-by: Gabriel Hojda <ghojda@yo2urs.ro>
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-16 15:22:55 -04:00
Andrey Zhizhikin
101a0f71e4 .gitignore: add files produced by b4
b4 utility [1] is introduced by Linux Kernel developers and used to
fetch patches and patch series from lore.kernel.org and is proven
to be useful for U-Boot development. Detailed usage of the tool can be
read under post from the original author [2].

This tool fetches files from the list and populates the source folder
with additional files (*.cover and *.mbx) which are not ignored by git
and shown as newly added files.

Add those file patterns into .gitignore file, so they can be safely
skipped during changes attestation.

Link: [1]: https://pypi.org/project/b4/
Link: [2]: https://people.kernel.org/monsieuricon/introducing-b4-and-patch-attestation
Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-06-16 15:22:55 -04:00
Christian Gmeiner
761157d310 arch: arm: mach-k3: am642_init: bring back MCU_PADCFG_MMR1 unlock
Without this register unlock it is not possible to configure the
pinmux used for mcu spi0.

Fixes: 92e46092f2 ("arch: arm: mach-k3: am642_init: Probe ESM nodes")
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
2022-06-16 15:22:54 -04:00
Christophe Leroy
48f44de8b4 Update email address and company name
This patch updates my email address and company name.

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
2022-06-16 15:22:54 -04:00
Stefan Roese
41b2182af7 crypto: fsl_hash: Remove unnecessary alignment check in caam_hash()
While working on an LX2160 based board and updating to latest mainline
I noticed problems using the HW accelerated hash functions on this
platform, when trying to boot a FIT Kernel image. Here the resulting
error message:

   Using 'conf-freescale_lx2160a.dtb' configuration
   Trying 'kernel-1' kernel subimage
   Verifying Hash Integrity ... sha256Error: Address arguments are not aligned
CAAM was not setup properly or it is faulty
 error!
Bad hash value for 'hash-1' hash node in 'kernel-1' image node
Bad Data Hash
ERROR: can't get kernel image!

Testing and checking with Gaurav Jain from NXP has revealed, that this
alignment check is not necessary here at all. So let's remove this
check completely.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Gaurav Jain <gaurav.jain@nxp.com>
Cc: dullfire@yahoo.com
Reviewed-by: Gaurav Jain <gaurav.jain@nxp.com>
2022-06-16 15:22:54 -04:00
Tom Rini
9abfbef57f Merge tag 'u-boot-imx-20220616' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
u-boot-imx-20220616
-------------------

Fixes for 2022.07 + Toradex apalis-imx8 (missed in last PR)

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/12322
2022-06-16 08:38:46 -04:00
Marek Vasut
163863d572 arm: socfpga: vining: Unmount UBIFS and detach UBI in ubi_load script
Clean up in ubiload script. Unmount UBIFS from which kernel image was
loaded and detach UBI on which the UBIFS is located, otherwise message
similar to the following is printed just before booting kernel:

Removing MTD device #7 (rootfs) with use count 1
Error when deleting partition "rootfs" (-16)

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Tien Fong Chee  <tien.fong.chee@intel.com>
2022-06-16 16:11:06 +08:00
Tien Fong Chee
39bbcc341b ddr: altera: Stratix10: Use phys_size_t for memory size
Replace with phys_size_t for all memory size variables declaration
for the sake of scalability. phys_size_t is defined in
/arch/arm/include/asm/types.h.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2022-06-16 16:10:58 +08:00
Tien Fong Chee
ee06c5390f ddr: altera: Ignore bit[7-4] for both seq2core & core2seq handshake in HPS
Bit[7-4] for both register seq2core and core2seq handshake in HPS are not
required for triggering DDR re-calibration or resetting EMIF. So, ignoring
these bits just for playing it safe.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2022-06-16 16:10:44 +08:00
Yau Wai Gan
f70e00fa7d arm: dts: socfpga: stratix10: Update MMC smplsel value
This new MMC sample select value is obtained from running
tests on multiple Stratix 10 boards and proven working.

Signed-off-by: Yau Wai Gan <yau.wai.gan@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2022-06-16 16:02:26 +08:00
Tom Rini
fd27812e52 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-pmic 2022-06-15 23:11:30 -04:00
Tom Rini
488d30a1e9 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-mmc 2022-06-15 23:10:17 -04:00
Tien Fong Chee
166e5b82a3 intel: n5x: ddr: update license
All the source code of sdram_n5x.c are from Intel, update the license to
use both GPL2.0 and BSD-3 Clause because this copy of code may used for
open source and internal project.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2022-06-15 17:48:22 +08:00
Marek Vasut
1a558fafbb spi: nxp_fspi: Fix clock imbalance
The nxp_fspi_default_setup() is only ever called from nxp_fspi_probe(),
where the IP clock are initially disabled. Drop the second disabling of
clock to prevent clock enable/disable imbalance reported by clock core:

"
clk qspi_root_clk already disabled
"

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-06-15 11:34:38 +02:00
Loic Poulain
12a29d3b85 mmc: fsl_esdhc_imx: Implement wait_dat0 mmc ops
Implement wait_dat0 mmc ops callbac, allowing to reduce SPL boot time.

Before (using grabserial):
[0.000001 0.000001] U-Boot SPL 2021.04-xxxx
[0.028257 0.028257] DDRINFO: start DRAM init
[0.028500 0.000243] DDRINFO: DRAM rate 3000MTS
[0.304627 0.276127] DDRINFO:ddrphy calibration done
[0.305647 0.001020] DDRINFO: ddrmix config done
[0.352584 0.046937] SEC0:  RNG instantiated
[0.374299 0.021715] Normal Boot
[0.374675 0.000376] Trying to boot from MMC2
[1.250580 0.875905] NOTICE:  BL31: v2.4(release):lf-5.10.72-2.2.0-0-g5782363f9
[1.251985 0.001405] NOTICE:  BL31: Built : 08:02:40, Apr 12 2022
[1.522560 0.270575]
[1.522734 0.000174]
[1.522788 0.000054] U-Boot 2021.04-xxxx

After:
[0.000001 0.000001] U-Boot SPL 2021.04-xxxx
[0.001614 0.001614] DDRINFO: start DRAM init
[0.002377 0.000763] DDRINFO: DRAM rate 3000MTS
[0.278494 0.276117] DDRINFO:ddrphy calibration done
[0.279266 0.000772] DDRINFO: ddrmix config done
[0.338432 0.059166] SEC0:  RNG instantiated
[0.339051 0.000619] Normal Boot
[0.339431 0.000380] Trying to boot from MMC2
[0.412587 0.073156] NOTICE:  BL31: v2.4(release):lf-5.15.5-1.0.0-0-g05f788b
[0.414191 0.001604] NOTICE:  BL31: Built : 10:35:26, Apr  6 2022
[0.700685 0.286494]
[0.700793 0.000108]
[0.700845 0.000052] U-Boot 2021.04-xxxx

Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-06-15 15:39:59 +09:00
Loic Poulain
d6ad5a0af9 mmc: Add support for wait_dat0 callback
There is no wait_dat0 mmc ops, causing operations waiting for data
line state change (e.g mmc_switch_voltage) to fallback to a 250ms
active delay. mmc_ops still used when DM_MMC is not enabled, which
is often the case for SPL. The result can be unexpectly long SPL
boot time.

This change adds support for wait_dat0() mmc operation.

Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-06-15 15:39:56 +09:00
Patrick Delaunay
d72267049b env: mmc : align erase address and size on erase_grp_size
On eMMC device, the erase_grp_size > 1 so the address and size for the
erase block command in env/mmc.c can be unaligned on erase group size and
some strange trace occurs and the result is not guarantee by MMC devices.

The SD-Card behavior doesn't change as erase_grp_size = 1 for SD-Card.

For example, on eMMC present on STM32MP15C-EV1 and before the patch:

  STM32MP> env erase

  Erasing Environment on MMC...

  Caution! Your devices Erase group is 0x400
  The erase range would be change to 0x2000~0x27ff

  16 blocks erased: OK

  Caution! Your devices Erase group is 0x400
  The erase range would be change to 0x2000~0x23ff

  16 blocks erased: OK
  OK

After this patch:
  STM32MP> env erase
  Erasing Environment on MMC...
  1024 blocks erased at 0x2000: OK
  1024 blocks erased at 0x2000: OK
  OK

Here the 2 copies of U-Boot environment are in the same devices Erase
group: it is erased twice.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-06-15 15:34:18 +09:00
Patrick Delaunay
212875e707 mmc: fix error message for unaligned erase request
Fix the end address in the message for unaligned erase request in
mmc_berase() when start + blkcnt is aligned to erase_grp_size.

for example:
  - start = 0x2000 - 26
  - count = 26
  - erase_grp_size = 0x400

  Caution! Your devices Erase group is 0x400
  The erase range would be change to 0x2000~0x27ff

But no issue when the end address is not aligned, for example
  - start = 0x2000 - 2 * 26
  - count = 26
  - erase_grp_size = 0x400

  Caution! Your devices Erase group is 0x400
  The erase range would be change to 0x2000~0x23ff

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-06-15 15:34:18 +09:00
Gaurav Jain
66e54716cf secure boot: enable ARCH_MISC_INIT config.
add ARCH_MISC_INIT to initilaize caam jr driver.

Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-06-14 21:25:26 +02:00
Andrey Zhizhikin
65d5931d02 clk: imx8mp: use usb_core_ref for usb_root_clk
Upstream commit 7a2c3be95a ("clk: imx8mp: Fill in DWC3 USB, USB PHY,
HSIOMIX clock") added usb_core_ref for USB Controller but never set it
to be used as a clock source, using rather "osc_32k" instead.

This produces following boot log message:
"clk_register: failed to get osc_32k device (parent of usb_root_clk)"

Fix the USB controller clock source by using usb_core_ref instead of
osc_32k.

Fixes: 7a2c3be95a ("clk: imx8mp: Fill in DWC3 USB, USB PHY, HSIOMIX clock")
Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-06-14 21:25:26 +02:00
Andrey Zhizhikin
698c0411cf clk: imx8mp: fix root clock names for ecspi
Root clock name contained underscore, which does not match to the actual
clock name.

Correct the name to match what is present in the FDT.

Fixes: 87f958810f ("clk: imx8mp: Add ECSPI clocks")
Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: uboot-imx <uboot-imx@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-06-14 21:25:26 +02:00
Philippe Schenker
a3f2dcf8f4 verdin-imx8mm, verdin-imx8mp: Fix default systemd console output
systemd prints its messages on the last console= statement that it finds
in the kernel arguments. The current ordering sends the systemd messages
to tty1, by default this is the display.

Ensure that systemd sends its messages to the default UART, reorder the
console= statements accordingly.

Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-06-14 21:25:26 +02:00
Josua Mayer
815216187e mx6cuboxi: enable driver for adin1300 phy
Since SoMs revision 1.9 the ar8035 phy has been replaced by adin1300.
Enable the driver so that the new SoMs have functional networking.

Signed-off-by: Josua Mayer <josua@solid-run.com>
2022-06-14 21:25:26 +02:00
Josua Mayer
741ce3084e mx6cuboxi: fixup dtb ethernet phy nodes before booting an OS
SoM revision 1.9 has replaced the ar8035 phy address 0 with an adin1300
at address 1. Because early SoMs had a hardware flaw, the ar8035 can
also appear at address 4 - making it a total of 3 phy nodes in the DTB.

To avoid confusing Linux with probe errors, fixup the dtb to only enable
the phy node that is detected at runtime.

Signed-off-by: Josua Mayer <josua@solid-run.com>
2022-06-14 21:25:26 +02:00
Josua Mayer
17baba4682 ARM: dts: imx6qdl-sr-som: add support for alternate phy addresses
The Cubox has an unstable phy address - which can appear at either
address 0 (intended) or 4 (unintended).

SoM revision 1.9 has replaced the ar8035 phy with an adin1300, which
will always appear at address 1.

Change the reg property of the phy node to the magic value 0xffffffff,
which indicates to the generic phy driver that all addresses should be
probed. That allows the same node (which is pinned by phy-handle) to match
either the AR8035 PHY at both possible addresses, as well as the new one
at address 1.
Also add the new adi,phy-output-clock property for enabling the 125MHz
clock used by the fec ethernet controller, as submitted to Linux [1].

Linux solves this problem differently:
For the ar8035 phy it will probe both phy nodes in device-tree in order,
and use the one that succeeds. For the new adin1300 it expects U-Boot to
patch the status field in the DTB before booting

While at it also sync the reset-delay with the upstream Linux dtb.

[1] https://patchwork.kernel.org/project/netdevbpf/patch/20220428082848.12191-4-josua@solid-run.com/

Signed-off-by: Josua Mayer <josua@solid-run.com>
2022-06-14 21:25:26 +02:00
Josua Mayer
54337abb14 phy: adin: add support for clock output
The ADIN1300 supports generating certain clocks on its GP_CLK pin, as
well as providing the reference clock on CLK25_REF.

Add support for selecting the clock via device-tree properties.

This patch is based on the Linux implementation for this feature,
which has been added to netdev/net-next.git [1].

[2] https://patchwork.kernel.org/project/netdevbpf/cover/20220517085143.3749-1-josua@solid-run.com/

Signed-off-by: Josua Mayer <josua@solid-run.com>
2022-06-14 21:25:26 +02:00
Nate Drude
4cc25cd5ce phy: adin: fix broken support for adi, phy-mode-override
Currently, the adin driver fails to compile.

The original patch introducing the adin driver used the function
phy_get_interface_by_name to support the adi,phy-mode-override
property. Unfortunately, a few days before the adin patch
was accepted, another patch removed support for phy_get_interface_by_name:

123ca114e0

This patch refactors adin_get_phy_mode_override, implementing the logic in
the new function, ofnode_read_phy_mode, from the patch above.

Signed-off-by: Nate Drude <nate.d@variscite.com>
Tested-by: Josua Mayer <josua@solid-run.com>
Signed-off-by: Josua Mayer <josua@solid-run.com>
2022-06-14 21:25:26 +02:00
Fabio Estevam
827ded0e82 imx8mn_evk: Add Ethernet support to the LPDDR4 variant
The imx8mn-ddr4-evk board has Ethernet support already, but the
lpddr4 board does not.

Add Ethernet support for the LPDDR4 variant too.

Signed-off-by: Fabio Estevam <festevam@denx.de>
2022-06-14 21:25:26 +02:00
Philippe Schenker
0da8dde634 board: apalis-imx8: add new 8gb product variant
Add the new Apalis iMX8 product variant

0067: Apalis iMX8 QuadMax 8GB Wi-Fi / BT IT

the only difference to the product

0037 Apalis iMX8 QuadMax 4GB Wi-Fi / BT IT

is the 8gb of RAM. Toradex strategy to choose the correct RAM timing in
SCFW is by fuses in the user area telling which RAM timing to load.

This commit makes use of this information to set the correct size of
the RAM and therefore distinguish between the new 0067 and 0037 product

Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-06-14 21:25:26 +02:00
Philippe Schenker
4941035143 toradex: tdx-cfg-block: add new 8gb apalis-imx8
0067: Apalis iMX8 QuadMax 8GB Wi-Fi / BT IT

This module is identical to its 4GB counterpart
0037: Apalis iMX8 QuadMax 4GB Wi-Fi / BT IT
except for the RAM size.

Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-06-14 21:25:26 +02:00
Fabio Estevam
e104a9f8eb imx8mn_evk: Add the missing spl.bin entry
The generated flash.bin does not boot the imx8mn evk LPDDR4 variant
as it misses the spl.bin description in binman.

Add its entry to fix the boot on the imx8mn evk LPDDR4 variant.

Signed-off-by: Fabio Estevam <festevam@denx.de>
Tested-by: Arti Zirk <art@zirk.me>
Reviewed-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2022-06-14 21:25:26 +02:00
Tom Rini
c18e5fb055 dtoc: Update test_src_scan.py for new tegra compatibles
This test was written to match up with the list of compatibles in
drivers/i2c/tegra_i2c.c so adding another one requires the test to be
updated to match.

Fixes: 0d2105ae5e ("arm: tegra: Update some DT compatibles")
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-14 13:59:23 -04:00
Tom Rini
c1d9020cc7 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-tegra
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-14 12:59:12 -04:00
Rasmus Villemoes
752bea3ca4 pmic: pca9450: add DM_I2C dependencies in Kconfig
The pca9450 driver uses dm_i2c_{read,write}, which
are (unsurprisingly) only available with DM_I2C. Make sure one can't
create an unbuildable .config by adding proper dependencies.

While here, append "in SPL" to the prompt for the SPL_ variant so it
doesn't read the same as the one for the non-SPL_ variant.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-06-14 11:20:50 +09:00
Marcel Ziswiler
8f27bf114e board: apalis_t30/tk1/colibri_t20/t30: integrate mac address via dt
Use device tree to set MAC address of the Ethernet chip.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2022-06-13 15:31:15 -07:00
Peter Robinson
0d2105ae5e arm: tegra: Update some DT compatibles
Some of the DT compatibles have changed upstream so add new DT compatibles
to ensure things continue to keep working if the device trees are
updated.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2022-06-13 15:31:10 -07:00
Peter Robinson
b5cf255f73 pci: tegra: Update error prints with new lines
Add new lines to make errorr messages easier to read.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2022-06-13 15:31:00 -07:00
Peter Robinson
5b060e465e ARM: tegra: XUSB padctl: Add new lines for errors
Add new lines for error messages to make them easier to read.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2022-06-13 15:31:00 -07:00
Tom Rini
92a8bc6b41 Merge tag 'efi-2022-07-rc5' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request for efi-2022-07-rc5

UEFI:

* Ignore OsIndications if CONFIG_EFI_IGNORE_OSINDICATIONS=y
* Correct UEFI default binary name
* Let efidebug create boot options without file path
* Support booting with a boot option with shortened device only device path
2022-06-13 09:33:37 -04:00
Heinrich Schuchardt
72fa9cd59e efi_loader: create boot options without file path
Allow the efidebug command to create boot options without file path, e.g.

    efidebug boot add -b 0001 'short dev only' host 0:1 ''
    efidebug boot add -B 0002 'long dev only' host 0:1 ''

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2022-06-12 13:02:34 +02:00
Heinrich Schuchardt
178667b34b efi_loader: allow booting from short dev only DP
Allow booting from a short form device-path without file path, e.g.

    /HD(1,GPT,5ef79931-a1aa-4c70-9d67-611e8f69eafd,0x800,0x1000)

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2022-06-12 09:17:54 +02:00
Heinrich Schuchardt
3a0654ecd0 efi_loader: correctly identify binary name
Only on the sandbox the default EFI binary name (e.g. BOOTX64.EFI) must
match the host architecture.

In all other cases we must use the target architecture.

Use #elif where appropriate.

Reported-by: Vagrant Cascadian <vagrant@reproducible-builds.org>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-06-12 09:17:54 +02:00
Sughosh Ganu
556a12654a EFI: FMP: Use a common GetImageInfo function for FIT and raw images
The GetImageInfo function definitions for the FIT images and raw
images are the same. Use a common function for the both the Firmware
Management Protocol(FMP) instances for raw and FIT images.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-06-12 09:17:54 +02:00
Sughosh Ganu
119fafdefb EFI: Do not consider OsIndications variable if CONFIG_EFI_IGNORE_OSINDICATIONS is enabled
The EFI_IGNORE_OSINDICATIONS config symbol was introduced as a
mechanism to have capsule updates work even on platforms where the
SetVariable runtime service was not supported. The current logic
requires the OsIndications variable to have been set to a 64 bit value
even when the EFI_IGNORE_OSINDICATIONS config is enabled. Return an
error code on not being able to read the variable only when
EFI_IGNORE_OSINDICATIONS is not enabled.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-06-12 09:17:54 +02:00
Tom Rini
57bd363de7 Merge https://source.denx.de/u-boot/custodians/u-boot-usb
- MediaTek XHCI bugfix, add  USB251xB/xBi driver
2022-06-08 08:25:30 -04:00
Marek Vasut
02544db9a7 misc: Port USB251xB/xBi Hi-Speed Hub Controller Driver from Linux
This patch adds a driver for configuration of the Microchip USB251xB/xBi
USB 2.0 hub controller series with USB 2.0 upstream connectivity, SMBus
configuration interface and two to four USB 2.0 downstream ports.

This is ported from Linux as of Linux kernel commit
5c2b9c61ae5d8 ("usb: usb251xb: add boost-up property support")

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Simon Glass <sjg@chromium.org>
2022-06-07 16:14:20 +02:00
Tom Rini
6530de23e9 Merge https://source.denx.de/u-boot/custodians/u-boot-watchdog
- Fix SPL build with watchdog disabled in asm files (Pali)
2022-06-07 08:17:24 -04:00
Tom Rini
d9ad48464c Merge tag 'xilinx-for-v2022.07-rc4-v2' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2022.07-rc4-v2

- Fix revision name (remove spaces)
2022-06-07 08:17:08 -04:00
Chunfeng Yun
fe8e8af36c usb: xhci-mtk: disable all ports when disable host controller
This is used to avoid the ports status of IPPC being brought in kernel
stage, it may cause ports error especially when the xhci controller is
a component of dual-role controller.

Reported-by: Yun-Chien Yu <yun-chien.yu@mediatek.com>
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
2022-06-07 09:55:57 +02:00
Pali Rohár
06ceff70bf watchdog: Fix SPL build with watchdog disabled in asm files
Allow to compile assembler files in SPL build which calls WATCHDOG_RESET
function when watchdog is disabled in SPL and enabled in U-Boot proper.

This issue was fixed in past by commit 7fbd42f5af ("watchdog: Handle SPL
build with watchdog disabled") for C source files, but not for assembler
source files.

Currently the only assembler source file which calls WATCHDOG_RESET is
arch/powerpc/lib/ticks.S, so this patch affects and fixes powerpc SPL
builds.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-06-07 08:45:35 +02:00
Tom Rini
8f527342db Prepare v2022.07-rc4
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-06 10:25:13 -04:00
Camelia Groza
380e32b171 configs: fsl: add missing SYS_FMAN_FW_ADDR defines
Two defconfigs were missed when transitioning the SYS_FMAN_FW_ADDR
symbol to Kconfig. CONFIG_SYS_FMAN_FW_ADDR is currently initialized to
0 by default on these builds, which prevents the firmware from loading.

Add the correct symbols to these defconfigs.

Fixes: a97a071d10 ("configs: fsl: migrate FMAN/QE specific defines to Kconfig")
Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
2022-06-06 10:20:09 -04:00
Patrick Delaunay
660d74278f doc: update mail author for st-dt.rst
Update author email address with the one dedicated to
upstream activities.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-06-06 10:20:04 -04:00
Michal Simek
93216276f5 xilinx: fru: Replace spaces with \0 in detected revision
Also fix board revision field where spaces are used instead of \0.
The same change was done for board name by commit 530560b6f8 ("xilinx:
fru: Replace spaces with \0 in detected name").

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/e069e5134e57899e859786ad8ba48721df6df752.1653911444.git.michal.simek@amd.com
2022-06-06 09:32:26 +02:00
Tom Rini
0f259fe79d Merge tag 'efi-2022-07-rc4-4' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request for efi-2022-07-rc4-4

UEFI:

* Fix the implementation of the firmware management protocol
* Fix the unit tests for signed update capsules
2022-06-04 09:38:56 -04:00
Vincent Stehlé
8645aefc8b efi: test/py: authenticate fit capsules
Add support for the authentication of UEFI capsules containing FIT images.

The authentication code is moved out of the function handling raw images
into a new function efi_firmware_capsule_authenticate(). The special case
for the FMP header coming from edk2 tools is preserved. There is no
functional change for capsules containing raw images.

The python test for signed capsules with raw images is renamed with no
functional change and a new test is added for signed capsules containing
FIT images.

This can be tested with sandbox64_defconfig or sandbox_flattree_defconfig,
plus CONFIG_EFI_CAPSULE_AUTHENTICATE=y.

Signed-off-by: Vincent Stehlé <vincent.stehle@arm.com>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
2022-06-04 08:43:55 +02:00
Vincent Stehlé
82b3f4cb46 test/py: efi_capsule: repair image authentication test
Repair the python tests for authenticated EFI capsules, which can be run
with sandbox_defconfig plus CONFIG_EFI_CAPSULE_AUTHENTICATE=y.

- Account for the reset changes done by commit 3e6f810006 ("efi_loader:
  test/py: Reset system after capsule update on disk").
- Fix the capsule GUID typo introduced by commit 2e9c3c6965 ("test:
  capsule: Modify the capsule tests to use GUID values for sandbox").

Signed-off-by: Vincent Stehlé <vincent.stehle@arm.com>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
2022-06-04 08:43:55 +02:00
Sughosh Ganu
aad7f1ad60 EFI: Update the documentation to reflect the correct value of OsIndications
The OsIndications is a 64 bit variable, and the current code expects
the value of the variable to be 64 bit. Update the documentation to
reflect this fact.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-06-04 08:43:55 +02:00
Sughosh Ganu
6a463bc1c9 EFI: Populate descriptor_count value only when image_info_size is not zero
The GetImageInfo function of the Firmware Mangement Protocol(FMP) gets
called initially to query the size of the image descriptor array that
would have to be allocated. During this call, the rest of the function
arguments, specifically pointers might be passed as NULL. Do not
populate the descriptor_count value before it is known that the call
to GetImageInfo has been made with the allocated buffer for the image
descriptors.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-06-04 08:43:55 +02:00
Chris Packham
f1533c41a7 doc: environment: Fix typo
"valu" should be "value".

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-06-04 08:43:55 +02:00
Tom Rini
90189ecd59 Merge branch '2022-06-03-assorted-fixes'
- armv8 TCR write bugfix, ubifs bugfix, imx8mq clk bugfixes, two network
  fixes, Add U-Boot version to chosen node, update TI AM64x board
  maintainers
2022-06-03 15:42:13 -04:00
Dave Gerlach
c30f6d62f0 board: ti: am64x: Update MAINTAINERS
Move maintainership of TI AM64x boards to Vignesh.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2022-06-03 15:42:05 -04:00
Pali Rohár
9320db0926 squashfs: Fix compilation on big endian systems
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
2022-06-03 11:15:24 -04:00
Peng Fan
ad9f3771f6 imx: imx8mq: select CONFIG_CMD_CLK
select CONFIG_CMD_CLK to enable dump clk in uboot shell

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-06-03 11:15:24 -04:00
Peng Fan
4230d68aa8 imx: imx8mq: default select CLK_IMX8MQ
Since the power domain driver default select CONFIG_CLK, so we will
meet lots failures without CLK_IMX8MQ, so default select it.

Fixes: commit 4eb82c2e56 ("imx: power-domain: Get rid of SMCCC dependency")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-06-03 11:15:24 -04:00
Francesco Dolcini
622ecee93a fdt: Add U-Boot version to chosen node
Add a new device tree property "u-boot,version" in the chosen node to
pass the U-Boot version to the operating system.
This can be useful to implement a firmware upgrade procedure from the
operating system.

Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-06-03 11:15:24 -04:00
Fabio Estevam
b85d130ea0 net: Check for the minimum IP fragmented datagram size
Nicolas Bidron and Nicolas Guigo reported the two bugs below:

"
----------BUG 1----------

In compiled versions of U-Boot that define CONFIG_IP_DEFRAG, a value of
`ip->ip_len` (IP packet header's Total Length) higher than `IP_HDR_SIZE`
and strictly lower than `IP_HDR_SIZE+8` will lead to a value for `len`
comprised between `0` and `7`. This will ultimately result in a
truncated division by `8` resulting value of `0` forcing the hole
metadata and fragment to point to the same location. The subsequent
memcopy will overwrite the hole metadata with the fragment data. Through
a second fragment, this can be exploited to write to an arbitrary offset
controlled by that overwritten hole metadata value.

This bug is only exploitable locally as it requires crafting two packets
the first of which would most likely be dropped through routing due to
its unexpectedly low Total Length. However, this bug can potentially be
exploited to root linux based embedded devices locally.

```C
static struct ip_udp_hdr *__net_defragment(struct ip_udp_hdr *ip, int *lenp)
{
     static uchar pkt_buff[IP_PKTSIZE] __aligned(PKTALIGN);
     static u16 first_hole, total_len;
     struct hole *payload, *thisfrag, *h, *newh;
     struct ip_udp_hdr *localip = (struct ip_udp_hdr *)pkt_buff;
     uchar *indata = (uchar *)ip;
     int offset8, start, len, done = 0;
     u16 ip_off = ntohs(ip->ip_off);

     /* payload starts after IP header, this fragment is in there */
     payload = (struct hole *)(pkt_buff + IP_HDR_SIZE);
     offset8 =  (ip_off & IP_OFFS);
     thisfrag = payload + offset8;
     start = offset8 * 8;
     len = ntohs(ip->ip_len) - IP_HDR_SIZE;
```

The last line of the previous excerpt from `u-boot/net/net.c` shows how
the attacker can control the value of `len` to be strictly lower than
`8` by issuing a packet with `ip_len` between `21` and `27`
(`IP_HDR_SIZE` has a value of `20`).

Also note that `offset8` here is `0` which leads to `thisfrag = payload`.

```C
     } else if (h >= thisfrag) {
         /* overlaps with initial part of the hole: move this hole */
         newh = thisfrag + (len / 8);
         *newh = *h;
         h = newh;
         if (h->next_hole)
             payload[h->next_hole].prev_hole = (h - payload);
         if (h->prev_hole)
             payload[h->prev_hole].next_hole = (h - payload);
         else
             first_hole = (h - payload);

     } else {
```

Lower down the same function, execution reaches the above code path.
Here, `len / 8` evaluates to `0` leading to `newh = thisfrag`. Also note
that `first_hole` here is `0` since `h` and `payload` point to the same
location.

```C
     /* finally copy this fragment and possibly return whole packet */
     memcpy((uchar *)thisfrag, indata + IP_HDR_SIZE, len);
```

Finally, in the above excerpt the `memcpy` overwrites the hole metadata
since `thisfrag` and `h` both point to the same location. The hole
metadata is effectively overwritten with arbitrary data from the
fragmented IP packet data. If `len` was crafted to be `6`, `last_byte`,
`next_hole`, and `prev_hole` of the `first_hole` can be controlled by
the attacker.

Finally the arbitrary offset write occurs through a second fragment that
only needs to be crafted to write data in the hole pointed to by the
previously controlled hole metadata (`next_hole`) from the first packet.

 ### Recommendation

Handle cases where `len` is strictly lower than 8 by preventing the
overwrite of the hole metadata during the memcpy of the fragment. This
could be achieved by either:
* Moving the location where the hole metadata is stored when `len` is
lower than `8`.
* Or outright rejecting fragmented IP datagram with a Total Length
(`ip_len`) lower than 28 bytes which is the minimum valid fragmented IP
datagram size (as defined as the minimum fragment of 8 octets in the IP
Specification Document:
[RFC791](https://datatracker.ietf.org/doc/html/rfc791) page 25).

----------BUG 2----------

In compiled versions of U-Boot that define CONFIG_IP_DEFRAG, a value of
`ip->ip_len` (IP packet header's Total Length) lower than `IP_HDR_SIZE`
will lead to a negative value for `len` which will ultimately result in
a buffer overflow during the subsequent `memcpy` that uses `len` as it's
`count` parameter.

This bug is only exploitable on local ethernet as it requires crafting
an invalid packet to include an unexpected `ip_len` value in the IP UDP
header that's lower than the minimum accepted Total Length of a packet
(21 as defined in the IP Specification Document:
[RFC791](https://datatracker.ietf.org/doc/html/rfc791)). Such packet
would in all likelihood be dropped while being routed to its final
destination through most routing equipment and as such requires the
attacker to be in a local position in order to be exploited.

```C
static struct ip_udp_hdr *__net_defragment(struct ip_udp_hdr *ip, int *lenp)
{
     static uchar pkt_buff[IP_PKTSIZE] __aligned(PKTALIGN);
     static u16 first_hole, total_len;
     struct hole *payload, *thisfrag, *h, *newh;
     struct ip_udp_hdr *localip = (struct ip_udp_hdr *)pkt_buff;
     uchar *indata = (uchar *)ip;
     int offset8, start, len, done = 0;
     u16 ip_off = ntohs(ip->ip_off);

     /* payload starts after IP header, this fragment is in there */
     payload = (struct hole *)(pkt_buff + IP_HDR_SIZE);
     offset8 =  (ip_off & IP_OFFS);
     thisfrag = payload + offset8;
     start = offset8 * 8;
     len = ntohs(ip->ip_len) - IP_HDR_SIZE;
```

The last line of the previous excerpt from `u-boot/net/net.c` shows
where the underflow to a negative `len` value occurs if `ip_len` is set
to a value strictly lower than 20 (`IP_HDR_SIZE` being 20). Also note
that in the above excerpt the `pkt_buff` buffer has a size of
`CONFIG_NET_MAXDEFRAG` which defaults to 16 KB but can range from 1KB to
64 KB depending on configurations.

```C
     /* finally copy this fragment and possibly return whole packet */
     memcpy((uchar *)thisfrag, indata + IP_HDR_SIZE, len);
```

In the above excerpt the `memcpy` overflows the destination by
attempting to make a copy of nearly 4 gigabytes in a buffer that's
designed to hold `CONFIG_NET_MAXDEFRAG` bytes at most which leads to a DoS.

 ### Recommendation

Stop processing of the packet if `ip_len` is lower than 21 (as defined
by the minimum length of a data carrying datagram in the IP
Specification Document:
[RFC791](https://datatracker.ietf.org/doc/html/rfc791) page 34)."

Add a check for ip_len lesser than 28 and stop processing the packet
in this case.

Such a check covers the two reported bugs.

Reported-by: Nicolas Bidron <nicolas.bidron@nccgroup.com>
Signed-off-by: Fabio Estevam <festevam@denx.de>
2022-06-03 11:15:24 -04:00
Andre Przywara
2b641211c5 armv8: Fix TCR 64-bit writes
The AArch64 TCR_ELx register is a 64-bit register, and many newer
architecture features use bits in the upper half. So far U-Boot was
igorant of those bits, trying to leave them alone.
However, in an effort to set bit 31 to 1, it failed doing so, because
the compiler sign-extended "1 << 31", so that all bits[63:31] got set.

Older ARMv8.0 cores don't define anything dangerous up there, but newer
architecture revisions do, and setting all those bits will end badly:
=================
$ qemu-system-aarch64 -cpu max ....
U-Boot 2022.07-rc1 (May 09 2022 - 15:21:00 +0100)

DRAM:  1.5 GiB
=================  (hangs here)

Defining TCR_ELx_RSVD to "1U << 31" avoids the sign-extension, so all
upper bits stay at a safe 0 value. This means no more surprises when
U-Boot runs on a more capable CPU core.

Reported-by: Balaji Anandapadmanaban <Balaji.Anandapadmanaban@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Peter Collingbourne <pcc@google.com>
Reviewed-by: Peter Collingbourne <pcc@google.com>
2022-06-03 11:15:24 -04:00
Michael Walle
7704b7fd67 net: enetc: unregister mdiobus
If the device fails to probe - for example, when there is no
ethaddr set - then the private data is automatically freed
but the mdiobus remains registered.

Fixes: 1e354cb393 ("drivers: net: fsl_enetc: register internal MDIO bus")
Signed-off-by: Michael Walle <michael@walle.cc>
2022-06-03 11:15:24 -04:00
Pali Rohár
339f652992 ubifs: Fix lockup/crash when reading files
Commit b1a14f8a1c ("UBIFS: Change ubifsload to not read beyond the
requested size") added optimization to do not read more bytes than it is
really needed. But this commit introduced incorrect handling of the hole at
the end of file. This logic cause U-Boot to crash or lockup when trying to
read from the ubifs filesystem.

When read_block() call returns -ENOENT error (not an error, but the hole)
then dn-> structure is not filled and contain garbage. So using of dn->size
for memcpy() argument cause that U-Boot tries to copy unspecified amount of
bytes from possible unmapped memory. Which randomly cause lockup of P2020
CPU.

Fix this issue by copying UBIFS_BLOCK_SIZE bytes from read buffer when
dn->size is not available. UBIFS_BLOCK_SIZE is the size of the buffer
itself and read_block() fills buffer by zeros when it returns -ENOENT.

This patch fixes ubifsload on P2020.

Fixes: b1a14f8a1c ("UBIFS: Change ubifsload to not read beyond the requested size")
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-06-03 10:23:22 -04:00
Tom Rini
3053b78146 Merge tag 'efi-2022-07-rc4-3' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request for efi-2022-07-rc4-3

UEFI:

* fix a problem in loading an image from a short-path
* fix building the bootmenu command for CONFIG_EFI_LOADER=n
* correct the bootefi command syntax
* add firmware management protocol to the documentation

Others:

* bootmenu: fix bootmenu title handling

Tested-by: Pali Rohár <pali@kernel.org> [n900, for bootmenu working as before]
2022-05-31 13:05:53 -04:00
Masahisa Kojima
e85727ddb6 bootmenu: use utf-8 for menu title
The commit a3d0aa87ac ("bootmenu: update bootmenu_entry structure")
changes the bootmenu title type from char to u16(UTF16 string)
to support EFI based system. If EFI_LOADER is not enabled,
printf("%ls") is not supported, so bootmenu does not appear
correctly.

This commit changes the type of menu title from u16(UTF16) to
utf-8 string and EFI strings is conveted into utf-8.

Fixes: a3d0aa87ac ("bootmenu: update bootmenu_entry structure")
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Tested-by: Pali Rohar <pali@kernel.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-05-31 07:57:02 +02:00
Vincent Stehlé
2ee9550a7d doc/efi: add firmware management protocol to the documentation
The firmware management protocol can be used to manage device firmware.
U-Boot can be configured to provide an implementation.

Document the related functions in the API section.

Signed-off-by: Vincent Stehlé <vincent.stehle@arm.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-05-28 10:59:27 +02:00
Vincent Stehlé
7751d2ef86 efi: fix documentation warnings
This fixes the following warnings:

  ./lib/efi_loader/efi_firmware.c:283: warning: Function parameter or member 'package_version' not described in 'efi_firmware_fit_get_image_info'
  ./lib/efi_loader/efi_firmware.c:283: warning: Function parameter or member 'package_version_name' not described in 'efi_firmware_fit_get_image_info'
  ./lib/efi_loader/efi_firmware.c:369: warning: bad line: firmware image
  ./lib/efi_loader/efi_firmware.c:395: warning: Function parameter or member 'package_version' not described in 'efi_firmware_raw_get_image_info'
  ./lib/efi_loader/efi_firmware.c:395: warning: Function parameter or member 'package_version_name' not described in 'efi_firmware_raw_get_image_info'

Signed-off-by: Vincent Stehlé <vincent.stehle@arm.com>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-05-28 10:59:27 +02:00
Masahisa Kojima
afbeedc868 lib/charset: fix compile warnings
This commit fixes the following compile warnings
for the documentation.

./include/charset.h:276: warning: Function parameter or member 'size' not described in 'u16_strlcat'
./include/charset.h:276: warning: Excess function parameter 'count' description in 'u16_strlcat'

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-05-28 10:59:27 +02:00
AKASHI Takahiro
57ad624103 efi_loader: bootmgr: fix a problem in loading an image from a short-path
Booting from a short-form device path which starts with the first element
being a File Path Media Device Path failed because it doesn't contain
any valid device with simple file system protocol and efi_dp_find_obj()
in efi_load_image_from_path() will return NULL.
For instance,
/VenHw(e61d73b9-a384-4acc-aeab-82e828f3628b)/Scsi(0,0)/\helloworld.efi
-> shortened version: /\helloworld.efi

With this patch applied, all the media devices with simple file system
protocol are enumerated and the boot manager attempts to boot temporarily
generated device paths one-by-one.

This new implementation is still a bit incompatible with the UEFI
specification in terms of:
* not creating real boot options
* not try
  "If a device does not support the EFI_SIMPLE_FILE_SYSTEM_PROTOCOL, but
  supports the EFI_BLOCK_IO_PROTOCOL protocol, then the EFI Boot Service
  ConnectController must be called for this device with DriverImageHandle
  and RemainingDevicePath set to NULL and the Recursive flag is set to TRUE."
(See section 3.1.2 "Load Option Processing".)

But it still gives us a closer and better solution than the current.

Fixes: commit 9cdf470274 ("efi_loader: support booting via short-form device-path")
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-05-28 10:59:27 +02:00
AKASHI Takahiro
05f391e2fc efi_loader: disk: add efi_disk_is_removable()
This helper function will be used to determine if the device is
removable media, initially for handling a short-path loading.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2022-05-28 10:59:27 +02:00
Heinrich Schuchardt
8131c85a77 cmd/bootefi: correct command syntax
For indicating the address and size of a memory region other commands use a
<addr>[:<size>] syntax. Do the same for bootefi.

Fixes: 2058983689 ("cmd: bootefi: restore ability to boot arbitrary blob")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-05-28 10:59:27 +02:00
Heinrich Schuchardt
b96de9cb0c test: don't change console timeout in EFI selftest.
Changing the console timeout to 500 ms without restoring the original value
leads to failures in other tests. As the console timeout change is not
necessary for the text input protocol tests remove it.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-05-28 10:59:27 +02:00
Heinrich Schuchardt
b9bf9c587f test: fix pylint warnings in test_efi_selftest.py
* change format of parameter documentation
* avoid superfluous assignments

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-05-28 10:59:27 +02:00
Masahisa Kojima
83f73632c9 bootmenu: U-Boot console is enabled as default
The commit 2158b0da22 ("bootmenu: add Kconfig option
not to enter U-Boot console") disables to enter U-Boot
console from bootmenu as default, this change affects the
existing bootmenu users.

This commit reverts the default behavior, the bootmenu can
enter U-Boot console same as before.
CMD_BOOTMENU_ENTER_UBOOT_CONSOLE is renamed
BOOTMENU_DISABLE_UBOOT_CONSOLE and depends on
AUTOBOOT_MENU_SHOW.

Fixes: 2158b0da22 ("bootmenu: add Kconfig option not to enter U-Boot console")
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Tested-by: Pali Rohar <pali@kernel.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-05-28 10:59:27 +02:00
Sean Anderson
a24b20ea67 doc: sandbox: Add additional valgrind documentation
This documents some additional options which can be used with valgrind, as
well as directions for future work. It also fixes up inline literals to
actually be inline literals (and not italics). The content of this
documentation is primarily adapted from [1].

[1] https://lore.kernel.org/u-boot/57cb4b49-fa30-1194-9ac3-faa53e8033bd@gmail.com/

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-05-28 10:59:27 +02:00
Heinrich Schuchardt
42356472bf doc/build/gcc: add more required packages
The following Python packages are used by U-Boot, too:

* python3-asteval
* python3-subunit
* python3-testtools

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-05-28 10:59:27 +02:00
Bin Meng
783f2c879d doc: sandbox: Add a note of disabling LTO when using gdb
Image created by LTO is not friendly to debugger, let's document this.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

Mention CONFIG_CC_OPTIMIZE_FOR_DEBUG and LLDB.
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2022-05-28 10:59:27 +02:00
Bin Meng
27267c61b1 doc: sandbox: Correct the memory size config option
It should be CONFIG_SANDBOX_RAM_SIZE_MB.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-05-28 10:59:27 +02:00
Sean Anderson
1e5514fd68 valgrind: Disable on Risc-V
There are no defined instruction sequences in include/valgrind.h for
Risc-V, so CONFIG_VALGRIND will do nothing on this arch (and possibly won't
compile?). Update Kconfig accordingly.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-05-28 10:59:27 +02:00
Heinrich Schuchardt
018b993bba test: restore timeout after bootmenu unit test
In the bootmenu unit test the console timeout is set to 500 ms.
Other tests rely on the original timeout. Ensure that the original value
is restored.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-05-28 10:59:27 +02:00
Heinrich Schuchardt
1291c2d446 disk: incorrect message in is_gpt_valid()
alloc_read_gpt_entries() writes differentiated error messages.
The caller is_gpt_valid() should not write an extra possibly wrong message.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-05-28 10:59:27 +02:00
Tom Rini
4fe629d2e8 Merge https://source.denx.de/u-boot/custodians/u-boot-riscv 2022-05-27 08:50:42 -04:00
Tom Rini
0fdc468b06 Merge branch '2022-05-26-assorted-fixes'
- Fixes for pytest timeout in CI, missing dependency on PCI for the
  e1000 driver, fix for CVE-2022-30767 (NFS), TI K3 AM642 DTS bugfix,
  MAINTAINERS updates, mksquashfs version check fix.
2022-05-27 08:48:47 -04:00
Sean Anderson
d64ac8549d net: e1000: Depend on CONFIG_PCI
This driver depends on PCI. Update the Kconfig accordingly.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-05-26 10:32:27 -04:00
Heinrich Schuchardt
d051a91c8d test: fix parsing the mksquashfs version number
Testing with mksquasshfs 4.5.1 results in an error

    ValueError: could not convert string to float: '4.5.1'

Version 4.10 would be considered to be lower than 4.4.

Fixes: 04c9813e95 ("test/py: rewrite common tools for SquashFS tests")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-05-26 10:32:27 -04:00
Wasim Khan
d9402bd49b board: freescale: Update MAINTAINERS List
Update MAINTAINERS List for LS2088ARDB and LS2088AQDS
platforms

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
2022-05-26 10:32:26 -04:00
Georgi Vlaev
e7356f08e9 arm: dts: k3-am642-*: Mark the memory node with u-boot, dm-spl
Since commit dffdb1f8eb ("board: ti: am64x: Use fdt functions
for ram and bank init") ddr_init() and dram_bank_init() have
switched to fdtdec for getting the memory configuration from
the am64xx dts files instead of using hardcoded values. This
requires an accessible memory node in SPL as we already have
in k3-am642-r5-evm.dts.

Make the memory node accessible in A53 SPL for both am642-sk
and am642-evm and in am642-sk R5 SPL.

Signed-off-by: Georgi Vlaev <g-vlaev@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-05-26 10:32:26 -04:00
Joel Stanley
24c8d1aba1 MAINTAINERS: aspeed: Add more files and myself as a reviewer
Add the rest of the ASPEED drivers that are in tree. Most are obvious,
except for ftgmac100 which matches the register layout used in the
ASPEED SoC.

I am the Linux maintainer for the ASPEED kernel port, and help maintain
the fork of u-boot used for OpenBMC, so add myself as a reviewer so I
can stay informed about u-boot changes.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
2022-05-26 10:32:26 -04:00
Andrea zi0Black Cappa
bdbf7a05e2 net: nfs: Fix CVE-2022-30767 (old CVE-2019-14196)
This patch mitigates the vulnerability identified via CVE-2019-14196.

The previous patch was bypassed/ineffective, and now the vulnerability
is identified via CVE-2022-30767. The patch removes the sanity check
introduced to mitigate CVE-2019-14196 since it's ineffective.
filefh3_length is changed to unsigned type integer, preventing negative
numbers from being used during comparison with positive values during
size sanity checks.

Signed-off-by: Andrea zi0Black Cappa <zi0Black@protonmail.com>
2022-05-26 10:32:06 -04:00
Bin Meng
9e892ac276 test/py: test_part: Correct the test case name
Use test_part_types as the name instead of dm_compact.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2022-05-26 10:27:14 -04:00
Bin Meng
7eb2e88ae9 test/py: test_fs: Correct the test case name
Use test_fstypes as the name instead of test_dm_compact.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2022-05-26 10:27:14 -04:00
Bin Meng
7bb683513c test/py: Reset the console timeout value
Reset the console timeout value as some tests may change its default
value during the execution.

This fixes the random case timeout issue seen in the U-Boot CI.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2022-05-26 10:27:14 -04:00
Bin Meng
c544b281cd riscv: qemu: Set kernel_comp_addr_r for compressed kernel
Set kernel_comp_addr_r and kernel_comp_size for compressed kernel.
Adjust existing addresses for ramdisk, so that kernel_comp_addr_r
comes before the ramdisk image, since the decompressed kernel size
is known to us. This way we can allow big ramdisk image to be loaded.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2022-05-26 18:42:34 +08:00
Bin Meng
ce78c4cd6e riscv: sifive: unleashed: Set kernel_comp_addr_r for compressed kernel
Set kernel_comp_addr_r and kernel_comp_size for compressed kernel.
Adjust existing addresses for ramdisk, so that kernel_comp_addr_r
comes before the ramdisk image, since the decompressed kernel size
is known to us. This way we can allow big ramdisk image to be loaded.

Update unleashed.rst to remove the manual environment configuration
for compressed kernel boot.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2022-05-26 18:42:34 +08:00
Bin Meng
b84d24c3c5 riscv: sifive: unmatched: Adjust for big ramdisk image
Move kernel_comp_addr_r to an address that comes before the ramdisk
image, since the decompressed kernel size is known to us. This way
we can allow big ramdisk image to be loaded.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2022-05-26 18:42:33 +08:00
Leo Yu-Chi Liang
d5af15bf51 riscv: Clean up asm/io.h
Clean up asm/io.h by
- removing commented code
- removing outdated comments
- removing unused definitions (for mem_isa, mem_pci)

This massively improves the readability of the file.

Suggested by commits:
7ab2e47d27 ("arm: Clean up asm/io.h")
909d0399a5 ("ARM: asm/io.h: kill off confusing #ifdef __mem_pci block")

Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2022-05-26 18:41:21 +08:00
Michal Simek
8ac37b461c riscv: remove CONFIG_ARCH_MAP_SYSMEM from io.h
Commit ba1ed5b022 ("Convert CONFIG_ARCH_MAP_SYSMEM to Kconfig") clearly
defined that this option is available for SANDBOX (was also for already
removed NDS32). That's why there is no way how this code can be enabled
with current Kconfig layout for riscv.
Based on this removing this code.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2022-05-26 18:38:02 +08:00
Heinrich Schuchardt
73872eb05a cmd/sbi: add implementation ID 6 - Coffer
The sbi command displays the ID of the implementation of the RISC-V
Supervisor Binary Interface Specification. A new ID for Coffer has recently
been added.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2022-05-26 18:37:55 +08:00
Rick Chen
9da5ced5c5 riscv: ae350: Fix OF_BOARD boot failure
Disable BINMAN_FDT for ae350 boards which don't actually use it.

Fixes: 836eac7c6f ("fdt: Make OF_BOARD a bool option")
Signed-off-by: Rick Chen <rick@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2022-05-26 18:37:51 +08:00
Rick Chen
b277a95c6e riscv: ae350: Fix OF_BOARD boot failure
Enable OF_HAS_PRIOR_STAGE for ae350 boards with OF_BOARD

Fixes: 239d22c795 ("fdt: Enable OF_HAS_PRIOR_STAGE for most boards with OF_BOARD")
Signed-off-by: Rick Chen <rick@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2022-05-26 18:37:51 +08:00
Tom Rini
661f540075 Merge tag 'xilinx-for-v2022.07-rc4' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2022.07-rc4

zynqmp:
- Fix DP PLL configuration for zcu102/zcu106 and SOM
- Fix split mode for starting R5s
- DT fixes
- Remove firmware node for mini configurations
- Wire TEE for multi DTB fit image

xilinx:
- Handle board_get_usable_ram_top(0) properly

phy:
- Extend psgtr timeout

mmc:
- Fix mini configuration which misses zynqmp_pm_is_function_supported()
2022-05-25 09:50:08 -04:00
Tom Rini
7e0edcadb0 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi
The bulk of it is (finally!) some DT sync from the kernel. We refrained
from syncing one incompatible change, as this would spoil booting Linux
kernels before v5.13 with U-Boot's DT (via UEFI, for instance).
I test booted Linux v5.18 and v5.4 with that new DT on some boards, and
the headless peripherals (MMC, USB, Ethernet) seemed to work.
The rest are fixes:
- silencing missing clock warnings due to the new pinctrl driver
- fixing "UART0 on PortF", allowing UART access through the SD card pins
- add an F1C100s clock driver, to enable MMC support (SPI comes later)
- some cleanups for CONS_INDEX_n in Kconfig

Tested on BananaPi-M1, Pine64-LTS, Pine-H64, X96-Mate (H616) and
OrangePi-Zero.
2022-05-24 23:29:00 -04:00
Tom Rini
1b04a961c6 Merge tag 'tpm-24052022' of https://source.denx.de/u-boot/custodians/u-boot-tpm
Add support for i2c devices
2022-05-24 09:03:34 -04:00
Michal Simek
594f692f49 xilinx: zynqmp: Wire tee for Multi DTB use cases
Fix TEE wiring when MULTI_DTB is selected.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c8523a89d910ae6b8a9971b4e7b3bda89be3dc27.1652874088.git.michal.simek@amd.com
2022-05-24 08:44:24 +02:00
Tom Rini
bfb550db16 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-socfpga
- Add the terasic de10-standard board
2022-05-23 22:56:35 -04:00
Samuel Holland
7495051219 serial: Remove obsolete CONS_INDEX_n Kconfig options
These were only ever implied by sunxi platforms, and that usage has
been removed. Current practice is to specify CONFIG_CONS_INDEX in each
board's defconfig.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-05-24 01:46:06 +01:00
Samuel Holland
821fdfbba3 sunxi: Remove obsolete Kconfig selections
ARCH_SUNXI selects DM_SERIAL, so the condition can never be satisfied.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-05-24 01:46:06 +01:00
Andre Przywara
e26ece267e sunxi: board: Fix UART PortF pinmux setup
When CONFIG_UART0_PORT_F is defined, we try to configure two PortF pins
(usually used for the SD card) as UART0. Some SoCs use the mux value of
3 for this, while others use 4.

The combination of Kconfig symbols we currently use was not quite right:
we mis-configure the A31, A64, H6 and H616.

Going through the list in the pinctrl driver, there are only a few older
SoCs that use a value of 4, so revert the #ifdef clause, and name those
explicitly, instead of the other way around.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
2022-05-24 01:45:47 +01:00
Andre Przywara
d6cb09d89d clk: sunxi: add and use dummy gate clocks
Some devices enumerate various clocks in their DT, and many drivers
just blanketly try to enable all of them. This creates problems
since we only model a few gate clocks, and the clock driver outputs
a warning when a clock is not described:
=========
sunxi_set_gate: (CLK#3) unhandled
=========

Some clocks don't have an enable bit, or are already enabled in a
different way, so we might want to just ignore them.

Add a CCU_CLK_F_DUMMY_GATE flag that indicates that case, and define
a GATE_DUMMY macro that can be used in the clock description array.
Define a few clocks, used by some pinctrl devices, that way to suppress
the runtime warnings.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
2022-05-24 01:16:15 +01:00
Andre Przywara
444ab3569b clk: sunxi: add PIO bus gate clocks
The introduction of the DM pinctrl driver made its probe function enable
all clocks enumerated in the DT. This includes the "CLK_BUS_PIO" (and
variations) gate clock. Also CLK_PLL_PERIPH0 is used by the R_CCU device.
So far we didn't describe those clocks in our clock driver.
As we enable them already in the SPL, the devices happen to work, but
the clock driver still complains about not finding those clocks:
=========
sunxi_set_gate: (CLK#58) unhandled
=========

Add the one-liners that are needed to announce the gate bit for those
clocks, to silence that message on the console.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
2022-05-24 01:15:09 +01:00
Samuel Holland
596247e54b clk: sunxi: h6_r: Correct the driver name
H6 is from the sun50i family, not sun6i.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-05-24 01:15:01 +01:00
Samuel Holland
818e1636ac mmc: sunxi: Remove unnecessary pinmux option dependency
Now that the pinmux conflict is handled in the board code (by skipping
setup for the one conflicting MMC controller), the driver does not need
to be entirely disabled based on the UART pinmux.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-05-24 01:14:51 +01:00
Samuel Holland
3ba0a25c44 sunxi: Skip MMC0 init when its pinmux conflicts with UART0
Currently, selecting UART0_PORT_F entirely disables MMC support on sunxi
platforms. But this is a bigger hammer then needed. Muxing UART0 to the
pins on port F only causes a conflict with MMC0, so minimize the impact
by specifically skipping MMC0 init. We can continue to use MMC1/2 if
those are enabled.

Let's also remove the preprocessor check while refacting this function.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-05-24 01:14:35 +01:00
Tom Rini
b6d46d951f Prepare v2022.07-rc3
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-05-23 15:40:41 -04:00
Humberto Naves
1b05136a6c arm: socfpga: Add the terasic de10-standard board
Use the de10-nano files as templates for the de10-standard board.
The files in qts directory are generated by quartus from the GHRD
design.

Signed-off-by: Humberto Naves <hsnaves@gmail.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2022-05-23 21:28:07 +02:00
Tom Rini
c0a1409d21 configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-05-23 13:56:21 -04:00
Tom Rini
c04a418d52 Merge branch '2022-05-23-regression-fixes'
- Fix PowerPC NOR booting, important SPI uclass fixes/updates, gic_v2
  fix when CPU is not in EL3, fsl_esdhc_spl fix, and squashfs fix for
  linking on some architectures, and fix phy_string_for_interface
2022-05-23 13:52:53 -04:00
Tim Harvey
faa6ce6061 net: fix phy_string_for_interface
commit ffb0f6f488 ("treewide: Rename PHY_INTERFACE_MODE_NONE to
PHY_INTERFACE_MODE_NA") broke the phy_string_for_interface function.
Fix it.

Fixes ffb0f6f488 ("treewide: Rename PHY_INTERFACE_MODE_NONE to PHY_INTERFACE_MODE_NA")
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Cc: Marek Behún <marek.behun@nic.cz>
Cc: Stefan Roese <sr@denx.de>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-05-23 13:52:02 -04:00
Eddie James
9f971dac93 tpm: add support for TPMv2.x I2C chips
Add the tpm2_tis_i2c driver that should support any TPMv2 compliant
I2C chips, such as the NPCT75X chip.

[Ilias rename priv_auto_alloc_size to priv_auto]
Signed-off-by: Eddie James <eajames@linux.ibm.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2022-05-23 16:33:58 +03:00
Pali Rohár
c1abf7659c mmc: fsl_esdhc_spl: Fix checking for number of read sectors
Commit 0980cbba7b ("mmc: fsl_esdhc_spl: pre-PBL: implement redundancy
support") changed number of sectors which are read but did not adjusted
error check.

Fix it and check for if correct number of sectors were read.

Fixes: 0980cbba7b ("mmc: fsl_esdhc_spl: pre-PBL: implement redundancy support")
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-05-23 09:33:10 -04:00
Sai Pavan Boddu
2d25f63cc0 arm: gic_v2: Skip gic_init_secure when cpu is not in el3
This would prevent configuring non-secure regs in case gic security
extensions are not emulated in Qemu.

Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-05-23 09:33:10 -04:00
Patrice Chotard
012afa83ae test: dm: spi: Replace _spi_get_bus_and_cs() by spi_get_bus_and_cs() in some case
In case _spi_get_bus_and_cs()'s parameters drv_name and dev_name are
respectively set to NULL and 0, use spi_get_bus_and_cs() instead.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>

Cc: Marek Behun <marek.behun@nic.cz>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Vignesh R <vigneshr@ti.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Lukasz Majewski <lukma@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Cc: "Pali Rohár" <pali@kernel.org>
Cc: Konstantin Porotchkin <kostap@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Pratyush Yadav <p.yadav@ti.com>
Cc: Sean Anderson <seanga2@gmail.com>
Cc: Anji J <anji.jagarlmudi@nxp.com>
Cc: Biwen Li <biwen.li@nxp.com>
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Cc: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
2022-05-23 09:33:10 -04:00
Patrice Chotard
3feea0ba19 spi: spi_flash_probe_bus_cs() rely on DT for spi speed and mode
Now, spi_flash_probe_bus_cs() relies on DT for spi speed and mode
and logically calls spi_get_bus_and_cs(). In case spi mode and speed are
not read from DT, make usage of spi_flash_probe() instead.

To sum-up:
 - Previous call tree was:
    spi_flash_probe() -> spi_flash_probe_bus_cs() -> spi_get_bus_and_cs()

 - Current call tree is:
    spi_flash_probe() -> _spi_get_bus_and_cs()
    spi_flash_probe_bus_cs() -> spi_get_bus_and_cs()

This patch impacts the following :
  - cmd/sf.c: if spi mode and/or speed is passed in argument of
    do_spi_flash_probe(), call spi_flash_probe() otherwise call
    spi_flash_probe_bus_cs().

  - drivers/net/fm/fm.c: as by default spi speed and mode was set to
    0 and a comment indicates that speed and mode are read from DT,
    use spi_flash_probe_bus_cs().

  - drivers/net/pfe_eth/pfe_firmware.c: spi speed and mode are not read
    from DT by all platforms using this driver, so keep legacy and replace
    spi_flash_probe_bus_cs() by spi_flash_probe();

  - drivers/net/sni_netsec.c : spi speed and mode are not read from DT,
    so replace spi_flash_probe_bus_cs() by spi_flash_probe().

  - drivers/usb/gadget/max3420_udc.c: Can't find any platform which make
    usage of this driver, nevertheless, keep legacy and replace
    spi_get_bus_and_cs() by _spi_get_bus_and_cs().

  - env/sf.c: a comment indicates that speed and mode are read
    from DT. So use spi_flash_probe_bus_cs().

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>

Cc: Marek Behun <marek.behun@nic.cz>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Vignesh R <vigneshr@ti.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Lukasz Majewski <lukma@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Cc: "Pali Rohár" <pali@kernel.org>
Cc: Konstantin Porotchkin <kostap@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Pratyush Yadav <p.yadav@ti.com>
Cc: Sean Anderson <seanga2@gmail.com>
Cc: Anji J <anji.jagarlmudi@nxp.com>
Cc: Biwen Li <biwen.li@nxp.com>
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Cc: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
2022-05-23 09:33:10 -04:00
Patrice Chotard
61708bb0a2 spi: spi-uclass: Add new spi_get_bus_and_cs() implementation
Move legacy spi_get_bus_and_cs() code to _spi_get_bus_and_cs().

Add new spi_get_bus_and_cs() implementation which rely on DT
for speed and mode and don't need any drv_name nor dev_name
parameters. This will prepare the ground for next patch.

Update all callers to use _spi_get_bus_and_cs() to keep the
same behavior.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>

Cc: Marek Behun <marek.behun@nic.cz>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Vignesh R <vigneshr@ti.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Lukasz Majewski <lukma@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Cc: "Pali Rohár" <pali@kernel.org>
Cc: Konstantin Porotchkin <kostap@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Pratyush Yadav <p.yadav@ti.com>
Cc: Sean Anderson <seanga2@gmail.com>
Cc: Anji J <anji.jagarlmudi@nxp.com>
Cc: Biwen Li <biwen.li@nxp.com>
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Cc: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
2022-05-23 09:33:10 -04:00
Pali Rohár
827a232623 powerpc: mpc85xx: Fix CONFIG_OF_EMBED support for NOR booting
mpc85xx NOR binary contains also reset vector and therefore option
CONFIG_MPC85XX_HAVE_RESET_VECTOR must be defined.

When build system uses binman, it takes care of constructing final image
which consist of u-boot-without-reset-vector, DTB and reset-vector.

CONFIG_OF_EMBED does not use binman, there is no external DTB and Makefile
produce directly final u-boot.bin binary.

So in this case mpc85xx reset vector must not be stripped from the final
u-boot.bin binary. Fix it.

Signed-off-by: Pali Rohár <pali@kernel.org>
2022-05-23 09:33:10 -04:00
Pali Rohár
b898f6a6db powerpc: mpc85xx: Fix CONFIG_OF_SEPARATE support for NOR booting
Commit e8c0e0064c ("powerpc: mpc85xx: Fix CONFIG_OF_SEPARATE support")
fixed SD card booting on mpc85xx boards but broke NOR booting on these
boards. Reason is that U-Boot build system for NOR images uses binman and
this binman ignores alignment defined in linker script. Instead it has own
config file where is alignment defined.

Fix binman alignment for mpc85xx boards to match what is _now_ defined in
linker script.

This change fixes building of U-Boot for NOR booting on P2020 board.

Fixes: e8c0e0064c ("powerpc: mpc85xx: Fix CONFIG_OF_SEPARATE support")
Signed-off-by: Pali Rohár <pali@kernel.org>
2022-05-23 09:33:10 -04:00
Sean Nyekjaer
92080c6ef6 fs/squashfs: use lldiv function for math
When compling for x86:
ld.bfd: fs/squashfs/sqfs.o: in function `sqfs_read':
u-boot/fs/squashfs/sqfs.c:1443: undefined reference to `__udivmoddi4'
ld.bfd: u-boot/fs/squashfs/sqfs.c:1521: undefined reference to `__udivmoddi4'

Signed-off-by: Sean Nyekjaer <sean.nyekjaer.ext@siemensgamesa.com>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Pali Rohár <pali@kernel.org>
2022-05-23 09:33:10 -04:00
Eddie James
8d7199da3f tpm: core: Set timeouts before requesting locality
Requesting the locality uses the timeout values, so they need
to be set beforehand.

Signed-off-by: Eddie James <eajames@linux.ibm.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2022-05-23 16:32:55 +03:00
Tom Rini
004d30c786 Merge tag 'u-boot-imx-20220523' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
u-boot-imx-20220523
-------------------

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/12087

Additionally to u-boot-imx20200520:

- DH MX8MP
- i.MX GPIO: reading GPIO when direction is output
- Menlo i.MX53: switch to DM

And from u-boot-imx20200520:

- fix Verdin hang
- add pca9450 regulator
- conversion to DM_SERIAL
- NAND block handling
- fix crypto
- enable cache on some boards
- add ACC board (MX6)
2022-05-23 09:25:39 -04:00
Marek Vasut
4d573d5c98 ARM: dts: imx: Add support for DH electronics i.MX8M Plus DHCOM and PDK2
Add support for DH electronics i.MX8M Plus DHCOM SoM on PDK2 carrier board.
Currently supported are serial console, EQoS and FEC ethernets, eMMC, SD,
SPI NOR and USB 3.0 host.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2022-05-23 11:37:58 +02:00
Christoph Fritz
0539d16d22 gpio: rgpio2p: Enhance reading of GPIO pin value
Add support for reading GPIO pin value when function is output.
With this patch applied, gpio toggle command is working.

Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-05-23 11:37:58 +02:00
Marek Vasut
9d371e5fea ARM: imx: mx5: Convert MX53 Menlo board to DM I2C and DM RTC
Convert the board to DM I2C and DM RTC. This leads to removal of board
side iomuxc configuration, which is now done using pin control driver,
and conversion of board side legacy I2C accessors to DM ones.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2022-05-23 11:37:58 +02:00
Sergei Antonov
fdc55a6ba8 meson: axg: search dtb for meson-axg-usb-ctrl on board axg
USB controller for AXG is described as meson-axg-usb-ctrl,
see arch/arm/dts/meson-axg.dtsi
Look for that name instead of meson-gxl-usb-ctrl.

Signed-off-by: Sergei Antonov <saproj@gmail.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lore.kernel.org/r/20220509113618.2891126-1-saproj@gmail.com
2022-05-23 10:40:01 +02:00
Andre Przywara
92373de041 Revert "sunxi: f1c100s: Drop SYSRESET to enable reset functionality"
The original Allwinner F1C100 .dtsi imported from the Linux kernel tree
used the wrong compatible string for the watchdog timer, so the Allwinner
DM reset driver was not working properly. We worked around this by
disabling the SYSRESET driver, so the hardcoded SPL reset driver took
over.
Now the issue was fixed in the DTs in mainline Linux, and we synced the
fixed .dtsi file into U-Boot, so drop the hack and use the normal U-Boot
proper reset infrastructure.

This reverts commit cfcf1952c1.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-05-23 00:37:52 +01:00
Andre Przywara
d037e79f3a sunxi: F1C100s: update DT files from Linux
The initial U-Boot F1C100s port was based on the mainline kernel DT
files, which were quite basic and were missing the essential MMC and
SPI peripherals. While we could work around this in the SPL by
hardcoding the required information, this left U-Boot proper without SD
card or SPI flash support, so actual loading would require FEL boot.

Now the missing DT bits have been submitted and accepted in the kernel
tree, so lets sync back those files into U-Boot to enable MMC and
SPI, plus benefit from some fixes.

This is a verbatim copy of the .dts and .dtsi file from
linux-sunxi/dt-for-5.19[1], which have been part of linux-next for a
while as well.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux.git/log/?h=sunxi/dt-for-5.19

Link: https://lore.kernel.org/linux-arm-kernel/20220317162349.739636-1-andre.przywara@arm.com/
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-05-23 00:37:51 +01:00
George Hilliard
89dd650f20 clk: sunxi: implement clock driver for suniv f1c100s
The f1c100s has a clock tree similar to those of other sunxi parts.
Add support for it.

Signed-off-by: George Hilliard <thirtythreeforty@gmail.com>
Signed-off-by: Yifan Gu <me@yifangu.com>
Acked-by: Sean Anderson <seanga2@gmail.com>
[Andre: add PIO and I2C]
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-05-23 00:37:51 +01:00
Samuel Holland
ce00370b87 ARM: dts: sun50i: H6: Sync from Linux v5.18-rc1
Copy the devicetree source for the H6 SoC and all existing boards
from the Linux v5.18-rc1 tag.

To maintain ABI compatibility with existing LTS kernels, one change
moving some IP blocks to the r_intc interrupt controller is excluded.
This effectively reverts Linux commits 189bef235dd3 and 73088dfee635.

This commit also adds the following new board devicetrees:
 - sun50i-h6-pine-h64-model-b.dts
 - sun50i-h6-tanix-tx6-mini.dts

This update should not impact any existing U-Boot functionality.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-05-23 00:37:51 +01:00
Samuel Holland
7710282334 ARM: dts: sun50i: A64: Sync from Linux v5.18-rc1
Copy the devicetree source for the A64 SoC and all existing boards
from the Linux v5.18-rc1 tag.

To maintain ABI compatibility with existing LTS kernels, one change
moving some IP blocks to the r_intc interrupt controller is excluded.
This effectively reverts Linux commits 189bef235dd3 and 73088dfee635.

This update should not impact any existing U-Boot functionality.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-05-23 00:37:51 +01:00
Samuel Holland
7024755bd7 ARM: dts: sun8i: R40/T3: Sync from Linux v5.18-rc1
Copy the devicetree for the R40/T3 SoC verbatim from the Linux v5.18-rc1
tag. None of the existing boards had any devicetree updates.

This commit adds the following new board devicetrees:
 - sun8i-r40-oka40i-c.dts
 - sun8i-t3-cqa3t-bv3.dts

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-05-23 00:37:51 +01:00
Samuel Holland
94539ab840 ARM: dts: sun8i: V3/V3s/S3: Sync from Linux v5.18-rc1
Copy the devicetree source for the V3(s)/S3 SoCs and all existing boards
verbatim from the Linux v5.18-rc1 tag.

This commit also adds the following new board devicetrees:
 - sun8i-s3-elimo-initium.dts
 - sun8i-v3-sl631-imx179.dts

This update should not impact any existing U-Boot functionality.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-05-23 00:37:51 +01:00
Samuel Holland
2c597855aa ARM: dts: sunxi: H2+/H3/H5: Sync from Linux v5.18-rc1
Copy the devicetree source for the H2+/H3/H5 SoCs and all existing
boards from the Linux v5.18-rc1 tag.

To maintain ABI compatibility with existing LTS kernels, one change
moving some IP blocks to the r_intc interrupt controller is excluded.
This effectively reverts Linux commits 994e5818392c and 9fdef3c3d8c2.

This commit also adds the following new board devicetree:
 - sun8i-h3-nanopi-r1.dts

This update should not impact any existing U-Boot functionality.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-05-23 00:37:51 +01:00
Samuel Holland
2d648e6982 ARM: dts: sun8i: A83T: Sync from Linux v5.18-rc1
Copy the devicetree source for the A83T SoC and all existing boards
from the Linux v5.18-rc1 tag.

To maintain ABI compatibility with existing LTS kernels, one change
moving some IP blocks to the r_intc interrupt controller is excluded.
This effectively reverts Linux commits 994e5818392c and 9fdef3c3d8c2.

As with the other SoCs, updates of note include adding detection GPIO
properties in the USB PHY nodes.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-05-23 00:37:51 +01:00
Samuel Holland
6f97e028ef ARM: dts: sun9i: Sync from Linux v5.18-rc1
Copy the devicetree source for the A80 SoC and all existing boards
verbatim from the Linux v5.18-rc1 tag.

This update should not impact any existing U-Boot functionality.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-05-23 00:37:51 +01:00
Samuel Holland
70f24fa02b ARM: dts: sunxi: A13/A31/A23/A33: Sync from Linux v5.18-rc1
Copy the devicetree source for the A10s/A13/GR8, A31(s), and A23/A33/R16
SoCs and all existing boards from the Linux v5.18-rc1 tag.

These changes are combined into one commit due to interdependencies:
 - The unit addresses were removed from bitbanged I2C buses, which
   drives a Kconfig default change. This affects sun5i-a13-utoo-p66.dts
   and sun6i-a31-colombus.dts.
 - The pinctrl nodes were renamed, including some used by the shared
   header sunxi-reference-design-tablet.dtsi.

To maintain ABI compatibility with existing LTS kernels, one change
moving some IP blocks to the r_intc interrupt controller is excluded.
This effectively reverts Linux commits 994e5818392c and 9fdef3c3d8c2.

This commit renames the file sun8i-r16-nintendo-nes-classic-edition.dts
to sun8i-r16-nintendo-nes-classic.dts to match the Linux tree.

This commit also adds the following new board devicetrees:
 - sun5i-a13-licheepi-one.dts
 - sun5i-a13-pocketbook-touch-lux-3.dts
 - sun5i-gr8-evb.dts
 - sun8i-a23-ippo-q8h-v1.2.dts
 - sun8i-a23-ippo-q8h-v5.dts
 - sun8i-a33-et-q8-v1.6.dts
 - sun8i-a33-ippo-q8h-v1.2.dts
 - sun8i-r16-nintendo-super-nes-classic.dts

As with the other SoCs, updates of note are conversion of GPIO pull-up
from pinconf to GPIO flags and renaming the detection GPIO properties in
the USB PHY nodes.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-05-23 00:37:51 +01:00
Samuel Holland
4746694cba ARM: dts: sun4i: Sync from Linux v5.18-rc1
Copy the devicetree source for the A10 SoC and all existing boards
verbatim from the Linux v5.18-rc1 tag.

This commit also adds the following new board devicetree:
 - sun4i-a10-topwise-a721.dts

While this update should not impact any existing U-Boot functionality,
the changes to the USB PHY detection GPIO properties are needed to
convert that driver to use the DM GPIO framework.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-05-23 00:37:51 +01:00
Samuel Holland
0605ac405c ARM: dts: sun7i: Sync from Linux v5.18-rc1
Copy the devicetree source for the A20 SoC and all existing boards
verbatim from the Linux v5.18-rc1 tag.

This commit also adds the following new board devicetrees:
 - sun7i-a20-haoyu-marsboard.dts
 - sun7i-a20-linutronix-testbox-v2.dts
 - sun7i-a20-olinuxino-lime-emmc.dts

This update includes changes to the USB PHY detection GPIO properties
which are needed to convert that driver to use the DM GPIO framework.

Signed-off-by: Samuel Holland <samuel@sholland.org>
[Andre: fix Mele M5 U-Boot only DT]
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-05-23 00:37:50 +01:00
Samuel Holland
91407bbd41 ARM: dts: sunxi: Remove unused devicetree headers
These files are not included anywhere and do not exist in the Linux
devicetree source.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-05-23 00:37:50 +01:00
Samuel Holland
9a50489c60 dt-bindings: sunxi: Update clock/reset binding headers
Some devicetree updates make use of newly-exposed clocks and resets.
To support that, copy the binding headers from the Linux v5.18-rc1 tag.

Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-05-23 00:37:50 +01:00
Tom Rini
6f00b97d7e Merge https://source.denx.de/u-boot/custodians/u-boot-usb 2022-05-20 22:07:56 -04:00
Jan Kiszka
868d58f69c usb: dwc3: Fix non-usb3 configurations
Missing nodes may also be signaled via -ENODATA. We need to check for
that to prevent failing in non-usb3 setups.

Furthermore, dev.phy must be NULL'ed in case usb3-phy was not found.

Fixes: 142d50fbce ("usb: dwc3: Add support for usb3-phy PHY configuration")
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2022-05-20 23:30:36 +02:00
Tom Rini
658d38e193 Merge tag 'u-boot-stm32-20220520' of https://source.denx.de/u-boot/custodians/u-boot-stm
- spi: fix busy bit check in stm32_qspi driver
- stm32mp15: configure Buck3 voltage per PMIC NVM on Avenger96 board
2022-05-20 13:50:11 -04:00
Philip Oberfichtner
bd8df1f7dd ARM: imx6: Adapt device tree selection in DH board file
Before this commit device tree selection could rely solely on
differentiating the iMX6 processor variant Q and DL. After adding two new
carrier boards, the DRC02 and the picoITX, the interchangeability of SoMs
makes this approach infeasible.

It is now required to specify the carrier board (dhcom-drc02,
dhcom-picoitx or dhcom-pdk2) at compile time using
CONFIG_DEFAULT_DEVICETREE. The SoM is determined at runtime as before.

Signed-off-by: Philip Oberfichtner <pro@denx.de>
2022-05-20 12:36:49 +02:00
Philip Oberfichtner
c5a46943a2 ARM: dts: imx: Configure FEC for iMX6QDL DRC02
Add a u-boot dtsi for configuring the FEC node of the DH DRC02.

Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Philip Oberfichtner <pro@denx.de>
2022-05-20 12:36:49 +02:00
Philip Oberfichtner
84d9ce5607 ARM: dts: imx: Configure FEC for iMX6QDL picoITX
Add a u-boot dtsi for configuring the FEC node of the DH picoITX.

Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Philip Oberfichtner <pro@denx.de>
2022-05-20 12:36:49 +02:00
Philip Oberfichtner
dcb59a1306 ARM: dts: imx: Simplify fec node for iMX6QDL DHCOM boards
Firstly the FEC can now use the regulator reg_eth_vio from
imx6qdl-dhcom-som.dtsi instead of defining its own.

Secondly the &fec node is moved to the more generic SoM device tree
file, because it can be used by multiple boards.

Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Philip Oberfichtner <pro@denx.de>
2022-05-20 12:36:49 +02:00
Philip Oberfichtner
6ecd1d66a9 ARM: imx6: Remove CONFIG_FEC_MXC_PHYADDR from DH header
Use phy address from device tree instead of CONFIG_FEC_MXC_PHYADDR from
board header. This is required, because the DH picoITX and DRC02 boards
require different settings than PDK2. The corresponding 'phy-handle'
device tree properties are already there.

I tested this change on picoITX and DRC02, but on PDK2 it is untested.

Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Philip Oberfichtner <pro@denx.de>
2022-05-20 12:36:48 +02:00
Philip Oberfichtner
874c76867a ARM: dts: imx: Migrate iMX6QDL picoITX DTs from Linux
Migrate DH picoITX device trees from Linux commit 42226c989789
(tag v5.18-rc7). No changes have been made, the DTs are exact copies.
Furthermore add the DTB to dh_imx6_defconfig.

Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Philip Oberfichtner <pro@denx.de>
2022-05-20 12:36:48 +02:00
Philip Oberfichtner
45964cbf3c ARM: dts: imx: Migrate iMX6QDL DRC02 DTs from Linux
Migrate DH DRC02 device trees from Linux commit 42226c989789
(tag v5.18-rc7). No changes have been made, the DTs are exact copies.
Furthermore add the DTB to dh_imx6_defconfig.

Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Philip Oberfichtner <pro@denx.de>
2022-05-20 12:36:48 +02:00
Philip Oberfichtner
e1e0d9ab9f ARM: imx6: Fix broken DT path in DH board file
In the DH electronics iMX6 board file fix the outdated eeprom path by
using a DT label instead.

The label has been newly created for all iMX6QDL DHCOM boards.

Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Philip Oberfichtner <pro@denx.de>
2022-05-20 12:36:48 +02:00
Marek Vasut
326337fb00 pmic: pca9450: Add regulator driver
Add PCA9450 regulator driver. This is complementary driver for the BUCKn
and LDOn regulators provided by the PCA9450 PMIC driver. Currently the
driver permits reading the settngs and configuring the BUCKn and LDOn
regulators.

Reviewed-by: Fabio Estevam <festevam@denx.de>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2022-05-20 12:36:48 +02:00
Marek Vasut
1d51e779e3 pmic: pca9450: Add upstream regulators subnode match
The upstream DT regulators node subnodes are named BUCKn and LDOn,
the downstream DT regulators node subnodes are named buckn and ldon,
add the upstream match.

Reviewed-by: Fabio Estevam <festevam@denx.de>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2022-05-20 12:36:48 +02:00
Peng Fan
fbc6b14143 imx: imx8mp_rsb3720a1: convert to DM_SERIAL
Enable CONFIG_DM_SERIAL. uart2 and its pinmux was already
marked with u-boot,dm-spl.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-05-20 12:36:48 +02:00
Marcel Ziswiler
c898b53755 ARM: imx8mm: verdin-imx8mm: fix board hang in spl
Move the preloader_console_init() call after spl_early_init() to avoid
board hang in SPL.

While at it remove explicit in-code console/debug UART pinmuxing (uart1
and its pinmuxing are already marked as u-boot,dm-spl via device tree).

Fixes: 4551e18987 ("configs: verdin-imx8mm: verdin-imx8mp: enable dm serial")
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-05-20 12:36:48 +02:00
Fabio Estevam
886e423a21 imx8mp_rsb3720a1: Enable cache in SPL
There is no reason for disabling I-cache and D-cache
in SPL.

Remove the unneeded CONFIG_SPL_SYS_ICACHE_OFF and
CONFIG_SPL_SYS_DCACHE_OFF options.

Signed-off-by: Fabio Estevam <festevam@denx.de>
2022-05-20 12:36:48 +02:00
Fabio Estevam
a3f0d49408 cgtqmx8: Enable cache in SPL
There is no reason for disabling I-cache and D-cache
in SPL.

Remove the unneeded CONFIG_SPL_SYS_ICACHE_OFF and
CONFIG_SPL_SYS_DCACHE_OFF options.

Signed-off-by: Fabio Estevam <festevam@denx.de>
2022-05-20 12:36:48 +02:00
Fabio Estevam
ec7eb75fcf imx8mm-cl-iot-gate: Enable cache in SPL
There is no reason for disabling I-cache and D-cache
in SPL.

Remove the unneeded CONFIG_SPL_SYS_ICACHE_OFF and
CONFIG_SPL_SYS_DCACHE_OFF options.

Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
2022-05-20 12:36:48 +02:00
Philip Oberfichtner
55d1537c5b bosch: Add initial board support for ACC
The Bosch ACC (Air Center Control) Board is based on the i.MX6D.

The device tree is copied from Linux, see [1]. The only difference
compared to the Linux DT is the removal of usbphynop properties. They are
defined in the Linux version of imx6qdl.dtsi, but not in the u-boot
version.

[1] Commit 6192cf8ac082 from
    git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git

Signed-off-by: Philip Oberfichtner <pro@denx.de>
2022-05-20 12:36:48 +02:00
Michael Trimarchi
35461fe94e imx: imx8mn_smm_s2/s2pro: Enable TrustZone
When the board was added, enabling tzc380 was left off by
mistake. The optee was tested with the following configuration
in s2pro

+	firmware {
+		optee {
+			compatible = "linaro,optee-tz";
+			method = "smc";
+		};
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		/* 6MiB */
+		optee_core@5f800000 {
+			reg = <0x00 0x5f800000 0x00 0x600000>;
+		};
+
+		/* 2MiB */
+		optee_shm@5fe00000 {
+			reg = <0x00 0x5fe00000 0x00 0x200000>;
+		};
+	};
+

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2022-05-20 12:36:48 +02:00
Michael Trimarchi
cc980143c0 spl: spl_nand: Fix bad block handling in fitImage
If the fitImage has some bad block in fit image area, the
offset must be recalulcated. This should be done always.
After implementing it in mxs now is possible to call the function
even for that platform.

Cc: Fabio Estevam <festevam@gmail.com>
Tested-By: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2022-05-20 12:36:48 +02:00
Michael Trimarchi
37a7c374a6 arm: mach-imx: cmd_nandbcb fix bad block handling
The badblock should be skipped properly in reading and writing.
Fix the logic. The bcb struct is written, skipping the bad block,
so we need to read using the same logic. This was tested create
bad block in the area and then flash it and read it back.

Acked-by: Han Xu <han.xu@nxp.com>
Tested-By: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2022-05-20 12:36:48 +02:00
Michael Trimarchi
a222c14792 mtd: nand: mxs_nand_spl: Fix bad block skipping
The specific implementation was having bug. Those bugs are since
the beginning of the implementation. Some manufactures can already
experience this bug in their SPL code. This bug can be more visible on
architecture that has complicated boot process like imx8mn. Older
version of uboot can be affected if the bad block
appear in correspoding of the beginning of u-boot image. In order to
adjust the function we scan from the first erase block.

The problematic part of old code was in this part:

while (is_badblock(mtd, offs, 1)) {
           page = page + nand_page_per_block;
          /* Check i we've reached the end of flash. */
          if (page >= mtd->size >> chip->page_shift) {
                      free(page_buf);
                      return -ENOMEM;
         }
}

Even we fix it adding increment of the offset of one erase block size
, we don't fix the problem, because the first erase block where the
image start is not checked. The code was tested on an imx8mn where
the boot rom api was not able to skip it. This code is used by other
architecures like imx6 and imx8mm

Cc: Han Xu <han.xu@nxp.com>
Cc: Fabio Estevam <festevam@gmail.com>
Acked-by: Han Xu <han.xu@nxp.com>
Tested-By: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2022-05-20 12:36:47 +02:00
Michael Trimarchi
78bf8e802c nand: raw: mxs_nand: Fix specific hook registration
Move the hook after nand_scan_tail is called. The hook must be replaced
to the mxs specific one but those must to be assignment later in the
probe function.

With this fix markbad is working again. Before this change:

nand markbad 0xDEC00
NXS NAND: Writing OOB isn't supported
NXS NAND: Writing OOB isn't supported
block 0x000dec00 NOT marked as bad! ERROR 0

Cc: Han Xu <han.xu@nxp.com>
Cc: Fabio Estevam <festevam@gmail.com>
Acked-by: Han Xu <han.xu@nxp.com>
Tested-By: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2022-05-20 12:36:47 +02:00
Gaurav Jain
1919f58a8f crypto/fsl: fsl_hash: Fix dcache issue in caam_hash_finish
HW accelerated hash operations are giving incorrect hash output.
so add flush and invalidate for input/output hash buffers.

Fixes: 94e3c8c4fd (crypto/fsl - Add progressive hashing support using hardware acceleration.)
Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
2022-05-20 12:36:47 +02:00
Gaurav Jain
cad77280c3 i.MX8ULP: add display_ele_fw_version api
implement get f/w version api.
print ele f/w version in spl.

Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Pankaj Gupta <pankaj.gupta@nxp.com>
2022-05-20 12:36:47 +02:00
Ye Li
cda8f87349 caam: Fix crash in case caam_jr_probe failed
If probing caam_jr returns failure, the variable "dev" will not be
initialized, so we can't use dev->name for the error print.
Otherwise it will cause crash.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Gaurav Jain <gaurav.jain@nxp.com>
2022-05-20 12:36:47 +02:00
Fabio Estevam
5ed4c33f36 kontron-sl-mx8mm: Select the CONFIG_CMD_UNZIP option
Select the CMD_UNZIP option so that the 'gzwrite' command
can be used to flash wic.gz image into the eMMC.

Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2022-05-20 12:36:47 +02:00
Mark Kettenis
6a6468f479 usb: xhci-dwc3: Support role switch default role
When the device tree indicates support for role switching through
the "usb-role-switch" property, take the "role-switch-default-mode"
property into account when deciding which role to put the
controller into.

This makes USB devices work on Apple M1 systems where the device
tree may include a "dr_mode" property that is set to "otg", but
where we need to put the controller into "host" mode to see
devices connected to the type-C ports.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
2022-05-20 09:41:33 +02:00
Peng Fan
8494fe077c imx: toradex/verdin-imx8mm/p: cleanup board watchdog code
pinctrl_wdog already marked u-boot,dm-spl, so clean up board code.

The set_wdog_reset() function is not necessary as this is handled by
the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property
being set.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-05-20 09:30:29 +02:00
Peng Fan
a6924c95d1 imx: verdin-imx8mm/p: cleanup board watchdog code
pinctrl_wdog already marked u-boot,dm-spl, so clean up board code.

The set_wdog_reset() function is not necessary as this is handled by
the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property
being set.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-05-20 09:30:29 +02:00
Peng Fan
09bf8270cf imx: imx8mn_smm_s2: clean up board watchdog code
pinctrl_wdog already marked u-boot,dm-spl, so clean up board code.

The set_wdog_reset() function is not necessary as this is handled by
the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property
being set.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Ariel D'Alessandro <ariel.dalessandro@collabora.com>
2022-05-20 09:30:29 +02:00
Peng Fan
0726bdd460 imx: imx8mm-mx8menlo: drop unneeded watchdog settings
pinctrl_wdog as u-boot,dm-spl already marked in imx8mm-verdin-u-boot.dtsi,

The set_wdog_reset() function is not necessary as this is handled by
the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property
being set.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2022-05-20 09:30:29 +02:00
Peng Fan
a38ed61643 imx: imx8mp_evk: enable pinctrl_wdog in SPL
Mark pinctrl_wdog as u-boot,dm-spl to clean up board code,

The set_wdog_reset() function is not necessary as this is handled by
the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property
being set.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-05-20 09:30:29 +02:00
Peng Fan
ba06ea8991 imx: imx8mm_evk: enable pinctrl_wdog in SPL
Mark pinctrl_wdog as u-boot,dm-spl to clean up board code,

The set_wdog_reset() function is not necessary as this is handled by
the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property
being set.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-05-20 09:30:29 +02:00
Peng Fan
6d5cc90670 imx: imx8mn_evk: enable pinctrl_wdog in SPL
Mark pinctrl_wdog as u-boot,dm-spl to clean up board code,

The set_wdog_reset() function is not necessary as this is handled by
the imx_watchdog.c driver due to the 'fsl,ext-reset-output' property
being set.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-05-20 09:30:29 +02:00
Peng Fan
597514e738 imx: imx8mq-phanbell: enable CONFIG_DM_SERIAL
Marked related nodes as u-boot,dm-spl for serial driver model
Enable CONFIG_DM_SERIAL

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-05-20 09:30:29 +02:00
Peng Fan
1d8c0c2d7b imx: imx8mq-pico: enable CONFIG_DM_SERIAL
Marked related nodes as u-boot,dm-spl for serial driver model
Enable CONFIG_DM_SERIAL

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-05-20 09:30:29 +02:00
Peng Fan
23df340f32 imx: imx8mq-cm: enable CONFIG_DM_SERIAL
Marked related nodes as u-boot,dm-spl for serial driver model
Enable CONFIG_DM_SERIAL

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-05-20 09:30:29 +02:00
Peng Fan
56f3888b43 imx: dts: move common changes to imx8mq-u-boot.dtsi
Move some common changes to imx8mq-u-boot.dtsi, so others could reuse it

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-05-20 09:30:29 +02:00
Peng Fan
6ea118ef9a imx: imx8mm_edm_sbc: Enable SPL_DM_SERIAL
Enable CONFIG_SPL_DM_SERIAL. uart and its pinmux was already
marked with u-boot,dm-spl.
Move preloader_console_init after spl_early_init to make sure driver
model work.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-05-20 09:30:28 +02:00
Peng Fan
2232d5f5b7 imx: imx8mm_mx8menlo: Enable DM_SERIAL
Enable CONFIG_DM_SERIAL. uart2 and its pinmux was already
marked with u-boot,dm-spl.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-05-20 09:30:28 +02:00
Tim Harvey
d003d89372 board: gateworks: gw_ventana: remove obsolete file
commit 61cf225053 ("board: gateworks: gw_ventana: use comomn GSC driver")
moved to the common GSC driver and moved remaining board-specific
functions to eeprom.c. The functions in gsc.c are no longer used and it
was removed from the Makefile but the file itself was not removed.
Remove it now.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2022-05-20 09:30:28 +02:00
Tim Harvey
0cba71c1eb board: gateworks: gw_ventana: add support for GPY111 PHY
The MaxLinear GPY111 PHY is being used on some boards due to part
availability. Add support for this PHY which requires a longer reset
post-delay and RGMII delay configuration.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2022-05-20 09:30:28 +02:00
Tim Harvey
6fc639461b board: gateworks: venice: enable SPL_DM_SERIAL
The uart2 and its pinmux are already marked with u-boot,dm-spl but we
need to move the call to preloader_console_init() after spl_early_init()
to avoid a board hang as dm can't be used until after spl_early_init()
due to the uart driver not enabling the uart clock.

Remove the manual config of the UART pinmux now that it is no longer
needed.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2022-05-20 09:30:28 +02:00
Tim Harvey
8e3cc42a3f configs: remove FEC_QUIRK_ENET_MAC from imx8m configs
FEC_QUIRK_ENET_MAC is defined in the imx-regs.h include file and thus
does not need to be defined in the various board config includes.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2022-05-20 09:30:28 +02:00
Tim Harvey
110998f3c6 configs: imx8mp_venice: add FEC_QUIRK_ENET_MAC
The IMX8MP SoC FEC needs to have the FEC_QUIRK_ENET_MAC defined.

Fixes: commit 2395625209 ("board: gateworks: venice: add imx8mp-venice-gw740x support")
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2022-05-20 09:30:28 +02:00
Tim Harvey
400eebf10d configs: imx8m{m, n}_venice: remove unneeded CONFIG_FEC_MXC_PHYADDR
The IMX8M based Venice boards all have device-tree fec nodes that
use proper dt with a phy-handle pointing to a phy with reg assigned
to the proper phy address.

There is no need to keep using the CONFIG_FEC_MXC_PHYADDR hack when
a proper dt is used - remove it.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2022-05-20 09:30:28 +02:00
Peng Fan
a1d675ac77 imx: imx8m: drop uneeded check
All i.MX8M needs TZASC ID SWAP set and locked, no need the check to
waste cpu cycles.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
2022-05-20 09:30:28 +02:00
Peng Fan
5dd9db8f7d imx: imx8m: add rproc_att
With rpoc_att, bootaux able to kick elf file for M core

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-05-20 09:30:28 +02:00
Peng Fan
40153df63a imx: bootaux: get stack from elf file
To i.MX8, M core stack is pre-coded in source code, so need to get it
before kicking M core. The stack pointer is stored in the first word of
the first PT_LOAD section __isr_vector. So use a num to index the
section loading.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-05-20 09:30:28 +02:00
Peng Fan
fd60a87e75 imx: bootaux: add missing newline
Add missing newline

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-05-20 09:30:28 +02:00
Peng Fan
56c2dbdaba imx: bootaux: cleanup code
Use if (CONFIG_IS_ENABLED()) to make code cleaner
Enable elf support for i.MX8M

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-05-20 09:30:28 +02:00
Rasmus Villemoes
290ffe5788 imx8m: fix reading of DDR4 MR registers
I was trying to employ lpddr4_mr_read() to something similar to what
the imx8mm-cl-iot-gate board is doing for auto-detecting the RAM
type. However, the version in drivers/ddr/imx/imx8m/ddrphy_utils.c
differs from the private one used by that board in how it extracts the
byte value, and I was only getting zeroes. Adding a bit of debug
printf'ing gives me

 tmp = 0x00ffff00
 tmp = 0x00070700
 tmp = 0x00000000
 tmp = 0x00101000

and indeed I was expecting a (combined) value of 0xff070010 (0xff
being Manufacturer ID for Micron). I can't find any documentation that
says how the values are supposed to be read, but clearly the iot-gate
definition is the right one, both for its use case as well as my
imx8mp-based board.

So lift the private definition of lpddr4_mr_read() from the
imx8mm-cl-iot-gate board code to ddrphy_utils.c, and add a declaration
in the ddr.h header where e.g. get_trained_CDD() is already declared.

This has only been compile-tested for the imx8mm-cl-iot-gate
board (since I don't have the hardware), but since I've merely moved
its definition of lpddr4_mr_read(), I'd be surprised if it changed
anything for that board.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Tested-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-05-20 09:30:28 +02:00
Marek Vasut
c329f9349b ARM: imx: imx31: Introduce and use UART_BASE_ADDR(n)
Introduce helper macro UART_BASE_ADDR(n), which returns Nth UART base
address. Convert all board configurations to this new macro. This is the
first step toward switching CONFIG_MXC_UART_BASE to Kconfig. This is a
clean up, no functional change.

The new macro contains compile-time test to verify N is in suitable
range. The test works such that it multiplies constant N by constant
double-negation of size of a non-empty structure, i.e. it multiplies
constant N by constant 1 in each successful compilation case.

The non-empty structure may contain C11 _Static_assert(), make use of
this and place the kernel variant of static assert in there, so that
it performs the compile-time check for N in the correct range. Note
that it is not possible to directly use static_assert in compound
statements, hence this convoluted construct.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2022-05-20 09:03:01 +02:00
Marek Vasut
be23774ed1 ARM: imx: imx27: Introduce and use UART_BASE_ADDR(n)
Introduce helper macro UART_BASE_ADDR(n), which returns Nth UART base
address. Convert all board configurations to this new macro. This is the
first step toward switching CONFIG_MXC_UART_BASE to Kconfig. This is a
clean up, no functional change.

The new macro contains compile-time test to verify N is in suitable
range. The test works such that it multiplies constant N by constant
double-negation of size of a non-empty structure, i.e. it multiplies
constant N by constant 1 in each successful compilation case.

The non-empty structure may contain C11 _Static_assert(), make use of
this and place the kernel variant of static assert in there, so that
it performs the compile-time check for N in the correct range. Note
that it is not possible to directly use static_assert in compound
statements, hence this convoluted construct.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2022-05-20 09:03:01 +02:00
Marek Vasut
52b6b480db ARM: imx: imx8m: Introduce and use UART_BASE_ADDR(n)
Introduce helper macro UART_BASE_ADDR(n), which returns Nth UART base
address. Convert all board configurations to this new macro. This is the
first step toward switching CONFIG_MXC_UART_BASE to Kconfig. This is a
clean up, no functional change.

The new macro contains compile-time test to verify N is in suitable
range. The test works such that it multiplies constant N by constant
double-negation of size of a non-empty structure, i.e. it multiplies
constant N by constant 1 in each successful compilation case.

The non-empty structure may contain C11 _Static_assert(), make use of
this and place the kernel variant of static assert in there, so that
it performs the compile-time check for N in the correct range. Note
that it is not possible to directly use static_assert in compound
statements, hence this convoluted construct.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2022-05-20 09:03:01 +02:00
Fabio Estevam
16ee0f2afd mx6sllevk: Remove duplicated "mmc dev" command
The "mmc dev ${mmcdev}" command is done twice.

Remove one ocurrence to avoid the duplication.

Signed-off-by: Fabio Estevam <festevam@denx.de>
2022-05-19 21:39:36 +02:00
Fabio Estevam
3df5f19836 mx6slevk: Remove duplicated "mmc dev" command
The "mmc dev ${mmcdev}" command is done twice.

Remove one ocurrence to avoid the duplication.

Signed-off-by: Fabio Estevam <festevam@denx.de>
2022-05-19 21:39:36 +02:00
Gaurav Jain
db74ced5df i.MX8 crypto/fsl: Enable fsl CAAM rng driver
rng driver enabled to read random number using caam.

Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
2022-05-19 21:39:36 +02:00
Marek Vasut
ff04a0944d ARM: dts: imx: Use 100 kHz I2C2 on Data Modul i.MX8M Mini eDM SBC
The I2C2 has SMBus device SMSC USB2514Bi connected to it, the device is
capable of up to 100 kHz operation. Reduce the bus frequency to 100 kHz
to guarantee this I2C device can work correctly.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2022-05-19 21:39:36 +02:00
Fabio Estevam
d175982c20 imx8mn/8mp: Allow booting via USB
When trying to boot via USB on i.MX8MN it is necessary to specify
the U-Boot environment location, otherwise the boot process simply
hangs.

Specify the environment location when booting from USB.

Tested on a imx8mn-evk.

Suggested-by: Michael Nazzareno Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Fabio Estevam <festevam@denx.de>
Tested-By: Tim Harvey <tharvey@gateworks.com>
2022-05-19 21:39:36 +02:00
Fabio Estevam
7038156447 imx8mn_ddr4_evk: Add USB Mass Storage support
Add USB Mass Storage support, which is a convenient way to flash
the eMMC card, for example.

Signed-off-by: Fabio Estevam <festevam@denx.de>
2022-05-19 21:39:36 +02:00
Gaurav Jain
0c45c77b8a i.MX6SX: crypto/fsl: fix entropy delay value
RNG Hardware error is reported due to incorrect entropy delay

rng self test are run to determine the correct ent_dly.
test is executed with different voltage and temperature to identify the
worst case value for ent_dly. after adding a margin value(1000),
ent_dly should be at least 12000.

Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-05-19 21:39:36 +02:00
Ye Li
9fd406de52 mtd: rawnand: mxs_nand: Fix use_minimum_ecc for spl driver
Because mxs_nand_spl driver does not support DM, to use the minimum ECC
layout, it needs to handle the CONFIG_NAND_MXS_USE_MINIMUM_ECC.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Han Xu <han.xu@nxp.com>
2022-05-19 21:39:36 +02:00
Patrice Chotard
b6a469360a spi: stm32_qspi: Remove SR_BUSY bit check before sending command
Waiting for SR_BUSY bit when receiving a new command is not needed.
SR_BUSY bit is already managed in the previous command treatment.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-05-19 18:54:18 +02:00
Patrice Chotard
a6d7eeb66d spi: stm32_qspi: Always check SR_TCF flags in stm32_qspi_wait_cmd()
Currently, SR_TCF flag is checked in case there is data, this criteria
is not correct.

SR_TCF flags is set when programmed number of bytes have been transferred
to the memory device ("bytes" comprised command and data send to the
SPI device).
So even if there is no data, we must check SR_TCF flag.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-05-19 18:54:18 +02:00
Marek Vasut
0adf10a87b ARM: dts: stm32: Configure Buck3 voltage per PMIC NVM on Avenger96
The Avenger96 board comes in multiple regulator configurations.
 - rev.100 or rev.200 have Buck3 preconfigured to 3V3 operation on
   boot and contains extra Enpirion EP53A8LQI DCDC converter which
   supplies the IO. Reduce Buck3 voltage to 2V9 to not waste power.
 - rev.200L have Buck3 preconfigured to 1V8 operation and have no
   Enpirion EP53A8LQI DCDC anymore, the IO is supplied from Buck3.

Configure the Buck3 voltage on this board per PMIC NVM settings and
update buck3 voltage limits in DT passed to OS before booting OS to
prevent potential hardware damage.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-05-19 18:48:50 +02:00
Tom Rini
f83bd23e2a Merge https://source.denx.de/u-boot/custodians/u-boot-marvell
- Misc Kconfig cleanups (Chris & Pali)
- turris_omnia: Fix hangup in debug UART (this introduces
  TPL/SPL_DEBUG_UART_BASE) Pali
- mvebu: uDPU: include fixed-phy support (Robert)
- pinctrl: probe pinctrl drivers during post-bind (Robert)
2022-05-18 08:41:13 -04:00
Michal Simek
11ed38f5dc arm64: zynqmp: Add DT description for si5328 for zcu102/zcu106
Origin DT binding just specify driver but wasn't aligned with DT binding
which came later. Extend description for zcu102 and zcu106 to cover latest
binding.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/db66a4bb501183ffbd033da4dd263afdb214f8ec.1652262769.git.michal.simek@amd.com
2022-05-18 13:17:54 +02:00
Michal Simek
d5b9b22f7b arm64: zynqmp: Add linux,code for fwuen button
BTN_MISC looks like the most reasonable option for this button.
Button is used by firmware to indicate (after reset, power up) that user
wants to do firmware upgrade via firmware update utility.
For bootloader or OS is this just user button which is worth to have it
mapped.
Also button can be used as a wakeup source and pressing it for more time
can generate more chars that's why also adding wakeup-source and autorepeat
properties.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Link: https://lore.kernel.org/r/7f6d627473632c3c3036ec9f6aaa36e00f4615e2.1652262769.git.michal.simek@amd.com
2022-05-18 13:17:54 +02:00
Michal Simek
e4f1d2881e arm64: zynqmp: Add PHY description for SGMII on vck190 SC
SGMII requires phy to be configured. The support for this has been added to
Linux and U-Boot already that's why also describe the phy via DT. Clock is
coming from si5332 chip (output 1) 125MHz which is only one GT line use on
this board.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/8ad8d0c2fc9690cc90f95feddf87b0e94a685a43.1652262769.git.michal.simek@amd.com
2022-05-18 13:17:54 +02:00
T Karthik Reddy
725badc5a2 Revert "arm64: zynqmp: Add zynqmp firmware specific DT nodes"
This reverts commit 50a6bd000f.

As zynqmp mini emmc does not rely on firmware, remove firmware related
device tree modes from zynqmp mini emmc dts files.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Acked-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/e69b30d82b0307c563fe72630d9172e53964aeda.1652262769.git.michal.simek@amd.com
2022-05-18 13:17:54 +02:00
Michal Simek
dda356db64 arm64: zynqmp: Add dmas, gpu, rtc, watchdogs and opp nodes for SOM
There are couple of IPs which are enabled in origin HW design which are
missing in SOM dt. Add them to match default setup.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/901401beacbea5931fc18cde20c157e5978a7023.1652262769.git.michal.simek@amd.com
2022-05-18 13:17:54 +02:00
Vishal Patel
07f8e78af0 arm64: zynqmp: Add pwm-fan node and fix ttc0 pwm-cells property
Add pwm-fan node to control fan through hwmon and change
pwm-cells property to 3 to allow fancontrol utility to
function correctly.

Signed-off-by: Vishal Patel <vishal.patel@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/21b4dfce3e45136a468974ea3dedca03320e27b8.1652262769.git.michal.simek@amd.com
2022-05-18 13:17:54 +02:00
Michal Simek
d59fac2f3f arm64: zynqmp: Add power domain description for PL
PL has own power domain which is not described in DT. That's why add it
there by default.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/b38e2ea95dab434bc007f9ed6c438c68149744bf.1652262769.git.michal.simek@amd.com
2022-05-18 13:17:54 +02:00
Michal Simek
234f8be568 arm64: zynqmp: Fix opp-table-cpu
OPP table name now should start with "opp-table" and OPP entries
shouldn't contain commas and @ signs in accordance to the new schema
requirement.

The same change was done in Linux by commit c6d4a8977598 ("ARM: tegra:
Rename CPU and EMC OPP table device-tree nodes"), commit ffbe853a3f5a
("ARM: dts: sunxi: Fix OPPs node name") or commit b7072cc5704d ("arm64:
dts: qcom: qcs404: Rename CPU and CPR OPP tables").

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/a1176349448df35127dbac15c1eeb2229505bae7.1652262769.git.michal.simek@amd.com
2022-05-18 13:17:54 +02:00
Michal Simek
e7b390024c arm64: zynqmp: Add gpio labels for modepin
Using labels helps with better identifications of chips.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/15b0f68077fb3c86d438caf8562de87367361c60.1652262769.git.michal.simek@amd.com
2022-05-18 13:17:54 +02:00
Piyush Mehta
a4180c3696 arm64: zynqmp: Add mode-pin GPIO controller DT node
Add mode-pin GPIO controller DT node in zynqmp.dtsi and also setup default
reset-gpios property for usb which is default Xilinx setup.

Signed-off-by: Piyush Mehta <piyush.mehta@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/f2a1f6f541c41075ea36062857031bfc28d6d303.1652262769.git.michal.simek@amd.com
2022-05-18 13:17:54 +02:00
Neal Frager
6be41ea4e6 arm64: zynqmp: zynqmp-sm-k26-revA: Fix DP PLL configuration
This patch fixes the DP audio and video PLL configurations for the zynqmp-sm-k26-revA som.

The Linux DP driver expects the DP to be using the following PLL config:
  - DP video PLL should use the VPLL (0x0)
  - DP audio PLL should use the RPLL (0x3)
  - DP system time clock PLL should use RPLL (0x3)

Register 0xFD1A0070 configures the DP video PLL.
Register 0xFD1A0074 configures the DP audio PLL.
Register 0xFD1A007C configures the DP system time clock PLL.

Signed-off-by: Neal Frager <neal.frager@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/fa7e9abc419c9d7648405d1c62367dbe701d09b8.1652709736.git.michal.simek@amd.com
2022-05-18 13:17:54 +02:00
Ashok Reddy Soma
e9869f474c phy: zynqmp: Increase timeout value to 10ms
Observing psgtr pll timeouts with some usb hubs and devices behind it.
Increase timeout to 10ms to take care of it.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/20220510131234.2650-1-ashok.reddy.soma@xilinx.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-05-18 13:17:54 +02:00
Amit Kumar Mahapatra
6e38e2ea79 arm64: zynqmp: Set qspi tx-buswidth to 4
In all the ZynqMP boards dts files tx-buswidth is by default set to 1. Due
to this the framework only issues 1-1-1 write commands to the GQSPI driver.
But the GQSPI controller is capable of handling 1-4-4 write commands, so
updated the tx-buswidth to 4 in ZynqMP boards dts files. This would enable
the spi-nor framework to issue 1-4-4 write commands instead of 1-1-1. This
will increase the tx data transfer rate, as now the tx data will be
transferred on four lines instead on single line.

Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/ad61199f55e5e00f29de6206d9d1872a52a7657e.1652193179.git.michal.simek@amd.com
2022-05-18 13:17:18 +02:00
Michal Simek
10c29fa1cc xilinx: zynqmp: Do not guard SPL_FS_LOAD_PAYLOAD_NAME by SDHCI driver
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME is used by set_dfu_alt_info() for string
generation. It doesn't depend on SDHCI because the same file can be stored
to other non volatile memories like qspi.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/97434e122c6f8f042330b60d3e8de4c31f3e3f93.1652192580.git.michal.simek@amd.com
Link: https://lore.kernel.org/r/718de136c68c9a76fc7b4e536a727f401b05bfb9.1652702625.git.michal.simek@amd.com
2022-05-18 13:17:18 +02:00
Neal Frager
67bdaa0165 arm64: zynqmp: Fix split mode reset functionality
This patch fixes two issues in the set_r5_reset function.

1. When in split mode, the lpd_amba_rst bit should only be set when
both r5 cpu cores are in reset. Otherwise, if one r5 core is still
running, setting the lpd_amba_rst bit will cause an error for the
running core. The set_r5_reset function has been modified to check
if the other r5 core is still running before setting the lpd_amba_rst
bit.

2. The cpu_disable function was always assuming that the r5 cores
are in split mode when resetting either core 4 or 5. This is
incorrect for lockstep functionality. This patch adds a function
check_r5_mode to handle the cpu_disable function correctly for
the r5 cores by checking the mode and handling the reset appropriately.

Signed-off-by: Neal Frager <neal.frager@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/d99cbd7f2394ac055ef27457298f554ff0747ba7.1651648344.git.michal.simek@amd.com
2022-05-18 13:17:18 +02:00
Neal Frager
2946c551f1 arm64: zynqmp: zynqmp-zcu102-revA: Fix DP PLL configuration
This patch fixes the DP audio and video PLL configurations for the
zynqmp-zcu102-revA evaluation board.

The Linux DP driver expects the DP to be using the following PLL config:
  - DP video PLL should use the VPLL (0x0)
  - DP audio PLL should use the RPLL (0x3)

Register 0xFD1A0070 configures the DP video PLL.
Register 0xFD1A0074 configures the DP audio PLL.

Signed-off-by: Neal Frager <neal.frager@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/b2eb87758e0cd4844e1754da8c58fce58d9cf683.1651740949.git.michal.simek@amd.com
2022-05-18 13:17:18 +02:00
Neal Frager
a3659640e0 arm64: zynqmp: zynqmp-zcu106-revA: Fix DP PLL configuration
This patch fixes the DP audio and video PLL configurations
for the zynqmp-zcu106-revA evaluation board.

The Linux DP driver expects the DP to be using the following PLL config:
  - DP video PLL should use the VPLL (0x0)
  - DP audio PLL should use the RPLL (0x3)

Register 0xFD1A0070 configures the DP video PLL.
Register 0xFD1A0074 configures the DP audio PLL.

Signed-off-by: Neal Frager <neal.frager@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/62538b4a04dee28a6fc8ac5b85f8c845a5a76aa4.1651740988.git.michal.simek@amd.com
2022-05-18 13:17:18 +02:00
Neal Frager
80b8bbbf98 arm64: zynqmp: zynqmp-zcu106-rev1.0: Fix DP PLL configuration
This patch fixes the DP audio and video PLL configurations for the zynqmp-zcu106-rev1.0 evaluation board.

The Linux DP driver expects the DP to be using the following PLL config:
  - DP video PLL should use the VPLL (0x0)
  - DP audio PLL should use the RPLL (0x3)

Register 0xFD1A0070 configures the DP video PLL.
Register 0xFD1A0074 configures the DP audio PLL.

Signed-off-by: Neal Frager <neal.frager@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/ae42ad6185418713a473660c8d15903299af7764.1652192319.git.michal.simek@amd.com
2022-05-18 13:17:18 +02:00
Robert Marko
f9ec791b5e pinctrl: probe pinctrl drivers during post-bind
Currently, pinctrl drivers only get probed if pinconf is actually being
used, however on SoC-s like Armada 3720 pinctrl driver is a also the GPIO
driver.

So, if the pinctrl driver doesn't get probed GPIO-s won't get registered
and thus they cannot be used.

This is a problem on the Methode eDPU as it just uses SB pins as GPIO-s
and without them being registered networking won't work as it only has
one SFP slot and the TX disable GPIO is on the SB controller.

So, probe the pinctrl drivers using DM_FLAG_PROBE_AFTER_BIND like LED
uclass does.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Reviewed-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-05-17 06:44:06 +02:00
Robert Marko
c7111e6ffd mvebu: uDPU: include fixed-phy support
uDPU relies on using fixed-phy for the SFP support, and since the
fixed-phy parsing was moved to the generic driver instead of mvneta
networking stopped working on uDPU with:
uDPU>> dhcp
dm_eth_phy_connect failed

This is due to the conversion commit not enabling fixed-phy support
in defconfig like it did for other boards.

Fixes: 77fcf3cf12 ("net: mvneta: Convert to use PHY_FIXED for fixed-link")
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-05-17 06:44:06 +02:00
Pali Rohár
29dd6e475a arm: mvebu: turris_{omnia,mox}: Enable CONFIG_NETCONSOLE
This allows to use U-Boot console on Turris devices via network.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-05-17 06:44:06 +02:00
Pali Rohár
5be172819f arm: mvebu: Fix DEBUG_UART_BASE for all 32-bit boards
UART base address is located in internal registers.

Internal registers for 32-bit mvebu boards in SPL are at address 0xd0000000
and in proper U-Boot at address 0xf1000000.

Fix DEBUG_UART_BASE option for all 32-bit mvebu boards.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-05-17 06:44:06 +02:00
Pali Rohár
2418c1f56f arm: mvebu: turris_omnia: Fix DEBUG_UART_BASE
Internal registers in SPL are at address 0xd0000000 and in proper U-Boot at
address 0xf1000000. UART base address is located in internal registers.

Fix DEBUG_UART_BASE option to correct value for both SPL and proper U-Boot.

This change fixes hangup of proper U-Boot when it is trying to print
something via debug UART.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-05-17 06:44:06 +02:00
Pali Rohár
d293759d55 serial: ns16550: Add support for SPL_DEBUG_UART_BASE
Use CONFIG_VAL(DEBUG_UART_BASE) instead of CONFIG_DEBUG_UART_BASE, so
proper config value (CONFIG_DEBUG_UART_BASE or CONFIG_SPL_DEBUG_UART_BASE)
is used based on building target.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-05-17 06:44:06 +02:00
Pali Rohár
958789f026 serial: Add new config option TPL_DEBUG_UART_BASE
TPL_DEBUG_UART_BASE is same as DEBUG_UART_BASE, but applies only for TPL.

Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Stefan Roese <sr@denx.de>
2022-05-17 06:44:06 +02:00
Pali Rohár
9f971ff714 serial: Add new config option SPL_DEBUG_UART_BASE
SPL_DEBUG_UART_BASE is same as DEBUG_UART_BASE, but applies only for SPL.

In some cases base address of UART is different in SPL and proper U-Boot.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-05-16 11:31:34 +02:00
Pali Rohár
5bb2c550b1 arm: mvebu: Move internal registers in arch_very_early_init() function
Moving of internal registers from INTREG_BASE_ADDR_REG to SOC_REGS_PHY_BASE
needs to be done very early, prior calling any function which may touch
internal registers, like debug_uart_init().

So do it earlier in arch_very_early_init() instead of arch_cpu_init().

Movement is done in proper U-Boot, not in SPL. SPL may return to bootrom
and bootrom requires internal registers at (old) expected location.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-05-16 11:31:34 +02:00
Pali Rohár
948da7773e arm: Add new config option ARCH_VERY_EARLY_INIT
When this option is set then ARM _main() function would call
arch_very_early_init() function at the beginning. It would be before
calling any other functions like debug_uart_init() and also before
initializing C runtime environment.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-05-16 11:31:33 +02:00
Chris Packham
1001a0ab46 arm: mvebu: Remove unused ARMADA_64BIT
Nothing selects ARMADA_64BIT. Instead the 64-bit SoCs just select ARM64
directly. Remove the unused config item.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-05-16 11:31:33 +02:00
Pali Rohár
008468fa35 cmd: mvebu: Hide bubt specific options when bubt is disabled
CONFIG_MVEBU_NAND_BOOT, CONFIG_MVEBU_SPI_BOOT, CONFIG_MVEBU_MMC_BOOT and
CONFIG_MVEBU_UBOOT_DFLT_NAME are unused when CONFIG_CMD_MVEBU_BUBT is not
enabled. So hide them.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-05-16 11:31:33 +02:00
T Karthik Reddy
155353234e mmc: zynq_sdhci: Add weak function prototype
zynqmp_pm_is_function_supported() which checks feature support on som,
which is implemented in firmware_zynqmp.c driver. As mini configuration
does not use firmware driver, so create a weak function to avoid
compilation error on zynqmp mini configuration.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Acked-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/c60655a509956b8fc3a81671a7dc51157f3973db.1651048030.git.michal.simek@xilinx.com
2022-05-13 09:10:02 +02:00
T Karthik Reddy
1720336d3c Revert "arm64: xilinx: Set CONFIG_ZYNQMP_FIRMWARE config for mini emmc"
This reverts commit 122ca834f2.

Disable CONFIG_ZYNQMP_FIRMWARE config from zynqmp & versal mini emmc
defconfig files, as mini emmc does not use any firmware.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Acked-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/f73a50980d3af894f1e86cfc98742dbdec573760.1651048242.git.michal.simek@xilinx.com
2022-05-13 09:10:02 +02:00
Michal Simek
9c563e916c xilinx: Handle board_get_usable_ram_top(0) properly
board_get_usable_ram_top() was designed for getting the top most location
for U-Boot allocation that's why function itself supports via total_size
parameter to find out where the right location for U-Boot is.
But function itself is also reused by different (EFI) which is passing
total_size as 0 to find out where the usable ram top is. For this case
doesn't make sense (a waste time) to call any lmb functions.
That's why simply return gd->ram_top.

And gd->ram_top is filled already based on previous call for U-Boot iself.
The same solution is also used by stm32mp by commit 92b611e8b0 ("stm32mp:
correctly handle board_get_usable_ram_top(0)") and commit c8510e397f
("stm32mp: Fix board_get_usable_ram_top()").

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/44470619e74f3e480b70deac24578e3e0d5c907e.1651225945.git.michal.simek@amd.com
2022-05-13 09:10:02 +02:00
Michal Simek
303198e26d soc: xilinx: zynqmp: fix out of bounds array access
The call to xilinx_pm_request requires an array of a larger size.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/5f1409de285d7454af171a54e5f115da9d82c44e.1650440343.git.michal.simek@xilinx.com
2022-05-13 09:10:02 +02:00
Jorge Ramirez-Ortiz
9b31e109b2 soc: xilinx: versal: fix out of bounds array access
The call to xilinx_pm_request requires an array of a larger size.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Link: https://lore.kernel.org/r/20220416181530.2311155-1-jorge@foundries.io
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2022-05-13 09:10:02 +02:00
Tom Rini
c387e62614 Merge branch '2022-05-11-Kconfig-cleanups-etc'
- Migrate CONFIG_MTD_CONCAT to Kconfig, use CONFIG_VAL/IS_ENABLED in
  more places, rename SPL_LEGACY_IMAGE_SUPPORT to
  SPL_LEGACY_IMAGE_FORMAT and update some related dependencies for TI
  platforms.
2022-05-11 13:27:44 -04:00
Ralph Siemsen
db26c507c9 Makefile: update warning about CONFIG_OF_EMBED
Update the diagnostic message with revised location of document, which
changed in 3e9fddfc4f ("doc: Move devicetree control doc to rST")

Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
2022-05-11 09:22:24 -04:00
Ovidiu Panait
13ae36cc8d board_r: use IS_ENABLED(CONFIG_NEEDS_MANUAL_RELOC) in board_init_r()
Drop CONFIG_NEEDS_MANUAL_RELOC ifdefs in board_init_r() and use
IS_ENABLED() instead. Also, use the MANUAL_RELOC() macro to update the
initcall pointers.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
2022-05-11 09:22:24 -04:00
Chris Packham
54a54a6313 Convert CONFIG_MTD_CONCAT to Kconfig
This converts the following to Kconfig:
  CONFIG_MTD_CONCAT

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-05-11 09:22:24 -04:00
Rasmus Villemoes
cff2963693 common/console.c: use CONFIG_VAL() with PRE_CON_BUF_* variables
There is currently no support for PRE_CONSOLE_BUFFER in SPL, but if
and when that gets implemented, one would almost certainly want to use
a different address and/or size for the buffer (e.g., U-Boot proper
might specify an address in DRAM and a generous buffer, while SPL
would be much more constrained).

So a prerequisite for adding SPL_PRE_CONSOLE_BUFFER is to make the
code use SPL_-specific values. No functional change.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2022-05-11 09:22:24 -04:00
Andrew Davis
042e87e835 boot: Kconfig: Enable FIT processing by default on TI secure devices
TI secure devices chain-of-trust depends on FIT image processing,
enable it by default on these devices. This also reduces the delta
between the secure and non-secure defconfig files.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-05-11 09:22:24 -04:00
Andrew Davis
52dc3343fd boot: Kconfig: Disable non-FIT loading for TI secure devices
Non-FIT image loading support should be disabled for TI secure
devices as the image handlers for those image types do not follow
our secure boot checks.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-05-11 09:22:24 -04:00
Andrew Davis
11f32da79f spl: Force disable non-FIT loading for TI secure devices
Booting of non-FIT images bypass our chain-of-trust boot flow,
these options should not be allowed when high security is set.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-05-11 09:22:24 -04:00
Andrew Davis
6665ab1795 spl: Rename Kconfig SPL_LEGACY_IMAGE_SUPPORT to SPL_LEGACY_IMAGE_FORMAT
This matches what this support is called in the non-SPL case. The postfix
_SUPPORT is redundant as enabling Kconfig options implies support.
With this we can use CONFIG_IS_ENABLED() as needed.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-05-11 09:22:24 -04:00
Tom Rini
21e25992c8 Merge tag 'u-boot-stm32-20220510' of https://source.denx.de/u-boot/custodians/u-boot-stm
Add new STM32 MCU boards and Documentation
STM32 programmer improvements
video: support several LTDC HW versions and fix data enable polarity
board: fix stboard error message, consider USB cable connected when boot device is USB
configs: stm32mp1: set console variable for extlinux.conf
configs: stm32mp1: add support for baudrate higher than 115200 for ST-Link
ARM: stm32mp: Fix Silicon version handling and ft_system_setup()
phy: stm32-usbphyc: Add DT phy tuning support
arm: dts: stm32mp15: alignment with v5.18
ram: Conditionally enable ASR
mach-stm32mp: psci: retain MCUDIVR, PLL3CR, PLL4CR, MSSCKSELR across suspend
configs: Use TFTP_TSIZE on DHSOM and STMicroelectronics boards
ARM: stm32: Use default CONFIG_TFTP_BLOCKSIZE on DHSOM
pinctrl: stm32: rework GPIO holes management
2022-05-10 15:28:02 -04:00
Tom Rini
b4eb577663 Merge tag 'i2c-2022-07' of https://source.denx.de/u-boot/custodians/u-boot-i2c
i2c changes for 2022.07

- i2c: ihs: intel: Fix typo in comments
  Patch from Michal

- misc: atsha204a: Add support for atsha204 chip
  from Pali
2022-05-10 09:52:00 -04:00
Sean Anderson
381277410d misc: Fix always compiling MISC even for SPL/TPL
We should only build support for misc if the appropriate SPL/TPL symbol
is defined. To ease the transition, make SPL/TPL_MISC default to MISC.
This is necessary because many drivers don't specify their dependencies
properly. These defaults can be removed once all drivers depend on the
appropriate config.

Fixes: aaba703fd0 ("spl: misc: Allow misc drivers in SPL and TPL")
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
[trini: Add VPL_MISC symbol, handle like SPL/TPL_MISC]
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-05-10 09:51:50 -04:00
Patrice Chotard
e198d4fe7c doc: Add documentation for STM32 MCUs
Add documentation for STM32 MCUs (F4, F7 and H7 series).

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-05-10 13:56:12 +02:00
Patrice Chotard
eda7b6a632 configs: stm32746g-eval: Add stm32746g-eval_spl_defconfig
Add stm32746g-eval_spl_defconfig for stm32746g evaluation board to
build SPL.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-05-10 13:56:12 +02:00
Patrice Chotard
e9881a1e75 configs: stm32746g-eval: Add stm32746g-eval_defconfig
Add stm32746g-eval_defconfig for stm32746g evaluation board to
build U-Boot proper.

Full board description can be found here :
https://www.st.com/en/evaluation-tools/stm32746g-eval.html

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-05-10 13:56:12 +02:00
Patrice Chotard
7aa4b4523f configs: stm32f746-disco: use CONFIG_DEFAULT_DEVICE_TREE as fdtfile
As stm32f46-disco, stm32f769-disco and stm32746g-eval are very similar
except their respective device tree file. These 3 boards uses the same
TARGET_STM32F746_DISCO flag (so same include/configs/stm32f746-disco.h
and same board file board/st/stm32f746-disco/stm32f746-disco.c)

To be able to compile these 3 boards, replace the hard-coded device-tree
name in include/configs/stm32f746-disco.h by CONFIG_DEFAULT_DEVICE_TREE
which is set in each board defconfig file with the correct value.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-05-10 13:56:12 +02:00
Patrice Chotard
16613edbc1 board: stm32f746-disco: Fix dram_init() in none SPL config
Replace CONFIG_SUPPORT_SPL by CONFIG_SPL_BUILD to allow
dram_init() execution when using none SPL defconfig
(stm32f746-disco_defconfig).

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-05-10 13:56:12 +02:00
Patrice Chotard
35a15bc12e configs: stm32f746-disco: Migrate SPL flags to defconfig
Migrate SPL flags to stm32f746-disco_spl_defconfig

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-05-10 13:56:12 +02:00
Patrice Chotard
5ff7f0490d configs: stm32f769-disco: Migrate SPL flags to defconfig
Migrate SPL flags to stm32f769-disco_spl_defconfig

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-05-10 13:56:11 +02:00
Patrice Chotard
bad1b79028 configs: stm32f769-disco: Add stm32f769-disco_defconfig
Add stm32f769-disco_defconfig for stm32f769 discovery board to
build U-Boot proper.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-05-10 13:56:11 +02:00
Patrice Chotard
969bc0aece configs: stm32f769-disco: Rename stm32f769-disco_defconfig to stm32f769-disco_spl_defconfig
The current stm32f769-disco_defconfig file supports SPL, rename it to
stm32f769-disco_spl_defconfig to reflect the supported configuration.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-05-10 13:56:11 +02:00
Patrice Chotard
50f48340f0 configs: stm32f746-disco: Add stm32f746-disco_defconfig
Add stm32f746-disco_defconfig for stm32f746 discovery board to
build U-Boot proper.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-05-10 13:56:11 +02:00
Patrice Chotard
0d4ef527da configs: stm32f746-disco: Rename stm32f746-disco_defconfig to stm32f746-disco_spl_defconfig
The current stm32f746-disco_defconfig file supports SPL, rename it to
stm32f746-disco_spl_defconfig to reflect the supported configuration.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-05-10 13:56:11 +02:00
Patrice Chotard
480995b76b configs: stm32f746-disco: Concatenate spl and u-boot binaries
This allows to concatenate spl and u-boot binaries together.
Previously, both binaries has to be flashed separately at the correct
offset (spl at offset 0 and u-boot at offset 0x8000).
With this patch, only one binary is generated (u-boot-with-spl.bin)
and has to be copied in flash at offset 0 using openocd for example
or simply copied in exported mass storage.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-05-10 13:56:11 +02:00
Marek Vasut
05a3a028c1 clk: stm32mp1: Add missing newline
Add missing newline to this debug message, no functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-05-10 13:56:11 +02:00
Patrice Chotard
67899c2201 board: st: stm32mp1: Consider USB cable connected when boot device is USB
Always consider USB cable is connected when USB boot device is detected.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-05-10 13:56:11 +02:00
Patrice Chotard
da6473c0d4 phy: stm32-usbphyc: stm32-usbphyc: Add DT phy tuning support
Add support of phy-tuning properties for sm32-usbphyc's phy tuning
aligned with v5.15 kernel bindings.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-05-10 13:56:07 +02:00
Patrice Chotard
427f452cb9 gpio: stm32_gpio: Rework GPIO hole management
On some STM32 SoC's package, GPIO bank may have hole in their GPIO bank
Example:
  If GPIO bank have 16 GPIO pins [0-15].
  In particular SoC's package case, some GPIO bank can have less GPIO pins:
    - [0-10] => 11 pins;
    - [2-7] => 6 pins.

Commit dbf928dd26 ("gpio: stm32f7: Add gpio bank holes management")
proposed a first implementation by not counting GPIO "inside" hole. GPIO
are not displaying correctly using gpio or pinmux command when GPIO holes
are located at the beginning of GPIO bank.

To simplify, consider that all GPIO have 16 GPIO and use the gpio_ranges
struct to indicate if a GPIO is mapped or not. GPIO uclass offers several
GPIO functions ("input", "output", "unused", "unknown" and "func"), use
"unknown" GPIO function to indicate that a GPIO is not mapped.

stm32_offset_to_index() is no more needed and removed.

This must be reflected using the "gpio" command to indicate to user
that a particular GPIO is not mapped (marked as "unknown") as shown below:

Example for a 16 pins GPIO bank with the [2-7] mapping (only 6 pins
mapped):
GPIOI0          : unknown
GPIOI1          : unknown
GPIOI2          : analog
GPIOI3          : analog
GPIOI4          : alt function 0 push-pull pull-down
GPIOI5          : alt function 0 push-pull pull-down
GPIOI6          : alt function 0 push-pull pull-down
GPIOI7          : analog
GPIOI8          : unknown
GPIOI9          : unknown
GPIOI10         : unknown
GPIOI11         : unknown
GPIOI12         : unknown
GPIOI13         : unknown
GPIOI14         : unknown
GPIOI15         : unknown

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-05-10 13:54:48 +02:00
Patrice Chotard
234b03f3a9 pinctrl: pinctrl_stm32: Use GPIOF_UNKNOWN to indicate not mapped pins
GPIOF_UNKNOWN becomes a valid pin muxing information to indicate
that a pin is not mapped.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-05-10 13:54:48 +02:00
Patrice Chotard
4382e55c42 pinctrl: pinctrl_stm32: Update pinmux_mode definition
pinmux_mode[] is linked to gpio_function[] defined in gpio-uclass.c
So reuse the same gpio_func_t enum value

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-05-10 13:54:48 +02:00
Patrick Delaunay
8202c958cf ARM: stm32: Use CONFIG_TFTP_TSIZE on STMicroelectronics boards
Long TFTP transfers lead to a wall of # characters on UART, which in
the end may slow down the transfer itself. Use CONFIG_TFTP_TSIZE to
print progress in fewer # characters.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-05-10 13:54:48 +02:00
Marek Vasut
6d4619f68c ARM: dts: stm32: Move DHCOR BUCK3 VDD 2V9 adjustment to 1V8 DTSI
The Buck3 on DHCOR is used to supply IO voltage. It can output either 3V3
in the default DHCOR configuration, or 2V9 in case of AV96 DHCOR variant
which has extra Empirion DCDC converter in front of the 1V8 IO supply, or
outright 1V8 in case of 1V8 IO DHCOR without the Empirion DCDC converter.

The 2V9 mode in case of AV96 DHCOR variant is used to reduce unnecessarily
high input voltage to the Empirion DCDC converter, so move it into matching
DTSI to stop confusing users.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-05-10 13:54:47 +02:00
Marek Vasut
473c7d72e4 ARM: stm32: Use CONFIG_TFTP_TSIZE on DHSOM
Long TFTP transfers lead to a wall of # characters on UART, which in
the end may slow down the transfer itself. Use CONFIG_TFTP_TSIZE to
print progress in fewer # characters.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-05-10 13:54:47 +02:00
Marek Vasut
9da04c17a3 ARM: stm32: Use default CONFIG_TFTP_BLOCKSIZE on DHSOM
The DHCOM does ship with KS8851 with 1.5 kiB packet buffer. The DHSOM
may be extended with other MAC options connected to FMC2 bus, like the
DM9000, wih similar limitations. Use default CONFIG_TFTP_BLOCKSIZE of
1468 Bytes instead of 1536 Bytes, which always avoids overflowing the
packet buffers of such limited MACs, which leads to e.g. TFTP timeouts.
This also avoids receiving a short packet fragment at the end of each
TFTP block, which led to reduced performance.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-05-10 13:54:47 +02:00
Marek Vasut
d6ae183965 stm32mp: psci: Retain MCUDIVR, PLL3CR, PLL4CR, MSSCKSELR across suspend
The SoC seems to lose the values of MCUDIVR, PLL3CR, PLL4CR, RCC_MSSCKSELR
during suspend/resume cycle, cache them and reinstate their values on resume.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-05-10 13:54:47 +02:00
Marek Vasut
221869efc3 ram: stm32mp1: Conditionally enable ASR
Enable DRAM ASR, auto self-refresh, conditionally, based on DT PWRCTL
register bits. While ASR does save considerable amount of power at
runtime automatically, it also causes LTDC underruns on large panels.
Let user select whether or not ASR is required or not, generally ASR
should be enabled on portable and battery operated devices.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-05-10 13:54:47 +02:00
Patrick Delaunay
189ec2fee6 arm: dts: stm32mp15: alignment with v5.18
Device tree alignment with Linux kernel v5.18-rc2:
- ARM: dts: stm32: Add support for the emtrion emSBC-Argon
  (only the pincontrol part)
- ARM: dts: stm32: Drop duplicate status okay from DHCOM gpioc node
- ARM: dts: stm32: add st,stm32-sdmmc2 compatible on stm32mp151
- ARM: dts: stm32: fix AV96 board SAI2 pin muxing on stm32mp15
- ARM: dts: stm32: use exti 19 as main interrupt to support RTC wakeup on
  stm32mp157
- ARM: dts: stm32: add DMA configuration to UART nodes on stm32mp151
- ARM: dts: stm32: keep uart4 behavior on *
- ARM: dts: stm32: Correct masks for GIC PPI interrupts on stm32mp15

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-05-10 13:54:47 +02:00
Patrick Delaunay
655af9aa9c ARM: stm32mp: correctly handle Silicon revision
Handle correctly the silicon revision = REV_ID[15:0] of Device Version
and the associated device marking, A to Z on STMicroelectronics STM32MP
SOCs.

This patch prepare the introduction of next STM32MP family,
with STM32MP13x Rev.Z for REV_ID = 1.1.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-05-10 10:56:39 +02:00
Patrick Delaunay
6a69eaf6f4 ARM: stm32mp: skip ft_system_setup when the soc node is absent
The function ft_system_setup shouldn't return an error when the
/soc node is absent in the provided device tree but just skip the
updates.

This patch solves an issue when the U-Boot pytest is executed on board.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-05-10 10:56:39 +02:00
Patrick Delaunay
5367b67be4 configs: stm32mp1: Add support for baudrates higher than 115200 for st-link
On STMicroelectronics boards, the UART can reliably go up to
2000000 bauds when connected to the on-board ST-LINK-V2 for STM32MP15

Unfortunately U-Boot will fall back to 115200 unless higher rates are
declared via CONFIG_SYS_BAUDRATE_TABLE.

This patch add the support of higher baudrates on STMicroelectronics
boards with ST-LINK.

Cc: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-05-10 10:56:39 +02:00
Patrick Delaunay
806c4dd315 configs: stm32mp1: set the console variable for extlinux.conf
Set the environment variable "console", used in extlinux.conf file when it
is generated by YOCTO distribution with:

UBOOT_EXTLINUX_CONSOLE ??= "console=${console},${baudrate}"

With these 2 variables, U-Boot give dynamically the used console and
baudrate in the Linux kernel bootargs.

For the STMicroelectronics boards, the used console is ttySTM0.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-05-10 10:56:39 +02:00
Patrick Delaunay
1494e37586 board: st: common: fix the error messages in stboard command
Add missing \n at the end of the error trace

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-05-10 10:56:39 +02:00
Yannick Fertre
13dc7562b6 video: stm32: stm32_ltdc: support several hardware versions
Register mapping & pixel formats depend on version of ltdc
display controller.

Signed-off-by: Yannick Fertre <yannick.fertre@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-05-10 10:56:39 +02:00
Yannick FERTRE
ef4ce6df32 video: stm32: stm32_ltdc: fix data enable polarity
Wrong DISPLAY_FLAGS used to set the data enable polarity.

Signed-off-by: Yannick FERTRE <yannick.fertre@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-05-10 10:56:39 +02:00
Patrick Delaunay
a9fed5aac5 stm32mp: stm32prog: handle flashlayout without STM32 image header
Accept flashlayout without header in alternate 0, to simplify
the support of stm32prog command with dfu-util.

By default the flashlayout file size is the size of the received binary,
provided with the offset in the DFU alternate.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-05-10 10:56:39 +02:00
Patrick Delaunay
152576a598 stm32mp: stm32prog: handle U-Boot script in flashlayout alternate
Update the stm32prog command to allow the reception of U-Boot script in
the FlashLayout alternate during the first USB enumeration.

This patch is aligned with the last TF-A behavior: the Flashlayout
is now loaded by U-Boot; it is no more present at STM32_DDR_BASE when
the stm32prog is launched after a serial boot, on UART or on USB.

The received script must be a U-Boot legacy image, no more need to add
a stm32image header.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-05-10 10:56:39 +02:00
Patrick Delaunay
7f1121a85a stm32mp: stm32prog: handle interruption during the first enumeration
When an interruption is received during the first USB enumeration
used to received the FlashLayout, with handle ctrl-c, the second
enumeration is not needed and the result for stm32prog_usb_loop
is false (reset is not needed).

This patch avoids the need of a second ctrl to interrupt the command
stm32prog.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-05-10 10:56:39 +02:00
Patrick Delaunay
2a4fe0ee48 stm32mp: stm32prog: add support of UUID for FIP partition
Add support of UUID for FIP parttion, required by Firmware update
support in TF-A:
- UUID TYPE for FIP partition: 19d5df83-11b0-457b-be2c-7559c13142a5
- "fip-a" partition UUID: 4fd84c93-54ef-463f-a7ef-ae25ff887087
- "fip-b" partition UUID: 09c54952-d5bf-45af-acee-335303766fb3

This check is done with a new partition type "FIP" associated
at the FIP UUID.

The A/B partition UUID is detected by the partition name:
"fip-a", "fip-b".

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-05-10 10:56:39 +02:00
Patrick Delaunay
49d0ecb123 stm32mp: stm32prog: add support of STM32IMAGE version 2
Add support of new header for the STM32IMAGE version V2
in command stm32prog command for STM32MP13x family.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-05-10 10:56:39 +02:00
Patrick Delaunay
e82ab4c890 stm32mp: stm32prog: add TEE support in stm32prog command
When OP-TEE is used, the SMC for BSEC management are not
available and the PTA provisioning for OTP must be used.

U-Boot opens the session to this PTA and use it for OTP
access.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-05-10 10:56:39 +02:00
Patrick Delaunay
72450b4b35 stm32mp: stm32prog: add CONFIG_CMD_STM32PROG_OTP
Add a configuration flag CONFIG_CMD_STM32PROG_OTP to enable the support of
OTP update in stm32prog command.

This new configuration allows to deactivate this feature for security reason
and it is a preliminary step for support of OPT update with the OP-TEE
provisioning TA.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-05-10 10:56:39 +02:00
Patrick Delaunay
d983e503c4 stm32mp: stm32prog: fix comment
Fix "partition" in comment.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-05-10 10:56:39 +02:00
Pali Rohár
89eabd2f35 misc: atsha204a: Add support for atsha204 chip
atsha204 chip is predecessor of atsha204a chip. Current U-Boot driver
atsha204a-i2c.c can use both atsha204 and atsha204a chips because it does
not call specific functions to just one of these chips.

So just add compatible string for atsha204.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
2022-05-10 06:48:05 +02:00
Pali Rohár
25965e8613 doc: Add device-tree-bindings for atsha204 and atsha204a
Document trivial bindings for atsha204 and atsha204a.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
2022-05-10 06:47:38 +02:00
Michal Simek
a6cc0b082f i2c: ihs: intel: Fix typo in comments (actual)
s/actucal/actual/g

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2022-05-10 06:47:13 +02:00
Tom Rini
f6973cce6a Merge branch '2022-05-09-TI-platform-updates'
- Assorted minor TI platform updates
2022-05-09 13:40:35 -04:00
Neil Armstrong
28a4c31134 ARM: dts: k3-am642-sk-u-boot: add PMIC node
The E4 revision of the AM64 SKEVM embeds a TPS65219 PMIC,
this adds the PMIC node with the required regulators voltages.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2022-05-09 13:40:24 -04:00
Neil Armstrong
75388a8e21 config: enable TPS65219 for am64x_evm_a53 boards
The E4 revision of the AM64 SKEVM embeds a TPS65219 PMIC,
this enables the necessary options to load and control the
PMIC regulators.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2022-05-09 13:40:24 -04:00
Neil Armstrong
411502ccb8 regulator: add driver for the TPS65219 BUCK & LDO regulators
The TPS65219 I2S PMIC features 3 Buck converters and 4 linear regulators,
2 GPOs, 1 GPIO, and 3 multi-function-pin.

This adds the driver for the Buck converters & linear regulators.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2022-05-09 13:40:24 -04:00
Neil Armstrong
b5cfa0c7ca power: add driver for the TPS65219 PMIC
The TPS65219 I2S PMIC features 3 Buck converters and 4 linear regulators,
2 GPOs, 1 GPIO, and 3 multi-function-pin.

This adds the PMIC driver, loading the regulator sub-nodes.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2022-05-09 13:40:24 -04:00
Pali Rohár
c7484ce091 Nokia RX-51: Convert to CONFIG_DM_SERIAL
For CONFIG_DM_SERIAL it is required to increase CONFIG_SYS_MALLOC_F_LEN as
default value is not enough for memory hungry CONFIG_DM_SERIAL code.

Signed-off-by: Pali Rohár <pali@kernel.org>
Tested-by: Merlijn Wajer <merlijn@wizzup.org>
2022-05-09 13:40:24 -04:00
Pali Rohár
f017c817a8 Nokia RX-51: Enable CONFIG_SUPPORT_RAW_INITRD
This enable booting of Debian systems which use raw initrd image (instead
of uInitrd created by mkimage). This change increase size of u-boot.bin
binary by just 64 bytes.

Signed-off-by: Pali Rohár <pali@kernel.org>
2022-05-09 13:40:24 -04:00
Gireesh Hiremath
655a93f079 am335x, guardian: Drop non DM_I2C code
On this platform DM_I2C and SPL_DM_I2C enabled.
Remove legacy code.

Signed-off-by: Gireesh Hiremath <Gireesh.Hiremath@in.bosch.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-05-09 13:40:24 -04:00
Gireesh Hiremath
75878e9f13 configs: am335x_guardian: Enable DM_I2C
Move from I2C legacy to the DM I2C version

Signed-off-by: Gireesh Hiremath <Gireesh.Hiremath@in.bosch.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-05-09 13:40:23 -04:00
Gireesh Hiremath
e61374b7af ARM: dts: am335x: guardian: switch to AM33XX_PADCONF
switch the pin definitions from AM33XX_IOPAD to AM33XX_PADCONF macro

Signed-off-by: Gireesh Hiremath <Gireesh.Hiremath@in.bosch.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-05-09 13:40:23 -04:00
780 changed files with 23504 additions and 5854 deletions

2
.gitignore vendored
View File

@@ -10,6 +10,7 @@
*.asn1.[ch]
*.bin
*.cfgout
*.cover
*.dtb
*.dtbo
*.dtb.S
@@ -22,6 +23,7 @@
*.lex.c
*.lst
*.mod.c
*.mbx
*.o
*.o.*
*.order

View File

@@ -305,6 +305,7 @@ config TPL_SYS_MALLOC_F_LEN
config VALGRIND
bool "Inform valgrind about memory allocations"
depends on !RISCV
help
Valgrind is an instrumentation framework for building dynamic analysis
tools. In particular, it may be used to detect memory management bugs

View File

@@ -121,6 +121,7 @@ F: arch/arm/include/asm/arch-m1/
F: arch/arm/mach-apple/
F: configs/apple_m1_defconfig
F: drivers/iommu/apple_dart.c
F: drivers/nvme/nvme_apple.c
F: drivers/pinctrl/pinctrl-apple.c
F: drivers/watchdog/apple_wdt.c
F: include/configs/apple.h
@@ -169,12 +170,23 @@ ARM ASPEED
M: Ryan Chen <ryan_chen@aspeedtech.com>
M: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
R: Aspeed BMC SW team <BMC-SW@aspeedtech.com>
R: Joel Stanley <joel@jms.id.au>
S: Maintained
F: arch/arm/mach-aspeed/
F: arch/arm/include/asm/arch-aspeed/
F: board/aspeed/
F: drivers/clk/aspeed/
F: drivers/crypto/aspeed/
F: drivers/gpio/gpio-aspeed.c
F: drivers/i2c/ast_i2c.[ch]
F: drivers/mmc/aspeed_sdhci.c
F: drivers/net/aspeed_mdio.c
F: drivers/net/ftgmac100.[ch]
F: drivers/pinctrl/aspeed/
F: drivers/pwm/pwm-aspeed.c
F: drivers/ram/aspeed/
F: drivers/reset/reset-ast2500.c
F: drivers/watchdog/ast_wdt.c
N: aspeed
ARM BROADCOM BCM283X / BCM27XX
@@ -1052,8 +1064,9 @@ T: git https://source.denx.de/u-boot/custodians/u-boot-mmc.git
F: drivers/mmc/
NAND FLASH
#M: Scott Wood <oss@buserror.net>
S: Orphaned (Since 2018-07)
M: Dario Binacchi <dario.binacchi@amarulasolutions.com>
M: Michael Trimarchi <michael@amarulasolutions.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-nand-flash.git
F: drivers/mtd/nand/raw/

View File

@@ -3,7 +3,7 @@
VERSION = 2022
PATCHLEVEL = 07
SUBLEVEL =
EXTRAVERSION = -rc2
EXTRAVERSION =
NAME =
# *DOCUMENTATION*
@@ -1120,7 +1120,7 @@ ifeq ($(CONFIG_OF_EMBED)$(CONFIG_EFI_APP),y)
@echo >&2 "CONFIG_OF_EMBED is enabled. This option should only"
@echo >&2 "be used for debugging purposes. Please use"
@echo >&2 "CONFIG_OF_SEPARATE for boards in mainline."
@echo >&2 "See doc/README.fdt-control for more info."
@echo >&2 "See doc/develop/devicetree/control.rst for more info."
@echo >&2 "===================================================="
endif
ifneq ($(CONFIG_SPL_FIT_GENERATOR),)
@@ -1263,7 +1263,7 @@ spl/u-boot-spl.srec: spl/u-boot-spl FORCE
OBJCOPYFLAGS_u-boot-nodtb.bin := -O binary \
$(if $(CONFIG_X86_16BIT_INIT),-R .start16 -R .resetvec) \
$(if $(CONFIG_MPC85XX_HAVE_RESET_VECTOR),-R .bootpg -R .resetvec)
$(if $(CONFIG_MPC85XX_HAVE_RESET_VECTOR),$(if $(CONFIG_OF_EMBED),,-R .bootpg -R .resetvec))
binary_size_check: u-boot-nodtb.bin FORCE
@file_size=$(shell wc -c u-boot-nodtb.bin | awk '{print $$1}') ; \

View File

@@ -401,6 +401,12 @@ config SYS_ARM_CACHE_WRITEALLOC
write is performed.
endchoice
config ARCH_VERY_EARLY_INIT
bool
config SPL_ARCH_VERY_EARLY_INIT
bool
config ARCH_CPU_INIT
bool "Enable ARCH_CPU_INIT"
help

View File

@@ -409,7 +409,7 @@ int arch_misc_init(void)
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
if (ret)
printf("Failed to initialize %s: %d\n", dev->name, ret);
printf("Failed to initialize caam_jr: %d\n", ret);
}
return 0;

View File

@@ -153,7 +153,7 @@ static void __secure sunxi_cpu_set_power(int cpu, bool on)
sunxi_power_switch((void *)cpucfg + SUN8I_R40_PWR_CLAMP(cpu),
(void *)cpucfg + SUN8I_R40_PWROFF,
on, 0);
on, cpu);
}
#else /* ! CONFIG_MACH_SUN7I && ! CONFIG_MACH_SUN8I_R40 */
static void __secure sunxi_cpu_set_power(int cpu, bool on)

View File

@@ -39,8 +39,28 @@ DECLARE_GLOBAL_DATA_PTR;
* off: FFF
*/
u64 get_tcr(int el, u64 *pips, u64 *pva_bits)
static int get_effective_el(void)
{
int el = current_el();
if (el == 2) {
u64 hcr_el2;
/*
* If we are using the EL2&0 translation regime, the TCR_EL2
* looks like the EL1 version, even though we are in EL2.
*/
__asm__ ("mrs %0, HCR_EL2\n" : "=r" (hcr_el2));
if (hcr_el2 & BIT(HCR_EL2_E2H_BIT))
return 1;
}
return el;
}
u64 get_tcr(u64 *pips, u64 *pva_bits)
{
int el = get_effective_el();
u64 max_addr = 0;
u64 ips, va_bits;
u64 tcr;
@@ -115,7 +135,7 @@ static u64 *find_pte(u64 addr, int level)
debug("addr=%llx level=%d\n", addr, level);
get_tcr(0, NULL, &va_bits);
get_tcr(NULL, &va_bits);
if (va_bits < 39)
start_level = 1;
@@ -343,7 +363,7 @@ __weak u64 get_page_table_size(void)
u64 va_bits;
int start_level = 0;
get_tcr(0, NULL, &va_bits);
get_tcr(NULL, &va_bits);
if (va_bits < 39)
start_level = 1;
@@ -415,7 +435,7 @@ __weak void mmu_setup(void)
setup_all_pgtables();
el = current_el();
set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(NULL, NULL),
MEMORY_ATTRIBUTES);
/* enable the mmu */

View File

@@ -454,7 +454,7 @@ static inline void early_mmu_setup(void)
/* point TTBR to the new table */
set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
get_tcr(el, NULL, NULL) &
get_tcr(NULL, NULL) &
~(TCR_ORGN_MASK | TCR_IRGN_MASK),
MEMORY_ATTRIBUTES);
@@ -609,7 +609,7 @@ static inline void final_mmu_setup(void)
invalidate_icache_all();
/* point TTBR to the new table */
set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(NULL, NULL),
MEMORY_ATTRIBUTES);
set_sctlr(get_sctlr() | CR_M);
@@ -1648,7 +1648,7 @@ int arch_misc_init(void)
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
if (ret)
printf("Failed to initialize %s: %d\n", dev->name, ret);
printf("Failed to initialize caam_jr: %d\n", ret);
}
serdes_misc_init();

View File

@@ -125,7 +125,7 @@ pie_fixup_done:
msr cptr_el3, xzr /* Enable FP/SIMD */
b 0f
2: mrs x1, hcr_el2
tbnz x1, #34, 1f /* HCR_EL2.E2H */
tbnz x1, #HCR_EL2_E2H_BIT, 1f /* HCR_EL2.E2H */
orr x1, x1, #HCR_EL2_AMO_EL2 /* Route SErrors to EL2 */
msr hcr_el2, x1
set_vbar vbar_el2, x0

View File

@@ -418,6 +418,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \
socfpga_agilex_socdk.dtb \
socfpga_arria5_secu1.dtb \
socfpga_arria5_socdk.dtb \
socfpga_arria10_chameleonv3_270_3.dtb \
socfpga_arria10_chameleonv3_480_2.dtb \
socfpga_arria10_socdk_sdmmc.dtb \
socfpga_cyclone5_mcvevk.dtb \
socfpga_cyclone5_is1.dtb \
@@ -539,7 +541,8 @@ dtb-$(CONFIG_MACH_SUN4I) += \
sun4i-a10-olinuxino-lime.dtb \
sun4i-a10-pcduino.dtb \
sun4i-a10-pcduino2.dtb \
sun4i-a10-pov-protab2-ips9.dtb
sun4i-a10-pov-protab2-ips9.dtb \
sun4i-a10-topwise-a721.dtb
dtb-$(CONFIG_MACH_SUN5I) += \
sun5i-a10s-auxtek-t003.dtb \
sun5i-a10s-auxtek-t004.dtb \
@@ -554,11 +557,14 @@ dtb-$(CONFIG_MACH_SUN5I) += \
sun5i-a13-hsg-h702.dtb \
sun5i-a13-inet-86vs.dtb \
sun5i-a13-inet-98v-rev2.dtb \
sun5i-a13-licheepi-one.dtb \
sun5i-a13-olinuxino.dtb \
sun5i-a13-olinuxino-micro.dtb \
sun5i-a13-pocketbook-touch-lux-3.dtb \
sun5i-a13-q8-tablet.dtb \
sun5i-a13-utoo-p66.dtb \
sun5i-gr8-chip-pro.dtb \
sun5i-gr8-evb.dtb \
sun5i-r8-chip.dtb
dtb-$(CONFIG_MACH_SUN6I) += \
sun6i-a31-app4-evb1.dtb \
@@ -582,11 +588,13 @@ dtb-$(CONFIG_MACH_SUN7I) += \
sun7i-a20-bananapro.dtb \
sun7i-a20-cubieboard2.dtb \
sun7i-a20-cubietruck.dtb \
sun7i-a20-haoyu-marsboard.dtb \
sun7i-a20-hummingbird.dtb \
sun7i-a20-i12-tvbox.dtb \
sun7i-a20-icnova-swac.dtb \
sun7i-a20-itead-ibox.dtb \
sun7i-a20-lamobo-r1.dtb \
sun7i-a20-linutronix-testbox-v2.dtb \
sun7i-a20-m3.dtb \
sun7i-a20-m5.dtb \
sun7i-a20-mk808c.dtb \
@@ -594,6 +602,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \
sun7i-a20-olimex-som204-evb.dtb \
sun7i-a20-olimex-som204-evb-emmc.dtb \
sun7i-a20-olinuxino-lime.dtb \
sun7i-a20-olinuxino-lime-emmc.dtb \
sun7i-a20-olinuxino-lime2.dtb \
sun7i-a20-olinuxino-lime2-emmc.dtb \
sun7i-a20-olinuxino-micro.dtb \
@@ -610,17 +619,22 @@ dtb-$(CONFIG_MACH_SUN8I_A23) += \
sun8i-a23-evb.dtb \
sun8i-a23-gt90h-v4.dtb \
sun8i-a23-inet86dz.dtb \
sun8i-a23-ippo-q8h-v1.2.dtb \
sun8i-a23-ippo-q8h-v5.dtb \
sun8i-a23-polaroid-mid2407pxe03.dtb \
sun8i-a23-polaroid-mid2809pxe04.dtb \
sun8i-a23-q8-tablet.dtb
dtb-$(CONFIG_MACH_SUN8I_A33) += \
sun8i-a33-et-q8-v1.6.dtb \
sun8i-a33-ga10h-v1.1.dtb \
sun8i-a33-inet-d978-rev2.dtb \
sun8i-a33-ippo-q8h-v1.2.dtb \
sun8i-a33-olinuxino.dtb \
sun8i-a33-q8-tablet.dtb \
sun8i-a33-sinlinx-sina33.dtb \
sun8i-r16-bananapi-m2m.dtb \
sun8i-r16-nintendo-nes-classic-edition.dtb \
sun8i-r16-nintendo-nes-classic.dtb \
sun8i-r16-nintendo-super-nes-classic.dtb \
sun8i-r16-parrot.dtb
dtb-$(CONFIG_MACH_SUN8I_A83T) += \
sun8i-a83t-allwinner-h8homlet-v2.dtb \
@@ -643,6 +657,7 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \
sun8i-h3-nanopi-m1-plus.dtb \
sun8i-h3-nanopi-neo.dtb \
sun8i-h3-nanopi-neo-air.dtb \
sun8i-h3-nanopi-r1.dtb \
sun8i-h3-orangepi-2.dtb \
sun8i-h3-orangepi-lite.dtb \
sun8i-h3-orangepi-one.dtb \
@@ -655,9 +670,13 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \
sun8i-h3-zeropi.dtb
dtb-$(CONFIG_MACH_SUN8I_R40) += \
sun8i-r40-bananapi-m2-ultra.dtb \
sun8i-r40-oka40i-c.dtb \
sun8i-t3-cqa3t-bv3.dtb \
sun8i-v40-bananapi-m2-berry.dtb
dtb-$(CONFIG_MACH_SUN8I_V3S) += \
sun8i-s3-elimo-initium.dtb \
sun8i-s3-pinecube.dtb \
sun8i-v3-sl631-imx179.dtb \
sun8i-v3s-licheepi-zero.dtb
dtb-$(CONFIG_MACH_SUN50I_H5) += \
sun50i-h5-bananapi-m2-plus.dtb \
@@ -678,7 +697,9 @@ dtb-$(CONFIG_MACH_SUN50I_H6) += \
sun50i-h6-orangepi-lite2.dtb \
sun50i-h6-orangepi-one-plus.dtb \
sun50i-h6-pine-h64.dtb \
sun50i-h6-tanix-tx6.dtb
sun50i-h6-pine-h64-model-b.dtb \
sun50i-h6-tanix-tx6.dtb \
sun50i-h6-tanix-tx6-mini.dtb
dtb-$(CONFIG_MACH_SUN50I_H616) += \
sun50i-h616-orangepi-zero2.dtb
dtb-$(CONFIG_MACH_SUN50I) += \
@@ -738,6 +759,7 @@ dtb-y += \
imx6dl-cubox-i-emmc-som-v15.dtb \
imx6dl-cubox-i-som-v15.dtb \
imx6dl-dhcom-pdk2.dtb \
imx6dl-dhcom-picoitx.dts \
imx6dl-gw51xx.dtb \
imx6dl-gw52xx.dtb \
imx6dl-gw53xx.dtb \
@@ -771,12 +793,14 @@ dtb-y += \
imx6dl-sabreauto.dtb \
imx6dl-sabresd.dtb \
imx6dl-wandboard-revd1.dtb \
imx6s-dhcom-drc02.dtb
endif
ifneq ($(CONFIG_MX6Q)$(CONFIG_MX6QDL),)
dtb-y += \
imx6-apalis.dtb \
imx6q-bosch-acc.dtb \
imx6q-cm-fx6.dtb \
imx6q-cubox-i.dtb \
imx6q-cubox-i-emmc-som-v15.dtb \
@@ -936,6 +960,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mn-beacon-kit.dtb \
imx8mq-mnt-reform2.dtb \
imx8mq-phanbell.dtb \
imx8mp-dhcom-pdk2.dtb \
imx8mp-evk.dtb \
imx8mp-phyboard-pollux-rdk.dtb \
imx8mp-venice.dtb \
@@ -1150,7 +1175,8 @@ dtb-$(CONFIG_STM32MP15x) += \
stm32mp15xx-dhcom-drc02.dtb \
stm32mp15xx-dhcom-pdk2.dtb \
stm32mp15xx-dhcom-picoitx.dtb \
stm32mp15xx-dhcor-avenger96.dtb
stm32mp15xx-dhcor-avenger96.dtb \
stm32mp15xx-dhcor-drc-compact.dtb
dtb-$(CONFIG_SOC_K3_AM6) += \
k3-am654-base-board.dtb \

View File

@@ -82,7 +82,7 @@
lcd0_pins: pinmux_lcd0_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x908, PIN_OUTPUT_PULLUP | MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_OUTPUT_PULLUP, MUX_MODE7)
>;
};
};

View File

@@ -388,167 +388,189 @@
clkout2_pin: pinmux_clkout2_pin {
pinctrl-single,pins = <
AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3)
AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3)
>;
};
dmtimer7_pins: pinmux_dmtimer7_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x968, PIN_OUTPUT | MUX_MODE5)
AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE5)
>;
};
guardian_button_pins: pinmux_gpio_keys_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x940, PIN_INPUT | MUX_MODE7)
AM33XX_IOPAD(0x884, PIN_INPUT | MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT, MUX_MODE7)
>;
};
guardian_interface_pins: pinmux_guardian_interface_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x990, PIN_OUTPUT_PULLUP | MUX_MODE7)
AM33XX_IOPAD(0x9ac, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x980, PIN_INPUT | MUX_MODE7)
AM33XX_IOPAD(0x984, PIN_INPUT | MUX_MODE7)
AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE7)
AM33XX_IOPAD(0x90c, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x944, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x91c, PIN_INPUT | MUX_MODE7)
AM33XX_IOPAD(0x918, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLUP, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_OUTPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_OUTPUT_PULLDOWN, MUX_MODE7)
>;
};
i2c0_pins: pinmux_i2c0_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0)
AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)
>;
};
lcd_disen_pins: pinmux_lcd_disen_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x9a4, PIN_OUTPUT_PULLUP | SLEWCTRL_SLOW | MUX_MODE7)
AM33XX_PADCONF
(AM335X_PIN_MCASP0_FSR, PIN_OUTPUT_PULLUP | SLEWCTRL_SLOW, MUX_MODE7)
>;
};
lcd_pins_default: pinmux_lcd_pins_default {
pinctrl-single,pins = <
AM33XX_IOPAD(0x820, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
AM33XX_IOPAD(0x824, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
AM33XX_IOPAD(0x828, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
AM33XX_IOPAD(0x82c, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
AM33XX_IOPAD(0x830, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
AM33XX_IOPAD(0x834, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
AM33XX_IOPAD(0x838, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
AM33XX_IOPAD(0x83c, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
AM33XX_IOPAD(0x8a0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
AM33XX_IOPAD(0x8a4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
AM33XX_IOPAD(0x8a8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
AM33XX_IOPAD(0x8ac, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
AM33XX_IOPAD(0x8b0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
AM33XX_IOPAD(0x8b4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
AM33XX_IOPAD(0x8b8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
AM33XX_IOPAD(0x8bc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
AM33XX_IOPAD(0x8c0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
AM33XX_IOPAD(0x8c4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
AM33XX_IOPAD(0x8c8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
AM33XX_IOPAD(0x8cc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
AM33XX_IOPAD(0x8d0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
AM33XX_IOPAD(0x8d4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
AM33XX_IOPAD(0x8d8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
AM33XX_IOPAD(0x8dc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
AM33XX_IOPAD(0x8e0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
AM33XX_IOPAD(0x8e4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
AM33XX_IOPAD(0x8e8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
AM33XX_IOPAD(0x8ec, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE1)
AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE1)
AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE1)
AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE1)
AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE1)
AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE1)
AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE1)
AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE1)
AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0)
AM33XX_PADCONF
(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0)
>;
};
lcd_pins_sleep: pinmux_lcd_pins_sleep {
pinctrl-single,pins = <
AM33XX_IOPAD(0x8a0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
AM33XX_IOPAD(0x8a4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
AM33XX_IOPAD(0x8a8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
AM33XX_IOPAD(0x8ac, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
AM33XX_IOPAD(0x8b0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
AM33XX_IOPAD(0x8b4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
AM33XX_IOPAD(0x8b8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
AM33XX_IOPAD(0x8bc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
AM33XX_IOPAD(0x8c0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
AM33XX_IOPAD(0x8c4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
AM33XX_IOPAD(0x8c8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
AM33XX_IOPAD(0x8cc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
AM33XX_IOPAD(0x8d0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
AM33XX_IOPAD(0x8d4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
AM33XX_IOPAD(0x8d8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
AM33XX_IOPAD(0x8dc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
AM33XX_IOPAD(0x8e0, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7)
AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7)
AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7)
AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7)
AM33XX_PADCONF
(AM335X_PIN_LCD_DATA0, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7)
AM33XX_PADCONF
(AM335X_PIN_LCD_DATA1, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7)
AM33XX_PADCONF
(AM335X_PIN_LCD_DATA2, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7)
AM33XX_PADCONF
(AM335X_PIN_LCD_DATA3, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7)
AM33XX_PADCONF
(AM335X_PIN_LCD_DATA4, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7)
AM33XX_PADCONF
(AM335X_PIN_LCD_DATA5, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7)
AM33XX_PADCONF
(AM335X_PIN_LCD_DATA6, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7)
AM33XX_PADCONF
(AM335X_PIN_LCD_DATA7, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7)
AM33XX_PADCONF
(AM335X_PIN_LCD_DATA8, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7)
AM33XX_PADCONF
(AM335X_PIN_LCD_DATA9, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7)
AM33XX_PADCONF
(AM335X_PIN_LCD_DATA10, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7)
AM33XX_PADCONF
(AM335X_PIN_LCD_DATA11, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7)
AM33XX_PADCONF
(AM335X_PIN_LCD_DATA12, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7)
AM33XX_PADCONF
(AM335X_PIN_LCD_DATA13, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7)
AM33XX_PADCONF
(AM335X_PIN_LCD_DATA14, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7)
AM33XX_PADCONF
(AM335X_PIN_LCD_DATA15, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7)
AM33XX_PADCONF
(AM335X_PIN_LCD_VSYNC, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW, MUX_MODE7)
AM33XX_PADCONF
(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW, MUX_MODE7)
AM33XX_PADCONF
(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW, MUX_MODE7)
AM33XX_PADCONF
(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW, MUX_MODE7)
>;
};
guardian_led_pins: pinmux_leds_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x868, PIN_OUTPUT | MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_OUTPUT, MUX_MODE7)
>;
};
mmc1_pins: pinmux_mmc1_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0)
AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0)
AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0)
AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0)
AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0)
AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0)
AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7)
>;
};
spi0_pins: pinmux_spi0_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x950, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
AM33XX_IOPAD(0x954, PIN_OUTPUT_PULLUP | MUX_MODE0)
AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0)
AM33XX_IOPAD(0x95c, PIN_OUTPUT_PULLUP | MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT_PULLUP, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_OUTPUT_PULLUP, MUX_MODE0)
>;
};
uart0_pins: pinmux_uart0_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)
AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
>;
};
uart2_pins: pinmux_uart2_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE1)
AM33XX_IOPAD(0x930, PIN_OUTPUT_PULLDOWN | MUX_MODE1)
AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE1)
AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE1)
>;
};
nandflash_pins: pinmux_nandflash_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x800, PIN_INPUT | MUX_MODE0)
AM33XX_IOPAD(0x804, PIN_INPUT | MUX_MODE0)
AM33XX_IOPAD(0x808, PIN_INPUT | MUX_MODE0)
AM33XX_IOPAD(0x80c, PIN_INPUT | MUX_MODE0)
AM33XX_IOPAD(0x810, PIN_INPUT | MUX_MODE0)
AM33XX_IOPAD(0x814, PIN_INPUT | MUX_MODE0)
AM33XX_IOPAD(0x818, PIN_INPUT | MUX_MODE0)
AM33XX_IOPAD(0x81c, PIN_INPUT | MUX_MODE0)
AM33XX_IOPAD(0x870, PIN_INPUT | MUX_MODE0)
AM33XX_IOPAD(0x874, PIN_OUTPUT | MUX_MODE0)
AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0)
AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0)
AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0)
AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0)
AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0)
>;
};
};

View File

@@ -53,7 +53,7 @@
interrupt-controller;
#interrupt-cells = <1>;
ac_power_supply: ac-power-supply {
ac_power_supply: ac-power {
compatible = "x-powers,axp202-ac-power-supply";
status = "disabled";
};
@@ -69,7 +69,7 @@
#gpio-cells = <2>;
};
battery_power_supply: battery-power-supply {
battery_power_supply: battery-power {
compatible = "x-powers,axp209-battery-power-supply";
status = "disabled";
};
@@ -112,7 +112,7 @@
};
};
usb_power_supply: usb-power-supply {
usb_power_supply: usb-power {
compatible = "x-powers,axp202-usb-power-supply";
status = "disabled";
};

View File

@@ -52,12 +52,17 @@
interrupt-controller;
#interrupt-cells = <1>;
ac_power_supply: ac-power-supply {
ac_power_supply: ac-power {
compatible = "x-powers,axp221-ac-power-supply";
status = "disabled";
};
battery_power_supply: battery-power-supply {
axp_adc: adc {
compatible = "x-powers,axp221-adc";
#io-channel-cells = <1>;
};
battery_power_supply: battery-power {
compatible = "x-powers,axp221-battery-power-supply";
status = "disabled";
};
@@ -158,7 +163,7 @@
};
};
usb_power_supply: usb_power_supply {
usb_power_supply: usb-power {
compatible = "x-powers,axp221-usb-power-supply";
status = "disabled";
};

View File

@@ -10,7 +10,7 @@
interrupt-controller;
#interrupt-cells = <1>;
ac_power_supply: ac-power-supply {
ac_power_supply: ac-power {
compatible = "x-powers,axp803-ac-power-supply",
"x-powers,axp813-ac-power-supply";
status = "disabled";
@@ -26,18 +26,18 @@
gpio-controller;
#gpio-cells = <2>;
gpio0_ldo: gpio0-ldo {
gpio0_ldo: gpio0-ldo-pin {
pins = "GPIO0";
function = "ldo";
};
gpio1_ldo: gpio1-ldo {
gpio1_ldo: gpio1-ldo-pin {
pins = "GPIO1";
function = "ldo";
};
};
battery_power_supply: battery-power-supply {
battery_power_supply: battery-power {
compatible = "x-powers,axp803-battery-power-supply",
"x-powers,axp813-battery-power-supply";
status = "disabled";
@@ -147,7 +147,7 @@
};
};
usb_power_supply: usb-power-supply {
usb_power_supply: usb-power {
compatible = "x-powers,axp803-usb-power-supply",
"x-powers,axp813-usb-power-supply";
status = "disabled";

View File

@@ -48,6 +48,11 @@
interrupt-controller;
#interrupt-cells = <1>;
ac_power_supply: ac-power {
compatible = "x-powers,axp813-ac-power-supply";
status = "disabled";
};
axp_adc: adc {
compatible = "x-powers,axp813-adc";
#io-channel-cells = <1>;
@@ -58,18 +63,18 @@
gpio-controller;
#gpio-cells = <2>;
gpio0_ldo: gpio0-ldo {
gpio0_ldo: gpio0-ldo-pin {
pins = "GPIO0";
function = "ldo";
};
gpio1_ldo: gpio1-ldo {
gpio1_ldo: gpio1-ldo-pin {
pins = "GPIO1";
function = "ldo";
};
};
battery_power_supply: battery-power-supply {
battery_power_supply: battery-power {
compatible = "x-powers,axp813-battery-power-supply";
status = "disabled";
};
@@ -166,4 +171,8 @@
status = "disabled";
};
};
usb_power_supply: usb-power {
compatible = "x-powers,axp813-usb-power-supply";
};
};

View File

@@ -0,0 +1,10 @@
// SPDX-License-Identifier: (GPL-2.0+)
/*
* Copyright (C) 2022 Philip Oberfichtner <pro@denx.de>
*/
#include "imx6qdl-dhcom-u-boot.dtsi"
&fec {
phy-reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
};

View File

@@ -0,0 +1,20 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2021 DH electronics GmbH
*
* DHCOM iMX6 variant:
* DHCM-iMX6DL-C0800-R102-F0819-E-SD-RTC-T-HS-I-01D2
* DHCOM PCB number: 493-300 or newer
* PicoITX PCB number: 487-600 or newer
*/
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-dhcom-som.dtsi"
#include "imx6qdl-dhcom-picoitx.dtsi"
/ {
model = "DH electronics i.MX6DL DHCOM on PicoITX";
compatible = "dh,imx6dl-dhcom-picoitx", "dh,imx6dl-dhcom-som",
"fsl,imx6dl";
};

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// SPDX-License-Identifier: GPL-2.0+
/* Copyright (C) 2022 Denx Software Engineering GmbH
* Philip Oberfichtner <pro@denx.de>
*/
/ {
chosen {
stdout-path = &uart2;
};
soc {
u-boot,dm-spl;
bus@2000000 {
u-boot,dm-spl;
spba-bus@2000000 {
u-boot,dm-spl;
};
};
bus@2100000 {
u-boot,dm-spl;
};
};
bootcount {
compatible = "u-boot,bootcount-pmic";
pmic = <&pmic>;
};
};
&uart1 {
u-boot,dm-spl;
};
&uart2 {
u-boot,dm-spl;
};
&usdhc2 {
u-boot,dm-spl;
};
&usdhc4 {
u-boot,dm-spl;
};
&gpio1 {
u-boot,dm-spl;
};
&gpio2 {
u-boot,dm-spl;
};
&gpio3 {
u-boot,dm-spl;
};
&gpio4 {
u-boot,dm-spl;
};
&gpio5 {
u-boot,dm-spl;
};
&gpio6 {
u-boot,dm-spl;
};
&gpio7 {
u-boot,dm-spl;
};
&wdog1 {
u-boot,dm-spl;
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Support for the i.MX6-based Bosch ACC board.
*
* Copyright (C) 2016 Garz & Fricke GmbH
* Copyright (C) 2018 DENX Software Engineering GmbH, Heiko Schocher <hs@denx.de>
* Copyright (C) 2018 DENX Software Engineering GmbH, Niel Fourie <lusus@denx.de>
* Copyright (C) 2019-2021 Bosch Thermotechnik GmbH, Matthias Winker <matthias.winker@bosch.com>
* Copyright (C) 2022 DENX Software Engineering GmbH, Philip Oberfichtner <pro@denx.de>
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include "imx6q.dtsi"
/ {
model = "Bosch ACC";
compatible = "bosch,imx6q-acc", "fsl,imx6q";
aliases {
i2c0 = &i2c1;
i2c1 = &i2c2;
i2c2 = &i2c3;
mmc0 = &usdhc4;
mmc1 = &usdhc2;
serial0 = &uart2;
serial1 = &uart1;
};
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0x40000000>;
};
backlight_lvds: backlight-lvds {
compatible = "pwm-backlight";
pwms = <&pwm1 0 200000>;
brightness-levels = <0 61 499 1706 4079 8022 13938 22237 33328 47623 65535>;
num-interpolated-steps = <10>;
default-brightness-level = <60>;
power-supply = <&reg_lcd>;
};
panel {
compatible = "dataimage,fg1001l0dsswmg01";
backlight = <&backlight_lvds>;
port {
panel_in: endpoint {
remote-endpoint = <&lvds0_out>;
};
};
};
refclk: refclk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&clks IMX6QDL_CLK_CKO2>;
clock-div = <1>;
clock-mult = <1>;
clock-output-names = "12mhz_refclk";
assigned-clocks = <&clks IMX6QDL_CLK_CKO>,
<&clks IMX6QDL_CLK_CKO2>,
<&clks IMX6QDL_CLK_CKO2_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_CKO2>,
<&clks IMX6QDL_CLK_CKO2_PODF>,
<&clks IMX6QDL_CLK_OSC>;
assigned-clock-rates = <0>, <12000000>, <0>;
};
cpus {
cpu0: cpu@0 {
operating-points = <
/* kHz uV */
1200000 1275000
996000 1225000
852000 1225000
792000 1150000
396000 950000
>;
fsl,soc-operating-points = <
/* ARM kHz SOC-PU uV */
1200000 1225000
996000 1175000
852000 1175000
792000 1150000
396000 1150000
>;
};
cpu1: cpu@1 {
operating-points = <
/* kHz uV */
1200000 1275000
996000 1225000
852000 1225000
792000 1150000
396000 950000
>;
fsl,soc-operating-points = <
/* ARM kHz SOC-PU uV */
1200000 1225000
996000 1175000
852000 1175000
792000 1150000
396000 1150000
>;
};
};
pwm-leds {
compatible = "pwm-leds";
led_red: led-0 {
color = <LED_COLOR_ID_RED>;
max-brightness = <248>;
default-state = "off";
pwms = <&pwm2 0 500000>;
};
led_white: led-1 {
color = <LED_COLOR_ID_WHITE>;
max-brightness = <248>;
default-state = "off";
pwms = <&pwm3 0 500000>;
linux,default-trigger = "heartbeat";
};
};
gpio-leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reset_gpio_led>;
led-2 {
color = <LED_COLOR_ID_RED>;
gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
};
reg_5p0: regulator-5p0 {
compatible = "regulator-fixed";
regulator-name = "5p0";
};
reg_vin: regulator-vin {
compatible = "regulator-fixed";
regulator-name = "VIN";
regulator-min-microvolt = <4500000>;
regulator-max-microvolt = <4500000>;
regulator-always-on;
vin-supply = <&reg_5p0>;
};
reg_usb_otg_vbus: regulator-usb-otg-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_usb_h1_vbus: regulator-usb-h1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
vin-supply = <&reg_5p0>;
};
reg_usb_h2_vbus: regulator-usb-h2-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_h2_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&reg_5p0> ;
regulator-always-on;
};
reg_vsnvs: regulator-vsnvs {
compatible = "regulator-fixed";
regulator-name = "VSNVS_3V0";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
vin-supply = <&reg_5p0>;
};
reg_lcd: regulator-lcd {
compatible = "regulator-fixed";
regulator-name = "LCD0 POWER";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd_enable>;
gpio = <&gpio3 23 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-boot-on;
};
reg_dac: regulator-dac {
compatible = "regulator-fixed";
regulator-name = "vref_dac";
regulator-min-microvolt = <20000>;
regulator-max-microvolt = <20000>;
vin-supply = <&reg_5p0> ;
regulator-boot-on;
};
reg_sw4: regulator-sw4 {
compatible = "regulator-fixed";
regulator-name = "SW4_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
vin-supply = <&reg_5p0>;
};
reg_sys: regulator-sys {
compatible = "regulator-fixed";
regulator-name = "SYS_4V2";
regulator-min-microvolt = <4200000>;
regulator-max-microvolt = <4200000>;
regulator-always-on;
vin-supply = <&reg_5p0>;
};
};
&reg_arm {
vin-supply = <&sw2_reg>;
};
&reg_soc {
vin-supply = <&sw1c_reg>;
};
&reg_vdd1p1 {
vin-supply = <&reg_vsnvs>;
};
&reg_vdd2p5 {
vin-supply = <&reg_vsnvs>;
};
&reg_vdd3p0 {
vin-supply = <&reg_vsnvs>;
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
clocks = <&clks IMX6QDL_CLK_ENET>,
<&clks IMX6QDL_CLK_ENET>,
<&clks IMX6QDL_CLK_ENET>,
<&clks IMX6QDL_CLK_ENET_REF>;
clock-names = "ipg", "ahb", "ptp", "enet_out";
phy-mode = "rmii";
phy-supply = <&reg_sw4>;
phy-handle = <&ethphy>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
interrupt-parent = <&gpio1>;
interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
smsc,disable-energy-detect;
};
};
};
&gpu_vg {
status = "disabled";
};
&gpu_2d {
status = "disabled";
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clock-frequency = <400000>;
status = "okay";
pmic: pmic@8 {
compatible = "fsl,pfuze100";
reg = <0x08>;
regulators {
sw1c_reg: sw1c {
regulator-name = "VDD_SOC (sw1abc)";
regulator-min-microvolt = <1275000>;
regulator-max-microvolt = <1500000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
sw2_reg: sw2 {
regulator-name = "VDD_ARM (sw2)";
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1500000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
sw3a_reg: sw3a {
compatible = "regulator-fixed";
regulator-name = "DDR_1V5a";
regulator-boot-on;
regulator-always-on;
};
sw3b_reg: sw3b {
compatible = "regulator-fixed";
regulator-name = "DDR_1V5b";
regulator-boot-on;
regulator-always-on;
};
sw4_reg: sw4 {
regulator-name = "AUX 3V15 (sw4)";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
};
swbst_reg: swbst {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>;
regulator-boot-on;
regulator-always-on;
status = "disabled";
};
snvs_reg: vsnvs {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3000000>;
regulator-boot-on;
regulator-always-on;
};
vref_reg: vrefddr {
regulator-boot-on;
regulator-always-on;
};
vgen1_reg: vgen1 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
regulator-always-on;
};
vgen2_reg: vgen2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
regulator-always-on;
};
vgen3_reg: vgen3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen4_reg: vgen4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
vgen5_reg: vgen5 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
vgen6_reg: vgen6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
lm75: sensor@49 {
compatible = "national,lm75b";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lm75>;
reg = <0x49>;
};
eeprom: eeprom@50 {
compatible = "atmel,24c32";
reg = <0x50>;
pagesize = <32>;
};
rtc: rtc@51 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rtc>;
compatible = "nxp,pcf8563";
reg = <0x51>;
};
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clock-frequency = <100000>;
status = "okay";
eeprom_ext: eeprom@50 {
compatible = "atmel,24c32";
reg = <0x50>;
pagesize = <32>;
};
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clock-frequency = <400000>;
status = "okay";
usb3503: usb@8 {
compatible = "smsc,usb3503";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb3503>;
reg = <0x08>;
connect-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; /* Old: 0, SS: HIGH */
intn-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; /* Old: 1, SS: HIGH */
reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; /* Old: 0, SS: HIGH */
initial-mode = <1>;
clocks = <&refclk>;
clock-names = "refclk";
refclk-frequency = <12000000>;
};
exc3000: touchscreen@2a {
compatible = "eeti,exc3000";
reg = <0x2a>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ctouch>;
interrupt-parent = <&gpio4>;
interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
touchscreen-size-x = <4096>;
touchscreen-size-y = <4096>;
};
vcnl4035: light-sensor@60 {
compatible = "vishay,vcnl4035";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_proximity>;
reg = <0x60>;
};
};
&ldb {
status = "okay";
lvds0: lvds-channel@0 {
fsl,data-mapping = "spwg";
fsl,data-width = <24>;
port@4 {
reg = <4>;
lvds0_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
};
&pwm1 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&pwm2 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
status = "okay";
};
&pwm3 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
};
&pwm4 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
rts-gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>;
linux,rs485-enabled-at-boot-time;
rs485-rx-during-tx;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
uart-has-rtscts;
status = "okay";
};
&usbh1 {
vbus-supply = <&reg_usb_h1_vbus>;
status = "okay";
};
&usbh2 {
pinctrl-names = "idle", "active";
pinctrl-0 = <&pinctrl_usbh2_idle>;
pinctrl-1 = <&pinctrl_usbh2_active>;
vbus-supply = <&reg_usb_h2_vbus>;
status = "okay";
};
&usbotg {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
vbus-supply = <&reg_usb_otg_vbus>;
disable-over-current;
dr_mode = "otg";
srp-disable;
hnp-disable;
adp-disable;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
no-1-8-v;
keep-power-in-suspend;
enable-sdio-wakeup;
voltage-ranges = <3300 3300>;
vmmc-supply = <&reg_sw4>;
fsl,wp-controller;
status = "okay";
};
&usdhc4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc4>;
bus-width = <8>;
non-removable;
no-1-8-v;
keep-power-in-suspend;
voltage-ranges = <3300 3300>;
vmmc-supply = <&reg_sw4>;
fsl,wp-controller;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog1>;
fsl,ext-reset-output;
timeout-sec=<10>;
status = "okay";
};
&iomuxc {
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0 /* FEC INT */
MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x0001b098
MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x0001b098
MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x0001b098
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
>;
};
pinctrl_reset_gpio_led: reset-gpio-led-grp {
fsl,pins = <
MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b810
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b810
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
>;
};
pinctrl_lcd_enable: lcdenablegrp {
fsl,pins = <
MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 /* lcd enable */
MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x1b0b0 /* sel6_8 */
>;
};
pinctrl_lm75: lm75grp {
fsl,pins = <
MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
>;
};
pinctrl_proximity: proximitygrp {
fsl,pins = <
MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x0001b0b0
>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x0001b0b0
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x0001b0b0
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x0001b0b0
>;
};
pinctrl_rtc: rtc-grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x1b0b0 /* RTC INT */
>;
};
pinctrl_ctouch: ctouch-grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 /* CTOUCH_INT */
MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x0001b0b0 /* CTOUCH_RESET */
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x0001b0b0
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x1b0b1
MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x1b0b1
MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x1b0b1
>;
};
pinctrl_usbh2_idle: usbh2-idle-grp {
fsl,pins = <
MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x00013018
MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x00013018
>;
};
pinctrl_usbh2_active: usbh2-active-grp {
fsl,pins = <
MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x00013018
MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x00017018
>;
};
pinctrl_usb3503: usb3503-grp {
fsl,pins = <
MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x00000018
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 /* USB INT */
MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x0001b0b0 /* USB Reset */
MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0 /* USB Connect */
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x00017069
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x00010038
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x00017069
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x00017069
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x00017069
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x00017069
MX6QDL_PAD_GPIO_4__SD2_CD_B 0x0001b0b0
>;
};
pinctrl_usdhc4: usdhc4grp {
fsl,pins = <
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x00017059
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x00010059
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x00017059
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x00017059
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x00017059
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x00017059
MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x00017059
MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x00017059
MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x00017059
MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x00017059
>;
};
pinctrl_wdog1: wdoggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0
>;
};
};

View File

@@ -0,0 +1,143 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2021 DH electronics GmbH
*/
/ {
chosen {
stdout-path = "serial0:115200n8";
};
};
/*
* Special SoM hardware required which uses the pins from micro SD card. The
* pins SD3_DAT0 and SD3_DAT1 are muxed as can2 Tx and Rx. The signals for can2
* Tx and Rx are routed to the DHCOM UART1 rts/cts pins. Therefore the micro SD
* card must be disabled and the uart1 rts/cts must be output on other DHCOM
* pins, see uart1 and usdhc3 node below.
*/
&can2 {
status = "okay";
};
&gpio1 {
/*
* NOTE: On DRC02, the RS485_RX_En is controlled by a separate
* GPIO line, however the i.MX6 UART driver assumes RX happens
* during TX anyway and that it only controls drive enable DE
* line. Hence, the RX is always enabled here.
*/
rs485-rx-en-hog {
gpio-hog;
gpios = <18 0>; /* GPIO Q */
line-name = "rs485-rx-en";
output-low;
};
};
&gpio3 {
gpio-line-names =
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "DRC02-In1", "", "", "", "";
};
&gpio4 {
gpio-line-names =
"", "", "", "", "", "DHCOM-E", "DRC02-In2", "DHCOM-H",
"DHCOM-I", "DRC02-HW0", "", "", "", "", "", "",
"", "", "", "", "DRC02-Out1", "", "", "",
"", "", "", "", "", "", "", "";
};
&gpio6 {
gpio-line-names =
"", "", "", "DRC02-Out2", "", "", "SOM-HW1", "",
"", "", "", "", "", "", "DRC02-HW2", "DRC02-HW1",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&i2c1 {
eeprom@50 {
compatible = "atmel,24c04";
reg = <0x50>;
pagesize = <16>;
};
};
&uart1 {
/*
* Due to the use of can2 the signals for can2 Tx and Rx are routed to
* DHCOM UART1 rts/cts pins. Therefore this UART have to use DHCOM GPIOs
* for rts/cts. So configure DHCOM GPIO I as rts and GPIO M as cts.
*/
/delete-property/ uart-has-rtscts;
cts-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; /* GPIO M */
pinctrl-0 = <&pinctrl_uart1 &pinctrl_dhcom_i &pinctrl_dhcom_m>;
pinctrl-names = "default";
rts-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* GPIO I */
};
&uart5 {
/*
* On DRC02 this UART is used as RS485 interface and RS485_TX_En is
* controlled by DHCOM GPIO P. So remove rts/cts pins and the property
* uart-has-rtscts from this UART and add the DHCOM GPIO P pin via
* rts-gpios. The RS485_RX_En is controlled by DHCOM GPIO Q, see gpio1
* node above.
*/
/delete-property/ uart-has-rtscts;
linux,rs485-enabled-at-boot-time;
pinctrl-0 = <&pinctrl_uart5_core &pinctrl_dhcom_p &pinctrl_dhcom_q>;
pinctrl-names = "default";
rts-gpios = <&gpio7 13 GPIO_ACTIVE_HIGH>; /* GPIO P */
};
&usbh1 {
disable-over-current;
};
&usdhc2 { /* SD card */
status = "okay";
};
&usdhc3 {
/*
* Due to the use of can2 the micro SD card on module have to be
* disabled, because the pins SD3_DAT0 and SD3_DAT1 are muxed as
* can2 Tx and Rx.
*/
status = "disabled";
};
&iomuxc {
pinctrl-0 = <
/*
* The following DHCOM GPIOs are used on this board.
* Therefore, they have been removed from the list below.
* I: uart1 rts
* M: uart1 cts
* P: uart5 rs485-tx-en
* Q: uart5 rs485-rx-en
*/
&pinctrl_hog_base
&pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c
&pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f
&pinctrl_dhcom_g &pinctrl_dhcom_h
&pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l
&pinctrl_dhcom_n &pinctrl_dhcom_o
&pinctrl_dhcom_r
&pinctrl_dhcom_s &pinctrl_dhcom_t &pinctrl_dhcom_u
&pinctrl_dhcom_v &pinctrl_dhcom_w &pinctrl_dhcom_int
>;
pinctrl-names = "default";
pinctrl_uart5_core: uart5-core-grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1
MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1
>;
};
};

View File

@@ -5,19 +5,6 @@
#include "imx6qdl-dhcom-u-boot.dtsi"
/ {
fec_vio: regulator-fec {
compatible = "regulator-fixed";
regulator-name = "fec-vio";
gpio = <&gpio1 7 GPIO_ACTIVE_LOW>;
};
};
&fec {
phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
phy-reset-duration = <1>;
phy-reset-post-delay = <10>;
phy-supply = <&fec_vio>;
};

View File

@@ -0,0 +1,69 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2021 DH electronics GmbH
*/
#include <dt-bindings/leds/common.h>
/ {
chosen {
stdout-path = "serial0:115200n8";
};
led {
compatible = "gpio-leds";
led-0 {
color = <LED_COLOR_ID_YELLOW>;
default-state = "off";
function = LED_FUNCTION_INDICATOR;
gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* GPIO I */
pinctrl-0 = <&pinctrl_dhcom_i>;
pinctrl-names = "default";
};
};
};
&gpio1 {
gpio-line-names =
"", "", "DHCOM-A", "", "DHCOM-B", "PicoITX-In2", "", "",
"", "", "", "", "", "", "", "",
"DHCOM-R", "DHCOM-S", "DHCOM-Q", "DHCOM-T", "DHCOM-U", "", "", "",
"", "", "", "", "", "", "", "";
};
&gpio4 {
gpio-line-names =
"", "", "", "", "", "PicoITX-In1", "DHCOM-INT", "DHCOM-H",
"DHCOM-I", "PicoITX-HW2", "", "", "", "", "", "",
"", "", "", "", "PicoITX-Out1", "", "", "",
"", "", "", "", "", "", "", "";
};
&gpio6 {
gpio-line-names =
"", "", "", "PicoITX-Out2", "", "", "SOM-HW1", "",
"", "", "", "", "", "", "PicoITX-HW0", "PicoITX-HW1",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&iomuxc {
pinctrl-0 = <
/*
* The following DHCOM GPIOs are used on this board.
* Therefore, they have been removed from the list below.
* I: yellow led
*/
&pinctrl_hog_base
&pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c
&pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f
&pinctrl_dhcom_g &pinctrl_dhcom_h
&pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l
&pinctrl_dhcom_m &pinctrl_dhcom_n &pinctrl_dhcom_o
&pinctrl_dhcom_p &pinctrl_dhcom_q &pinctrl_dhcom_r
&pinctrl_dhcom_s &pinctrl_dhcom_t &pinctrl_dhcom_u
&pinctrl_dhcom_v &pinctrl_dhcom_w &pinctrl_dhcom_int
>;
pinctrl-names = "default";
};

View File

@@ -1,8 +1,26 @@
// SPDX-License-Identifier: (GPL-2.0+)
/*
* Copyright (C) 2020 Harald Seiler <hws@denx.de>
* Copyright (C) 2022 Philip Oberfichtner <pro@denx.de>
*/
/ {
aliases {
eeprom0 = &eeprom0;
};
};
&fec {
phy-reset-duration = <1>;
phy-reset-post-delay = <10>;
phy-supply = <&reg_eth_vio>;
};
&i2c3 {
eeprom0: eeprom@50 {
};
};
&reg_usb_otg_vbus {
gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
enable-active-high;

View File

@@ -130,7 +130,7 @@
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
phy-reset-post-delay = <100>;
phy-reset-post-delay = <300>;
status = "okay";
};

View File

@@ -196,7 +196,7 @@
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
phy-reset-post-delay = <100>;
phy-reset-post-delay = <300>;
status = "okay";
};

View File

@@ -190,7 +190,7 @@
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
phy-reset-post-delay = <100>;
phy-reset-post-delay = <300>;
status = "okay";
};

View File

@@ -227,7 +227,7 @@
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
phy-reset-post-delay = <100>;
phy-reset-post-delay = <300>;
status = "okay";
};

View File

@@ -281,7 +281,7 @@
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
phy-reset-post-delay = <100>;
phy-reset-post-delay = <300>;
status = "okay";
};

View File

@@ -225,7 +225,7 @@
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
phy-reset-post-delay = <100>;
phy-reset-post-delay = <300>;
status = "okay";
};

View File

@@ -203,7 +203,7 @@
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
phy-reset-post-delay = <100>;
phy-reset-post-delay = <300>;
status = "okay";
fixed-link {

View File

@@ -132,7 +132,7 @@
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
phy-reset-post-delay = <100>;
phy-reset-post-delay = <300>;
status = "okay";
};

View File

@@ -148,7 +148,7 @@
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
phy-reset-post-delay = <100>;
phy-reset-post-delay = <300>;
status = "okay";
};

View File

@@ -144,7 +144,7 @@
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
phy-reset-post-delay = <100>;
phy-reset-post-delay = <300>;
status = "okay";
};

View File

@@ -123,7 +123,7 @@
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
phy-reset-post-delay = <100>;
phy-reset-post-delay = <300>;
status = "okay";
};

View File

@@ -55,7 +55,13 @@
pinctrl-0 = <&pinctrl_microsom_enet_ar8035>;
phy-handle = <&phy>;
phy-mode = "rgmii-id";
phy-reset-duration = <2>;
/*
* The PHY seems to require a long-enough reset duration to avoid
* some rare issues where the PHY gets stuck in an inconsistent and
* non-functional state at boot-up. 10ms proved to be fine .
*/
phy-reset-duration = <10>;
phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
status = "okay";
@@ -64,8 +70,15 @@
#size-cells = <0>;
phy: ethernet-phy@0 {
reg = <0>;
/*
* The PHY can appear either:
* - AR8035: at address 0 or 4
* - ADIN1300: at address 1
* Actual address being detected at runtime.
*/
reg = <0xffffffff>;
qca,clk-out-frequency = <125000000>;
adi,phy-output-clock = "125mhz-free-running";
};
};
};

View File

@@ -0,0 +1,10 @@
// SPDX-License-Identifier: (GPL-2.0+)
/*
* Copyright (C) 2022 Philip Oberfichtner <pro@denx.de>
*/
#include "imx6qdl-dhcom-u-boot.dtsi"
&fec {
phy-reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
};

View File

@@ -0,0 +1,30 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2021 DH electronics GmbH
*
* DHCOM iMX6 variant:
* DHCM-iMX6S-C0800-R102-F0409-E-CAN2-RTC-I-01D2
* DHCOM PCB number: 493-400 or newer
* DRC02 PCB number: 568-100 or newer
*/
/dts-v1/;
/*
* The kernel only distinguishes between i.MX6 Quad and DualLite,
* but the Solo is actually a DualLite with only one CPU. So use
* DualLite for the Solo and disable one CPU node.
*/
#include "imx6dl.dtsi"
#include "imx6qdl-dhcom-som.dtsi"
#include "imx6qdl-dhcom-drc02.dtsi"
/ {
model = "DH electronics i.MX6S DHCOM on DRC02";
compatible = "dh,imx6s-dhcom-drc02", "dh,imx6s-dhcom-som",
"fsl,imx6dl";
cpus {
/delete-node/ cpu@1;
};
};

View File

@@ -392,7 +392,7 @@
&i2c2 {
/* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
clock-frequency = <320000>;
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;

View File

@@ -121,6 +121,10 @@
u-boot,dm-spl;
};
&pinctrl_wdog {
u-boot,dm-spl;
};
&fec1 {
phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
};

View File

@@ -6,7 +6,6 @@
/dts-v1/;
#include "imx8mm-kontron-n801x-som.dtsi"
#include <dt-bindings/net/mscc-phy-vsc8531.h>
/ {
model = "Kontron i.MX8MM N801X S";
@@ -81,7 +80,6 @@
regulator-name = "vdd-5v";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
};
@@ -124,38 +122,14 @@
#size-cells = <0>;
ethphy: ethernet-phy@0 {
compatible = "ethernet-phy-id0007.0570";
reg = <0>;
reset-assert-us = <100>;
reset-deassert-us = <100>;
reset-assert-us = <1>;
reset-deassert-us = <15000>;
reset-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>;
vsc8531,led-0-mode = <VSC8531_LINK_100_1000_ACTIVITY>;
vsc8531,led-1-mode = <VSC8531_LINK_ACTIVITY>;
vsc8531,led-0-combine-disable;
};
};
};
&gpio4 {
dsi_mux_sel: dsi_mux_sel {
gpio-hog;
gpios = <14 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "dsi-mux-sel";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dsi_sel>;
};
dsi_mux_oe {
gpio-hog;
gpios = <15 GPIO_ACTIVE_LOW>;
output-high;
line-name = "dsi-mux-oe";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dsi_oe>;
};
};
&i2c4 {
clock-frequency = <100000>;
pinctrl-names = "default";
@@ -208,7 +182,7 @@
#address-cells = <1>;
#size-cells = <0>;
usbnet: usbether@1 {
usbnet: ethernet@1 {
compatible = "usb424,ec00";
reg = <1>;
local-mac-address = [ 00 00 00 00 00 00 ];
@@ -237,18 +211,6 @@
>;
};
pinctrl_dsi_sel: dsiselgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x19
>;
};
pinctrl_dsi_oe: dsioegrp {
fsl,pins = <
MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x19
>;
};
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
@@ -362,7 +324,7 @@
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
@@ -374,7 +336,7 @@
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6

View File

@@ -63,10 +63,10 @@
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
status = "okay";
spi-flash@0 {
flash@0 {
compatible = "mxicy,mx25r1635f", "jedec,spi-nor";
spi-max-frequency = <80000000>;
reg = <0>;
@@ -154,7 +154,7 @@
reg_vdd_snvs: LDO2 {
regulator-name = "ldo2";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
regulator-max-microvolt = <900000>;
regulator-boot-on;
regulator-always-on;
};

View File

@@ -25,10 +25,23 @@
};
};
&fec1 {
phy-mode = "rgmii-rxid";
&crypto {
u-boot,dm-spl;
};
&sec_jr0 {
u-boot,dm-spl;
};
&sec_jr1 {
u-boot,dm-spl;
};
&sec_jr2 {
u-boot,dm-spl;
};
&i2c1 {
u-boot,dm-spl;
u-boot,dm-pre-reloc;

View File

@@ -80,6 +80,10 @@
u-boot,dm-spl;
};
&pinctrl_wdog {
u-boot,dm-spl;
};
&gpio1 {
u-boot,dm-spl;
};

View File

@@ -58,7 +58,9 @@
};
flash {
spl {
filename = "spl.bin";
mkimage {
args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x912000";

View File

@@ -0,0 +1,141 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2022 Marek Vasut <marex@denx.de>
*/
#include "imx8mp-u-boot.dtsi"
/ {
aliases {
eeprom0 = &eeprom0;
eeprom1 = &eeprom1;
mmc0 = &usdhc2; /* MicroSD */
mmc1 = &usdhc3; /* eMMC */
mmc2 = &usdhc1; /* SDIO */
};
config {
dh,ram-coding-gpios = <&gpio3 22 0>, <&gpio3 23 0>, <&gpio3 24 0>;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
u-boot,dm-spl;
};
};
&buck4 {
u-boot,dm-spl;
};
&buck5 {
u-boot,dm-spl;
};
&eqos {
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ assigned-clock-rates;
};
&gpio1 {
u-boot,dm-spl;
};
&gpio2 {
u-boot,dm-spl;
};
&gpio3 {
u-boot,dm-spl;
};
&gpio4 {
u-boot,dm-spl;
};
&gpio5 {
u-boot,dm-spl;
};
&i2c3 {
u-boot,dm-spl;
};
&pinctrl_i2c3 {
u-boot,dm-spl;
};
&pinctrl_i2c3_gpio {
u-boot,dm-spl;
};
&pinctrl_pmic {
u-boot,dm-spl;
};
&pinctrl_uart1 {
u-boot,dm-spl;
};
&pinctrl_usdhc2 {
u-boot,dm-spl;
};
&pinctrl_usdhc2_100mhz {
u-boot,dm-spl;
};
&pinctrl_usdhc2_200mhz {
u-boot,dm-spl;
};
&pinctrl_usdhc2_vmmc {
u-boot,dm-spl;
};
&pinctrl_usdhc3 {
u-boot,dm-spl;
};
&pinctrl_usdhc3_100mhz {
u-boot,dm-spl;
};
&pinctrl_usdhc3_100mhz {
u-boot,dm-spl;
};
&pmic {
u-boot,dm-spl;
regulators {
u-boot,dm-spl;
};
};
&reg_usdhc2_vmmc {
u-boot,dm-spl;
};
&uart1 {
u-boot,dm-spl;
};
/* SDIO WiFi */
&usdhc1 {
status = "disabled";
};
&usdhc2 {
u-boot,dm-spl;
};
&usdhc3 {
u-boot,dm-spl;
};
&wdog1 {
u-boot,dm-spl;
};

View File

@@ -0,0 +1,152 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2022 Marek Vasut <marex@denx.de>
*/
/dts-v1/;
#include <dt-bindings/leds/common.h>
#include <dt-bindings/net/qca-ar803x.h>
#include <dt-bindings/phy/phy-imx8-pcie.h>
#include "imx8mp-dhcom-som.dtsi"
/ {
model = "DH electronics i.MX8M Plus DHCOM Premium Developer Kit (2)";
compatible = "dh,imx8mp-dhcom-pdk2", "fsl,imx8mp";
chosen {
stdout-path = &uart1;
};
gpio-keys {
#size-cells = <0>;
compatible = "gpio-keys";
button-0 {
gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; /* GPIO A */
label = "TA1-GPIO-A";
linux,code = <KEY_A>;
pinctrl-0 = <&pinctrl_dhcom_a>;
pinctrl-names = "default";
wakeup-source;
};
button-1 {
gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; /* GPIO B */
label = "TA2-GPIO-B";
linux,code = <KEY_B>;
pinctrl-0 = <&pinctrl_dhcom_b>;
pinctrl-names = "default";
wakeup-source;
};
button-2 {
gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; /* GPIO C */
label = "TA3-GPIO-C";
linux,code = <KEY_C>;
pinctrl-0 = <&pinctrl_dhcom_c>;
pinctrl-names = "default";
wakeup-source;
};
button-3 {
gpios = <&gpio4 27 GPIO_ACTIVE_LOW>; /* GPIO D */
label = "TA4-GPIO-D";
linux,code = <KEY_D>;
pinctrl-0 = <&pinctrl_dhcom_d>;
pinctrl-names = "default";
wakeup-source;
};
};
led {
compatible = "gpio-leds";
led-5 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_INDICATOR;
gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* GPIO E */
pinctrl-0 = <&pinctrl_dhcom_e>;
pinctrl-names = "default";
};
led-6 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_INDICATOR;
gpios = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* GPIO F */
pinctrl-0 = <&pinctrl_dhcom_f>;
pinctrl-names = "default";
};
led-7 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_INDICATOR;
gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; /* GPIO H */
pinctrl-0 = <&pinctrl_dhcom_h>;
pinctrl-names = "default";
};
led-8 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_INDICATOR;
gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; /* GPIO I */
pinctrl-0 = <&pinctrl_dhcom_i>;
pinctrl-names = "default";
};
};
};
/*
* PDK2 carrier board uses SoM with KSZ9131 populated and connected to
* SoM EQoS ethernet RGMII interface. Remove the other SoM PHY DT node.
*/
/delete-node/ &ethphy0f;
/*
* PDK2 carrier board has KSZ9021 PHY populated and connected to SoM FEC
* ethernet RGMII interface. The SoM is not populated with second FEC PHY.
*/
/delete-node/ &ethphy1f;
&fec { /* Second ethernet */
phy-handle = <&ethphypdk>;
mdio {
ethphypdk: ethernet-phy@7 { /* KSZ 9021 */
compatible = "ethernet-phy-ieee802.3-c22";
interrupt-parent = <&gpio4>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&pinctrl_ethphy1>;
pinctrl-names = "default";
reg = <7>;
reset-assert-us = <1000>;
reset-deassert-us = <1000>;
reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
rxc-skew-ps = <3000>;
rxd0-skew-ps = <0>;
rxd1-skew-ps = <0>;
rxd2-skew-ps = <0>;
rxd3-skew-ps = <0>;
rxdv-skew-ps = <0>;
txc-skew-ps = <3000>;
txd0-skew-ps = <0>;
txd1-skew-ps = <0>;
txd2-skew-ps = <0>;
txd3-skew-ps = <0>;
txen-skew-ps = <0>;
max-speed = <100>;
};
};
};
&flexcan1 {
status = "okay";
};
&usb3_1 {
fsl,over-current-active-low;
};

File diff suppressed because it is too large Load Diff

View File

@@ -43,6 +43,10 @@
u-boot,dm-spl;
};
&pinctrl_wdog {
u-boot,dm-spl;
};
&gpio1 {
u-boot,dm-spl;
};

View File

@@ -9,6 +9,14 @@
};
};
&pinctrl_uart1 {
u-boot,dm-spl;
};
&uart1 {
u-boot,dm-spl;
};
&binman {
u-boot-spl-ddr {
filename = "u-boot-spl-ddr.bin";

View File

@@ -2,30 +2,6 @@
#include "imx8mq-u-boot.dtsi"
&{/soc@0} {
u-boot,dm-spl;
};
&{/soc@0/bus@30000000} {
u-boot,dm-spl;
};
&{/soc@0/bus@30400000} {
u-boot,dm-spl;
};
&{/soc@0/bus@30800000} {
u-boot,dm-spl;
};
&{/soc@0/bus@32c00000} {
u-boot,dm-spl;
};
&iomuxc {
u-boot,dm-spl;
};
&pinctrl_uart1 {
u-boot,dm-spl;
};

View File

@@ -10,3 +10,18 @@
sd-uhs-sdr104;
sd-uhs-ddr50;
};
&uart1 {
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
};
&uart2 {
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
};
&uart3 {
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
};

View File

@@ -5,3 +5,11 @@
&reg_usdhc2_vmmc {
u-boot,off-on-delay-us = <20000>;
};
&uart1 {
u-boot,dm-spl;
};
&pinctrl_uart1 {
u-boot,dm-spl;
};

View File

@@ -0,0 +1,9 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
&pinctrl_uart1 {
u-boot,dm-spl;
};
&uart1 {
u-boot,dm-spl;
};

View File

@@ -10,6 +10,30 @@
};
&{/soc@0} {
u-boot,dm-spl;
};
&{/soc@0/bus@30000000} {
u-boot,dm-spl;
};
&{/soc@0/bus@30400000} {
u-boot,dm-spl;
};
&{/soc@0/bus@30800000} {
u-boot,dm-spl;
};
&{/soc@0/bus@32c00000} {
u-boot,dm-spl;
};
&iomuxc {
u-boot,dm-spl;
};
&binman {
u-boot-spl-ddr {
align = <4>;

View File

@@ -8,6 +8,10 @@
stdout-path = "serial2:115200n8";
tick-timer = &timer1;
};
memory@80000000 {
u-boot,dm-spl;
};
};
&cbass_main{

View File

@@ -27,7 +27,7 @@
device_type = "memory";
/* 2G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
u-boot,dm-spl;
};
a53_0: a53@0 {

View File

@@ -12,6 +12,10 @@
aliases {
mmc1 = &sdhci1;
};
memory@80000000 {
u-boot,dm-spl;
};
};
&cbass_main{
@@ -48,6 +52,67 @@
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
tps65219: pmic@30 {
compatible = "ti,tps65219";
reg = <0x30>;
regulators {
buck1_reg: buck1 {
regulator-name = "VDD_CORE";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <750000>;
regulator-boot-on;
regulator-always-on;
};
buck2_reg: buck2 {
regulator-name = "VCC1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
buck3_reg: buck3 {
regulator-name = "VDD_LPDDR4";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-boot-on;
regulator-always-on;
};
ldo1_reg: ldo1 {
regulator-name = "VDDSHV_SD_IO_PMIC";
regulator-min-microvolt = <33000000>;
regulator-max-microvolt = <33000000>;
};
ldo2_reg: ldo2 {
regulator-name = "VDDAR_CORE";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
regulator-boot-on;
regulator-always-on;
};
ldo3_reg: ldo3 {
regulator-name = "VDDA_1V8";
regulator-min-microvolt = <18000000>;
regulator-max-microvolt = <18000000>;
regulator-boot-on;
regulator-always-on;
};
ldo4_reg: ldo4 {
regulator-name = "VDD_PHY_2V5";
regulator-min-microvolt = <25000000>;
regulator-max-microvolt = <25000000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};
&main_uart0 {

View File

@@ -642,8 +642,7 @@
compatible = "rockchip,rk3188-grf", "syscon", "simple-mfd";
usbphy: usbphy {
compatible = "rockchip,rk3188-usb-phy",
"rockchip,rk3288-usb-phy";
compatible = "rockchip,rk3188-usb-phy";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";

View File

@@ -448,7 +448,7 @@
status = "okay";
};
&mipi_dsi0 {
&mipi_dsi {
status = "disabled";
rockchip,panel = <&panel>;
display-timings {

View File

@@ -86,47 +86,6 @@
};
};
amba {
compatible = "arm,amba-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
dmac_peri: dma-controller@ff250000 {
compatible = "arm,pl330", "arm,primecell";
broken-no-flushp;
reg = <0xff250000 0x4000>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
clocks = <&cru ACLK_DMAC2>;
clock-names = "apb_pclk";
};
dmac_bus_ns: dma-controller@ff600000 {
compatible = "arm,pl330", "arm,primecell";
broken-no-flushp;
reg = <0xff600000 0x4000>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
clocks = <&cru ACLK_DMAC1>;
clock-names = "apb_pclk";
status = "disabled";
};
dmac_bus_s: dma-controller@ffb20000 {
compatible = "arm,pl330", "arm,primecell";
broken-no-flushp;
reg = <0xffb20000 0x4000>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
clocks = <&cru ACLK_DMAC1>;
clock-names = "apb_pclk";
};
};
xin24m: oscillator {
compatible = "fixed-clock";
clock-frequency = <24000000>;
@@ -367,6 +326,18 @@
pinctrl-0 = <&uart4_xfer>;
status = "disabled";
};
dmac_peri: dma-controller@ff250000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0xff250000 0x4000>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
broken-no-flushp;
clocks = <&cru ACLK_DMAC2>;
clock-names = "apb_pclk";
};
thermal: thermal-zones {
#include "rk3288-thermal.dtsi"
};
@@ -458,6 +429,18 @@
status = "disabled";
};
dmac_bus_ns: dma-controller@ff600000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0xff600000 0x4000>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
broken-no-flushp;
clocks = <&cru ACLK_DMAC1>;
clock-names = "apb_pclk";
status = "disabled";
};
i2c0: i2c@ff650000 {
compatible = "rockchip,rk3288-i2c";
reg = <0xff650000 0x1000>;
@@ -709,7 +692,63 @@
status = "disabled";
};
edp: edp@ff970000 {
mipi_dsi: mipi@ff960000 {
compatible = "rockchip,rk3288_mipi_dsi";
reg = <0xff960000 0x4000>;
clocks = <&cru PCLK_MIPI_DSI0>;
clock-names = "pclk_mipi";
/*pinctrl-names = "default";
pinctrl-0 = <&lcdc0_ctl>;*/
rockchip,grf = <&grf>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
ports {
reg = <1>;
mipi_in: port {
#address-cells = <1>;
#size-cells = <0>;
mipi_in_vopb: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopb_out_mipi>;
};
mipi_in_vopl: endpoint@1 {
reg = <1>;
remote-endpoint = <&vopl_out_mipi>;
};
};
};
};
lvds: lvds@ff96c000 {
compatible = "rockchip,rk3288-lvds";
reg = <0xff96c000 0x4000>;
clocks = <&cru PCLK_LVDS_PHY>;
clock-names = "pclk_lvds";
pinctrl-names = "default";
pinctrl-0 = <&lcdc0_ctl>;
rockchip,grf = <&grf>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
lvds_in: port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
lvds_in_vopb: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopb_out_lvds>;
};
lvds_in_vopl: endpoint@1 {
reg = <1>;
remote-endpoint = <&vopl_out_lvds>;
};
};
};
};
edp: dp@ff970000 {
compatible = "rockchip,rk3288-edp";
reg = <0xff970000 0x4000>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
@@ -762,62 +801,6 @@
};
};
lvds: lvds@ff96c000 {
compatible = "rockchip,rk3288-lvds";
reg = <0xff96c000 0x4000>;
clocks = <&cru PCLK_LVDS_PHY>;
clock-names = "pclk_lvds";
pinctrl-names = "default";
pinctrl-0 = <&lcdc0_ctl>;
rockchip,grf = <&grf>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
lvds_in: port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
lvds_in_vopb: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopb_out_lvds>;
};
lvds_in_vopl: endpoint@1 {
reg = <1>;
remote-endpoint = <&vopl_out_lvds>;
};
};
};
};
mipi_dsi0: mipi@ff960000 {
compatible = "rockchip,rk3288_mipi_dsi";
reg = <0xff960000 0x4000>;
clocks = <&cru PCLK_MIPI_DSI0>;
clock-names = "pclk_mipi";
/*pinctrl-names = "default";
pinctrl-0 = <&lcdc0_ctl>;*/
rockchip,grf = <&grf>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
ports {
reg = <1>;
mipi_in: port {
#address-cells = <1>;
#size-cells = <0>;
mipi_in_vopb: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopb_out_mipi>;
};
mipi_in_vopl: endpoint@1 {
reg = <1>;
remote-endpoint = <&vopl_out_mipi>;
};
};
};
};
hdmi_audio: hdmi_audio {
compatible = "rockchip,rk3288-hdmi-audio";
i2s-controller = <&i2s>;
@@ -870,6 +853,17 @@
status = "disabled";
};
dmac_bus_s: dma-controller@ffb20000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0xffb20000 0x4000>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
broken-no-flushp;
clocks = <&cru ACLK_DMAC1>;
clock-names = "apb_pclk";
};
efuse: efuse@ffb40000 {
compatible = "rockchip,rk3288-efuse";
reg = <0xffb40000 0x10000>;
@@ -1072,411 +1066,411 @@
sleep {
global_pwroff: global-pwroff {
rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>;
};
ddrio_pwroff: ddrio-pwroff {
rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>;
};
ddr0_retention: ddr0-retention {
rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
rockchip,pins = <0 RK_PA2 1 &pcfg_pull_up>;
};
ddr1_retention: ddr1-retention {
rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>;
};
};
i2c0 {
i2c0_xfer: i2c0-xfer {
rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
<0 16 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>,
<0 RK_PC0 1 &pcfg_pull_none>;
};
};
i2c1 {
i2c1_xfer: i2c1-xfer {
rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
<8 5 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <8 RK_PA4 1 &pcfg_pull_none>,
<8 RK_PA5 1 &pcfg_pull_none>;
};
};
i2c2 {
i2c2_xfer: i2c2-xfer {
rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
<6 10 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <6 RK_PB1 1 &pcfg_pull_none>,
<6 RK_PB2 1 &pcfg_pull_none>;
};
};
i2c3 {
i2c3_xfer: i2c3-xfer {
rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
<2 17 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>,
<2 RK_PC1 1 &pcfg_pull_none>;
};
};
i2c4 {
i2c4_xfer: i2c4-xfer {
rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
<7 18 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <7 RK_PC1 1 &pcfg_pull_none>,
<7 RK_PC2 1 &pcfg_pull_none>;
};
};
i2c5 {
i2c5_xfer: i2c5-xfer {
rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
<7 20 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <7 RK_PC3 1 &pcfg_pull_none>,
<7 RK_PC4 1 &pcfg_pull_none>;
};
};
i2s0 {
i2s0_bus: i2s0-bus {
rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
<6 1 RK_FUNC_1 &pcfg_pull_none>,
<6 2 RK_FUNC_1 &pcfg_pull_none>,
<6 3 RK_FUNC_1 &pcfg_pull_none>,
<6 4 RK_FUNC_1 &pcfg_pull_none>,
<6 8 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <6 RK_PA0 1 &pcfg_pull_none>,
<6 RK_PA1 1 &pcfg_pull_none>,
<6 RK_PA2 1 &pcfg_pull_none>,
<6 RK_PA3 1 &pcfg_pull_none>,
<6 RK_PA4 1 &pcfg_pull_none>,
<6 RK_PB0 1 &pcfg_pull_none>;
};
};
lcdc0 {
lcdc0_ctl: lcdc0-ctl {
rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>,
<1 25 RK_FUNC_1 &pcfg_pull_none>,
<1 26 RK_FUNC_1 &pcfg_pull_none>,
<1 27 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>,
<1 RK_PD1 1 &pcfg_pull_none>,
<1 RK_PD2 1 &pcfg_pull_none>,
<1 RK_PD3 1 &pcfg_pull_none>;
};
};
sdmmc {
sdmmc_clk: sdmmc-clk {
rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none>;
};
sdmmc_cmd: sdmmc-cmd {
rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up>;
};
sdmmc_cd: sdmcc-cd {
rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
rockchip,pins = <6 RK_PC6 1 &pcfg_pull_up>;
};
sdmmc_bus1: sdmmc-bus1 {
rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>;
};
sdmmc_bus4: sdmmc-bus4 {
rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
<6 17 RK_FUNC_1 &pcfg_pull_up>,
<6 18 RK_FUNC_1 &pcfg_pull_up>,
<6 19 RK_FUNC_1 &pcfg_pull_up>;
rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>,
<6 RK_PC1 1 &pcfg_pull_up>,
<6 RK_PC2 1 &pcfg_pull_up>,
<6 RK_PC3 1 &pcfg_pull_up>;
};
};
sdio0 {
sdio0_bus1: sdio0-bus1 {
rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>;
};
sdio0_bus4: sdio0-bus4 {
rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
<4 21 RK_FUNC_1 &pcfg_pull_up>,
<4 22 RK_FUNC_1 &pcfg_pull_up>,
<4 23 RK_FUNC_1 &pcfg_pull_up>;
rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>,
<4 RK_PC5 1 &pcfg_pull_up>,
<4 RK_PC6 1 &pcfg_pull_up>,
<4 RK_PC7 1 &pcfg_pull_up>;
};
sdio0_cmd: sdio0-cmd {
rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
rockchip,pins = <4 RK_PD0 1 &pcfg_pull_up>;
};
sdio0_clk: sdio0-clk {
rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none>;
};
sdio0_cd: sdio0-cd {
rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
rockchip,pins = <4 RK_PD2 1 &pcfg_pull_up>;
};
sdio0_wp: sdio0-wp {
rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
rockchip,pins = <4 RK_PD3 1 &pcfg_pull_up>;
};
sdio0_pwr: sdio0-pwr {
rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
rockchip,pins = <4 RK_PD4 1 &pcfg_pull_up>;
};
sdio0_bkpwr: sdio0-bkpwr {
rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
rockchip,pins = <4 RK_PD5 1 &pcfg_pull_up>;
};
sdio0_int: sdio0-int {
rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
rockchip,pins = <4 RK_PD6 1 &pcfg_pull_up>;
};
};
sdio1 {
sdio1_bus1: sdio1-bus1 {
rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>;
rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>;
};
sdio1_bus4: sdio1-bus4 {
rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>,
<3 25 RK_FUNC_4 &pcfg_pull_up>,
<3 26 RK_FUNC_4 &pcfg_pull_up>,
<3 27 RK_FUNC_4 &pcfg_pull_up>;
rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>,
<3 RK_PD1 4 &pcfg_pull_up>,
<3 RK_PD2 4 &pcfg_pull_up>,
<3 RK_PD3 4 &pcfg_pull_up>;
};
sdio1_cd: sdio1-cd {
rockchip,pins = <3 28 RK_FUNC_4 &pcfg_pull_up>;
rockchip,pins = <3 RK_PD4 4 &pcfg_pull_up>;
};
sdio1_wp: sdio1-wp {
rockchip,pins = <3 29 RK_FUNC_4 &pcfg_pull_up>;
rockchip,pins = <3 RK_PD5 4 &pcfg_pull_up>;
};
sdio1_bkpwr: sdio1-bkpwr {
rockchip,pins = <3 30 RK_FUNC_4 &pcfg_pull_up>;
rockchip,pins = <3 RK_PD6 4 &pcfg_pull_up>;
};
sdio1_int: sdio1-int {
rockchip,pins = <3 31 RK_FUNC_4 &pcfg_pull_up>;
rockchip,pins = <3 RK_PD7 4 &pcfg_pull_up>;
};
sdio1_cmd: sdio1-cmd {
rockchip,pins = <4 6 RK_FUNC_4 &pcfg_pull_up>;
rockchip,pins = <4 RK_PA6 4 &pcfg_pull_up>;
};
sdio1_clk: sdio1-clk {
rockchip,pins = <4 7 RK_FUNC_4 &pcfg_pull_none>;
rockchip,pins = <4 RK_PA7 4 &pcfg_pull_none>;
};
sdio1_pwr: sdio1-pwr {
rockchip,pins = <4 9 RK_FUNC_4 &pcfg_pull_up>;
rockchip,pins = <4 RK_PB1 4 &pcfg_pull_up>;
};
};
emmc {
emmc_clk: emmc-clk {
rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none>;
};
emmc_cmd: emmc-cmd {
rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
rockchip,pins = <3 RK_PC0 2 &pcfg_pull_up>;
};
emmc_pwr: emmc-pwr {
rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
rockchip,pins = <3 RK_PB1 2 &pcfg_pull_up>;
};
emmc_bus1: emmc-bus1 {
rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>;
};
emmc_bus4: emmc-bus4 {
rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
<3 1 RK_FUNC_2 &pcfg_pull_up>,
<3 2 RK_FUNC_2 &pcfg_pull_up>,
<3 3 RK_FUNC_2 &pcfg_pull_up>;
rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>,
<3 RK_PA1 2 &pcfg_pull_up>,
<3 RK_PA2 2 &pcfg_pull_up>,
<3 RK_PA3 2 &pcfg_pull_up>;
};
emmc_bus8: emmc-bus8 {
rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
<3 1 RK_FUNC_2 &pcfg_pull_up>,
<3 2 RK_FUNC_2 &pcfg_pull_up>,
<3 3 RK_FUNC_2 &pcfg_pull_up>,
<3 4 RK_FUNC_2 &pcfg_pull_up>,
<3 5 RK_FUNC_2 &pcfg_pull_up>,
<3 6 RK_FUNC_2 &pcfg_pull_up>,
<3 7 RK_FUNC_2 &pcfg_pull_up>;
rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>,
<3 RK_PA1 2 &pcfg_pull_up>,
<3 RK_PA2 2 &pcfg_pull_up>,
<3 RK_PA3 2 &pcfg_pull_up>,
<3 RK_PA4 2 &pcfg_pull_up>,
<3 RK_PA5 2 &pcfg_pull_up>,
<3 RK_PA6 2 &pcfg_pull_up>,
<3 RK_PA7 2 &pcfg_pull_up>;
};
};
spi0 {
spi0_clk: spi0-clk {
rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
rockchip,pins = <5 RK_PB4 1 &pcfg_pull_up>;
};
spi0_cs0: spi0-cs0 {
rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
rockchip,pins = <5 RK_PB5 1 &pcfg_pull_up>;
};
spi0_tx: spi0-tx {
rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
rockchip,pins = <5 RK_PB6 1 &pcfg_pull_up>;
};
spi0_rx: spi0-rx {
rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
rockchip,pins = <5 RK_PB7 1 &pcfg_pull_up>;
};
spi0_cs1: spi0-cs1 {
rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
rockchip,pins = <5 RK_PC0 1 &pcfg_pull_up>;
};
};
spi1 {
spi1_clk: spi1-clk {
rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
rockchip,pins = <7 RK_PB4 2 &pcfg_pull_up>;
};
spi1_cs0: spi1-cs0 {
rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
rockchip,pins = <7 RK_PB5 2 &pcfg_pull_up>;
};
spi1_rx: spi1-rx {
rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
rockchip,pins = <7 RK_PB6 2 &pcfg_pull_up>;
};
spi1_tx: spi1-tx {
rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
rockchip,pins = <7 RK_PB7 2 &pcfg_pull_up>;
};
};
spi2 {
spi2_cs1: spi2-cs1 {
rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
rockchip,pins = <8 RK_PA3 1 &pcfg_pull_up>;
};
spi2_clk: spi2-clk {
rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
rockchip,pins = <8 RK_PA6 1 &pcfg_pull_up>;
};
spi2_cs0: spi2-cs0 {
rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
rockchip,pins = <8 RK_PA7 1 &pcfg_pull_up>;
};
spi2_rx: spi2-rx {
rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
rockchip,pins = <8 RK_PB0 1 &pcfg_pull_up>;
};
spi2_tx: spi2-tx {
rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
rockchip,pins = <8 RK_PB1 1 &pcfg_pull_up>;
};
};
uart0 {
uart0_xfer: uart0-xfer {
rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
<4 17 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <4 RK_PC0 1 &pcfg_pull_up>,
<4 RK_PC1 1 &pcfg_pull_none>;
};
uart0_cts: uart0-cts {
rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <4 RK_PC2 1 &pcfg_pull_none>;
};
uart0_rts: uart0-rts {
rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <4 RK_PC3 1 &pcfg_pull_none>;
};
};
uart1 {
uart1_xfer: uart1-xfer {
rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
<5 9 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <5 RK_PB0 1 &pcfg_pull_up>,
<5 RK_PB1 1 &pcfg_pull_none>;
};
uart1_cts: uart1-cts {
rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <5 RK_PB2 1 &pcfg_pull_none>;
};
uart1_rts: uart1-rts {
rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <5 RK_PB3 1 &pcfg_pull_none>;
};
};
uart2 {
uart2_xfer: uart2-xfer {
rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
<7 23 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <7 RK_PC6 1 &pcfg_pull_up>,
<7 RK_PC7 1 &pcfg_pull_none>;
};
/* no rts / cts for uart2 */
};
uart3 {
uart3_xfer: uart3-xfer {
rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
<7 8 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <7 RK_PA7 1 &pcfg_pull_up>,
<7 RK_PB0 1 &pcfg_pull_none>;
};
uart3_cts: uart3-cts {
rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <7 RK_PB1 1 &pcfg_pull_none>;
};
uart3_rts: uart3-rts {
rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <7 RK_PB2 1 &pcfg_pull_none>;
};
};
uart4 {
uart4_xfer: uart4-xfer {
rockchip,pins = <5 12 3 &pcfg_pull_up>,
<5 13 3 &pcfg_pull_none>;
rockchip,pins = <5 RK_PB4 3 &pcfg_pull_up>,
<5 RK_PB5 3 &pcfg_pull_none>;
};
uart4_cts: uart4-cts {
rockchip,pins = <5 14 3 &pcfg_pull_none>;
rockchip,pins = <5 RK_PB6 3 &pcfg_pull_none>;
};
uart4_rts: uart4-rts {
rockchip,pins = <5 15 3 &pcfg_pull_none>;
rockchip,pins = <5 RK_PB7 3 &pcfg_pull_none>;
};
};
tsadc {
otp_out: otp-out {
rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <0 RK_PB2 1 &pcfg_pull_none>;
};
};
pwm0 {
pwm0_pin: pwm0-pin {
rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <7 RK_PA0 1 &pcfg_pull_none>;
};
};
pwm1 {
pwm1_pin: pwm1-pin {
rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <7 RK_PA1 1 &pcfg_pull_none>;
};
};
pwm2 {
pwm2_pin: pwm2-pin {
rockchip,pins = <7 22 RK_FUNC_3 &pcfg_pull_none>;
rockchip,pins = <7 RK_PC6 3 &pcfg_pull_none>;
};
};
pwm3 {
pwm3_pin: pwm3-pin {
rockchip,pins = <7 23 RK_FUNC_3 &pcfg_pull_none>;
rockchip,pins = <7 RK_PC7 3 &pcfg_pull_none>;
};
};
gmac {
rgmii_pins: rgmii-pins {
rockchip,pins = <3 30 3 &pcfg_pull_none>,
<3 31 3 &pcfg_pull_none>,
<3 26 3 &pcfg_pull_none>,
<3 27 3 &pcfg_pull_none>,
<3 28 3 &pcfg_pull_none_12ma>,
<3 29 3 &pcfg_pull_none_12ma>,
<3 24 3 &pcfg_pull_none_12ma>,
<3 25 3 &pcfg_pull_none_12ma>,
<4 0 3 &pcfg_pull_none>,
<4 5 3 &pcfg_pull_none>,
<4 6 3 &pcfg_pull_none>,
<4 9 3 &pcfg_pull_none_12ma>,
<4 4 3 &pcfg_pull_none_12ma>,
<4 1 3 &pcfg_pull_none>,
<4 3 3 &pcfg_pull_none>;
rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>,
<3 RK_PD7 3 &pcfg_pull_none>,
<3 RK_PD2 3 &pcfg_pull_none>,
<3 RK_PD3 3 &pcfg_pull_none>,
<3 RK_PD4 3 &pcfg_pull_none_12ma>,
<3 RK_PD5 3 &pcfg_pull_none_12ma>,
<3 RK_PD0 3 &pcfg_pull_none_12ma>,
<3 RK_PD1 3 &pcfg_pull_none_12ma>,
<4 RK_PA0 3 &pcfg_pull_none>,
<4 RK_PA5 3 &pcfg_pull_none>,
<4 RK_PA6 3 &pcfg_pull_none>,
<4 RK_PB1 3 &pcfg_pull_none_12ma>,
<4 RK_PA4 3 &pcfg_pull_none_12ma>,
<4 RK_PA1 3 &pcfg_pull_none>,
<4 RK_PA3 3 &pcfg_pull_none>;
};
rmii_pins: rmii-pins {
rockchip,pins = <3 30 3 &pcfg_pull_none>,
<3 31 3 &pcfg_pull_none>,
<3 28 3 &pcfg_pull_none>,
<3 29 3 &pcfg_pull_none>,
<4 0 3 &pcfg_pull_none>,
<4 5 3 &pcfg_pull_none>,
<4 4 3 &pcfg_pull_none>,
<4 1 3 &pcfg_pull_none>,
<4 2 3 &pcfg_pull_none>,
<4 3 3 &pcfg_pull_none>;
rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>,
<3 RK_PD7 3 &pcfg_pull_none>,
<3 RK_PD4 3 &pcfg_pull_none>,
<3 RK_PD5 3 &pcfg_pull_none>,
<4 RK_PA0 3 &pcfg_pull_none>,
<4 RK_PA5 3 &pcfg_pull_none>,
<4 RK_PA4 3 &pcfg_pull_none>,
<4 RK_PA1 3 &pcfg_pull_none>,
<4 RK_PA2 3 &pcfg_pull_none>,
<4 RK_PA3 3 &pcfg_pull_none>;
};
};
spdif {
spdif_tx: spdif-tx {
rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <6 RK_PB3 1 &pcfg_pull_none>;
};
};
};

View File

@@ -17,6 +17,7 @@
/ {
model = "Pine64 Pinebook Pro";
compatible = "pine64,pinebook-pro", "rockchip,rk3399";
chassis-type = "laptop";
aliases {
mmc0 = &sdio0;
@@ -242,12 +243,12 @@
vdd_log: vdd-log {
compatible = "pwm-regulator";
pwms = <&pwm2 0 25000 1>;
pwm-supply = <&vcc_sysin>;
regulator-name = "vdd_log";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
vin-supply = <&vcc_sysin>;
regulator-state-mem {
regulator-on-in-suspend;
@@ -385,10 +386,6 @@
};
};
&cdn_dp {
status = "okay";
};
&cpu_b0 {
cpu-supply = <&vdd_cpu_b>;
};
@@ -475,8 +472,6 @@
vcc10-supply = <&vcc_sysin>;
vcc11-supply = <&vcc_sysin>;
vcc12-supply = <&vcc3v3_sys>;
vcc13-supply = <&vcc_sysin>;
vcc14-supply = <&vcc_sysin>;
regulators {
/* rk3399 center logic supply */
@@ -711,7 +706,7 @@
connector {
compatible = "usb-c-connector";
data-role = "host";
data-role = "dual";
label = "USB-C";
op-sink-microwatt = <1000000>;
power-role = "dual";

View File

@@ -2,7 +2,7 @@
/*
* U-Boot additions
*
* Copyright (C) 2019 Intel Corporation <www.intel.com>
* Copyright (C) 2019-2022 Intel Corporation <www.intel.com>
*/
#include "socfpga_agilex-u-boot.dtsi"
@@ -11,6 +11,15 @@
aliases {
spi0 = &qspi;
i2c0 = &i2c1;
freeze_br0 = &freeze_controller;
};
soc {
freeze_controller: freeze_controller@f9000450 {
compatible = "altr,freeze-bridge-controller";
reg = <0xf9000450 0x00000010>;
status = "disabled";
};
};
memory {

View File

@@ -0,0 +1,90 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2022 Google LLC
*/
/dts-v1/;
#include "socfpga_arria10_mercury_aa1.dtsi"
/ {
model = "Google Chameleon V3";
compatible = "google,chameleon-v3",
"altr,socfpga-arria10", "altr,socfpga";
aliases {
serial0 = &uart0;
i2c0 = &i2c0;
i2c1 = &i2c1;
};
};
&gmac0 {
status = "okay";
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&gpio2 {
status = "okay";
};
&i2c0 {
status = "okay";
ssm2603: ssm2603@1a {
compatible = "adi,ssm2603";
reg = <0x1a>;
};
};
&i2c1 {
status = "okay";
u80: u80@21 {
compatible = "nxp,pca9535";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names =
"SOM_AUD_MUTE",
"DP1_OUT_CEC_EN",
"DP2_OUT_CEC_EN",
"DP1_SOM_PS8469_CAD",
"DPD_SOM_PS8469_CAD",
"DP_OUT_PWR_EN",
"STM32_RST_L",
"STM32_BOOT0",
"FPGA_PROT",
"STM32_FPGA_COMM0",
"TP119",
"TP120",
"TP121",
"TP122",
"TP123",
"TP124";
};
};
&mmc {
status = "okay";
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&usb0 {
status = "okay";
dr_mode = "host";
};

View File

@@ -0,0 +1,8 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2022 Google LLC
*/
#include "socfpga_arria10_chameleonv3_270_3_handoff.h"
#include "socfpga_arria10-handoff.dtsi"
#include "socfpga_arria10_handoff_u-boot.dtsi"
#include "socfpga_arria10_mercury_aa1-u-boot.dtsi"

View File

@@ -0,0 +1,5 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2022 Google LLC
*/
#include "socfpga_arria10_chameleonv3.dts"

View File

@@ -0,0 +1,305 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Intel Arria 10 SoCFPGA configuration
*/
#ifndef __SOCFPGA_ARRIA10_CONFIG_H__
#define __SOCFPGA_ARRIA10_CONFIG_H__
/* Clocks */
#define CB_INTOSC_LS_CLK_HZ 60000000
#define EMAC0_CLK_HZ 250000000
#define EMAC1_CLK_HZ 250000000
#define EMAC2_CLK_HZ 250000000
#define EOSC1_CLK_HZ 33330000
#define F2H_FREE_CLK_HZ 200000000
#define H2F_USER0_CLK_HZ 200000000
#define H2F_USER1_CLK_HZ 100000000
#define L3_MAIN_FREE_CLK_HZ 200000000
#define SDMMC_CLK_HZ 200000000
#define TPIU_CLK_HZ 100000000
#define MAINPLLGRP_CNTR15CLK_CNT 900
#define MAINPLLGRP_CNTR2CLK_CNT 900
#define MAINPLLGRP_CNTR3CLK_CNT 900
#define MAINPLLGRP_CNTR4CLK_CNT 900
#define MAINPLLGRP_CNTR5CLK_CNT 900
#define MAINPLLGRP_CNTR6CLK_CNT 7
#define MAINPLLGRP_CNTR7CLK_CNT 7
#define MAINPLLGRP_CNTR7CLK_SRC 0
#define MAINPLLGRP_CNTR8CLK_CNT 15
#define MAINPLLGRP_CNTR9CLK_CNT 900
#define MAINPLLGRP_CNTR9CLK_SRC 0
#define MAINPLLGRP_MPUCLK_CNT 0
#define MAINPLLGRP_MPUCLK_SRC 0
#define MAINPLLGRP_NOCCLK_CNT 0
#define MAINPLLGRP_NOCCLK_SRC 0
#define MAINPLLGRP_NOCDIV_CSATCLK 0
#define MAINPLLGRP_NOCDIV_CSPDBGCLK 1
#define MAINPLLGRP_NOCDIV_CSTRACECLK 0
#define MAINPLLGRP_NOCDIV_L4MAINCLK 0
#define MAINPLLGRP_NOCDIV_L4MPCLK 1
#define MAINPLLGRP_NOCDIV_L4SPCLK 2
#define MAINPLLGRP_VCO0_PSRC 0
#define MAINPLLGRP_VCO1_DENOM 32
#define MAINPLLGRP_VCO1_NUMER 1584
#define PERPLLGRP_CNTR2CLK_CNT 5
#define PERPLLGRP_CNTR2CLK_SRC 1
#define PERPLLGRP_CNTR3CLK_CNT 900
#define PERPLLGRP_CNTR3CLK_SRC 1
#define PERPLLGRP_CNTR4CLK_CNT 14
#define PERPLLGRP_CNTR4CLK_SRC 1
#define PERPLLGRP_CNTR5CLK_CNT 374
#define PERPLLGRP_CNTR5CLK_SRC 1
#define PERPLLGRP_CNTR6CLK_CNT 900
#define PERPLLGRP_CNTR6CLK_SRC 0
#define PERPLLGRP_CNTR7CLK_CNT 900
#define PERPLLGRP_CNTR8CLK_CNT 900
#define PERPLLGRP_CNTR8CLK_SRC 0
#define PERPLLGRP_CNTR9CLK_CNT 900
#define PERPLLGRP_EMACCTL_EMAC0SEL 0
#define PERPLLGRP_EMACCTL_EMAC1SEL 0
#define PERPLLGRP_EMACCTL_EMAC2SEL 0
#define PERPLLGRP_GPIODIV_GPIODBCLK 32000
#define PERPLLGRP_VCO0_PSRC 0
#define PERPLLGRP_VCO1_DENOM 32
#define PERPLLGRP_VCO1_NUMER 1485
#define CLKMGR_TESTIOCTRL_DEBUGCLKSEL 16
#define CLKMGR_TESTIOCTRL_MAINCLKSEL 8
#define CLKMGR_TESTIOCTRL_PERICLKSEL 8
#define ALTERAGRP_MPUCLK_MAINCNT 1
#define ALTERAGRP_MPUCLK_PERICNT 900
#define ALTERAGRP_NOCCLK_MAINCNT 7
#define ALTERAGRP_NOCCLK_PERICNT 900
#define ALTERAGRP_MPUCLK ((ALTERAGRP_MPUCLK_PERICNT << 16) | \
(ALTERAGRP_MPUCLK_MAINCNT))
#define ALTERAGRP_NOCCLK ((ALTERAGRP_NOCCLK_PERICNT << 16) | \
(ALTERAGRP_NOCCLK_MAINCNT))
/* Pin Mux Configuration */
#define CONFIG_IO_10_INPUT_BUF_EN 1
#define CONFIG_IO_10_PD_DRV_STRG 10
#define CONFIG_IO_10_PD_SLW_RT 1
#define CONFIG_IO_10_PU_DRV_STRG 8
#define CONFIG_IO_10_PU_SLW_RT 1
#define CONFIG_IO_10_RTRIM 1
#define CONFIG_IO_10_WK_PU_EN 0
#define CONFIG_IO_11_INPUT_BUF_EN 1
#define CONFIG_IO_11_PD_DRV_STRG 10
#define CONFIG_IO_11_PD_SLW_RT 1
#define CONFIG_IO_11_PU_DRV_STRG 8
#define CONFIG_IO_11_PU_SLW_RT 1
#define CONFIG_IO_11_RTRIM 1
#define CONFIG_IO_11_WK_PU_EN 0
#define CONFIG_IO_12_INPUT_BUF_EN 0
#define CONFIG_IO_12_PD_DRV_STRG 0
#define CONFIG_IO_12_PD_SLW_RT 0
#define CONFIG_IO_12_PU_DRV_STRG 0
#define CONFIG_IO_12_PU_SLW_RT 0
#define CONFIG_IO_12_RTRIM 1
#define CONFIG_IO_12_WK_PU_EN 1
#define CONFIG_IO_13_INPUT_BUF_EN 0
#define CONFIG_IO_13_PD_DRV_STRG 0
#define CONFIG_IO_13_PD_SLW_RT 0
#define CONFIG_IO_13_PU_DRV_STRG 0
#define CONFIG_IO_13_PU_SLW_RT 0
#define CONFIG_IO_13_RTRIM 1
#define CONFIG_IO_13_WK_PU_EN 1
#define CONFIG_IO_14_INPUT_BUF_EN 0
#define CONFIG_IO_14_PD_DRV_STRG 0
#define CONFIG_IO_14_PD_SLW_RT 0
#define CONFIG_IO_14_PU_DRV_STRG 0
#define CONFIG_IO_14_PU_SLW_RT 0
#define CONFIG_IO_14_RTRIM 1
#define CONFIG_IO_14_WK_PU_EN 1
#define CONFIG_IO_15_INPUT_BUF_EN 0
#define CONFIG_IO_15_PD_DRV_STRG 0
#define CONFIG_IO_15_PD_SLW_RT 0
#define CONFIG_IO_15_PU_DRV_STRG 0
#define CONFIG_IO_15_PU_SLW_RT 0
#define CONFIG_IO_15_RTRIM 1
#define CONFIG_IO_15_WK_PU_EN 1
#define CONFIG_IO_16_INPUT_BUF_EN 0
#define CONFIG_IO_16_PD_DRV_STRG 10
#define CONFIG_IO_16_PD_SLW_RT 1
#define CONFIG_IO_16_PU_DRV_STRG 8
#define CONFIG_IO_16_PU_SLW_RT 1
#define CONFIG_IO_16_RTRIM 1
#define CONFIG_IO_16_WK_PU_EN 0
#define CONFIG_IO_17_INPUT_BUF_EN 1
#define CONFIG_IO_17_PD_DRV_STRG 10
#define CONFIG_IO_17_PD_SLW_RT 1
#define CONFIG_IO_17_PU_DRV_STRG 8
#define CONFIG_IO_17_PU_SLW_RT 1
#define CONFIG_IO_17_RTRIM 1
#define CONFIG_IO_17_WK_PU_EN 0
#define CONFIG_IO_1_INPUT_BUF_EN 1
#define CONFIG_IO_1_PD_DRV_STRG 10
#define CONFIG_IO_1_PD_SLW_RT 0
#define CONFIG_IO_1_PU_DRV_STRG 8
#define CONFIG_IO_1_PU_SLW_RT 0
#define CONFIG_IO_1_RTRIM 1
#define CONFIG_IO_1_WK_PU_EN 1
#define CONFIG_IO_2_INPUT_BUF_EN 1
#define CONFIG_IO_2_PD_DRV_STRG 10
#define CONFIG_IO_2_PD_SLW_RT 0
#define CONFIG_IO_2_PU_DRV_STRG 8
#define CONFIG_IO_2_PU_SLW_RT 0
#define CONFIG_IO_2_RTRIM 1
#define CONFIG_IO_2_WK_PU_EN 1
#define CONFIG_IO_3_INPUT_BUF_EN 1
#define CONFIG_IO_3_PD_DRV_STRG 10
#define CONFIG_IO_3_PD_SLW_RT 0
#define CONFIG_IO_3_PU_DRV_STRG 8
#define CONFIG_IO_3_PU_SLW_RT 0
#define CONFIG_IO_3_RTRIM 1
#define CONFIG_IO_3_WK_PU_EN 1
#define CONFIG_IO_4_INPUT_BUF_EN 1
#define CONFIG_IO_4_PD_DRV_STRG 10
#define CONFIG_IO_4_PD_SLW_RT 1
#define CONFIG_IO_4_PU_DRV_STRG 8
#define CONFIG_IO_4_PU_SLW_RT 1
#define CONFIG_IO_4_RTRIM 1
#define CONFIG_IO_4_WK_PU_EN 0
#define CONFIG_IO_5_INPUT_BUF_EN 1
#define CONFIG_IO_5_PD_DRV_STRG 10
#define CONFIG_IO_5_PD_SLW_RT 1
#define CONFIG_IO_5_PU_DRV_STRG 8
#define CONFIG_IO_5_PU_SLW_RT 1
#define CONFIG_IO_5_RTRIM 1
#define CONFIG_IO_5_WK_PU_EN 0
#define CONFIG_IO_6_INPUT_BUF_EN 0
#define CONFIG_IO_6_PD_DRV_STRG 10
#define CONFIG_IO_6_PD_SLW_RT 1
#define CONFIG_IO_6_PU_DRV_STRG 8
#define CONFIG_IO_6_PU_SLW_RT 1
#define CONFIG_IO_6_RTRIM 1
#define CONFIG_IO_6_WK_PU_EN 0
#define CONFIG_IO_7_INPUT_BUF_EN 1
#define CONFIG_IO_7_PD_DRV_STRG 10
#define CONFIG_IO_7_PD_SLW_RT 1
#define CONFIG_IO_7_PU_DRV_STRG 8
#define CONFIG_IO_7_PU_SLW_RT 1
#define CONFIG_IO_7_RTRIM 1
#define CONFIG_IO_7_WK_PU_EN 0
#define CONFIG_IO_8_INPUT_BUF_EN 1
#define CONFIG_IO_8_PD_DRV_STRG 10
#define CONFIG_IO_8_PD_SLW_RT 1
#define CONFIG_IO_8_PU_DRV_STRG 8
#define CONFIG_IO_8_PU_SLW_RT 1
#define CONFIG_IO_8_RTRIM 1
#define CONFIG_IO_8_WK_PU_EN 0
#define CONFIG_IO_9_INPUT_BUF_EN 1
#define CONFIG_IO_9_PD_DRV_STRG 10
#define CONFIG_IO_9_PD_SLW_RT 1
#define CONFIG_IO_9_PU_DRV_STRG 8
#define CONFIG_IO_9_PU_SLW_RT 1
#define CONFIG_IO_9_RTRIM 1
#define CONFIG_IO_9_WK_PU_EN 0
#define CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO 1
#define CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO 1
#define PINMUX_DEDICATED_IO_10_SEL 15
#define PINMUX_DEDICATED_IO_11_SEL 15
#define PINMUX_DEDICATED_IO_12_SEL 1
#define PINMUX_DEDICATED_IO_13_SEL 1
#define PINMUX_DEDICATED_IO_14_SEL 10
#define PINMUX_DEDICATED_IO_15_SEL 10
#define PINMUX_DEDICATED_IO_16_SEL 13
#define PINMUX_DEDICATED_IO_17_SEL 13
#define PINMUX_DEDICATED_IO_4_SEL 8
#define PINMUX_DEDICATED_IO_5_SEL 8
#define PINMUX_DEDICATED_IO_6_SEL 8
#define PINMUX_DEDICATED_IO_7_SEL 8
#define PINMUX_DEDICATED_IO_8_SEL 8
#define PINMUX_DEDICATED_IO_9_SEL 8
#define PINMUX_I2C0_USEFPGA_SEL 1
#define PINMUX_I2C1_USEFPGA_SEL 0
#define PINMUX_I2CEMAC0_USEFPGA_SEL 0
#define PINMUX_I2CEMAC1_USEFPGA_SEL 0
#define PINMUX_I2CEMAC2_USEFPGA_SEL 0
#define PINMUX_NAND_USEFPGA_SEL 0
#define PINMUX_PLL_CLOCK_OUT_USEFPGA_SEL 0
#define PINMUX_QSPI_USEFPGA_SEL 0
#define PINMUX_RGMII0_USEFPGA_SEL 0
#define PINMUX_RGMII1_USEFPGA_SEL 0
#define PINMUX_RGMII2_USEFPGA_SEL 0
#define PINMUX_SDMMC_USEFPGA_SEL 0
#define PINMUX_SHARED_IO_Q1_10_SEL 8
#define PINMUX_SHARED_IO_Q1_11_SEL 8
#define PINMUX_SHARED_IO_Q1_12_SEL 8
#define PINMUX_SHARED_IO_Q1_1_SEL 8
#define PINMUX_SHARED_IO_Q1_2_SEL 8
#define PINMUX_SHARED_IO_Q1_3_SEL 8
#define PINMUX_SHARED_IO_Q1_4_SEL 8
#define PINMUX_SHARED_IO_Q1_5_SEL 8
#define PINMUX_SHARED_IO_Q1_6_SEL 8
#define PINMUX_SHARED_IO_Q1_7_SEL 8
#define PINMUX_SHARED_IO_Q1_8_SEL 8
#define PINMUX_SHARED_IO_Q1_9_SEL 8
#define PINMUX_SHARED_IO_Q2_10_SEL 4
#define PINMUX_SHARED_IO_Q2_11_SEL 4
#define PINMUX_SHARED_IO_Q2_12_SEL 4
#define PINMUX_SHARED_IO_Q2_1_SEL 4
#define PINMUX_SHARED_IO_Q2_2_SEL 4
#define PINMUX_SHARED_IO_Q2_3_SEL 4
#define PINMUX_SHARED_IO_Q2_4_SEL 4
#define PINMUX_SHARED_IO_Q2_5_SEL 4
#define PINMUX_SHARED_IO_Q2_6_SEL 4
#define PINMUX_SHARED_IO_Q2_7_SEL 4
#define PINMUX_SHARED_IO_Q2_8_SEL 4
#define PINMUX_SHARED_IO_Q2_9_SEL 4
#define PINMUX_SHARED_IO_Q3_10_SEL 15
#define PINMUX_SHARED_IO_Q3_11_SEL 1
#define PINMUX_SHARED_IO_Q3_12_SEL 1
#define PINMUX_SHARED_IO_Q3_1_SEL 15
#define PINMUX_SHARED_IO_Q3_2_SEL 15
#define PINMUX_SHARED_IO_Q3_3_SEL 15
#define PINMUX_SHARED_IO_Q3_4_SEL 15
#define PINMUX_SHARED_IO_Q3_5_SEL 15
#define PINMUX_SHARED_IO_Q3_6_SEL 15
#define PINMUX_SHARED_IO_Q3_7_SEL 0
#define PINMUX_SHARED_IO_Q3_8_SEL 0
#define PINMUX_SHARED_IO_Q3_9_SEL 15
#define PINMUX_SHARED_IO_Q4_10_SEL 10
#define PINMUX_SHARED_IO_Q4_11_SEL 10
#define PINMUX_SHARED_IO_Q4_12_SEL 10
#define PINMUX_SHARED_IO_Q4_1_SEL 10
#define PINMUX_SHARED_IO_Q4_2_SEL 10
#define PINMUX_SHARED_IO_Q4_3_SEL 10
#define PINMUX_SHARED_IO_Q4_4_SEL 10
#define PINMUX_SHARED_IO_Q4_5_SEL 10
#define PINMUX_SHARED_IO_Q4_6_SEL 10
#define PINMUX_SHARED_IO_Q4_7_SEL 10
#define PINMUX_SHARED_IO_Q4_8_SEL 10
#define PINMUX_SHARED_IO_Q4_9_SEL 10
#define PINMUX_SPIM0_USEFPGA_SEL 0
#define PINMUX_SPIM1_USEFPGA_SEL 0
#define PINMUX_SPIS0_USEFPGA_SEL 0
#define PINMUX_SPIS1_USEFPGA_SEL 0
#define PINMUX_UART0_USEFPGA_SEL 1
#define PINMUX_UART1_USEFPGA_SEL 0
#define PINMUX_USB0_USEFPGA_SEL 0
#define PINMUX_USB1_USEFPGA_SEL 0
/* Bridge Configuration */
#define F2H_AXI_SLAVE 1
#define F2SDRAM0_AXI_SLAVE 1
#define F2SDRAM1_AXI_SLAVE 1
#define F2SDRAM2_AXI_SLAVE 1
#define H2F_AXI_MASTER 1
#define LWH2F_AXI_MASTER 1
/* Voltage Select for Config IO */
#define CONFIG_IO_BANK_VSEL \
(((CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO & 0x3) << 8) | \
(CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO & 0x3))
/* Macro for Config IO bit mapping */
#define CONFIG_IO_MACRO(NAME) (((NAME ## _RTRIM & 0xff) << 19) | \
((NAME ## _INPUT_BUF_EN & 0x3) << 17) | \
((NAME ## _WK_PU_EN & 0x1) << 16) | \
((NAME ## _PU_SLW_RT & 0x1) << 13) | \
((NAME ## _PU_DRV_STRG & 0xf) << 8) | \
((NAME ## _PD_SLW_RT & 0x1) << 5) | \
(NAME ## _PD_DRV_STRG & 0x1f))
#endif /* __SOCFPGA_ARRIA10_CONFIG_H__ */

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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2022 Google LLC
*/
#include "socfpga_arria10_chameleonv3_480_2_handoff.h"
#include "socfpga_arria10-handoff.dtsi"
#include "socfpga_arria10_handoff_u-boot.dtsi"
#include "socfpga_arria10_mercury_aa1-u-boot.dtsi"

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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2022 Google LLC
*/
#include "socfpga_arria10_chameleonv3.dts"

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Intel Arria 10 SoCFPGA configuration
*/
#ifndef __SOCFPGA_ARRIA10_CONFIG_H__
#define __SOCFPGA_ARRIA10_CONFIG_H__
/* Clocks */
#define CB_INTOSC_LS_CLK_HZ 60000000
#define EMAC0_CLK_HZ 250000000
#define EMAC1_CLK_HZ 250000000
#define EMAC2_CLK_HZ 250000000
#define EOSC1_CLK_HZ 33330000
#define F2H_FREE_CLK_HZ 200000000
#define H2F_USER0_CLK_HZ 200000000
#define H2F_USER1_CLK_HZ 100000000
#define L3_MAIN_FREE_CLK_HZ 200000000
#define SDMMC_CLK_HZ 200000000
#define TPIU_CLK_HZ 100000000
#define MAINPLLGRP_CNTR15CLK_CNT 900
#define MAINPLLGRP_CNTR2CLK_CNT 900
#define MAINPLLGRP_CNTR3CLK_CNT 900
#define MAINPLLGRP_CNTR4CLK_CNT 900
#define MAINPLLGRP_CNTR5CLK_CNT 900
#define MAINPLLGRP_CNTR6CLK_CNT 9
#define MAINPLLGRP_CNTR7CLK_CNT 9
#define MAINPLLGRP_CNTR7CLK_SRC 0
#define MAINPLLGRP_CNTR8CLK_CNT 19
#define MAINPLLGRP_CNTR9CLK_CNT 900
#define MAINPLLGRP_CNTR9CLK_SRC 0
#define MAINPLLGRP_MPUCLK_CNT 0
#define MAINPLLGRP_MPUCLK_SRC 0
#define MAINPLLGRP_NOCCLK_CNT 0
#define MAINPLLGRP_NOCCLK_SRC 0
#define MAINPLLGRP_NOCDIV_CSATCLK 0
#define MAINPLLGRP_NOCDIV_CSPDBGCLK 1
#define MAINPLLGRP_NOCDIV_CSTRACECLK 0
#define MAINPLLGRP_NOCDIV_L4MAINCLK 0
#define MAINPLLGRP_NOCDIV_L4MPCLK 1
#define MAINPLLGRP_NOCDIV_L4SPCLK 2
#define MAINPLLGRP_VCO0_PSRC 0
#define MAINPLLGRP_VCO1_DENOM 32
#define MAINPLLGRP_VCO1_NUMER 1980
#define PERPLLGRP_CNTR2CLK_CNT 7
#define PERPLLGRP_CNTR2CLK_SRC 1
#define PERPLLGRP_CNTR3CLK_CNT 900
#define PERPLLGRP_CNTR3CLK_SRC 1
#define PERPLLGRP_CNTR4CLK_CNT 19
#define PERPLLGRP_CNTR4CLK_SRC 1
#define PERPLLGRP_CNTR5CLK_CNT 499
#define PERPLLGRP_CNTR5CLK_SRC 1
#define PERPLLGRP_CNTR6CLK_CNT 900
#define PERPLLGRP_CNTR6CLK_SRC 0
#define PERPLLGRP_CNTR7CLK_CNT 900
#define PERPLLGRP_CNTR8CLK_CNT 900
#define PERPLLGRP_CNTR8CLK_SRC 0
#define PERPLLGRP_CNTR9CLK_CNT 900
#define PERPLLGRP_EMACCTL_EMAC0SEL 0
#define PERPLLGRP_EMACCTL_EMAC1SEL 0
#define PERPLLGRP_EMACCTL_EMAC2SEL 0
#define PERPLLGRP_GPIODIV_GPIODBCLK 32000
#define PERPLLGRP_VCO0_PSRC 0
#define PERPLLGRP_VCO1_DENOM 32
#define PERPLLGRP_VCO1_NUMER 1980
#define CLKMGR_TESTIOCTRL_DEBUGCLKSEL 16
#define CLKMGR_TESTIOCTRL_MAINCLKSEL 8
#define CLKMGR_TESTIOCTRL_PERICLKSEL 8
#define ALTERAGRP_MPUCLK_MAINCNT 1
#define ALTERAGRP_MPUCLK_PERICNT 900
#define ALTERAGRP_NOCCLK_MAINCNT 9
#define ALTERAGRP_NOCCLK_PERICNT 900
#define ALTERAGRP_MPUCLK ((ALTERAGRP_MPUCLK_PERICNT << 16) | \
(ALTERAGRP_MPUCLK_MAINCNT))
#define ALTERAGRP_NOCCLK ((ALTERAGRP_NOCCLK_PERICNT << 16) | \
(ALTERAGRP_NOCCLK_MAINCNT))
/* Pin Mux Configuration */
#define CONFIG_IO_10_INPUT_BUF_EN 1
#define CONFIG_IO_10_PD_DRV_STRG 10
#define CONFIG_IO_10_PD_SLW_RT 1
#define CONFIG_IO_10_PU_DRV_STRG 8
#define CONFIG_IO_10_PU_SLW_RT 1
#define CONFIG_IO_10_RTRIM 1
#define CONFIG_IO_10_WK_PU_EN 0
#define CONFIG_IO_11_INPUT_BUF_EN 1
#define CONFIG_IO_11_PD_DRV_STRG 10
#define CONFIG_IO_11_PD_SLW_RT 1
#define CONFIG_IO_11_PU_DRV_STRG 8
#define CONFIG_IO_11_PU_SLW_RT 1
#define CONFIG_IO_11_RTRIM 1
#define CONFIG_IO_11_WK_PU_EN 0
#define CONFIG_IO_12_INPUT_BUF_EN 0
#define CONFIG_IO_12_PD_DRV_STRG 0
#define CONFIG_IO_12_PD_SLW_RT 0
#define CONFIG_IO_12_PU_DRV_STRG 0
#define CONFIG_IO_12_PU_SLW_RT 0
#define CONFIG_IO_12_RTRIM 1
#define CONFIG_IO_12_WK_PU_EN 1
#define CONFIG_IO_13_INPUT_BUF_EN 0
#define CONFIG_IO_13_PD_DRV_STRG 0
#define CONFIG_IO_13_PD_SLW_RT 0
#define CONFIG_IO_13_PU_DRV_STRG 0
#define CONFIG_IO_13_PU_SLW_RT 0
#define CONFIG_IO_13_RTRIM 1
#define CONFIG_IO_13_WK_PU_EN 1
#define CONFIG_IO_14_INPUT_BUF_EN 0
#define CONFIG_IO_14_PD_DRV_STRG 0
#define CONFIG_IO_14_PD_SLW_RT 0
#define CONFIG_IO_14_PU_DRV_STRG 0
#define CONFIG_IO_14_PU_SLW_RT 0
#define CONFIG_IO_14_RTRIM 1
#define CONFIG_IO_14_WK_PU_EN 1
#define CONFIG_IO_15_INPUT_BUF_EN 0
#define CONFIG_IO_15_PD_DRV_STRG 0
#define CONFIG_IO_15_PD_SLW_RT 0
#define CONFIG_IO_15_PU_DRV_STRG 0
#define CONFIG_IO_15_PU_SLW_RT 0
#define CONFIG_IO_15_RTRIM 1
#define CONFIG_IO_15_WK_PU_EN 1
#define CONFIG_IO_16_INPUT_BUF_EN 0
#define CONFIG_IO_16_PD_DRV_STRG 10
#define CONFIG_IO_16_PD_SLW_RT 1
#define CONFIG_IO_16_PU_DRV_STRG 8
#define CONFIG_IO_16_PU_SLW_RT 1
#define CONFIG_IO_16_RTRIM 1
#define CONFIG_IO_16_WK_PU_EN 0
#define CONFIG_IO_17_INPUT_BUF_EN 1
#define CONFIG_IO_17_PD_DRV_STRG 10
#define CONFIG_IO_17_PD_SLW_RT 1
#define CONFIG_IO_17_PU_DRV_STRG 8
#define CONFIG_IO_17_PU_SLW_RT 1
#define CONFIG_IO_17_RTRIM 1
#define CONFIG_IO_17_WK_PU_EN 0
#define CONFIG_IO_1_INPUT_BUF_EN 1
#define CONFIG_IO_1_PD_DRV_STRG 10
#define CONFIG_IO_1_PD_SLW_RT 0
#define CONFIG_IO_1_PU_DRV_STRG 8
#define CONFIG_IO_1_PU_SLW_RT 0
#define CONFIG_IO_1_RTRIM 1
#define CONFIG_IO_1_WK_PU_EN 1
#define CONFIG_IO_2_INPUT_BUF_EN 1
#define CONFIG_IO_2_PD_DRV_STRG 10
#define CONFIG_IO_2_PD_SLW_RT 0
#define CONFIG_IO_2_PU_DRV_STRG 8
#define CONFIG_IO_2_PU_SLW_RT 0
#define CONFIG_IO_2_RTRIM 1
#define CONFIG_IO_2_WK_PU_EN 1
#define CONFIG_IO_3_INPUT_BUF_EN 1
#define CONFIG_IO_3_PD_DRV_STRG 10
#define CONFIG_IO_3_PD_SLW_RT 0
#define CONFIG_IO_3_PU_DRV_STRG 8
#define CONFIG_IO_3_PU_SLW_RT 0
#define CONFIG_IO_3_RTRIM 1
#define CONFIG_IO_3_WK_PU_EN 1
#define CONFIG_IO_4_INPUT_BUF_EN 1
#define CONFIG_IO_4_PD_DRV_STRG 10
#define CONFIG_IO_4_PD_SLW_RT 1
#define CONFIG_IO_4_PU_DRV_STRG 8
#define CONFIG_IO_4_PU_SLW_RT 1
#define CONFIG_IO_4_RTRIM 1
#define CONFIG_IO_4_WK_PU_EN 0
#define CONFIG_IO_5_INPUT_BUF_EN 1
#define CONFIG_IO_5_PD_DRV_STRG 10
#define CONFIG_IO_5_PD_SLW_RT 1
#define CONFIG_IO_5_PU_DRV_STRG 8
#define CONFIG_IO_5_PU_SLW_RT 1
#define CONFIG_IO_5_RTRIM 1
#define CONFIG_IO_5_WK_PU_EN 0
#define CONFIG_IO_6_INPUT_BUF_EN 0
#define CONFIG_IO_6_PD_DRV_STRG 10
#define CONFIG_IO_6_PD_SLW_RT 1
#define CONFIG_IO_6_PU_DRV_STRG 8
#define CONFIG_IO_6_PU_SLW_RT 1
#define CONFIG_IO_6_RTRIM 1
#define CONFIG_IO_6_WK_PU_EN 0
#define CONFIG_IO_7_INPUT_BUF_EN 1
#define CONFIG_IO_7_PD_DRV_STRG 10
#define CONFIG_IO_7_PD_SLW_RT 1
#define CONFIG_IO_7_PU_DRV_STRG 8
#define CONFIG_IO_7_PU_SLW_RT 1
#define CONFIG_IO_7_RTRIM 1
#define CONFIG_IO_7_WK_PU_EN 0
#define CONFIG_IO_8_INPUT_BUF_EN 1
#define CONFIG_IO_8_PD_DRV_STRG 10
#define CONFIG_IO_8_PD_SLW_RT 1
#define CONFIG_IO_8_PU_DRV_STRG 8
#define CONFIG_IO_8_PU_SLW_RT 1
#define CONFIG_IO_8_RTRIM 1
#define CONFIG_IO_8_WK_PU_EN 0
#define CONFIG_IO_9_INPUT_BUF_EN 1
#define CONFIG_IO_9_PD_DRV_STRG 10
#define CONFIG_IO_9_PD_SLW_RT 1
#define CONFIG_IO_9_PU_DRV_STRG 8
#define CONFIG_IO_9_PU_SLW_RT 1
#define CONFIG_IO_9_RTRIM 1
#define CONFIG_IO_9_WK_PU_EN 0
#define CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO 1
#define CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO 1
#define PINMUX_DEDICATED_IO_10_SEL 15
#define PINMUX_DEDICATED_IO_11_SEL 15
#define PINMUX_DEDICATED_IO_12_SEL 1
#define PINMUX_DEDICATED_IO_13_SEL 1
#define PINMUX_DEDICATED_IO_14_SEL 10
#define PINMUX_DEDICATED_IO_15_SEL 10
#define PINMUX_DEDICATED_IO_16_SEL 13
#define PINMUX_DEDICATED_IO_17_SEL 13
#define PINMUX_DEDICATED_IO_4_SEL 8
#define PINMUX_DEDICATED_IO_5_SEL 8
#define PINMUX_DEDICATED_IO_6_SEL 8
#define PINMUX_DEDICATED_IO_7_SEL 8
#define PINMUX_DEDICATED_IO_8_SEL 8
#define PINMUX_DEDICATED_IO_9_SEL 8
#define PINMUX_I2C0_USEFPGA_SEL 1
#define PINMUX_I2C1_USEFPGA_SEL 0
#define PINMUX_I2CEMAC0_USEFPGA_SEL 0
#define PINMUX_I2CEMAC1_USEFPGA_SEL 0
#define PINMUX_I2CEMAC2_USEFPGA_SEL 0
#define PINMUX_NAND_USEFPGA_SEL 0
#define PINMUX_PLL_CLOCK_OUT_USEFPGA_SEL 0
#define PINMUX_QSPI_USEFPGA_SEL 0
#define PINMUX_RGMII0_USEFPGA_SEL 0
#define PINMUX_RGMII1_USEFPGA_SEL 0
#define PINMUX_RGMII2_USEFPGA_SEL 0
#define PINMUX_SDMMC_USEFPGA_SEL 0
#define PINMUX_SHARED_IO_Q1_10_SEL 8
#define PINMUX_SHARED_IO_Q1_11_SEL 8
#define PINMUX_SHARED_IO_Q1_12_SEL 8
#define PINMUX_SHARED_IO_Q1_1_SEL 8
#define PINMUX_SHARED_IO_Q1_2_SEL 8
#define PINMUX_SHARED_IO_Q1_3_SEL 8
#define PINMUX_SHARED_IO_Q1_4_SEL 8
#define PINMUX_SHARED_IO_Q1_5_SEL 8
#define PINMUX_SHARED_IO_Q1_6_SEL 8
#define PINMUX_SHARED_IO_Q1_7_SEL 8
#define PINMUX_SHARED_IO_Q1_8_SEL 8
#define PINMUX_SHARED_IO_Q1_9_SEL 8
#define PINMUX_SHARED_IO_Q2_10_SEL 4
#define PINMUX_SHARED_IO_Q2_11_SEL 4
#define PINMUX_SHARED_IO_Q2_12_SEL 4
#define PINMUX_SHARED_IO_Q2_1_SEL 4
#define PINMUX_SHARED_IO_Q2_2_SEL 4
#define PINMUX_SHARED_IO_Q2_3_SEL 4
#define PINMUX_SHARED_IO_Q2_4_SEL 4
#define PINMUX_SHARED_IO_Q2_5_SEL 4
#define PINMUX_SHARED_IO_Q2_6_SEL 4
#define PINMUX_SHARED_IO_Q2_7_SEL 4
#define PINMUX_SHARED_IO_Q2_8_SEL 4
#define PINMUX_SHARED_IO_Q2_9_SEL 4
#define PINMUX_SHARED_IO_Q3_10_SEL 15
#define PINMUX_SHARED_IO_Q3_11_SEL 1
#define PINMUX_SHARED_IO_Q3_12_SEL 1
#define PINMUX_SHARED_IO_Q3_1_SEL 15
#define PINMUX_SHARED_IO_Q3_2_SEL 15
#define PINMUX_SHARED_IO_Q3_3_SEL 15
#define PINMUX_SHARED_IO_Q3_4_SEL 15
#define PINMUX_SHARED_IO_Q3_5_SEL 15
#define PINMUX_SHARED_IO_Q3_6_SEL 15
#define PINMUX_SHARED_IO_Q3_7_SEL 0
#define PINMUX_SHARED_IO_Q3_8_SEL 0
#define PINMUX_SHARED_IO_Q3_9_SEL 15
#define PINMUX_SHARED_IO_Q4_10_SEL 10
#define PINMUX_SHARED_IO_Q4_11_SEL 10
#define PINMUX_SHARED_IO_Q4_12_SEL 10
#define PINMUX_SHARED_IO_Q4_1_SEL 10
#define PINMUX_SHARED_IO_Q4_2_SEL 10
#define PINMUX_SHARED_IO_Q4_3_SEL 10
#define PINMUX_SHARED_IO_Q4_4_SEL 10
#define PINMUX_SHARED_IO_Q4_5_SEL 10
#define PINMUX_SHARED_IO_Q4_6_SEL 10
#define PINMUX_SHARED_IO_Q4_7_SEL 10
#define PINMUX_SHARED_IO_Q4_8_SEL 10
#define PINMUX_SHARED_IO_Q4_9_SEL 10
#define PINMUX_SPIM0_USEFPGA_SEL 0
#define PINMUX_SPIM1_USEFPGA_SEL 0
#define PINMUX_SPIS0_USEFPGA_SEL 0
#define PINMUX_SPIS1_USEFPGA_SEL 0
#define PINMUX_UART0_USEFPGA_SEL 1
#define PINMUX_UART1_USEFPGA_SEL 0
#define PINMUX_USB0_USEFPGA_SEL 0
#define PINMUX_USB1_USEFPGA_SEL 0
/* Bridge Configuration */
#define F2H_AXI_SLAVE 1
#define F2SDRAM0_AXI_SLAVE 1
#define F2SDRAM1_AXI_SLAVE 1
#define F2SDRAM2_AXI_SLAVE 1
#define H2F_AXI_MASTER 1
#define LWH2F_AXI_MASTER 1
/* Voltage Select for Config IO */
#define CONFIG_IO_BANK_VSEL \
(((CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO & 0x3) << 8) | \
(CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO & 0x3))
/* Macro for Config IO bit mapping */
#define CONFIG_IO_MACRO(NAME) (((NAME ## _RTRIM & 0xff) << 19) | \
((NAME ## _INPUT_BUF_EN & 0x3) << 17) | \
((NAME ## _WK_PU_EN & 0x1) << 16) | \
((NAME ## _PU_SLW_RT & 0x1) << 13) | \
((NAME ## _PU_DRV_STRG & 0xf) << 8) | \
((NAME ## _PD_SLW_RT & 0x1) << 5) | \
(NAME ## _PD_DRV_STRG & 0x1f))
#endif /* __SOCFPGA_ARRIA10_CONFIG_H__ */

View File

@@ -0,0 +1,54 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2022 Google LLC
*/
#include "socfpga_arria10-u-boot.dtsi"
/ {
chosen {
firmware-loader = <&fs_loader0>;
};
fs_loader0: fs-loader {
u-boot,dm-pre-reloc;
compatible = "u-boot,fs-loader";
phandlepart = <&mmc 1>;
};
};
&atsha204a {
u-boot,dm-pre-reloc;
};
&fpga_mgr {
u-boot,dm-pre-reloc;
altr,bitstream = "fpga.itb";
};
&i2c1 {
u-boot,dm-pre-reloc;
};
&main_sdmmc_clk {
u-boot,dm-pre-reloc;
};
&mmc {
u-boot,dm-pre-reloc;
};
&peri_sdmmc_clk {
u-boot,dm-pre-reloc;
};
&sdmmc_clk {
u-boot,dm-pre-reloc;
};
&sdmmc_free_clk {
u-boot,dm-pre-reloc;
};
&uart1 {
u-boot,dm-pre-reloc;
};

View File

@@ -0,0 +1,72 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2022 Google LLC
*/
#include "socfpga_arria10.dtsi"
/ {
aliases {
ethernet0 = &gmac0;
serial1 = &uart1;
};
chosen {
stdout-path = "serial1:115200n8";
};
memory@0 {
name = "memory";
device_type = "memory";
reg = <0x0 0x80000000>; /* 2GB */
};
};
&gmac0 {
phy-mode = "rgmii";
phy-handle = <&phy3>;
max-frame-size = <3800>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy3: ethernet-phy@3 {
reg = <3>;
txd0-skew-ps = <0>; /* -420ps */
txd1-skew-ps = <0>; /* -420ps */
txd2-skew-ps = <0>; /* -420ps */
txd3-skew-ps = <0>; /* -420ps */
rxd0-skew-ps = <420>; /* 0ps */
rxd1-skew-ps = <420>; /* 0ps */
rxd2-skew-ps = <420>; /* 0ps */
rxd3-skew-ps = <420>; /* 0ps */
txen-skew-ps = <0>; /* -420ps */
txc-skew-ps = <1860>; /* 960ps */
rxdv-skew-ps = <420>; /* 0ps */
rxc-skew-ps = <1680>; /* 780ps */
};
};
};
&i2c1 {
atsha204a: atsha204a@64 {
compatible = "atmel,atsha204a";
reg = <0x64>;
};
isl12022: isl12022@6f {
compatible = "isil,isl12022";
reg = <0x6f>;
};
};
&mmc {
cap-sd-highspeed;
broken-cd;
bus-width = <4>;
};
&osc1 {
clock-frequency = <33330000>;
};

View File

@@ -0,0 +1,86 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2017, Intel Corporation
*
* Adapted from socfpga_cyclone5_de10_nano.dts
*/
#include "socfpga_cyclone5.dtsi"
#include "socfpga-common-u-boot.dtsi"
/ {
model = "Terasic DE10-Standard";
compatible = "altr,socfpga-cyclone5", "altr,socfpga";
chosen {
bootargs = "console=ttyS0,115200";
stdout-path = "serial0:115200n8";
};
aliases {
ethernet0 = &gmac1;
udc0 = &usb1;
};
memory {
name = "memory";
device_type = "memory";
reg = <0x0 0x40000000>; /* 1GB */
};
};
&gmac1 {
status = "okay";
phy-mode = "rgmii";
rxd0-skew-ps = <420>;
rxd1-skew-ps = <420>;
rxd2-skew-ps = <420>;
rxd3-skew-ps = <420>;
txen-skew-ps = <0>;
txc-skew-ps = <1860>;
rxdv-skew-ps = <420>;
rxc-skew-ps = <1680>;
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&gpio2 {
status = "okay";
};
&porta {
bank-name = "porta";
};
&portb {
bank-name = "portb";
};
&portc {
bank-name = "portc";
};
&mmc0 {
status = "okay";
u-boot,dm-pre-reloc;
};
&usb1 {
status = "okay";
};
&uart0 {
clock-frequency = <100000000>;
u-boot,dm-pre-reloc;
};
&watchdog0 {
status = "disabled";
};

View File

@@ -2,7 +2,7 @@
/*
* U-Boot additions
*
* Copyright (C) 2019-2020 Intel Corporation <www.intel.com>
* Copyright (C) 2019-2022 Intel Corporation <www.intel.com>
*/
#include "socfpga_stratix10-u-boot.dtsi"
@@ -10,6 +10,15 @@
/{
aliases {
spi0 = &qspi;
freeze_br0 = &freeze_controller;
};
soc {
freeze_controller: freeze_controller@f9000450 {
compatible = "altr,freeze-bridge-controller";
reg = <0xf9000450 0x00000010>;
status = "disabled";
};
};
};

View File

@@ -92,7 +92,7 @@
broken-cd;
bus-width = <4>;
drvsel = <3>;
smplsel = <0>;
smplsel = <2>;
};
&qspi {

View File

@@ -338,6 +338,47 @@
};
};
ethernet0_rmii_pins_b: rmii-1 {
pins1 {
pinmux = <STM32_PINMUX('B', 5, AF0)>, /* ETH1_CLK */
<STM32_PINMUX('C', 1, AF11)>, /* ETH1_MDC */
<STM32_PINMUX('G', 13, AF11)>, /* ETH1_TXD0 */
<STM32_PINMUX('G', 14, AF11)>; /* ETH1_TXD1 */
bias-disable;
drive-push-pull;
slew-rate = <1>;
};
pins2 {
pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH1_MDIO */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins3 {
pinmux = <STM32_PINMUX('A', 7, AF11)>, /* ETH1_CRS_DV */
<STM32_PINMUX('C', 4, AF11)>, /* ETH1_RXD0 */
<STM32_PINMUX('C', 5, AF11)>; /* ETH1_RXD1 */
bias-disable;
};
pins4 {
pinmux = <STM32_PINMUX('B', 11, AF11)>; /* ETH1_TX_EN */
};
};
ethernet0_rmii_sleep_pins_b: rmii-sleep-1 {
pins1 {
pinmux = <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */
<STM32_PINMUX('A', 7, ANALOG)>, /* ETH1_CRS_DV */
<STM32_PINMUX('B', 5, ANALOG)>, /* ETH1_CLK */
<STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_TX_EN */
<STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */
<STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RXD0 */
<STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RXD1 */
<STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_TXD0 */
<STM32_PINMUX('G', 14, ANALOG)>; /* ETH1_TXD1 */
};
};
fmc_pins_a: fmc-0 {
pins1 {
pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
@@ -888,6 +929,26 @@
};
};
m_can1_pins_c: m-can1-2 {
pins1 {
pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
slew-rate = <1>;
drive-push-pull;
bias-disable;
};
pins2 {
pinmux = <STM32_PINMUX('H', 14, AF9)>; /* CAN1_RX */
bias-disable;
};
};
m_can1_sleep_pins_c: m_can1-sleep-2 {
pins {
pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */
<STM32_PINMUX('H', 14, ANALOG)>; /* CAN1_RX */
};
};
m_can2_pins_a: m-can2-0 {
pins1 {
pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */
@@ -927,6 +988,21 @@
};
};
pwm1_pins_b: pwm1-1 {
pins {
pinmux = <STM32_PINMUX('E', 9, AF1)>; /* TIM1_CH1 */
bias-pull-down;
drive-push-pull;
slew-rate = <0>;
};
};
pwm1_sleep_pins_b: pwm1-sleep-1 {
pins {
pinmux = <STM32_PINMUX('E', 9, ANALOG)>; /* TIM1_CH1 */
};
};
pwm2_pins_a: pwm2-0 {
pins {
pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */
@@ -1702,6 +1778,21 @@
};
};
spi2_pins_b: spi2-1 {
pins1 {
pinmux = <STM32_PINMUX('I', 1, AF5)>, /* SPI1_SCK */
<STM32_PINMUX('I', 3, AF5)>; /* SPI1_MOSI */
bias-disable;
drive-push-pull;
slew-rate = <1>;
};
pins2 {
pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI1_MISO */
bias-disable;
};
};
spi4_pins_a: spi4-0 {
pins {
pinmux = <STM32_PINMUX('E', 12, AF5)>, /* SPI4_SCK */
@@ -1779,6 +1870,49 @@
};
};
uart4_pins_d: uart4-3 {
pins1 {
pinmux = <STM32_PINMUX('A', 13, AF8)>; /* UART4_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
bias-disable;
};
};
uart4_idle_pins_d: uart4-idle-3 {
pins1 {
pinmux = <STM32_PINMUX('A', 13, ANALOG)>; /* UART4_TX */
};
pins2 {
pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
bias-disable;
};
};
uart4_sleep_pins_d: uart4-sleep-3 {
pins {
pinmux = <STM32_PINMUX('A', 13, ANALOG)>, /* UART4_TX */
<STM32_PINMUX('B', 2, ANALOG)>; /* UART4_RX */
};
};
uart5_pins_a: uart5-0 {
pins1 {
pinmux = <STM32_PINMUX('B', 13, AF14)>; /* UART5_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('B', 5, AF12)>; /* UART5_RX */
bias-disable;
};
};
uart7_pins_a: uart7-0 {
pins1 {
pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */
@@ -2042,6 +2176,83 @@
};
};
usart3_pins_d: usart3-3 {
pins1 {
pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
<STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('D', 9, AF7)>, /* USART3_RX */
<STM32_PINMUX('D', 11, AF7)>; /* USART3_CTS_NSS */
bias-disable;
};
};
usart3_idle_pins_d: usart3-idle-3 {
pins1 {
pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
<STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
<STM32_PINMUX('D', 11, ANALOG)>; /* USART3_CTS_NSS */
};
pins2 {
pinmux = <STM32_PINMUX('D', 9, AF7)>; /* USART3_RX */
bias-disable;
};
};
usart3_sleep_pins_d: usart3-sleep-3 {
pins {
pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
<STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
<STM32_PINMUX('D', 11, ANALOG)>, /* USART3_CTS_NSS */
<STM32_PINMUX('D', 9, ANALOG)>; /* USART3_RX */
};
};
usart3_pins_e: usart3-4 {
pins1 {
pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
<STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('B', 11, AF7)>, /* USART3_RX */
<STM32_PINMUX('D', 11, AF7)>; /* USART3_CTS_NSS */
bias-pull-up;
};
};
usart3_idle_pins_e: usart3-idle-4 {
pins1 {
pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
<STM32_PINMUX('D', 11, ANALOG)>; /* USART3_CTS_NSS */
};
pins2 {
pinmux = <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins3 {
pinmux = <STM32_PINMUX('B', 11, AF7)>; /* USART3_RX */
bias-pull-up;
};
};
usart3_sleep_pins_e: usart3-sleep-4 {
pins {
pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
<STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
<STM32_PINMUX('D', 11, ANALOG)>, /* USART3_CTS_NSS */
<STM32_PINMUX('B', 11, ANALOG)>; /* USART3_RX */
};
};
usbotg_hs_pins_a: usbotg-hs-0 {
pins {
pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */

View File

@@ -188,18 +188,6 @@
#size-cells = <0>;
};
&sdmmc1 {
compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
};
&sdmmc2 {
compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
};
&sdmmc3 {
compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
};
&usart1 {
resets = <&rcc USART1_R>;
};

View File

@@ -63,10 +63,10 @@
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-parent = <&intc>;
};
@@ -473,6 +473,9 @@
interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc USART2_K>;
wakeup-source;
dmas = <&dmamux1 43 0x400 0x15>,
<&dmamux1 44 0x400 0x11>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -482,6 +485,9 @@
interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc USART3_K>;
wakeup-source;
dmas = <&dmamux1 45 0x400 0x15>,
<&dmamux1 46 0x400 0x11>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -491,6 +497,9 @@
interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc UART4_K>;
wakeup-source;
dmas = <&dmamux1 63 0x400 0x15>,
<&dmamux1 64 0x400 0x11>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -500,6 +509,9 @@
interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc UART5_K>;
wakeup-source;
dmas = <&dmamux1 65 0x400 0x15>,
<&dmamux1 66 0x400 0x11>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -606,6 +618,9 @@
interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc UART7_K>;
wakeup-source;
dmas = <&dmamux1 79 0x400 0x15>,
<&dmamux1 80 0x400 0x11>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -615,6 +630,9 @@
interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc UART8_K>;
wakeup-source;
dmas = <&dmamux1 81 0x400 0x15>,
<&dmamux1 82 0x400 0x11>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -696,6 +714,9 @@
interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc USART6_K>;
wakeup-source;
dmas = <&dmamux1 71 0x400 0x15>,
<&dmamux1 72 0x400 0x11>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -1077,7 +1098,7 @@
};
sdmmc3: mmc@48004000 {
compatible = "arm,pl18x", "arm,primecell";
compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00253180>;
reg = <0x48004000 0x400>;
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
@@ -1411,7 +1432,7 @@
};
sdmmc1: mmc@58005000 {
compatible = "arm,pl18x", "arm,primecell";
compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00253180>;
reg = <0x58005000 0x1000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
@@ -1426,7 +1447,7 @@
};
sdmmc2: mmc@58007000 {
compatible = "arm,pl18x", "arm,primecell";
compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00253180>;
reg = <0x58007000 0x1000>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
@@ -1590,7 +1611,7 @@
reg = <0x5c004000 0x400>;
clocks = <&rcc RTCAPB>, <&rcc RTC>;
clock-names = "pclk", "rtc_ck";
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};

View File

@@ -22,6 +22,13 @@
interrupt-affinity = <&cpu0>, <&cpu1>;
};
timer {
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
};
soc {
m_can1: can@4400e000 {
compatible = "bosch,m_can";

View File

@@ -0,0 +1,30 @@
// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
/*
* Copyright (C) 2022 Marek Vasut <marex@denx.de>
*
* DHCOR STM32MP1 variant:
* DHCR-STM32MP153C-C065-R051-V33-SPI-I-01LG
* DHCOR PCB number: 586-100 or newer
* DRC Compact PCB number: 627-100 or newer
*/
/dts-v1/;
#include "stm32mp153.dtsi"
#include "stm32mp15xc.dtsi"
#include "stm32mp15xx-dhcor-som.dtsi"
#include "stm32mp15xx-dhcor-drc-compact.dtsi"
/ {
model = "DH electronics STM32MP153C DHCOR DRC Compact";
compatible = "dh,stm32mp153c-dhcor-drc-compact",
"dh,stm32mp153c-dhcor-som",
"st,stm32mp153";
};
&m_can1 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&m_can1_pins_c>;
pinctrl-1 = <&m_can1_sleep_pins_c>;
status = "okay";
};

View File

@@ -43,5 +43,7 @@
pinctrl-0 = <&uart4_pins_a>;
pinctrl-1 = <&uart4_sleep_pins_a>;
pinctrl-2 = <&uart4_idle_pins_a>;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};

View File

@@ -43,5 +43,7 @@
pinctrl-0 = <&uart4_pins_a>;
pinctrl-1 = <&uart4_sleep_pins_a>;
pinctrl-2 = <&uart4_idle_pins_a>;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};

View File

@@ -143,6 +143,8 @@
pinctrl-0 = <&uart4_pins_a>;
pinctrl-1 = <&uart4_sleep_pins_a>;
pinctrl-2 = <&uart4_idle_pins_a>;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};
@@ -150,5 +152,7 @@
&uart8 {
pinctrl-names = "default";
pinctrl-0 = <&uart8_pins_a>;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};

View File

@@ -44,6 +44,8 @@
pinctrl-0 = <&uart4_pins_a>;
pinctrl-1 = <&uart4_sleep_pins_a>;
pinctrl-2 = <&uart4_idle_pins_a>;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};
@@ -51,5 +53,7 @@
&uart8 {
pinctrl-names = "default";
pinctrl-0 = <&uart8_pins_a>;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};

View File

@@ -392,6 +392,8 @@
pinctrl-0 = <&uart4_pins_a>;
pinctrl-1 = <&uart4_sleep_pins_a>;
pinctrl-2 = <&uart4_idle_pins_a>;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};

View File

@@ -132,6 +132,8 @@
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&uart4_pins_a>;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};

View File

@@ -131,6 +131,8 @@
&usart3 {
pinctrl-names = "default";
pinctrl-0 = <&usart3_pins_a>;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};
@@ -144,6 +146,8 @@
pinctrl-names = "default";
pinctrl-0 = <&uart8_pins_a>;
rts-gpios = <&gpioe 6 GPIO_ACTIVE_HIGH>;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};

View File

@@ -287,6 +287,8 @@
&usart3 {
pinctrl-names = "default";
pinctrl-0 = <&usart3_pins_a>;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};
@@ -294,6 +296,8 @@
pinctrl-names = "default";
pinctrl-0 = <&uart8_pins_a &uart8_rtscts_pins_a>;
uart-has-rtscts;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};

View File

@@ -105,12 +105,16 @@
&usart3 {
pinctrl-names = "default";
pinctrl-0 = <&usart3_pins_a>;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};
&uart8 {
pinctrl-names = "default";
pinctrl-0 = <&uart8_pins_a &uart8_rtscts_pins_a>;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};

View File

@@ -196,7 +196,6 @@
"", "", "DHCOM-E", "",
"", "", "", "",
"", "", "", "";
status = "okay";
};
&gpiod {
@@ -521,5 +520,7 @@
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&uart4_pins_a>;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};

View File

@@ -376,6 +376,8 @@
label = "LS-UART1";
pinctrl-names = "default";
pinctrl-0 = <&uart4_pins_b>;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};
@@ -385,6 +387,8 @@
pinctrl-names = "default";
pinctrl-0 = <&uart7_pins_a>;
uart-has-rtscts;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};
@@ -394,6 +398,8 @@
pinctrl-0 = <&usart2_pins_a>;
pinctrl-1 = <&usart2_sleep_pins_a>;
st,hw-flow-ctrl;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
bluetooth {

View File

@@ -0,0 +1,120 @@
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* Copyright (C) 2022 Marek Vasut <marex@denx.de>
*/
#include "stm32mp15xx-dhcor-u-boot.dtsi"
/delete-node/ &ksz8851;
/ {
aliases {
mmc0 = &sdmmc1;
mmc1 = &sdmmc2;
usb0 = &usbotg_hs;
ethernet1 = &ks8851;
};
config {
dh,board-coding-gpios = <&gpioh 9 0>, <&gpioh 8 0>, <&gpioh 3 0>;
};
/* This is actually on FMC2, but we do not have bus driver for that */
ks8851: ks8851mll@64000000 {
compatible = "micrel,ks8851-mll";
reg = <0x64000000 0x20000>;
};
};
&ethernet0 {
phy-reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>;
mdio0 {
ethernet-phy@7 {
reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>;
reset-assert-us = <11000>;
reset-deassert-us = <1000>;
};
};
};
&pinctrl {
/* These should bound to FMC2 bus driver, but we do not have one */
pinctrl-0 = <&fmc_pins_b>;
pinctrl-1 = <&fmc_sleep_pins_b>;
pinctrl-names = "default", "sleep";
};
&sdmmc1 {
u-boot,dm-spl;
st,use-ckin;
st,cmd-gpios = <&gpiod 2 0>;
st,ck-gpios = <&gpioc 12 0>;
st,ckin-gpios = <&gpioe 4 0>;
};
&sdmmc1_b4_pins_a {
u-boot,dm-spl;
pins1 {
u-boot,dm-spl;
};
pins2 {
u-boot,dm-spl;
};
};
&sdmmc1_dir_pins_b {
u-boot,dm-spl;
pins1 {
u-boot,dm-spl;
};
pins2 {
u-boot,dm-spl;
};
};
&sdmmc2 {
u-boot,dm-spl;
};
&sdmmc2_b4_pins_a {
u-boot,dm-spl;
pins1 {
u-boot,dm-spl;
};
pins2 {
u-boot,dm-spl;
};
};
&sdmmc2_d47_pins_c {
u-boot,dm-spl;
pins {
u-boot,dm-spl;
};
};
&sdmmc3 { /* SDIO Wi-Fi */
status = "disabled";
};
&uart4 {
u-boot,dm-pre-reloc;
};
&uart4_pins_d {
u-boot,dm-pre-reloc;
pins1 {
u-boot,dm-pre-reloc;
};
pins2 {
u-boot,dm-pre-reloc;
/delete-property/ bias-disable;
bias-pull-up;
};
};
&usbotg_hs {
u-boot,force-b-session-valid;
hnp-srp-disable;
};

View File

@@ -0,0 +1,16 @@
// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
/*
* Copyright (C) 2022 Marek Vasut <marex@denx.de>
*/
/dts-v1/;
#include "stm32mp151.dtsi"
#include "stm32mp15xc.dtsi"
#include "stm32mp15xx-dhcor-som.dtsi"
#include "stm32mp15xx-dhcor-drc-compact.dtsi"
/ {
model = "DH electronics STM32MP15xx DHCOR DRC Compact";
compatible = "dh,stm32mp15xx-dhcor-drc-compact", "st,stm32mp1xx";
};

View File

@@ -0,0 +1,326 @@
// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
/*
* Copyright (C) 2022 Marek Vasut <marex@denx.de>
*/
/ {
aliases {
ethernet0 = &ethernet0;
ethernet1 = &ksz8851;
mmc0 = &sdmmc1;
rtc0 = &hwrtc;
rtc1 = &rtc;
serial0 = &uart4;
serial1 = &uart8;
serial2 = &usart3;
serial3 = &uart5;
spi0 = &qspi;
};
chosen {
stdout-path = "serial0:115200n8";
};
led {
compatible = "gpio-leds";
led1 {
label = "yellow:user0";
gpios = <&gpioz 6 GPIO_ACTIVE_LOW>;
default-state = "off";
};
led2 {
label = "red:user1";
gpios = <&gpioz 3 GPIO_ACTIVE_LOW>;
default-state = "off";
};
};
ethernet_vio: vioregulator {
compatible = "regulator-fixed";
regulator-name = "vio";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpioh 2 GPIO_ACTIVE_LOW>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vdd>;
};
};
&adc { /* X11 ADC inputs */
pinctrl-names = "default";
pinctrl-0 = <&adc12_ain_pins_b>;
vdd-supply = <&vdd>;
vdda-supply = <&vdda>;
vref-supply = <&vdda>;
status = "okay";
adc1: adc@0 {
st,adc-channels = <0 1 6>;
st,min-sample-time-nsecs = <5000>;
status = "okay";
};
adc2: adc@100 {
st,adc-channels = <0 1 2>;
st,min-sample-time-nsecs = <5000>;
status = "okay";
};
};
&ethernet0 {
status = "okay";
pinctrl-0 = <&ethernet0_rgmii_pins_c>;
pinctrl-1 = <&ethernet0_rgmii_sleep_pins_c>;
pinctrl-names = "default", "sleep";
phy-mode = "rgmii";
max-speed = <1000>;
phy-handle = <&phy0>;
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>;
reset-delay-us = <1000>;
reset-post-delay-us = <1000>;
phy0: ethernet-phy@7 {
reg = <7>;
rxc-skew-ps = <1500>;
rxdv-skew-ps = <540>;
rxd0-skew-ps = <420>;
rxd1-skew-ps = <420>;
rxd2-skew-ps = <420>;
rxd3-skew-ps = <420>;
txc-skew-ps = <1440>;
txen-skew-ps = <540>;
txd0-skew-ps = <420>;
txd1-skew-ps = <420>;
txd2-skew-ps = <420>;
txd3-skew-ps = <420>;
};
};
};
&fmc {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&fmc_pins_b>;
pinctrl-1 = <&fmc_sleep_pins_b>;
status = "okay";
ksz8851: ethernet@1,0 {
compatible = "micrel,ks8851-mll";
reg = <1 0x0 0x2>, <1 0x2 0x20000>;
interrupt-parent = <&gpioc>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
bank-width = <2>;
/* Timing values are in nS */
st,fmc2-ebi-cs-mux-enable;
st,fmc2-ebi-cs-transaction-type = <4>;
st,fmc2-ebi-cs-buswidth = <16>;
st,fmc2-ebi-cs-address-setup-ns = <5>;
st,fmc2-ebi-cs-address-hold-ns = <5>;
st,fmc2-ebi-cs-bus-turnaround-ns = <5>;
st,fmc2-ebi-cs-data-setup-ns = <45>;
st,fmc2-ebi-cs-data-hold-ns = <1>;
st,fmc2-ebi-cs-write-address-setup-ns = <5>;
st,fmc2-ebi-cs-write-address-hold-ns = <5>;
st,fmc2-ebi-cs-write-bus-turnaround-ns = <5>;
st,fmc2-ebi-cs-write-data-setup-ns = <45>;
st,fmc2-ebi-cs-write-data-hold-ns = <1>;
};
};
&gpioa {
gpio-line-names = "", "", "", "",
"DRCC-VAR2", "", "", "",
"", "", "", "",
"", "", "", "";
};
&gpioe {
gpio-line-names = "", "", "", "",
"", "DRCC-GPIO0", "", "",
"", "", "", "",
"", "", "", "";
};
&gpiog {
gpio-line-names = "", "", "", "",
"", "", "", "",
"", "", "", "",
"DRCC-GPIO5", "", "", "";
};
&gpioh {
gpio-line-names = "", "", "", "DRCC-HW2",
"DRCC-GPIO4", "", "", "",
"DRCC-HW1", "DRCC-HW0", "", "DRCC-VAR1",
"DRCC-VAR0", "", "", "DRCC-GPIO6";
};
&gpioi {
gpio-line-names = "", "", "", "",
"", "", "", "DRCC-GPIO2",
"", "DRCC-GPIO1", "", "",
"", "", "", "";
};
&i2c1 { /* X11 I2C1 */
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins_b>;
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
/delete-property/dmas;
/delete-property/dma-names;
};
&i2c4 {
hwrtc: rtc@32 {
compatible = "microcrystal,rv8803";
reg = <0x32>;
};
eeprom@50 {
compatible = "atmel,24c04";
reg = <0x50>;
pagesize = <16>;
};
};
&sdmmc1 { /* MicroSD */
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc1_b4_pins_a>;
pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
cd-gpios = <&gpioi 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
disable-wp;
st,neg-edge;
bus-width = <4>;
vmmc-supply = <&vdd>;
vqmmc-supply = <&vdd>;
status = "okay";
};
&sdmmc2 { /* eMMC */
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>;
pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_c>;
pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_c>;
bus-width = <8>;
no-sd;
no-sdio;
non-removable;
st,neg-edge;
vmmc-supply = <&v3v3>;
vqmmc-supply = <&vdd>;
status = "okay";
};
&sdmmc3 { /* SDIO Wi-Fi */
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc3_b4_pins_a>;
pinctrl-1 = <&sdmmc3_b4_od_pins_a>;
pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>;
broken-cd;
bus-width = <4>;
mmc-ddr-3_3v;
st,neg-edge;
vmmc-supply = <&v3v3>;
vqmmc-supply = <&v3v3>;
status = "okay";
};
&spi2 { /* X11 SPI */
pinctrl-names = "default";
pinctrl-0 = <&spi2_pins_b>;
cs-gpios = <&gpioi 0 0>;
status = "disabled";
/delete-property/dmas;
/delete-property/dma-names;
};
&uart4 {
label = "UART0";
pinctrl-names = "default";
pinctrl-0 = <&uart4_pins_d>;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};
&uart5 { /* X11 UART */
label = "X11-UART5";
pinctrl-names = "default";
pinctrl-0 = <&uart5_pins_a>;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};
&uart8 {
label = "RS485-1";
pinctrl-names = "default";
pinctrl-0 = <&uart8_pins_a &uart8_rtscts_pins_a>;
uart-has-rtscts;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};
&usart3 { /* RS485 or RS232 */
label = "RS485-2";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&usart3_pins_e>;
pinctrl-1 = <&usart3_sleep_pins_e>;
uart-has-rtscts;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};
&usbh_ehci {
phys = <&usbphyc_port0>;
status = "okay";
};
&usbh_ohci {
phys = <&usbphyc_port0>;
status = "okay";
};
&usbotg_hs {
dr_mode = "otg";
pinctrl-0 = <&usbotg_hs_pins_a>;
pinctrl-names = "default";
phy-names = "usb2-phy";
phys = <&usbphyc_port1 0>;
vbus-supply = <&vbus_otg>;
status = "okay";
};
&usbphyc {
status = "okay";
};
&usbphyc_port0 {
phy-supply = <&vdd_usb>;
vdda1v1-supply = <&reg11>;
vdda1v8-supply = <&reg18>;
connector {
compatible = "usb-a-connector";
vbus-supply = <&vbus_sw>;
};
};
&usbphyc_port1 {
phy-supply = <&vdd_usb>;
vdda1v1-supply = <&reg11>;
vdda1v8-supply = <&reg18>;
};

View File

@@ -18,6 +18,11 @@
};
};
&vdd {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2900000>;
};
&pwr_regulators {
vdd-supply = <&vdd_io>;
};

View File

@@ -77,8 +77,8 @@
vdd: buck3 {
regulator-name = "vdd";
regulator-min-microvolt = <2900000>;
regulator-max-microvolt = <2900000>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-initial-mode = <0>;
regulator-over-current-protection;

View File

@@ -658,6 +658,8 @@
pinctrl-0 = <&uart4_pins_a>;
pinctrl-1 = <&uart4_sleep_pins_a>;
pinctrl-2 = <&uart4_idle_pins_a>;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};
@@ -666,6 +668,8 @@
pinctrl-0 = <&uart7_pins_c>;
pinctrl-1 = <&uart7_sleep_pins_c>;
pinctrl-2 = <&uart7_idle_pins_c>;
/delete-property/dmas;
/delete-property/dma-names;
status = "disabled";
};

View File

@@ -60,15 +60,26 @@
stdout-path = "serial0:115200n8";
};
hdmi-connector {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&hdmi_out_con>;
};
};
};
leds {
compatible = "gpio-leds";
red {
led-0 {
label = "a1000:red:usr";
gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>;
};
blue {
led-1 {
label = "a1000:blue:pwr";
gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>;
default-state = "on";
@@ -125,7 +136,7 @@
};
&emac {
phy = <&phy1>;
phy-handle = <&phy1>;
status = "okay";
};
@@ -133,6 +144,20 @@
status = "okay";
};
&de {
status = "okay";
};
&hdmi {
status = "okay";
};
&hdmi_out {
hdmi_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
&i2c0 {
status = "okay";

View File

@@ -68,7 +68,7 @@
};
&emac {
phy = <&phy1>;
phy-handle = <&phy1>;
status = "okay";
};

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