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345 Commits

Author SHA1 Message Date
Tom Rini
6d41f0a39d Prepare v2025.01
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-01-06 18:54:44 -06:00
Prasanth Babu Mantena
e7713a7882 dma: ti: k3-udma: Fix BCDMA probe by adding check for MMR_RFLOW
RFLOW config related MMR does not exist incase of BCDMA.
Add check to bypass the RFLOW MMR extraction.
Without this, the probe sequence fails checking for
the MMR_RFLOW region, which is valid only for packet based
DMA and obselete for BCDMA.

Fixes: 5abb694d60 ("dma: ti: k3-udma: Add support for native configuration of chan/flow")
Signed-off-by: Prasanth Babu Mantena <p-mantena@ti.com>
Tested-by: Jonathan Humphreys <j-humphreys@ti.com>
2024-12-31 07:53:17 -06:00
Tom Rini
4be4046075 Prepare v2025.01-rc6
Signed-off-by: Tom Rini <trini@konsulko.com>
2024-12-30 22:07:58 -06:00
Venkatesh Yadav Abbarapu
9bb02f7f45 mtd: spi-nor: Fix the spi_nor_read() when config SPI_STACKED_PARALLEL is enabled
Update the spi_nor_read() function based on the config SPI_FLASH_BAR
and update the length and bank calculation by spliting the memory of
16MB size banks only when the address width is 3byte.
Fix the read issue for 4byte address width by passing the entire
length to the read function.

Fixes: 5d40b3d384 ("mtd: spi-nor: Add parallel and stacked memories support")
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
2024-12-30 08:20:15 -06:00
Tom Rini
cb7410257a Merge tag 'doc-2025-01-rc6' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request doc-2025-01-rc6

Fix a number of typos

* cmd: bootmenu typo 'read'
* cmd/rng: fix long help text
* crypto: typo volatge
* board: freescale: typo volatge
* scripts: add volatge to spelling.txt
* doc: fit: Format image tree source example
2024-12-26 10:21:22 -06:00
Heinrich Schuchardt
0be26928bf scripts: add volatge to spelling.txt
To avoid future misspells add volatge to spelling.txt.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-12-24 18:09:46 +01:00
Heinrich Schuchardt
354a70a5d9 board: freescale: typo volatge
%s/volatge/voltage/g

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
2024-12-24 18:09:46 +01:00
Heinrich Schuchardt
980bcccf41 crypto: typo volatge
%s/volatge/voltage/g

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
2024-12-24 18:07:53 +01:00
J. Neuschäfer
12876f8cd8 doc: fit: Format image tree source example
The example in kernel_fdt.rst is inconsistently indented, making it
difficult to read.

Indent the example with the same standard as the other examples:
Four spaces for the ReST code block and for every nesting level.

Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
2024-12-24 17:06:59 +01:00
Heinrich Schuchardt
528b6b817e cmd/rng: fix long help text
The number of bytes may only be specified if a device number id provided.

Correct the formatting.

Acked-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-12-24 17:02:23 +01:00
Heinrich Schuchardt
f920257ac2 cmd: bootmenu typo 'read'
%s/read/reads/

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-12-24 17:01:57 +01:00
Tom Rini
3391587e3f Prepare v2025.01-rc5
Signed-off-by: Tom Rini <trini@konsulko.com>
2024-12-23 20:40:49 -06:00
Tom Rini
d532df3a61 configs: Resync with savedefconfig
Resync all defconfig files using qconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2024-12-23 08:53:36 -06:00
Tom Rini
0d05bd2058 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh 2024-12-23 08:45:34 -06:00
Marek Vasut
70da4f2859 net: rswitch: Do not register disabled ports as ethernet devices
In case an rswitch port is described as disabled in DT, do not
register it as ethernet device in U-Boot. This way, such ports
cannot be accessed from U-Boot command line.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-22 22:34:32 +01:00
Marek Vasut
118a10e1dd ARM: renesas: Consistently enable ENV_OVERWRITE on Renesas R-Car
Move CONFIG_ENV_OVERWRITE=y into commont renesas_rcar.config to make sure
this configuration option is consistently enabled on all of Renesas R-Car
Gen2, Gen3, Gen4. Currently this option is not enabled on Gen4, this fix
corrects that omission.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-22 22:31:01 +01:00
Tom Rini
cfe57427c2 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh
- Two rswitch fixes and a clock fix
2024-12-21 09:45:30 -06:00
Marek Vasut
fa0f9e83a0 net: rswitch: Add missing cache invalidate of TX descriptor
TFTP transfers of large files, for example 128 MiB, can sporadically
get stuck and the transfer slows down considerably.

This happens because the TX DMA descriptor in DRAM becomes out of sync
with the view of the TX DMA descriptor content from the CPU side, which
is viewed through the CPU caches. In order to guarantee these two views
are consistent, the cache over TX DMA descriptor that has possibly been
written by the rswitch hardware must first be invalidated, only then can
the descriptor be cleared and updated by the CPU, and finally the cache
over that area must be flushed back into DRAM to make sure the rswitch
hardware has consistent view of the updated descriptor content.

The very first invalidation operation was missing, which led to sporadic
corruption of the TX DMA descriptor. Fix it, add the missing invalidation
operation.

Reported-by: Enric Balletbo i Serra <eballetb@redhat.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Tested-by: Enric Balletbo i Serra <eballetb@redhat.com>
2024-12-20 22:20:37 +01:00
Marek Vasut
9899a6a750 net: renesas: Enable TFTP_TSIZE on all Renesas hardware
TFTP transfer size can be used to re-size the TFTP progress bar on
single line based on the server reported file size. Enable it by
default for Renesas hardware to avoid long scrolling walls of '#'
character during long TFTP transfers.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-20 22:20:37 +01:00
Geert Uytterhoeven
08806a6e52 clk: renesas: r8a779h0: Drop CLK_PLL2_DIV2 to clarify ZCn clocks
Early revisions of the R-Car V4M Series Hardware User’s Manual
contained an incorrect formula for the CPU core clocks:

    ZCnφ = (PLL2VCO x 1/2) x mult/32

Dang-san fixed this by using CLK_PLL2_DIV2 instead of CLK_PLL2 as the
parent clock.

In Rev.0.70 of the documentation, the formula was corrected to:

    ZCnφ = (PLL2VCO x 1/4) x mult/32

As the CPG Block Diagram now shows a separate 1/4 post-divider for PLL2,
the use of CLK_PLL2_DIV2 is a recurring source of confusion.  Hence get
rid of CLK_PLL2_DIV2, and include the proper 1/4 post-divider in the
invocation of the DEF_GEN4_Z() macro, like is done on other R-Car Gen4
(and Gen3) SoCs.

Ported from Linux commit
92850bed9d4d ("clk: renesas: r8a779h0: Drop CLK_PLL2_DIV2 to clarify ZCn clocks")

Reported-by: Vinh Nguyen <vinh.nguyen.xz@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/0d2789cac2bf306145fe0bbf269c2da5942bb68f.1728377724.git.geert+renesas@glider.be
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-20 22:20:37 +01:00
Tom Rini
5c8ef70f08 Merge tag 'xilinx-for-v2025.01-rc5-v2' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
AMD/Xilinx changes for v2025.01-rc5 - second

- Fix find_ram_top() return to support configs > 4GB
2024-12-20 08:26:16 -06:00
Venkatesh Yadav Abbarapu
1b70b6c9cc common: memtop: Fix the return type for find_ram_top
As the return type is "int" for find_ram_top() function and
returning the "base" which is of phys_addr_t is breaking when the
"base" address is 64-bit. So fix this by updating the return type as
phys_addr_t.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Reviewed-by: Michal Simek <michal.simek@amd.com>
Acked-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Link: https://lore.kernel.org/r/20241220030742.1745984-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2024-12-20 09:17:43 +01:00
Manorit Chawdhry
c06705a9a1 Makefile: Match the full path to ccache for filtering
One can use ccache by keeping ccache in PATH or by providing the full
path to ccache as well. Providing the full path to ccache fails as the
current regex tries to look for ccache being the initial token during
filtering.

Do a greedy search to remove anything before ccache for regex matching.

Fixes: 04b1d84221 ("Makefile: fix empty MK_ARCH when using ccache")
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2024-12-19 12:18:57 -06:00
Ilias Apalodimas
0b7f4c7cf3 imx: Fix usable memory ranges for imx8m SOCs
commit e27bddff4b ("imx8m: Restrict usable memory to space below 4G boundary")
tried to adjust the usable memory limits on a 4GB boundary.

ram_top is described as 'top address of RAM used by U-Boot' and we want
to preserve that. This is defined as a phys_addr_t and unfortunately
its size differs across architectures. This has lead us to a weird
state where 32bit boards define it 'SZ_4GB - 1' and 64bit boards as
'SZ_4GB' unless it was otherwise defined.

With some recent LMB changes and specifically
commit 1a48b0be93 ("lmb: prohibit allocations above ram_top even from same bank")
the board fails to boot properly although the commit above is correct
since it's making sure that no memory above ram_top is usable -- but
added to our memory map so EFI can hand it over to the booted OS.

The reason for that is that during the LMB init we add all usable memory
in lmb_add_memory(). In that function any memory above ram_top gets added
as 'reserved' for LMB. With the current values tha's set to 0xFFFF_FFFF
for this board. Later LMB is trying to protect the memory area U-Boot lives
in with lmb_reserve_common(). The latter fails though since it tries to
add U-Boot top (which is 0xFFFF_FFFF as well) to U-Boot 'bottom'. This call
will fail since 1 byte of that memory range is already marked as 'reserved'.

Since we are close to the release, LMB seems to assume that the address
is rounded up and is the 'next address' and so does parsing and adding
memory ranges from DT files, bump the ram_top of the board by 1byte.

In the long run we should change all of the above and have 32b and 64b
platforms define ram_top identically.

Add a Fixes tag although the commit is correct, so people can figure out
the broken scenarios in the future.

Suggested-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Fixes: commit 1a48b0be93 ("lmb: prohibit allocations above ram_top even from same bank")
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reported-by: João Paulo Gonçalves <jpaulo.silvagoncalves@gmail.com>
Closes: https://lore.kernel.org/all/20241216114231.qpfwug3zfqkxn3d5@joaog-nb.corp.toradex.com/
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Fixes: 74f88b7221 ("ARM: imx: imx8m: Fix board_get_usable_ram_top()")
2024-12-19 12:17:52 -06:00
E Shattow
ff1d5d87d0 Revert "configs: JH7110: enable EFI_LOADER_BOUNCE_BUFFER"
("Enable EFI_LOADER_BOUNCE_BUFFER") is not the correct fix for the
problem it describes.

The change of memory addressing leading to side-effects in commit
22f2c9ed9f ("efi: memory: use the lmb API's for allocating and
freeing memory") is remedied by commit 1a48b0be93 ("lmb: prohibit
allocations above ram_top even from same bank").

This reverts commit 9c792ab336.
2024-12-19 12:17:44 -06:00
Heinrich Schuchardt
d701c6ab42 net: lwip: check if network device is available in do_dhcp
eth_get_dev() returns NULL if no network device is available.
Not checking the return value leads to a crash when the device
pointer is dereferenced.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
2024-12-19 12:17:37 -06:00
Heinrich Schuchardt
b6691d0add net: lwip: do not return CMD_RET_USAGE if no interface
If the dns command cannot find a network interface, we should return
CMD_RETFAIURE and not -1 (CMD_RET_USAGE).

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
2024-12-19 12:17:32 -06:00
Tom Rini
9378307136 binman: Regenerate tools/binman/entries.rst
There have been a few changes to the areas that this file documents
without having regenerated the file. Do so now.

Signed-off-by: Tom Rini <trini@konsulko.com>
2024-12-19 10:19:57 -06:00
Tom Rini
1688f84745 Merge tag 'u-boot-dfu-20241219' of https://source.denx.de/u-boot/custodians/u-boot-dfu
CI: https://source.denx.de/u-boot/custodians/u-boot-dfu/-/pipelines/23951

Android:
- Fix kcmdline_extra support when parsing boot image
- Fix memory leak when after bootargs concatenation
- Fix length calculation when merging bootargs, cmdline and kcmdline
2024-12-19 10:19:29 -06:00
Tom Rini
69bd83568c Merge tag 'u-boot-stm32-20241218' of https://source.denx.de/u-boot/custodians/u-boot-stm
CI: https://source.denx.de/u-boot/custodians/u-boot-stm/-/pipelines/23931

- Restore SPL boot from sdcard for STM32MP1 platforms
- Fix STACK_SIZE for STM32 MCU's board
2024-12-18 08:01:17 -06:00
Nicolas Belin
9e5fad0f79 boot: android: rework bootargs concatenation
Rework the bootargs concatenation allocating more accurately
the length that is needed.
Do not forget an extra byte for the null termination byte as,
in some cases, the allocation was 1 byte short.

Fixes: 86f4695b ("image: Fix Android boot image support")
Signed-off-by: Nicolas Belin <nbelin@baylibre.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Link: https://lore.kernel.org/r/20241217-fix-bootargs-concatenation-v2-3-b2fd7cf4e130@baylibre.com
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2024-12-18 14:04:23 +01:00
Nicolas Belin
fd8b44a81b boot: android: free newbootargs when done
Free newbootargs when the concatenation is done and bootargs env
is set.

Fixes: 86f4695b ("image: Fix Android boot image support")
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Signed-off-by: Nicolas Belin <nbelin@baylibre.com>
Link: https://lore.kernel.org/r/20241217-fix-bootargs-concatenation-v2-2-b2fd7cf4e130@baylibre.com
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2024-12-18 14:04:23 +01:00
Nicolas Belin
53a0ddb6d3 boot: android: fix extra command line support
Check that the value at the address kcmdline_extra is not 0
instead of checking the address value itself keeping it
consistent with what is done for kcmdline.

Fixes: b36b227b ("android: boot: support extra command line")
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Signed-off-by: Nicolas Belin <nbelin@baylibre.com>
Link: https://lore.kernel.org/r/20241217-fix-bootargs-concatenation-v2-1-b2fd7cf4e130@baylibre.com
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2024-12-18 14:04:23 +01:00
Patrice Chotard
06a8063ec9 configs: stm32mp1: Restore boot SPL from sdcard for Engicam i.Core STM32MP1 C.TOUCH 2.0
Restore boot SPL from sdcard for Engicam i.Core STM32MP1 C.TOUCH 2.0.

Fixes: 2a00d73d08 ("spl: mmc: Try to clean up raw-mode options")

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2024-12-18 11:34:10 +01:00
Patrice Chotard
f3f14c2e3b configs: stm32mp1: Restore boot SPL from sdcard for Engicam MicroGEA STM32MP1 MicroDev 2.0 7" OF
Restore boot SPL from sdcard for Engicam MicroGEA STM32MP1 MicroDev 2.0 7" OF

Fixes: 2a00d73d08 ("spl: mmc: Try to clean up raw-mode options")

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2024-12-18 11:34:10 +01:00
Patrice Chotard
fb612b4b53 configs: stm32mp1: Restore boot SPL from sdcard for Engicam i.Core STM32MP1 EDIMM2.2
Restore boot SPL from sdcard for Engicam i.Core STM32MP1 EDIMM2.2.

Fixes: 2a00d73d08 ("spl: mmc: Try to clean up raw-mode options")

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2024-12-18 11:34:10 +01:00
Patrice Chotard
c8eacfcedc configs: stm32mp1: Restore boot SPL from sdcard for Engicam i.Core STM32MP1 C.TOUCH 2.0
Restore boot SPL from sdcard for Engicam i.Core STM32MP1 C.TOUCH 2.0.

Fixes: 2a00d73d08 ("spl: mmc: Try to clean up raw-mode options")

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2024-12-18 11:34:10 +01:00
Patrice Chotard
7169576807 configs: stm32mp1: Restore boot SPL from sdcard for stm32mp15
Restore boot SPL from sdcard for STM32MP1 platforms.

Fixes: 2a00d73d08 ("spl: mmc: Try to clean up raw-mode options")

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2024-12-18 11:34:10 +01:00
Marek Vasut
5470a6a0b1 ARM: dts: stm32: Deduplicate CONFIG_OF_SPL_REMOVE_PROPS on DH STM32MP15xx DHSOM
The content of CONFIG_OF_SPL_REMOVE_PROPS is the same in both
STM32MP15xx DHCOM and DHCOR defconfigs, deduplicate the content
into stm32mp15_dhsom.config .

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2024-12-18 11:30:28 +01:00
Marek Vasut
72c6a40fad ARM: dts: stm32: Drop access-controllers from SPL DT on DH STM32MP15xx DHSOM
The access-controllers DT property is not useful in STM32MP15xx SPL,
remove it to reduce SPL control DT size. No functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2024-12-18 11:30:27 +01:00
Marek Vasut
dae1f13daa ARM: dts: stm32: Reinstate SPL_SYS_MMCSD_RAW_MODE on DH STM32MP15xx DHSOM
Commit 2a00d73d08 ("spl: mmc: Try to clean up raw-mode options")
broke booting from SD card on STM32MP15xx , reinstate raw mode SD
boot configuration options and select the correct raw mode partition
for STM32MP15xx to fix SD boot on STM32MP15xx DHSOM.

Fixes: 2a00d73d08 ("spl: mmc: Try to clean up raw-mode options")
Reported-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2024-12-18 11:30:27 +01:00
Marek Vasut
b651906122 ARM: dts: stm32: Reinstate missing root oscillators on DH STM32MP15xx DHCOR
The root oscillators reference used to be in rcc node since
3d15245502 ("ARM: dts: stm32mp1: explicit clock reference needed by RCC clock driver")
however this is not part of upstream stm32mp151.dtsi . The
RCC driver does need this reference, reinstate it locally.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2024-12-18 11:30:27 +01:00
Marek Vasut
edc425ef16 ARM: dts: stm32: Reinstate missing root oscillators on STM32MP15xx
The root oscillators reference used to be in rcc node since
3d15245502 ("ARM: dts: stm32mp1: explicit clock reference needed by RCC clock driver")
however this is not part of upstream stm32mp151.dtsi . The
RCC driver does need this reference, reinstate it globally.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Tested-by: Patrice Chotard <patrice.chotard@foss.st.com>
2024-12-18 11:29:47 +01:00
Patrice Chotard
d4ce588515 Kconfig: Set STACK_SIZE to 16KB for STM32 MCUs
Since commit 6534d26ee9 ("lmb: do away with arch_lmb_reserve()"),
STM32F746-disco hangs when loading device tree just before starting
kernel:

Retrieving file: /stm32f746-disco.dtb
Kernel image @ 0xc0008000 [ 0x000000 - 0x19ae00 ]
Flattened Device Tree blob at c0408000
   Booting using the fdt blob at 0xc0408000
Working FDT set to c0408000
   Loading Device Tree to c05f8000, end c05ff71c ...

Adjust STACK_SIZE to 16KB for STM32 MCUs (F4/F7 and H7) boards
to fix kernel boot process as some of these boards embeds a limited
amount of memory.

Fixes: 6534d26ee9 ("lmb: do away with arch_lmb_reserve()")

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2024-12-18 11:27:14 +01:00
Patrice Chotard
25fb58e88a ARM: stm32mp: Fix dram_bank_mmu_setup() for LMB located above ram_top
Previously, all LMB marked with LMB_NOMAP (above and below ram_top)
are considered as invalid entry in TLB.

Since commit 1a48b0be93 ("lmb: prohibit allocations above ram_top
 even from same bank") all LMB located above ram_top are now marked
LMB_NOOVERWRITE and no more LMB_MAP.

This area above ram_top is reserved for OPTEE and must not be cacheable,
otherwise this leads to a Panic on some boards (Issue on STM32MP135F-DK).

Restore previous behavior by marking invalid entry all TLB above ram_top.

Fixes: 1a48b0be93 ("lmb: prohibit allocations above ram_top even from same bank")

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
cc: Sughosh Ganu <sughosh.ganu@linaro.org>
Acked-by: Sughosh Ganu <sughosh.ganu@linaro.org>
2024-12-17 09:14:01 -06:00
Simon Glass
1cde96bee5 gitlab: Add an rpi to the sjg lab
I have an original rpi installed now, loaded with OS Lite (32-bit)
Add an entry for it so that it can be used for testing.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-12-17 09:13:31 -06:00
Simon Glass
315fd02729 boot: Use correct PHASE_ variable for expo
This patch was written before the XPL change-over. Update the Makefile
condition to the new way.

Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: ae3b5928d6 ("x86: coreboot: Allow building an expo for...")
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
2024-12-17 09:11:49 -06:00
Simon Glass
a8f09d6282 test/py: Always use the current dir as the source tree
The logic in get_details() retrieves the default source directory from
the Labgrid settings. This is convenient for interactive use, since it
allows pytests to be run from any directory and still find the source
tree.

However, it is not actually correct.

Gitlab sets the current directory to the source tree and expects that to
be used. At present it is ignored. The result is that Gitlab builds
whatever happens to be in the default source directory, ignoring the
tree it is supposed to be building.

Fix this by using the directory of the source tree, always. This is
obtained by looking at the grandparent of the conftest.py file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Tom Rini <trini@konsulko.com>
Fixes: bf89a8f1fc ("test: Introduce the concept of a role")
Tested-by: Tom Rini <trini@konsulko.com>
2024-12-17 09:11:43 -06:00
Tom Rini
429d4846ea Merge patch series "Tegra: fix clock init"
Svyatoslav Ryhel <clamor95@gmail.com> says:

This should fix:
https://lore.kernel.org/all/20241201164810.GT3600562@bill-the-cat/T/#m2b62b471fd37e4c9725c98547e2a919cf11db5e5

Link: https://lore.kernel.org/r/20241213145319.10956-1-clamor95@gmail.com
2024-12-16 17:07:42 -06:00
Svyatoslav Ryhel
b46bd4f874 driver: clk: tegra: init basic clocks on probe
In case DM drivers probe earlier than board clock setup is done
init of basic clocks should be done in CAR driver probe as well.
Add it to avoid possible clock related problems.

Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2024-12-16 17:07:39 -06:00
Svyatoslav Ryhel
1db256a347 driver: clk: tegra: partially support PLL clocks
Return PLL id into struct clk if PLL is parsed from device
tree instead of throwing an error. Allow requesting PLL
clock rate via get_rate op.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2024-12-16 17:07:39 -06:00
Tom Rini
e46fe0daf3 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-mmc
CI: https://source.denx.de/u-boot/custodians/u-boot-mmc/-/pipelines/23871

- Fix potential timer value truncation
2024-12-16 16:17:13 -06:00
Ronald Wahl
822afeb7bf mmc: Fix potential timer value truncation
On 64bit systems the timer value might be truncated to a 32bit value
causing malfunctions. For example on ARM the timer might start from 0
again only after a cold reset. The 32bit overflow occurs after a bit
more than 49 days (1000 Hz counter) so booting after that time may lead
to a surprise because the board might become stuck requiring a cold
reset.

Signed-off-by: Ronald Wahl <ronald.wahl@legrand.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2024-12-16 11:24:42 +09:00
Tom Rini
50334151c0 Merge tag 'fsl-qoriq-2024-12-15' of https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq
CI: https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq/-/pipelines/23856

- Use strcat to replace sprintf for t208xqds
- Fix bootefi for board ls1028a
- Various fixes to sl28 board
2024-12-15 08:02:46 -06:00
Tom Rini
eb1817ad87 Merge tag 'doc-2025-01-rc5' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request doc-2025-01-rc5

Documentation:

* sending_patches: Fix spelling of "its"
* environment: NET_LWIP dhcp sets ipaddrN, netmaskN and gatewayipN
* remove redundant Rockchip bindings
* fwu_updates: Fix formatting
* coolpi: Fix document style
* board: theobroma-systems: fix feature list in introductions

Fix typos in code comments:

* clk: mpc83xx: Fix typo in "Coherent System Bus"
* efi_loader: Fix typos in enum efi_allocate_type
2024-12-15 08:02:22 -06:00
Francois Berder
c71aaaf6a8 board: freescale: Replace invalid usage of sprintf by strcat
buf was used as destination and as parameter to sprintf
which triggers an undefined behaviour.
This commit removes this usage of sprintf and uses strcat
to append strings to buf variable.

Signed-off-by: Francois Berder <fberder@outlook.fr>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2024-12-15 10:08:07 +08:00
Wei Ming Chen
b4626f3934 configs: ls1028a: Fix bootefi issue on Layerscape ls1028ardb platform
Without this patch, there will be error indicating that
"Cannot use 64 bit addresses with SDMA", and the booting
process will stuck.

please see full boot log below

U-Boot 2022.04-g18185931 (Sep 11 2024 - 13:15:30 +0800)

SoC:  LS1028AE Rev1.0 (0x870b0010)
Clock Configuration:
       CPU0(A72):1500 MHz  CPU1(A72):1500 MHz
       Bus:      400  MHz  DDR:      1600 MT/s
Reset Configuration Word (RCW):
       00000000: 3c004010 00000030 00000000 00000000
       00000010: 00000000 018f0000 0030c000 00000000
       00000020: 020031a0 00002580 00000000 00003296
       00000030: 00000000 00000010 00000000 00000000
       00000040: 00000000 00000000 00000000 00000000
       00000050: 00000000 00000000 00000000 00000000
       00000060: 00000000 00000000 200e705a 00000000
       00000070: bb580000 00000000
Model: LS1028A RDB Board
Board: LS1028AE Rev1.0-RDB, Version: C, boot from SD
FPGA: v8 (RDB)
SERDES1 Reference : Clock1 = 100.00MHz Clock2 = 100.00MHz
DRAM:  3.9 GiB
DDR    3.9 GiB (DDR4, 32-bit, CL=11, ECC on)
Using SERDES1 Protocol: 47960 (0xbb58)
PCIe1: pcie@3400000 Root Complex: no link
PCIe2: pcie@3500000 Root Complex: x1 gen2
Core:  45 devices, 22 uclasses, devicetree: separate
WDT:   Started watchdog@c000000 with servicing (60s timeout)
WDT:   Started watchdog@c010000 with servicing (60s timeout)
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
Loading Environment from MMC... *** Warning - bad CRC, using default environment

EEPROM: Invalid ID (ff ff ff ff)
In:    serial
Out:   serial
Err:   serial
SEC0:  RNG instantiated
Net:
Warning: enetc-0 (eth0) using random MAC address - d2:9b:a5:37:7b:b5
eth0: enetc-0
Warning: enetc-2 (eth1) using random MAC address - ca:57:11:de:de:cb
, eth1: enetc-2, eth2: swp0, eth3: swp1, eth4: swp2, eth5: swp3
Hit any key to stop autoboot:  0
Trying load HDP firmware from SD..
switch to partitions #0, OK
mmc0 is current device
Device: FSL_SDHC
Manufacturer ID: 9f
OEM: 5449
Name: SD32G
Bus Speed: 50000000
Mode: SD High Speed (50MHz)
Rd Block Len: 512
SD version 3.0
High Capacity: Yes
Capacity: 28.9 GiB
Bus Width: 4-bit
Erase Group Size: 512 Bytes

MMC read: dev # 0, block # 18944, count 512 ... 512 blocks read: OK
Loading hdp firmware from 0x00000000a0000000 offset 0x0000000000002000
Loading hdp firmware Complete
switch to partitions #0, OK
mmc0 is current device
Scanning mmc 0:1...
** Unable to read file / **
Failed to load '/'
libfdt fdt_check_header(): FDT_ERR_BADMAGIC
Scanning disk mmc@2140000.blk...
Scanning disk mmc@2150000.blk...
Found 7 disks
ERROR: invalid device tree
Found EFI removable media binary efi/boot/bootaa64.efi
981992 bytes read in 44 ms (21.3 MiB/s)
libfdt fdt_check_header(): FDT_ERR_BADMAGIC
WARNING could not find node vivante,gc: FDT_ERR_NOTFOUND.
Booting /efi\boot\bootaa64.efi
Cannot use 64 bit addresses with SDMA
Error reading cluster
** Unable to read file /efi/boot/grubaa64.efi **
Unexpected return from initial read: Device Error, buffersize 29D790
Failed to load image ぀¬ : Device Error
start_image() returned Device Error
EFI LOAD FAILED: continuing...
switch to partitions #0, OK
mmc1(part 0) is current device
Scanning mmc 1:1...
** Unable to read file / **
Failed to load '/'
libfdt fdt_check_header(): FDT_ERR_BADMAGIC
BootOrder not defined
EFI boot manager: Cannot load any image
Scanning mmc 1:2...
** Unable to read file / **
Failed to load '/'
libfdt fdt_check_header(): FDT_ERR_BADMAGIC
BootOrder not defined
EFI boot manager: Cannot load any image
starting USB...
Bus usb@3100000: Register 200017f NbrPorts 2
Starting the controller
USB XHCI 1.00
Bus usb@3110000: Register 200017f NbrPorts 2
Starting the controller
USB XHCI 1.00
scanning bus usb@3100000 for devices... 1 USB Device(s) found
scanning bus usb@3110000 for devices... 1 USB Device(s) found
       scanning usb for storage devices... 0 Storage Device(s) found

Device 0: unknown device
Trying load from SD ...
switch to partitions #0, OK
mmc0 is current device
Device: FSL_SDHC
Manufacturer ID: 9f
OEM: 5449
Name: SD32G
Bus Speed: 50000000
Mode: SD High Speed (50MHz)
Rd Block Len: 512
SD version 3.0
High Capacity: Yes
Capacity: 28.9 GiB
Bus Width: 4-bit
Erase Group Size: 512 Bytes

MMC read: dev # 0, block # 32768, count 81920 ... 81920 blocks read: OK
Wrong Image Format for bootm command
ERROR: can't get kernel image!

Signed-off-by: Wei Ming Chen <jj251510319013@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2024-12-15 09:49:16 +08:00
Leonard Anderweit
55e8704402 doc: cosmetic: fwu_updates: Fix formatting
Remove one of the double colon so ..code-block is used for formatting.

Signed-off-by: Leonard Anderweit <l.anderweit@phytec.de>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2024-12-15 02:11:13 +01:00
Jerome Forissier
d8b0020dde doc: environment: NET_LWIP dhcp sets ipaddrN, netmaskN and gatewayipN
Document environment variables set by the dhcp command when the network
stack is lwIP.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
2024-12-15 02:09:34 +01:00
Quentin Schulz
c7360f17fb doc: board: theobroma-systems: fix feature list in introductions
Board introductions have a feature list which isn't formatted properly
according to rST and is thus rendered incorrectly.

Fix this by adding the missing newlines in the appropriate places.

Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
2024-12-15 02:07:54 +01:00
Simon Glass
920e165ebf efi_loader: Fix typos in enum efi_allocate_type
Fix 'indicatged' and 'adress' typos.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
2024-12-15 02:07:23 +01:00
Andy Yan
d9825e8d0f doc: coolpi: Fix document style
Add a blank line after title "Specification:" to
make it render correctly html.

And also remove the useless > in bash code block.

Signed-off-by: Andy Yan <andyshrk@163.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
2024-12-15 02:05:36 +01:00
Johan Jonker
4888d1bd0e doc: remove redundant Rockchip bindings
Most Rockchip device tree related bindings are converted to YAML
and available in the U-boot /dts/upstream/Bindings/ directory.
Remove all redundant U-boot entries.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
2024-12-15 02:05:04 +01:00
J. Neuschäfer
a7dc9f3220 doc: sending_patches: Fix spelling of "its"
Although it has historically been different, the current standard
spelling of the neutral singular possessive pronoun is "its".

Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
2024-12-15 02:03:52 +01:00
J. Neuschäfer
69ec7f35e0 clk: mpc83xx: Fix typo in "Coherent System Bus"
Cosmetic change.

Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
2024-12-15 02:03:52 +01:00
Michael Walle
56aa021f08 board: sl28: fix USB0
Since commit 61ff13283c ("board: sl28: move to OF_UPSTREAM") USB0 is
broken because the former u-boot soc dtsi was setting dr_mode to "host"
but the linux device tree isn't. That is because linux fully supports
OTG but u-boot doesn't. Therefore, u-boot only ever enabled host mode
and never OTG mode. Add it to our board "-u-boot.dtsi" to fix it.

Fixes: 61ff13283c ("board: sl28: move to OF_UPSTREAM")
Reported-by: Heiko Thiery <heiko.thiery@gmail.com>
Signed-off-by: Michael Walle <mwalle@kernel.org>
Tested-by: Heiko Thiery <heiko.thiery@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2024-12-15 09:00:32 +08:00
Michael Walle
079ae2734c doc: board: sl28: fix table
Convert the table to a correct reST table syntax.

Signed-off-by: Michael Walle <mwalle@kernel.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2024-12-15 09:00:32 +08:00
Michael Walle
ad7ebf1b98 board: sl28: fix network on variant 3
Network is broken on variant 3 boards since commit 61ff13283c ("board:
sl28: move to OF_UPSTREAM") because it was removing the variant 3
handling. That is because at that time the var3 device tree was not
upstream. FWIW variant 3 is actually the same as the base variant, but
I've missed that the -u-boot.dtsi is not inlcuded in this case which
will set the ethernet alias.  Now that the var3 device tree is upstream,
just re-add it to the SPL handling again.

Fixes: 61ff13283c ("board: sl28: move to OF_UPSTREAM")
Signed-off-by: Michael Walle <mwalle@kernel.org>
Reviewed-by: Heiko Thiery <heiko.thiery@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2024-12-15 09:00:32 +08:00
Michael Walle
6c849340b7 board: sl28: increase SPL_SYS_MALLOC_SIZE
Increase the malloc size to 2MiB because our FIT image exceeds the 1MiB
limit either if BL31 mode is enabled or if another device tree is added
to the image.

Signed-off-by: Michael Walle <mwalle@kernel.org>
Tested-by: Heiko Thiery <heiko.thiery@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2024-12-15 09:00:31 +08:00
Michael Walle
781a7c660c board: sl28: fix linking with disabled watchdog
We don't have a reference to the driver used by
uclass_get_device_by_driver() in stop_recovery_watchdog(). Fix it by not
calling that function if the watchdog driver isn't enabled.

Signed-off-by: Michael Walle <mwalle@kernel.org>
Reviewed-by: Heiko Thiery <heiko.thiery@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2024-12-15 09:00:31 +08:00
Tom Rini
88bd5701ef Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-usb
- USB onboard-hub fix
2024-12-12 09:50:25 -06:00
Tom Rini
39adaa54cc Merge tag 'xilinx-for-v2025.01-rc5' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
AMD/Xilinx changes for v2025.01-rc5

- Fix reset issue for SOM
2024-12-12 09:20:52 -06:00
Sam Protsenko
5a6aa7d591 boot: fdt: Handle already reserved memory in boot_fdt_reserve_region()
The boot_fdt_add_mem_rsv_regions() function can be called twice, e.g.
first time during the board init (as a part of LMB init), and then when
booting the OS with 'booti' command:

    lmb_add_region_flags
    lmb_reserve_flags
    boot_fdt_reserve_region
    boot_fdt_add_mem_rsv_regions
               ^
               |
               +-----------------------+
               | (1)                   | (2)
    lmb_reserve_common        image_setup_linux
    lmb_init                  ...
    initr_lmb                 do_booti
    board_init_r              'booti'

That consequently leads to the attempt of reserving the same memory
areas (described in the 'reserved-memory' dts node) in LMB. The
lmb_add_region_flags() returns -EEXIST error code in such cases, but
boot_fdt_reserve_region() handles all negative error codes as a failure
to reserve fdt memory region, printing corresponding error messages,
which are essentially harmless, but misleading. For example, this is the
output of 'booti' command on E850-96 board:

    => booti $loadaddr - $fdtaddr
    ...
    ERROR: reserving fdt memory region failed
           (addr=bab00000 size=5500000 flags=2)
    ERROR: reserving fdt memory region failed
           (addr=f0000000 size=200000 flags=4)
    ...
    Starting kernel ...

The mentioned false positive error messages are observed starting with
commit 1d9aa4a283 ("lmb: Fix the allocation of overlapping memory
areas with !LMB_NONE"), which removes the check for the already added
memory regions in lmb_add_region_flags(), making it return -1 for
!LMB_NONE cases. Another commit 827dee587b ("fdt: lmb: add reserved
regions as no-overwrite") changes flags used for reserving memory in
boot_fdt_add_mem_rsv_regions() from LMB_NONE to LMB_NOOVERWRITE. So
together with the patch mentioned earlier, it makes
lmb_add_region_flags() return -1 when called from
boot_fdt_reserve_region().

Since then, the different patch was implemented, returning -EEXIST error
code in described cases, which is:

   lmb: Return -EEXIST in lmb_add_region_flags() if region already added

Handle -EEXIST error code as a normal (successful) case in
lmb_reserve_flags() and don't print any messages.

Fixes: 1d9aa4a283 ("lmb: Fix the allocation of overlapping memory areas with !LMB_NONE")
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Tested-by: Michal Simek <michal.simek@amd.com>
2024-12-12 09:20:32 -06:00
Sam Protsenko
8b8b35a4f5 lmb: Return -EEXIST in lmb_add_region_flags() if region already added
An attempt to add the already added LMB region using
lmb_add_region_flags() ends up in lmb_addrs_overlap() check, which
eventually leads to either returning 0 if 'flags' is LMB_NONE, or -1
otherwise. It makes it impossible for the user of this function to catch
the case when the region is already added and differentiate it from
regular errors. That in turn may lead to incorrect error handling in the
caller code, like reporting misleading errors or interrupting the normal
code path where it could be treated as the normal case. An example is
boot_fdt_reserve_region() function, which might be called twice (e.g.
during board startup in initr_lmb(), and then during 'booti' command
booting the OS), thus trying to reserve exactly the same memory regions
described in the device tree twice, which produces an error message on
second call.

Return -EEXIST error code in case when the added region exists and it's
not LMB_NONE; for LMB_NONE return 0, to conform to unit tests
(specifically test_alloc_addr() in test/lib/lmb.c) and the preferred
behavior described in commit 1d9aa4a283 ("lmb: Fix the allocation of
overlapping memory areas with !LMB_NONE"). The change of
lmb_add_region_flags() return values is described in the table below:

    Return case                        Pre-1d9   1d9    New
    -----------------------------------------------------------
    Added successfully                    0      0      0
    Failed to add                         -1     -1     -1
    Already added, flags == LMB_NONE      0      0      0
    Already added, flags != LMB_NONE      0      -1     -EEXIST

Rework all affected functions and their documentation. Also fix the
corresponding unit test which checks reserving the same region with the
same flags to account for the changed return value.

No functional change is intended (by this patch itself).

Fixes: 1d9aa4a283 ("lmb: Fix the allocation of overlapping memory areas with !LMB_NONE")
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Tested-by: Michal Simek <michal.simek@amd.com>
2024-12-12 09:20:32 -06:00
Roger Quadros
e371dfef21 configs: am62x_evm_*: Fix USB DFU configuration
CONFIG_USB_XHCI_DWC3 is not required for AM62x as the XHCI
driver is registered through the dwc3-generic driver.

CONFIG_USB_XHCI_DWC3 causes problems by hijacking the
USB controller even if it is not set for Host mode in
device tree.

'dm tree' output after 'usb start' is fixed from

 simple_bus    5  [ + ]   dwc3-am62             |   |-- dwc3-usb@f900000
 usb_gadget    0  [   ]   dwc3-generic-periphe  |   |   |-- usb@31000000
 usb           0  [ + ]   xhci-dwc3             |   |   `-- usb@31000000
 usb_hub       0  [ + ]   usb_hub               |   |       `-- usb_hub
 simple_bus    6  [ + ]   dwc3-am62             |   |-- dwc3-usb@f910000
 usb           1  [ + ]   dwc3-generic-host     |   |   |-- usb@31100000
 usb_hub       1  [ + ]   usb_hub               |   |   |   `-- usb_hub
 usb           1  [ + ]   xhci-dwc3             |   |   `-- usb@31100000
 usb_hub       2  [ + ]   usb_hub               |   |       `-- usb_hub

[notice that 'xhci-dwc3' and 'usb_hub' drivers are probed
 for both USB instances although the first instance
 is supposed to be 'peripheral' only]

to

 simple_bus    5  [   ]   dwc3-am62             |   |-- dwc3-usb@f900000
 usb_gadget    0  [   ]   dwc3-generic-periphe  |   |   `-- usb@31000000
 simple_bus    6  [ + ]   dwc3-am62             |   |-- dwc3-usb@f910000
 usb           1  [ + ]   dwc3-generic-host     |   |   `-- usb@31100000
 usb_hub       0  [ + ]   usb_hub               |   |       `-- usb_hub

Fixes: dfc2dff5a8 ("configs: am62x_evm_*: Enable USB and DFU support")
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
2024-12-12 09:20:06 -06:00
Tom Rini
9452fb7484 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh
- Fix some spelling mistakes
2024-12-11 12:50:29 -06:00
Tom Rini
26512629fb Merge tag 'rpi-2025.01-rc5' of https://source.denx.de/u-boot/custodians/u-boot-raspberrypi
Updates for RPi for 2025.01:

- Enable capsule updates
- Pass CMA through from firmware DT
2024-12-11 10:17:59 -06:00
Ilias Apalodimas
6a5fc32fd2 board: rpi: Enable capsule updates
Since RPI works well using EFI and has no size limitations with regards
to U-Boot, add the needed structures to support capsule updates.

While at it update the most commonly used defconfigs and include capsule
support and U-Boot commands needed by EFI

Tested-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-12-11 15:54:52 +00:00
Michal Simek
8b81010a2f video: zynqmp: Add support for reset
In Kria SOM configuration DP is under reset and access to DP is causing
hang that's why call reset at probe to avoid this situation.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/0504474a91a9839828aecd37f8855fd154cdf2e1.1733742708.git.michal.simek@amd.com
2024-12-11 12:40:13 +01:00
Peter Robinson
28a620d281 board: rpi: Pass CMA through from firmware DT
For a lot of usecases, such as display, camera, media
the Raspberry Pi needs a lot more CMA than distros
configure as default so we should pass this parameter
through so things work as expected. Fix a spelling
mistake while we're at it.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Matthias Brugger <mbrugger@suse.com>
2024-12-11 09:41:22 +00:00
Marek Vasut
802b08805c usb: renesas: Fix R-Car spelling
The correct spelling is R-Car, including the dash, update the usage.
Kconfig strings and comment changes only, no functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-11 08:36:24 +01:00
Marek Vasut
14655e62cf spi: renesas: Fix R-Car spelling
The correct spelling is R-Car, including the dash, update the usage.
Kconfig strings and comment changes only, no functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-11 08:36:24 +01:00
Marek Vasut
b1c2886cf2 serial: renesas: Fix R-Car spelling
The correct spelling is R-Car, including the dash, update the usage.
Kconfig strings and comment changes only, no functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-11 08:36:24 +01:00
Marek Vasut
4380b31e40 pinctrl: renesas: Fix R-Car spelling
The correct spelling is R-Car, including the dash, update the usage.
Kconfig strings and comment changes only, no functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-11 08:36:24 +01:00
Marek Vasut
1bf8f02f14 phy: renesas: Fix R-Car spelling
The correct spelling is R-Car, including the dash, update the usage.
Comment changes only, no functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-11 08:36:24 +01:00
Marek Vasut
7246f98d29 pci: renesas: Fix R-Car spelling
The correct spelling is R-Car, including the dash, update the usage.
Kconfig strings and comment changes only, no functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-11 08:36:24 +01:00
Marek Vasut
5f97f5c7ed mtd: renesas: Fix R-Car spelling
The correct spelling is R-Car, including the dash, update the usage.
Kconfig strings and comment changes only, no functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-11 08:36:24 +01:00
Marek Vasut
190c6d05e8 mmc: renesas: Fix R-Car spelling
The correct spelling is R-Car, including the dash, update the usage.
Comment changes only, no functional change.

Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-11 08:36:24 +01:00
Marek Vasut
1fea57811f i2c: renesas: Fix R-Car spelling
The correct spelling is R-Car, including the dash, update the usage.
Kconfig strings and comment changes only, no functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-11 08:36:24 +01:00
Marek Vasut
4a9c8946b8 gpio: renesas: Fix R-Car spelling
The correct spelling is R-Car, including the dash, update the usage.
Kconfig strings and comment changes only, no functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-11 08:36:24 +01:00
Marek Vasut
d774197bb0 clk: renesas: Fix R-Car spelling
The correct spelling is R-Car, including the dash, update the usage.
Kconfig strings and comment changes only, no functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-11 08:36:24 +01:00
Marek Vasut
279d916b98 ARM: renesas: Fix R-Car spelling
The correct spelling is R-Car, including the dash, update the usage.
Kconfig strings and comment changes only, no functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-11 08:36:24 +01:00
Marek Vasut
c1b9d3eb88 ARM: dts: renesas: Fix R-Car spelling
The correct spelling is R-Car, including the dash, update the usage.
Comment change only, no functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-11 08:36:24 +01:00
Venkatesh Yadav Abbarapu
0e24474cc3 usb: onboard-hub: Update the bind function based on peer-hub property
As the "peer-hub" property is optional, don't error out just
skip the bind function.

Fixes: 57e30b09fc ("usb: onboard-hub: Bail out if peer hub is already probed")
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Tested-by: Patrice Chotard <patrice.chotard@foss.st.com>
2024-12-11 08:22:17 +01:00
Tom Rini
b841e559cd Prepare v2025.01-rc4
Signed-off-by: Tom Rini <trini@konsulko.com>
2024-12-09 16:09:28 -06:00
Tom Rini
497353969e Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh 2024-12-09 08:46:33 -06:00
Marek Vasut
455e66bc59 arm64: renesas: Disable AVB1 and AVB2 on R8A779G0 V4H White Hawk board
The U-Boot is currently not capable of handling ethernet-phy-ieee802.3-c45
PHYs correctly, and also does not handle MDIO bus wide reset-gpios property.
Until proper C45 PHY support lands in U-Boot, disable AVB1/AVB2 interfaces.
This only disables the two MACs with 88Q2110/88Q2112 100/1000BASE-T1 PHYs
on ethenet sub-board, the main board AVB0 ethernet is unaffected.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-08 23:07:34 +01:00
Paul Barker
3a735cff5f pinctrl: rzg2l: Drop unnecessary scope
In rzg2l_pinconf_set(), there are no new variables defined in the case
statement for PIN_CONFIG_INPUT_ENABLE so no additional scope is needed.

Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-08 23:06:52 +01:00
Paul Barker
bba516a772 pinctrl: rzg2l: Support Ethernet TXC output enable
On the RZ/G2L SoC family, the direction of the Ethernet TXC/TX_CLK
signal is selectable to support an Ethernet PHY operating in either MII
or RGMII mode. By default, the signal is configured as an input and MII
mode is supported. The ETH_MODE register can be modified to configure
this signal as an output to support RGMII mode.

As this signal is be default an input, and can optionally be switched to
an output, it maps neatly onto an `output-enable` property in the device
tree.

Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-08 23:06:52 +01:00
Paul Barker
215663f5e4 pinctrl: rzg2l: Support 2.5V PVDD for Ethernet interfaces
The Ethenet interfaces on the Renesas RZ/G2L SoC family can operate at
multiple power supply voltages: 3.3V (default value), 2.5V and 1.8V.

rzg2l_pinconf_set() is extended to support the 2.5V setting, with a
check to ensure this is only used on Ethernet interfaces as it is not
supported on the SD & QSPI interfaces.

While we're modifying rzg2l_pinconf_set(), drop the unnecessary default
value for pwr_reg as it is set in every branch of the following if
condition.

Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-08 23:06:52 +01:00
Paul Barker
2b1a5efca8 net: ravb: Simplify max-speed handling in ravb_of_to_plat
We can call dev_read_u32_default() instead of calling fdt_getprop() then
fdt32_to_cpu().

Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-08 23:06:52 +01:00
Paul Barker
9a699a0a0d clk: rzg2l: Ignore enable for core clocks
In the RZ/G2L family, core clocks are always on and can't be disabled.
However, drivers which are shared with other SoCs may call clk_enable()
or clk_enable_bulk() for a clock referenced in the device tree which
happens to be a core clock on the RZ/G2L. To avoid the need for
conditionals in these drivers, simply ignore attempts to enable a core
clock.

Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-08 23:06:52 +01:00
Ilias Apalodimas
45f05f6812 mbedtls: remove MBEDTLS_HAVE_TIME
When MbedTLS TLS features were added MBEDTLS_HAVE_TIME was defined as part
of enabling https:// support. However that pointed to the wrong function
which could crash if it received a NULL pointer.

Looking closer that function is not really needed, as it only seems to
increase the RNG entropy by using 4b of the current time and date.
The reason that was enabled is that lwIP was unconditionally requiring it,
although it's configurable and can be turned off.

Since lwIP doesn't use that field anywhere else, make it conditional and
disable it from our config.

Fixes: commit a564f5094f ("mbedtls: Enable TLS 1.2 support")
Reported-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
2024-12-06 17:47:23 -06:00
Vincent Stehlé
1f40dbad60 arm: qemu: fix update_info declaration
Add a missing comma in the update_info structure declaration.

This fixes the following build error when building with
EFI_RUNTIME_UPDATE_CAPSULE or EFI_CAPSULE_ON_DISK:

  board/emulation/qemu-arm/qemu-arm.c:52:9: error: request for member ‘images’ in something not a structure or union

Fixes: cccea18813 ("efi_loader: add the number of image entries in efi_capsule_update_info")
Signed-off-by: Vincent Stehlé <vincent.stehle@arm.com>
Cc: Masahisa Kojima <masahisa.kojima@linaro.org>
Cc: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Cc: Tom Rini <trini@konsulko.com>
2024-12-06 17:47:23 -06:00
Heinrich Schuchardt
c7401fc1d9 net: disable MBEDTLS in SPL
Building SPL fails with MBEDTLS enabled.
Currently we don't need it there.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
2024-12-06 17:47:23 -06:00
Heinrich Schuchardt
1ac2838350 rtc: CONFIGS_RTC_PL031 must depend on CONFIGS_DM_RTC
Building qemu_arm64_defconfig with CONFIGS_DM_RTC=n and CONFIGS_RTC_PL031=y
leads to a build failure.

Adjust the vexpress64 configuration to avoid circular dependency.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-12-06 17:47:23 -06:00
Sughosh Ganu
1a48b0be93 lmb: prohibit allocations above ram_top even from same bank
There are platforms which set the value of ram_top based on certain
restrictions that the platform might have in accessing memory above
ram_top, even when the memory region is in the same DRAM bank. So,
even though the LMB allocator works as expected, when trying to
allocate memory above ram_top, prohibit this by marking all memory
above ram_top as reserved, even if the said memory region is from the
same bank.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Tested-by: Andreas Schwab <schwab@suse.de>
2024-12-06 17:47:23 -06:00
Tom Rini
ef9574da96 configs: Resync with savedefconfig
Resync all defconfig files using qconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2024-12-06 17:47:16 -06:00
Tom Rini
448add5529 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-pmic
CI: https://source.denx.de/u-boot/custodians/u-boot-pmic/-/pipelines/23718

- Correct a few debug/error print calls
2024-12-05 08:11:35 -06:00
Tom Rini
ac3428fcc7 Merge tag 'efi-master-05122024' of https://source.denx.de/u-boot/custodians/u-boot-tpm
CI: https://source.denx.de/u-boot/custodians/u-boot-tpm/-/pipelines/23719

Two fixes for the EFI subsystem coming via the TPM tree as agreed by Heinrich

The LMB patch fixes a failure in SystemReady testing. Nothing bad happens
without the patch in the device operation, but the return values are wrong
and SCT tests fail for MemoryAllocationServicesTest category.

The second is a shielding the device against mistakes in the definition of
struct fields needed by the capsule update mechanism. Instead of crashing,
print a humna readable message of what's wrong.
2024-12-05 08:10:51 -06:00
Ilias Apalodimas
1d9aa4a283 lmb: Fix the allocation of overlapping memory areas with !LMB_NONE
At the moment the LMB allocator will return 'success' immediately on two
consecutive allocations if the second one is smaller and the flags match
without resizing the reserved area.

This is problematic for two reasons, first of all the new updated
allocation won't update the size and we end up holding more memory than
needed, but most importantly it breaks the EFI SCT tests since EFI
now allocates via LMB.

More specifically when EFI requests a specific address twice with the
EFI_ALLOCATE_ADDRESS flag set, the first allocation will succeed and
update the EFI memory map. Due to the LMB behavior the second allocation
will also succeed but the address ranges are already in the EFI memory
map due the first allocation. EFI will then fail to update the memory map,
returning EFI_OUT_OF_RESOURCES instead of EFI_NOT_FOUND which break EFI
conformance.

So let's remove the fast check with is problematic anyway and leave LMB
resize and calculate address properly. LMB will now
- try to resize the reservations for LMB_NONE
- return -1 if the memory is not LMB_NONE and already reserved

The LMB code needs some cleanup in that part, but since we are close to
2025.01 do the easy fix and plan to refactor it later.
Also update the dm tests with the new behavior.

Fixes: commit 22f2c9ed9f ("efi: memory: use the lmb API's for allocating and freeing memory")
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-12-05 09:01:44 +02:00
Ilias Apalodimas
05396fb724 efi_loader: Check for a valid fw_name before auto generating GUIDs
The gen_v5_guid() is a void and does no error checking with pointers
being available etc. Instead it expects all things to be in place to
generate GUIDs. If a board capsule definition is buggy and does not
define the firmware names when enabling capsule updates, the board will
crash trying to bring up the EFI subsystem.

Check for a valid firmware name before generating GUIDs.

Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-12-05 09:01:33 +02:00
Patrice Chotard
74cd1af112 power: regulator: replace dev_dbg() by dev_err() in regulator_post_bind()
To ease debugging, use dev_err() instead of dev_dbg() for
alerting when regulator has nonunique value.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2024-12-05 07:31:31 +09:00
Patrice Chotard
ccddb0abec power: regulator: replace some debug() by dev_dbg()
Replace some debug() by dev_dbg() when dev variable
is available/valid.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2024-12-05 07:31:21 +09:00
Tom Rini
f96e513318 Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-samsung 2024-12-03 12:37:20 -06:00
Sam Protsenko
0bbc17f06b configs: e850-96: Disable PSCI reset
PSCI reset is not implemented in Exynos850 EL3 firmware. Disable it to
fix the reset in cases where it can be used, e.g. when running EFI
selftest.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2024-12-03 15:14:53 +09:00
Evgeny Bachinin
acab6e78ac common: relocate fdt_blob in global_data for FDTSRC_EMBED case
Patch resolves two kind of bugs, one of which is vulnerability related
to KASLR.

=== Issue briefly ===

  Working with FDT (via non-relocated gd::fdt_blob) from inside bootm
command may lead to the reading the garbage instead of FDT nodes. And
this can result in various side-effects depending on DTS nodes, being
parsed during bootm.

  But below is my specific story how I faced with this issue due to
MESON_RNG probing failure.

=== Bugs description ===

1) Bug is revealed on:
* configuration below
* U-boot 2024.10 - f919c3a889 ("Prepare v2024.10")

  It seems, the following patch is a trigger:
ea955eea4f ("fdt: automatically add /chosen/kaslr-seed if DM_RNG is enabled")

  Generally, CONFIG_OF_EMBED=y & CONFIG_RNG_MESON=y are the most
valuable ones for reproducing the issue.
```
  CONFIG_ARCH_FIXUP_FDT_MEMORY=y
  CONFIG_CMD_FDT=y
  CONFIG_DEFAULT_FDT_FILE=""
  CONFIG_FDT_64BIT=y
  CONFIG_OF_BOARD_SETUP=y
  CONFIG_OF_CONTROL=y
  CONFIG_OF_EMBED=y
  CONFIG_OF_LIBFDT_ASSUME_MASK=0x0
  CONFIG_OF_LIBFDT_OVERLAY=y
  CONFIG_OF_LIBFDT=y
  CONFIG_OF_LIST="meson-axg-our-device-name"
  CONFIG_OF_REAL=y
  CONFIG_OF_TRANSLATE=y
  CONFIG_SUPPORT_OF_CONTROL=y
  CONFIG_SYS_FDT_PAD=0x3000
  CONFIG_TOOLS_OF_LIBFDT=y

  CONFIG_DM_RNG=y
  CONFIG_RNG_MESON=y
```

2) Due to CONFIG_OF_EMBED, the DTS is embedded into U-boot ELF and
accessible via __dtb_dt_begin symbol.

  On early boot stage (board_f.c) the fdtdec_setup() is called only
once before U-boot's relocation into top of RAM. fdtdec_setup()
initializes gd::fdt_blob for FDTSRC_EMBED case:
```
  gd->fdt_blob = dtb_dt_embedded();
  gd->fdt_src = FDTSRC_EMBED;
```

3) Then reloc_fdt() is called in board_f.c

  But due to CONFIG_OF_EMBED=y the reloc_fdt() does not update
gd::fdt_blob value (strictly speaking, it is impossible for
CONFIG_OF_EMBED=y, because U-boot ELF has not been relocated yet
at this moment).

  As a result after relocation we get fdt_blob, pointing to DTS address
before relocation:
```
   # bdinfo
  <...>
  relocaddr = 0x000000000fedf000
  reloc off = 0x000000000eedf000
  <...>
  fdt_blob = 0x010ce6c0 << points to __dtb_dt_begin before relocation
  new_fdt = 0x0000000000000000  << empty erroneously
  fdt_size = 0x0000000000000000 << zero erroneously
```

4) During bootm command (according to our ITS-config file) the Linux
is loaded into 0x01080000 (which is very close to fdt_blob addr
0x010ce6c0).
```
  ## Loading kernel from FIT Image at 04000000 ...
     Trying 'kernel' kernel subimage
       <...>
       Load Address: 0x01080000
```

  So Linux image overwrites the gd::fdt_blob memory location
in RAM (0x010ce6c0).

5) Issue:

  Hence any manipulation with DTS (say, via FDT API) inside
implementation of bootm command leads to accessing the fdt_blob area
with garbage, that can lead to two situations:

5.1) Abort.

  Call to fdt_off_dt_struct() from fdt_next_tag() :: fdt_offset_ptr()::
fdt_offset_ptr_() returns with garbage, that leads to tagp value
being out of RAM top addr (256 Mb in our board), causing the abort:
```
  Boot cmd: bootm 0x4000000#boot_evt1
  bootm_run_states()
  <...>
  image_setup_libfdt()
   fdt_chosen()
    fdt_kaslrseed()
     uclass_get_device()
      uclass_get_device_tail()
       device_probe()
        device_of_to_plat()
        meson_rng_of_to_plat()
         clk_get_by_name_optional()
          clk_get_by_name()
           clk_get_by_name_nodev()
            ofnode_stringlist_search()
             fdt_stringlist_search()
              fdt_getprop()
               fdt_get_property_namelen_()
                fdt_first_property_offset()
                 fdt_check_node_offset_()
                  fdt_next_tag():
                    ```
                      tagp = fdt_offset_ptr(fdt, offset, FDT_TAGSIZE);
                    ```
                  fdt_next_tag() tagp:0x22890766
                  fdt_next_tag() ram_top:0x10000000 (tagp OUT of RAM)
  "Synchronous Abort" handler, esr 0x96000010, far 0x22890766
  elr: 000000000108be24 lr : 000000000108be24 (reloc)
  elr: 000000000ff6fe24 lr : 000000000ff6fe24
  x0 : 0000000000000041 x1 : 0000000000000000
  x2 : 000000000ff3b57c x3 : 0000000000000012
  x4 : 000000000ded2ad5 x5 : 0000000000000020
  x6 : 00000000ffffffe8 x7 : 000000000ded2f40
  x8 : 00000000ffffffd8 x9 : 000000000000000d
  x10: 0000000000000006 x11: 000000000001869f
  x12: 000000000fffffff x13: 000000000fffffff
  x14: 0000000000000000 x15: 000000000ded2abb
  x16: 000000000ff3b080 x17: 0000000000000001
  x18: 000000000ded3dc0 x19: 0000000022890766
  x20: 00000000010cb0f0 x21: 00000000000015e4
  x22: 000000000ff8f4d8 x23: 000000000000000b
  x24: 000000000ded2fbc x25: 000000000ffe2000
  x22: 000000000ff8f4d8 x23: 000000000000000b
  x24: 000000000ded2fbc x25: 000000000ffe2000
  x26: 000000000ffe2000 x27: 000000000000000b
  x28: 000000000ff9cf2d x29: 000000000ded2f40

  Code: aa1603e1 91197484 52801742 94004de8 (b9400276)
```

5.2) Vulnerability situation "KASLR is disabled".

Almost the same as in (5.1), but 2 situations happen (depending on
the value of garbage):
  * call to fdt_offset_ptr_() :: fdt_off_dt_struct(fdt)
    returns not so big garbage, leading to tagp, being inside RAM.
  * or calculations of absoffset inside fdt_offset_ptr() leads to
    failure of the one of if() conditions with NULL as retval.

  Result is fdt_next_tag() interprets the tagp as FDT_END. And we are
returning from our callstack via functions' error paths, leading to
"No RNG device" and "KASLR disabled due to lack of seed":
```
  fdt_kaslrseed()
   uclass_get_device()
   <...>
    device_probe()
     device_of_to_plat()
      meson_rng_of_to_plat()
       clk_get_by_name()
        clk_get_by_name_nodev()
        <...>
         fdt_stringlist_search()
          fdt_getprop()
           fdt_get_property_namelen_()
            fdt_first_property_offset()
             fdt_check_node_offset_()
              fdt_next_tag():
                ```
                  tagp = fdt_offset_ptr(fdt, offset, FDT_TAGSIZE);
                ```
              fdt_next_tag() tagp:0000000001890677
              fdt_next_tag() ram_top:0x10000000 (tagp is inside RAM)
      uclass_get_device_tail():486 device_probe() ret:-22
  No RNG device
 Starting kernel ...

  [ 0.000000] Linux version 6.9.12
  [ 0.000000] KASLR disabled due to lack of seed
```

Signed-off-by: Evgeny Bachinin <EABachinin@salutedevices.com>
2024-12-02 07:48:28 -06:00
Simon Glass
924a5e4e41 Revert "global_data: Drop spl_handoff"
This breaks chromebook_coral which says:

   Video: No video mode configured in FSP!

This reverts commit 2e9313179a.

Signed-off-by: Simon Glass <sjg@chromium.org>
2024-12-02 07:40:39 -06:00
Simon Glass
03e57244bc binman: Avoid skipping binman_init()
A recent lwip change stopped binman's init from working, so it is not
possible to read nodes from the image description anymore.

Correct this by dropping the offending line.

Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: 4d4d783812 net: lwip: add TFTP support and tftpboot command
2024-12-02 07:40:30 -06:00
Rasmus Villemoes
12fcb98257 powerpc/t2080qds: remove spurious x permission from README file
It doesn't make sense for a README file to be executable. Remove that
bit.

Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
2024-11-30 12:46:34 -06:00
Rasmus Villemoes
6e3e72ed4e arm: dts: socfpga: remove spurious execute permission from dt files
It doesn't make sense for these files to have the x bit set. It was,
probably accidentally, added in:

Fixes: 2c494e62c3 (arm: dts: Stratix10: Add QSPI node)
Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
2024-11-30 12:46:30 -06:00
Mark Kettenis
57b6fb7eb1 Makefile: avoid non-standard sed expressions
The '?' that is used in the sed expression that determines MK_ARCH
is part of the extended regular expression syntax, but the default
behaviour of sed as specified by POSIX is to use only basic regular
expression syntax.  Use the equivalent '\{0,1\}' instead as
suggested by the OpenBSD re_format(7) man page.

Fixes: 04b1d84221 ("Makefile: fix empty MK_ARCH when using ccache")
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Tested-by: Quentin Schulz <quentin.schulz@cherry.de>
2024-11-30 11:57:08 -06:00
Jerome Forissier
a37064cb2e net: lwip: wget: fix legacy syntax
Commit 356011f7ac ("lwip: fix code style issues") has inadvertently
broken the support for the legacy syntax:

 => wget 192.168.0.16:test.bin
 invalid uri, no file path
 Invalid URL. Use http(s)://

The reason is two calls to strncpy() were replaced by strlcpy() without
paying attention to the fact that they are not equivalent in the present
case. Since we are using a character counter (n) and since we do not
depend on having a properly null-terminated string at each step in the
parsing, strlcpy() is not justified and strncpy() is the right tool for
the job. So use it again.

Reported-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
2024-11-30 11:52:47 -06:00
Ilias Apalodimas
65b38a519b Revert "efi_memory: do not add U-Boot memory to the memory map"
This reverts commit ("commit a68c9ac5d8 ("efi_memory: do not add
U-Boot memory to the memory map").

This code was removed when the EFI subsystem started using LMB calls for
the reservations. In hindsight it unearthed two problems.

The e820 code is adding u-boot memory as EfiReservedMemory while it
should look at what LMB added and decide instead of blindly overwriting
it. The reason this worked is that we marked that code properly late,
when the EFI came up. But now with the LMB changes, the EFI map gets
added first and the e820 code overwrites it.

The second problem is that we never mark SetVirtualAddressMap as runtime
code, which we should according to the spec. Until we fix this the
current hack can't go away, at least for architectures that *need* to
call SVAM.

More specifically x86 currently requires SVAM and sets the NX bit for
pages not marked as *_CODE. So unless we do that late, it will crash
trying to execute from non-executable memory. It's also worth noting
that x86 calls SVAM late in the boot, so this will work until someone
decides to overwrite/use BootServicesCode from the OS.

Notably arm64 disables it explicitly if the VA space is > 48bits, so
doesn't suffer from any of these problems.

This doesn't really deserve a fixes tag, since it brings back a hack to
remedy a situation that was wrong long before that commit, but in case
anyone hits the same bug ...
Simon sent the original revert in the link, but we need a proper
justification for it.

Link: https://lore.kernel.org/u-boot/20241112131830.576864-1-sjg@chromium.org/
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Acked-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reported-by: Simon Glass <sjg@chromium.org>
2024-11-30 08:37:53 -06:00
Tom Rini
bf3dfb405b Merge tag 'u-boot-imx-master-20241130' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/23643

- Make DRAM coding GPIOs available before relocation on Data Modul
  i.MX8M Mini/Plus eDM SBC because the DRAM configuration GPIO straps
  must be accessible in SPL and before relocation because the GPIOs are
  sampled both in U-Boot SPL as well as early on in U-Boot proper.
- Pick safe DRAM size on failure on Data Modul i.MX8M Mini/Plus eDM SBC
  instead of failing with hang() or panic().
- Replace YModem with SDP on Data Modul i.MX8M Mini eDM SBC SPL since
  SDP is much more flexible.
- Deduplicate Data Modul i.MX8M eDM SBC defconfigs.
- Perform plain boot in altbootcmd on Data Modul i.MX8M Mini/Plus eDM
  SBC.
2024-11-30 08:34:45 -06:00
Jerome Forissier
20f641987f test/cmd/wget.c: move net_test_wget() to the cmd test suite
Since net_test_wget() is testing a command and is in test/cmd it should
be in the 'cmd' test suite, not 'lib'.

Saving and restoring the values of the environment variables that the
test manipulates is necessary to avoid a regression when running the
whole ut test suite. A minimal reproducer is:

 $ ./u-boot -T -c "ut cmd net_test_wget; ut dm dm_test_eth_act" | \
     grep -E "(Test:|Failures:)"

Reported-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
2024-11-29 07:51:57 -06:00
Tom Rini
6ceb861882 Revert "arm64: dts: ti: k3-j7200: Fix OSPI boot"
While I had thought this commit was a cherry-pick from upstream, it is
not. And so, this is not allowed here.

This reverts commit dfe5f16a33.

Signed-off-by: Tom Rini <trini@konsulko.com>
2024-11-29 07:50:33 -06:00
Marek Vasut
4835efca7a ARM: dts: imx: Enable PCIe and NVMe on Data Modul i.MX8M Mini eDM SBC
Enable PCIe/NVMe support on Data Modul i.MX8M Mini eDM SBC. Except for
the configuration options which are enabled, add slight adjustment
to board u-boot.dtsi, which is necessary as there is currently no
driver for the I2C PCIe clock generator. Since the generator is
strapped to be always on, it is possible to supplant the generator
functionality by fixed-clock.

Signed-off-by: Marek Vasut <marex@denx.de>
2024-11-29 09:20:47 -03:00
Marek Vasut
0b97a394f6 ARM: imx: Replace YModem with SDP on Data Modul i.MX8M Mini eDM SBC SPL
The YModem support in SPL was never really used on this device,
the SDP support is much more convenient on i.MX8M Mini based
hardware. Replace the YModem support with SDP support.

The SDP can be utilized by forcing the board into SDP boot mode
by grounding test point right next to silkscreen label U30, and
then by using mfgtools 'uuu -brun spl flash.bin' once the device
enumerates on host system USB bus. The SDP capable USB port is
available on the USB micro-B port on the base board.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2024-11-29 09:20:25 -03:00
Marek Vasut
3a689038bf ARM: imx: Deduplicate Data Modul i.MX8M eDM SBC defconfigs
Deduplicate defconfigs for all Data Modul i.MX8M eDM SBC systems by factoring
out the common parts into generic imx8m_data_modul.config and including
those using the #include <configs/...> preprocessor macro in the current
set of board specific defconfigs. The preprocessor macro is applicable
to defconfigs as well.

This introduces no functional change, the resulting .config is almost
identical for all Data Modul i.MX8M eDM SBC systems, except for slight
alignment in DEBUG_UART and SYS_PBSIZE.

Signed-off-by: Marek Vasut <marex@denx.de>
2024-11-29 09:19:00 -03:00
Marek Vasut
ec3e5fa55d ARM: imx: Perform plain boot in altbootcmd on Data Modul i.MX8M Mini/Plus eDM SBC
The current A/B switching preparatory altbootcmd is confusing
to users, replace it with plain 'run bootcmd' which can be
replaced by proper A/B switching altbootcmd when the matching
updater is added on top of the platform. By default, keep the
boot counter incrementing, but do not do any A/B partition
switching.

Signed-off-by: Marek Vasut <marex@denx.de>
2024-11-29 09:19:00 -03:00
Marek Vasut
1171adfd89 ARM: dts: imx: Pick safe DRAM size on failure on Data Modul i.MX8M Mini/Plus eDM SBC
In case gpio_request_list_by_name_nodev() in board dmo_get_memcfg()
returns error code, pick a safe default DRAM configuration instead
of bailing out with some sort of hang() or panic(). The BIT(2)|BIT(0)
strap option is the lowest known option of 2 GiB , use that.

Signed-off-by: Marek Vasut <marex@denx.de>
2024-11-29 09:19:00 -03:00
Marek Vasut
6e18eec908 ARM: dts: imx: Make DRAM coding GPIOs available before relocation on Data Modul i.MX8M Mini/Plus eDM SBC
The DRAM configuration GPIO straps must be accessible in SPL and before
relocation because the GPIOs are sampled both in U-Boot SPL as well as early
on in U-Boot proper. The already present bootph-pre-ram DT property made the
GPIO controllers available in SPL, but not early on in U-Boot proper, which
made gpio_request_list_by_name_nodev() in board dmo_get_memcfg() fail. Add
missing bootph-some-ram DT property to all GPIO controllers which are
referenced in dmo,ram-coding-gpios DT property to make those GPIO
controllers available early in U-Boot proper as well.

Fixes: 8c103c33fb ("dm: dts: Convert driver model tags to use new schema")
Signed-off-by: Marek Vasut <marex@denx.de>
2024-11-29 09:19:00 -03:00
Tom Rini
b51b97e9be Merge https://source.denx.de/u-boot/custodians/u-boot-riscv
CI: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/23592

- some configs modification
2024-11-27 07:34:17 -06:00
Tom Rini
931122add7 Merge branch 'u-boot-nand-20241126' of https://source.denx.de/u-boot/custodians/u-boot-nand-flash
CI: https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/pipelines/23584

Remove device specific nand driver files as they are now replaced by a
common driver bcmbca_nand.c

Make use of OF_UPSTREAM which uses Linux dts.

Implement a minimal set of defconfig options to enable basic NAND
functionality. Tested on:
47622
63146
63158
63178
6813

Set parameter_page_big_endian to zero for bcmbca.

Update log level messages so that more critical messages can be logged
to console and help the troubleshooting with field devices.
2024-11-27 07:33:06 -06:00
Yuri Zaporozhets
bdca70632d configs: enable CONFIG_PCI_REGION_MULTI_ENTRY=y in sifive_unmatched_defconfig
Currently, the PCI subsystem selects the small "region 2" (which starts at 0x7000000)
as bus_addr/phys_addr. As a consequence, the BAR0 on PCIe video card cannot be initialized,
because it simply doesn't fit into 0x1000000 bytes size of "region 2".

U-Boot should use "region 1" instead (the one which starts at 0x60090000), because
it has much bigger size (0xFF70000), and easily accomodates BAR0 of the video card.
Linux kernel also uses 0x60090000 as bus_start/phys_start.

Signed-off-by: Yuri Zaporozhets <yuriz@vodafonemail.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-11-27 19:58:08 +08:00
Andreas Schwab
185986caeb configs: visionfive2: re-enable SPL_SYS_MMCSD_RAW_MODE
To restore MMC boot, enable SPL_SYS_MMCSD_RAW_MODE and recover
SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION and
SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION.

Fixes: 2a00d73d08 ("spl: mmc: Try to clean up raw-mode options")
Signed-off-by: Andreas Schwab <schwab@suse.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-11-27 19:32:56 +08:00
Heinrich Schuchardt
afc52da894 configs: SiFive Unmatched: enable 'env erase' sub-command
With the move from script based booting to using bootmeth a lot of
environment variables have changed. To always use the default environment
it is recommendable to erase the environment stored in the SPI flash.
This can be done with the 'env erase' sub-command.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-11-27 19:31:29 +08:00
Yuri Zaporozhets
91bc909d31 spl: increase SPL_SYS_MALLOC_SIZE when using BIOSEMU on RISC-V
If BIOSEMU is compiled for RISC-V (SiFive Unmatched board) and the function
dm_pci_run_vga_bios() is executed, U-Boot stops with error message saying
that the SPL malloc pool is too small. So increase the default pool size
when both BIOSEMU and RISCV parameters are set.

Signed-off-by: Yuri Zaporozhets <yuriz@qrv-systems.net>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-11-27 19:31:10 +08:00
david regan
5b70f26fed mtd: rawnand: brcmnand: update log level messages
Update log level messages so that more critical messages can be logged
to console and help the troubleshooting with field devices.

This is a port of the upstream Linux patch to U-Boot.

https://lore.kernel.org/linux-mtd/20240223034758.13753-4-william.zhang@broadcom.com/

Signed-off-by: david regan <dregan@broadcom.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: William Zhang <william.zhang@broadcom.com>
Reviewed-by: Anand Gore <anand.gore@broadcom.com>
2024-11-26 21:14:44 +01:00
david regan
a4f72e8b6e mtd: rawnand: brcmnand: Default bcmbca parameter_page_big_endian to zero
Set parameter_page_big_endian to zero for bcmbca

Signed-off-by: david regan <dregan@broadcom.com>
Reviewed-by: William Zhang <william.zhang@broadcom.com>
Reviewed-by: Anand Gore <anand.gore@broadcom.com>
2024-11-26 21:14:44 +01:00
david regan
67e52b59a2 arm: dts: Use upstream dts
Make use of OF_UPSTREAM which uses Linux dts.

Signed-off-by: david regan <dregan@broadcom.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: William Zhang <william.zhang@broadcom.com>
Reviewed-by: Anand Gore <anand.gore@broadcom.com>
2024-11-26 21:14:44 +01:00
david regan
a2fa53be4f mtd: nand: brcmnand: remove device specific nand driver files
These device specific nand driver files can be removed because
they are now replaced by a common driver bcmbca_nand.c

Signed-off-by: david regan <dregan@broadcom.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: William Zhang <william.zhang@broadcom.com>
Reviewed-by: Anand Gore <anand.gore@broadcom.com>
2024-11-26 21:14:44 +01:00
Tom Rini
3881c6b903 configs: Resync with savedefconfig
Rsync all defconfig files using qconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2024-11-26 08:17:35 -06:00
Tom Rini
9e66cb41ee Merge tag 'u-boot-dfu-20241126' of https://source.denx.de/u-boot/custodians/u-boot-dfu
CI: https://source.denx.de/u-boot/custodians/u-boot-dfu/-/pipelines/23572

- Fastboot:
  - handle unknown partition type as "raw"
- USB gadget:
  - Fix ci_udc gadget driver for Tegra 2 devices by not using USBADRA
2024-11-26 08:05:11 -06:00
Tom Rini
6b96e01d70 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-marvell
CI: https://dev.azure.com/sr0718/u-boot/_build/results?buildId=379&view=results

- mvebu: Disable JFFS2 support for Kirkwood and Armada XP boards (Tony)
- kirkwood: Enable bootstd for Sheevaplug board (Tony)
- mvebu: Add Allied Telesis x250 board (Chris)
- mvebu: Updates for Allied Telesis boards (Chris)
2024-11-26 08:04:44 -06:00
Chris Packham
7446e29db5 arm: mvebu: Add Allied Telesis x250 board
The x250 and SE250 are series of 10G L2+ switches from Allied Telesis.
There are a number of them in the range but as far as U-Boot is
concerned all the CPU block components are the same so there's only one
board defined.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2024-11-26 13:20:03 +01:00
Chris Packham
f337b5aaad arm: mvebu: x530: Enable IPV6 support
Enable IPV6 support for the x530 board.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2024-11-26 13:20:03 +01:00
Chris Packham
c6b17af142 arm: mvebu: x530: Don't build mkeficapsule
The x530 board doesn't use EFI and our toolchains don't include gnutls
so disable the tool in the defconfig.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2024-11-26 13:20:03 +01:00
Chris Packham
1b46176532 arm: mvebu: x530: Remove dead comments
As things have been moved to Kconfig there are a number of dead comments
left over in x530.h. Remove them.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2024-11-26 13:20:03 +01:00
Chris Packham
b25b2d4f67 arm: mvebu: x240: Enable IPV6 support
Enable IPV6 support for the x240 board.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2024-11-26 13:20:03 +01:00
Chris Packham
cbbfa8d778 arm: mvebu: x240: Don't build mkeficapsule
The x240 board doesn't use EFI and our toolchains don't include gnutls
so disable the tool in the defconfig.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2024-11-26 13:20:02 +01:00
Chris Packham
27b2488735 arm: mvebu: x240: Switch to standard boot
Use standard boot instead of the distro boot scripts. Regenerate the
board defconfig now that some options are selected automatically.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2024-11-26 13:20:00 +01:00
Chris Packham
3eef899b57 arm: mvebu: x240: Use default baudrate table
Remove CFG_SYS_BAUDRATE_TABLE as there's no reason not to use the
defaults defined via config_fallbacks.h.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2024-11-26 13:19:55 +01:00
Tony Dinh
96ca314798 arm: kirkwood: Enable bootstd for Sheevaplug board
Enable bootstd for Sheevaplug board.
Remove JFFS2 support. See JFFS2 Vulnerability[1].
Enable LTO to keep board size within limit.
Move default envs to text-base environment

[1] https://lore.kernel.org/u-boot/20241114233005.GN3600562@bill-the-cat/T/#m2fc25da1d2c019bc3cd8676991fdd64b8a21aa9b

Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2024-11-26 13:19:48 +01:00
Tony Dinh
325ac6c1e7 arm: mvebu: Disable JFFS2 support for Kirkwood and Armada XP boards
These boards don't use JFFS2 file system for booting so remove it.

Ref: https://lore.kernel.org/u-boot/20241114233005.GN3600562@bill-the-cat/T/#t
Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Acked-by: Phil Sutter <phil@nwl.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
2024-11-26 13:19:42 +01:00
Ion Agorria
35d967f5a8 usb: ci_udc: don't use "advance" feature when setting address
In the older USB controllers like for example in ChipIdea controller
used by the Tegra 2 the "USBADRA: Device Address Advance" bitflag
does not exist, so the new device address set during SET_ADDRESS
can't be deferred by hardware, which causes the host to not recognize
the device and give an error.

Instead store it until ep completes to apply the change into the hw
register as Linux kernel does. This should fix regression on old and
and be compatible with newer controllers.

Inspired by: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=ef15e5490edc7edf808d3477ab32e0e320792f65

Signed-off-by: Ion Agorria <ion@agorria.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Link: https://lore.kernel.org/r/20241126072956.64778-2-clamor95@gmail.com
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2024-11-26 09:56:03 +01:00
Tom Rini
3073246d1b Prepare v2025.01-rc3
Signed-off-by: Tom Rini <trini@konsulko.com>
2024-11-25 16:59:13 -06:00
Tom Rini
b71edd464f Merge branch 'master-asix' of https://source.denx.de/u-boot/custodians/u-boot-usb
- Fix two issues with the asix88179 driver
2024-11-25 15:32:16 -06:00
Dominik Wernberger
1420c75914 spi: Fix missed rename from SPI_ADVANCE to SPI_STACKED_PARALLEL
Fix missed rename from SPI_ADVANCE to SPI_STACKED_PARALLEL. This fixes
an issue encountered while testing the Zynq-7000 QSPI parallel Flash
implementation.

Fixes: f896aa6567 ("mtd: spi-nor: Rename SPI_ADVANCE to SPI_STACKED_PARALLEL")
Reviewed-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Dominik Wernberger <dominik.wernberger@gmx.de>
2024-11-25 15:29:45 -06:00
Tom Rini
31cf17c61a Merge https://source.denx.de/u-boot/custodians/u-boot-usb
- Support for Microchip USB5744 hub
2024-11-25 13:12:19 -06:00
Joel Stanley
7327218681 ast2600: spl: Use readl for reading mmio
u-boot was crashing in qemu as the modeled hardware enforced overly
strict memory reads.

While this code will work on existing hardware, fix to avoid future issues.

Fixes: 12770d0df0 ("ast2600: spl: Add boot mode detection")
Link: https://gitlab.com/qemu-project/qemu/-/issues/2636
Signed-off-by: Joel Stanley <joel@jms.id.au>
2024-11-25 13:12:19 -06:00
Andy Shevchenko
c0e978b4b7 mtd: Drop superfluous const qualifier
The compiler will ignore it anyway:

  include/linux/mtd/mtd.h:342:15: warning: type qualifiers ignored on function return type [-Wignored-qualifiers]

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2024-11-25 13:12:19 -06:00
Khoa Hoang
05278af8b3 eth: asix88179: packet drop when receiving large fragmented packets
The ASIX 88179A drops packets when receiving fragmented packets larger
than the MTU size due to an insufficient URB buffer size. This change
synchronizes the URB buffer size with the configuration used in the
Linux kernel, resolving the packet drop issue.

To reproduce the issue, set the following configuration:
    CONFIG_IP_DEFRAG=y
    CONFIG_TFTP_BLOCKSIZE=16352

Then, run the `tftp` command. It will fail with a timeout error:

    U-Boot> tftp zero.bin
    Using ax88179_eth device
    TFTP from server 10.0.0.196; our IP address is 10.0.0.18
    Filename 'zero.bin'
    Load address: 0x10000000
    Loading: T T T T T T T T T T T
    Retry count exceeded; starting again

Signed-off-by: Khoa Hoang <admin@khoahoang.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2024-11-25 19:11:19 +01:00
Khoa Hoang
9713c15d2e eth: asix88179: Fix ASIX AX88179A PHY hang
The ASIX AX88179A locks up when the ADVERTISE_NPAGE bit is set in the
MII_ADVERTISE register, suggesting that this feature may be broken or
unsupported on this chip. In the Linux kernel, this bit is not set,
and enabling it also causes the PHY to lock up and stay in a
link-down state.

Additionally, the AX88179 and AX88179A variants do not appear to
support the ADVERTISE_LPACK bit, as setting it consistently reads
back as 0.

This patch removes the ADVERTISE_NPAGE and ADVERTISE_LPACK bits from
the MII_ADVERTISE register configuration. It also resets the PHY
before modifying the MII_ADVERTISE register, then restarts
auto-negotiation, following the same flow used in the U-Boot asix.c
driver.

Signed-off-by: Khoa Hoang <admin@khoahoang.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2024-11-25 19:11:19 +01:00
Venkatesh Yadav Abbarapu
57e30b09fc usb: onboard-hub: Bail out if peer hub is already probed
The .bind function is implemented to bind the correct
"half" of the hub that the driver wants to bind,
and returning -ENODEV for the other "half".

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2024-11-25 05:40:49 +01:00
Venkatesh Yadav Abbarapu
09f557e106 usb: onboard-hub: Add i2c initialization for usb5744 hub
Add i2c initialization hook and set usb5744 platform
data with function having required i2c initialization sequence.

Apart from the USB command attach, prevent the hub from suspend.
when the “USB Attach with SMBUS (0xAA56)” command is issued to the hub,
the hub is getting enumerated and then it puts in a suspend mode.
This causes the hub to NAK any SMBUS access made by the SMBUS Master
during this period and not able to see the hub's slave address while
running the "i2c probe" command.

Prevent the MCU from the putting the HUB in suspend mode through register
write. The BYPASS_UDC_SUSPEND bit (Bit 3) of the RuntimeFlags2 register at
address 0x411D controls this aspect of the hub. The BYPASS_UDC_SUSPEND
bit in register 0x411Dh must be set to ensure that the MCU is always
enabled and ready to respond to SMBus runtime commands. This register
needs to be written before the USB attach command is issued.
The byte sequence is as follows:
Slave addr: 0x2d           00 00 05 00 01 41 1D 08
Slave addr: 0x2d           99 37 00
Slave addr: 0x2d           AA 56 00

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2024-11-25 05:40:49 +01:00
Venkatesh Yadav Abbarapu
f9d96095e4 usb: onboard-hub: add support for Microchip USB5744
Add support for the Microchip USB5744 USB3.0 and USB2.0 Hub.
The usb5744 driver trigger hub reset signal after soft reset.
The usb5744 hub need to reset after the phy initialization,
which toggles the gpio.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2024-11-25 05:40:49 +01:00
Venkatesh Yadav Abbarapu
5fdce1fa17 usb: onboard-hub: Fix the return values of regulator APIs
Don't error out if there is no vdd regulator supply, as these are
optional properties.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2024-11-25 05:40:49 +01:00
Venkatesh Yadav Abbarapu
0e670e2917 usb: onboard-hub: Add reset-gpio support
As part of the reset, sets the direction of the pin to output before
toggling the pin. Delay of millisecond is added in between low and
high to meet the setup and hold time requirement of the reset.
Update the usb2514 hub_data with the reset delay and power on
delay values.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2024-11-25 05:40:49 +01:00
Tom Rini
880fcc49eb Merge patch series "Fix device removal order for Apple dart iommu"
Janne Grunau <j@jannau.net> says:

Starting with v2024.10 dev_iommu_dma_unmap calls during device removal
trigger a NULL pointer dereference in the Apple dart iommu driver. The
iommu device is removed before its user. The sparsely used DM_FLAG_VITAL
flag is intended to describe this dependency. Add it to the driver.

Adding this flag is unfortunately not enough since the boot routines
except the arm one simply remove all drivers. Add and use a new function
which calls
    dm_remove_devioce_flags(DM_REMOVE_ACTIVE_ALL | DM_REMOVE_NON_VITAL);
    dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL);
to ensure this order dependency is head consistently.

Link: https://lore.kernel.org/r/20241123-iommu_apple_dart_ordering-v2-0-cc2ade6dde97@jannau.net
2024-11-24 15:41:32 -06:00
Janne Grunau
dabaa4ae32 dm: Add dm_remove_devices_active() for ordered device removal
This replaces dm_remove_devices_flags() calls in all boot
implementations to ensure non vital devices are consistently removed
first. All boot implementation except arch/arm/lib/bootm.c currently
just call dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL). This can result
in crashes when dependencies between devices exists. The driver model's
design document describes DM_FLAG_VITAL as "indicates that the device is
'vital' to the operation of other devices". Device removal at boot
should follow this.

Instead of adding dm_remove_devices_flags() with (DM_REMOVE_ACTIVE_ALL |
DM_REMOVE_NON_VITAL) everywhere add dm_remove_devices_active() which
does this.

Fixes a NULL pointer deref in the apple dart IOMMU driver during EFI
boot. The xhci-pci (driver which depends on the IOMMU to work) removes
its mapping on removal. This explodes when the IOMMU device was removed
first.

dm_remove_devices_flags() is kept since it is used for testing of
device_remove() calls in dm.

Signed-off-by: Janne Grunau <j@jannau.net>
2024-11-24 15:41:28 -06:00
Janne Grunau
544a76bac3 iommu: apple: Mark device with DM_FLAG_VITAL
Avoids NULL pointer dereferences in apple_dart_unmap when the iommu
device is removed before its user. U-boot's device model does not track
dependencies between devices.
Observed on a M1 Ultra Mac Studio with v2024.10.

Acked-by: Mark Kettenis <kettenis@openbsd.org>
Signed-off-by: Janne Grunau <j@jannau.net>
2024-11-24 15:41:28 -06:00
Tom Rini
6c791b6646 Merge tag 'efi-2025-01-rc3' of https://source.denx.de/u-boot/custodians/u-boot-efi
CI: https://source.denx.de/u-boot/custodians/u-boot-efi/-/pipelines/23529

- Documentation:
  - Document wget syntax enhancements with lwIP network stack
  - Move README.kconfig to HTML documentation
  - Remove redundant README.TPL
- UEFI:
  - Simplify efi_tcg2_hash_log_extend_event()
  - Allow EFI_LOADER_BOUNCE_BUFFER on all architectures
  - Correctly unmap and free memory on errors
- Other:
 - Enable EFI_LOADER_BOUNCE_BUFFER on StarFive VisionFive 2
2024-11-24 09:37:32 -06:00
Ilias Apalodimas
967d57ab59 lmb: Correctly unmap and free memory on errors
We never free and unmap the memory on errors and we never unmap it when
freeing it. The latter won't cause any problems even on sandbox, but for
consistency always use unmap_sysmem()

Fixes: commit 22f2c9ed9f ("efi: memory: use the lmb API's for allocating and freeing memory")
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-11-24 15:25:03 +01:00
Tom Rini
5e9b16ebca Merge tag 'u-boot-imx-master-20241123' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/23523

- Fix a imx8mn clock driver regression where the 32kHz clock can not be
  found in SPL.
2024-11-23 21:14:15 -06:00
Heinrich Schuchardt
9c792ab336 configs: JH7110: enable EFI_LOADER_BOUNCE_BUFFER
Our MMC driver for JH7110 boards only supports reading to the low 4 GiB of
memory. Booting boards with more memory requires EFI_LOADER_BOUNCE_BUFFER.

Reported-by: E Shattow <lucent@gmail.com>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Tested-by: Loic Devulder <ldevulder@suse.com>
2024-11-23 23:37:00 +01:00
Heinrich Schuchardt
3fbbaf139c efi_loader: allow EFI_LOADER_BOUNCE_BUFFER on all architectures
Commit 775f7657ba ("Kconfig: clean up the efi configuration status")
by mistake revoked commit dcd1b63b70 ("efi_loader: allow
EFI_LOADER_BOUNCE_BUFFER on all architectures").

Fixes: 775f7657ba ("Kconfig: clean up the efi configuration status")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Tested-by: Loic Devulder <ldevulder@suse.com>
2024-11-23 23:36:54 +01:00
Jerome Forissier
5753b9eb48 doc: cmd: wget: document lwIP syntax
The lwIP version of wget supports a different syntax with a URL,
in addition to the legacy syntax. Document that.

While we're at it, fix a couple of minor issues in the legacy
syntax:
- hostIPaddr can be a DNS name if CONFIG_CMD_DNS is enabled
- path is mandatory

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-11-23 23:33:48 +01:00
Heinrich Schuchardt
f9dd2e2c9f doc: remove README.TPL
doc/develop/spl.rst describes SPL, TPL, VPL.
Remove the outdated README.TPL document.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-11-23 23:16:03 +01:00
Heinrich Schuchardt
8c87187119 doc: move README.kconfig to HTML documentation
* format according to Sphinx style
* add link to Linux Kconfig documentation
* sort table alphabetically in 'Conversion from boards.cfg to Kconfig'

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-11-23 23:15:39 +01:00
Heinrich Schuchardt
a152e14999 efi_loader: simplify efi_tcg2_hash_log_extend_event()
The value of variable nt is never used. Just use NULL when calling
efi_check_pe().

The API function is not expected to write to the console. Such output might
have unwanted side effects on the screen layout of an EFI application.

Leave error handling to the caller.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-11-23 23:14:15 +01:00
Marek Vasut
c02cdd4187 arm64: dts: imx8mn: Include 32kHz oscillator clock in SPL DTs
Since 50cdd3f74a ("clk: imx: clk-imx8mn Fix nand and spi clock parent"),
drivers/clk/imx/clk-imx8mn.c clk_get_by_name(dev, "osc_24m", &osc_24m_clk)
fails with error -22 EINVAL in SPL. This is because clk_get_by_name() in the
end calls fdtdec_parse_phandle_with_args(), which iterates over all phandles
in clock-controller@30380000 { clocks = <&osc_32k>, <&osc_24m>, ... } node
'clocks' property in an attempt to find the "osc_24m" clock, but fails to
resolve the &osc_32k phandle and returns with -EINVAL.

Include the osc_32k clock in SPL DTs as a low risk fix for v2025.01 release.
This way, fdtdec_parse_phandle_with_args() can resolve both the osc_32k and
following osc_24m phandle and successfully look up the osc_24m clock.

Fixes: 50cdd3f74a ("clk: imx: clk-imx8mn Fix nand and spi clock parent")
Signed-off-by: Marek Vasut <marex@denx.de>
Tested-by: Adam Ford <aford173@gmail.com> #imx8mn-beacon
2024-11-23 15:46:34 -03:00
Tom Rini
52c0e5f8a3 Merge branch '2024-11-22-assorted-fixes'
- Assorted additional lwIP fixes
- Assorted test fixes
- Assorted other localized fixes
2024-11-22 15:04:54 -06:00
Heinrich Schuchardt
0e3cd1313f cmd: improve description of the cdp command
Users might not know what 'CDP' refers to. Provide basic information.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-11-22 15:04:54 -06:00
Heinrich Schuchardt
5444189998 test: unit test for hextoull()
Provide a unit test for the hextoull() function.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2024-11-22 15:04:54 -06:00
Jerome Forissier
13e13f5867 net: lwip: dhcp: support arguments for TFTP file download
The dhcp command is supposed to have the following syntax as per
"help dhcp":

  dhcp [loadAddress] [[hostIPaddr:]bootfilename]

In other words, any arguments should be passed to an implicit
tftpboot command after the DHCP exchange has occurred.

Add the missing code to the lwIP version of do_dhcp().

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
2024-11-22 14:51:26 -06:00
Ilias Apalodimas
2cde2f4a00 net: lwip: provide entropy to MBed TLS in one go
We currently provide entropy to mbedTLS using 8b chunks.
Take into account the 'len' parameter passed by MBed TLS to the entropy
gathering function instead. Note that the current code works because len
is always 128 (defined at compile time), therefore mbedtls_hardware_poll()
is called repeatedly and the buffer is filled correctly. But passing 'len'
to dm_rng_read() is both better and simpler.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Suggested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2024-11-22 14:40:53 -06:00
Jerome Forissier
572b5b0d5a net: lwip: wget: update help string
The lwIP version of wget also supports the legacy syntax. Document it in
the help string.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-11-22 14:40:53 -06:00
Jerome Forissier
7d80e7368e net: lwip: fix get_udev_ipv4_info()
The local variables ipstr, maskstr and gwstr in static function
get_udev_ipv4_info() cannot be pointers to read-only data, since
they may be written to in case the device index is > 0. Therefore
make them char arrays allocated on the stack.

Reported-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reported-by: Adriano Cordova <adrianox@gmail.com>
Link: https://lists.denx.de/pipermail/u-boot/2024-November/572066.html
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-11-22 14:37:49 -06:00
Udit Kumar
dfe5f16a33 arm64: dts: ti: k3-j7200: Fix OSPI boot
OSPI boot is broken due to missing bootph property
in pin mux of OSPI.
So add bootph to fix OSPI boot.

Signed-off-by: Udit Kumar <u-kumar1@ti.com>
2024-11-22 14:37:49 -06:00
Ben Horgan
afa99e65b9 board: armltd: Make myself maintainer for total compute
The previous maintainer is no longer involved in total compute.

Signed-off-by: Ben Horgan <ben.horgan@arm.com>
Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Leo Yan <leo.yan@arm.com>
2024-11-22 14:37:49 -06:00
Tom Rini
c16fcbc14a Revert "test: Update time tests to use unit-test asserts"
While at the base level, this conversion looks equivalent, we now see
both of these tests failing (due to exceeding their allowed margin for
being too slow) in Azure with a very high frequency.

This reverts commit 88db4fc5fe.

Signed-off-by: Tom Rini <trini@konsulko.com>
Tested-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2024-11-22 14:37:21 -06:00
Jerome Forissier
8c95d84b39 net: lwip: fix dhcp_loop()
The local variables ipstr, maskstr and gwstr in static function
dhcp_loop() cannot be pointers to read-only data, since they may be
written to in case the device index is > 0. Therefore make them char
arrays allocated on the stack.

Reported-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-11-22 14:37:21 -06:00
Mattijs Korpershoek
e92b5d0ddf test: boot: Set DM|SCAN_FDT flags for bootmeth_{cros,android}
We make fewer calls to dm_test_restore() since
commit fbdac8155c ("test: Expand implementation of ut_list_has_dm_tests()")

Because of this some valid test combinations are now broken:

$ ./test/py/test.py --bd sandbox --build -k test_ut
$ ./test/py/test.py --bd sandbox --build -k "bootflow_android or bootflow_cros"

Shows:

  Expected '  2  cros         ready   mmc          4 mmc5.bootdev.part_4       ',
  got '  2  cros         ready   mmc          2 mmc5.bootdev.part_2       '

Here prep_mmc_bootdev() is called twice and it will bind bootmeth_cros twice.

Since bootmeth_cros is bound twice, 'bootflow scan' will find 2x the
expected bootflows.

Before
commit fbdac8155c ("test: Expand implementation of ut_list_has_dm_tests()")
this did not happen because a cleanup was called each time.

Add UTF_DM and UTF_SCAN_FDT flags to both tests to make sure that the
bootmeths are unbound after the test finishes.

Fixes: fbdac8155c ("test: Expand implementation of ut_list_has_dm_tests()")
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2024-11-22 14:37:21 -06:00
Tom Rini
35d5ad6cf2 Merge branch 'qcom-main' of https://source.denx.de/u-boot/custodians/u-boot-snapdragon
CI: https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/pipelines/23474

- UFS support is enabled for SC7280 and SM8150 platforms.
- Qualcomm dt-bindings headers are all dropped in favour of
  dts/upstream.
- The SMMU driver now correctly handles stream ID 0 and is disabled in
  EL2.
- Initial support for capsule updates (using the new dynamic UUIDs) is
  added for the RB3 Gen 2 board alongside a new SCSI backend for DFU.
- CONFIG_PINCONF is enabled in qcom_defconfig.
- The vqmmc supply is now enabled for sdcard support on boards that need
  it.
- A quirk is added for reading GPIOs on the PM8550 PMIC
2024-11-20 11:55:24 -06:00
Caleb Connolly
7aad783332 treewide: remove Qualcomm dt-binding headers that are available upstream
Some dt-binding headers mask the upstream ones which can lead to build
failures, or worse: super weird bugs, if they get out of sync.

Remove these headers so our devicetree and binding headers will both be
in sync with upstream.

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-11-20 17:57:58 +01:00
Caleb Connolly
e55fc3ab20 iommu: qcom-smmu: handle running in el2
We only need to configure the SMMU when running in EL1. In EL2 the
hypervisor isn't running so peripherals can just do DMA as they wish.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-11-20 17:57:58 +01:00
Caleb Connolly
53c0f1beac iommu: qcom-smmu: allow SID 0
It turns out this is a very real stream ID. Who woulda thought?

Drop the 0 check on the SID, there's no reason for it to be there in the first
place.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-11-20 17:57:58 +01:00
Caleb Connolly
e88089e4f1 qcom_defconfig: enable capsule update support
Enable all the necessary options for capsule updates to work, as well as
a few additional EFI features.

Capsule updates themselves are only enabled for the RB3 Gen 2, since the
exact details on where to flash U-Boot (or how to handle multiple boot
methods) has not been finalised for other boards.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-11-20 17:57:58 +01:00
Caleb Connolly
b10b4c0e1e mach-snapdragon: implement capsule update support
Qualcomm boards flash U-Boot a variety of partitions, implement support
for determining which slot U-Boot is running from, finding the correct
partition for that slot and configuring the appropriate DFU string.

Initially, we only support the RB3 Gen 2 where U-Boot is flashed to the
UEFI partition, and ignore handling of slots. In the future we will
additionally support booting U-Boot from other partitions (e.g. boot)
and correct handling for A/B.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-11-20 17:57:58 +01:00
Caleb Connolly
eab4675f93 disk: expose partition type flags
GPT partition tables include two bytes worth of vendor defined
attributes, per partition. ChromeOS and Qualcomm both use these (with
different encoding!) to handle A/B slot switching with a retry counter.

Expose these via the disk_partition struct so that they can be parsed by
the relevant board code.

This will be used on Qualcomm boards to determine which slot we're
booting on so that we can flash capsule updates to the correct one.

Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-11-20 17:57:58 +01:00
Caleb Connolly
ef14c347db dfu: add scsi backend
This is extremely similar to the MMC backend, but there are some notable
differences.

Works with a DFU string like

    scsi 4=u-boot-bin part 11

Where "4" is the SCSI dev number (sequential LUN across all SCSI devices)
and "11" is the partition number.

Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Acked-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-11-20 17:57:58 +01:00
Julius Lehmann
0ce0b77243 phy: qcom: Add SM8150 to QMP UFS PHY driver
Copy PHY tables over from Linux to support SM8150

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
2024-11-20 17:57:58 +01:00
Caleb Connolly
1e49d9916b phy: qcom: ufs: add sc7280
Add configuration for the SC7280, copied from Linux 6.11

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-11-20 17:57:58 +01:00
Neil Armstrong
70cb7c239f qcom_defconfig: enable UFS Qualcomm controller and PHY drivers
Now the Qualcomm controller and PHY drivers were accepted,
enable then in the qcom_defconfig file.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-11-20 17:57:57 +01:00
Neil Armstrong
0e3f5c5829 dt-bindings: remove phy/phy-qcom-qmp.h in favor of dts/upstream
The upstream version has new defines use to build DT, drop
it in favor of the dts/upstream more recent one.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-11-20 17:57:57 +01:00
Neil Armstrong
5afcd44096 phy: qcom: ufs: drop unused ufsphy_v2_regs_layout
The ufsphy_v2_regs_layout is not used, drop it and fix:
phy-qcom-qmp-ufs.c:87:27: warning: ‘ufsphy_v2_regs_layout’ defined but not used [-Wunused-const-variable=]

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-11-20 17:57:57 +01:00
Neil Armstrong
9b9ccca64c gpio: qcom_pmic: add again the quirk to skip GPIO configuration on PM8550
The qcom_pmic code is broken for new PMICs and should be fixed,
without the QUIRK the code is broken and the GPIOs don't work
anymore on SM8550 and SM8650 platforms.

Partially revert the revert and only add the quirk on the PM8550
PMIC, making the buttons and MMC detect gpio work again.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-11-20 17:57:57 +01:00
Neil Armstrong
615dfe1aea mmc: msm_sdhci: enable vqmmc at probe if available
On earlier platforms, the vqmmc regulator was enabled by the
previous bootloader, but on the newest (SM8650) it's not
and we need vqmmc to be enabled in order to have the card
to respond.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-11-20 17:57:57 +01:00
Caleb Connolly
ab76484cf2 mach-snapdragon: configure logging
Set LOG_CATEGORY and pr_fmt. Also fix the time.h include.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-11-20 17:57:57 +01:00
Neil Armstrong
c75a535bd3 ARM: mach-snapdragon: configure a larger default SYS_MALLOC_LEN for fastboot
Fastboot is very hungry when it flashes larges chunks, and 8MiB
is way too small, allocate a much bigger size like other platforms
using Fastboot.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Tested-by: Caleb Connolly <caleb.connolly@linaro.org> # rb1
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-11-20 17:57:57 +01:00
Neil Armstrong
1ef0f64a68 qcom_defconfig: enable PINCONF
The SM8550 and SM8650 SoCs requires PINCONF to properly
setup SDC pins in order to function correctly.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-11-20 17:57:57 +01:00
Tom Rini
7fe55182d9 Merge tag 'xilinx-for-v2025.01-rc3-v2' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
AMD/Xilinx changes for v2025.01-rc3:

- microblaze:
  - Disable JFFS2
- fpga:
  - pass compatible flag to fpga_load()
- zynqmp:
  - SOM RTC fix
  - SC(system controller) PMW polarity fix
  - Fix ram_top calculation with introducing XILINX_MINI
  - Fix RPU release command
- versal:
  - Enable capsule update
  - Enable soft reset and Micron octal flashes
- xilinx:
  - Align Kconfig regarding SPI_STACKED_PARALLEL
- bootcount:
  - Add new zynqmp driver
2024-11-19 12:58:05 -06:00
Michal Simek
383fc2f501 xilinx: Introduce XILINX_MINI configuration
There is no common symbol which mini configurations are using and recent
get_mem_top() changes adding 1.3kB without having a way to remove it.
That's why introduce new symbol which can be used for removing features
which are not requested by these configurations.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/aa27b72e17057fa8cbdd92a2bbb863a31c8c1226.1731681053.git.michal.simek@amd.com
2024-11-19 15:57:56 +01:00
Michal Simek
57066053b6 microblaze: Disable JFFS2 support
JFFS2 is not maintained for quite a long time and none should be using it.
Please use other filesystems for flashes like UBIFS instead.

Also remove jffs to MTD map but MTD map is for example that's why it won't
affect anything.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/a8239acee8886229fdbff66142c46d522e3fe851.1731659933.git.michal.simek@amd.com
2024-11-19 15:57:31 +01:00
Michal Simek
253b26a72f arm64: zynqmp: Set default RTC device at start
For RTC to start to operate there is a need to call the driver. The simple
way to do it is to set default RTC instance which will call the probe and
do basic initialization.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/01155f1555dbd42adc618906629f5fb45754d5a4.1731419926.git.michal.simek@amd.com
2024-11-19 15:56:44 +01:00
Venkatesh Yadav Abbarapu
93501f641b arm64: versal: Enable soft reset support for xspi flashes
Activate the xSPI Software Reset support, which will be
utilized to transition from octal DTR mode to legacy
mode during shutdown and boot (if enabled).

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20241114042641.22642-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2024-11-19 15:56:44 +01:00
Venkatesh Yadav Abbarapu
46911346ee arm64: versal: Enable defconfig for Micron octal flashes
The Micron MT35 series octal flashes can be activated
through the configuration option CONFIG_SPI_FLASH_MT35XU.
To ensure their detection, enable this option in the
default defconfig for octal flashes.

Signed-off-by: Tejas Bhumkar <tejas.arvind.bhumkar@amd.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20241114051047.13700-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2024-11-19 15:56:44 +01:00
Venkatesh Yadav Abbarapu
5a24caca06 spi: cadence_qspi: Fix OSPI boot issue
Moving the hw_reset function from the controller driver to
the NOR framework has caused the OSPI reset not to be triggered
in the Cadence driver's probe function. As a result, reading the
flash ID during SPI calibration is incorrect, and the
CQSPI_REG_RD_DATA_CAPTURE is set with an invalid value.This makes
it unable to read the flash ID properly.
To solve this problem, it's suggested to skip SPI calibration and
instead retrieve the read_delay directly from the device tree.

Skipping SPI calibration doesn't bring harm since there's no need
for the flash golden values stored during SPI calibration.
Instead, they are now read during the spi_nor_read_id call in the
NOR framework.

Signed-off-by: Tejas Bhumkar <tejas.arvind.bhumkar@amd.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20241114062045.17581-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2024-11-19 15:56:44 +01:00
Caleb Connolly
06b8aafd68 fastboot: properly handle unknown partition type
In getvar_partition_type() we attempt to find a filesystem driver for
the partition (of the list of driver enabled in U-Boot), on failure we
return the error to fastboot and completely bail out of the operation.

However, this should not be a failure, instead we should just default to
"raw". This allows commands like "fastboot format:ext4 userdata" to work
if userdata didn't already have an ext4 partition table (or if FS_EXT4
is disabled in U-Boot), as failing to determine the current partition
type is not an error in this case.

Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Link: https://lore.kernel.org/r/20241113050607.1850472-1-caleb.connolly@linaro.org
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2024-11-19 15:10:56 +01:00
Heinrich Schuchardt
3d0da87cd4 test: cmd/hash: check return value of ut_check_console_line
ut_check_console_line() does include an assert.
Pass the result to ut_assertok().

Addresses-Coverity-ID:  514958 Error handling issues
Fixes: 7dfafcd65e ("test: unit test for hash command")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-11-18 19:10:56 -06:00
Jerome Forissier
deb9a07cf1 Kconfig: describe NET, NO_NET, LWIP_DEBUG and LWIP_ASSERT
Some Kconfig symbols introduced in commit 8cb330355b ("net: introduce
alternative implementation as net/lwip/") need a full description. The
NET symbol needs one, too.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-11-18 13:32:16 -06:00
Heinrich Schuchardt
2071583c8f net: lwip/wget: correct SERVER_NAME_SIZE
The maximum length of a domain name is 253 as defined in RFC 1035.
So SERVER_NAME_SIZE should be 254 including NUL.

Fixes: 3c656c928b ("net: lwip: add wget command")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-11-18 13:32:12 -06:00
Tom Rini
0e6432e19f Merge patch series "Fix boot failure due to misaligned DMA buffer"
Nam Cao <namcao@linutronix.de> says:

We observed the following sporadic boot failure while booting from MMC
device:

=> boot
CACHE: Misaligned operation at range [9efa25f8, 9efa27f8]
CACHE: Misaligned operation at range [9efa25f8, 9efa27f8]
CACHE: Misaligned operation at range [9efa25f8, 9efa27f8]
CACHE: Misaligned operation at range [9efa25f8, 9efa27f8]
** Booting bootflow 'mmc@2194000.bootdev.part_1' with extlinux
Ignoring unknown command: �D���D��
Boot failed (err=-14)

The reason is because while allocating buffer to read a file from MMC,
alignment of 1 byte is used. Thus, the buffer doesn't work for performing
DMA, and garbage data is read.

While looking at this issue, I also noticed that if no alignment specified
(align=0) then fs_read_alloc() is documented to use the default. But the
default is no alignment. Therefore, other users of fs_read_alloc() which
specify align=0 may be broken as well.

The first patch changes extlinux_read_bootflow() to use proper buffer
alignment for DMA.

The second patch changes the default alignment of fs_read_alloc() to be
DMA-suitable, to fix other potential bugs.
2024-11-18 08:24:06 -06:00
Nam Cao
6ea8dc661b fs: Use ARCH_DMA_MINALIGN as default alignment for fs_read_alloc()
The comment above fs_read_alloc() explains:

    @align: Alignment to use for memory allocation (0 for default)

However, in the actual implementation, there is no alignment when @align is
zero.

This current default is probably fine for most cases. But for some block
devices which transfer data via DMA, ARCH_DMA_MINALIGN is needed.

Change the default alignment to ARCH_DMA_MINALIGN.

Fixes: de7b5a8a1a ("fs: Create functions to load and allocate a file")
Signed-off-by: Nam Cao <namcao@linutronix.de>
Tested-by: Javier Fernandez Pastrana <javier.pastrana@linutronix.de>
2024-11-18 08:23:56 -06:00
Nam Cao
5efd63c93c boot: extlinux: Fix unaligned buffer for reading data from file system
extlinux_read_bootflow() allocates a buffer to read from file system
without any alignment.

But for some block devices which transfer data via DMA, ARCH_DMA_MINALIGN
alignment is required. For example, due to misaligned buffer, the below
boot failure is observed.

=> boot
CACHE: Misaligned operation at range [9efa25f8, 9efa27f8]
CACHE: Misaligned operation at range [9efa25f8, 9efa27f8]
CACHE: Misaligned operation at range [9efa25f8, 9efa27f8]
CACHE: Misaligned operation at range [9efa25f8, 9efa27f8]
** Booting bootflow 'mmc@2194000.bootdev.part_1' with extlinux
Ignoring unknown command: �D���D��
Boot failed (err=-14)

Change the buffer alignment to ARCH_DMA_MINALIGN.

Fixes: 31aefaf89a ("bootstd: Add an implementation of distro boot")
Signed-off-by: Nam Cao <namcao@linutronix.de>
Tested-by: Javier Fernandez Pastrana <javier.pastrana@linutronix.de>
2024-11-18 08:23:56 -06:00
Tom Rini
a38390284a Merge tag 'tpm-master-16112024' of https://source.denx.de/u-boot/custodians/u-boot-tpm
CI: https://source.denx.de/u-boot/custodians/u-boot-tpm/-/pipelines/23393

- Two changes from Heinrich:
  - One is adding some missing TPM files for proper maintenance.
  - The second addresses Coverity-ID: 356664 replacing a mempcy() which
    has undefined behavior with memmove()
2024-11-16 13:09:18 -06:00
Heinrich Schuchardt
c0231ede0f MAINTAINERS: add lib/tpm* to TPM DRIVERS
All TPM code should be maintained.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-11-16 19:23:11 +02:00
Heinrich Schuchardt
6c717d952d tpm: use memmove() for overlapping buffers
The behavior of memcpy() for overlapping buffers is undefined.

Fixes: 4c57ec76b7 ("tpm: Implement state command for Cr50")
Addresses-Coverity-ID: 356664 Overlapping buffer in memory copy
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-11-16 19:21:59 +02:00
Holger Brunck
f39199e809 km: disable CMD_JFFS2 for all PPC boards
We don't use this feature, we can remove it therefore in the defconfigs.

Signed-off-by: Holger Brunck <holger.brunck@hitachienergy.com>
2024-11-15 13:11:51 -06:00
Dominique Martinet
6e988fde65 fs: btrfs: hide duplicate 'Cannot lookup file' error on 'load'
Running commands such as 'load mmc 2:1 $addr $path' when path does not
exists will print an error twice if the file does not exist, e.g.:
```
Cannot lookup file boot/boot.scr
Failed to load 'boot/boot.scr'
```
(where the first line is printed by btrfs and the second by common fs
code)

Historically other filesystems such as ext4 or fat have not been
printing a message here, so do the same here to avoid duplicate.

The other error messages in this function are also somewhat redundant,
but bring useful diagnostics if they happen somewhere, so have been left
as printf.

Note that if a user wants no message to be printed for optional file
loads, they have to check for file existence first with other commands
such as 'size'.

Signed-off-by: Dominique Martinet <dominique.martinet@atmark-techno.com>
Reviewed-by: Qu Wenruo <wqu@suse.com>
2024-11-15 13:11:47 -06:00
Love Kumar
92e1c2bf9e test/py: spi: Rephrase the warning/error messages
Rephrasing the error and warning messages to be more meaningful and
clear.

Signed-off-by: Love Kumar <love.kumar@amd.com>
2024-11-15 13:11:29 -06:00
Tom Rini
c04999d999 Merge tag 'u-boot-imx-master-20241115' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/23373

- Fix a missing break for CMD_DCD_SKIP reported by Coverty on imx8image.
- Fix i.MX thermal threshold regression.
2024-11-15 13:10:36 -06:00
Francesco Dolcini
e6c3c63035 imx: Fix critical thermal threshold
Fix the critical thermal threshold for i.MX processors, this was changed
while moving the code from imx8m/imx9 directories into a shared place.

There is no need to keep the critical threshold 5 degrees less than the
SoC maximum temperature threshold, what is actually going to happen in
practice is that we are going to power-off the board when the SoC is
still within its working temperature range.

In addition to that this is a change in the actual behavior, that is
introducing a regression to users, and it was hidden within a software
refactoring.

Fixes: d0fe80890a ("imx: Generalize fixup_thermal_trips")
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
2024-11-15 14:36:47 -03:00
Fabio Estevam
3c417c79e0 tools: imx8image: Add missing break for CMD_DCD_SKIP
The CMD_DCD_SKIP case misses a break statement.

Add it.

Fixes: 254c00803b ("tools: imx8image: add possibility to skip dcd")
Addresses-Coverity-ID: 514648: Control flow issues (MISSING_BREAK)
Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
2024-11-15 14:36:33 -03:00
Vasileios Amoiridis
159dfef261 drivers: bootcount: Add ZynqMP specific bootcount support
Add native support of the bootcount mechanism in the ZynqMP by
utilising internal PMU registers. The Persistent Global Storage
Registers of the Platform Management Unit can keep their value
during reboot cycles unless there is a POR reset, making them
appropriate for the bootcount mechanism.

Signed-off-by: Vasileios Amoiridis <vasileios.amoiridis@cern.ch>
Reviewed-by: Heiko Schocher <hs@denx.de>
Link: https://lore.kernel.org/r/20241105132744.1572759-2-vassilisamir@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2024-11-15 14:32:47 +01:00
Peter Korsgaard
4bd7222c6b boot/image-board.c: boot_get_fpga(): pass compatible flag to fpga_load()
For E.G. signed FPGA bitstreams, similar to how it is done for the FPGA
loading from SPL since commit 71f1a5392a ("spl: fit: pass real compatible
flags to fpga_load()").

Signed-off-by: Peter Korsgaard <peter@korsgaard.com>
Link: https://lore.kernel.org/r/20241105162136.839633-1-peter@korsgaard.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2024-11-15 14:32:47 +01:00
Michal Simek
064c8978b4 arm64: versal: Enable capsule update (SD)
Enable capsule update in SD boot mode. For getting it work there is a need
to generate or setup dfu_alt_info and enable sysreset with DFU_MMC.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/cede513de764b99560dc3737457dbc8a5cc71d21.1729857366.git.michal.simek@amd.com
2024-11-15 14:32:47 +01:00
Michal Simek
cf3aa7b52c arm64: versal: Do not define do_reset() if sysreset is enabled
If sysreset is enabled reset_cpu is defined in sysreset uclass that's why
it can't be in platform/board code.
The same change was done by commit f1bc214b00 ("arm64: zynqmp: Do not
define do_reset() if sysreset is enabled").

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/8c1a5d6148c5e6c46790b725e8148a4e12d393ba.1729857366.git.michal.simek@amd.com
2024-11-15 14:32:47 +01:00
Padmarao Begari
b872583df1 arm64: zynqmp: Fix r5 mode for cpu release command
The cpu release command for r5 mode (lockstep/split) argument
accepts only string. But the zynqmp tcminit command accepts
string or number for r5 mode (lockstep/split or 0/1) argument.
To fix the r5 mode argument, the common argument (lockstep/split
or 0/1) is used across different u-boot commands. Use the strcmp()
instead of strncmp() to make uniform the r5 mode (lockstep/split
or 0/1) for the zynqmp tcminit and cpu release command.

Signed-off-by: Padmarao Begari <padmarao.begari@amd.com>
Link: https://lore.kernel.org/r/20241104122750.96251-1-padmarao.begari@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2024-11-15 14:32:47 +01:00
Michal Simek
6f7ff73fba arm64: xilinx: Rename SPI_ADVANCE to SPI_STACKED_PARALLEL
Align defconfigs with the latest Kconfig layout.

Fixes: f896aa6567 ("mtd: spi-nor: Rename SPI_ADVANCE to SPI_STACKED_PARALLEL")
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/fe05a0e542d6117c10956e4a104123e46f956793.1730450241.git.michal.simek@amd.com
2024-11-15 14:32:47 +01:00
Sughosh Ganu
62fbddf7c8 xilinx: use get_mem_top() to compute ram_top
Use the get_mem_top function to compute the value of ram_top. This was
earlier done through LMB API's, which are no longer available till
after relocation. Use get_mem_top() instead to compute the ram_top
value.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20241025172724.195093-3-sughosh.ganu@linaro.org
Signed-off-by: Michal Simek <michal.simek@amd.com>
2024-11-15 14:32:47 +01:00
Sughosh Ganu
feb423a3a3 common: memtop: add logic to detect ram_top
Add generic logic to determine the ram_top value for boards. Earlier,
this was achieved in an indirect manner through a set of LMB API's.
That has since changed so that the LMB code is available only after
relocation. Replace those LMB calls with a single call to
get_mem_top() to determine the value of ram_top.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20241025172724.195093-2-sughosh.ganu@linaro.org
Signed-off-by: Michal Simek <michal.simek@amd.com>
2024-11-15 14:32:02 +01:00
Christian Marangi
2bf2615b80 .gitignore: add test overlay .S and u_boot_logo files
Add test overlay .S and u_boot_logo file to gitignore as these files are
generated and should not be committed but ignored.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-11-14 18:14:06 -06:00
Heinrich Schuchardt
dfe7ab3514 lmb.c: add missing comma in lmb_dump_region()
In the message string " %s[%d]\t[0x%llx-0x%llx], 0x%08llx bytes flags: "
a comma is missing before flags.

To avoid increasing the code size replace '0x%' by '%#'.

Printing the size with leading zeros but not the addresses does not really
make sense. Remove the leading zeros from the size output.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
[trini: Fix test/cmd/bdinfo.c for these changes]
Signed-off-by: Tom Rini <trini@konsulko.com>
2024-11-14 18:14:06 -06:00
Heinrich Schuchardt
5430a5f67e test: use %zd for size_t in mbr_test_run()
For printing size_t we must use %zd and not %ld to avoid
a -Wformat error on 32-bit systems.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-11-14 18:14:06 -06:00
Heinrich Schuchardt
20b23f049f test: print_printf() must check availability of %ls
Availability of %ls in printf() depends on having
CONFIG_EFI_LOADER or CONFIG_EFI_APP.

Respect this when testing.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-11-14 18:14:06 -06:00
Heinrich Schuchardt
d8c5bcbd22 test: cmd/mbr: pass correct buffer size to init_write_buffers
We want to completely initialize the mbr and embr buffers. This requires
passing the buffer size and not the size of a pointer to the buffer.

Addresses-Coverity-ID: 510454 Wrong sizeof argument
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-11-14 18:14:06 -06:00
Heinrich Schuchardt
b891826067 upl: fix parsing of DT property
When calling decode_addr_size() we must pass the size of the device-tree
property and not sizeof(void *).

Fixes: 90469da3da ("upl: Add support for reading a upl handoff")
Addresses-Coverity-ID: 510459 Wrong sizeof argument
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-11-14 18:14:06 -06:00
Heinrich Schuchardt
504f36ed7a cmd: upl: initialize unit test state
do_upl_write() calls upl_get_test_data() which may increment the fail
count in the unit test state. We should initialize it.

Addresses-Coverity-ID: 510465 Uninitialized scalar variable
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2024-11-14 18:14:05 -06:00
Heinrich Schuchardt
e54ddc32cf xyz-modem: Add missing fallthrough annotation
Falltroughs in switch statements should be explicit.

Addresses-Coverity-ID: 131162 Missing break in switch
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-11-14 18:14:05 -06:00
Heinrich Schuchardt
1f66c0e1f4 lmb: do not panic in lmb_print_region_flags
Commit c3cf0dc64f ("lmb: add a check to prevent memory overrun")
addressed a possible buffer overrun using assert_noisy().

Resetting via panic() in lmb_print_region() while allowing invalid
lmb flags elsewhere is not reasonable.

Instead of panicking print a message indicating the problem.

fls() returns an int. Using a u64 for bitpos does not match.
Use int instead.

fls() takes an int as argument. Using 1ull << bitpos generates a u64.
Use 1u << bitpos instead.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Acked-by: Sughosh Ganu <sughosh.ganu@linaro.org>
2024-11-14 18:14:05 -06:00
Loic Poulain
1b99c15d73 lib: rsa: Set conventional salt length RSA-PSS parameter
RFC 3447 says that Typical salt length are either 0 or the length
of the output of the digest algorithm, RFC 4055 also recommends
hash value length as the salt length. Moreover, By convention,
most of the signing infrastructures/libraries use the length of
the digest algorithm (such as google cloud kms:
                      https://cloud.google.com/kms/docs/algorithms).

If the salt-length parameter is not set, openssl default to the
maximum allowed value, which is a openssl 'specificity', so this
works well for local signing, but restricts compatibility with
other engines (e.g pkcs11/libkmsp11):

```
returning 0x71 from C_SignInit due to status INVALID_ARGUMENT:
    at rsassa_pss.cc:53: expected salt length for key XX is 32,
    but 478 was supplied in the parameters
Could not obtain signature: error:41000070:PKCS#11 module::Mechanism invalid
```

To improve compatibility, we set the default RSA-PSS salt-length
value to the conventional one. A further improvement could consist
in making it configurable as signature FIT node attribute.

rfc3447: https://datatracker.ietf.org/doc/html/rfc3447
rfc4055: https://datatracker.ietf.org/doc/html/rfc4055

Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
2024-11-14 18:14:05 -06:00
Jerome Forissier
356011f7ac lwip: fix code style issues
Fix various code style issues in the lwIP code.

Reported-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-11-14 18:14:05 -06:00
Quentin Schulz
04b1d84221 Makefile: fix empty MK_ARCH when using ccache
One can use ccache by prefixing the typical CROSS_COMPILE value with
"ccache " (e.g. "ccache aarch64-gnu-linux-" for Aarch64). This however
makes the MK_ARCH empty because sed won't find a match anymore since it
expects the CROSS_COMPILE value to start with the actual toolchain (with
an unlimited number of white spaces before).

This is failing builds since commit 7506c15669 ("sandbox: Report host
default-filename in native mode").

Add "ccache" prefix to ignore but participate in the matching regex used
by sed to identify the target architecture.

Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
2024-11-14 10:51:28 -06:00
Tom Rini
2b14d12067 Merge patch series "examples: fix building on arm64"
Heinrich Schuchardt <heinrich.schuchardt@canonical.com> says:

Commit f9886bc60f ("Added arm64 assembly for examples/api crt0") added
the arm64 architecture but the code does not even build.

With the changes the 'demo' program runs on qemu_arm64_defconfig using

    setenv autostart no
    dhcp demo
    setenv autostart yes
    bootelf $loadaddr

Link: https://lore.kernel.org/r/20241103053551.52715-1-heinrich.schuchardt@canonical.com
2024-11-14 10:51:28 -06:00
Heinrich Schuchardt
9e7d7f95ec examples: make glue and demo code compatible with 64-bit
Commit f9886bc60f ("Added arm64 assembly for examples/api crt0")
added a 64-bit target for the examples but did not adjust the demo
code to be 64-bit compatible.

Change variable size for pointers.
Use %p to print pointers.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-11-14 10:51:07 -06:00
Heinrich Schuchardt
2ed26ee374 examples: adjust LOAD_ADDR on arm64
Change the load address on arm64 such that it is compatible with the memory
available on qemu_arm64_defconfig.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-11-14 10:51:07 -06:00
Heinrich Schuchardt
a3c101a613 examples: fix building on arm64
Commit f9886bc60f ("Added arm64 assembly for examples/api crt0") tried to
add arm64 support to the examples but crt0.S does not even build for
qemu_arm64_defconfig with CONFIG_API=y, CONFIG_EXAMPLES=y:

    examples/api/crt0.S: Assembler messages:
    examples/api/crt0.S:32: Error:
        expected a register at operand 1 -- `ldr ip,=search_hint'
    examples/api/crt0.S:33: Error:
        unexpected register type at operand 1 -- `str sp,[ip]'
    make[2]: *** [scripts/Makefile.build:292: examples/api/crt0.o] Error 1

Do not define _start twice.
Use valid register names.
Move syscall_ptr and search_hint to the data section to avoid an invalid
relocation.

Fixes: f9886bc60f ("Added arm64 assembly for examples/api crt0")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-11-14 10:51:07 -06:00
Tom Rini
f6ee671264 Merge patch series "cmd: hash: correct parameter count check"
Heinrich Schuchardt <heinrich.schuchardt@canonical.com> says:

Since commit 348ea87850 ("cmd: hash: fix param count check") the hash
command cannot be used without the optional variable name parameter if
CONFIG_HASH_VERIFY=y. 'hash sha1 $loadaddr $filesize' returns
CMD_RET_USAGE.

The minimum number of arguments is four no matter if verification is
enabled or not.

Fix the parameter check.

Provide a unit test.

Link: https://lore.kernel.org/r/20241102100836.103005-1-heinrich.schuchardt@canonical.com
2024-11-14 10:49:51 -06:00
Tom Rini
a45d823c02 Merge patch series "Apply SoM overlays on phyCORE-AM6xx SoMs"
Wadim Egorov <w.egorov@phytec.de> says:

Our SoMs are available in multiple configurations, managed via device
tree overlays. To determine the specific variant in use, we read the
EEPROM and apply the appropriate overlays during boot to the device tree
used by the OS.

Apply overlays for phyCORE-AM62x and phyCORE-AM64x SoMs.
Future K3 SoMs will be able to reuse this logic and overlays.

Link: https://lore.kernel.org/r/20241030164815.1763506-1-w.egorov@phytec.de
2024-11-14 10:49:51 -06:00
Heinrich Schuchardt
7dfafcd65e test: unit test for hash command
Provide a unit test testing the hash command.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-11-14 10:49:24 -06:00
Heinrich Schuchardt
6831415e39 cmd: hash: correct parameter count check
Since commit 348ea87850 ("cmd: hash: fix param count check") the hash
command cannot be used without the optional variable name parameter if
CONFIG_HASH_VERIFY=y. 'hash sha1 $loadaddr $filesize' returns
CMD_RET_USAGE.

The minimum number of arguments is four no matter if verification is
enabled or not.

Fixes: 348ea87850 ("cmd: hash: fix param count check")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@gmail.com>
2024-11-14 10:49:24 -06:00
Wadim Egorov
a687070664 board: phytec: common: k3: Apply SoM-specific overlays to OS device tree
Our SoMs are available in multiple configurations, managed via device
tree overlays. To determine the specific variant in use, we read the
EEPROM and apply the appropriate overlays during boot to the device tree
used by the OS.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Acked-by: Neha Malcom Francis <n-francis@ti.com>
2024-11-14 10:46:22 -06:00
Wadim Egorov
e09fabad2e arm: dts: k3-am642-phycore-som-binman: Add SoM overlays
Include SoM dt-overlays that handle variants of our SoMs into
u-boot's FIT image.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
2024-11-14 10:46:22 -06:00
Wadim Egorov
9f57a5bad1 arm: dts: k3-am625-phycore-som-binman: Add SoM overlays
Include SoM dt-overlays that handle variants of our SoMs into
u-boot's FIT image.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
2024-11-14 10:46:22 -06:00
Wadim Egorov
5476cc005c configs: phycore_am64x_a53_defconfig: Enable PHYTEC_SOM_DETECTION
Enable CONFIG_PHYTEC_SOM_DETECTION to apply SoM overlays
based on EEPROM configuration.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
2024-11-14 10:46:22 -06:00
Wadim Egorov
cfb88eb272 configs: phycore_am64x_a53_defconfig: Add SoM overlays to OF_OVERLAY_LIST
Include SoM dt-overlays for DT control so we can include them
into our u-boot FIT image.
While at it also resync after savedefconfig.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
2024-11-14 10:46:22 -06:00
Wadim Egorov
dc8a30a370 configs: phycore_am62x_a53_defconfig: Add SoM overlays to OF_OVERLAY_LIST
Include SoM dt-overlays for DT control so we can include them
into our u-boot FIT image.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
2024-11-14 10:46:22 -06:00
Tom Rini
8573ea4105 Merge patch series "labgrid: Provide an integration with Labgrid"
Simon Glass <sjg@chromium.org> says:

Labgrid provides access to a hardware lab in an automated way. It is
possible to boot U-Boot on boards in the lab without physically touching
them. It relies on relays, USB UARTs and SD muxes, among other things.

By way of background, about 4 years ago I wrong a thing called Labman[1]
which allowed my lab of about 30 devices to be operated remotely, using
tbot for the console and build integration. While it worked OK and I
used it for many bisects, I didn't take it any further.

It turns out that there was already an existing program, called Labgrid,
which I did not know about at time (thank you Tom for telling me). It is
more rounded than Labman and has a number of advantages:

- does not need udev rules, mostly
- has several existing users who rely on it
- supports multiple machines exporting their devices

It lacks a 'lab check' feature and a few other things, but these can be
remedied.

On and off over the past several weeks I have been experimenting with
Labgrid. I have managed to create an initial U-Boot integration (this
series) by adding various features to Labgrid[2] and the U-Boot test
hooks.

I hope that this might inspire others to set up boards and run tests
automatically, rather than relying on infrequent, manual test. Perhaps
it may even be possible to have a number of labs available.

Included in the integration are a number of simple scripts which make it
easy to connect to boards and run tests:

ub-int <target>
    Build and boot on a target, starting an interactive session

ub-cli <target>
    Build and boot on a target, ensure U-Boot starts and provide an interactive
    session from there

ub-smoke <target>
    Smoke test U-Boot to check that it boots to a prompt on a target

ub-bisect <target>
    Bisect a git tree to locate a failure on a particular target

ub-pyt <target> <testspec>
    Run U-Boot pytests on a target

Some of these help to provide the same tbot[4] workflow which I have
relied on for several years, albeit much simpler versions.

The goal here is to create some sort of script which can collect
patches from the mailing list, apply them and test them on a selection
of boards. I suspect that script already exists, so please let me know
what you suggest.

I hope you find this interesting and take a look!

[1] https://github.com/sjg20/u-boot/tree/lab6a
[2] https://github.com/labgrid-project/labgrid/pull/1411
[3] https://github.com/sjg20/uboot-test-hooks/tree/labgrid
[4] https://tbot.tools/index.html

Link: https://lore.kernel.org/r/20241112141326.643128-1-sjg@chromium.org
[trini: Move the sjg-lab job to prior to world build, to fix pipeline
        status]
Signed-off-by: Tom Rini <trini@konsulko.com>
2024-11-13 16:39:19 -06:00
Tom Rini
aa482995a8 Merge patch series "test: Tidy up the test/ directory"
Simon Glass <sjg@chromium.org> says:

Some tests do not use the unit-test framework. Others are in a suite of
their own, for no obvious reason.

This series tidies this up.

Link: https://lore.kernel.org/r/20241102193715.432529-1-sjg@chromium.org
2024-11-13 16:02:58 -06:00
Simon Glass
a819845df7 sandbox: Add a build without CMDLINE
Sometimes this breaks, so add a build to keep it working. Since sandbox
enables a lot of options, it is a good board to use. The new config is
created simply by copying the existing sandbox and turning off CMDLINE

Once we have tests for non-CMDLINE operation, this can be adjusted to
run those tests.

Create a new build which will be picked up by CI. Update the maintainer
entry as well.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2024-11-13 16:02:58 -06:00
Simon Glass
1888b09671 CI: Allow running tests on sjg lab
Add a way to run tests on a real hardware lab. This is in the very early
experimental stages. There are only 23 boards and 3 of those are broken!
(bob, ff3399, samus). A fourth fails due to problems with the TPM tests.

To try this, assuming you have gitlab access, set SJG_LAB=1, e.g.:

   git push -o ci.variable="SJG_LAB=1" dm HEAD:try

This relies on the two previous series targeted at -next as well as the
bugfix series for -master

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
2024-11-13 12:01:35 -06:00
Simon Glass
5e92fbcefc test: Correct regex string in test_spi
Use an 'r' string to avoid a warning:

  test/py/tests/test_spi.py:698: DeprecationWarning: invalid escape
     sequence '\s'

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Love Kumar <love.kumar@amd.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2024-11-13 12:01:35 -06:00
Simon Glass
8f2a9fa7d6 test: Support testing with two board-builds
The Beagleplay board uses an SoC from the TI K3 family. This has both a
Cortex-R core and a Cortex-A core and the R core needs to come up before
the A core. In both cases we have U-Boot SPL then U-Boot proper being
used.

In practice this means we need two entirely separate builds to produce
an image.

Handle this in test.py by adding more parameters.

Signed-off-by: Simon Glass <sjg@chromium.org>
2024-11-13 12:01:35 -06:00
Simon Glass
6d0ff32650 test: Add a section for closing the connection
This can take a while and involve multiple steps (e.g. turning the board
back off). Add a section for it and show the output.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2024-11-13 12:01:35 -06:00
Simon Glass
082f3359c7 test: Try to shut down the lab console gracefully
Send the Labgrid quit characters to ask it to exit gracefully. This
typically allows it to power off the board being used. Only do this when
labgrid is being used (detected with an env var).

If that doesn't work, try the less graceful approach.

The normal approach for pytest is to simply kill the child process. This
makes Labgrid exit immediately. Thus it does not get a chance to execute
the 'off' part of strategy (which may power it off) and release the
device.

Without this, every board disconnect leaves the board in a bad state,
requiring separate steps to recover the board, then power it off.

The action is conditional on since USE_LABGRID_SJG being set, so only
affects operation if the Labgrid-sjg integration is being used.

Signed-off-by: Simon Glass <sjg@chromium.org>
2024-11-13 12:01:35 -06:00
Simon Glass
5825ddccc6 test: Avoid double echo when starting up
There is a very annoying bug at present where the terminal echos part
of the first command sent to the board. This happens because the
terminal is still set to echo for a period until Labgrid starts up and
can change this.

Fix this by disabling echo (and other terminal features) as soon as the
spawn happens.

Signed-off-by: Simon Glass <sjg@chromium.org>
2024-11-13 12:01:35 -06:00
Simon Glass
f32951df40 test: Improve handling of sending commands
We expect commands to be echoed and this should happen quite quickly,
since U-Boot is sitting at the prompt waiting for a command.

Reduce the timeout for this situation. Try to produce a more useful
error message when something goes wrong. Also handle the case where the
connection has gone away since the last command was issued.

Signed-off-by: Simon Glass <sjg@chromium.org>
2024-11-13 12:01:35 -06:00
Simon Glass
8308a5eed6 test: Introduce lab mode
There is quite a bit of code in pytest to try to start up U-Boot on a
board, with timeouts, expects, etc.

This is tedious to maintain and is peripheral to the test system's
purpose. It seems better to put this logic in the lab itself, where is
can provide such support.

With Labgrid we can use the UbootStrategy class to get the board into a
useful state, however it needs to do it. Then it can report to pytest
by writing a suitable string along with the U-Boot version it detected.

Add support for detecting 'lab mode' and simply assume that all is well
in that case. Collect the version string when Labgrid says it is ready.

This is only used with the Labgrid-sjg integration. When Labgrid starts
the UbootStrategy it checks if U_BOOT_SOURCE_DIR is set. If so it emits
a string '{lab mode}' that tells test.py to simply wait for an
indication that the board is ready. All banner-checking is skipped. The
indication comes in the form of another string 'Lab: Board is ready'
which Labgrid sends once the board is sitting at a prompt ready to run
tests. Then test.py emits 'U-Boot is ready' and continues with testing.

Note that Labgrid has the same kind of "check for a string" logic that
is in test.py, except it's not caring about the correct number / order
of banner prints. This checking could be added, however. If something
fails, the complete output is shown, so it is possible to see what went
wrong.

Signed-off-by: Simon Glass <sjg@chromium.org>
2024-11-13 12:01:35 -06:00
Simon Glass
bf89a8f1fc test: Introduce the concept of a role
In Labgrid there is the concept of a 'role', which is similar to the
U-Boot board ID in U-Boot's pytest subsystem.

The role indicates both the target and information about the U-Boot
build to use. It can also provide any amount of other configuration.
The information is obtained using the 'labgrid-client query' operation.

Using this role, all required configuration for the board is stored
within the Labgrid environment, with pytest simply querying it. This
allows connecting to boards using an interactive console, something that
isn't possible without some kind of mapping. It also means that we don't
need to replicate the pytest functionality in tbot, since Labgrid can
handle the console and kick off builds as needed.

Make use of this in tests, so that only the role is required in gitlab
and other situations. The board type and other things can be queried
as needed.

Use a new 'u-boot-test-getrole' script to obtain the requested
information.

With this it is possible to run lab tests in gitlab with just a single
'ROLE' variable for each board.

Note that, without this feature:
- interactive use of boards with Labgrid-sjg would require repeating the
  id/board in a separate configuration file
- Gitlab yaml file would need to specify both the id and board

This feature is entirely optional, however, with the code gracefully
falling back to using a separate ID and board.

Link: https://tbot.tools

Signed-off-by: Simon Glass <sjg@chromium.org>
2024-11-13 12:01:35 -06:00
Simon Glass
6f3583074f test: Allow connecting to a running board
Sometimes we know that the board is already running the right software,
so provide an option to allow running of tests directly, without first
resetting the board.

This saves time when re-running a test where only the Python code is
changing.

Note that this feature is open to errors, since the user must know that
the board is in a fit state to execute tests. It is useful for repeated
iteration on a particular test, where it can save quite a bit of time.

Signed-off-by: Simon Glass <sjg@chromium.org>
2024-11-13 12:01:35 -06:00
Simon Glass
530c694c45 test: Release board after tests complete
When a board is finished with, the lab may want to power it off, or
perform some other function. Add a new script which is called when tests
are complete.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2024-11-13 12:01:35 -06:00
Simon Glass
8344038a93 test: Allow signaling that U-Boot is ready
When Labgrid is used, it can get U-Boot ready for running tests. It
prints a message when it has done so.

Add logic to detect this message and accept it.

Note that this does not change pytest, which still (also) looks for the
U-Boot banner. This change merely makes it possible for pytest to
believe Labgrid when it says that the board is ready for use.

In several cases, the board starts up and Labgrid receives some initial
output, then pytest starts and misses some of that output, because it
came in while Labgrid had the console open. Then pytest fails because
it doesn't see the expected banners.

With this change, Labgrid handles getting U-Boot to a prompt, in a
fully reliable manner. Then pytest starts up and can simply start
running its tests.

But, again, this does not prevent pytest from handling a banner if one
is provided (e.g. if not using the Labgrid integration).

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2024-11-13 12:01:35 -06:00
Simon Glass
c63f4e40f1 test: Quote test names
When mentioning a test name, add single quotes to make it easier to see.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Rini <trini@konsulko.com> # rpi_3, rpi_4, rpi_arm64, am64x_evm_a53, am64-sk
2024-11-13 11:56:02 -06:00
Simon Glass
4f570b36aa test: Correct display of failing test
This should show the test name, not the selected name, since the user
may be running all tests, in which case 'select_name' is NULL

Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Rini <trini@konsulko.com> # rpi_3, rpi_4, rpi_arm64, am64x_evm_a53, am64-sk
2024-11-13 11:56:02 -06:00
Simon Glass
88db4fc5fe test: Update time tests to use unit-test asserts
Rather than returning various error codes, use assertions to check that
the test passes.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Rini <trini@konsulko.com> # rpi_3, rpi_4, rpi_arm64, am64x_evm_a53, am64-sk
2024-11-13 11:56:02 -06:00
Simon Glass
dd0057dacb test: Move time tests into the lib suite
There is no particular need for the time tests to have their own test
command. Move them into the lib suite instead.

Update the test functions to match the normal unit-test signature.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Rini <trini@konsulko.com> # rpi_3, rpi_4, rpi_arm64, am64x_evm_a53, am64-sk
2024-11-13 11:56:02 -06:00
Simon Glass
890d91ff35 test: Move time_ut test into lib
This test doesn't belong at the top level. Move it into the lib/
directory, to match its implementation. Rename it to drop the
unnecessary _ut suffix.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Rini <trini@konsulko.com> # rpi_3, rpi_4, rpi_arm64, am64x_evm_a53, am64-sk
2024-11-13 11:56:02 -06:00
Simon Glass
5912a9ea1a test: Move unicode tests into the lib suite
There is no particular need for the unicode tests to have their own test
suite. Move them into the lib suite instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Tested-by: Tom Rini <trini@konsulko.com> # rpi_3, rpi_4, rpi_arm64, am64x_evm_a53, am64-sk
2024-11-13 11:56:02 -06:00
Simon Glass
7a27d4187a test: Move unicode_ut test into lib
This test doesn't belong at the top level. Move it into the lib/
directory, to match its implementation. Rename it to drop the
unnecessary _ut suffix.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Tested-by: Tom Rini <trini@konsulko.com> # rpi_3, rpi_4, rpi_arm64, am64x_evm_a53, am64-sk
2024-11-13 11:56:02 -06:00
Simon Glass
4563fb42f8 str: test: Move into the lib suite
There is no particular need for the str tests to have their own test
suite. Move them into the lib suite instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Rini <trini@konsulko.com> # rpi_3, rpi_4, rpi_arm64, am64x_evm_a53, am64-sk
2024-11-13 11:56:02 -06:00
Simon Glass
2352526362 test: Move str_ut test into lib
This test doesn't belong at the top level. Move it into the lib/
directory, to match (most of) its implementation. Rename it to drop the
unnecessary _ut suffix.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Rini <trini@konsulko.com> # rpi_3, rpi_4, rpi_arm64, am64x_evm_a53, am64-sk
2024-11-13 11:56:01 -06:00
Simon Glass
33ca12b233 test: Move print_ut into the common suite
There is no particular need for bloblist to have its own test suite.
Move it into the common suite instead.

Add the missing help for 'common'.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Rini <trini@konsulko.com> # rpi_3, rpi_4, rpi_arm64, am64x_evm_a53, am64-sk
2024-11-13 11:56:01 -06:00
Simon Glass
479b389c3d test: Move print_ut test into common
This test doesn't belong at the top level. Move it into the common/
directory, to match its implementation. Rename it to drop the
unnecessary _ut suffix.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Rini <trini@konsulko.com> # rpi_3, rpi_4, rpi_arm64, am64x_evm_a53, am64-sk
2024-11-13 11:56:01 -06:00
Simon Glass
7f8b8c5abc bootm: test: Move test into boot
This test doesn't belong at the top level. Move it into the boot/
directory, to match its implementation.

This test is currently dependent on bloblist, but the real dependency is
on sandbox, so update that.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Rini <trini@konsulko.com> # rpi_3, rpi_4, rpi_arm64, am64x_evm_a53, am64-sk
2024-11-13 11:56:01 -06:00
Simon Glass
ee3c8698e0 test: Update command test to use unit-test functions
Rather than enabled DEBUG and using assert(), use the unit-test
functions now provided.

Drop a check that causes pytest to fail.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Rini <trini@konsulko.com> # rpi_3, rpi_4, rpi_arm64, am64x_evm_a53, am64-sk
2024-11-13 11:56:01 -06:00
Simon Glass
c25b35b6c6 command: test: Move into the cmd suite
The command test was the very first test written in U-Boot, some 12
years ago. It predates the unit-test subsystem and was never converted
over.

There is no particular need for the command test to have its own
command. It is also confusing to have it separate from the normal test
suites. At present this test is not run in CI.

Move it into the cmd suite instead, updating it to become a unit test.
One of the checks is dropped to avoid an error.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Rini <trini@konsulko.com> # rpi_3, rpi_4, rpi_arm64, am64x_evm_a53, am64-sk
2024-11-13 11:56:01 -06:00
Simon Glass
a6165509f2 command_ut: test: Move test into lib
This test doesn't belong at the top level. Move it into the lib/
directory, since that is where compression is implemented.

Rename it to just 'command', since it is obviously a unit test and the
_ut suffix does not add much except to make it different from the names
of other test files.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Rini <trini@konsulko.com> # rpi_3, rpi_4, rpi_arm64, am64x_evm_a53, am64-sk
2024-11-13 11:56:01 -06:00
Simon Glass
5cf39254e3 compression: test: Move into the lib suite
There is no particular need for compression to have its own test suite.
Move it into the lib suite instead.

Add the missing help for 'common' and update the docs.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Rini <trini@konsulko.com> # rpi_3, rpi_4, rpi_arm64, am64x_evm_a53, am64-sk
2024-11-13 11:56:01 -06:00
Simon Glass
e67cc4ba1f compression: test: Move test into lib
This test doesn't belong at the top level. Move it into the lib/
directory, since that is where compression is implemented.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Rini <trini@konsulko.com> # rpi_3, rpi_4, rpi_arm64, am64x_evm_a53, am64-sk
2024-11-13 11:56:01 -06:00
Simon Glass
a5896b8a3e test: Drop test-trace.sh and common.sh
The trace feature is now tested in CI so there is no need for these old
script. Also they don't work. Drop them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Rini <trini@konsulko.com> # rpi_3, rpi_4, rpi_arm64, am64x_evm_a53, am64-sk
2024-11-13 11:56:01 -06:00
Simon Glass
692ed744ba bloblist: test: Drop global_data declarations
This pointer is not used any more, so drop the declarations.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Rini <trini@konsulko.com> # rpi_3, rpi_4, rpi_arm64, am64x_evm_a53, am64-sk
2024-11-13 11:56:01 -06:00
Simon Glass
82e6d79d9e bloblist: test: Move test into common
This test doesn't belong at the top level. Move it into the common/
directory, to match its implementation.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Rini <trini@konsulko.com> # rpi_3, rpi_4, rpi_arm64, am64x_evm_a53, am64-sk
2024-11-13 11:56:01 -06:00
Heinrich Schuchardt
9084e1b1b9 fs: ext4: correct error handling
After calling strdup() check the returned pointer.

Avoid a memory leak if the directory is not found.

Reported-by: Michael Nazzareno Trimarchi <michael@amarulasolutions.com>
Fixes: 22fdac381f ("fs: ext4: implement opendir, readdir, closedir")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-11-13 08:18:50 -06:00
Simon Glass
bbc3d12516 Makefile: Fake external blob with BINMAN_ALLOW_MISSING=1
This flag was lost by a previous change and has never been restored.
Without it, binman cannot fully handle missing blobs which are
themselves inputs to mkimage.

Discussion on this at [1] indicated that this was necessary but the
patch was not updated.

Restore the flag so that all missing blobs are reported.

Link: https://patchwork.ozlabs.org/project/uboot/patch/20221206020336.315465-1-trini@konsulko.com/

Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: 93685d0dcb ("Makefile: With BINMAN_ALLOW_MISSING=1 don't error")
2024-11-13 08:18:31 -06:00
Heinrich Schuchardt
3147f00f7a board: qemu-arm: select CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR
qemu_arm64_defconfig with CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=n leads to a
build error:

    arch/arm/lib/crt0_64.S:85:
    Error: constant expression expected at operand 2 --
    `ldr x0,=((CFG_SYS_INIT_RAM_ADDR+CFG_SYS_INIT_RAM_SIZE-480))'

We do not define CFG_SYS_INIT_RAM_ADDR and CFG_SYS_INIT_RAM_SIZE for QEMU.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-11-13 08:18:20 -06:00
Heinrich Schuchardt
e6b937f35e test: run longjmp() test only on supported architectures
We have only implemented longjmp() on the EFI architectures.

Define a symbol CONFIG_HAVE_SETJMP and have it selected by the relevant
architectures.

Use CONFIG_HAVE_SETJMP to decide if the longjmp test shall be built.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2024-11-13 08:16:47 -06:00
Heinrich Schuchardt
1cfafff319 lib: vsprintf: fix API build
Avoid a build failure when building with CONFIG_API=y, CONFIG_EXAMPLES=y:

    lib/vsprintf.c:312:14: warning:
    ‘device_path_string’ defined but not used [-Wunused-function]
     312 | static char *device_path_string(char *buf, char *end, void *dp, int field_width,
         |              ^~~~~~~~~~~~~~~~~~

Fixes: 64b5ba4d29 ("efi_loader: make device path to text protocol customizable")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-11-13 08:16:41 -06:00
Tom Rini
9d49c73862 Merge patch series "lib: uuid: fix uuid_str_to_le_bin() on 32-bit"
Heinrich Schuchardt <heinrich.schuchardt@canonical.com> says:

The lib_test_uuid_to_le and lib lib_test_dynamic_uuid tests fail on
32-bit systems. But we never caught this in our CI because we never
ran any of our C unit tests on 32-bit.

Enable CONFIG_UNIT_TEST on qemu_arm_defconfig.

hextoul() cannot convert a string to a 64-bit number on a 32-bit system.
Use the new function hextoull() instead.

Link: https://lore.kernel.org/r/20241103224223.195255-1-heinrich.schuchardt@canonical.com
2024-11-13 08:14:29 -06:00
Heinrich Schuchardt
37587d2e14 configs: enable UNIT_TEST on qemu_arm_defconfig
The lib_test_uuid_to_le test fails on 32-bit systems. But we never caught
this in our CI because we never ran any of our C unit tests on 32-bit.

Enable CONFIG_UNIT_TEST on qemu_arm_defconfig.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2024-11-13 08:14:23 -06:00
Heinrich Schuchardt
6a2664b126 lib: uuid: fix uuid_str_to_bin() on 32-bit
hextoul() cannot convert a string to a 64-bit number on a 32-bit system.
Use function hextoull() instead.

Reported-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Fixes: 22c48a92cd ("lib: uuid: supporting building as part of host tools")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Tested-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2024-11-13 08:14:23 -06:00
Heinrich Schuchardt
e5a0cb3eb3 lib: uuid: fix uuid_str_to_le_bin() on 32-bit
hextoul() cannot convert a string to a 64-bit number on a 32-bit system.
Use function hextoull() instead.

Reported-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Fixes: 22c48a92cd ("lib: uuid: supporting building as part of host tools")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Tested-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-11-13 08:14:23 -06:00
Heinrich Schuchardt
8ff37ec010 lib: provide function hextoull()
We often convert hexadecimal strings to hextoull(). Provide a wrapper
function to simple_strtoull() that does not require specifying the radix.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-11-13 08:14:23 -06:00
Tom Rini
b30787ad24 Merge patch series "Enable https for wget"
Ilias Apalodimas <ilias.apalodimas@linaro.org> says:

Hi all,

This is a respin of [1] adding https support to wget. In short

patch#1 enables the crypto algorithms we need in mbedTLS
patches#2, #3 enable anf fix the lwIP part we need
patch#4 is adding https:// parsing support in our wget
patch#5 is making https:// the default for QEMU lwip defconfig so
people can easily test
and finaly patch#6 updates our documentation

[1] https://lore.kernel.org/u-boot/20241024112449.1362319-1-ilias.apalodimas@linaro.org/

Link: https://lore.kernel.org/r/20241110083017.367565-1-ilias.apalodimas@linaro.org
2024-11-12 19:10:01 -06:00
Ilias Apalodimas
99649c6757 doc: uefi: Describe UEFI HTTPs boot
We now can use a combination og lwIP & mbedTLS and download from
https://. Describe the config options needed to enable it as well
as some limitations

Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-11-12 19:09:52 -06:00
Ilias Apalodimas
d9c4ee3838 configs: Enable https for wget on qemu arm64
QEMU already has an lwip variant of a defconfig. That defconfig
is also configured with mbedTLS by default. So let's enable the
remaining config options to enable wget for https:// as well
and test that codepath in the CI

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-11-12 19:09:52 -06:00
Ilias Apalodimas
5907c81647 net: lwip: Enable https:// support for wget
With the recent changes of lwip & mbedTLS we can now download from
https:// urls instead of just http://.
Adjust our wget lwip version parsing to support both URLs.
While at it adjust the default TCP window for QEMU since https seems to
require at least 16384

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
2024-11-12 19:09:52 -06:00
Javier Tia
1f444e915e net: lwip: Add Support Server Name Indication support
SNI, or Server Name Indication, is an addition to the TLS encryption
protocol that enables a client device to specify the domain name it is
trying to reach in the first step of the TLS handshake, preventing
common name mismatch errors and not reaching to HTTPS server that
enforce this condition. Since most of the websites require it nowadays
add support for it.

It's worth noting that this is already sent to lwIP [0]

[0] https://github.com/lwip-tcpip/lwip/pull/47

Signed-off-by: Javier Tia <javier.tia@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-11-12 19:09:52 -06:00
Javier Tia
514f18f8dc net: lwip: Update lwIP for mbedTLS > 3.0 support and enable https
The current code support mbedTLS 2.28. Since we are using a newer
version in U-Boot, update the necessary accessors and the lwIP codebase
to work with mbedTLS 3.6.0. It's worth noting that the patches are
already sent to lwIP [0]

While at it enable LWIP_ALTCP_TLS and enable TLS support in lwIP

[0] https://github.com/lwip-tcpip/lwip/pull/47

Signed-off-by: Javier Tia <javier.tia@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-11-12 19:09:52 -06:00
Ilias Apalodimas
a564f5094f mbedtls: Enable TLS 1.2 support
Since lwIP and mbedTLS have been merged we can tweak the config options
and enable TLS1.2 support. Add RSA and ECDSA by default and enable
enough block cipher modes of operation to be comatible with modern
TLS requirements and webservers

Reviewed-by: Raymond Mao <raymond.mao@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-11-12 19:09:52 -06:00
Jerome Forissier
385af1b898 net: wget: drop Content-Length processing
We don't do anything with Content-Length except a debug print, and the
strict_strtoul() call is incorrect (it always returns -EINVAL and leaves
content_length to zero due to the presence of trailing characters after
the decimal valuoe of Content-Length). So let's just drop this piece of
code.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
2024-11-12 19:08:57 -06:00
Tom Rini
867e16ae05 configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2024-11-12 15:00:36 -06:00
Tom Rini
9f538624fc Merge tag 'u-boot-stm32-20241112' of https://source.denx.de/u-boot/custodians/u-boot-stm
CI: https://source.denx.de/u-boot/custodians/u-boot-stm/-/pipelines/23296

- Deduplicate DH STM32MP1xx DHSOM and DHCOR defconfigs
- Fixes STM32MP1xx DHSOM and DHCOR device trees
- Add support of manufacturing environment to STM32MP15xx DHSOM
2024-11-12 13:40:29 -06:00
Marek Vasut
f9cfc47a83 ARM: stm32: Add optional manufacturing environment to DH STM32MP15xx DHSOM
Add manufacturing environment into STM32MP15xx DH electronics DHSOM
configuration. This environment is part of every board build, but only
takes effect on systems booted with the dh,stm32mp15xx-dhcor-testbench
device tree, i.e. systems populated with factory build of U-Boot.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2024-11-12 15:18:10 +01:00
Marek Vasut
0841716fdc ARM: stm32: Deduplicate DH STM32MP1xx DHSOM defconfigs
Deduplicate defconfigs for all DH STM32MP1xx DHSOM systems by factoring
out the common parts into generic stm32mp_dhsom.config and including
those using the #include <configs/...> preprocessor macro in the current
set of board specific defconfigs. The preprocessor macro is applicable
to defconfigs as well.

This introduces no functional change, the resulting .config is identical
for all DH STM32MP1xx DHSOM systems.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2024-11-12 14:18:43 +01:00
Marek Vasut
aa33518eb3 ARM: stm32: Deduplicate DH STM32MP15xx DHSOM defconfigs
Deduplicate defconfigs for all DH STM32MP15xx DHSOM systems by factoring
out the common parts into generic stm32mp15_dhsom.config and including
those using the #include <configs/...> preprocessor macro in the current
set of board specific defconfigs. The preprocessor macro is applicable
to defconfigs as well.

This introduces no functional change, the resulting .config is identical
for all DH STM32MP15xx DHSOM systems.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2024-11-12 14:18:43 +01:00
Marek Vasut
3cd3e0aa06 ARM: dts: stm32: Sort DH STM32 DHCOM DTSI
Sort the DTSI alphabetically. No functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2024-11-12 14:18:35 +01:00
Marek Vasut
2e5ebcfa6b ARM: dts: stm32: Drop duplicate pinmux on DH STM32 DHCOM
The ethernet0_rmii_pins_a pinmux change has no effect on any
DHSOM based hardware. The mco2_pins_a and mco2_sleep_pins_a
are both part of stm32mp15-pinctrl.dtsi . Drop both pinmux
changes.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2024-11-12 14:09:09 +01:00
Marek Vasut
635e9483c8 ARM: dts: stm32: Drop remnants of upstream DT switch on DH STM32 DHSOM
Remove unused local DT copies after the OF_UPSTREAM conversion.

Fixes: cccb29fc12 ("ARM: dts: stm32: Switch to using upstream DT on DH STM32 DHSOM")
Reported-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2024-11-12 12:57:36 +01:00
Saeed Nowshadi
7aeed221db arm64: zynqmp: Fix pwm-fan polarity
In previous version of pwm driver, the polarity of pwm were implemented
in reverse.  In recent release, that issue in the driver is fixed,
therefore, correctly set the polarity in the device tree.

Signed-off-by: Saeed Nowshadi <saeed.nowshadi@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/3e8e38b77101335f86bca0f05b3988877bb12993.1729766551.git.michal.simek@amd.com
2024-11-12 09:01:46 +01:00
Michal Simek
4de127a44a arm64: zynqmp: Configure SoC RTC on SOM
Use RTC available in HW on Kria SOM without using emulation that's why
configure it properly and disable emulated one.
Power on reset value of RTC Calibration register without battery backup is
not matching with crystal frequency which leads to RTC time drift. That's
why write CALIB_WRITE register with crystal frequency (0x7FFF). There is
also an option to write zero so that Linux will set default value (0x7FFF)
in driver probe but calibration 0 is not permited by DT schema.

Co-developed-by: Srinivas Goud <srinivas.goud@amd.com>
Signed-off-by: Srinivas Goud <srinivas.goud@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/9b684faeec85381b9b8fe796aaebc2ee79f17b8e.1729663761.git.michal.simek@amd.com
2024-11-12 09:01:46 +01:00
Sam Protsenko
57e77dc80e arm: dts: e850-96: Remove TRNG node from appended dts
Commit 136b7b6d2e ("Subtree merge tag 'v6.11-dts' of dts repo [1] into
dts/upstream") updates the upstream dts for E850-96 board, bringing
upstream TRNG node. There is no need to keep TRNG node in appended dts
anymore, so remove it.

Tested on E850-96 board by running 'rng' command in U-Boot shell.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2024-11-05 14:26:58 +09:00
Henrik Grimler
e5565c24bb pinctrl: exynos: fix type of count integer
unsigned int count is used to capture return of dev_read_string_count.
When an error occurs dev_read_string_count returns -ve, which can
hence not be handled correctly. Use int instead of unsigned int so
that errors are detected.

Fixes: 16ca80adc5 ("pinctrl: Add pinctrl driver support for Exynos7420 SoC")

Signed-off-by: Henrik Grimler <henrik@grimler.se>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2024-11-05 14:26:13 +09:00
Simon Glass
6e625484f5 test: boot: Use a consistent name for the script bootmeth
In the bootflow tests the script bootmeth is bound with the name
bootmeth_script whereas the others have a name without the bootmeth_
prefix. Adjust it to be the same.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2024-11-02 11:13:59 -06:00
Simon Glass
cedf9ccaa2 dm: core: Add a function to see if a device exists
All the uclass functions for finding a device end up creating a uclass
if it doesn't exist. Add a function which instead returns NULL in this
case.

This is useful when in the 'unbind' path, since we don't want to undo
any unbinding which has already happened.

Signed-off-by: Simon Glass <sjg@chromium.org>
2024-11-02 11:13:59 -06:00
Simon Glass
b84c13f37d alist: Add maintainer
Add myself as maintainer of alist

Signed-off-by: Simon Glass <sjg@chromium.org>
2024-11-02 11:13:59 -06:00
Simon Glass
d01c58acb7 alist: Add a way to efficiently filter an alist
Unlike linked lists, it is inefficient to remove items from an alist,
particularly if it is large. If most items need to be removed, then the
time-complexity approaches O(n2).

Provide a way to do this efficiently, by working through the alist once
and copying elements down.

Signed-off-by: Simon Glass <sjg@chromium.org>
2024-11-02 11:13:59 -06:00
Simon Glass
70f5f17415 alist: Add a function to empty the list
Sometimes it is useful to empty the list without de-allocating any of
the memory used, e.g. when the list will be re-populated immediately
afterwards.

Add a new function for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2024-11-02 11:13:59 -06:00
Simon Glass
83bc5989fc alist: Add for-loop helpers
Add some macros which permit easy iteration through an alist, similar to
those provided by the 'list' implementation.

Signed-off-by: Simon Glass <sjg@chromium.org>
2024-11-02 11:13:59 -06:00
Simon Glass
2ce146a3de alist: Add a way to get the next element
Add a new function which returns the next element after the one
provided, if it exists in the list.

Signed-off-by: Simon Glass <sjg@chromium.org>
2024-11-02 11:13:59 -06:00
Simon Glass
6668d860f7 alist: Expand the comment for alist_get()
Add a better description for this macro.

Signed-off-by: Simon Glass <sjg@chromium.org>
2024-11-02 11:13:59 -06:00
Simon Glass
13bd298499 alist: Add a comment for alist_init_struct()
Comment this macro so that it is clear how to use it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2024-11-02 11:13:59 -06:00
Simon Glass
a8c07ac497 alist: Mention the error condition in alist_add_placeholder()
Update the function comment to note that this function can return NULL
if it runs out of memory.

Signed-off-by: Simon Glass <sjg@chromium.org>
2024-11-02 11:13:59 -06:00
931 changed files with 6603 additions and 10479 deletions

5
.gitignore vendored
View File

@@ -75,6 +75,9 @@ fit-dtb.blob*
/keep-syms-lto.*
/*imx8mimage*
/*imx8mcst*
/drivers/video/u_boot_logo.S
/test/overlay/test-fdt-overlay.dtbo.S
/test/overlay/test-fdt-overlay-stacked.dtbo.S
#
# Generated include files
@@ -83,6 +86,8 @@ fit-dtb.blob*
/include/config.h
/include/config/
/include/generated/
/include/bmp_logo.h
/include/bmp_logo_data.h
# stgit generated dirs
patches-*

View File

@@ -3,6 +3,7 @@
variables:
DEFAULT_TAG: ""
MIRROR_DOCKER: docker.io
SJG_LAB: ""
default:
tags:
@@ -16,6 +17,7 @@ image: ${MIRROR_DOCKER}/trini/u-boot-gitlab-ci-runner:jammy-20240808-21Aug2024
stages:
- testsuites
- test.py
- sjg-lab
- world build
.buildman_and_testpy_template: &buildman_and_testpy_dfn
@@ -521,3 +523,163 @@ coreboot test.py:
TEST_PY_TEST_SPEC: "not sleep"
TEST_PY_ID: "--id qemu"
<<: *buildman_and_testpy_dfn
.lab_template: &lab_dfn
stage: sjg-lab
rules:
- if: $SJG_LAB == "1"
when: always
- if: $SJG_LAB != "1"
when: manual
allow_failure: true
tags: [ 'lab' ]
script:
- if [[ -z "${SJG_LAB}" ]]; then
exit 0;
fi
# Environment:
# SRC - source tree
# OUT - output directory for builds
- export SRC="$(pwd)"
- export OUT="${SRC}/build/${BOARD}"
- export PATH=$PATH:~/bin
- export PATH=$PATH:/vid/software/devel/ubtest/u-boot-test-hooks/bin
# Load it on the device
- ret=0
- echo "role ${ROLE}"
- export strategy="-s uboot -e off"
- export USE_LABGRID_SJG=1
# export verbose="-v"
- ${SRC}/test/py/test.py --role ${ROLE} --build-dir "${OUT}"
--capture=tee-sys -k "not bootstd" || ret=$?
- U_BOOT_BOARD_IDENTITY="${ROLE}" u-boot-test-release || true
- if [[ $ret -ne 0 ]]; then
exit $ret;
fi
artifacts:
when: always
paths:
- "build/${BOARD}/test-log.html"
- "build/${BOARD}/multiplexed_log.css"
expire_in: 1 week
rpi3:
variables:
ROLE: rpi3
<<: *lab_dfn
opi_pc:
variables:
ROLE: opi_pc
<<: *lab_dfn
pcduino3_nano:
variables:
ROLE: pcduino3_nano
<<: *lab_dfn
samus:
variables:
ROLE: samus
<<: *lab_dfn
link:
variables:
ROLE: link
<<: *lab_dfn
jerry:
variables:
ROLE: jerry
<<: *lab_dfn
minnowmax:
variables:
ROLE: minnowmax
<<: *lab_dfn
opi_pc2:
variables:
ROLE: opi_pc2
<<: *lab_dfn
bpi:
variables:
ROLE: bpi
<<: *lab_dfn
rpi2:
variables:
ROLE: rpi2
<<: *lab_dfn
bob:
variables:
ROLE: bob
<<: *lab_dfn
ff3399:
variables:
ROLE: ff3399
<<: *lab_dfn
coral:
variables:
ROLE: coral
<<: *lab_dfn
rpi3z:
variables:
ROLE: rpi3z
<<: *lab_dfn
bbb:
variables:
ROLE: bbb
<<: *lab_dfn
kevin:
variables:
ROLE: kevin
<<: *lab_dfn
pine64:
variables:
ROLE: pine64
<<: *lab_dfn
c4:
variables:
ROLE: c4
<<: *lab_dfn
rpi4:
variables:
ROLE: rpi4
<<: *lab_dfn
rpi0:
variables:
ROLE: rpi0
<<: *lab_dfn
snow:
variables:
ROLE: snow
<<: *lab_dfn
pcduino3:
variables:
ROLE: pcduino3
<<: *lab_dfn
nyan-big:
variables:
ROLE: nyan-big
<<: *lab_dfn
rpi:
variables:
ROLE: rpi
<<: *lab_dfn

View File

@@ -578,6 +578,7 @@ config STACK_SIZE
hex "Define max stack size that can be used by U-Boot"
default 0x4000000 if ARCH_VERSAL_NET || ARCH_VERSAL || ARCH_ZYNQMP
default 0x200000 if MICROBLAZE
default 0x4000 if ARCH_STM32
default 0x1000000
help
Define Max stack size that can be used by U-Boot. This value is used
@@ -765,10 +766,15 @@ choice
config NO_NET
bool "No networking support"
help
Do not include networking support
config NET
bool "Legacy U-Boot networking stack"
imply NETDEVICES
help
Include networking support with U-Boot's internal implementation of
the TCP/IP protocol stack.
config NET_LWIP
bool "Use lwIP for networking stack"

View File

@@ -860,6 +860,7 @@ M: Michal Simek <michal.simek@amd.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git
F: arch/arm/mach-zynqmp/
F: drivers/bootcount/bootcount_zynqmp.c
F: drivers/clk/clk_zynqmp.c
F: driver/firmware/firmware-zynqmp.c
F: drivers/fpga/zynqpl.c
@@ -1551,6 +1552,7 @@ SANDBOX
M: Simon Glass <sjg@chromium.org>
S: Maintained
F: arch/sandbox/
F: configs/sandbox*
F: doc/arch/sandbox.rst
F: drivers/*/*sandbox*.c
F: include/dt-bindings/*/sandbox*.h
@@ -1697,6 +1699,7 @@ T: git https://source.denx.de/u-boot/custodians/u-boot-tpm.git
F: cmd/tpm*
F: drivers/tpm/
F: include/tpm*
F: lib/tpm*
TQ GROUP
#M: Martin Krause <martin.krause@tq-systems.de>

View File

@@ -3,7 +3,7 @@
VERSION = 2025
PATCHLEVEL = 01
SUBLEVEL =
EXTRAVERSION = -rc2
EXTRAVERSION =
NAME =
# *DOCUMENTATION*
@@ -21,7 +21,7 @@ include include/host_arch.h
ifeq ("", "$(CROSS_COMPILE)")
MK_ARCH="${shell uname -m}"
else
MK_ARCH="${shell echo $(CROSS_COMPILE) | sed -n 's/^[[:space:]]*\([^\/]*\/\)*\([^-]*\)-[^[:space:]]*/\2/p'}"
MK_ARCH="${shell echo $(CROSS_COMPILE) | sed -n 's/^\(.*ccache\)\{0,1\}[[:space:]]*\([^\/]*\/\)*\([^-]*\)-[^[:space:]]*/\3/p'}"
endif
unexport HOST_ARCH
ifeq ("x86_64", $(MK_ARCH))
@@ -1398,7 +1398,8 @@ cmd_binman = $(srctree)/tools/binman/binman $(if $(BINMAN_DEBUG),-D) \
--toolpath $(objtree)/tools \
$(if $(BINMAN_VERBOSE),-v$(BINMAN_VERBOSE)) \
build -u -d u-boot.dtb -O . -m \
--allow-missing $(if $(BINMAN_ALLOW_MISSING),--ignore-missing) \
--allow-missing --fake-ext-blobs \
$(if $(BINMAN_ALLOW_MISSING),--ignore-missing) \
-I . -I $(srctree) -I $(srctree)/board/$(BOARDDIR) \
$(foreach f,$(of_list_dirs),-I $(f)) -a of-list=$(of_list) \
$(foreach f,$(BINMAN_INDIRS),-I $(f)) \

View File

@@ -8,6 +8,11 @@ config CREATE_ARCH_SYMLINK
config HAVE_ARCH_IOREMAP
bool
config HAVE_SETJMP
bool
help
The architecture supports setjmp() and longjmp().
config SUPPORT_BIG_ENDIAN
bool
@@ -73,6 +78,7 @@ config ARC
config ARM
bool "ARM architecture"
select HAVE_SETJMP
select ARCH_SUPPORTS_LTO
select CREATE_ARCH_SYMLINK
select HAVE_PRIVATE_LIBGCC if !ARM64
@@ -129,6 +135,7 @@ config PPC
config RISCV
bool "RISC-V architecture"
select CREATE_ARCH_SYMLINK
select HAVE_SETJMP
select SUPPORT_ACPI
select SUPPORT_LITTLE_ENDIAN
select SUPPORT_OF_CONTROL
@@ -154,6 +161,7 @@ config RISCV
config SANDBOX
bool "Sandbox"
select HAVE_SETJMP
select ARCH_SUPPORTS_LTO
select BOARD_LATE_INIT
select BZIP2
@@ -249,6 +257,7 @@ config SH
config X86
bool "x86 architecture"
select HAVE_SETJMP
select SUPPORT_SPL
select SUPPORT_TPL
select SUPPORT_LITTLE_ENDIAN

View File

@@ -190,7 +190,8 @@ dtb-$(CONFIG_ARCH_MVEBU) += \
cn9130-crb-A.dtb \
cn9130-crb-B.dtb \
ac5-98dx35xx-rd.dtb \
ac5-98dx35xx-atl-x240.dtb
ac5-98dx35xx-atl-x240.dtb \
cn9130-atl-x250.dtb
endif
dtb-$(CONFIG_ARCH_SYNQUACER) += synquacer-sc2a11-developerbox.dtb

View File

@@ -1,126 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Broadcom Ltd.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
compatible = "brcm,bcm47622", "brcm,bcmbca";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
CA7_0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x0>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
CA7_1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x1>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
CA7_2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x2>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
CA7_3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x3>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
L2_0: l2-cache0 {
compatible = "cache";
};
};
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
arm,cpu-registers-not-fw-configured;
};
pmu: pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&CA7_0>, <&CA7_1>,
<&CA7_2>, <&CA7_3>;
};
clocks: clocks {
periph_clk: periph-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};
uart_clk: uart-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&periph_clk>;
clock-div = <4>;
clock-mult = <1>;
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
cpu_off = <1>;
cpu_on = <2>;
};
axi@81000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x81000000 0x818000>;
gic: interrupt-controller@1000 {
compatible = "arm,cortex-a7-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x1000 0x1000>,
<0x2000 0x2000>;
};
};
bus@ff800000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xff800000 0x800000>;
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart_clk>, <&uart_clk>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
};
};

View File

@@ -1,128 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Broadcom Ltd.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "brcm,bcm4912", "brcm,bcmbca";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
B53_0: cpu@0 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x0>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
B53_1: cpu@1 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x1>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
B53_2: cpu@2 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x2>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
B53_3: cpu@3 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x3>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
L2_0: l2-cache0 {
compatible = "cache";
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
pmu: pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&B53_0>, <&B53_1>,
<&B53_2>, <&B53_3>;
};
clocks: clocks {
periph_clk: periph-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};
uart_clk: uart-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&periph_clk>;
clock-div = <4>;
clock-mult = <1>;
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
axi@81000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x81000000 0x8000>;
gic: interrupt-controller@1000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
reg = <0x1000 0x1000>,
<0x2000 0x2000>,
<0x4000 0x2000>,
<0x6000 0x2000>;
};
};
bus@ff800000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0xff800000 0x800000>;
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart_clk>, <&uart_clk>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
};
};

View File

@@ -1,110 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Broadcom Ltd.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "brcm,bcm63146", "brcm,bcmbca";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
B53_0: cpu@0 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x0>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
B53_1: cpu@1 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x1>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
L2_0: l2-cache0 {
compatible = "cache";
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
};
pmu: pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&B53_0>, <&B53_1>;
};
clocks: clocks {
periph_clk: periph-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};
uart_clk: uart-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&periph_clk>;
clock-div = <4>;
clock-mult = <1>;
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
axi@81000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x81000000 0x8000>;
gic: interrupt-controller@1000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x1000 0x1000>,
<0x2000 0x2000>,
<0x4000 0x2000>,
<0x6000 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_HIGH)>;
};
};
bus@ff800000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0xff800000 0x800000>;
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart_clk>, <&uart_clk>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
};
};

View File

@@ -1,278 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Philippe Reynes <philippe.reynes@softathome.com>
* Copyright 2022 Broadcom Ltd.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "brcm,bcm63158", "brcm,bcmbca";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
B53_0: cpu@0 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x0>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
B53_1: cpu@1 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x1>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
B53_2: cpu@2 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x2>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
B53_3: cpu@3 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x3>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
L2_0: l2-cache0 {
compatible = "cache";
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
pmu: pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&B53_0>, <&B53_1>,
<&B53_2>, <&B53_3>;
};
clocks {
bootph-all;
periph_clk: periph-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};
hsspi_pll: hsspi-pll {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&periph_clk>;
clock-mult = <2>;
clock-div = <1>;
};
uart_clk: uart-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&periph_clk>;
clock-div = <4>;
clock-mult = <1>;
};
wdt_clk: wdt-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&periph_clk>;
clock-div = <4>;
clock-mult = <1>;
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
axi@81000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x81000000 0x8000>;
gic: interrupt-controller@1000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
reg = <0x1000 0x1000>,
<0x2000 0x2000>,
<0x4000 0x2000>,
<0x6000 0x2000>;
};
};
bus@ff800000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0xff800000 0x800000>;
bootph-all;
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart_clk>, <&uart_clk>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
leds: led-controller@800 {
compatible = "brcm,bcm6858-leds";
reg = <0x800 0xe4>;
status = "disabled";
};
wdt1: watchdog@480 {
compatible = "brcm,bcm6345-wdt";
reg = <0x480 0x14>;
clocks = <&wdt_clk>;
};
wdt2: watchdog@4c0 {
compatible = "brcm,bcm6345-wdt";
reg = <0x4c0 0x14>;
clocks = <&wdt_clk>;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdt1>;
};
gpio0: gpio-controller@500 {
compatible = "brcm,bcm6345-gpio";
reg = <0x500 0x4>,
<0x520 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio1: gpio-controller@504 {
compatible = "brcm,bcm6345-gpio";
reg = <0x504 0x4>,
<0x524 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio2: gpio-controller@508 {
compatible = "brcm,bcm6345-gpio";
reg = <0x508 0x4>,
<0x528 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio3: gpio-controller@50c {
compatible = "brcm,bcm6345-gpio";
reg = <0x50c 0x4>,
<0x52c 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio4: gpio-controller@510 {
compatible = "brcm,bcm6345-gpio";
reg = <0x510 0x4>,
<0x530 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio5: gpio-controller@514 {
compatible = "brcm,bcm6345-gpio";
reg = <0x514 0x4>,
<0x534 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio6: gpio-controller@518 {
compatible = "brcm,bcm6345-gpio";
reg = <0x518 0x4>,
<0x538 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio7: gpio-controller@51c {
compatible = "brcm,bcm6345-gpio";
reg = <0x51c 0x4>,
<0x53c 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
hsspi: spi-controller@1000 {
compatible = "brcm,bcm6328-hsspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1000 0x600>;
clocks = <&hsspi_pll>, <&hsspi_pll>;
clock-names = "hsspi", "pll";
spi-max-frequency = <100000000>;
num-cs = <8>;
status = "disabled";
};
nand: nand-controller@1800 {
compatible = "brcm,nand-bcm63158",
"brcm,brcmnand-v5.0",
"brcm,brcmnand";
reg-names = "nand", "nand-int-base", "nand-cache";
reg = <0x1800 0x180>,
<0x2000 0x10>,
<0x1c00 0x200>;
parameter-page-big-endian = <0>;
status = "disabled";
};
};
};

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@@ -1,120 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Broadcom Ltd.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
compatible = "brcm,bcm63178", "brcm,bcmbca";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
CA7_0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x0>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
CA7_1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x1>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
CA7_2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x2>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
L2_0: l2-cache0 {
compatible = "cache";
};
};
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>;
arm,cpu-registers-not-fw-configured;
};
pmu: pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&CA7_0>, <&CA7_1>,
<&CA7_2>;
};
clocks: clocks {
periph_clk: periph-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};
uart_clk: uart-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&periph_clk>;
clock-div = <4>;
clock-mult = <1>;
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
axi@81000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x81000000 0x8000>;
gic: interrupt-controller@1000 {
compatible = "arm,cortex-a7-gic";
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_HIGH)>;
reg = <0x1000 0x1000>,
<0x2000 0x2000>,
<0x4000 0x2000>,
<0x6000 0x2000>;
};
};
bus@ff800000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xff800000 0x800000>;
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart_clk>, <&uart_clk>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
};
};

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@@ -1,130 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Broadcom Ltd.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
compatible = "brcm,bcm6756", "brcm,bcmbca";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
CA7_0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x0>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
CA7_1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x1>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
CA7_2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x2>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
CA7_3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x3>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
L2_0: l2-cache0 {
compatible = "cache";
};
};
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
arm,cpu-registers-not-fw-configured;
};
pmu: pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&CA7_0>, <&CA7_1>,
<&CA7_2>, <&CA7_3>;
};
clocks: clocks {
periph_clk: periph-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};
uart_clk: uart-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&periph_clk>;
clock-div = <4>;
clock-mult = <1>;
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
axi@81000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x81000000 0x8000>;
gic: interrupt-controller@1000 {
compatible = "arm,cortex-a7-gic";
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
reg = <0x1000 0x1000>,
<0x2000 0x2000>,
<0x4000 0x2000>,
<0x6000 0x2000>;
};
};
bus@ff800000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xff800000 0x800000>;
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart_clk>, <&uart_clk>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
};
};

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@@ -1,128 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Broadcom Ltd.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "brcm,bcm6813", "brcm,bcmbca";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
B53_0: cpu@0 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x0>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
B53_1: cpu@1 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x1>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
B53_2: cpu@2 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x2>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
B53_3: cpu@3 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x3>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
L2_0: l2-cache0 {
compatible = "cache";
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
pmu: pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&B53_0>, <&B53_1>,
<&B53_2>, <&B53_3>;
};
clocks: clocks {
periph_clk: periph-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};
uart_clk: uart-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&periph_clk>;
clock-div = <4>;
clock-mult = <1>;
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
axi@81000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x81000000 0x8000>;
gic: interrupt-controller@1000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
reg = <0x1000 0x1000>,
<0x2000 0x2000>,
<0x4000 0x2000>,
<0x6000 0x2000>;
};
};
bus@ff800000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0xff800000 0x800000>;
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart_clk>, <&uart_clk>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
};
};

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@@ -1,257 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2022 Philippe Reynes <philippe.reynes@softathome.com>
* Copyright 2022 Broadcom Ltd.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
compatible = "brcm,bcm6855", "brcm,bcmbca";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
CA7_0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x0>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
CA7_1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x1>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
CA7_2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x2>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
L2_0: l2-cache0 {
compatible = "cache";
};
};
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>;
arm,cpu-registers-not-fw-configured;
};
pmu: pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&CA7_0>, <&CA7_1>, <&CA7_2>;
};
clocks: clocks {
bootph-all;
periph_clk: periph-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};
uart_clk: uart-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&periph_clk>;
clock-div = <4>;
clock-mult = <1>;
};
hsspi_pll: hsspi-pll {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&periph_clk>;
clock-mult = <2>;
clock-div = <1>;
};
wdt_clk: wdt-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&periph_clk>;
clock-div = <4>;
clock-mult = <1>;
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
axi@81000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x81000000 0x8000>;
gic: interrupt-controller@1000 {
compatible = "arm,cortex-a7-gic";
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_HIGH)>;
reg = <0x1000 0x1000>,
<0x2000 0x2000>,
<0x4000 0x2000>,
<0x6000 0x2000>;
};
};
bus@ff800000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xff800000 0x800000>;
bootph-all;
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart_clk>, <&uart_clk>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
wdt1: watchdog@480 {
compatible = "brcm,bcm6345-wdt";
reg = <0x480 0x14>;
clocks = <&wdt_clk>;
};
wdt2: watchdog@4c0 {
compatible = "brcm,bcm6345-wdt";
reg = <0x4c0 0x14>;
clocks = <&wdt_clk>;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdt1>;
};
gpio0: gpio-controller@500 {
compatible = "brcm,bcm6345-gpio";
reg = <0x500 0x4>,
<0x520 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio1: gpio-controller@504 {
compatible = "brcm,bcm6345-gpio";
reg = <0x504 0x4>,
<0x524 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio2: gpio-controller@508 {
compatible = "brcm,bcm6345-gpio";
reg = <0x508 0x4>,
<0x528 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio3: gpio-controller@50c {
compatible = "brcm,bcm6345-gpio";
reg = <0x50c 0x4>,
<0x52c 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio4: gpio-controller@510 {
compatible = "brcm,bcm6345-gpio";
reg = <0x510 0x4>,
<0x530 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio5: gpio-controller@514 {
compatible = "brcm,bcm6345-gpio";
reg = <0x514 0x4>,
<0x534 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio6: gpio-controller@518 {
compatible = "brcm,bcm6345-gpio";
reg = <0x518 0x4>,
<0x538 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio7: gpio-controller@51c {
compatible = "brcm,bcm6345-gpio";
reg = <0x51c 0x4>,
<0x53c 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
nand: nand-controller@1800 {
compatible = "brcm,nand-bcm6753",
"brcm,brcmnand-v5.0",
"brcm,brcmnand";
reg-names = "nand", "nand-int-base", "nand-cache";
reg = <0x1800 0x180>,
<0x2000 0x10>,
<0x1c00 0x200>;
parameter-page-big-endian = <0>;
status = "disabled";
};
leds: led-controller@3000 {
compatible = "brcm,bcm6753-leds";
reg = <0x3000 0x3480>;
status = "disabled";
};
};
};

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@@ -1,253 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2020 Philippe Reynes <philippe.reynes@softathome.com>
* Copyright 2022 Broadcom Ltd.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "brcm,bcm6856", "brcm,bcmbca";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
B53_0: cpu@0 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x0>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
B53_1: cpu@1 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x1>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
L2_0: l2-cache0 {
compatible = "cache";
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
};
pmu: pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&B53_0>, <&B53_1>;
};
clocks: clocks {
bootph-all;
periph_clk:periph-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};
hsspi_pll: hsspi-pll {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&periph_clk>;
clock-mult = <2>;
clock-div = <1>;
};
wdt_clk: wdt-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&periph_clk>;
clock-div = <4>;
clock-mult = <1>;
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
axi@81000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x81000000 0x8000>;
gic: interrupt-controller@1000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x1000 0x1000>, /* GICD */
<0x2000 0x2000>, /* GICC */
<0x4000 0x2000>, /* GICH */
<0x6000 0x2000>; /* GICV */
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_HIGH)>;
};
};
bus@ff800000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0xff800000 0x800000>;
bootph-all;
uart0: serial@640 {
compatible = "brcm,bcm6345-uart";
reg = <0x640 0x18>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&periph_clk>;
clock-names = "refclk";
status = "disabled";
};
wdt1: watchdog@480 {
compatible = "brcm,bcm6345-wdt";
reg = <0x480 0x14>;
clocks = <&wdt_clk>;
};
wdt2: watchdog@4c0 {
compatible = "brcm,bcm6345-wdt";
reg = <0x4c0 0x14>;
clocks = <&wdt_clk>;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdt1>;
};
leds: led-controller@800 {
compatible = "brcm,bcm6858-leds";
reg = <0x800 0xe4>;
status = "disabled";
};
gpio0: gpio-controller@500 {
compatible = "brcm,bcm6345-gpio";
reg = <0x500 0x4>,
<0x520 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio1: gpio-controller@504 {
compatible = "brcm,bcm6345-gpio";
reg = <0x504 0x4>,
<0x524 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio2: gpio-controller@508 {
compatible = "brcm,bcm6345-gpio";
reg = <0x508 0x4>,
<0x528 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio3: gpio-controller@50c {
compatible = "brcm,bcm6345-gpio";
reg = <0x50c 0x4>,
<0x52c 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio4: gpio-controller@510 {
compatible = "brcm,bcm6345-gpio";
reg = <0x510 0x4>,
<0x530 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio5: gpio-controller@514 {
compatible = "brcm,bcm6345-gpio";
reg = <0x514 0x4>,
<0x534 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio6: gpio-controller@518 {
compatible = "brcm,bcm6345-gpio";
reg = <0x518 0x4>,
<0x538 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio7: gpio-controller@51c {
compatible = "brcm,bcm6345-gpio";
reg = <0x51c 0x4>,
<0x53c 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
hsspi: spi-controller@1000 {
compatible = "brcm,bcm6328-hsspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1000 0x600>;
clocks = <&hsspi_pll>, <&hsspi_pll>;
clock-names = "hsspi", "pll";
spi-max-frequency = <100000000>;
num-cs = <8>;
status = "disabled";
};
nand: nand-controller@1800 {
compatible = "brcm,nand-bcm68360",
"brcm,brcmnand-v5.0",
"brcm,brcmnand";
reg-names = "nand", "nand-int-base", "nand-cache";
reg = <0x1800 0x180>,
<0x2000 0x10>,
<0x1c00 0x200>;
parameter-page-big-endian = <0>;
status = "disabled";
};
};
};

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@@ -1,272 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com>
* Copyright 2022 Broadcom Ltd.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "brcm,bcm6858", "brcm,bcmbca";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
B53_0: cpu@0 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x0>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
B53_1: cpu@1 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x1>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
B53_2: cpu@2 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x2>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
B53_3: cpu@3 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x3>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
L2_0: l2-cache0 {
compatible = "cache";
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
pmu: pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&B53_0>, <&B53_1>,
<&B53_2>, <&B53_3>;
};
clocks {
bootph-all;
periph_clk: periph_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};
hsspi_pll: hsspi-pll {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&periph_clk>;
clock-mult = <2>;
clock-div = <1>;
};
wdt_clk: wdt-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&periph_clk>;
clock-div = <4>;
clock-mult = <1>;
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
axi@81000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x81000000 0x8000>;
gic: interrupt-controller@1000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x1000 0x1000>, /* GICD */
<0x2000 0x2000>, /* GICC */
<0x4000 0x2000>, /* GICH */
<0x6000 0x2000>; /* GICV */
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_HIGH)>;
};
};
bus@ff800000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0xff800000 0x800000>;
bootph-all;
uart0: serial@640 {
compatible = "brcm,bcm6345-uart";
reg = <0x640 0x18>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&periph_clk>;
clock-names = "refclk";
status = "disabled";
};
leds: led-controller@800 {
compatible = "brcm,bcm6858-leds";
reg = <0x800 0xe4>;
status = "disabled";
};
wdt1: watchdog@2780 {
compatible = "brcm,bcm6345-wdt";
reg = <0x2780 0x14>;
clocks = <&wdt_clk>;
};
wdt2: watchdog@27c0 {
compatible = "brcm,bcm6345-wdt";
reg = <0x27c0 0x14>;
clocks = <&wdt_clk>;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdt1>;
};
gpio0: gpio-controller@500 {
compatible = "brcm,bcm6345-gpio";
reg = <0x500 0x4>,
<0x520 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio1: gpio-controller@504 {
compatible = "brcm,bcm6345-gpio";
reg = <0x504 0x4>,
<0x524 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio2: gpio-controller@508 {
compatible = "brcm,bcm6345-gpio";
reg = <0x508 0x4>,
<0x528 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio3: gpio-controller@50c {
compatible = "brcm,bcm6345-gpio";
reg = <0x50c 0x4>,
<0x52c 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio4: gpio-controller@510 {
compatible = "brcm,bcm6345-gpio";
reg = <0x510 0x4>,
<0x530 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio5: gpio-controller@514 {
compatible = "brcm,bcm6345-gpio";
reg = <0x514 0x4>,
<0x534 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio6: gpio-controller@518 {
compatible = "brcm,bcm6345-gpio";
reg = <0x518 0x4>,
<0x538 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio7: gpio-controller@51c {
compatible = "brcm,bcm6345-gpio";
reg = <0x51c 0x4>,
<0x53c 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
hsspi: spi-controller@1000 {
compatible = "brcm,bcm6328-hsspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1000 0x600>;
clocks = <&hsspi_pll>, <&hsspi_pll>;
clock-names = "hsspi", "pll";
spi-max-frequency = <100000000>;
num-cs = <8>;
status = "disabled";
};
nand: nand-controller@1800 {
compatible = "brcm,nand-bcm6858",
"brcm,brcmnand-v5.0",
"brcm,brcmnand";
reg-names = "nand", "nand-int-base", "nand-cache";
reg = <0x1800 0x180>,
<0x2000 0x10>,
<0x1c00 0x200>;
parameter-page-big-endian = <0>;
status = "disabled";
};
};
};

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@@ -1,111 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Broadcom Ltd.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
compatible = "brcm,bcm6878", "brcm,bcmbca";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
CA7_0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x0>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
CA7_1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x1>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
L2_0: l2-cache0 {
compatible = "cache";
};
};
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
arm,cpu-registers-not-fw-configured;
};
pmu: pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&CA7_0>, <&CA7_1>;
};
clocks: clocks {
periph_clk: periph-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};
uart_clk: uart-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&periph_clk>;
clock-div = <4>;
clock-mult = <1>;
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
axi@81000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x81000000 0x8000>;
gic: interrupt-controller@1000 {
compatible = "arm,cortex-a7-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x1000 0x1000>,
<0x2000 0x2000>,
<0x4000 0x2000>,
<0x6000 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_HIGH)>;
};
};
bus@ff800000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xff800000 0x800000>;
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart_clk>, <&uart_clk>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
};
};

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@@ -1,30 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2019 Broadcom Ltd.
*/
/dts-v1/;
#include "bcm47622.dtsi"
/ {
model = "Broadcom BCM947622 Reference Board";
compatible = "brcm,bcm947622", "brcm,bcm47622", "brcm,bcmbca";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x08000000>;
};
};
&uart0 {
status = "okay";
};

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@@ -1,30 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Broadcom Ltd.
*/
/dts-v1/;
#include "bcm4912.dtsi"
/ {
model = "Broadcom BCM94912 Reference Board";
compatible = "brcm,bcm94912", "brcm,bcm4912", "brcm,bcmbca";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x08000000>;
};
};
&uart0 {
status = "okay";
};

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@@ -1,30 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Broadcom Ltd.
*/
/dts-v1/;
#include "bcm63146.dtsi"
/ {
model = "Broadcom BCM963146 Reference Board";
compatible = "brcm,bcm963146", "brcm,bcm63146", "brcm,bcmbca";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x08000000>;
};
};
&uart0 {
status = "okay";
};

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@@ -1,30 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Broadcom Ltd.
*/
/dts-v1/;
#include "bcm63158.dtsi"
/ {
model = "Broadcom BCM963158 Reference Board";
compatible = "brcm,bcm963158", "brcm,bcm63158", "brcm,bcmbca";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x08000000>;
};
};
&uart0 {
status = "okay";
};

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@@ -1,30 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2019 Broadcom Ltd.
*/
/dts-v1/;
#include "bcm63178.dtsi"
/ {
model = "Broadcom BCM963178 Reference Board";
compatible = "brcm,bcm963178", "brcm,bcm63178", "brcm,bcmbca";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x08000000>;
};
};
&uart0 {
status = "okay";
};

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@@ -1,30 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2019 Broadcom Ltd.
*/
/dts-v1/;
#include "bcm6756.dtsi"
/ {
model = "Broadcom BCM96756 Reference Board";
compatible = "brcm,bcm96756", "brcm,bcm6756", "brcm,bcmbca";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x08000000>;
};
};
&uart0 {
status = "okay";
};

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@@ -1,30 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Broadcom Ltd.
*/
/dts-v1/;
#include "bcm6813.dtsi"
/ {
model = "Broadcom BCM96813 Reference Board";
compatible = "brcm,bcm96813", "brcm,bcm6813", "brcm,bcmbca";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x08000000>;
};
};
&uart0 {
status = "okay";
};

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@@ -1,30 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Broadcom Ltd.
*/
/dts-v1/;
#include "bcm6855.dtsi"
/ {
model = "Broadcom BCM96855 Reference Board";
compatible = "brcm,bcm96855", "brcm,bcm6855", "brcm,bcmbca";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x08000000>;
};
};
&uart0 {
status = "okay";
};

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@@ -1,30 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Broadcom Ltd.
*/
/dts-v1/;
#include "bcm6856.dtsi"
/ {
model = "Broadcom BCM96856 Reference Board";
compatible = "brcm,bcm96856", "brcm,bcm6856", "brcm,bcmbca";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x08000000>;
};
};
&uart0 {
status = "okay";
};

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@@ -1,30 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Broadcom Ltd.
*/
/dts-v1/;
#include "bcm6858.dtsi"
/ {
model = "Broadcom BCM96858 Reference Board";
compatible = "brcm,bcm96858", "brcm,bcm6858", "brcm,bcmbca";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x08000000>;
};
};
&uart0 {
status = "okay";
};

View File

@@ -1,30 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2019 Broadcom Ltd.
*/
/dts-v1/;
#include "bcm6878.dtsi"
/ {
model = "Broadcom BCM96878 Reference Board";
compatible = "brcm,bcm96878", "brcm,bcm6878", "brcm,bcmbca";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x08000000>;
};
};
&uart0 {
status = "okay";
};

View File

@@ -0,0 +1,274 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2024 Allied Telesis Labs
*/
#include "cn9130.dtsi"
/ {
model = "Allied Telesis x250";
compatible = "alliedtelesis,x250",
"marvell,cn9130",
"marvell,armada-ap806-quad",
"marvell,armada-ap806";
aliases {
serial0 = &uart0;
i2c0 = &cp0_i2c0;
i2c1 = &cp0_i2c1;
};
chosen {
stdout-path = "serial0:115200n8";
};
gpio-leds {
compatible = "gpio-leds";
fault {
label = "fault:red";
gpios = <&cp0_gpio1 9 GPIO_ACTIVE_LOW>;
default-state = "on";
};
};
};
/*
* AP related configuration
*/
&ap_pinctl {
/* AP_MPP Pins:
* GPIO & NC [0-6,9-10,12]
* UART0 [11,19]
* UART1 [7,8]
* Note: The x250-28XTm PT1 units has the console port wired
* to the second uart pins (UART1). This was fixed in all
* subsequent models.
* Here we choose to configure the pin control for both
* uarts to cater for either unit.
*/
/* 0 1 2 3 4 5 6 7 8 9 */
pin-func = < 0 0 0 0 0 0 0 3 3 0
0 3 0 0 0 0 0 0 0 3 >;
};
&ap_gpio0 {
pp-reset {
gpio-hog;
gpios = <0 GPIO_ACTIVE_LOW>;
output-high;
line-name = "pp-reset";
};
};
/*
* CP related configuration
*/
&cp0_pinctl {
/* MPP Bus:
* [0-1] DEV
* [2-8] GPIO
* [9] DEV
* [10-12] GPIO
* [13] ND_RB
* [14] GPIO
* [15-28] DEV
* [29-30] GPIO
* [31] DEV
* [32-34] GPIO
* [35-36] I2C1
* [37-38] I2C0
* [39-55] GPIO
* [56-60] SPI
* [61-62] GPIO
*/
/* 0 1 2 3 4 5 6 7 8 9 */
pin-func = < 1 1 0 0 0 0 0 0 0 1
0 0 0 2 0 1 1 1 1 1
1 1 1 1 1 1 1 1 1 0
0 1 0 0 0 2 2 2 2 0
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 6 6 6 6
6 0 0>;
cp0_i2c0_pins: cp0-i2c-pins-0 {
marvell,pins = <37 38>;
marvell,function = <2>;
};
cp0_i2c0_gpio_pins: cp0-i2c-gpio-pins-0 {
marvell,pins = <37 38>;
marvell,function = <0>;
};
cp0_i2c1_pins: cp0-i2c-pins-1 {
marvell,pins = <35 36>;
marvell,function = <2>;
};
cp0_nand_pins: cp0-nand-pins {
marvell,pins = <0 1 9 15 16 17 18 19 20 21 22 23 24 25 26 27 28 31>;
marvell,function = <1>;
};
cp0_nand_rb: cp0-nand-rb {
marvell,pins = <13>;
marvell,function = <2>;
};
cp0_spi0_pins: cp0-spi-pins-0 {
marvell,pins = <56 57 58 59 60>;
marvell,function = <6>;
};
};
&cp0_comphy {
phy0 {
phy-type = <COMPHY_TYPE_PEX0>;
};
phy1 {
phy-type = <COMPHY_TYPE_IGNORE>;
};
phy2 {
phy-type = <COMPHY_TYPE_IGNORE>;
};
phy3 {
phy-type = <COMPHY_TYPE_IGNORE>;
};
phy4 {
phy-type = <COMPHY_TYPE_IGNORE>;
};
phy5 {
phy-type = <COMPHY_TYPE_IGNORE>;
};
};
&cp0_pcie0 {
num-lanes = <1>;
/* non-prefetchable memory */
ranges =<0x82000000 0 0xc0000000 0 0xc0000000 0 0x2000000>;
status = "disabled";
};
&uart0 {
status = "okay";
};
&uart1 {
clock-frequency = <200000000>;
};
&cp0_utmi0 {
status = "okay";
};
&cp0_usb3_0 {
status = "okay";
};
&cp0_spi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp0_spi0_pins>;
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <50000000>;
m25p,fast-read;
};
};
&cp0_nand {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp0_nand_pins &cp0_nand_rb>;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
nand-timing-mode = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@user {
reg = <0x00000000 0x10000000>;
label = "user";
};
};
};
&cp0_gpio0
{
nand-protect {
gpio-hog;
gpios = <29 GPIO_ACTIVE_LOW>;
output-low;
line-name = "nand-protect";
};
};
&cp0_gpio1
{
usb-en {
gpio-hog;
gpios = <0 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "usb-en";
};
phy-reset {
gpio-hog;
gpios = <21 GPIO_ACTIVE_LOW>;
output-high;
line-name = "phy-reset";
};
};
&cp0_i2c0 {
status = "okay";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&cp0_i2c0_pins>;
pinctrl-1 = <&cp0_i2c0_gpio_pins>;
scl-gpios = <&cp0_gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&cp0_gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
mux@71 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "nxp,pca9546";
reg = <0x71>;
i2c-mux-idle-disconnect;
reset-gpios = <&cp0_gpio1 19 GPIO_ACTIVE_LOW>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
hwmon@2e {
compatible = "adi,adt7476";
reg = <0x2e>;
};
rtc@68 {
compatible = "adi,max31331";
reg = <0x68>;
};
};
};
};
&cp0_i2c1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp0_i2c1_pins>;
};

View File

@@ -3,17 +3,6 @@
* Copyright (c) 2023 Linaro Ltd.
*/
&soc {
/* TODO: Remove this node once it appears in upstream dts */
trng: rng@12081400 {
compatible = "samsung,exynos850-trng";
reg = <0x12081400 0x100>;
clocks = <&cmu_core CLK_GOUT_SSS_ACLK>,
<&cmu_core CLK_GOUT_SSS_PCLK>;
clock-names = "secss", "pclk";
};
};
&pmu_system_controller {
bootph-all;
samsung,uart-debug-1;

View File

@@ -203,3 +203,7 @@
&sysclk {
bootph-all;
};
&usb0 {
dr_mode = "host";
};

View File

@@ -16,6 +16,12 @@
dmo,ram-coding-gpios = <&gpio2 8 0>, <&gpio2 1 0>, <&gpio2 0 0>;
};
clk_pcie100: clk-pcie100 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
@@ -35,6 +41,15 @@
bootph-pre-ram;
};
&pcie_phy {
clocks = <&clk_pcie100>;
};
&pcie0 {
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
<&clk_pcie100>;
};
&pinctrl_hog_sbc {
bootph-pre-ram;
};
@@ -77,6 +92,7 @@
&gpio2 {
bootph-pre-ram;
bootph-some-ram;
dsi-reset-hog {
bootph-pre-ram;
@@ -144,8 +160,17 @@
bootph-pre-ram;
};
&usbmisc1 {
bootph-pre-ram;
};
&usbphynop1 {
bootph-pre-ram;
};
&usbotg1 {
dr_mode = "peripheral";
bootph-pre-ram;
};
&usdhc2 {

View File

@@ -68,6 +68,11 @@
bootph-all;
};
&osc_32k {
bootph-pre-ram;
bootph-all;
};
#ifdef CONFIG_FSL_CAAM
&sec_jr0 {
bootph-pre-ram;

View File

@@ -64,6 +64,7 @@
&gpio3 {
bootph-pre-ram;
bootph-some-ram;
bl-enable-hog {
bootph-pre-ram;
@@ -92,6 +93,7 @@
&gpio4 {
bootph-pre-ram;
bootph-some-ram;
dsi-reset-hog {
bootph-pre-ram;

View File

@@ -301,6 +301,54 @@
description = "U-Boot for phyCORE-AM62x";
};
som-no-rtc {
description = "k3-am6xx-phycore-disable-rtc";
type = "flat_dt";
compression = "none";
load = <0x8F000000>;
arch = "arm";
blob-ext {
filename = "dts/upstream/src/arm64/ti/k3-am6xx-phycore-disable-rtc.dtbo";
};
};
som-no-spi {
description = "k3-am6xx-phycore-disable-spi-nor";
type = "flat_dt";
compression = "none";
load = <0x8F001000>;
arch = "arm";
blob-ext {
filename = "dts/upstream/src/arm64/ti/k3-am6xx-phycore-disable-spi-nor.dtbo";
};
};
som-no-eth {
description = "k3-am6xx-phycore-disable-eth-phy";
type = "flat_dt";
compression = "none";
load = <0x8F002000>;
arch = "arm";
blob-ext {
filename = "dts/upstream/src/arm64/ti/k3-am6xx-phycore-disable-eth-phy.dtbo";
};
};
som-qspi {
description = "k3-am6xx-phycore-qspi-nor";
type = "flat_dt";
compression = "none";
load = <0x8F003000>;
arch = "arm";
blob-ext {
filename = "dts/upstream/src/arm64/ti/k3-am6xx-phycore-qspi-nor.dtbo";
};
};
fdt-0 {
description = "k3-am625-phyboard-lyra-rdk";
type = "flat_dt";
@@ -325,7 +373,11 @@
conf-0 {
description = "k3-am625-phyboard-lyra-rdk";
firmware = "uboot";
loadables = "uboot";
loadables = "uboot",
"som-no-rtc",
"som-no-spi",
"som-no-eth",
"som-qspi";
fdt = "fdt-0";
};
};

View File

@@ -344,6 +344,54 @@
description = "U-Boot for AM64 board";
};
som-no-rtc {
description = "k3-am6xx-phycore-disable-rtc";
type = "flat_dt";
compression = "none";
load = <0x8F000000>;
arch = "arm";
blob-ext {
filename = "dts/upstream/src/arm64/ti/k3-am6xx-phycore-disable-rtc.dtbo";
};
};
som-no-spi {
description = "k3-am6xx-phycore-disable-spi-nor";
type = "flat_dt";
compression = "none";
load = <0x8F001000>;
arch = "arm";
blob-ext {
filename = "dts/upstream/src/arm64/ti/k3-am6xx-phycore-disable-spi-nor.dtbo";
};
};
som-no-eth {
description = "k3-am6xx-phycore-disable-eth-phy";
type = "flat_dt";
compression = "none";
load = <0x8F002000>;
arch = "arm";
blob-ext {
filename = "dts/upstream/src/arm64/ti/k3-am6xx-phycore-disable-eth-phy.dtbo";
};
};
som-qspi {
description = "k3-am6xx-phycore-qspi-nor";
type = "flat_dt";
compression = "none";
load = <0x8F003000>;
arch = "arm";
blob-ext {
filename = "dts/upstream/src/arm64/ti/k3-am6xx-phycore-qspi-nor.dtbo";
};
};
fdt-0 {
description = "k3-am642-phyboard-electra-rdk";
type = "flat_dt";
@@ -368,7 +416,11 @@
conf-0 {
description = "k3-am642-phyboard-electra-rdk";
firmware = "uboot";
loadables = "uboot";
loadables = "uboot",
"som-no-rtc",
"som-no-spi",
"som-no-eth",
"som-qspi";
fdt = "fdt-0";
};
};

View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source extras for U-Boot on RCar R8A7790 SoC
* Device Tree Source extras for U-Boot on R-Car R8A7790 SoC
*
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
*/

View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source extras for U-Boot on RCar R8A7791 SoC
* Device Tree Source extras for U-Boot on R-Car R8A7791 SoC
*
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
*/

View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source extras for U-Boot on RCar R8A7792 SoC
* Device Tree Source extras for U-Boot on R-Car R8A7792 SoC
*
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
*/

View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source extras for U-Boot on RCar R8A7793 SoC
* Device Tree Source extras for U-Boot on R-Car R8A7793 SoC
*
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
*/

View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source extras for U-Boot on RCar R8A7794 SoC
* Device Tree Source extras for U-Boot on R-Car R8A7794 SoC
*
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
*/

View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source extras for U-Boot on RCar R8A7795 SoC
* Device Tree Source extras for U-Boot on R-Car R8A7795 SoC
*
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
*/

View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source extras for U-Boot on RCar R8A7796 SoC
* Device Tree Source extras for U-Boot on R-Car R8A7796 SoC
*
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
*/

View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source extras for U-Boot on RCar R8A77965 SoC
* Device Tree Source extras for U-Boot on R-Car R8A77965 SoC
*
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
*/

View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source extras for U-Boot on RCar R8A77970 SoC
* Device Tree Source extras for U-Boot on R-Car R8A77970 SoC
*
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
*/

View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source extras for U-Boot on RCar R8A77980 SoC
* Device Tree Source extras for U-Boot on R-Car R8A77980 SoC
*
* Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com>
*/

View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source extras for U-Boot on RCar R8A77990 SoC
* Device Tree Source extras for U-Boot on R-Car R8A77990 SoC
*
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
*/

View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source extras for U-Boot on RCar R8A77995 SoC
* Device Tree Source extras for U-Boot on R-Car R8A77995 SoC
*
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
*/

View File

@@ -13,6 +13,14 @@
};
};
&avb1 {
status = "disabled";
};
&avb2 {
status = "disabled";
};
&rpc {
flash@0 {
spi-tx-bus-width = <1>;

View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source extras for U-Boot on RCar Gen3
* Device Tree Source extras for U-Boot on R-Car Gen3
*
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
*/

0
arch/arm/dts/socfpga_stratix10.dtsi Executable file → Normal file
View File

0
arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi Executable file → Normal file
View File

0
arch/arm/dts/socfpga_stratix10_socdk.dts Executable file → Normal file
View File

View File

@@ -1,308 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) 2024 Marek Vasut <marex@denx.de>
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/mfd/st,stpmic1.h>
#include <dt-bindings/regulator/st,stm32mp13-regulator.h>
#include "stm32mp13-pinctrl.dtsi"
/ {
model = "DH electronics STM32MP13xx DHCOR SoM";
compatible = "dh,stm32mp131a-dhcor-som",
"st,stm32mp131";
aliases {
mmc0 = &sdmmc2;
mmc1 = &sdmmc1;
serial0 = &uart4;
serial1 = &uart7;
rtc0 = &rv3032;
spi0 = &qspi;
};
memory@c0000000 {
device_type = "memory";
reg = <0xc0000000 0x20000000>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
optee@dd000000 {
reg = <0xdd000000 0x3000000>;
no-map;
};
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpiof 12 GPIO_ACTIVE_LOW>;
};
vin: vin {
compatible = "regulator-fixed";
regulator-name = "vin";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
};
&i2c3 {
i2c-scl-rising-time-ns = <96>;
i2c-scl-falling-time-ns = <3>;
clock-frequency = <400000>;
status = "okay";
/* spare dmas for other usage */
/delete-property/dmas;
/delete-property/dma-names;
pmic: stpmic@33 {
compatible = "st,stpmic1";
reg = <0x33>;
interrupts-extended = <&gpioi 3 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <2>;
status = "okay";
regulators {
compatible = "st,stpmic1-regulators";
ldo1-supply = <&vin>;
ldo2-supply = <&vin>;
ldo3-supply = <&vin>;
ldo4-supply = <&vin>;
ldo5-supply = <&vin>;
ldo6-supply = <&vin>;
pwr_sw1-supply = <&bst_out>;
pwr_sw2-supply = <&bst_out>;
vddcpu: buck1 { /* VDD_CPU_1V2 */
regulator-name = "vddcpu";
regulator-min-microvolt = <1250000>;
regulator-max-microvolt = <1250000>;
regulator-always-on;
regulator-initial-mode = <0>;
regulator-over-current-protection;
};
vdd_ddr: buck2 { /* VDD_DDR_1V35 */
regulator-name = "vdd_ddr";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-initial-mode = <0>;
regulator-over-current-protection;
};
vdd: buck3 { /* VDD_3V3_1V8 */
regulator-name = "vdd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-initial-mode = <0>;
regulator-over-current-protection;
};
vddcore: buck4 { /* VDD_CORE_1V2 */
regulator-name = "vddcore";
regulator-min-microvolt = <1250000>;
regulator-max-microvolt = <1250000>;
regulator-always-on;
regulator-initial-mode = <0>;
regulator-over-current-protection;
};
vdd_adc: ldo1 { /* VDD_ADC_1V8 */
regulator-name = "vdd_adc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
interrupts = <IT_CURLIM_LDO1 0>;
};
vdd_ldo2: ldo2 { /* LDO2_OUT_1V8 */
regulator-name = "vdd_ldo2";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
interrupts = <IT_CURLIM_LDO2 0>;
};
vdd_ldo3: ldo3 { /* LDO3_OUT */
regulator-name = "vdd_ldo3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
interrupts = <IT_CURLIM_LDO3 0>;
};
vdd_usb: ldo4 { /* VDD_USB_3V3 */
regulator-name = "vdd_usb";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
interrupts = <IT_CURLIM_LDO4 0>;
};
vdd_sd: ldo5 { /* VDD_SD_3V3_1V8 */
regulator-name = "vdd_sd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
interrupts = <IT_CURLIM_LDO5 0>;
};
vdd_sd2: ldo6 { /* VDD_SD2_3V3_1V8 */
regulator-name = "vdd_sd2";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
interrupts = <IT_CURLIM_LDO6 0>;
};
vref_ddr: vref_ddr { /* VREF_DDR_0V675 */
regulator-name = "vref_ddr";
regulator-always-on;
};
bst_out: boost { /* BST_OUT_5V2 */
regulator-name = "bst_out";
};
vbus_otg: pwr_sw1 {
regulator-name = "vbus_otg";
interrupts = <IT_OCP_OTG 0>;
};
vbus_sw: pwr_sw2 {
regulator-name = "vbus_sw";
interrupts = <IT_OCP_SWOUT 0>;
regulator-active-discharge = <1>;
};
};
onkey {
compatible = "st,stpmic1-onkey";
interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 1>;
interrupt-names = "onkey-falling", "onkey-rising";
status = "okay";
};
watchdog {
compatible = "st,stpmic1-wdt";
status = "disabled";
};
};
eeprom0: eeprom@50 {
compatible = "atmel,24c256"; /* ST M24256 */
reg = <0x50>;
pagesize = <64>;
};
rv3032: rtc@51 {
compatible = "microcrystal,rv3032";
reg = <0x51>;
interrupts-extended = <&gpioi 0 IRQ_TYPE_EDGE_FALLING>;
};
};
&iwdg2 {
timeout-sec = <32>;
status = "okay";
};
&qspi {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qspi_clk_pins_a
&qspi_bk1_pins_a
&qspi_cs1_pins_a>;
pinctrl-1 = <&qspi_clk_sleep_pins_a
&qspi_bk1_sleep_pins_a
&qspi_cs1_sleep_pins_a>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
flash0: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>;
#address-cells = <1>;
#size-cells = <1>;
};
};
/* Console UART */
&uart4 {
pinctrl-names = "default", "sleep", "idle";
pinctrl-0 = <&uart4_pins_b>;
pinctrl-1 = <&uart4_sleep_pins_b>;
pinctrl-2 = <&uart4_idle_pins_b>;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};
/* Bluetooth */
&uart7 {
pinctrl-names = "default", "sleep", "idle";
pinctrl-0 = <&uart7_pins_a>;
pinctrl-1 = <&uart7_sleep_pins_a>;
pinctrl-2 = <&uart7_idle_pins_a>;
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "infineon,cyw43439-bt", "brcm,bcm4329-bt";
max-speed = <3000000>;
device-wakeup-gpios = <&gpiog 9 GPIO_ACTIVE_HIGH>;
shutdown-gpios = <&gpioi 2 GPIO_ACTIVE_HIGH>;
};
};
/* SDIO WiFi */
&sdmmc1 {
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>;
pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_clk_pins_a>;
pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
bus-width = <4>;
cap-power-off-card;
keep-power-in-suspend;
non-removable;
st,neg-edge;
vmmc-supply = <&vdd>;
mmc-pwrseq = <&sdio_pwrseq>;
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
brcmf: bcrmf@1 { /* muRata 1YN */
reg = <1>;
compatible = "infineon,cyw43439-fmac", "brcm,bcm4329-fmac";
interrupt-parent = <&gpioe>;
interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "host-wake";
};
};
/* eMMC */
&sdmmc2 {
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a &sdmmc2_clk_pins_a>;
pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a &sdmmc2_clk_pins_a>;
pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>;
bus-width = <8>;
mmc-ddr-3_3v;
no-sd;
no-sdio;
non-removable;
st,neg-edge;
vmmc-supply = <&vdd>;
vqmmc-supply = <&vdd>;
status = "okay";
};

View File

@@ -186,6 +186,9 @@
bootph-all;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "hse", "hsi", "csi", "lse", "lsi";
clocks = <&clk_hse>, <&clk_hsi>, <&clk_csi>,
<&clk_lse>, <&clk_lsi>;
};
&usart1 {

View File

@@ -1,30 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
/*
* Copyright (C) 2022 Marek Vasut <marex@denx.de>
*
* DHCOR STM32MP1 variant:
* DHCR-STM32MP153C-C065-R051-V33-SPI-I-01LG
* DHCOR PCB number: 586-100 or newer
* DRC Compact PCB number: 627-100 or newer
*/
/dts-v1/;
#include "stm32mp153.dtsi"
#include "stm32mp15xc.dtsi"
#include "stm32mp15xx-dhcor-som.dtsi"
#include "stm32mp15xx-dhcor-drc-compact.dtsi"
/ {
model = "DH electronics STM32MP153C DHCOR DRC Compact";
compatible = "dh,stm32mp153c-dhcor-drc-compact",
"dh,stm32mp153c-dhcor-som",
"st,stm32mp153";
};
&m_can1 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&m_can1_pins_c>;
pinctrl-1 = <&m_can1_sleep_pins_c>;
status = "okay";
};

View File

@@ -1,38 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
/*
* Copyright (C) Linaro Ltd 2019 - All Rights Reserved
* Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
* Copyright (C) 2020 Marek Vasut <marex@denx.de>
*
* DHCOR STM32MP1 variant:
* DHCR-STM32MP157A-C065-R102-V18-SPI-C-01LG
* DHCOR PCB number: 586-100 or newer
* Avenger96 PCB number: 588-200 or newer
*/
/dts-v1/;
#include "stm32mp157.dtsi"
#include "stm32mp15xc.dtsi"
#include "stm32mp15xx-dhcor-som.dtsi"
#include "stm32mp15xx-dhcor-avenger96.dtsi"
/ {
model = "Arrow Electronics STM32MP157A Avenger96 board";
compatible = "arrow,stm32mp157a-avenger96", "dh,stm32mp157a-dhcor-som",
"st,stm32mp157";
};
&m_can1 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&m_can1_pins_b>;
pinctrl-1 = <&m_can1_sleep_pins_b>;
status = "disabled";
};
&m_can2 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&m_can2_pins_a>;
pinctrl-1 = <&m_can2_sleep_pins_a>;
status = "disabled";
};

View File

@@ -12,6 +12,7 @@
/ {
aliases {
eeprom0 = &eeprom0;
i2c1 = &i2c2;
i2c3 = &i2c4;
i2c4 = &i2c5;
@@ -19,15 +20,14 @@
mmc1 = &sdmmc2;
spi0 = &qspi;
usb0 = &usbotg_hs;
eeprom0 = &eeprom0;
};
config {
u-boot,boot-led = "heartbeat";
u-boot,error-led = "error";
dh,som-coding-gpios = <&gpiof 12 0>, <&gpiof 13 0>, <&gpiof 15 0>;
dh,ddr3-coding-gpios = <&gpioz 6 0>, <&gpioz 7 0>;
dh,mac-coding-gpios = <&gpioc 3 0>;
dh,som-coding-gpios = <&gpiof 12 0>, <&gpiof 13 0>, <&gpiof 15 0>;
u-boot,boot-led = "heartbeat";
u-boot,error-led = "error";
};
};
@@ -36,17 +36,6 @@
/delete-property/ st,eth-ref-clk-sel;
};
&ethernet0_rmii_pins_a {
pins1 {
pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */
<STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */
<STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */
<STM32_PINMUX('A', 1, AF11)>, /* ETH1_RMII_REF_CLK */
<STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */
<STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */
};
};
&i2c4 {
bootph-all;
bootph-pre-ram;
@@ -62,36 +51,6 @@
};
};
&phy0 {
/delete-property/ reset-gpios;
};
&pinctrl {
mco2_pins_a: mco2-0 {
pins {
pinmux = <STM32_PINMUX('G', 2, AF1)>; /* MCO2 */
bias-disable;
drive-push-pull;
slew-rate = <2>;
};
};
mco2_sleep_pins_a: mco2-sleep-0 {
pins {
pinmux = <STM32_PINMUX('G', 2, ANALOG)>; /* MCO2 */
};
};
};
&pmic {
bootph-all;
bootph-pre-ram;
regulators {
bootph-pre-ram;
};
};
&flash0 {
bootph-pre-ram;
@@ -123,6 +82,19 @@
};
};
&phy0 {
/delete-property/ reset-gpios;
};
&pmic {
bootph-all;
bootph-pre-ram;
regulators {
bootph-pre-ram;
};
};
&qspi {
bootph-pre-ram;
};
@@ -269,6 +241,14 @@
};
};
&reg11 {
bootph-pre-ram;
};
&reg18 {
bootph-pre-ram;
};
&sdmmc1 {
bootph-pre-ram;
st,use-ckin;
@@ -331,14 +311,6 @@
};
};
&reg11 {
bootph-pre-ram;
};
&reg18 {
bootph-pre-ram;
};
&usb33 {
bootph-pre-ram;
};

View File

@@ -112,6 +112,10 @@
};
&rcc {
clock-names = "hse", "hsi", "csi", "lse", "lsi";
clocks = <&clk_hse>, <&clk_hsi>, <&clk_csi>,
<&clk_lse>, <&clk_lsi>;
st,clksrc = <
CLK_MPU_PLL1P
CLK_AXI_PLL2P

View File

@@ -3,7 +3,7 @@
* dts file for Xilinx ZynqMP Generic System Controller
*
* (C) Copyright 2021 - 2022, Xilinx, Inc.
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
* (C) Copyright 2022 - 2024, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -80,7 +80,7 @@
pwm-fan {
compatible = "pwm-fan";
status = "okay";
pwms = <&ttc0 2 40000 1>;
pwms = <&ttc0 2 40000 0>;
};
};

View File

@@ -387,6 +387,7 @@
&rtc {
status = "okay";
calibration = <0x7fff>;
};
&lpd_dma_chan1 {

View File

@@ -73,11 +73,10 @@ static void announce_and_cleanup(int fake)
* Call remove function of all devices with a removal flag set.
* This may be useful for last-stage operations, like cancelling
* of DMA operation or releasing device internal buffers.
* dm_remove_devices_active() ensures that vital devices are removed in
* a second round.
*/
dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL | DM_REMOVE_NON_VITAL);
/* Remove all active vital devices next */
dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL);
dm_remove_devices_active();
cleanup_before_linux();
}

View File

@@ -45,10 +45,10 @@ u32 spl_boot_device(void)
}
/* boot from UART has higher priority */
if (scu->hwstrap2 & SCU_HWSTRAP2_BOOT_UART)
if (readl(&scu->hwstrap2) & SCU_HWSTRAP2_BOOT_UART)
return BOOT_DEVICE_UART;
if (scu->hwstrap1 & SCU_HWSTRAP1_BOOT_EMMC)
if (readl(&scu->hwstrap1) & SCU_HWSTRAP1_BOOT_EMMC)
return BOOT_DEVICE_MMC1;
out:

View File

@@ -8,6 +8,7 @@ if BCM47622
config TARGET_BCM947622
bool "Broadcom 47622 Reference Board"
depends on ARCH_BCMBCA
imply OF_UPSTREAM
config SYS_SOC
default "bcm47622"

View File

@@ -8,6 +8,7 @@ if BCM4912
config TARGET_BCM94912
bool "Broadcom 4912 Reference Board"
depends on ARCH_BCMBCA
imply OF_UPSTREAM
config SYS_SOC
default "bcm4912"

View File

@@ -8,6 +8,7 @@ if BCM63146
config TARGET_BCM963146
bool "Broadcom 63146 Reference Board"
depends on ARCH_BCMBCA
imply OF_UPSTREAM
config SYS_SOC
default "bcm63146"

View File

@@ -8,6 +8,7 @@ if BCM63158
config TARGET_BCM963158
bool "Broadcom 63158 Reference Board"
depends on ARCH_BCMBCA
imply OF_UPSTREAM
config SYS_SOC
default "bcm63158"

View File

@@ -8,6 +8,7 @@ if BCM63178
config TARGET_BCM963178
bool "Broadcom 63178 Reference Board"
depends on ARCH_BCMBCA
imply OF_UPSTREAM
config SYS_SOC
default "bcm63178"

View File

@@ -8,6 +8,7 @@ if BCM6756
config TARGET_BCM96756
bool "Broadcom 6756 Reference Board"
depends on ARCH_BCMBCA
imply OF_UPSTREAM
config SYS_SOC
default "bcm6756"

View File

@@ -8,6 +8,7 @@ if BCM6813
config TARGET_BCM96813
bool "Broadcom 6813 Reference Board"
depends on ARCH_BCMBCA
imply OF_UPSTREAM
config SYS_SOC
default "bcm6813"

View File

@@ -8,6 +8,7 @@ if BCM6855
config TARGET_BCM96855
bool "Broadcom 6855 Reference Board"
depends on ARCH_BCMBCA
imply OF_UPSTREAM
config SYS_SOC
default "bcm6855"

View File

@@ -8,6 +8,7 @@ if BCM6856
config TARGET_BCM96856
bool "Broadcom 6856 Reference Board"
depends on ARCH_BCMBCA
imply OF_UPSTREAM
config SYS_SOC
default "bcm6856"

View File

@@ -8,6 +8,7 @@ if BCM6858
config TARGET_BCM96858
bool "Broadcom 6858 Reference Board"
depends on ARCH_BCMBCA
imply OF_UPSTREAM
config SYS_SOC
default "bcm6858"

View File

@@ -8,6 +8,7 @@ if BCM6878
config TARGET_BCM96878
bool "Broadcom 6878 Reference Board"
depends on ARCH_BCMBCA
imply OF_UPSTREAM
config SYS_SOC
default "bcm6878"

View File

@@ -115,7 +115,7 @@ int fixup_thermal_trips(void *blob, const char *name)
temp = 0;
if (!strcmp(type, "critical"))
temp = 1000 * (maxc - 5);
temp = 1000 * maxc;
else if (!strcmp(type, "passive"))
temp = 1000 * (maxc - 10);
if (temp) {

View File

@@ -362,7 +362,7 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
* space below the 4G address boundary (which is 3GiB big),
* even when the effective available memory is bigger.
*/
top_addr = clamp_val((u64)PHYS_SDRAM + gd->ram_size, 0, 0xffffffff);
top_addr = clamp_val((u64)PHYS_SDRAM + gd->ram_size, 0, SZ_4G);
/*
* rom_pointer[0] stores the TEE memory start address.

View File

@@ -215,9 +215,16 @@ config TARGET_X530
bool "Support Allied Telesis x530"
select 88F6820
config TARGET_X250
bool "Support Allied Telesis x250"
select ARMADA_8K
imply SCSI
imply BOOTSTD_DEFAULTS
config TARGET_X240
bool "Support Allied Telesis x240"
select ALLEYCAT_5
imply BOOTSTD_DEFAULTS
config TARGET_DB_XC3_24G4XG
bool "Support DB-XC3-24G4XG"
@@ -301,6 +308,7 @@ config SYS_BOARD
default "theadorable" if TARGET_THEADORABLE
default "a38x" if TARGET_CONTROLCENTERDC
default "x530" if TARGET_X530
default "x250" if TARGET_X250
default "x240" if TARGET_X240
default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236
@@ -325,6 +333,7 @@ config SYS_CONFIG_NAME
default "turris_mox" if TARGET_TURRIS_MOX
default "controlcenterdc" if TARGET_CONTROLCENTERDC
default "x530" if TARGET_X530
default "x250" if TARGET_X250
default "x240" if TARGET_X240
default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236
@@ -349,6 +358,7 @@ config SYS_VENDOR
default "CZ.NIC" if TARGET_TURRIS_MOX
default "gdsys" if TARGET_CONTROLCENTERDC
default "alliedtelesis" if TARGET_X530
default "alliedtelesis" if TARGET_X250
default "alliedtelesis" if TARGET_X240
default "mikrotik" if TARGET_CRS3XX_98DX3236
default "Marvell" if TARGET_MVEBU_ALLEYCAT5

View File

@@ -1,11 +1,11 @@
if RCAR_32
config ARCH_RENESAS_BOARD_STRING
string "Renesas RCar Gen2 board name"
string "Renesas R-Car Gen2 board name"
default "Board"
config RCAR_GEN2
bool "Renesas RCar Gen2"
bool "Renesas R-Car Gen2"
select PHY
select PHY_RCAR_GEN2
select TMU_TIMER

View File

@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Specialty padding for the RCar Gen2 SPL JTAG loading
* Specialty padding for the R-Car Gen2 SPL JTAG loading
*/
#ifndef __BOOT0_H

View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Renesas RCar Gen3 memory map tables
* Renesas R-Car Gen3 memory map tables
*
* Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
*/

View File

@@ -11,6 +11,9 @@ config SYS_VENDOR
Based on this option board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD>
will be used as the custom board directory.
config SYS_MALLOC_LEN
default 0x10000000
config SYS_MALLOC_F_LEN
default 0x2000
@@ -20,6 +23,9 @@ config SPL_SYS_MALLOC_F
config SPL_SYS_MALLOC_F_LEN
default 0x2000
config SYS_MALLOC_LEN
default 0x800000
config LNX_KRNL_IMG_TEXT_OFFSET_BASE
default 0x80000000

View File

@@ -3,4 +3,5 @@
# (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
obj-y += board.o
obj-$(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) += capsule_update.o
obj-$(CONFIG_OF_LIVE) += of_fixup.o

View File

@@ -6,7 +6,9 @@
* Author: Caleb Connolly <caleb.connolly@linaro.org>
*/
#include "time.h"
#define LOG_CATEGORY LOGC_BOARD
#define pr_fmt(fmt) "QCOM: " fmt
#include <asm/armv8/mmu.h>
#include <asm/gpio.h>
#include <asm/io.h>
@@ -29,6 +31,7 @@
#include <fdt_support.h>
#include <usb.h>
#include <sort.h>
#include <time.h>
#include "qcom-priv.h"
@@ -448,6 +451,9 @@ int board_late_init(void)
configure_env();
qcom_late_init();
/* Configure the dfu_string for capsule updates */
qcom_configure_capsule_updates();
return 0;
}

View File

@@ -0,0 +1,153 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Capsule update support for Qualcomm boards.
*
* Copyright (c) 2024 Linaro Ltd.
* Author: Caleb Connolly <caleb.connolly@linaro.org>
*/
#define pr_fmt(fmt) "QCOM-FMP: " fmt
#include <dm/device.h>
#include <dm/uclass.h>
#include <efi.h>
#include <efi_loader.h>
#include <malloc.h>
#include <scsi.h>
#include <part.h>
#include <linux/err.h>
#include "qcom-priv.h"
/*
* NOTE: for now this implementation only supports the rb3gen2. Supporting other
* boards that boot in different ways (e.g. chainloaded from ABL) will require
* additional complexity to properly create the dfu string and fw_images array.
*/
/*
* To handle different variants like chainloaded U-Boot here we'll need to
* build the fw_images array dynamically at runtime. It looks like
* mach-rockchip is a good example for how to do this.
* Detecting which image types a board uses is TBD, hence for now we only
* support the one new board that runs U-Boot as its primary bootloader.
*/
struct efi_fw_image fw_images[] = {
{
/* U-Boot flashed to the uefi_X partition (e.g. rb3gen2) */
.fw_name = u"UBOOT_UEFI_PARTITION",
.image_index = 1,
},
};
struct efi_capsule_update_info update_info = {
/* Filled in by configure_dfu_string() */
.dfu_string = NULL,
.num_images = ARRAY_SIZE(fw_images),
.images = fw_images,
};
/* LSB first */
struct part_slot_status {
u16: 2;
u16 active : 1;
u16: 3;
u16 successful : 1;
u16 unbootable : 1;
u16 tries_remaining : 4;
};
static int find_boot_partition(const char *partname, struct blk_desc *blk_dev, char *name)
{
int ret;
int partnum;
struct disk_partition info;
struct part_slot_status *slot_status;
for (partnum = 1;; partnum++) {
ret = part_get_info(blk_dev, partnum, &info);
if (ret)
return ret;
slot_status = (struct part_slot_status *)&info.type_flags;
log_io("%16s: Active: %1d, Successful: %1d, Unbootable: %1d, Tries left: %1d\n",
info.name, slot_status->active,
slot_status->successful, slot_status->unbootable,
slot_status->tries_remaining);
/*
* FIXME: eventually we'll want to find the active/inactive variant of the partition
* but on the rb3gen2 these values might all be 0
*/
if (!strncmp(info.name, partname, strlen(partname))) {
log_debug("Found active %s partition: '%s'!\n", partname, info.name);
strlcpy(name, info.name, sizeof(info.name));
return partnum;
}
}
return -1;
}
/**
* qcom_configure_capsule_updates() - Configure the DFU string for capsule updates
*
* U-Boot is flashed to the boot partition on Qualcomm boards. In most cases there
* are two boot partitions, boot_a and boot_b. As we don't currently support doing
* full A/B updates, we only support updating the currently active boot partition.
*
* So we need to find the current slot suffix and the associated boot partition.
* We do this by looking for the boot partition that has the 'active' flag set
* in the GPT partition vendor attribute bits.
*/
void qcom_configure_capsule_updates(void)
{
struct blk_desc *desc;
int ret = 0, partnum = -1, devnum;
static char dfu_string[32] = { 0 };
char name[32]; /* GPT partition name */
char *partname = "uefi_a";
struct udevice *dev = NULL;
if (IS_ENABLED(CONFIG_SCSI)) {
/* Scan for SCSI devices */
ret = scsi_scan(false);
if (ret) {
debug("Failed to scan SCSI devices: %d\n", ret);
return;
}
}
uclass_foreach_dev_probe(UCLASS_BLK, dev) {
if (device_get_uclass_id(dev) != UCLASS_BLK)
continue;
desc = dev_get_uclass_plat(dev);
if (!desc || desc->part_type == PART_TYPE_UNKNOWN)
continue;
devnum = desc->devnum;
partnum = find_boot_partition(partname, desc,
name);
if (partnum >= 0)
break;
}
if (partnum < 0) {
log_err("Failed to find boot partition\n");
return;
}
switch (desc->uclass_id) {
case UCLASS_SCSI:
snprintf(dfu_string, 32, "scsi %d=u-boot.bin part %d", devnum, partnum);
break;
case UCLASS_MMC:
snprintf(dfu_string, 32, "mmc 0=u-boot.bin part %d %d", devnum, partnum);
break;
default:
debug("Unsupported storage uclass: %d\n", desc->uclass_id);
return;
}
log_debug("boot partition is %s, DFU string: '%s'\n", name, dfu_string);
update_info.dfu_string = dfu_string;
}

View File

@@ -3,6 +3,12 @@
#ifndef __QCOM_PRIV_H__
#define __QCOM_PRIV_H__
#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)
void qcom_configure_capsule_updates(void);
#else
void qcom_configure_capsule_updates(void) {}
#endif /* EFI_HAVE_CAPSULE_SUPPORT */
#if CONFIG_IS_ENABLED(OF_LIVE)
/**
* qcom_of_fixup_nodes() - Fixup Qualcomm DT nodes

View File

@@ -53,6 +53,7 @@ void dram_bank_mmu_setup(int bank)
struct bd_info *bd = gd->bd;
int i;
phys_addr_t start;
phys_addr_t addr;
phys_size_t size;
bool use_lmb = false;
enum dcache_option option;
@@ -77,8 +78,12 @@ void dram_bank_mmu_setup(int bank)
for (i = start >> MMU_SECTION_SHIFT;
i < (start >> MMU_SECTION_SHIFT) + (size >> MMU_SECTION_SHIFT);
i++) {
addr = i << MMU_SECTION_SHIFT;
option = DCACHE_DEFAULT_OPTION;
if (use_lmb && lmb_is_reserved_flags(i << MMU_SECTION_SHIFT, LMB_NOMAP))
if (use_lmb &&
(lmb_is_reserved_flags(i << MMU_SECTION_SHIFT, LMB_NOMAP) ||
addr >= gd->ram_top)
)
option = 0; /* INVALID ENTRY in TLB */
set_section_dcache(i, option);
}

View File

@@ -188,6 +188,8 @@ struct pmu_regs {
u32 gen_storage4; /* 0x40 */
u32 reserved1[1];
u32 gen_storage6; /* 0x48 */
u32 reserved2[3];
u32 pers_gen_storage2; /* 0x58 */
};
#define pmu_base ((struct pmu_regs *)ZYNQMP_PMU_BASEADDR)

View File

@@ -352,7 +352,7 @@ int cpu_release(u32 nr, int argc, char *const argv[])
*/
flush_dcache_all();
if (!strncmp(argv[1], "lockstep", 8)) {
if (!strcmp(argv[1], "lockstep") || !strcmp(argv[1], "0")) {
if (nr != ZYNQMP_CORE_RPU0) {
printf("Lockstep mode should run on ZYNQMP_CORE_RPU0\n");
return 1;
@@ -369,7 +369,7 @@ int cpu_release(u32 nr, int argc, char *const argv[])
dcache_enable();
set_r5_halt_mode(nr, RELEASE, LOCK);
mark_r5_used(nr, LOCK);
} else if (!strncmp(argv[1], "split", 5)) {
} else if (!strcmp(argv[1], "split") || !strcmp(argv[1], "1")) {
printf("R5 split mode\n");
set_r5_reset(nr, SPLIT);
set_r5_tcm_mode(SPLIT);

View File

@@ -57,7 +57,7 @@ static void announce_and_cleanup(int fake)
* This may be useful for last-stage operations, like cancelling
* of DMA operation or releasing device internal buffers.
*/
dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL);
dm_remove_devices_active();
cleanup_before_linux();
}

View File

@@ -24,7 +24,9 @@ int arch_cpu_init(void)
int ret;
#if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_USE_HOB)
gd->arch.hob_list = handoff_get();
struct spl_handoff *ho = gd->spl_handoff;
gd->arch.hob_list = ho->arch.hob_list;
#endif
ret = x86_cpu_reinit_f();

View File

@@ -49,7 +49,7 @@ void bootm_announce_and_cleanup(void)
* This may be useful for last-stage operations, like cancelling
* of DMA operation or releasing device internal buffers.
*/
dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL);
dm_remove_devices_active();
}
#if defined(CONFIG_OF_LIBFDT) && !defined(CONFIG_OF_NO_KERNEL)

View File

@@ -59,7 +59,7 @@ int dram_init(void)
#endif
} else {
#if CONFIG_IS_ENABLED(HANDOFF)
struct spl_handoff *ho = handoff_get();
struct spl_handoff *ho = gd->spl_handoff;
if (!ho) {
log_debug("No SPL handoff found\n");
@@ -82,7 +82,7 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
return gd->ram_size;
#if CONFIG_IS_ENABLED(HANDOFF)
struct spl_handoff *ho = handoff_get();
struct spl_handoff *ho = gd->spl_handoff;
log_debug("usable_ram_top = %lx\n", ho->arch.usable_ram_top);

View File

@@ -0,0 +1,20 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2024 Tony Dinh <mibodhi@gmail.com>
*
* Environment variables configurations
*/
kernel_addr_r=0x800000
fdt_addr_r=0x2c00000
ramdisk_addr_r=0x01100000
scriptaddr=0x200000
fdtfile=CONFIG_DEFAULT_DEVICE_TREE.dtb
mtdparts=CONFIG_MTDPARTS_DEFAULT
console=ttyS0,115200
/* Standard Boot */
bootcmd=
bootflow scan -lb
failed=
echo CONFIG_SYS_BOARD boot failed - please check your image

View File

@@ -0,0 +1,7 @@
X250 BOARD
M: Chris Packham <chris.packham@alliedtelesis.co.nz>
S: Maintained
F: board/alliedtelesis/x250/
F: arch/arm/dts/cn9130-atl-x250.dts
F: include/configs/x250.h
F: configs/x250_defconfig

View File

@@ -0,0 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2024 Allied Telesis
#
obj-y += x250.o

View File

@@ -0,0 +1,19 @@
// SPDX-License-Identifier: GPL-2.0+
#include <config.h>
#include <asm/global_data.h>
#include <linux/io.h>
DECLARE_GLOBAL_DATA_PTR;
#define DEVICE_BUS_SYNC_CTRL 0xF27004C8
int board_init(void)
{
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
/* DEV_READYn is not needed for NVS, ignore it when accessing CS1 */
writel(0x00004001, DEVICE_BUS_SYNC_CTRL);
return 0;
}

View File

@@ -1,5 +1,5 @@
TOTAL_COMPUTE BOARD
M: Usama Arif <usama.arif@arm.com>
M: Ben Horgan <ben.horgan@arm.com>
S: Maintained
F: board/armltd/total_compute/
F: include/configs/total_compute.h

View File

@@ -16,8 +16,8 @@ config VEXPRESS64_BASE_MODEL
select VIRTIO_BLK if VIRTIO_MMIO
select VIRTIO_NET if VIRTIO_MMIO
select DM_ETH if VIRTIO_NET
imply DM_RTC
imply RTC_PL031
select DM_RTC if RTC_PL031
imply EFI_SET_TIME if DM_RTC
select LINUX_KERNEL_IMAGE_HEADER
select POSITION_INDEPENDENT

View File

@@ -47,6 +47,9 @@ u8 dmo_get_memcfg(void)
"dmo,ram-coding-gpios",
gpio, ARRAY_SIZE(gpio),
GPIOD_IS_IN);
if (ret < 0)
return BIT(2) | BIT(0);
for (i = 0; i < ret; i++)
memcfg |= !!dm_gpio_get_value(&(gpio[i])) << i;

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