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77801f4b64
As the PHYTEC phyCORE-i.MX91 [1] is just another variant of the existing PHYTEC phyCORE-i.MX93 SoM but with i.MX91 SoC populated instead, add it to the existing board-code "phycore_imx93", and rename that board to "phycore_imx91_93" to reflect the dual SoCs support. While at it, also rename and change common files accordingly. This way i.MX91 and i.MX93 SoC variants of the phyCORE SoM share most of the code and documentation without duplication, while maintaining own device-tree and defconfigs for each CPU variant. Supported features: - 1GB LPDDR4 RAM - Debug UART - EEPROM - eMMC - Ethernet - SD-card - USB Product page SoM: [1] https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/ Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
29 lines
789 B
C
29 lines
789 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2022 NXP
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* Copyright (C) 2023 PHYTEC Messtechnik GmbH
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* Christoph Stoidner <c.stoidner@phytec.de>
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* Copyright (C) 2024 Mathieu Othacehe <m.othacehe@gmail.com>
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*/
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#ifndef __PHYCORE_IMX91_93_H
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#define __PHYCORE_IMX91_93_H
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#include <linux/sizes.h>
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#include <asm/arch/imx-regs.h>
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#define CFG_SYS_UBOOT_BASE \
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(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
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#define CFG_SYS_INIT_RAM_ADDR 0x80000000
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#define CFG_SYS_INIT_RAM_SIZE 0x200000
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#define CFG_SYS_SDRAM_BASE 0x80000000
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#define PHYS_SDRAM 0x80000000
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#define PHYS_SDRAM_SIZE 0x80000000
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/* Using ULP WDOG for reset */
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#define WDOG_BASE_ADDR WDG3_BASE_ADDR
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#endif /* __PHYCORE_IMX91_93_H */
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