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b0d731d956
Add configuration for ARMv8-M aarch32 core, which are currently Cortex-M23/M33 cores. These cores are treated similar to ARMv7-M cores, except the code has to be compiled with matching compiler -march=armv8-m.main flag . These cores have no MMU, they have MPU, which is currently not configured. Unlike ARMv7-M, these cores have 512 interrupt vectors. While the SYS_ARM_ARCH should be set to 8, it is set to 7 because all of the initialization code is built from arch/arm/cpu/armv7m and not armv8. Furthermore, CONFIG_ARM64 must be disabled, although DTs for devices using these cores do come from arch/arm64/boot/dts. To avoid excess duplication in Makefiles, introduce one new Kconfig symbol, CPU_V7M_V8M. The CPU_V7M_V8M cover both ARMv7-M and ARMv8-M cores. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Udit Kumar <u-kumar1@ti.com>
70 lines
1.5 KiB
C
70 lines
1.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2010,2011
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* Vladimir Khusainov, Emcraft Systems, vlad@emcraft.com
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*
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* (C) Copyright 2015
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* Kamil Lulko, <kamil.lulko@gmail.com>
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*/
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#include <cpu_func.h>
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#include <irq_func.h>
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#include <asm/io.h>
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#include <asm/armv7m.h>
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#include <spl.h>
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/*
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* This is called right before passing control to
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* the Linux kernel point.
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*/
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int cleanup_before_linux(void)
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{
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if (!CONFIG_IS_ENABLED(LIB_BOOTM) && !CONFIG_IS_ENABLED(LIB_BOOTZ))
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return 0;
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/*
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* this function is called just before we call linux
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* it prepares the processor for linux
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*
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* disable interrupt and turn off caches etc ...
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*/
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disable_interrupts();
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/*
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* turn off D-cache
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* dcache_disable() in turn flushes the d-cache
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* MPU is still enabled & can't be disabled as the u-boot
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* code might be running in sdram which by default is not
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* executable area.
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*/
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dcache_disable();
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/* invalidate to make sure no cache line gets dirty between
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* dcache flushing and disabling dcache */
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invalidate_dcache_all();
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icache_disable();
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invalidate_icache_all();
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return 0;
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}
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/*
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* Perform the low-level reset. ARMv7M only.
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*/
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#if IS_ENABLED(CONFIG_CPU_V7M)
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void reset_cpu(void)
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{
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/*
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* Perform reset but keep priority group unchanged.
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*/
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writel((V7M_AIRCR_VECTKEY << V7M_AIRCR_VECTKEY_SHIFT)
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| (V7M_SCB->aircr & V7M_AIRCR_PRIGROUP_MSK)
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| V7M_AIRCR_SYSRESET, &V7M_SCB->aircr);
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}
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#endif
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void spl_perform_arch_fixups(struct spl_image_info *spl_image)
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{
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if (IS_ENABLED(CONFIG_XPL_BUILD))
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spl_image->entry_point |= 0x1;
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}
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