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The Allwinner A523 SoC has a slightly changed mod clock, where the P factor, formerly a shift value, is now a second divider value. Also the input clock is not PLL_PERIPH0 (600MHz) anymore, but PLL_PERIPH0_400M (for MMC0/1), so adjust the input rate calculation accordingly. MMC2 has a different set of parents, so the input clock is 800 MHz there. Adjust for all of this. Signed-off-by: Andre Przywara <andre.przywara@arm.com>