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[1] https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git - Remove netc_timerX nodes from arch/arm/dts/imx943-u-boot.dtsi as they are now upstream - Move dts/upstream/include/dt-bindings/reset/bcm6318-reset.h to include/dt-bindings/reset/bcm6318-reset.h as upstream has removed this file as unused (but we use it). Signed-off-by: Tom Rini <trini@konsulko.com>
127 lines
3.0 KiB
YAML
127 lines
3.0 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/msm/qcom,adreno-rgmu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: RGMU attached to certain Adreno GPUs
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maintainers:
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- Rob Clark <robin.clark@oss.qualcomm.com>
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description:
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RGMU (Reduced Graphics Management Unit) IP is present in some GPUs that
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belong to Adreno A6xx family. It is a small state machine that helps to
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toggle the GX GDSC (connected to CX rail) to implement IFPC feature and save
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power.
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properties:
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compatible:
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items:
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- const: qcom,adreno-rgmu-612.0
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- const: qcom,adreno-rgmu
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reg:
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items:
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- description: Core RGMU registers
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clocks:
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items:
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- description: GMU clock
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- description: GPU CX clock
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- description: GPU AXI clock
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- description: GPU MEMNOC clock
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- description: GPU SMMU vote clock
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clock-names:
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items:
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- const: gmu
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- const: cxo
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- const: axi
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- const: memnoc
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- const: smmu_vote
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power-domains:
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items:
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- description: CX GDSC power domain
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- description: GX GDSC power domain
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power-domain-names:
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items:
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- const: cx
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- const: gx
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interrupts:
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items:
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- description: GMU OOB interrupt
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- description: GMU interrupt
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interrupt-names:
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items:
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- const: oob
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- const: gmu
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operating-points-v2: true
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opp-table:
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type: object
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- power-domains
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- power-domain-names
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- interrupts
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- interrupt-names
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- operating-points-v2
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,qcs615-gpucc.h>
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#include <dt-bindings/clock/qcom,qcs615-gcc.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/qcom,rpmhpd.h>
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gmu@506a000 {
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compatible = "qcom,adreno-rgmu-612.0", "qcom,adreno-rgmu";
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reg = <0x05000000 0x90000>;
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clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
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<&gpucc GPU_CC_CXO_CLK>,
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<&gcc GCC_DDRSS_GPU_AXI_CLK>,
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<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
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<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
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clock-names = "gmu",
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"cxo",
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"axi",
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"memnoc",
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"smmu_vote";
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power-domains = <&gpucc CX_GDSC>,
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<&gpucc GX_GDSC>;
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power-domain-names = "cx",
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"gx";
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interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "oob",
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"gmu";
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operating-points-v2 = <&gmu_opp_table>;
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gmu_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-200000000 {
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opp-hz = /bits/ 64 <200000000>;
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required-opps = <&rpmhpd_opp_low_svs>;
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};
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};
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};
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