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e65a87e959
The Receive FIFO Enable (RXFE) field in the LPUART FIFO register is bit 3 on all supported architectures. The define has been wrong since it was introduced: for non-i.MX8/i.MXRT it set bit 6, which on LS102xA is read-only-as-zero, so the bug went unnoticed. NXP confirmed bit 3 is correct everywhere, so drop the ARCH-based selection. Link:9498bcc514Link: https://lore.kernel.org/u-boot/dc163ea7-9063-4dfb-a39a-e643c0bcccf1@oss.nxp.com/ Fixes:6209e14cb0("serial: lpuart: add 32-bit registers lpuart support") Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com> Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com> Reviewed-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>