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The AMD Versal Gen 2 PCIe host controller places its DBI registers (0x100000000000, 1 MB) and config space (0x100000100000, 255 MB) above 1 TB. Without MMU entries covering these ranges, U-Boot faults when the PCIe driver accesses them. The two regions are merged into a single entry as these are contiguous and share identical MMU attributes. Add this entry under a CONFIG_IS_ENABLED(PCIE_DW_AMD) guard so it is only included when the PCIe driver is configured. VERSAL2_MEM_MAP_USED is adjusted from 5 to 6 accordingly, keeping the DRAM bank index correct. Signed-off-by: Pranav Sanwal <pranav.sanwal@amd.com> Link: https://lore.kernel.org/r/20260327121015.996806-3-pranav.sanwal@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>