mirror of
https://source.denx.de/u-boot/u-boot.git
synced 2026-06-02 09:46:37 +03:00
9d47a5a4d5
Add support for building U-Boot for Cortex-M33 RSIP core in Renesas R-Car Gen5 R8A78000 X5H SoC. The main goal is to start U-Boot on the Cortex-M33 RSIP core, which initializes the hardware and then starts the Cortex-M33 SCP and Cortex-A720 cores which run the SCP firmware and applications software respectively. The SCP is responsible for platform resource management, and is used to start other CPU cores. The Cortex-M33 build contains its own r8a78000_ironhide_cm33_defconfig which configures the build for aarch32 instruction set compatible with the ARMv8M core. The build also uses -cm33 DT and -u-boot.dtsi which are derived from their non-CM33 counterparts, and add CM33 specifics. The arch/arm/mach-renesas/u-boot-rsip.lds is derived from generic arch/arm/cpu/u-boot.lds with adjustments to cater to the RSIP core, those are entrypoint before vectors, __data_start/__data_end symbols for data-only relocation, and placement of BSS into read-write SRAM area. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
64 lines
883 B
Makefile
64 lines
883 B
Makefile
#
|
|
# Copyright (C) 2024 Marek Vasut <marek.vasut+renesas@mailbox.org>
|
|
#
|
|
# SPDX-License-Identifier: GPL-2.0+
|
|
#
|
|
|
|
# R-Car SoCs
|
|
ifndef CONFIG_RZA1
|
|
ifndef CONFIG_RZG2L
|
|
|
|
# 32 bit SoCs
|
|
ifdef CONFIG_RCAR_32
|
|
ifdef CONFIG_RCAR_GEN2
|
|
endif
|
|
endif
|
|
|
|
# 64 bit SoCs
|
|
ifdef CONFIG_RCAR_64
|
|
ifdef CONFIG_XPL_BUILD
|
|
obj-y += rcar64-spl.o
|
|
else
|
|
obj-y += rcar64-common.o
|
|
endif
|
|
|
|
ifdef CONFIG_RCAR_GEN3
|
|
ifdef CONFIG_XPL_BUILD
|
|
obj-y += gen3-spl.o
|
|
else
|
|
obj-y += gen3-common.o
|
|
ifdef CONFIG_R8A77970
|
|
obj-y += v3-common.o
|
|
endif
|
|
ifdef CONFIG_R8A77980
|
|
obj-y += v3-common.o
|
|
endif
|
|
endif
|
|
endif
|
|
|
|
ifdef CONFIG_RCAR_GEN4
|
|
ifdef CONFIG_XPL_BUILD
|
|
obj-y += gen4-spl.o
|
|
else
|
|
obj-y += gen4-common.o
|
|
endif
|
|
endif
|
|
|
|
ifdef CONFIG_RCAR_GEN5
|
|
ifdef CONFIG_RCAR_64_RSIP
|
|
obj-y += gen5-cm33.o
|
|
else
|
|
obj-y += gen5-common.o
|
|
endif
|
|
endif
|
|
endif
|
|
|
|
endif
|
|
endif
|
|
|
|
# RZ/A1 SoCs
|
|
ifdef CONFIG_RZA1
|
|
obj-y += rza1-common.o
|
|
obj-y += rza1-lowlevel_init.o
|
|
endif
|