arm: renesas: Add Renesas R-Car R8A78000 X5H Cortex-M33 RSIP port

Add support for building U-Boot for Cortex-M33 RSIP core in Renesas
R-Car Gen5 R8A78000 X5H SoC. The main goal is to start U-Boot on the
Cortex-M33 RSIP core, which initializes the hardware and then starts
the Cortex-M33 SCP and Cortex-A720 cores which run the SCP firmware
and applications software respectively. The SCP is responsible for
platform resource management, and is used to start other CPU cores.

The Cortex-M33 build contains its own r8a78000_ironhide_cm33_defconfig
which configures the build for aarch32 instruction set compatible with
the ARMv8M core. The build also uses -cm33 DT and -u-boot.dtsi which
are derived from their non-CM33 counterparts, and add CM33 specifics.

The arch/arm/mach-renesas/u-boot-rsip.lds is derived from generic
arch/arm/cpu/u-boot.lds with adjustments to cater to the RSIP core,
those are entrypoint before vectors, __data_start/__data_end symbols
for data-only relocation, and placement of BSS into read-write SRAM
area.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

arch/arm/dts/Makefile

@@ -899,6 +899,9 @@ dtb-$(CONFIG_RZA1) += \
 	r7s72100-genmai.dtb \
 	r7s72100-gr-peach.dtb
 
+dtb-$(CONFIG_RCAR_GEN5) += \
+	r8a78000-ironhide-cm33.dtb
+
 dtb-$(CONFIG_TARGET_AT91SAM9261EK) += at91sam9261ek.dtb
 
 dtb-$(CONFIG_TARGET_PM9261) += at91sam9261ek.dtb

arch/arm/dts/r8a78000-ironhide-cm33-u-boot.dtsi

@@ -0,0 +1,130 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source extras for U-Boot for the Ironhide CM33 board
+ *
+ * Copyright (C) 2026 Renesas Electronics Corp.
+ */
+
+#include "r8a78000-ironhide-u-boot.dtsi"
+
+/ {
+	model = "Renesas Ironhide board CM33 based on r8a78000";
+	compatible = "renesas,ironhide-cm33", "renesas,r8a78000-cm33";
+
+	aliases {
+		serial1 = &hscif1;
+	};
+
+	chosen {
+		stdout-path = "serial1:1843200n8";
+	};
+
+	/delete-node/ firmware;
+	/delete-node/ memory@40000000;
+	/delete-node/ memory@60600000;
+	/delete-node/ memory@1080000000;
+	/delete-node/ memory@1200000000;
+	/delete-node/ memory@1400000000;
+	/delete-node/ memory@1600000000;
+	/delete-node/ memory@1800000000;
+	/delete-node/ memory@1a00000000;
+	/delete-node/ memory@1c00000000;
+	/delete-node/ memory@1e00000000;
+	/delete-node/ reserved-memory;
+
+	memory@b8400000 {
+		device_type = "memory";
+		reg = <0x0 0xb8400000 0x0 0x00200000>;
+	};
+
+	dummy_clk_rclk: dummy-clk-rclk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+	};
+
+	dummy_clk_sasyncd4_rt: dummy-clk-sasyncd4-rt {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <16660000>;
+	};
+
+	ctl: syscon@5fffd000 {
+		compatible = "renesas,r8a78000-ctl",
+			     "renesas,rcar-gen5-ctl",
+			     "syscon";
+		reg = <0 0x5fffd000 0 0xc4>;
+	};
+
+	watchdog@5fffd800 {
+		compatible = "renesas,r8a78000-wwdt",
+			     "renesas,rcar-gen5-wwdt";
+		clocks = <&dummy_clk_rclk>, <&dummy_clk_sasyncd4_rt>;
+		clock-names = "cnt", "bus";
+		reg = <0 0x5fffd800 0 0x10>;
+		syscon = <&ctl>;
+	};
+
+	scp@c1340000 {
+		compatible = "renesas,r8a78000-rproc";
+		reg = <0 0xc1340000 0 0x80000>;
+	};
+};
+
+&cpg {
+	/delete-property/ firmware;
+};
+
+&eth_pcs {
+	/* Stub clock */
+	clocks = <&dummy_clk_rclk>;
+};
+
+&hscif1 {
+	pinctrl-0 = <&hscif1_pins>;
+	pinctrl-names = "default";
+	uart-has-rtscts;
+	status = "okay";
+};
+
+&mdlc_hscn {
+	/delete-property/ firmware;
+};
+
+&mdlc_pere {
+	/delete-property/ firmware;
+};
+
+&mmc0 {
+	status = "disabled";
+};
+
+&mp_phy {
+	/* Stub clock */
+	clocks = <&dummy_clk_rclk>;
+};
+
+&pfc {
+	hscif1_pins: hscif1 {
+		groups = "hscif1_data", "hscif1_ctrl";
+		function = "hscif1";
+	};
+};
+
+&rswitch3 {
+	/* Stub clock */
+	clocks = <&dummy_clk_rclk>;
+};
+
+&soc {
+	dma-ranges = <0 0x00000000 0 0xa0000000 0 0x20000000>;
+};
+
+&ufs0 {
+	/delete-property/ power-domains;
+};
+
+&ufs1 {
+	/delete-property/ power-domains;
+	status = "disabled";
+};

arch/arm/dts/r8a78000-ironhide-cm33.dts

@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the Ironhide CM33 board
+ *
+ * Copyright (C) 2026 Renesas Electronics Corp.
+ */
+
+#include "../../../dts/upstream/src/arm64/renesas/r8a78000-ironhide.dts"

arch/arm/mach-renesas/u-boot-rsip.lds

@@ -0,0 +1,203 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ */
+
+#include <config.h>
+#include <asm/psci.h>
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+#if defined(CONFIG_ARMV7_SECURE_BASE) && defined(CONFIG_ARMV7_NONSEC)
+	/*
+	 * If CONFIG_ARMV7_SECURE_BASE is true, secure code will not
+	 * bundle with u-boot, and code offsets are fixed. Secure zone
+	 * only needs to be copied from the loading address to
+	 * CONFIG_ARMV7_SECURE_BASE, which is the linking and running
+	 * address for secure code.
+	 *
+	 * If CONFIG_ARMV7_SECURE_BASE is undefined, the secure zone will
+	 * be included in u-boot address space, and some absolute address
+	 * were used in secure code. The absolute addresses of the secure
+	 * code also needs to be relocated along with the accompanying u-boot
+	 * code.
+	 *
+	 * So DISCARD is only for CONFIG_ARMV7_SECURE_BASE.
+	 */
+	/DISCARD/ : { *(.rel._secure*) }
+#endif
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	__image_copy_start = ADDR(.text);
+	.text :
+	{
+		CPUDIR/start.o (.text*)
+		*(.vectors)
+	}
+
+	/* This needs to come before *(.text*) */
+	.efi_runtime : {
+		__efi_runtime_start = .;
+		*(.text.efi_runtime*)
+		*(.rodata.efi_runtime*)
+		*(.data.efi_runtime*)
+		__efi_runtime_stop = .;
+	}
+
+	.text_rest :
+	{
+		*(.text*)
+	}
+
+#ifdef CONFIG_ARMV7_NONSEC
+
+	/* Align the secure section only if we're going to use it in situ */
+	.__secure_start
+#ifndef CONFIG_ARMV7_SECURE_BASE
+		ALIGN(CONSTANT(COMMONPAGESIZE))
+#endif
+	: {
+		KEEP(*(.__secure_start))
+	}
+
+#ifndef CONFIG_ARMV7_SECURE_BASE
+#define __ARMV7_SECURE_BASE
+#define __ARMV7_PSCI_STACK_IN_RAM
+#else
+#define __ARMV7_SECURE_BASE	CONFIG_ARMV7_SECURE_BASE
+#endif
+
+	.secure_text __ARMV7_SECURE_BASE :
+		AT(ADDR(.__secure_start) + SIZEOF(.__secure_start))
+	{
+		*(._secure.text)
+	}
+
+	.secure_data : AT(LOADADDR(.secure_text) + SIZEOF(.secure_text))
+	{
+		*(._secure.data)
+	}
+
+#ifdef CONFIG_ARMV7_PSCI
+	.secure_stack ALIGN(ADDR(.secure_data) + SIZEOF(.secure_data),
+			    CONSTANT(COMMONPAGESIZE)) (NOLOAD) :
+#ifdef __ARMV7_PSCI_STACK_IN_RAM
+		AT(ADDR(.secure_stack))
+#else
+		AT(LOADADDR(.secure_data) + SIZEOF(.secure_data))
+#endif
+	{
+		KEEP(*(.__secure_stack_start))
+
+		/* Skip addresses for stack */
+		. = . + CONFIG_ARMV7_PSCI_NR_CPUS * ARM_PSCI_STACK_SIZE;
+
+		/* Align end of stack section to page boundary */
+		. = ALIGN(CONSTANT(COMMONPAGESIZE));
+
+		KEEP(*(.__secure_stack_end))
+
+#ifdef CONFIG_ARMV7_SECURE_MAX_SIZE
+		/*
+		 * We are not checking (__secure_end - __secure_start) here,
+		 * as these are the load addresses, and do not include the
+		 * stack section. Instead, use the end of the stack section
+		 * and the start of the text section.
+		 */
+		ASSERT((. - ADDR(.secure_text)) <= CONFIG_ARMV7_SECURE_MAX_SIZE,
+		       "Error: secure section exceeds secure memory size");
+#endif
+	}
+
+#ifndef __ARMV7_PSCI_STACK_IN_RAM
+	/* Reset VMA but don't allocate space if we have secure SRAM */
+	. = LOADADDR(.secure_stack);
+#endif
+
+#endif
+
+	.__secure_end : AT(ADDR(.__secure_end)) {
+		*(.__secure_end)
+		LONG(0x1d1071c);	/* Must output something to reset LMA */
+	}
+#endif
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : {
+		__data_start = .;
+		*(.data*)
+		__data_end = .;
+	}
+
+	. = ALIGN(4);
+
+	. = .;
+
+	. = ALIGN(4);
+	__u_boot_list : {
+		KEEP(*(SORT(__u_boot_list*)));
+	}
+
+	.efi_runtime_rel : {
+		__efi_runtime_rel_start = .;
+		*(.rel*.efi_runtime)
+		*(.rel*.efi_runtime.*)
+		__efi_runtime_rel_stop = .;
+	}
+
+	. = ALIGN(8);
+	__image_copy_end = .;
+
+	/*
+	 * if CONFIG_USE_ARCH_MEMSET is not selected __bss_end - __bss_start
+	 * needs to be a multiple of 8 and we overlay .bss with .rel.dyn
+	 */
+	.rel.dyn ALIGN(8) : {
+		__rel_dyn_start = .;
+		*(.rel*)
+		__rel_dyn_end = .;
+		. = ALIGN(8);
+	}
+
+	_end = .;
+	_image_binary_end = .;
+
+/*
+ * These sections occupy the same memory, but their lifetimes do
+ * not overlap: U-Boot initializes .bss only after applying dynamic
+ * relocations and therefore after it doesn't need .rel.dyn any more.
+ */
+
+	/* BSS goes to special read-write offset below U-Boot entry point */
+	. = 0xb8400000;
+	.bss (OVERLAY): {
+		__bss_start = .;
+		*(.bss*)
+		. = ALIGN(4);
+		__bss_end = .;
+	}
+
+	/DISCARD/ : { *(.dynsym) }
+	/DISCARD/ : { *(.dynbss) }
+	/DISCARD/ : { *(.dynstr*) }
+	/DISCARD/ : { *(.dynamic*) }
+	/DISCARD/ : { *(.plt*) }
+	/DISCARD/ : { *(.interp*) }
+	/DISCARD/ : { *(.gnu.hash) }
+	/DISCARD/ : { *(.gnu*) }
+	/DISCARD/ : { *(.ARM.exidx*) }
+	/DISCARD/ : { *(.gnu.linkonce.armexidx.*) }
+}
+
+ASSERT(_image_binary_end % 8 == 0, \
+       "_image_binary_end must be 8-byte aligned for device tree");

board/renesas/common/Makefile

@@ -45,9 +45,13 @@ endif
 endif
 
 ifdef CONFIG_RCAR_GEN5
+ifdef CONFIG_RCAR_64_RSIP
+obj-y	+= gen5-cm33.o
+else
 obj-y	+= gen5-common.o
 endif
 endif
+endif
 
 endif
 endif

configs/r8a78000_ironhide_cm33_defconfig

@@ -0,0 +1,80 @@
+#include <configs/renesas_rcar64.config>
+
+CONFIG_ARM=y
+CONFIG_ARCH_RENESAS=y
+CONFIG_RCAR_64_RSIP=y
+CONFIG_RCAR_GEN5=y
+CONFIG_TARGET_IRONHIDE=y
+CONFIG_DEFAULT_DEVICE_TREE="r8a78000-ironhide-cm33"
+CONFIG_DEFAULT_FDT_FILE="r8a78000-ironhide-cm33.dtb"
+
+CONFIG_TEXT_BASE=0x18410000
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x3fe10000
+CONFIG_SYS_CUSTOM_LDSCRIPT=y
+CONFIG_SYS_LDSCRIPT="arch/arm/mach-renesas/u-boot-rsip.lds"
+CONFIG_SKIP_RELOCATE_CODE=y
+CONFIG_SKIP_RELOCATE_CODE_DATA_OFFSET=0xa0000000
+
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_BAUDRATE=1843200
+CONFIG_BOOTCOMMAND=""
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_CMD_IMI=y
+CONFIG_CMD_REMOTEPROC=y
+CONFIG_CMD_UFS=y
+CONFIG_DM_DMA=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_DM_RESET=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_LAST_STAGE_INIT=y
+CONFIG_NET_LWIP=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_OF_LIVE=y
+CONFIG_PHY_R8A78000_ETHERNET_PCS=y
+CONFIG_PHY_R8A78000_MP_PHY=y
+CONFIG_PHY_TI_DP83869=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_RAM=y
+CONFIG_REMOTEPROC_RENESAS_RSIP=y
+CONFIG_RENESAS_ETHER_SWITCH=y
+CONFIG_RENESAS_R8A78000_POWER_DOMAIN=y
+CONFIG_SCSI=y
+CONFIG_SERIAL_PROBE_ALL=y
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SIMPLE_BUS_CORRECT_RANGE=y
+CONFIG_SKIP_RELOCATE=y
+CONFIG_SYS_ARCH_TIMER=y
+CONFIG_SYS_BARGSIZE=2048
+CONFIG_SYS_BOOT_GET_CMDLINE=y
+CONFIG_SYS_CLK_FREQ=16666666
+CONFIG_SYS_LOAD_ADDR=0xb8000000
+CONFIG_SYS_MALLOC_LEN=0x80000
+CONFIG_SYS_TIMER_COUNTS_DOWN=y
+CONFIG_UFS=y
+CONFIG_UFS_RENESAS_GEN5=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_WATCHDOG_TIMEOUT_MSECS=2000
+CONFIG_WDT=y
+CONFIG_WDT_RENESAS_WWDT=y
+# CONFIG_DM_THERMAL is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_BOOTM is not set
+# CONFIG_CMD_BOOTFLOW is not set
+# CONFIG_CMD_BOOTZ is not set
+# CONFIG_PROT_TCP is not set
+# CONFIG_OF_UPSTREAM is not set
+# CONFIG_BOARD_EARLY_INIT_F is not set
+# CONFIG_OF_BOARD_SETUP is not set
+# CONFIG_SYS_ARCH_TIMER is not set
+
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_SCIF=y
+CONFIG_DEBUG_UART_BASE=0xc0714000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_DEBUG_UART_BOARD_INIT=y

include/configs/rcar-gen5-common.h

@@ -14,7 +14,11 @@
 
 /* Memory */
 #define DRAM_RSV_SIZE			0x20600000
+#ifdef CONFIG_RCAR_64_RSIP
+#define CFG_SYS_SDRAM_BASE		0xb8400000
+#else
 #define CFG_SYS_SDRAM_BASE		(0x40000000 + DRAM_RSV_SIZE)
+#endif
 #define CFG_SYS_SDRAM_SIZE		(0x80000000u - DRAM_RSV_SIZE)
 #define CFG_MAX_MEM_MAPPED		(0x80000000u - DRAM_RSV_SIZE)