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Commitbb6f3c0f76("armv7: ls102xa: Update SCFG_QSPI_CLKSEL value") broke the SPI boot on the LS1021ATSN board (ls1021atsn_qspi_defconfig) at least. The commit message reads Update SCFG_QSPI_CLKSEL value : 0xC -> 0x5 which means ClusterPLL/16 The original submitted patch had the following description: Value 0xC is reserved. Replace it with correct value 0x5 which is ClusterPLL/16 Unfortunatly, the little information which was there, was stripped even further. Why is 0x5 the "correct" value? In fact, it seems that the upper bit is just ignored and thus the value 0xC translates to 0x4 which is ClusterPLL/20. This, will result in a SPI clock of 60MHz (if the PLL is clocked at 1.2GHz). But even that is too much for the (default) 03h read opcode (max 50MHz). Set the value to ClusterPLL/24 which is 50MHz. Link: https://lore.kernel.org/r/1568804284-25162-1-git-send-email-kuldeep.singh@nxp.com/ Fixes:bb6f3c0f76("armv7: ls102xa: Update SCFG_QSPI_CLKSEL value") Signed-off-by: Michael Walle <mwalle@kernel.org> Reviewed-by: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>