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rk3326: bl31: update version to v1.27

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Build from ATF commit:
	96550638e plat: px30-s: dram: phy io ctrl save and resume
Update feature:
	96550638e plat: px30-s: dram: phy io ctrl save and resume
	16b51a9f9 plat: px30-s: dram: fix ck/ckb to low before deepsleep
	90c6c51f7 plat: rockchip: rk3588: Set gpll source clock div to 0
	c5157a42e plat: px30-s: Restore DDR PHY dfi low power function
	0de2c3db8 plat: px30: sleep: enter ddr sref by software
	16fda9dd6 plat: px30s: suspend: add ddr resume support
	91188bd6f plat: px30: suspend: support ddr resume

Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
Change-Id: I5cc4bf115cc194a6c6c21ea452031d0898fe1b97
This commit is contained in:
Zhihuan He
2022-02-18 18:01:13 +08:00
committed by Jianhong Chen
parent 9940cf2a75
commit 61923c8335
3 changed files with 2 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
RKTRUST/RK3326TRUST.ini
View File

@@ -5,7 +5,7 @@ MINOR=0
SEC=0
[BL31_OPTION]
SEC=1
PATH=bin/rk33/rk3326_bl31_v1.26.elf
PATH=bin/rk33/rk3326_bl31_v1.27.elf
ADDR=0x00040000
[BL32_OPTION]
SEC=1

2
RKTRUST/RK3358TRUST.ini
View File

@@ -5,7 +5,7 @@ MINOR=0
SEC=0
[BL31_OPTION]
SEC=1
PATH=bin/rk33/rk3326_bl31_v1.26.elf
PATH=bin/rk33/rk3326_bl31_v1.27.elf
ADDR=0x00040000
[BL32_OPTION]
SEC=1

BIN
bin/rk33/rk3326_bl31_v1.26.elf → bin/rk33/rk3326_bl31_v1.27.elf
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