from commit:
rk_boot_all: e6c168
update feature:
src: spinand: Support new devices
Change-Id: I8c91dbc80507c4b90c8e4933c9fbdeb72aef1cbb
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
from commit:
rk_boot_all: e48799: src: spinor: Support 4KB erase aligned
update feature:
Support spinor 4KB erase aligned
Change-Id: Id0fc2751744a7ff1555e919623bc5b57cb650120
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
build from:
rk_boot_all c38741 src: spinand: support GD5F2GM7xxG
update feature:
Support new spiflash
Change-Id: I7ba8cf6be24532969700ba432efbdc8a560c3a23
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
build from next-dev:
9080840a12 drivers: ram: rv1126: Detect byte map of x16 DDR3/DDR4
update feature:
9080840a12 drivers: ram: rv1126: Detect byte map of x16 DDR3/DDR4
build command:
CONFIG_SPL_KERNEL_BOOT=y
for lpddr3 bin, CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE need set to 6.
for lpddr4 bin, CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE need set to 7.
default CONFIG_ROCKCHIP_DRAM_EXTENDED_TEMP_SUPPORT=n, if you need
extended temperature bin, you need enable "CONFIG_ROCKCHIP_DRAM\
_EXTENDED_TEMP_SUPPORT", then rebuild uboot.
./make.sh rv1126 && ./make.sh tpl.
Note:
the pre-build 528MHz binary disable ODT.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Change-Id: If0e8207e9e4b9e36850dbc7fb6aabebfc8a32bd8
build from:
rk_boot_all a00b18c src: platform: rv1126: Update to 1.20
build feature:
support new flash devices, W25N512GVEIG, GD5F1GQ4UExxH
Change-Id: I8e5fbea2a0a64cf7dd82b79ae9b15881ed3623e6
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
build from:
rk_boot_all b9678f6f src: spinand: not cache recheck for XTX device
build feature:
support new flash devices
Change-Id: I5e72a26108fa7004a61f8caf1acf8e162bb7ff80
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
build from next-dev:
b1b9d7fba4 drivers: ram: common: fix ssmod define err
update feature:
b1b9d7fba4 drivers: ram: common: fix ssmod define err
d49e7c3403 drivers: ram: rv1126: fix the judgment of "set ctl address map fail"
06a17b4adf drivers: ram: rv1126: Turn on DQS_c 2k pull-up resistor to workaround WDQS control of LPDDR4/LPDDR4X
246ad23dbf drivers: ram: rk356x: fix read_mr() of LPDDR3
e90784abb2 rv1126: ddr: fix tx dqs bypass phase setting err
c2a03d5d81 drivers: ram: rv1126: add support lpddr4x
bf922fc800 drivers: ram: rv1126: fix calculating of MSCH_DeviceSize
e2dc1cc022 drivers: ram: rv1126: Modify tRFC and related timing based on DDR capacity
330cd12fc3 drivers: ram: rv1126: fix return value of read_mr()
3993b0c711 drivers: ram: rv1126: Set default value of die bus with to x16 when bus width is x16/x32 of DDR3
9050e1f82e drivers: ram: rv1126: fix tZQLAT of LPDDR4
build command:
CONFIG_SPL_KERNEL_BOOT=y
for lpddr3 bin, CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE need set to 6.
for lpddr4 bin, CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE need set to 7.
default CONFIG_ROCKCHIP_DRAM_EXTENDED_TEMP_SUPPORT=n, if you need
extended temperature bin, you need enable "CONFIG_ROCKCHIP_DRAM\
_EXTENDED_TEMP_SUPPORT", then rebuild uboot.
./make.sh rv1126 && ./make.sh tpl.
Note:
the pre-build 528MHz binary disable ODT.
Change-Id: Ibb384f60d714535822202330d2c3ae3cef75337c
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
from commit: 726484
src: slc_flash: Support F59L4G81KAR1AM
Change-Id: I59468d493093496020a3f89915895013e018d73e
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
build from rk_boot_all:
commit id: a409e672ccd: add erase data api for spi nand and slc nand
update feature:
1. support nvm switch function by usb
2. add erase data api for spi nand and slc nand
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: Ic0754669fdf039e3f37ceb25b0b85121af18edc6
Build from rk_boot_all commit:
0c7ec: src: spinand: Support BWJX08K-2Gb
Update feature:
Support new SPI flash
Change-Id: Id74e5c9dd229cfac116da5521b9ffc90ec868dc6
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Build from rk_boot_all commit:
29eb64 src: platform: rv1126: Update to v1.15
Update feature:
Support new SPI flash
Change-Id: Ibc05db6f2dd9dc4e2d707e2cdb8583e1bcb40dc4
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Build from rk_boot_all commit:
a593123211 src: flash: Change to reserve 8 blks for IDB without FTL
Update feature:
Change to reserve 8 blks for IDB without FTL
Change-Id: I69f1341a3569acbb9542bdb68de91b421d8f34fc
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
build from next-dev:
507e690 lib: rsa-verify: require np/c factor if using hardware decrypt
build command:
CONFIG_SPL_KERNEL_BOOT=y
for lp3 bin, CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE need set to 6.
default CONFIG_ROCKCHIP_DRAM_EXTENDED_TEMP_SUPPORT=n, if you need
extended temperature bin, you need enable "CONFIG_ROCKCHIP_DRAM\
_EXTENDED_TEMP_SUPPORT", then rebuild uboot.
./make.sh rv1126 && ./make.sh tpl.
update feature:
1)ddr3 16bit support
2)optimizing ddr performance for bandwidth 16.
Change-Id: I5293dbadd36e32ae4c95eed2ca98f7a78de12426
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
from commit: ff6dc6fe57606621795a57d3cbd29cb72fb2a3e8
Support new SPI flash including GD5F1GQ5UEYIG
Change-Id: I474d37ecbda3f320db3fdeed4baa2d6feb292e6f
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
build from next-dev:
7c7fff3 clk: rockchip: rk3288: support get pll config by table
build command:
./make.sh rv1126-emmc-tb
update feature:
Switch to boot FIT image
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I99ebe949a80b08c469fa60c60f4a7c9662b8ed23
build from next-dev:
ee5f082 rv1126: ddr: add extended temperature support
build command:
CONFIG_ROCKCHIP_THUNDER_BOOT=y
for lp3 bin, CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE need set to 6.
default CONFIG_ROCKCHIP_DRAM_EXTENDED_TEMP_SUPPORT=n, if you need
extended temperature bin, you need enable "CONFIG_ROCKCHIP_DRAM\
_EXTENDED_TEMP_SUPPORT", then rebuild uboot.
./make.sh rv1126 && ./make.sh tpl.
update feature:
1) update driver strength.
2) fix bug of wr training fail.
3) fix dram bandwidth detect error.
4) support dqs layout longger than clk.
Change-Id: Ia79830e06e6b5f8f2e929a760414587e60f91754
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
from commit: 4910c7834a05bcbfa94bdc4c6c9a813f2eeec9e8
Update good block searching strategy for open source code
Change-Id: Ic9d803d7e94a849e744f6e9828e09bc5e4d87f8f
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
