build from:
e748f9ce32b dram_init: rk3506: add cpu rt schedule setting
update feature:
1. Added cpu real-time support for RK3506 and RK3506B.
2. Fixed the issue that ddrbin incorrectly entered the resume process.
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
Change-Id: I41e933d1a29dea77f2cc7953206b4953c2c1461d
Build from OPTEE commit in develop-next branch:
7e3f76304 rv1126: add rv112d support
Update features:
7e3f76304 rv1126: add rv112d support
a93f7e946 scripts: checkbuild: modify platform detect method
efddd55dd core: rockchip: enable atags and pstore in MOS
6b118d039 rockchip: fiq debugger: support separate stack for os callback
4f75b8a89 plat-rockchip: add multi os support
e9cc2fd6a plat-rockchip: sip: add more sip command for dmc
29b1dbc92 core: optimize memory info log to avoid misunderstand
57604957e pta: rk_os_service: add support for dolby
db0018c0b ree_fs_ta: fixed read ta_ver.db error cause by poweroff
Change-Id: I3c8e95bae366cc2e49d2eaf287385b8499313b5e
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
Build from OPTEE commit in develop-next branch:
6b118d039 rockchip: fiq debugger: support separate stack for os callback
Update features:
6b118d039 rockchip: fiq debugger: support separate stack for os callback
a55ef8f90 drivers: rockchip: trng: add rv1103b support
b7f14a533 drivers: hal_crypto: rv1103b: fix crypto clock bug
cb26c14a8 drivers: hal_crypto: add rv1103b support
e9cc2fd6a plat-rockchip: sip: add more sip command for dmc
29b1dbc92 core: optimize memory info log to avoid misunderstand
db0018c0b ree_fs_ta: fixed read ta_ver.db error cause by poweroff
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
Change-Id: I20fb2ea774d8186a70ae58ce8311afbd813efe1a
Build from optee commit in develop-next branch:
3ea8b24a1 rk3506: enable CFG_CORE_DYN_SHM and CFG_RK_USE_RESERVED_SHM
Change-Id: I428bfaf8f476976da08c4e31d36e218754b330b2
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
from commit:
48fb7bc rk322xh: update DDR Version 1.21 20241126
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
Change-Id: I4198347b7b9f8c96e203e59ff996edc738e37b1d
from commit:
48fb7bc rk322xh: update DDR Version 1.21 20241126
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
Change-Id: I5a3bdfd6a1b506aba31dbd2d48feb208cab50b1c
Build from ATF commit:
059b3c586 opteed: pm: restore icc_pmr after on_finish/suspend_finish handle
update feature:
059b3c586 opteed: pm: restore icc_pmr after on_finish/suspend_finish handle
f59798f60 plat: rockchip: Optimize some function names and code commenting
069fc8a18
4858aa126 plat: rk3528: only enable one ca odt in same channel
f1e50a2bc plat: rockchip: move rockchip_cpus_status to common file
810119069 plat: rk3528: virt-poweroff: dump wakeup source
6a314b999
a0178dfb6
bffcafacd plat: rk3528: dmc: add axi split support for suspend/resume
ba6ef224d rockchip: common: add ACCESS_MEM_OS_REG define
5fb78cd64 rockchip: uart: switch to loopback mode before checking busy status
02ff3b0da rockchip: uart: save uart register once
cafe351b4 rockchip: support non-24M counter
524fc65d0 rockchip: scmi: clock: add common clock
4a52a1f56 plat: rockchip: uart: set max timeout 5.6ms wait for uart busy
f282bdae0 rockchip: pstore: fix the error that rb->start is too big
Change-Id: I265f88dea3fe54154e7837db9c36d8a59b790d61
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
Build from OPTEE commit in develop-next branch:
57604957e pta: rk_os_service: add support for dolby
Update features:
57604957e pta: rk_os_service: add support for dolby
902ec504b rk3588: add function for dolby
db0018c0b ree_fs_ta: fixed read ta_ver.db error cause by poweroff
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
Change-Id: Ife35f04e3fcc899d5b01dfe5d6e29e1db47fbef0
Build from:
0e7e5b3c7ff rk3506: Add 'rockchip,sleep-io-config' setting support
Update features:
0e7e5b3c7ff rk3506: Add 'rockchip,sleep-io-config' setting support
5813e173a28 rk3506: pmu: Power up v1pll before logic off suspend
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Id5448cb5046fb086203d62e75f314b4faef32775
build from:
508b0f9682 dram_init: rk3506b: update ddr3 driver strength
update feature:
1. Update d3/d2 drv for rk3506b/j.
2. Add rk3506j support.
3. Fix emmc download failure issue.
4. Since most DDR2 chips can only reach a maximum of 533M,
the default DDR2 frequency is changed to 451MHz
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
Change-Id: I746ff161f588dbe00cacc622751999e17bf4536c
Build from OPTEE commit in develop-next branch:
9f2aca7d1 pta: uboot_storedata_otp: reinit ssk when set security level2
Update features:
9f2aca7d1 pta: uboot_storedata_otp: reinit ssk when set security level2
d038af9d2 pta: uboot_storedata_otp: add check for rpmb key
679d5bd8f core: tee: add func for check rpmb key is written
9be174551 rockchip: uart: Add real uart hw init
6b3714286 Revert "libcrypto: set RSA OAEP MGF1 MD function to SHA1"
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
Change-Id: I02da572751f84af3f918651602d2683d17ebf9fc
Build from OPTEE commit in develop-next branch:
9f2aca7d1 pta: uboot_storedata_otp: reinit ssk when set security level2
Update features:
9f2aca7d1 pta: uboot_storedata_otp: reinit ssk when set security level2
d038af9d2 pta: uboot_storedata_otp: add check for rpmb key
679d5bd8f core: tee: add func for check rpmb key is written
144ae5ffd drivers: hal_crypto: added alignment judgment for input and output addresses
9be174551 rockchip: uart: Add real uart hw init
6b3714286 Revert "libcrypto: set RSA OAEP MGF1 MD function to SHA1"
6b9b39300 ta.mk: not copy lib/libcrypto/include to host_include
0ca603d39 plat-rockchip: modify conditions for read secure boot flag
fd6b94676 plat-rockchip: vendor_props: fix xtest regression_1006 fail
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
Change-Id: I07ec5d6911900faa79068ef159a94459fa8f3db7
Build from OPTEE commit in develop-next branch:
9f2aca7d1 pta: uboot_storedata_otp: reinit ssk when set security level2
Update features:
9f2aca7d1 pta: uboot_storedata_otp: reinit ssk when set security level2
d038af9d2 pta: uboot_storedata_otp: add check for rpmb key
679d5bd8f core: tee: add func for check rpmb key is written
9be174551 rockchip: uart: Add real uart hw init
6b3714286 Revert "libcrypto: set RSA OAEP MGF1 MD function to SHA1"
6b9b39300 ta.mk: not copy lib/libcrypto/include to host_include
0ca603d39 plat-rockchip: modify conditions for read secure boot flag
fd6b94676 plat-rockchip: vendor_props: fix xtest regression_1006 fail
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
Change-Id: Ibb3e8563fb713a0d5a19ea3072dd22fa3f47296e
Build from OPTEE commit in develop-next branch:
9f2aca7d1 pta: uboot_storedata_otp: reinit ssk when set security level2
Update features:
9f2aca7d1 pta: uboot_storedata_otp: reinit ssk when set security level2
d038af9d2 pta: uboot_storedata_otp: add check for rpmb key
679d5bd8f core: tee: add func for check rpmb key is written
9be174551 rockchip: uart: Add real uart hw init
6b3714286 Revert "libcrypto: set RSA OAEP MGF1 MD function to SHA1"
6b9b39300 ta.mk: not copy lib/libcrypto/include to host_include
0ca603d39 plat-rockchip: modify conditions for read secure boot flag
fd6b94676 plat-rockchip: vendor_props: fix xtest regression_1006 fail
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
Change-Id: I69df3827275e4d90f7ec115eac11c87b06182043
Build from OPTEE commit in develop-next branch:
9f2aca7d1 pta: uboot_storedata_otp: reinit ssk when set security level2
Update features:
9f2aca7d1 pta: uboot_storedata_otp: reinit ssk when set security level2
d038af9d2 pta: uboot_storedata_otp: add check for rpmb key
679d5bd8f core: tee: add func for check rpmb key is written
6304c3979 drivers: rockchip: keylad: clear keytable after use
144ae5ffd drivers: hal_crypto: added alignment judgment for input and output addresses
9be174551 rockchip: uart: Add real uart hw init
6b3714286 Revert "libcrypto: set RSA OAEP MGF1 MD function to SHA1"
0ca603d39 plat-rockchip: modify conditions for read secure boot flag
4cd67e2b3 plat-rockchip: common: support soft ta encryption key
7eeac5fbf core: rpmb: change read data to multiple times
cb202f37a libutee: increase MPI_MEMPOOL_SIZE size
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
Change-Id: If75f2d313ffa890aca013a24fa4c6b5ef671f9aa
Build from ATF commit:
b21ffefc7 plat: rk3576: sleep: Add control for PLDO2 in the system suspend/resume
update feature:
b21ffefc7 plat: rk3576: sleep: Add control for PLDO2 in the system suspend/resume
b140017c6 plat: rk3576: fix the mrr_cycles issue for LPDDR5 of one rank
Change-Id: Ie3b259708547dea133d18c018ff500642f5081d8
Signed-off-by: Shengfei Xu <xsf@rock-chips.com>
Build from:
da47953620 dram_init: rk3308: Updata to v2.10
Update feature:
7ac0a4731c dram_init: rk3308/rv1108: fix the bug in ddr2 bank
detect process
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
Change-Id: Iec5cc7165fbd355f00bad2630fb4db72dcdaab51
