This is a prefix path from legacy rkdevelop U-Boot, we remove
it since there is not such path in rkbin project.
Change-Id: I7149b77a2d7ddaaf741ea98beeb75ecba63ad4c1
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
This is a prefix path from legacy rkdevelop U-Boot, we remove
it since there is not such path in rkbin project.
Change-Id: I17337389ced3feb104637825fc12496c15ac6f0e
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
build from next-dev with command: ./make.sh rk3399
on commit:
(2e6f3f4 tool: rockchip: boot/trust_merger: ignore prepath when it's already exist)
Change-Id: If82105789adbf2f500cca08468d1b94e34bc4e00
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Build from ATF commit:
51f2096 plat: rk3399: ddr: fix lpddr4 some timing error
update feature:
this bl31 is match ddr bin Version "DDR Version 1.22 20190506"
Change-Id: Ibcadbd24822c3f40650078dc6354a25d94f9a68e
Signed-off-by: CanYang He <hcy@rock-chips.com>
This reverts commit 2279615dc94327923bde221f632e6a2161d9c30b.
Change-Id: I0d8676107b56c8ab975196d5723e052d3007e2f3
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Build from ATF commit:
51f2096 plat: rk3399: ddr: fix lpddr4 some timing error
update feature:
this bl31 is match ddr bin Version "DDR Version 1.22 20190506"
Change-Id: Iac9d9cd63850aefdc2997712d40c6a62b04ae694
Signed-off-by: CanYang He <hcy@rock-chips.com>
update feature:
a9067a8 rk3368: disable uart output and update bl30 to v2.15
Change-Id: Ief740e0192812861abefe275c57607ab96c2e05b
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
built from ddr init project commit:
ebd89a6 version: DDR Version 1.07 20190329
update feature:
7b0f07c rk32: ddr: add atags support
f8ec0a8 rk32: ddr: using unify global argument for uart, dram info config
Change-Id: Icfbeeb7f271f8654d4785047c4abbe2679014d70
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
print info: DDR Version V1.08 20190329
from commit:
6130bc8 rk322x: ddr update to v1.08
update feature:
28d5e62 rk322x: ddr: add data check after training
eae3a4f rk3228: ddr: add atags support
07e8bf1 rk3228: ddr: using unify global argument for uart, dram info config
Change-Id: I27900534d21fcf75618436f2e7da00f3b22db041
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
print info: DDR Version V1.08 20190329
from commit:
6130bc8 rk322x: ddr update to v1.08
update feature:
28d5e62 rk322x: ddr: add data check after training
eae3a4f rk3228: ddr: add atags support
07e8bf1 rk3228: ddr: using unify global argument for uart, dram info config
Change-Id: I78b10f894e712231e73b4191d6cc76118770c028
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
print info: "DDR Version v2.04 20190329"
from commit:
68929e9 rk3368: ddr init code update to v2.04
update feature:
641cb68 rk3368: ddr: add data check after training
602b1c7 rk3368: ddr: add atags support
3e51f02 rk3368: ddr: using unify global argument for uart, dram info config
Change-Id: I914424a78a50e389fd09315935c837a47254310c
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
print info: DDR Version 1.14 20190328
from commit:
70ebea9 rk3328: ddr: update init code to v1.14
update feature:
d5771e2 rk3228H: ddr: add data R/W check after gate training
bf5693b rk3228H: ddr: add atags support
59d6b97 rk3228H: ddr: using unify global argument for uart, dram info config
Change-Id: I79ad1de3573b1cc810d8c09b08f545149a1165fd
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
Build from ATF commit:
6e39e59 plat: px30: change some debug info
update feature:
6e39e59 plat: px30: change some debug info
cba4b12 rockchip: svc: add CONFIG_DRAM_POST_SET_RATE sip call
b0cf3d1 rockchip: sram: add pmu_sram section defines
526676a rockchip: i2c: add i2c driver to common directory
c2b0155 plat: rockchip: move the function about dram spec timing to common
e1048e0 rockchip: console: enable/disable depends on atags serial
1f45fd9 rockchip: atags: compatible old preloader without atags support
a211ba1 plat: px30: use plat_uart_xxx to init console
ef42cbc plat: rockchip: support use preloader and kernel serial
f2cbed3 console: add console_simple_init() to initial console base addr
de92d92 plat: rockchip: add rk_atags support
36d01de plat: rockchip: move DIV_ROUND_UP to plat_private.h for common use
b275060 plat: px30: suspend: support pwm remotectl parse
e52f4a9 rockchip: move pwm_remotectl driver to public directory
43a2da1 rockchip: sip: allow SLT to access all memory region
9c6fa6a plat: px30: dfs: add support trigger dfs by vop intr
89a2d33 plat: px30: dfs: reduce the time of DCF wait dma finish
fc8ed34 plat: px30: dfs: update dcf code to V1.02
aebc56c plat: px30: dfs: set MSCH_DdrMode.MwrSize to zero
d964b6b rockchip: ddr_parameter: fix param layout description error
f9721cd plat: px30: dfs: compensate refresh for data_training
7dbdf27 plat: px30: dfs: reduce the execute time of data_training
dc2ca0e px30: pmu: fix compile error when not set DEBUG=1
Change-Id: I877b89a0fb142d9f1d063aca6ab4cb2dbc37590c
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
Build from ATF commit:
6e39e59 plat: px30: change some debug info
update feature:
6e39e59 plat: px30: change some debug info
cba4b12 rockchip: svc: add CONFIG_DRAM_POST_SET_RATE sip call
b0cf3d1 rockchip: sram: add pmu_sram section defines
526676a rockchip: i2c: add i2c driver to common directory
c2b0155 plat: rockchip: move the function about dram spec timing to common
e1048e0 rockchip: console: enable/disable depends on atags serial
1f45fd9 rockchip: atags: compatible old preloader without atags support
a211ba1 plat: px30: use plat_uart_xxx to init console
ef42cbc plat: rockchip: support use preloader and kernel serial
f2cbed3 console: add console_simple_init() to initial console base addr
de92d92 plat: rockchip: add rk_atags support
36d01de plat: rockchip: move DIV_ROUND_UP to plat_private.h for common use
b275060 plat: px30: suspend: support pwm remotectl parse
e52f4a9 rockchip: move pwm_remotectl driver to public directory
43a2da1 rockchip: sip: allow SLT to access all memory region
9c6fa6a plat: px30: dfs: add support trigger dfs by vop intr
89a2d33 plat: px30: dfs: reduce the time of DCF wait dma finish
fc8ed34 plat: px30: dfs: update dcf code to V1.02
aebc56c plat: px30: dfs: set MSCH_DdrMode.MwrSize to zero
d964b6b rockchip: ddr_parameter: fix param layout description error
f9721cd plat: px30: dfs: compensate refresh for data_training
7dbdf27 plat: px30: dfs: reduce the execute time of data_training
dc2ca0e px30: pmu: fix compile error when not set DEBUG=1
Change-Id: If78a95e124928b1735b7d13029b0a1e1eea4d14d
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
build from:
081e3d6 plat-rockchip: fiq debugger: support Thumb entry point
update feature:
081e3d6 plat-rockchip: fiq debugger: support Thumb entry point
77e9bc1 core: arm: support Thumb entry point
Change-Id: I4f6d0274f1a3d259ffbcd869ab0d649850932950
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
from commit: ccb171b14c138f0fe0b76d94c09345bcedc4cfee
reserve 512 bytes valid zero data for idblock secureboot.
Change-Id: I8a7e9ef4a989a4fe5124a8db3439129ae6df8868
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
