Build from OPTEE commit in develop-next branch:
87d94c5ef8 plat-rockchip: main: support hdcp key init via tee_entry_fast
Update features:
87d94c5ef8 plat-rockchip: main: support hdcp key init via tee_entry_fast
974e478864 plat-rockchip: rk3588: move rk_hdcpkey_init API to keyladder.c
0af3483b2e pta: crypto_service: support user ta call hard cipher
778974be4e core: tee: calculate node hash with meta default
4167319d34 core: tee: recreate dirf.db if open dirf.db fail
b61fa300d3 scripts: commit_bin: intercept the first 8 characters for LAST_CM
8e053a8819 rockchip: remove duplicate definitions for toybrick seed
Signed-off-by: Wang Xiaobin <xb.wang@rock-chips.com>
Change-Id: Id8c298a29bdc1c275fbc6676d93fc3f67609d199
build from optee commit in develop-rk3228 branch:
b37bf5f61 ddr: rk3228: select dpll power down mode 1
update feature:
fe1ece27b ddr: rk312x: select dpll power down mode 1
7728d9210 ddr: rk312x: add DPLL power down and up
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
Change-Id: I9c4edd2633bd12528a08e403309255b22d19da4d
from commit:
a883fb rk_boot_all
update fiture:
src: spinor: Fix rockusb return value
Change-Id: I569d22440291f816d3a30fe88f3a94b999691f5e
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
build from:
61825302a plat: rk312x: support 128M ddr
9b7567807 ta verify: close default key for sign ta
Change-Id: I70ecbd988e7ac149a5e4769437105a498d14d617
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
from commit:
rk_boot_all: e0b2ae
update feature:
Config erase operation as SFC write direction
Change-Id: I0d9c050c502437a1d79237a5949d3cdadf958ddf
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Build from ATF commit:
ae7c295ca rockchip: scmi: base: fix protocol list response size
update feature:
ae7c295ca rockchip: scmi: base: fix protocol list response size
834a4578c plat: rockchip: scmi: Add support to set low length for cpub
5d208a630 plat: rockchip: scmi: not allowed rate = 0 to set rate
37771fb0f rockchip: cpus_on_fixed_addr.S: ldr instead of adr for Position-independent
61463dac0 plat: rockchip: support aes_ctr.
bd56a9a02 plat: rockchip: support config irq aff by sip call
fc6a6b092 rockchip: plat_pm: add functions for cpu on/suspend resume
c0152bd35 opteed: Mask non-secure interrupts if the cpus will be off
5d54ce865 plat: rk3568: fix pwm0 output error when exit ultra suspend
8f8c332d6 plat: rk3568: support to config cache write streaming
3f58c537b rockchip: common: Add boot1 param for atags
698f83a30 rockchip: gicv3: add plat_rockchip_gic_its_quiescent function
67c9cdc3e lib: psci: Add weak psci_plat_system_suspend_prepare()
cb84541ac plat: rk3568: set the ATF RAM as secure
29d00ad58 rockchip: gicv3: support getting routing cpu.
898fdcd8a rockchip: only use plat_uart_base to initialize console
0337c56f8 plat: rockchip: scmi: mark clk_ops as const
c2e74efff rockchip: support sram_reuse section
d1849fccd plat: rockchip: add system control function for OPTEED.
5057c23a4 plat: rk3568: dmc: set NOC response type when change ddr freq
31f716829 plat: rk3568: sram init section use RW attribute
87a9dbe8e rockchip: scmi_clock: return cur_rate if no get_rate ops or get_rate return 0
58314759f make.sh: compile with "ARM_ARCH_MINOR"
58dc14a62 rockchip: fiq-debugger: fix error if fiq from el0
5bd6aa529 plat: rk3568: dmc: disable clk drv when suspend for ultar board
8e24b5662 plat: rk3568: dmc: remove struct ddr_dts_config_timing
5bede8da8 rockchip: simplify cpu_context's initialization
4edcdbb82 plat: rk3568: dmc: no longer get ddr timing from DTS
24ab016fc plat: rk3568: add support dfs_fsp_init
e7ed08b1f plat: rockchip: dram: update ddr_params.h
23d3e9d8b plat: rockchip: update rockchip_sip_svc for support dfs_fsp_init
78c6a27b5 plat: rk3568: use sram init section
c9a647cae plat: rk3568: dmc: update dcf code to v1.08
Change-Id: Ia3bf2c2b89351547eb02710f982a6749590c169c
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
Build from ATF commit:
55ca4fb1c plat: rk3588: support suspend from uboot
update feature:
55ca4fb1c plat: rk3588: support suspend from uboot
e1e41ada7 plat: rk3588: support RK_SIP_WDT_CFG
b1777a134 rockchip: svc: add RK_SIP_WDT_CFG define
5a6cefa04 plat: rockchip: rk3588: scmi: change pvtpll config for cpu gpu and npu
834a4578c plat: rockchip: scmi: Add support to set low length for cpub
b0aca2fce rockchip: wdt: move wdt macro to wdt.h
Change-Id: Ife7cb34e9e4d46d59055b0a3bd7530739515b5d3
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
support mcu wrap isp and venc
mcu use sram 0xff6ff000 - 0xff6fffff
build from rockit-ko
rockit-ko:
https://10.10.10.29/c/linux/rockit-ko/+/152944
Update feature:
1.mcu check once per 32 line and update vpu register
2.max height support to 2048
3.not support scall
Change-Id: Ibf8bb3cee8ec9edaa9bd9506f6264ee79d2e082d
Signed-off-by: aaron.sun <aaron.sun@rock-chips.com>
Build from:
5dc6490a60 drivers: ram: rv1106: Initial version v1.06 20220509
(https://10.10.10.29/c/rk/ubd/+/145841/42)
Update feature:
1. Set defalut pack to QFN
2. Add 528MHz of DDR3 (Config 528MHz with ddrbin_tool)
3. Do not print warning when read eye trn flag is high, because
it is easy to happen at low freq
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Change-Id: I40ada0a143b7b0b561fcc88f0c24f88ec7b29b52
build from:
03d6779 updata to version v1.10 20220506
update feature:
5854a58 tool: support -g gen.txt to modify ddrbin file
f088447 updata to version v1.10 20220406
0d86ab0 tool: add eye scanning support
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
Change-Id: I6cf674398d64243513eebbe0025597ea2ebcaa96
Build from u-boot-ddr:
drivers: ram: rv1106: Initial version v1.05 20220425
(https://10.10.10.29/c/rk/u-boot-ddr/+/145841/41)
Update feature:
1. Read OTP to get pack
2. Adjust NOC ReadLatency of DDR3 924MHz & 1056MHz
3. Delete 324MHz & 396MHz of DDR2
4. Enable PVTPLL
5. Config DDR_GRF_CON1&2 for power consumption
6. QFN gets SI info from MACRO, BGA gets SI info from
loader_params.inc
7. Set reg_train_2t_mode, and fix reg_cmd_2t_mode to 0x7fffff
8. Exit read gate if detect error flag
9. Fix set of t_xs_x32, t_xs_abort_x32 and t_xs_fast_x32
10. wait_phy_pll_lock in ddr_set_rate()
11. Decrease delay between rkclk_ddr_reset(dram, 1, 1, 1, 1) and
rkclk_ddr_reset(dram, 1, 1, 1, 0)
12. Call dram_all_config and enable_low_power in post_init
13. Add delay when detect row
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Change-Id: Ic125bf2081c01aafdd6ef473c9b2145d41337a66
Build from u-boot-ddr:
c44e2c2649 drivers: ram: rv1106: Initial version v1.02 20220330
(https://10.10.10.29/c/rk/u-boot-ddr/+/145841/37)
and change baudrate to 115200
Update feature:
Change baudrate to 115200
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Change-Id: Ic18c28757ae38670e27e5a1a0f6cc94ba4271f27
from commit:
rk_boot_all: fb9f8e: src: spinor: Support new spiflash
update feature:
Support new spiflash
Change-Id: I634d9f1707da419bafa3bf8d42778c8e758fe7c7
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Build from u-boot-ddr:
c44e2c2649 drivers: ram: rv1106: Initial version v1.02 20220330
(https://10.10.10.29/c/rk/u-boot-ddr/+/145841/37)
Update feature:
c44e2c2649 drivers: ram: rv1106: Initial version v1.02 20220330
(https://10.10.10.29/c/rk/u-boot-ddr/+/145841/37)
1. Fix 328MHz to 324MHz, 664MHz to 660MHz, 784MHz to 780MHz
2. Fix ReadLatency of NOC (-50)
3. Delete DQ skew cfg of DDR2
4. Set DeviceSize of NOC
5. Fix PHY PLL set
6. Fix wrong calc of wrlvl_info.tdqss_min/max
7. Fix wrong set of tRFC
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Change-Id: I78755018346355647a28e5b85ee2ee390c49605d
Build from ATF commit:
7380d9813 plat: rockchip: rk3588: dmc: configure sr_en and pd_en based on idle value
update feature:
7380d9813 plat: rockchip: rk3588: dmc: configure sr_en and pd_en based on idle value
fedf3922d plat: rockchip: rk3588: dmc: add support LPDDR5 frequency scan
9328b4ce3 plat: rockchip: rk3588: dmc: clrbit RD_CAL_MODE if rd deskew is 0
Change-Id: Id5c38d95b2f74a17c03c7b3ff04345ddc66c947b
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
from commit:
rk_boot_all: 209c77: src: spinand: Add SNAND tag for spinand PC tools
Update feature:
src: spinand: Add SNAND tag for spinand PC tools
Change-Id: Id03fc440a9d987c974bce0736e4494b5e0e939d5
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Build from u-boot-ddr:
0cc2c5d0bd drivers: ram: rv1106: Initial version v1.01 20220325
(https://10.10.10.29/c/rk/u-boot-ddr/+/145841/33)
Update feature:
0cc2c5d0bd drivers: ram: rv1106: Initial version v1.01 20220325
(https://10.10.10.29/c/rk/u-boot-ddr/+/145841/33)
1. Fix wrong calc of ddrconf, which ignore col
2. Do not init UART2 when in UART download
3. Fix wrong of memcpy of NOC
4. Fix wrong of update_dq_tx_skew/update_dq_tx_skew
5. Fix wrong of Disable PVT
6. Enable 2T of PHY_REG 0x1c
7. Return error if changing freq fail
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Change-Id: I4e564b8322623834d8e117efd4dc1387f66fbffa
