Important Notice: ddr bin v2.00 and later DO NOT support RK3308A(CHIP ID
= 0x0CEA). Please use ddr bin v1.29 for RK3308A.
build from u-boot-ddr:
2355fc526d dram_init: rk3308: update to v2.06
and cherry pick from u-boot | next-dev:
786fea6f82 drivers: ram: rv1108_pctl_phy: fix value of dll bypass regs
update feature:
d4b95bfb8b dram_init: rk3308: Add support of UART3 M1
07dde227db drivers: ram: rk3308: Add 294MHz
383c9c5c9a drivers: ram: rk3308: Adjust the way to assign value to sdram_configs
4a561efa5e drivers: ram: rk3308b-s: Fix calculation of Rx DQS skew of DDR2 & LPDDR2
acfae9184e drivers: ram: rk3308: Fix DRAM_ODT_EN_FREQ/PHY_ODT_EN_FREQ of LPDDR2
dbb5d8304f drivers: ram: rk3308: Fix tRRD of DDR3 451MHz
592950db9c drivers: ram: rk3308b-s: Modify the judgment of read gate result
8403d9cddf dram_init: dram_init_main: Invalid iCache when exiting dram_init_main()
build command:
cd dram_init
./make.sh rk3308
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Change-Id: Icf70bda9c5c86fb140650d6ebddfff76493290c6
Build from OPTEE commit:
ef7f159d
update feature:
ef7f159d
93218d76 plat-rockchip: otp: refine otp map defines
6e7c7880 core: otp: move otp map defines to platform respective file
8aabe4b8 plat-rockchip: config: sort config defines in alphabetical order
783935ed plat-rockchp: conf.mk: extract common configs
3b708b87 plat-rockchp: conf.mk: use $(call force, ...) to set values
6ac046ad core: use local time but not universal time
3e6c3d74 core: fix build error for expansion defined
825d470d lib: libutils: fix duplicate macro definitions
30c8b31d core: boringssl: fix build error for fall through
484bf66f lib: newlib: fix build error for fall through
273e9429 lib: libcxx: fixed no return error
753447cd lib: libcrypto: avoid macro definition conflicts
9a14fc75 plat-rockchip: conf.mk: mv crypto related config to separate file
958b8cef pta: rk_os_service: add GET_TRNG cmd support
c2b06d42 driver: rockchip: remove trng driver from crypto module
665a769d lib: libcrypto: add support for aes-xts
f3fa4248 lib: libcrypto: porting new version into OPTEE
fad0a581 lib: update BoringSSL
6453d8ba rv1126: otp: set nvm failtime to 19
75f71b29 pta: rk_os_service: change value of a macro definition
2b1ff59a pta: rk_os_service: add api for get oem otp size
c72692a9 ta: ta.mk: export CFG_CXX CFG_TUI vars
Change-Id: I094cede648a79b8f7ee28ce4d4a4bc9a06988092
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
build from:
rk_boot_all 69b359 src: spinand: support GD5F2GM7xxG
update feature:
Support new flash
Change-Id: I73fa55a2f464784284955d7d2f3de4ca069e065b
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
build from:
69b359 src: spinand: support GD5F2GM7xxG
update feature:
Add spiflash only version, delete sdcard and emmc support
Change-Id: Ib7f4a3c732017b24625daef6963ff684455657b4
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
build from:
8a6bcbf src: spinand: Check only the devices in need
update feature:
src: spinand: Check only the devices in need
Change-Id: If4fc6a008a69e68cf30777f9fc4d56be214777bd
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
build from:
rk_boot_all c38741 src: spinand: support GD5F2GM7xxG
update feature:
Support new spiflash
Change-Id: I7ba8cf6be24532969700ba432efbdc8a560c3a23
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
build from:
69b359 src: spinand: support GD5F2GM7xxG
update feature:
support new spiflash
Change-Id: I6d31582ff7b1f07106ed594c9999d918ca2051ba
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Build from ATF commit:
d5a5a89b7 plat: rk3308: use min voltage 0.843v for rk3308bs vdd_core
update feature:
d5a5a89b7 plat: rk3308: use min voltage 0.843v for rk3308bs vdd_core
42cb5315d plat: rk3308: only support standby wfi for cpu suspend
305418b09 lib: psci: Add weak psci_plat_cpu_suspend_prepare()
2f4c436b3 plat: rk3308: dram: ddr_get_rate() supports RK3308B-S
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ide88499d5e9840e1265fe1092f5d65d002ec51ea
build from:
rk_boot_all 59dfe7 platform: rk3308bs: initial flash and emmc iomux plus
update feature:
initial flash and emmc iomux plus
Change-Id: I9eb4f9a55db5124de20dfe89e15d0815cc685feb
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
from commit:
b6f5f6 platform: rk3308: update to v1.31.
build feature:
Support RK3308BS
Change-Id: I9d9962e6c079aee3d11234ca93aa5d7fb011bba8
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Build from optee commit in develop-next branch:
2d3f7fed rk3308bs: otp: compatible with revision
Update feature:
d15255c6 rk3308: otp: separate external interface
2b1ff59a pta: rk_os_service: add api for get oem otp size
e7c25607 rk3308: enlarge MAX_XLAT_TABLES to 8
Change-Id: I5270b8c50c08a52d624be4c4bf6fd14084f49e00
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
Build from optee commit in develop-next branch:
7b4275734 rockchip: sip: add share mem page type define
Update feature:
1. Update OP-TEE version to V3.13.0
2. Add build user info in boot up log
Change-Id: I558cc4d642764b567e156b47ddefc614e95f54ed
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
from commit:
I6560a6 platform: rk3308: update to v1.31
build feature:
src: platform: set GPIO0B5 normal for 3308BS.
Signed-off-by: Chen Fen <chenfen@rock-chips.com>
Change-Id: I2f59935d2c73fdc3575b871d88f6e1418756d18e
from commit:
rk_boot_all 89aaf6 src: spinand: Support TX25G01
build feature:
support new spiflash
Change-Id: Ie1fa344955e061052fcac21303142f4314142a60
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
from commit:
c8dea85 platform: rk3308: update to v1.30
build feature:
src: spinand: Fix GD5F1GQ5xExxG data strength setting
Change-Id: Ic5e2195891cd97d462716aa348a8a4bbdf2ad99e
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
build from:
rk_boot_all 5cb73e1 modify the step size and the count for scanning uboot
build feature:
modify the step size and the count for scanning uboot
EMMC: 512K x 8
SPI NAND Wo FTL: 128K X 16
SLC NAND Wo FTL: 128K x 16
SPI NOR: 64K X 32
Change-Id: I5edc87583ea6b56697c6e1ce2e44cc312ba0c79b
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Build from ATF commit:
16de7aecc plat: rk3568: enable sending bus idle request to BIU_VPU by hardware
update feature:
16de7aecc plat: rk3568: enable sending bus idle request to BIU_VPU by hardware
d89e43deb plat: rk3568: dfs: set dcf to sign-off rate when change ddr frequency
364c6a19b plat: px30: add scmi support
4ea66c757 plat: px30: port code from brach develop-rk3399 to develop-v2.3
84c6e64f0 rockchip: gicv2: add GICV2_G0_FOR_EL3 macro
968422912 rockchip: gicv2: add target_masks initialization
a2580fa7e rockchip: fix compile error for px30
205fc61a6 plat: rockchip: dram: update some common code about dram
d5719f63a plat: rk3568: the suspend clock switch to pvtm/32k_from_io
76228bab3 plat: rk3568: dmc: set ddr clock in phase when suspend
Change-Id: Icbcd89bb686c1cd7fdfc8eb0ad186925d5a1d8f7
Signed-off-by: Liang Chen <cl@rock-chips.com>
Build from optee commit in develop branch:
ef70f120a sta: rk_os_service: fix oem efuse size error
Update feature:
1. TA support get trng api
2. TA support read/write oem efuse api
3. add build user info in boot log
Signed-off-by: Elon Zhang <zhangzj@rock-chips.com>
Change-Id: Ic402e188ed2f3108b7010358642d6470fd00536c
build from next-dev:
9080840a12 drivers: ram: rv1126: Detect byte map of x16 DDR3/DDR4
update feature:
9080840a12 drivers: ram: rv1126: Detect byte map of x16 DDR3/DDR4
build command:
CONFIG_SPL_KERNEL_BOOT=y
for lpddr3 bin, CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE need set to 6.
for lpddr4 bin, CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE need set to 7.
default CONFIG_ROCKCHIP_DRAM_EXTENDED_TEMP_SUPPORT=n, if you need
extended temperature bin, you need enable "CONFIG_ROCKCHIP_DRAM\
_EXTENDED_TEMP_SUPPORT", then rebuild uboot.
./make.sh rv1126 && ./make.sh tpl.
Note:
the pre-build 528MHz binary disable ODT.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Change-Id: If0e8207e9e4b9e36850dbc7fb6aabebfc8a32bd8
build from:
rk_boot_all b9678f6f src: spinand: not cache recheck for XTX device
build feature:
support new flash devices
Change-Id: I101861937e2754e7a3b9d2584ac00b50054a1dff
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
build from:
rk_boot_all c9221db src: spinand: support GD5FxGQ5REYIG
new feature:
support new spiflash
Change-Id: I0b54b8d60548b249b214081322ad32ea0cce3754
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
build from:
rk_boot_all a00b18c src: platform: rv1126: Update to 1.20
build feature:
support new flash devices, W25N512GVEIG, GD5F1GQ4UExxH
Change-Id: I8e5fbea2a0a64cf7dd82b79ae9b15881ed3623e6
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Build from ATF commit:
76228bab3 plat: rk3568: dmc: set ddr clock in phase when suspend
update feature:
76228bab3 plat: rk3568: dmc: set ddr clock in phase when suspend
367a3ffb3 plat: rk3568: dfs: configure the response type in advance
81e0b993a rockchip: amp: support pass boot args0~3
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
Change-Id: I822a9c6140404107348cd368bddd3603a1a019e8
