from commit:
b6f5f6 platform: rk3308: update to v1.31.
build feature:
Support RK3308BS
Change-Id: I9d9962e6c079aee3d11234ca93aa5d7fb011bba8
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Build from optee commit in develop-next branch:
2d3f7fed rk3308bs: otp: compatible with revision
Update feature:
d15255c6 rk3308: otp: separate external interface
2b1ff59a pta: rk_os_service: add api for get oem otp size
e7c25607 rk3308: enlarge MAX_XLAT_TABLES to 8
Change-Id: I5270b8c50c08a52d624be4c4bf6fd14084f49e00
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
Build from optee commit in develop-next branch:
7b4275734 rockchip: sip: add share mem page type define
Update feature:
1. Update OP-TEE version to V3.13.0
2. Add build user info in boot up log
Change-Id: I558cc4d642764b567e156b47ddefc614e95f54ed
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
from commit:
I6560a6 platform: rk3308: update to v1.31
build feature:
src: platform: set GPIO0B5 normal for 3308BS.
Signed-off-by: Chen Fen <chenfen@rock-chips.com>
Change-Id: I2f59935d2c73fdc3575b871d88f6e1418756d18e
from commit:
rk_boot_all 89aaf6 src: spinand: Support TX25G01
build feature:
support new spiflash
Change-Id: Ie1fa344955e061052fcac21303142f4314142a60
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
from commit:
c8dea85 platform: rk3308: update to v1.30
build feature:
src: spinand: Fix GD5F1GQ5xExxG data strength setting
Change-Id: Ic5e2195891cd97d462716aa348a8a4bbdf2ad99e
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
build from:
rk_boot_all 5cb73e1 modify the step size and the count for scanning uboot
build feature:
modify the step size and the count for scanning uboot
EMMC: 512K x 8
SPI NAND Wo FTL: 128K X 16
SLC NAND Wo FTL: 128K x 16
SPI NOR: 64K X 32
Change-Id: I5edc87583ea6b56697c6e1ce2e44cc312ba0c79b
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Build from ATF commit:
16de7aecc plat: rk3568: enable sending bus idle request to BIU_VPU by hardware
update feature:
16de7aecc plat: rk3568: enable sending bus idle request to BIU_VPU by hardware
d89e43deb plat: rk3568: dfs: set dcf to sign-off rate when change ddr frequency
364c6a19b plat: px30: add scmi support
4ea66c757 plat: px30: port code from brach develop-rk3399 to develop-v2.3
84c6e64f0 rockchip: gicv2: add GICV2_G0_FOR_EL3 macro
968422912 rockchip: gicv2: add target_masks initialization
a2580fa7e rockchip: fix compile error for px30
205fc61a6 plat: rockchip: dram: update some common code about dram
d5719f63a plat: rk3568: the suspend clock switch to pvtm/32k_from_io
76228bab3 plat: rk3568: dmc: set ddr clock in phase when suspend
Change-Id: Icbcd89bb686c1cd7fdfc8eb0ad186925d5a1d8f7
Signed-off-by: Liang Chen <cl@rock-chips.com>
Build from optee commit in develop branch:
ef70f120a sta: rk_os_service: fix oem efuse size error
Update feature:
1. TA support get trng api
2. TA support read/write oem efuse api
3. add build user info in boot log
Signed-off-by: Elon Zhang <zhangzj@rock-chips.com>
Change-Id: Ic402e188ed2f3108b7010358642d6470fd00536c
build from next-dev:
9080840a12 drivers: ram: rv1126: Detect byte map of x16 DDR3/DDR4
update feature:
9080840a12 drivers: ram: rv1126: Detect byte map of x16 DDR3/DDR4
build command:
CONFIG_SPL_KERNEL_BOOT=y
for lpddr3 bin, CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE need set to 6.
for lpddr4 bin, CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE need set to 7.
default CONFIG_ROCKCHIP_DRAM_EXTENDED_TEMP_SUPPORT=n, if you need
extended temperature bin, you need enable "CONFIG_ROCKCHIP_DRAM\
_EXTENDED_TEMP_SUPPORT", then rebuild uboot.
./make.sh rv1126 && ./make.sh tpl.
Note:
the pre-build 528MHz binary disable ODT.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Change-Id: If0e8207e9e4b9e36850dbc7fb6aabebfc8a32bd8
build from:
rk_boot_all b9678f6f src: spinand: not cache recheck for XTX device
build feature:
support new flash devices
Change-Id: I101861937e2754e7a3b9d2584ac00b50054a1dff
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
build from:
rk_boot_all c9221db src: spinand: support GD5FxGQ5REYIG
new feature:
support new spiflash
Change-Id: I0b54b8d60548b249b214081322ad32ea0cce3754
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
build from:
rk_boot_all a00b18c src: platform: rv1126: Update to 1.20
build feature:
support new flash devices, W25N512GVEIG, GD5F1GQ4UExxH
Change-Id: I8e5fbea2a0a64cf7dd82b79ae9b15881ed3623e6
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Build from ATF commit:
76228bab3 plat: rk3568: dmc: set ddr clock in phase when suspend
update feature:
76228bab3 plat: rk3568: dmc: set ddr clock in phase when suspend
367a3ffb3 plat: rk3568: dfs: configure the response type in advance
81e0b993a rockchip: amp: support pass boot args0~3
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
Change-Id: I822a9c6140404107348cd368bddd3603a1a019e8
Build from optee commit in develop-next branch:
7b4275734 rockchip: sip: add share mem page type define
Update feature:
1. Update OP-TEE version to V3.13.0
2. Add build user info in boot up log
Signed-off-by: Elon Zhang <zhangzj@rock-chips.com>
Change-Id: Id876c9a6d8678834289e5ddc8a83c7df6962d7d7
Build from optee commit in develop-next branch:
7b4275734 rockchip: sip: add share mem page type define
Update feature:
1. Update OP-TEE version to V3.13.0
2. Add build user info in boot up log
Change-Id: Iefea11ab3df131499d44d291eb6b9099f097381b
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
Build from optee commit in develop-next branch:
7b4275734 rockchip: sip: add share mem page type define
Update feature:
1. Update OP-TEE version to V3.13.0
2. Add build user info in boot up log
Change-Id: I789f5b78f67cc96103aea0054c989d6c4f02801a
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
Build from optee commit in develop-next branch:
7b4275734 rockchip: sip: add share mem page type define
Update feature:
1. Update OP-TEE version to V3.13.0
2. Add build user info in boot up log
Change-Id: I7d8f0e930dad02f4af6aa07541983971c30051ee
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
Build from optee commit in develop-next branch:
7b4275734 rockchip: sip: add share mem page type define
Update feature:
1. Update OP-TEE version to V3.13.0
2. Add build user info in boot up log
Change-Id: I41948d0538306cdfd1165344f5a747474a2397bc
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
Build from optee commit in develop-next branch:
7b4275734 rockchip: sip: add share mem page type define
Update feature:
1. Update OP-TEE version to V3.13.0
2. Add build user info in boot up log
Change-Id: I5831f39fa93ede12197af65f680061a04b3a420f
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
Build from optee commit in develop-next branch:
7b427573 rockchip: sip: add share mem page type define
Update feature:
1. Update OP-TEE version to V3.13.0
2. Add build user info in boot up log
Change-Id: Icac12851bb18acd672e865c0d6a9e6a3c5cd2335
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
Build from ATF commit:
367a3ffb3 plat: rk3568: dfs: configure the response type in advance
update feature:
367a3ffb3 plat: rk3568: dfs: configure the response type in advance
Signed-off-by: shengfei Xu <xsf@rock-chips.com>
Change-Id: If057b6d21da837f67c0539009d8bc3efe6af11c1
build from:
92d64b31 src: spinor: Support XM25QU128C and XM25QU64C
feature:
Support spiflash
Change-Id: I7f18ba209678a59dcd09bb385b746583810831b8
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
from commit:
deeb564 platform: rk3308: Update to 1.28
build feature:
Support new spiflash devices
Change-Id: I1b785e4155b2baa87f93cd7be5dc43ea89e0a1f7
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
build from:
rk_boot_all b9678f6f src: spinand: not cache recheck for XTX device
build feature:
support new flash devices
Change-Id: I5e72a26108fa7004a61f8caf1acf8e162bb7ff80
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
build from:
rk_boot_all f817b47 src: slc_nand: support S34ML08G3
build feature:
support new flash devices
Change-Id: I8a8e9987e93ef91d24fc9902f6c196a3439d65e6
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
build from u-boot-ddr:
2a4cd42b0e dram_init: rv1126: update to v1.07
build command:
./make.sh rv1126
update feature:
4a3d962809 drivers: ram: rv1126: Support x16 bus width of
LPDDR4(X)
957ed7842b drivers: ram: rv1126: fix incorrect setting of
LPDDR4(X) tRFC
21372cf086 drivers: ram: rv1126: fix data types of wr_lvl result
for wr train
e8897b959f drivers: ram: rv1126: fix sdram_detect_row of LPDDR4/X
1ad4a306e5 drivers: ram: rv1126: Use ARRAY_SIZE to calculate
copy size to set ADDRMAP regs
a4bbeacc32 drivers: ram: rv1126: Add addrmap for ddrconf 23~28
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Change-Id: Ifda2f31c03d200d65bf08908af280d9fc089c47a
1. capture 5 raw data, buf reserve 6 frames size
2. fixes first frame anomaly
3. speed up i2c0 to 1MHz
4. reduce almost mcu-log before first frame
Test on battery-evb board under LP4 924MHz, the first frame was got at
92ms since RISC-V is running.
L 0, 1, 92, 0x8001000, 5533696, 0x1d8, 0x80, tick:93
Change-Id: Idaa0c141010093e022e9c9a20d5999e3f93195ec
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Build from rk_boot_all commit:
eb17f16181: rk3288: do not config nand1 iomux while using emmc
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: Ib1da65a92aa4b2150c960e3d2690fe7e3bb3a320
from commit: b651e6 src: spinand: Support new devices
Add spinand miniloader.bin to support more plane-select spinand.
Change-Id: Ic2c71ed98b4c0510c70e1e81b54fc3cf758f9687
Signed-off-by: zhijun.xie <xzj@rock-chips.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Build from ATF commit:
2257afb2f rk322xh: select dpll power down mode 1
update feature:
2257afb2f rk322xh: select dpll power down mode 1
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
Change-Id: Ifcf678163c00af49829e2da86cd01197b63edc85
