from commit:
rk3308_ddr_393MHz_v1.21.bin from 4929224 rk3308: DDR Version V1.21 in 393MHz
rk3308_ddr_451MHz_v1.21.bin from 82e6549 rk3308: DDR Version V1.21 in 451MHz
rk3308_ddr_589MHz_v1.21.bin from a321411 rk3308: DDR Version V1.21 in 589MHz
change:
enable ddr standby.
Change-Id: I7d1220e4b5823af1bc47ba9d31f31ddf9fe3dd5b
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
The v1.33 upgrade_tool supports gpt parameter flashing, usage:
$ sudo ./tools/upgrade_tool di -p ./tools/parameter_gpt.txt
Then it would write gpt table to emmc.
Change-Id: I6c4668d0405c880030cf4dfcc291caa62f23cf14
Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
PX3SE uses its own miniloader and the cpu debug port
is uart1. It can share the tee binary with rk3126,
so make a soft link to RKTRUST/RK3126TOS.ini for RKTRUST/PX3SETOS.ini.
px3se_ddr_300MHz_v2.08.bin makes the uart1 as debug port.
Change-Id: Ifdca0e7206d5d0c38504b4f6ac7ddd6674e04f0a
Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
built from ddr init project commit:
9e6431a Version: DDR Version 1.12 20180518
update feature:
1.fix ddr3 board power up fail because of lpddr4 commit
ddr3 power up fail at trust, and ddr3 board download flow can pass,
can enter system, reboot also pass, only power down and up, and hardware
reset can meet this problem.
the fail log as below:
NOTICE: BL31: Rockchip release version: v1.1
INFO: GICv3 with legacy support detected. ARM GICV3 driver initialized in EL3
INFO: Using opteed sec cpu_context!
INFO: boot cpu mask: 0
ASSERT: bakery_lock_release <170> : bakery_ticket_number(bakery->lock_data[me])
Change-Id: Ie010c8f6f9c415538703256ea11218851ddd8f18
Signed-off-by: CanYang He <hcy@rock-chips.com>
from commit:
fdfa64b rk3308: DDR Version V1.20
change:
adjust auto power down and auto self-refresh for lower
power in VCC_DDR and VDD_CORE.
Change-Id: I17fe5d5621d2db7ea64dfb5848706c49da1c3974
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
Build from ATF commit:
490c474 rk3308: set pwm pin pull none in gpio input mode
Update feature:
490c474 rk3308: set pwm pin pull none in gpio input mode
9b5adb5 rk3308: make suspend_mode_handler() suitable with kernel driver
a14f46a rk3308: save/restore cpu qos when system suspend
Change-Id: I1008a3926e252a7fa99b09ddc59794a116a9321c
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
There are wrong rk3308_ddr_589MHz_v1.19.bin file before.
from commit:
4a256e5ccf8d rk3308: DDR Version V1.19
Change-Id: I58d2da2192714d6d9cd93dee4293d062d4efabb4
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
built from ddr init project commit:
d6e7216 Version: DDR Version 1.11 20180509
update feature:
1.support 1 cs lpddr4
2.support lpddr4 only one channel
3.remove some lpddr4 log
Change-Id: Iac48d346fb1e86193a82369d024100bd02dba6a5
Signed-off-by: CanYang He <hcy@rock-chips.com>
build from optee commit:
ac72e46 rk322x: ddr: use vop raw status to wait line flag
update feature:
ac72e46 rk322x: ddr: use vop raw status to wait line flag
eaebb17 static ta: modify efuse write times
33168af efuse: modify udelay function
60b8da4 efuse: mask interrupt before efuse read & write
Change-Id: I7e0f2ba8a597af82be153dd8c29963397e80d559
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
from commit:
4a256e5ccf8d rk3308: DDR Version V1.19
change:
1.check boot memory device.If loader device turn to maskrom
device,download is normal.
2.adjust dq10,dq11,dq14,dq15 de-skew for better dqs1 eye training.
3.reduce pll vco
4.change qos prority,reduce cpu QOS prority,improve
some QOS prority.
5.Do not clear grf_os_reg0 when boot mode is BOOT_BROM_DOWNLOAD
Change-Id: Ie7cb666c634ce41ea558acbd71096f0811fe3444
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
build from optee:
c72e46 rk322x: ddr: use vop raw status to wait line flag
update features:
apply arm errata 825619 and FOOBAR
Change-Id: Icfb7fd16803dbabaae70b50be67636afa2bf02ab
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
build from optee commit:
e18ec91 workaround: rockchip: invalidate dcache before enable MMU
update feature:
e18ec91 workaround: rockchip: invalidate dcache before enable MMU
be33a34 rk3228: soc_monitor: make panic more powerful when soc check failed
e37b0f6 rk3228: soc_monitor: print some marks when panic
1ffdb85 rk322x: ddr: using aclk_vop to judge if vop is working
1c0d54b rpmb: add rpmb_test_key back
Change-Id: Ib3a5a72716c4fb371414f706fb5c45054c11e624
Signed-off-by: Zhang Zhijie <zhangzj@rock-chips.com>
from commit :
7b62dfc rk3308: DDR Version V1.11
add
1.set vpll0 in 1179.648MHz,vpll1 in 903.168MHz
2.ddr in vpll0,set 589MHz
3.adjusted deskew for aligning DQS and CK
4.delete clk 50% duty ratio setting in cru
5.set APLL,DPLL,VPLL0,VPLL1 without level shift
6.set pll vco high,but lower 3.2GHz,for minimum jitter.
7.add ddr scramble,include enable pmu pvtm.
8.updata ddr config grf_os_reg2,grf_os_reg3 to v1.08.
Change-Id: Ia459f53d7d9623f3af7e0de1edc2f99735d57c80
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
This is a temporary version, build from: c288f26
update features:
1. Support pwm regulator suspend voltage adjust;
2. Don't update voice VPLL.
Change-Id: I2620a245051a9cbd22ef81bdf9d19cf2ea5b4f28
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
built from ddr init project commit:
6ac5927 Version: DDR Version 1.10 20180410
update feature:
1.the init code change lpddr4 frequency from 50MHz to 400MHz,
and final to 800MHz, this version is a good support for
system suspend resume.
2.fix global reset fail when vdd_gpu power off
Change-Id: I490d26f243540d60bd6af2bfda3bddebf4218d1a
Signed-off-by: CanYang He <hcy@rock-chips.com>
from commit: ca6111834 rk3288 usbplug support upgrade by LBA.
Change-Id: I5b3bccfdcd58b92bfc9016deee6d4c6e23a8bde3
Signed-off-by: chenfen <chenfen@rock-chips.com>
