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imx8mq: evk: Migrate to DM PMIC framework

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Migrate the i.MX8MQ EVK board to the Driver Model (DM) PMIC framework.
This replaces legacy PMIC handling with DM_PMIC and enables proper
device-model support during SPL.

As part of this transition, enable CONFIG_SPL_DM and the required
DM subsystems such as I2C, PINCTRL, MMC, GPIO, and regulators so the
SPL boot flow continues to work correctly.

Board-specific SPL code is simplified accordingly by removing legacy
I2C, USDHC, and PMIC handling, relying instead on device tree
descriptions and DM drivers.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Peng Fan
2026-04-21 21:41:22 +08:00
committed by Fabio Estevam
parent 64e9956764
commit 186011ec8d
3 changed files with 129 additions and 165 deletions
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88
arch/arm/dts/imx8mq-evk-u-boot.dtsi
View File

@@ -2,19 +2,105 @@
#include "imx8mq-u-boot.dtsi"
&aips1 {
bootph-all;
};
&gpio2 {
bootph-pre-ram;
};
&pinctrl_i2c1 {
bootph-all;
};
&i2c1 {
bootph-all;
};
&soc {
bootph-all;
bootph-pre-ram;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@8} {
bootph-all;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@8/regulators} {
bootph-all;
};
&pinctrl_uart1 {
bootph-pre-ram;
};
&uart1 {
bootph-pre-ram;
};
&usdhc1 {
bootph-pre-ram;
mmc-hs400-1_8v;
/delete-property/ vqmmc-supply;
};
&pinctrl_usdhc1 {
bootph-pre-ram;
};
&pinctrl_usdhc1_100mhz {
bootph-pre-ram;
};
&pinctrl_usdhc1_200mhz {
bootph-pre-ram;
};
&usdhc2 {
bootph-pre-ram;
sd-uhs-sdr104;
sd-uhs-ddr50;
};
&uart1 {
&pinctrl_usdhc2 {
bootph-pre-ram;
};
&pinctrl_usdhc2_100mhz {
bootph-pre-ram;
};
&pinctrl_usdhc2_200mhz {
bootph-pre-ram;
};
&pinctrl_usdhc2_gpio {
bootph-pre-ram;
};
&pinctrl_reg_usdhc2 {
bootph-pre-ram;
};
&reg_usdhc2_vmmc {
bootph-pre-ram;
};
#ifdef CONFIG_FSL_CAAM
&crypto {
bootph-pre-ram;
};
&sec_jr0 {
bootph-pre-ram;
};
&sec_jr1 {
bootph-pre-ram;
};
&sec_jr2 {
bootph-pre-ram;
};
#endif

185
board/nxp/imx8mq_evk/spl.c
View File

@@ -9,23 +9,16 @@
#include <image.h>
#include <init.h>
#include <log.h>
#include <asm/io.h>
#include <errno.h>
#include <asm/io.h>
#include <asm/arch/ddr.h>
#include <asm/arch/imx8mq_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/clock.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/gpio.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/sections.h>
#include <fsl_esdhc_imx.h>
#include <fsl_sec.h>
#include <mmc.h>
#include <linux/delay.h>
#include <power/pmic.h>
#include <power/pfuze100_pmic.h>
#include <dm/uclass.h>
#include <dm/device.h>
#include <spl.h>
#include "../common/pfuze.h"
@@ -40,166 +33,52 @@ static void spl_dram_init(void)
ddr_init(&dram_timing_b0);
}
#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
static struct i2c_pads_info i2c_pad_info1 = {
.scl = {
.i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
.gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
.gp = IMX_GPIO_NR(5, 14),
},
.sda = {
.i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
.gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
.gp = IMX_GPIO_NR(5, 15),
},
};
#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret = 0;
switch (cfg->esdhc_base) {
case USDHC1_BASE_ADDR:
ret = 1;
break;
case USDHC2_BASE_ADDR:
ret = !gpio_get_value(USDHC2_CD_GPIO);
return ret;
}
return 1;
}
#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
PAD_CTL_FSEL2)
#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
static iomux_v3_cfg_t const usdhc1_pads[] = {
IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static iomux_v3_cfg_t const usdhc2_pads[] = {
IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
};
static struct fsl_esdhc_cfg usdhc_cfg[2] = {
{USDHC1_BASE_ADDR, 0, 8},
{USDHC2_BASE_ADDR, 0, 4},
};
int board_mmc_init(struct bd_info *bis)
{
int i, ret;
/*
* According to the board_mmc_init() the following map is done:
* (U-Boot device node) (Physical Port)
* mmc0 USDHC1
* mmc1 USDHC2
*/
for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
init_clk_usdhc(0);
usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
ARRAY_SIZE(usdhc1_pads));
gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
gpio_direction_output(USDHC1_PWR_GPIO, 0);
udelay(500);
gpio_direction_output(USDHC1_PWR_GPIO, 1);
break;
case 1:
init_clk_usdhc(1);
usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
ARRAY_SIZE(usdhc2_pads));
gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
gpio_direction_output(USDHC2_PWR_GPIO, 0);
udelay(500);
gpio_direction_output(USDHC2_PWR_GPIO, 1);
break;
default:
printf("Warning: you configured more USDHC controllers(%d) than supported by the board\n", i + 1);
return -EINVAL;
}
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
if (ret)
return ret;
}
return 0;
}
#if CONFIG_IS_ENABLED(POWER_LEGACY)
#define I2C_PMIC 0
int power_init_board(void)
{
struct pmic *p;
struct udevice *dev;
int reg;
int ret;
unsigned int reg;
ret = power_pfuze100_init(I2C_PMIC);
if (ret)
return -ENODEV;
ret = pmic_get("pmic@8", &dev);
if (ret == -ENODEV) {
puts("No pmic@8\n");
return 0;
}
if (ret < 0)
return ret;
p = pmic_get("PFUZE100");
ret = pmic_probe(p);
if (ret)
return -ENODEV;
pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
reg = pmic_reg_read(dev, PFUZE100_DEVICEID);
printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
pmic_reg_read(p, PFUZE100_SW3AVOL, &reg);
reg = pmic_reg_read(dev, PFUZE100_SW3AVOL);
if ((reg & 0x3f) != 0x18) {
reg &= ~0x3f;
reg |= 0x18;
pmic_reg_write(p, PFUZE100_SW3AVOL, reg);
pmic_reg_write(dev, PFUZE100_SW3AVOL, reg);
}
ret = pfuze_mode_init(p, APS_PFM);
ret = pfuze_mode_init(dev, APS_PFM);
if (ret < 0)
return ret;
/* set SW3A standby mode to off */
pmic_reg_read(p, PFUZE100_SW3AMODE, &reg);
reg = pmic_reg_read(dev, PFUZE100_SW3AMODE);
reg &= ~0xf;
reg |= APS_OFF;
pmic_reg_write(p, PFUZE100_SW3AMODE, reg);
pmic_reg_write(dev, PFUZE100_SW3AMODE, reg);
return 0;
}
#endif
void spl_board_init(void)
{
if (IS_ENABLED(CONFIG_FSL_CAAM)) {
if (sec_init())
printf("\nsec_init failed!\n");
struct udevice *dev;
int ret;
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
if (ret)
printf("Failed to initialize caam_jr: %d\n", ret);
}
puts("Normal Boot\n");
}
@@ -218,6 +97,9 @@ void board_init_f(ulong dummy)
{
int ret;
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
arch_cpu_init();
init_uart_clk(0);
@@ -226,25 +108,22 @@ void board_init_f(ulong dummy)
timer_init();
preloader_console_init();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
ret = spl_init();
ret = spl_early_init();
if (ret) {
debug("spl_init() failed: %d\n", ret);
debug("spl_early_init() failed: %d\n", ret);
hang();
}
preloader_console_init();
enable_tzc380();
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
power_init_board();
/* DDR initialization */
spl_dram_init();
init_clk_usdhc(0);
init_clk_usdhc(1);
board_init_r(NULL, 0);
}

21
configs/imx8mq_evk_defconfig
View File

@@ -4,12 +4,8 @@ CONFIG_TEXT_BASE=0x40200000
CONFIG_SYS_MALLOC_LEN=0x600000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x200000
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mq-evk"
CONFIG_TARGET_IMX8MQ_EVK=y
@@ -18,7 +14,7 @@ CONFIG_SYS_MONITOR_LEN=524288
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK=0x187ff0
CONFIG_SPL_STACK=0x920000
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x180000
@@ -73,6 +69,7 @@ CONFIG_CMD_EFIDEBUG=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_REDUNDANT=y
@@ -80,31 +77,33 @@ CONFIG_ENV_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_MMC_DEVICE_INDEX=1
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="FEC"
CONFIG_SPL_DM=y
CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
CONFIG_DFU_MMC=y
CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_GIGE=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY=y
CONFIG_PHY_IMX8MQ_USB=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
CONFIG_SPL_POWER_LEGACY=y
CONFIG_POWER_DOMAIN=y
CONFIG_IMX8M_POWER_DOMAIN=y
CONFIG_POWER_PFUZE100=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_PFUZE100=n
CONFIG_SPL_DM_PMIC_PFUZE100=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SPL_POWER_I2C=y
CONFIG_SPL_DM_REGULATOR_GPIO=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_TEE=y